From 0ec7e72b01dca8070c1a8ae9a0b0347d2281eadb Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Fri, 21 Oct 2016 22:31:27 +0200
Subject: [PATCH 001/307] improved USB serial Rx and implemented buffered Tx

---
 .../maple/libmaple/usb/stm32f1/usb_cdcacm.c   | 227 +++++++++++-------
 STM32F1/cores/maple/usb_serial.cpp            |  45 +---
 STM32F1/cores/maple/usb_serial.h              |   2 +-
 .../system/libmaple/usb/stm32f1/usb_reg_map.h |   4 +-
 4 files changed, 153 insertions(+), 125 deletions(-)

diff --git a/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c b/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c
index 448c05dfc..7a5a772af 100644
--- a/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c
+++ b/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c
@@ -261,18 +261,28 @@ static ONE_DESCRIPTOR String_Descriptor[N_STRING_DESCRIPTORS] = {
 
 /* I/O state */
 
-#define CDC_SERIAL_BUFFER_SIZE	512
+#define CDC_SERIAL_RX_BUFFER_SIZE	256 // must be power of 2
+#define CDC_SERIAL_RX_BUFFER_SIZE_MASK (CDC_SERIAL_RX_BUFFER_SIZE-1)
 
 /* Received data */
-static volatile uint8 vcomBufferRx[CDC_SERIAL_BUFFER_SIZE];
-/* Read index into vcomBufferRx */
-static volatile uint32 rx_offset = 0;
-/* Number of bytes left to transmit */
-static volatile uint32 n_unsent_bytes = 0;
-/* Are we currently sending an IN packet? */
-static volatile uint8 transmitting = 0;
-/* Number of unread bytes */
-static volatile uint32 n_unread_bytes = 0;
+static volatile uint8 vcomBufferRx[CDC_SERIAL_RX_BUFFER_SIZE];
+/* Write index to vcomBufferRx */
+static volatile uint32 rx_head;
+/* Read index from vcomBufferRx */
+static volatile uint32 rx_tail;
+
+#define CDC_SERIAL_TX_BUFFER_SIZE	256 // must be power of 2
+#define CDC_SERIAL_TX_BUFFER_SIZE_MASK (CDC_SERIAL_TX_BUFFER_SIZE-1)
+// Tx data
+static volatile uint8 vcomBufferTx[CDC_SERIAL_TX_BUFFER_SIZE];
+// Write index to vcomBufferTx
+static volatile uint32 tx_head;
+// Read index from vcomBufferTx
+static volatile uint32 tx_tail;
+// Are we currently sending an IN packet?
+static volatile int8 transmitting;
+
+
 
 /* Other state (line coding, DTR/RTS) */
 
@@ -393,30 +403,34 @@ void usb_cdcacm_putc(char ch) {
         ;
 }
 
-/* This function is blocking.
+/* This function is non-blocking.
  *
- * It copies data from a usercode buffer into the USB peripheral TX
+ * It copies data from a user buffer into the USB peripheral TX
  * buffer, and returns the number of bytes copied. */
-uint32 usb_cdcacm_tx(const uint8* buf, uint32 len) {
-    /* Last transmission hasn't finished, so abort. */
-    while ( usb_cdcacm_is_transmitting()>0 ) ; // wait for end of transmission
+uint32 usb_cdcacm_tx(const uint8* buf, uint32 len)
+{
+	if (len==0) return 0; // no data to send
 
-    /* We can only put USB_CDCACM_TX_EPSIZE bytes in the buffer. */
-    if (len > USB_CDCACM_TX_EPSIZE) {
-        len = USB_CDCACM_TX_EPSIZE;
-    }
+	uint32 head = tx_head; // load volatile variable
+	uint32 tx_unsent = (head - tx_tail) & CDC_SERIAL_TX_BUFFER_SIZE_MASK;
 
-    /* Queue bytes for sending. */
-    if (len) {
-        usb_copy_to_pma(buf, len, USB_CDCACM_TX_ADDR);
+    // We can only put bytes in the buffer if there is place
+    if (len > (CDC_SERIAL_TX_BUFFER_SIZE-tx_unsent-1) ) {
+        len = (CDC_SERIAL_TX_BUFFER_SIZE-tx_unsent-1);
     }
-    // We still need to wait for the interrupt, even if we're sending
-    // zero bytes. (Sending zero-size packets is useful for flushing
-    // host-side buffers.)
-    usb_set_ep_tx_count(USB_CDCACM_TX_ENDP, len);
-    n_unsent_bytes = len;
-    transmitting = 1;
-    usb_set_ep_tx_stat(USB_CDCACM_TX_ENDP, USB_EP_STAT_TX_VALID);
+	if (len==0) return 0; // buffer full
+
+	uint16 i;
+	// copy data from user buffer to USB Tx buffer
+	for (i=0; i<len; i++) {
+		vcomBufferTx[head] = buf[i];
+		head = (head+1) & CDC_SERIAL_TX_BUFFER_SIZE_MASK;
+	}
+	tx_head = head; // store volatile variable
+
+	if (transmitting<0) {
+		vcomDataTxCb(); // initiate data transmission
+	}
 
     return len;
 }
@@ -424,69 +438,73 @@ uint32 usb_cdcacm_tx(const uint8* buf, uint32 len) {
 
 
 uint32 usb_cdcacm_data_available(void) {
-    return n_unread_bytes;
+    return (rx_head - rx_tail) & CDC_SERIAL_RX_BUFFER_SIZE_MASK;
 }
 
 uint8 usb_cdcacm_is_transmitting(void) {
-    return transmitting;
+    return ( transmitting>0 ? transmitting : 0);
 }
 
 uint16 usb_cdcacm_get_pending(void) {
-    return n_unsent_bytes;
+    return (tx_head - tx_tail) & CDC_SERIAL_TX_BUFFER_SIZE_MASK;
 }
 
-/* Nonblocking byte receive.
+/* Non-blocking byte receive.
  *
  * Copies up to len bytes from our private data buffer (*NOT* the PMA)
  * into buf and deq's the FIFO. */
-uint32 usb_cdcacm_rx(uint8* buf, uint32 len) {
+uint32 usb_cdcacm_rx(uint8* buf, uint32 len)
+{
     /* Copy bytes to buffer. */
     uint32 n_copied = usb_cdcacm_peek(buf, len);
 
     /* Mark bytes as read. */
-    n_unread_bytes -= n_copied;
-    rx_offset = (rx_offset + n_copied) % CDC_SERIAL_BUFFER_SIZE;
+	uint16 tail = rx_tail; // load volatile variable
+	tail = (tail + n_copied) & CDC_SERIAL_RX_BUFFER_SIZE_MASK;
+	rx_tail = tail; // store volatile variable
 
-    /* If all bytes have been read, re-enable the RX endpoint, which
-     * was set to NAK when the current batch of bytes was received. */
-    if (n_unread_bytes == 0) {
-        usb_set_ep_rx_count(USB_CDCACM_RX_ENDP, USB_CDCACM_RX_EPSIZE);
+	uint32 rx_unread = (rx_head - tail) & CDC_SERIAL_RX_BUFFER_SIZE_MASK;
+    // If buffer was emptied to a pre-set value, re-enable the RX endpoint
+    if ( rx_unread <= 64 ) { // experimental value, gives the best performance
         usb_set_ep_rx_stat(USB_CDCACM_RX_ENDP, USB_EP_STAT_RX_VALID);
-    }
-
+	}
     return n_copied;
 }
 
-/* Nonblocking byte lookahead.
+/* Non-blocking byte lookahead.
  *
  * Looks at unread bytes without marking them as read. */
-uint32 usb_cdcacm_peek(uint8* buf, uint32 len) {
+uint32 usb_cdcacm_peek(uint8* buf, uint32 len)
+{
     int i;
-    uint32 head = rx_offset;
+    uint32 tail = rx_tail;
+	uint32 rx_unread = (rx_head-tail) & CDC_SERIAL_RX_BUFFER_SIZE_MASK;
 
-    if (len > n_unread_bytes) {
-        len = n_unread_bytes;
+    if (len > rx_unread) {
+        len = rx_unread;
     }
 
     for (i = 0; i < len; i++) {
-        buf[i] = vcomBufferRx[head];
-        head = (head + 1) % CDC_SERIAL_BUFFER_SIZE;
+        buf[i] = vcomBufferRx[tail];
+        tail = (tail + 1) & CDC_SERIAL_RX_BUFFER_SIZE_MASK;
     }
 
     return len;
 }
 
-uint32 usb_cdcacm_peek_ex(uint8* buf, uint32 offset, uint32 len) {
+uint32 usb_cdcacm_peek_ex(uint8* buf, uint32 offset, uint32 len)
+{
     int i;
-    uint32 head = (rx_offset + offset) % CDC_SERIAL_BUFFER_SIZE;
+    uint32 tail = (rx_tail + offset) & CDC_SERIAL_RX_BUFFER_SIZE_MASK ;
+	uint32 rx_unread = (rx_head-tail) & CDC_SERIAL_RX_BUFFER_SIZE_MASK;
 
-    if (len + offset > n_unread_bytes) {
-        len = n_unread_bytes - offset;
+    if (len + offset > rx_unread) {
+        len = rx_unread - offset;
     }
 
     for (i = 0; i < len; i++) {
-        buf[i] = vcomBufferRx[head];
-        head = (head + 1) % CDC_SERIAL_BUFFER_SIZE;
+        buf[i] = vcomBufferRx[tail];
+        tail = (tail + 1) & CDC_SERIAL_RX_BUFFER_SIZE_MASK;
     }
 
     return len;
@@ -495,12 +513,12 @@ uint32 usb_cdcacm_peek_ex(uint8* buf, uint32 offset, uint32 len) {
 /* Roger Clark. Added. for Arduino 1.0 API support of Serial.peek() */
 int usb_cdcacm_peek_char() 
 {
-    if (n_unread_bytes == 0) 
+    if (usb_cdcacm_data_available() == 0) 
 	{
 		return -1;
     }
 
-    return vcomBufferRx[rx_offset];
+    return vcomBufferRx[rx_tail];
 }
 
 uint8 usb_cdcacm_get_dtr() {
@@ -534,41 +552,75 @@ int usb_cdcacm_get_n_data_bits(void) {
     return line_coding.bDataBits;
 }
 
-
 /*
  * Callbacks
  */
-
-static void vcomDataTxCb(void) {
-    n_unsent_bytes = 0;
-    transmitting = 0;
+static void vcomDataTxCb(void)
+{
+	uint32 tail = tx_tail; // load volatile variable
+	uint32 tx_unsent = (tx_head - tail) & CDC_SERIAL_TX_BUFFER_SIZE_MASK;
+	if (tx_unsent==0) {
+		if ( (--transmitting)==0) goto flush; // no more data to send
+		return; // it was already flushed, keep Tx endpoint disabled
+	}
+	transmitting = 1;
+    // We can only send up to USB_CDCACM_TX_EPSIZE bytes in the endpoint.
+    if (tx_unsent > USB_CDCACM_TX_EPSIZE) {
+        tx_unsent = USB_CDCACM_TX_EPSIZE;
+    }
+	// copy the bytes from USB Tx buffer to PMA buffer
+	uint32 *dst = usb_pma_ptr(USB_CDCACM_TX_ADDR);
+    uint16 tmp = 0;
+	uint16 val;
+	int i;
+	for (i = 0; i < tx_unsent; i++) {
+		val = vcomBufferTx[tail];
+		tail = (tail + 1) & CDC_SERIAL_TX_BUFFER_SIZE_MASK;
+		if (i&1) {
+			*dst++ = tmp | (val<<8);
+		} else {
+			tmp = val;
+		}
+	}
+    if ( tx_unsent&1 ) {
+        *dst = tmp;
+    }
+	tx_tail = tail; // store volatile variable
+flush:
+	// enable Tx endpoint
+    usb_set_ep_tx_count(USB_CDCACM_TX_ENDP, tx_unsent);
+    usb_set_ep_tx_stat(USB_CDCACM_TX_ENDP, USB_EP_STAT_TX_VALID);
 }
 
-static void vcomDataRxCb(void) {
-	uint32 ep_rx_size;
-	uint32 tail = (rx_offset + n_unread_bytes) % CDC_SERIAL_BUFFER_SIZE;
-	uint8 ep_rx_data[USB_CDCACM_RX_EPSIZE];
-	uint32 i;
-
-    usb_set_ep_rx_stat(USB_CDCACM_RX_ENDP, USB_EP_STAT_RX_NAK);
-    ep_rx_size = usb_get_ep_rx_count(USB_CDCACM_RX_ENDP);
-    /* This copy won't overwrite unread bytes, since we've set the RX
-     * endpoint to NAK, and will only set it to VALID when all bytes
-     * have been read. */
-    usb_copy_from_pma((uint8*)ep_rx_data, ep_rx_size,
-                      USB_CDCACM_RX_ADDR);
 
+static void vcomDataRxCb(void)
+{
+	uint32 head = rx_head; // load volatile variable
+
+	uint32 ep_rx_size = usb_get_ep_rx_count(USB_CDCACM_RX_ENDP);
+	// This copy won't overwrite unread bytes as long as there is 
+	// enough room in the USB Rx buffer for next packet
+	uint32 *src = usb_pma_ptr(USB_CDCACM_RX_ADDR);
+    uint16 tmp = 0;
+	uint8 val;
+	uint32 i;
 	for (i = 0; i < ep_rx_size; i++) {
-		vcomBufferRx[tail] = ep_rx_data[i];
-		tail = (tail + 1) % CDC_SERIAL_BUFFER_SIZE;
+		if (i&1) {
+			val = tmp>>8;
+		} else {
+			tmp = *src++;
+			val = tmp&0xFF;
+		}
+		vcomBufferRx[head] = val;
+		head = (head + 1) & CDC_SERIAL_RX_BUFFER_SIZE_MASK;
 	}
+	rx_head = head; // store volatile variable
 
-	n_unread_bytes += ep_rx_size;
-
-    if ( n_unread_bytes == 0 ) {
-        usb_set_ep_rx_count(USB_CDCACM_RX_ENDP, USB_CDCACM_RX_EPSIZE);
-        usb_set_ep_rx_stat(USB_CDCACM_RX_ENDP, USB_EP_STAT_RX_VALID);
-    }
+	uint32 rx_unread = (head - rx_tail) & CDC_SERIAL_RX_BUFFER_SIZE_MASK;
+	// only enable further Rx if there is enough room to receive one more packet
+	if ( rx_unread < (CDC_SERIAL_RX_BUFFER_SIZE-USB_CDCACM_RX_EPSIZE) ) {
+		usb_set_ep_rx_stat(USB_CDCACM_RX_ENDP, USB_EP_STAT_RX_VALID);
+	}
 
     if (rx_hook) {
         rx_hook(USB_CDCACM_HOOK_RX, 0);
@@ -646,10 +698,11 @@ static void usbReset(void) {
     SetDeviceAddress(0);
 
     /* Reset the RX/TX state */
-    n_unread_bytes = 0;
-    n_unsent_bytes = 0;
-    rx_offset = 0;
-    transmitting = 0;
+	rx_head = 0;
+	rx_tail = 0;
+	tx_head = 0;
+	tx_tail = 0;
+    transmitting = -1;
 }
 
 static RESULT usbDataSetup(uint8 request) {
diff --git a/STM32F1/cores/maple/usb_serial.cpp b/STM32F1/cores/maple/usb_serial.cpp
index ab8816bce..24b0014d1 100644
--- a/STM32F1/cores/maple/usb_serial.cpp
+++ b/STM32F1/cores/maple/usb_serial.cpp
@@ -100,44 +100,23 @@ size_t n = 0;
 
 size_t USBSerial::write(const char *str) {
 size_t n = 0;
-    this->write(str, strlen(str));
+    this->write((const uint8*)str, strlen(str));
 	return n;
 }
 
-size_t USBSerial::write(const void *buf, uint32 len) {
+size_t USBSerial::write(const uint8 *buf, uint32 len)
+{
 size_t n = 0;
     if (!this->isConnected() || !buf) {
         return 0;
     }
 
     uint32 txed = 0;
-    uint32 old_txed = 0;
-    uint32 start = millis();
-
-    uint32 sent = 0;
-
-    while (txed < len && (millis() - start < USB_TIMEOUT)) {
-        sent = usb_cdcacm_tx((const uint8*)buf + txed, len - txed);
-        txed += sent;
-        if (old_txed != txed) {
-            start = millis();
-        }
-        old_txed = txed;
+    while (txed < len) {
+        txed += usb_cdcacm_tx((const uint8*)buf + txed, len - txed);
     }
 
-
-#if 0
-// this code leads to a serious performance drop and appears to be
-// unnecessary - everything seems to work fine without, -jcw, 2015-11-05
-// see http://stm32duino.com/posting.php?mode=quote&f=3&p=7746
-	if (sent == USB_CDCACM_TX_EPSIZE) {
-	while (usb_cdcacm_is_transmitting() != 0) {
-	}
-	/* flush out to avoid having the pc wait for more data */
-	usb_cdcacm_tx(NULL, 0);
-	}
-#endif
-		return n;
+	return n;
 }
 
 int USBSerial::available(void) {
@@ -168,14 +147,10 @@ void USBSerial::flush(void)
     return;
 }
 
-uint32 USBSerial::read(void *buf, uint32 len) {
-    if (!buf) {
-        return 0;
-    }
-
+uint32 USBSerial::read(uint8 * buf, uint32 len) {
     uint32 rxed = 0;
     while (rxed < len) {
-        rxed += usb_cdcacm_rx((uint8*)buf + rxed, len - rxed);
+        rxed += usb_cdcacm_rx(buf + rxed, len - rxed);
     }
 
     return rxed;
@@ -183,13 +158,13 @@ uint32 USBSerial::read(void *buf, uint32 len) {
 
 /* Blocks forever until 1 byte is received */
 int USBSerial::read(void) {
-    uint8 b;
+    int8 b;
 	/*
 	    this->read(&b, 1);
     return b;
 	*/
 	
-	if (usb_cdcacm_rx(&b, 1)==0)
+	if (usb_cdcacm_rx((uint8*)&b, 1)==0)
 	{
 		return -1;
 	}
diff --git a/STM32F1/cores/maple/usb_serial.h b/STM32F1/cores/maple/usb_serial.h
index 740ab0fd9..e50a16c27 100644
--- a/STM32F1/cores/maple/usb_serial.h
+++ b/STM32F1/cores/maple/usb_serial.h
@@ -53,7 +53,7 @@ class USBSerial : public Stream {
 
     virtual int available(void);// Changed to virtual
 
-    uint32 read(void *buf, uint32 len);
+    uint32 read(uint8 * buf, uint32 len);
    // uint8  read(void);
 
 	// Roger Clark. added functions to support Arduino 1.0 API
diff --git a/STM32F1/system/libmaple/usb/stm32f1/usb_reg_map.h b/STM32F1/system/libmaple/usb/stm32f1/usb_reg_map.h
index 6683264f8..9e9214cf1 100644
--- a/STM32F1/system/libmaple/usb/stm32f1/usb_reg_map.h
+++ b/STM32F1/system/libmaple/usb/stm32f1/usb_reg_map.h
@@ -349,8 +349,8 @@ static inline void usb_clear_status_out(uint8 ep) {
 void usb_copy_to_pma(const uint8 *buf, uint16 len, uint16 pma_offset);
 void usb_copy_from_pma(uint8 *buf, uint16 len, uint16 pma_offset);
 
-static inline void* usb_pma_ptr(uint32 offset) {
-    return (void*)(USB_PMA_BASE + 2 * offset);
+static inline uint32 * usb_pma_ptr(uint32 offset) {
+    return (uint32*)(USB_PMA_BASE + 2 * offset);
 }
 
 /*

From 42cb8b5bc809df2aa4b9d82f535d7a71caae9282 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Fri, 21 Oct 2016 23:01:45 +0200
Subject: [PATCH 002/307] small change

- revert local variable to uint8 in Serial.read
---
 STM32F1/cores/maple/usb_serial.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/STM32F1/cores/maple/usb_serial.cpp b/STM32F1/cores/maple/usb_serial.cpp
index 24b0014d1..5eaf70efb 100644
--- a/STM32F1/cores/maple/usb_serial.cpp
+++ b/STM32F1/cores/maple/usb_serial.cpp
@@ -158,13 +158,13 @@ uint32 USBSerial::read(uint8 * buf, uint32 len) {
 
 /* Blocks forever until 1 byte is received */
 int USBSerial::read(void) {
-    int8 b;
+    uint8 b;
 	/*
 	    this->read(&b, 1);
     return b;
 	*/
 	
-	if (usb_cdcacm_rx((uint8*)&b, 1)==0)
+	if (usb_cdcacm_rx(&b, 1)==0)
 	{
 		return -1;
 	}

From 34b6bd927d9ce7f66f43fcfd99f9204fb7de6289 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sat, 29 Oct 2016 22:09:44 +1100
Subject: [PATCH 003/307] Fixed issue with ILI9341_due library (and Touch
 libary), incorrectly including pins_arduino.h

---
 STM32F1/libraries/ILI9341_due_STM/ILI9341_due.h                | 2 +-
 STM32F1/libraries/Touch-Screen-Library_STM/TouchScreen_STM.cpp | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/STM32F1/libraries/ILI9341_due_STM/ILI9341_due.h b/STM32F1/libraries/ILI9341_due_STM/ILI9341_due.h
index 7b7268466..f06dd7153 100644
--- a/STM32F1/libraries/ILI9341_due_STM/ILI9341_due.h
+++ b/STM32F1/libraries/ILI9341_due_STM/ILI9341_due.h
@@ -53,7 +53,7 @@ MIT license, all text above must be included in any redistribution
  #include <avr/pgmspace.h>
  #include <limits.h>
  #include <libmaple/dma.h>
- #include "pins_arduino.h"
+// #include "pins_arduino.h"
  #include "wiring_private.h"
  #include <SPI.h>
 #endif
diff --git a/STM32F1/libraries/Touch-Screen-Library_STM/TouchScreen_STM.cpp b/STM32F1/libraries/Touch-Screen-Library_STM/TouchScreen_STM.cpp
index 0cddc44c2..4eadfc18c 100644
--- a/STM32F1/libraries/Touch-Screen-Library_STM/TouchScreen_STM.cpp
+++ b/STM32F1/libraries/Touch-Screen-Library_STM/TouchScreen_STM.cpp
@@ -5,7 +5,7 @@
 
 // Ported to STM32 by Jaret Burkett https://github.com/jaretburkett
 
-#include "pins_arduino.h"
+//#include "pins_arduino.h"
 #include "wiring_private.h"
 #ifdef __AVR
   #include <avr/pgmspace.h>

From e2c957489af9aa0307f43ef19e33cd8d7bc18156 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sun, 30 Oct 2016 21:38:30 +1100
Subject: [PATCH 004/307] Added support for Hy-Tiny STM32F103T

---
 STM32F1/boards.txt                            |  62 +++++
 STM32F1/variants/hytiny_stm32f103t/board.cpp  | 122 ++++++++++
 .../variants/hytiny_stm32f103t/board/board.h  |  75 ++++++
 .../hytiny_stm32f103t/ld/bootloader_20.ld     |  30 +++
 .../variants/hytiny_stm32f103t/ld/common.inc  | 220 +++++++++++++++++
 .../hytiny_stm32f103t/ld/extra_libs.inc       |   7 +
 .../variants/hytiny_stm32f103t/ld/flash.ld    |  26 ++
 .../variants/hytiny_stm32f103t/ld/flash_c8.ld |  33 +++
 STM32F1/variants/hytiny_stm32f103t/ld/jtag.ld |  31 +++
 .../variants/hytiny_stm32f103t/ld/jtag_c8.ld  |  36 +++
 .../hytiny_stm32f103t/ld/mem-flash.inc        |   5 +
 .../hytiny_stm32f103t/ld/mem-jtag.inc         |   5 +
 .../variants/hytiny_stm32f103t/ld/mem-ram.inc |   5 +
 STM32F1/variants/hytiny_stm32f103t/ld/ram.ld  |  25 ++
 .../variants/hytiny_stm32f103t/ld/ram_c8.ld   |  31 +++
 .../hytiny_stm32f103t/ld/vector_symbols.inc   |  78 ++++++
 .../variants/hytiny_stm32f103t/pins_arduino.h |   6 +
 STM32F1/variants/hytiny_stm32f103t/variant.h  |  19 ++
 .../hytiny_stm32f103t/wirish/boards.cpp       | 229 ++++++++++++++++++
 .../hytiny_stm32f103t/wirish/boards_setup.cpp |  96 ++++++++
 .../variants/hytiny_stm32f103t/wirish/start.S |  57 +++++
 .../hytiny_stm32f103t/wirish/start_c.c        |  95 ++++++++
 .../hytiny_stm32f103t/wirish/syscalls.c       | 176 ++++++++++++++
 23 files changed, 1469 insertions(+)
 create mode 100644 STM32F1/variants/hytiny_stm32f103t/board.cpp
 create mode 100644 STM32F1/variants/hytiny_stm32f103t/board/board.h
 create mode 100644 STM32F1/variants/hytiny_stm32f103t/ld/bootloader_20.ld
 create mode 100644 STM32F1/variants/hytiny_stm32f103t/ld/common.inc
 create mode 100644 STM32F1/variants/hytiny_stm32f103t/ld/extra_libs.inc
 create mode 100644 STM32F1/variants/hytiny_stm32f103t/ld/flash.ld
 create mode 100644 STM32F1/variants/hytiny_stm32f103t/ld/flash_c8.ld
 create mode 100644 STM32F1/variants/hytiny_stm32f103t/ld/jtag.ld
 create mode 100644 STM32F1/variants/hytiny_stm32f103t/ld/jtag_c8.ld
 create mode 100644 STM32F1/variants/hytiny_stm32f103t/ld/mem-flash.inc
 create mode 100644 STM32F1/variants/hytiny_stm32f103t/ld/mem-jtag.inc
 create mode 100644 STM32F1/variants/hytiny_stm32f103t/ld/mem-ram.inc
 create mode 100644 STM32F1/variants/hytiny_stm32f103t/ld/ram.ld
 create mode 100644 STM32F1/variants/hytiny_stm32f103t/ld/ram_c8.ld
 create mode 100644 STM32F1/variants/hytiny_stm32f103t/ld/vector_symbols.inc
 create mode 100644 STM32F1/variants/hytiny_stm32f103t/pins_arduino.h
 create mode 100644 STM32F1/variants/hytiny_stm32f103t/variant.h
 create mode 100644 STM32F1/variants/hytiny_stm32f103t/wirish/boards.cpp
 create mode 100644 STM32F1/variants/hytiny_stm32f103t/wirish/boards_setup.cpp
 create mode 100644 STM32F1/variants/hytiny_stm32f103t/wirish/start.S
 create mode 100644 STM32F1/variants/hytiny_stm32f103t/wirish/start_c.c
 create mode 100644 STM32F1/variants/hytiny_stm32f103t/wirish/syscalls.c

diff --git a/STM32F1/boards.txt b/STM32F1/boards.txt
index cb660a9e3..b56272f7d 100644
--- a/STM32F1/boards.txt
+++ b/STM32F1/boards.txt
@@ -462,6 +462,68 @@ genericSTM32F103Z.menu.upload_method.BMPMethod.upload.protocol=gdb_bmp
 genericSTM32F103Z.menu.upload_method.BMPMethod.upload.tool=bmp_upload
 genericSTM32F103Z.menu.upload_method.BMPMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG
 
+###################### HYTiny STM32F103T ########################################
+
+hytiny-stm32f103t.name=HYTiny STM32F103T series
+hytiny-stm32f103t.vid.0=0x1EAF
+hytiny-stm32f103t.pid.0=0x0004
+hytiny-stm32f103t.build.variant=hytiny_stm32f103t
+hytiny-stm32f103t.build.vect=VECT_TAB_ADDR=0x8000000
+hytiny-stm32f103t.build.core=maple
+hytiny-stm32f103t.build.board=HYTINY_STM32F103T
+hytiny-stm32f103t.upload.use_1200bps_touch=false
+hytiny-stm32f103t.upload.file_type=bin
+hytiny-stm32f103t.upload.auto_reset=true
+
+## STM32F103C8 -------------------------
+hytiny-stm32f103t.menu.device_variant.STM32F103C8=STM32F103C8 (20k RAM. 64k Flash)
+hytiny-stm32f103t.menu.device_variant.STM32F103C8.build.cpu_flags=-DMCU_STM32F103C8
+hytiny-stm32f103t.menu.device_variant.STM32F103C8.build.ldscript=ld/jtag_c8.ld
+hytiny-stm32f103t.menu.device_variant.STM32F103C8.upload.maximum_size=65536
+hytiny-stm32f103t.menu.device_variant.STM32F103C8.upload.ram.maximum_size=20480
+hytiny-stm32f103t.menu.device_variant.STM32F103C8.upload.flash.maximum_size=65536
+
+## STM32F103CB -------------------------
+hytiny-stm32f103t.menu.device_variant.STM32F103CB=STM32F103CB (20k RAM. 128k Flash)
+hytiny-stm32f103t.menu.device_variant.STM32F103CB.build.cpu_flags=-DMCU_STM32F103CB
+hytiny-stm32f103t.menu.device_variant.STM32F103CB.build.ldscript=ld/jtag.ld
+hytiny-stm32f103t.menu.device_variant.STM32F103CB.upload.maximum_size=131072
+hytiny-stm32f103t.menu.device_variant.STM32F103CB.upload.ram.maximum_size=20480
+hytiny-stm32f103t.menu.device_variant.STM32F103CB.upload.flash.maximum_size=131072
+
+#---------------------------- UPLOAD METHODS ---------------------------
+
+hytiny-stm32f103t.menu.upload_method.DFUUploadMethod=STM32duino bootloader
+hytiny-stm32f103t.menu.upload_method.DFUUploadMethod.upload.protocol=maple_dfu
+hytiny-stm32f103t.menu.upload_method.DFUUploadMethod.upload.tool=maple_upload
+hytiny-stm32f103t.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB 
+hytiny-stm32f103t.menu.upload_method.DFUUploadMethod.build.vect=VECT_TAB_ADDR=0x8002000
+hytiny-stm32f103t.menu.upload_method.DFUUploadMethod.build.ldscript=ld/bootloader_20.ld
+hytiny-stm32f103t.menu.upload_method.DFUUploadMethod.upload.usbID=1EAF:0003
+hytiny-stm32f103t.menu.upload_method.DFUUploadMethod.upload.altID=2
+
+hytiny-stm32f103t.menu.upload_method.serialMethod=Serial
+hytiny-stm32f103t.menu.upload_method.serialMethod.upload.protocol=maple_serial
+hytiny-stm32f103t.menu.upload_method.serialMethod.upload.tool=serial_upload
+
+
+hytiny-stm32f103t.menu.upload_method.STLinkMethod=STLink
+hytiny-stm32f103t.menu.upload_method.STLinkMethod.upload.protocol=STLink
+hytiny-stm32f103t.menu.upload_method.STLinkMethod.upload.tool=stlink_upload
+hytiny-stm32f103t.menu.upload_method.STLinkMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG=1 -DSERIAL_USB -DGENERIC_BOOTLOADER
+
+hytiny-stm32f103t.menu.upload_method.BMPMethod=BMP (Black Magic Probe)
+hytiny-stm32f103t.menu.upload_method.BMPMethod.upload.protocol=gdb_bmp
+hytiny-stm32f103t.menu.upload_method.BMPMethod.upload.tool=bmp_upload
+hytiny-stm32f103t.menu.upload_method.BMPMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG
+
+
+hytiny-stm32f103t.menu.upload_method.jlinkMethod=JLink
+hytiny-stm32f103t.menu.upload_method.jlinkMethod.upload.protocol=jlink
+hytiny-stm32f103t.menu.upload_method.jlinkMethod.upload.tool=jlink_upload
+hytiny-stm32f103t.menu.upload_method.jlinkMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG=1 -DSERIAL_USB -DGENERIC_BOOTLOADER 
+
+
 ###################### Generic GD32F103C  ########################################
 
 genericGD32F103C.name=Generic GD32F103C series
diff --git a/STM32F1/variants/hytiny_stm32f103t/board.cpp b/STM32F1/variants/hytiny_stm32f103t/board.cpp
new file mode 100644
index 000000000..f1fb44f07
--- /dev/null
+++ b/STM32F1/variants/hytiny_stm32f103t/board.cpp
@@ -0,0 +1,122 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * &file   wirish/boards/maple_mini/board.cpp
+ * &author Marti Bolivar <mbolivar&leaflabs.com>
+ * &brief  Maple Mini board file.
+ */
+
+#include <board/board.h>
+
+#include <libmaple/gpio.h>
+#include <libmaple/timer.h>
+
+/* Roger Clark. Added next to includes for changes to Serial */
+#include <libmaple/usart.h>
+#include <HardwareSerial.h>
+
+#include <wirish_debug.h>
+#include <wirish_types.h>
+
+/* Since we want the Serial Wire/JTAG pins as GPIOs, disable both SW
+ * and JTAG debug support, unless configured otherwise. */
+void boardInit(void) {
+#ifndef CONFIG_MAPLE_MINI_NO_DISABLE_DEBUG
+    disableDebugPorts();
+#endif
+}
+
+// Note. See the enum of pin names in board.h
+
+extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
+
+
+    {&gpioa, &timer2, &adc1,  0, 1,    0}, /* PA0 */
+    {&gpioa, &timer2, &adc1,  1, 2,    1}, /* PA1 */
+    {&gpioa, &timer2, &adc1,  2, 3,    2}, /* PA2 */	
+    {&gpioa, &timer2, &adc1,  3, 4,    3}, /* PA3 */
+    {&gpioa,   NULL, &adc1,  4, 0,    4}, /* PA4 */
+    {&gpioa,   NULL, &adc1,  5, 0,    5}, /* PA5 */
+    {&gpioa, &timer3, &adc1,  6, 1,    6}, /* PA6 */
+    {&gpioa, &timer3, &adc1,  7, 2,    7}, /* PA7 */
+    {&gpioa, &timer1, NULL,  8, 1, ADCx}, /* PA8 */	
+    {&gpioa, &timer1, NULL,  9, 2, ADCx}, /* PA9 */	
+    {&gpioa, &timer1, NULL, 10, 3, ADCx}, /* PA10 */
+    {&gpioa, &timer1, NULL, 11, 4, ADCx}, /* PA11 */
+    {&gpioa,   NULL, NULL, 12, 0, ADCx}, /* PA12 */	
+    {&gpioa,   NULL, NULL, 13, 0, ADCx}, /* PA13 */	
+    {&gpioa,   NULL, NULL, 14, 0, ADCx}, /* PA14 */
+    {&gpioa,   NULL, NULL, 15, 0, ADCx}, /* PA15 */
+	
+    {&gpiob, &timer3, &adc1,  0, 3,    8}, /* PB0 */	
+    {&gpiob, &timer3, &adc1,  1, 4,    9}, /* PB1 */
+    {&gpiob,   NULL, NULL,  2, 0, ADCx}, /* PB2 */
+    {&gpiob,   NULL, NULL,  3, 0, ADCx}, /* PB3 */
+    {&gpiob,   NULL, NULL,  4, 0, ADCx}, /* PB4 */
+    {&gpiob,   NULL, NULL,  5, 0, ADCx}, /* PB5 */
+    {&gpiob, &timer4, NULL,  6, 1, ADCx}, /* PB6 */
+    {&gpiob, &timer4, NULL,  7, 2, ADCx}, /* PB7 */	
+
+};
+
+extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
+    PB0, PA7, PA6, PA3, PA2, PA1, PA0, PB7, PB6, PA10, PA9, PA8
+};
+
+extern const uint8 boardADCPins[BOARD_NR_ADC_PINS] __FLASH__ = {
+    PB0, PA7, PA6 , PA5 , PA4 , PA3 , PA2 , PA1 , PA0 
+};
+
+// Note. These defines are not really used by generic boards. They are for  Maple Serial USB
+#define USB_DP PA12
+#define USB_DM PA11
+
+// NOte. These definitions are not really used for generic boards, they only relate to boards modified to behave like Maple boards
+extern const uint8 boardUsedPins[BOARD_NR_USED_PINS] __FLASH__ = {
+     USB_DP, USB_DM
+};
+
+
+/* 
+ * Roger Clark
+ * 
+ * 2015/05/28
+ *
+ * Moved definitions for Hardware Serial devices from HardwareSerial.cpp so that each board can define which Arduino "Serial" instance
+ * Maps to which hardware serial port on the microprocessor
+ */
+						
+#ifdef SERIAL_USB
+	DEFINE_HWSERIAL(Serial1, 1);
+
+	DEFINE_HWSERIAL(Serial2, 2);
+
+#else
+	DEFINE_HWSERIAL(Serial, 1);
+
+	DEFINE_HWSERIAL(Serial1, 2);
+#endif
diff --git a/STM32F1/variants/hytiny_stm32f103t/board/board.h b/STM32F1/variants/hytiny_stm32f103t/board/board.h
new file mode 100644
index 000000000..194b2e581
--- /dev/null
+++ b/STM32F1/variants/hytiny_stm32f103t/board/board.h
@@ -0,0 +1,75 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file   wirish/boards/maple_mini/include/board/board.h
+ * @author Marti Bolivar <mbolivar@leaflabs.com>
+ * @brief  Maple Mini board header.
+ *
+ * See wirish/boards/maple/include/board/board.h for more information
+ * on these definitions.
+ */
+
+#ifndef _BOARD_GENERIC_STM32F103C_H_
+#define _BOARD_GENERIC_STM32F103C_H_
+
+#define CYCLES_PER_MICROSECOND    72
+#define SYSTICK_RELOAD_VAL     (F_CPU/1000) - 1 /* takes a cycle to reload */
+
+#define BOARD_NR_USARTS           2
+#define BOARD_USART1_TX_PIN       PA9
+#define BOARD_USART1_RX_PIN       PA10
+#define BOARD_USART2_TX_PIN       PA2
+#define BOARD_USART2_RX_PIN       PA3
+
+
+#define BOARD_NR_SPI              1
+#define BOARD_SPI1_NSS_PIN        PA4
+#define BOARD_SPI1_MOSI_PIN       PA7
+#define BOARD_SPI1_MISO_PIN       PA6
+#define BOARD_SPI1_SCK_PIN        PA5
+
+#define BOARD_NR_GPIO_PINS        35
+#define BOARD_NR_PWM_PINS         12
+#define BOARD_NR_ADC_PINS          9
+#define BOARD_NR_USED_PINS         4
+
+#define BOARD_JTMS_SWDIO_PIN      22
+#define BOARD_JTCK_SWCLK_PIN      21
+#define BOARD_JTDI_PIN            20
+#define BOARD_JTDO_PIN            19
+#define BOARD_NJTRST_PIN          18
+
+#define BOARD_USB_DISC_DEV        GPIOA
+#define BOARD_USB_DISC_BIT        0
+
+// Note this needs to match with the PIN_MAP array in board.cpp
+enum {
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13,PA14,PA15,
+	PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7
+};
+
+#endif
diff --git a/STM32F1/variants/hytiny_stm32f103t/ld/bootloader_20.ld b/STM32F1/variants/hytiny_stm32f103t/ld/bootloader_20.ld
new file mode 100644
index 000000000..4de3a0839
--- /dev/null
+++ b/STM32F1/variants/hytiny_stm32f103t/ld/bootloader_20.ld
@@ -0,0 +1,30 @@
+/*
+ * libmaple linker script for "Flash" builds.
+ *
+ * A Flash build puts .text (and .rodata) in Flash, and
+ * .data/.bss/heap (of course) in SRAM, but offsets the sections by
+ * enough space to store the Maple bootloader, which lives in low
+ * Flash and uses low memory.
+ */
+
+/*
+ * This pulls in the appropriate MEMORY declaration from the right
+ * subdirectory of stm32/mem/ (the environment must call ld with the
+ * right include directory flags to make this happen). Boards can also
+ * use this file to use any of libmaple's memory-related hooks (like
+ * where the heap should live).
+ */
+MEMORY
+{
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
+  rom (rx)  : ORIGIN = 0x08002000, LENGTH = 120K
+}
+
+/* Provide memory region aliases for common.inc */
+REGION_ALIAS("REGION_TEXT", rom);
+REGION_ALIAS("REGION_DATA", ram);
+REGION_ALIAS("REGION_BSS", ram);
+REGION_ALIAS("REGION_RODATA", rom);
+
+/* Let common.inc handle the real work. */
+INCLUDE common.inc
diff --git a/STM32F1/variants/hytiny_stm32f103t/ld/common.inc b/STM32F1/variants/hytiny_stm32f103t/ld/common.inc
new file mode 100644
index 000000000..e086a58bc
--- /dev/null
+++ b/STM32F1/variants/hytiny_stm32f103t/ld/common.inc
@@ -0,0 +1,220 @@
+/*
+ * Linker script for libmaple.
+ *
+ * Original author "lanchon" from ST forums, with modifications by LeafLabs.
+ */
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+
+/*
+ * Configure other libraries we want in the link.
+ *
+ * libgcc, libc, and libm are common across supported toolchains.
+ * However, some toolchains require additional archives which aren't
+ * present everywhere (e.g. ARM's gcc-arm-embedded releases).
+ *
+ * To hack around this, we let the build system specify additional
+ * archives by putting the right extra_libs.inc (in a directory under
+ * toolchains/) in our search path.
+ */
+GROUP(libgcc.a libc.a libm.a)
+INCLUDE extra_libs.inc
+
+/*
+ * These force the linker to search for vector table symbols.
+ *
+ * These symbols vary by STM32 family (and also within families).
+ * It's up to the build system to configure the link's search path
+ * properly for the target MCU.
+ */
+INCLUDE vector_symbols.inc
+
+/* STM32 vector table. */
+EXTERN(__stm32_vector_table)
+
+/* C runtime initialization function. */
+EXTERN(start_c)
+
+/* main entry point */
+EXTERN(main)
+
+/* Initial stack pointer value. */
+EXTERN(__msp_init)
+PROVIDE(__msp_init = ORIGIN(ram) + LENGTH(ram));
+
+/* Reset vector and chip reset entry point */
+EXTERN(__start__)
+ENTRY(__start__)
+PROVIDE(__exc_reset = __start__);
+
+/* Heap boundaries, for libmaple */
+EXTERN(_lm_heap_start);
+EXTERN(_lm_heap_end);
+
+SECTIONS
+{
+    .text :
+      {
+        __text_start__ = .;
+        /*
+         * STM32 vector table.  Leave this here.  Yes, really.
+         */
+        *(.stm32.interrupt_vector)
+
+        /*
+         * Program code and vague linking
+         */
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.plt)
+        *(.gnu.warning)
+        *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+        *(.gcc_except_table)
+        *(.eh_frame_hdr)
+        *(.eh_frame)
+
+        . = ALIGN(4);
+        KEEP(*(.init))
+
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+      } > REGION_TEXT
+
+    /*
+     * End of text
+     */
+    .text.align :
+      {
+        . = ALIGN(8);
+        __text_end__ = .;
+      } > REGION_TEXT
+
+    /*
+     * .ARM.exidx exception unwinding; mandated by ARM's C++ ABI
+     */
+    __exidx_start = .;
+    .ARM.exidx :
+      {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+      } > REGION_RODATA
+    __exidx_end = .;
+
+    /*
+     * .data
+     */
+    .data :
+      {
+        __data_start__ = .;
+      	LONG(0)
+        . = ALIGN(8);
+
+        *(.got.plt) *(.got)
+        *(.data .data.* .gnu.linkonce.d.*)
+
+        . = ALIGN(8);
+        __data_end__ = .;
+      } > REGION_DATA AT> REGION_RODATA
+
+    /*
+     * Read-only data
+     */
+    .rodata :
+      {
+        *(.rodata .rodata.* .gnu.linkonce.r.*)
+        /* .USER_FLASH: We allow users to allocate into Flash here */
+        *(.USER_FLASH)
+        /* ROM image configuration; for C startup */
+        . = ALIGN(4);
+        _lm_rom_img_cfgp = .;
+        LONG(LOADADDR(.data));
+        /*
+         * Heap: Linker scripts may choose a custom heap by overriding
+         * _lm_heap_start and _lm_heap_end. Otherwise, the heap is in
+         * internal SRAM, beginning after .bss, and growing towards
+         * the stack.
+         *
+         * I'm shoving these here naively; there's probably a cleaner way
+         * to go about this. [mbolivar]
+         */
+        _lm_heap_start = DEFINED(_lm_heap_start) ? _lm_heap_start : _end;
+        _lm_heap_end   = DEFINED(_lm_heap_end) ? _lm_heap_end : __msp_init;
+      } > REGION_RODATA
+
+    /*
+     * .bss
+     */
+    .bss :
+      {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss .bss.* .gnu.linkonce.b.*)
+        *(COMMON)
+        . = ALIGN (8);
+        __bss_end__ = .;
+        _end = __bss_end__;
+      } > REGION_BSS
+
+    /*
+     * Debugging sections
+     */
+    .stab 0 (NOLOAD) : { *(.stab) }
+    .stabstr 0 (NOLOAD) : { *(.stabstr) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+
+    .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+    .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+    /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/STM32F1/variants/hytiny_stm32f103t/ld/extra_libs.inc b/STM32F1/variants/hytiny_stm32f103t/ld/extra_libs.inc
new file mode 100644
index 000000000..dd2c84fa4
--- /dev/null
+++ b/STM32F1/variants/hytiny_stm32f103t/ld/extra_libs.inc
@@ -0,0 +1,7 @@
+/*
+ * Extra archives needed by ARM's GCC ARM Embedded arm-none-eabi-
+ * releases (https://launchpad.net/gcc-arm-embedded/).
+ */
+
+/* This is for the provided newlib. */
+GROUP(libnosys.a)
diff --git a/STM32F1/variants/hytiny_stm32f103t/ld/flash.ld b/STM32F1/variants/hytiny_stm32f103t/ld/flash.ld
new file mode 100644
index 000000000..9e250cd74
--- /dev/null
+++ b/STM32F1/variants/hytiny_stm32f103t/ld/flash.ld
@@ -0,0 +1,26 @@
+/*
+ * libmaple linker script for "Flash" builds.
+ *
+ * A Flash build puts .text (and .rodata) in Flash, and
+ * .data/.bss/heap (of course) in SRAM, but offsets the sections by
+ * enough space to store the Maple bootloader, which lives in low
+ * Flash and uses low memory.
+ */
+
+/*
+ * This pulls in the appropriate MEMORY declaration from the right
+ * subdirectory of stm32/mem/ (the environment must call ld with the
+ * right include directory flags to make this happen). Boards can also
+ * use this file to use any of libmaple's memory-related hooks (like
+ * where the heap should live).
+ */
+INCLUDE mem-flash.inc
+
+/* Provide memory region aliases for common.inc */
+REGION_ALIAS("REGION_TEXT", rom);
+REGION_ALIAS("REGION_DATA", ram);
+REGION_ALIAS("REGION_BSS", ram);
+REGION_ALIAS("REGION_RODATA", rom);
+
+/* Let common.inc handle the real work. */
+INCLUDE common.inc
diff --git a/STM32F1/variants/hytiny_stm32f103t/ld/flash_c8.ld b/STM32F1/variants/hytiny_stm32f103t/ld/flash_c8.ld
new file mode 100644
index 000000000..46039238e
--- /dev/null
+++ b/STM32F1/variants/hytiny_stm32f103t/ld/flash_c8.ld
@@ -0,0 +1,33 @@
+/*
+ * libmaple linker script for "Flash" builds.
+ *
+ * A Flash build puts .text (and .rodata) in Flash, and
+ * .data/.bss/heap (of course) in SRAM, but offsets the sections by
+ * enough space to store the Maple bootloader, which lives in low
+ * Flash and uses low memory.
+ */
+
+/*
+ * This pulls in the appropriate MEMORY declaration from the right
+ * subdirectory of stm32/mem/ (the environment must call ld with the
+ * right include directory flags to make this happen). Boards can also
+ * use this file to use any of libmaple's memory-related hooks (like
+ * where the heap should live).
+ */
+/*INCLUDE mem-flash.inc*/
+
+MEMORY
+{
+  ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 17K
+  rom (rx)  : ORIGIN = 0x08000000, LENGTH = 44K
+}
+
+
+/* Provide memory region aliases for common.inc */
+REGION_ALIAS("REGION_TEXT", rom);
+REGION_ALIAS("REGION_DATA", ram);
+REGION_ALIAS("REGION_BSS", ram);
+REGION_ALIAS("REGION_RODATA", rom);
+
+/* Let common.inc handle the real work. */
+INCLUDE common.inc
diff --git a/STM32F1/variants/hytiny_stm32f103t/ld/jtag.ld b/STM32F1/variants/hytiny_stm32f103t/ld/jtag.ld
new file mode 100644
index 000000000..0612f9586
--- /dev/null
+++ b/STM32F1/variants/hytiny_stm32f103t/ld/jtag.ld
@@ -0,0 +1,31 @@
+/*
+ * libmaple linker script for "JTAG" builds.
+ *
+ * A "JTAG" build puts .text (and .rodata) in Flash, and
+ * .data/.bss/heap (of course) in SRAM, but links starting at the
+ * Flash and SRAM starting addresses (0x08000000 and 0x20000000
+ * respectively). This will wipe out a Maple bootloader if there's one
+ * on the board, so only use this if you know what you're doing.
+ *
+ * Of course, a "JTAG" build is perfectly usable for upload over SWD,
+ * the system memory bootloader, etc. The name is just a historical
+ * artifact.
+ */
+
+/*
+ * This pulls in the appropriate MEMORY declaration from the right
+ * subdirectory of stm32/mem/ (the environment must call ld with the
+ * right include directory flags to make this happen). Boards can also
+ * use this file to use any of libmaple's memory-related hooks (like
+ * where the heap should live).
+ */
+INCLUDE mem-jtag.inc
+
+/* Provide memory region aliases for common.inc */
+REGION_ALIAS("REGION_TEXT", rom);
+REGION_ALIAS("REGION_DATA", ram);
+REGION_ALIAS("REGION_BSS", ram);
+REGION_ALIAS("REGION_RODATA", rom);
+
+/* Let common.inc handle the real work. */
+INCLUDE common.inc
diff --git a/STM32F1/variants/hytiny_stm32f103t/ld/jtag_c8.ld b/STM32F1/variants/hytiny_stm32f103t/ld/jtag_c8.ld
new file mode 100644
index 000000000..d9d4a0f0f
--- /dev/null
+++ b/STM32F1/variants/hytiny_stm32f103t/ld/jtag_c8.ld
@@ -0,0 +1,36 @@
+/*
+ * libmaple linker script for "JTAG" builds.
+ *
+ * A "JTAG" build puts .text (and .rodata) in Flash, and
+ * .data/.bss/heap (of course) in SRAM, but links starting at the
+ * Flash and SRAM starting addresses (0x08000000 and 0x20000000
+ * respectively). This will wipe out a Maple bootloader if there's one
+ * on the board, so only use this if you know what you're doing.
+ *
+ * Of course, a "JTAG" build is perfectly usable for upload over SWD,
+ * the system memory bootloader, etc. The name is just a historical
+ * artifact.
+ */
+
+/*
+ * This pulls in the appropriate MEMORY declaration from the right
+ * subdirectory of stm32/mem/ (the environment must call ld with the
+ * right include directory flags to make this happen). Boards can also
+ * use this file to use any of libmaple's memory-related hooks (like
+ * where the heap should live).
+ */
+
+MEMORY
+{
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
+  rom (rx)  : ORIGIN = 0x08000000, LENGTH = 64K
+}
+
+/* Provide memory region aliases for common.inc */
+REGION_ALIAS("REGION_TEXT", rom);
+REGION_ALIAS("REGION_DATA", ram);
+REGION_ALIAS("REGION_BSS", ram);
+REGION_ALIAS("REGION_RODATA", rom);
+
+/* Let common.inc handle the real work. */
+INCLUDE common.inc
diff --git a/STM32F1/variants/hytiny_stm32f103t/ld/mem-flash.inc b/STM32F1/variants/hytiny_stm32f103t/ld/mem-flash.inc
new file mode 100644
index 000000000..a9091ca85
--- /dev/null
+++ b/STM32F1/variants/hytiny_stm32f103t/ld/mem-flash.inc
@@ -0,0 +1,5 @@
+MEMORY
+{
+  ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 17K
+  rom (rx)  : ORIGIN = 0x08005000, LENGTH = 108K
+}
diff --git a/STM32F1/variants/hytiny_stm32f103t/ld/mem-jtag.inc b/STM32F1/variants/hytiny_stm32f103t/ld/mem-jtag.inc
new file mode 100644
index 000000000..20fbec056
--- /dev/null
+++ b/STM32F1/variants/hytiny_stm32f103t/ld/mem-jtag.inc
@@ -0,0 +1,5 @@
+MEMORY
+{
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 20K
+  rom (rx)  : ORIGIN = 0x08000000, LENGTH = 128K
+}
diff --git a/STM32F1/variants/hytiny_stm32f103t/ld/mem-ram.inc b/STM32F1/variants/hytiny_stm32f103t/ld/mem-ram.inc
new file mode 100644
index 000000000..f02453b9a
--- /dev/null
+++ b/STM32F1/variants/hytiny_stm32f103t/ld/mem-ram.inc
@@ -0,0 +1,5 @@
+MEMORY
+{
+  ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 17K
+  rom (rx)  : ORIGIN = 0x08005000, LENGTH = 0K
+}
diff --git a/STM32F1/variants/hytiny_stm32f103t/ld/ram.ld b/STM32F1/variants/hytiny_stm32f103t/ld/ram.ld
new file mode 100644
index 000000000..34b468e0a
--- /dev/null
+++ b/STM32F1/variants/hytiny_stm32f103t/ld/ram.ld
@@ -0,0 +1,25 @@
+/*
+ * libmaple linker script for RAM builds.
+ *
+ * A Flash build puts .text, .rodata, and .data/.bss/heap (of course)
+ * in SRAM, but offsets the sections by enough space to store the
+ * Maple bootloader, which uses low memory.
+ */
+
+/*
+ * This pulls in the appropriate MEMORY declaration from the right
+ * subdirectory of stm32/mem/ (the environment must call ld with the
+ * right include directory flags to make this happen). Boards can also
+ * use this file to use any of libmaple's memory-related hooks (like
+ * where the heap should live).
+ */
+INCLUDE mem-ram.inc
+
+/* Provide memory region aliases for common.inc */
+REGION_ALIAS("REGION_TEXT", ram);
+REGION_ALIAS("REGION_DATA", ram);
+REGION_ALIAS("REGION_BSS", ram);
+REGION_ALIAS("REGION_RODATA", ram);
+
+/* Let common.inc handle the real work. */
+INCLUDE common.inc
diff --git a/STM32F1/variants/hytiny_stm32f103t/ld/ram_c8.ld b/STM32F1/variants/hytiny_stm32f103t/ld/ram_c8.ld
new file mode 100644
index 000000000..71e081e36
--- /dev/null
+++ b/STM32F1/variants/hytiny_stm32f103t/ld/ram_c8.ld
@@ -0,0 +1,31 @@
+/*
+ * libmaple linker script for RAM builds.
+ *
+ * A Flash build puts .text, .rodata, and .data/.bss/heap (of course)
+ * in SRAM, but offsets the sections by enough space to store the
+ * Maple bootloader, which uses low memory.
+ */
+
+/*
+ * This pulls in the appropriate MEMORY declaration from the right
+ * subdirectory of stm32/mem/ (the environment must call ld with the
+ * right include directory flags to make this happen). Boards can also
+ * use this file to use any of libmaple's memory-related hooks (like
+ * where the heap should live).
+ */
+/*INCLUDE mem-ram.inc*/
+MEMORY
+{
+  ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 17K
+  rom (rx)  : ORIGIN = 0x08005000, LENGTH = 0
+}
+
+
+/* Provide memory region aliases for common.inc */
+REGION_ALIAS("REGION_TEXT", ram);
+REGION_ALIAS("REGION_DATA", ram);
+REGION_ALIAS("REGION_BSS", ram);
+REGION_ALIAS("REGION_RODATA", ram);
+
+/* Let common.inc handle the real work. */
+INCLUDE common.inc
diff --git a/STM32F1/variants/hytiny_stm32f103t/ld/vector_symbols.inc b/STM32F1/variants/hytiny_stm32f103t/ld/vector_symbols.inc
new file mode 100644
index 000000000..f8519bba4
--- /dev/null
+++ b/STM32F1/variants/hytiny_stm32f103t/ld/vector_symbols.inc
@@ -0,0 +1,78 @@
+EXTERN(__msp_init)
+EXTERN(__exc_reset)
+EXTERN(__exc_nmi)
+EXTERN(__exc_hardfault)
+EXTERN(__exc_memmanage)
+EXTERN(__exc_busfault)
+EXTERN(__exc_usagefault)
+EXTERN(__stm32reservedexception7)
+EXTERN(__stm32reservedexception8)
+EXTERN(__stm32reservedexception9)
+EXTERN(__stm32reservedexception10)
+EXTERN(__exc_svc)
+EXTERN(__exc_debug_monitor)
+EXTERN(__stm32reservedexception13)
+EXTERN(__exc_pendsv)
+EXTERN(__exc_systick)
+
+EXTERN(__irq_wwdg)
+EXTERN(__irq_pvd)
+EXTERN(__irq_tamper)
+EXTERN(__irq_rtc)
+EXTERN(__irq_flash)
+EXTERN(__irq_rcc)
+EXTERN(__irq_exti0)
+EXTERN(__irq_exti1)
+EXTERN(__irq_exti2)
+EXTERN(__irq_exti3)
+EXTERN(__irq_exti4)
+EXTERN(__irq_dma1_channel1)
+EXTERN(__irq_dma1_channel2)
+EXTERN(__irq_dma1_channel3)
+EXTERN(__irq_dma1_channel4)
+EXTERN(__irq_dma1_channel5)
+EXTERN(__irq_dma1_channel6)
+EXTERN(__irq_dma1_channel7)
+EXTERN(__irq_adc)
+EXTERN(__irq_usb_hp_can_tx)
+EXTERN(__irq_usb_lp_can_rx0)
+EXTERN(__irq_can_rx1)
+EXTERN(__irq_can_sce)
+EXTERN(__irq_exti9_5)
+EXTERN(__irq_tim1_brk)
+EXTERN(__irq_tim1_up)
+EXTERN(__irq_tim1_trg_com)
+EXTERN(__irq_tim1_cc)
+EXTERN(__irq_tim2)
+EXTERN(__irq_tim3)
+EXTERN(__irq_tim4)
+EXTERN(__irq_i2c1_ev)
+EXTERN(__irq_i2c1_er)
+EXTERN(__irq_i2c2_ev)
+EXTERN(__irq_i2c2_er)
+EXTERN(__irq_spi1)
+EXTERN(__irq_spi2)
+EXTERN(__irq_usart1)
+EXTERN(__irq_usart2)
+EXTERN(__irq_usart3)
+EXTERN(__irq_exti15_10)
+EXTERN(__irq_rtcalarm)
+EXTERN(__irq_usbwakeup)
+
+EXTERN(__irq_tim8_brk)
+EXTERN(__irq_tim8_up)
+EXTERN(__irq_tim8_trg_com)
+EXTERN(__irq_tim8_cc)
+EXTERN(__irq_adc3)
+EXTERN(__irq_fsmc)
+EXTERN(__irq_sdio)
+EXTERN(__irq_tim5)
+EXTERN(__irq_spi3)
+EXTERN(__irq_uart4)
+EXTERN(__irq_uart5)
+EXTERN(__irq_tim6)
+EXTERN(__irq_tim7)
+EXTERN(__irq_dma2_channel1)
+EXTERN(__irq_dma2_channel2)
+EXTERN(__irq_dma2_channel3)
+EXTERN(__irq_dma2_channel4_5)
diff --git a/STM32F1/variants/hytiny_stm32f103t/pins_arduino.h b/STM32F1/variants/hytiny_stm32f103t/pins_arduino.h
new file mode 100644
index 000000000..3052f2eb2
--- /dev/null
+++ b/STM32F1/variants/hytiny_stm32f103t/pins_arduino.h
@@ -0,0 +1,6 @@
+
+
+
+
+// API compatibility
+#include "variant.h"
\ No newline at end of file
diff --git a/STM32F1/variants/hytiny_stm32f103t/variant.h b/STM32F1/variants/hytiny_stm32f103t/variant.h
new file mode 100644
index 000000000..fc5da7ecd
--- /dev/null
+++ b/STM32F1/variants/hytiny_stm32f103t/variant.h
@@ -0,0 +1,19 @@
+#ifndef _VARIANT_ARDUINO_STM32_
+#define _VARIANT_ARDUINO_STM32_
+
+#define digitalPinToPort(P)        ( PIN_MAP[P].gpio_device )
+#define digitalPinToBitMask(P)     ( BIT(PIN_MAP[P].gpio_bit) )
+#define portOutputRegister(port)   ( &(port->regs->ODR) )
+#define portInputRegister(port)    ( &(port->regs->IDR) )
+
+#define portSetRegister(pin)		( &(PIN_MAP[pin].gpio_device->regs->BSRR) )
+#define portClearRegister(pin)		( &(PIN_MAP[pin].gpio_device->regs->BRR) )
+
+#define portConfigRegister(pin)		( &(PIN_MAP[pin].gpio_device->regs->CRL) )
+
+static const uint8_t SS   = BOARD_SPI1_NSS_PIN;
+static const uint8_t MOSI = BOARD_SPI1_MOSI_PIN;
+static const uint8_t MISO = BOARD_SPI1_MISO_PIN;
+static const uint8_t SCK  = BOARD_SPI1_SCK_PIN;
+
+#endif /* _VARIANT_ARDUINO_STM32_ */
\ No newline at end of file
diff --git a/STM32F1/variants/hytiny_stm32f103t/wirish/boards.cpp b/STM32F1/variants/hytiny_stm32f103t/wirish/boards.cpp
new file mode 100644
index 000000000..0a358ee19
--- /dev/null
+++ b/STM32F1/variants/hytiny_stm32f103t/wirish/boards.cpp
@@ -0,0 +1,229 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Perry Hung.
+ * Copyright (c) 2011, 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file wirish/boards.cpp
+ * @brief init() and board routines.
+ *
+ * This file is mostly interesting for the init() function, which
+ * configures Flash, the core clocks, and a variety of other available
+ * peripherals on the board so the rest of Wirish doesn't have to turn
+ * things on before using them.
+ *
+ * Prior to returning, init() calls boardInit(), which allows boards
+ * to perform any initialization they need to. This file includes a
+ * weak no-op definition of boardInit(), so boards that don't need any
+ * special initialization don't have to define their own.
+ *
+ * How init() works is chip-specific. See the boards_setup.cpp files
+ * under e.g. wirish/stm32f1/, wirish/stmf32f2 for the details, but be
+ * advised: their contents are unstable, and can/will change without
+ * notice.
+ */
+
+#include <boards.h>
+#include <libmaple/libmaple_types.h>
+#include <libmaple/flash.h>
+#include <libmaple/nvic.h>
+#include <libmaple/systick.h>
+#include "boards_private.h"
+
+static void setup_flash(void);
+static void setup_clocks(void);
+static void setup_nvic(void);
+static void setup_adcs(void);
+static void setup_timers(void);
+
+/*
+ * Exported functions
+ */
+
+void init(void) {
+    setup_flash();
+    setup_clocks();
+    setup_nvic();
+    systick_init(SYSTICK_RELOAD_VAL);
+    wirish::priv::board_setup_gpio();
+    setup_adcs();
+    setup_timers();
+    wirish::priv::board_setup_usb();
+    wirish::priv::series_init();
+    boardInit();
+}
+
+/* Provide a default no-op boardInit(). */
+__weak void boardInit(void) {
+}
+
+/* You could farm this out to the files in boards/ if e.g. it takes
+ * too long to test on boards with lots of pins. */
+bool boardUsesPin(uint8 pin) {
+    for (int i = 0; i < BOARD_NR_USED_PINS; i++) {
+        if (pin == boardUsedPins[i]) {
+            return true;
+        }
+    }
+    return false;
+}
+
+/*
+ * Auxiliary routines
+ */
+
+static void setup_flash(void) {
+    // Turn on as many Flash "go faster" features as
+    // possible. flash_enable_features() just ignores any flags it
+    // can't support.
+    flash_enable_features(FLASH_PREFETCH | FLASH_ICACHE | FLASH_DCACHE);
+    // Configure the wait states, assuming we're operating at "close
+    // enough" to 3.3V.
+    flash_set_latency(FLASH_SAFE_WAIT_STATES);
+}
+
+static void setup_clocks(void) {
+    // Turn on HSI. We'll switch to and run off of this while we're
+    // setting up the main PLL.
+    rcc_turn_on_clk(RCC_CLK_HSI);
+
+    // Turn off and reset the clock subsystems we'll be using, as well
+    // as the clock security subsystem (CSS). Note that resetting CFGR
+    // to its default value of 0 implies a switch to HSI for SYSCLK.
+    RCC_BASE->CFGR = 0x00000000;
+    rcc_disable_css();
+    rcc_turn_off_clk(RCC_CLK_PLL);
+    rcc_turn_off_clk(RCC_CLK_HSE);
+    wirish::priv::board_reset_pll();
+    // Clear clock readiness interrupt flags and turn off clock
+    // readiness interrupts.
+    RCC_BASE->CIR = 0x00000000;
+
+    // Enable HSE, and wait until it's ready.
+    rcc_turn_on_clk(RCC_CLK_HSE);
+    while (!rcc_is_clk_ready(RCC_CLK_HSE))
+        ;
+
+    // Configure AHBx, APBx, etc. prescalers and the main PLL.
+    wirish::priv::board_setup_clock_prescalers();
+    rcc_configure_pll(&wirish::priv::w_board_pll_cfg);
+
+    // Enable the PLL, and wait until it's ready.
+    rcc_turn_on_clk(RCC_CLK_PLL);
+    while(!rcc_is_clk_ready(RCC_CLK_PLL))
+        ;
+
+    // Finally, switch to the now-ready PLL as the main clock source.
+    rcc_switch_sysclk(RCC_CLKSRC_PLL);
+}
+
+/*
+ * These addresses are where usercode starts when a bootloader is
+ * present. If no bootloader is present, the user NVIC usually starts
+ * at the Flash base address, 0x08000000.
+ */
+#if defined(BOOTLOADER_maple)
+	#define USER_ADDR_ROM 0x08005000
+#else
+	#if defined(BOOTLOADER_robotis)
+		#define USER_ADDR_ROM 0x08003000
+	#else
+		#define USER_ADDR_ROM 0x08000000
+	#endif
+#endif
+#define USER_ADDR_RAM 0x20000C00
+extern char __text_start__;
+
+static void setup_nvic(void) {
+
+nvic_init((uint32)VECT_TAB_ADDR, 0);
+
+/* Roger Clark. We now control nvic vector table in boards.txt using the build.vect paramater
+#ifdef VECT_TAB_FLASH
+    nvic_init(USER_ADDR_ROM, 0);
+#elif defined VECT_TAB_RAM
+    nvic_init(USER_ADDR_RAM, 0);
+#elif defined VECT_TAB_BASE
+    nvic_init((uint32)0x08000000, 0);
+#elif defined VECT_TAB_ADDR
+    // A numerically supplied value
+    nvic_init((uint32)VECT_TAB_ADDR, 0);
+#else
+    // Use the __text_start__ value from the linker script; this
+    // should be the start of the vector table.
+    nvic_init((uint32)&__text_start__, 0);
+#endif
+
+*/
+}
+
+static void adc_default_config( adc_dev *dev) {
+    adc_enable_single_swstart(dev);
+    adc_set_sample_rate(dev, wirish::priv::w_adc_smp);
+}
+
+static void setup_adcs(void) {
+    adc_set_prescaler(wirish::priv::w_adc_pre);
+    adc_foreach(adc_default_config);
+}
+
+static void timer_default_config(timer_dev *dev) {
+    timer_adv_reg_map *regs = (dev->regs).adv;
+    const uint16 full_overflow = 0xFFFF;
+    const uint16 half_duty = 0x8FFF;
+
+    timer_init(dev);
+    timer_pause(dev);
+
+    regs->CR1 = TIMER_CR1_ARPE;
+    regs->PSC = 1;
+    regs->SR = 0;
+    regs->DIER = 0;
+    regs->EGR = TIMER_EGR_UG;
+    switch (dev->type) {
+    case TIMER_ADVANCED:
+        regs->BDTR = TIMER_BDTR_MOE | TIMER_BDTR_LOCK_OFF;
+        // fall-through
+    case TIMER_GENERAL:
+        timer_set_reload(dev, full_overflow);
+        for (uint8 channel = 1; channel <= 4; channel++) {
+            if (timer_has_cc_channel(dev, channel)) {
+                timer_set_compare(dev, channel, half_duty);
+                timer_oc_set_mode(dev, channel, TIMER_OC_MODE_PWM_1,
+                                  TIMER_OC_PE);
+            }
+        }
+        // fall-through
+    case TIMER_BASIC:
+        break;
+    }
+
+    timer_generate_update(dev);
+    timer_resume(dev);
+}
+
+static void setup_timers(void) {
+    timer_foreach(timer_default_config);
+}
diff --git a/STM32F1/variants/hytiny_stm32f103t/wirish/boards_setup.cpp b/STM32F1/variants/hytiny_stm32f103t/wirish/boards_setup.cpp
new file mode 100644
index 000000000..5d762c7cc
--- /dev/null
+++ b/STM32F1/variants/hytiny_stm32f103t/wirish/boards_setup.cpp
@@ -0,0 +1,96 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+*****************************************************************************/
+
+/**
+ * @file wirish/stm32f1/boards_setup.cpp
+ * @author Marti Bolivar <mbolivar@leaflabs.com>
+ * @brief STM32F1 chip setup.
+ *
+ * This file controls how init() behaves on the STM32F1. Be very
+ * careful when changing anything here. Many of these values depend
+ * upon each other.
+ */
+
+#include "boards_private.h"
+
+#include <libmaple/gpio.h>
+#include <libmaple/timer.h>
+
+#include <boards.h>
+#include <usb_serial.h>
+
+// Allow boards to provide a PLL multiplier. This is useful for
+// e.g. STM32F100 value line MCUs, which use slower multipliers.
+// (We're leaving the default to RCC_PLLMUL_9 for now, since that
+// works for F103 performance line MCUs, which is all that LeafLabs
+// currently officially supports).
+#ifndef BOARD_RCC_PLLMUL
+#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+#endif
+
+namespace wirish {
+    namespace priv {
+
+        static stm32f1_rcc_pll_data pll_data = {BOARD_RCC_PLLMUL};
+        __weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data};
+        __weak adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_6;
+        __weak adc_smp_rate w_adc_smp = ADC_SMPR_55_5;
+
+        __weak void board_reset_pll(void) {
+            // TODO
+        }
+
+        __weak void board_setup_clock_prescalers(void) {
+            rcc_set_prescaler(RCC_PRESCALER_AHB, RCC_AHB_SYSCLK_DIV_1);
+            rcc_set_prescaler(RCC_PRESCALER_APB1, RCC_APB1_HCLK_DIV_2);
+            rcc_set_prescaler(RCC_PRESCALER_APB2, RCC_APB2_HCLK_DIV_1);
+			rcc_clk_disable(RCC_USB);
+			#if F_CPU == 72000000
+			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);
+			#elif F_CPU == 48000000
+			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);			
+			#endif				
+        }
+
+        __weak void board_setup_gpio(void) {
+            gpio_init_all();
+        }
+
+        __weak void board_setup_usb(void) {
+#ifdef SERIAL_USB
+//          SerialUSB.begin();
+			Serial.begin();// Roger Clark. Changed SerialUSB to Serial for Arduino sketch compatibility
+#endif
+		}
+
+        __weak void series_init(void) {
+            // Initialize AFIO here, too, so peripheral remaps and external
+            // interrupts work out of the box.
+            afio_init();
+        }
+
+    }
+}
diff --git a/STM32F1/variants/hytiny_stm32f103t/wirish/start.S b/STM32F1/variants/hytiny_stm32f103t/wirish/start.S
new file mode 100644
index 000000000..8b181aa99
--- /dev/null
+++ b/STM32F1/variants/hytiny_stm32f103t/wirish/start.S
@@ -0,0 +1,57 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/*
+ * This file is a modified version of a file obtained from
+ * CodeSourcery Inc. (now part of Mentor Graphics Corp.), in which the
+ * following text appeared:
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+        .text
+        .code 16
+        .thumb_func
+
+        .globl __start__
+        .type __start__, %function
+__start__:
+        .fnstart
+        ldr r1,=__msp_init
+        mov sp,r1
+        ldr r1,=start_c
+        bx r1
+        .pool
+        .cantunwind
+        .fnend
diff --git a/STM32F1/variants/hytiny_stm32f103t/wirish/start_c.c b/STM32F1/variants/hytiny_stm32f103t/wirish/start_c.c
new file mode 100644
index 000000000..655fefb88
--- /dev/null
+++ b/STM32F1/variants/hytiny_stm32f103t/wirish/start_c.c
@@ -0,0 +1,95 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/*
+ * This file is a modified version of a file obtained from
+ * CodeSourcery Inc. (now part of Mentor Graphics Corp.), in which the
+ * following text appeared:
+ *
+ * Copyright (c) 2006, 2007 CodeSourcery Inc
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+#include <stddef.h>
+
+extern void __libc_init_array(void);
+
+extern int main(int, char**, char**);
+
+extern void exit(int) __attribute__((noreturn, weak));
+
+/* The linker must ensure that these are at least 4-byte aligned. */
+extern char __data_start__, __data_end__;
+extern char __bss_start__, __bss_end__;
+
+struct rom_img_cfg {
+    int *img_start;
+};
+
+extern char _lm_rom_img_cfgp;
+
+void __attribute__((noreturn)) start_c(void) {
+    struct rom_img_cfg *img_cfg = (struct rom_img_cfg*)&_lm_rom_img_cfgp;
+    int *src = img_cfg->img_start;
+    int *dst = (int*)&__data_start__;
+    int exit_code;
+
+    /* Initialize .data, if necessary. */
+    if (src != dst) {
+        int *end = (int*)&__data_end__;
+        while (dst < end) {
+            *dst++ = *src++;
+        }
+    }
+
+    /* Zero .bss. */
+    dst = (int*)&__bss_start__;
+    while (dst < (int*)&__bss_end__) {
+        *dst++ = 0;
+    }
+
+    /* Run initializers. */
+    __libc_init_array();
+
+    /* Jump to main. */
+    exit_code = main(0, 0, 0);
+    if (exit) {
+        exit(exit_code);
+    }
+
+    /* If exit is NULL, make sure we don't return. */
+    for (;;)
+        continue;
+}
diff --git a/STM32F1/variants/hytiny_stm32f103t/wirish/syscalls.c b/STM32F1/variants/hytiny_stm32f103t/wirish/syscalls.c
new file mode 100644
index 000000000..d5f2d9fac
--- /dev/null
+++ b/STM32F1/variants/hytiny_stm32f103t/wirish/syscalls.c
@@ -0,0 +1,176 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Perry Hung.
+ * Copyright (c) 2011, 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file wirish/syscalls.c
+ * @brief newlib stubs
+ *
+ * Low level system routines used by newlib for basic I/O and memory
+ * allocation. You can override most of these.
+ */
+
+#include <libmaple/libmaple.h>
+
+#include <sys/stat.h>
+#include <errno.h>
+#include <stddef.h>
+
+/* If CONFIG_HEAP_START (or CONFIG_HEAP_END) isn't defined, then
+ * assume _lm_heap_start (resp. _lm_heap_end) is appropriately set by
+ * the linker */
+#ifndef CONFIG_HEAP_START
+extern char _lm_heap_start;
+#define CONFIG_HEAP_START               ((void *)&_lm_heap_start)
+#endif
+#ifndef CONFIG_HEAP_END
+extern char _lm_heap_end;
+#define CONFIG_HEAP_END                 ((void *)&_lm_heap_end)
+#endif
+
+/*
+ * _sbrk -- Increment the program break.
+ *
+ * Get incr bytes more RAM (for use by the heap).  malloc() and
+ * friends call this function behind the scenes.
+ */
+void *_sbrk(int incr) {
+    static void * pbreak = NULL; /* current program break */
+    void * ret;
+
+    if (pbreak == NULL) {
+        pbreak = CONFIG_HEAP_START;
+    }
+
+    if ((CONFIG_HEAP_END - pbreak < incr) ||
+        (pbreak - CONFIG_HEAP_START < -incr)) {
+        errno = ENOMEM;
+        return (void *)-1;
+    }
+
+    ret = pbreak;
+    pbreak += incr;
+    return ret;
+}
+
+__weak int _open(const char *path, int flags, ...) {
+    return 1;
+}
+
+__weak int _close(int fd) {
+    return 0;
+}
+
+__weak int _fstat(int fd, struct stat *st) {
+    st->st_mode = S_IFCHR;
+    return 0;
+}
+
+__weak int _isatty(int fd) {
+    return 1;
+}
+
+__weak int isatty(int fd) {
+    return 1;
+}
+
+__weak int _lseek(int fd, off_t pos, int whence) {
+    return -1;
+}
+
+__weak unsigned char getch(void) {
+    return 0;
+}
+
+
+__weak int _read(int fd, char *buf, size_t cnt) {
+    *buf = getch();
+
+    return 1;
+}
+
+__weak void putch(unsigned char c) {
+}
+
+__weak void cgets(char *s, int bufsize) {
+    char *p;
+    int c;
+    int i;
+
+    for (i = 0; i < bufsize; i++) {
+        *(s+i) = 0;
+    }
+//    memset(s, 0, bufsize);
+
+    p = s;
+
+    for (p = s; p < s + bufsize-1;) {
+        c = getch();
+        switch (c) {
+        case '\r' :
+        case '\n' :
+            putch('\r');
+            putch('\n');
+            *p = '\n';
+            return;
+
+        case '\b' :
+            if (p > s) {
+                *p-- = 0;
+                putch('\b');
+                putch(' ');
+                putch('\b');
+            }
+            break;
+
+        default :
+            putch(c);
+            *p++ = c;
+            break;
+        }
+    }
+    return;
+}
+
+__weak int _write(int fd, const char *buf, size_t cnt) {
+    int i;
+
+    for (i = 0; i < cnt; i++)
+        putch(buf[i]);
+
+    return cnt;
+}
+
+/* Override fgets() in newlib with a version that does line editing */
+__weak char *fgets(char *s, int bufsize, void *f) {
+    cgets(s, bufsize);
+    return s;
+}
+
+__weak void _exit(int exitcode) {
+    while (1)
+        ;
+}

From 16ab26608f44abe413ddbd0667b860fcf106decd Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sun, 30 Oct 2016 21:55:26 +1100
Subject: [PATCH 005/307] Fix minor issues with Hy-Tiny STM32F103T

---
 STM32F1/boards.txt | 22 +++++++---------------
 1 file changed, 7 insertions(+), 15 deletions(-)

diff --git a/STM32F1/boards.txt b/STM32F1/boards.txt
index b56272f7d..8cbd57b63 100644
--- a/STM32F1/boards.txt
+++ b/STM32F1/boards.txt
@@ -464,7 +464,7 @@ genericSTM32F103Z.menu.upload_method.BMPMethod.build.upload_flags=-DCONFIG_MAPLE
 
 ###################### HYTiny STM32F103T ########################################
 
-hytiny-stm32f103t.name=HYTiny STM32F103T series
+hytiny-stm32f103t.name=HYTiny STM32F103TB
 hytiny-stm32f103t.vid.0=0x1EAF
 hytiny-stm32f103t.pid.0=0x0004
 hytiny-stm32f103t.build.variant=hytiny_stm32f103t
@@ -475,21 +475,13 @@ hytiny-stm32f103t.upload.use_1200bps_touch=false
 hytiny-stm32f103t.upload.file_type=bin
 hytiny-stm32f103t.upload.auto_reset=true
 
-## STM32F103C8 -------------------------
-hytiny-stm32f103t.menu.device_variant.STM32F103C8=STM32F103C8 (20k RAM. 64k Flash)
-hytiny-stm32f103t.menu.device_variant.STM32F103C8.build.cpu_flags=-DMCU_STM32F103C8
-hytiny-stm32f103t.menu.device_variant.STM32F103C8.build.ldscript=ld/jtag_c8.ld
-hytiny-stm32f103t.menu.device_variant.STM32F103C8.upload.maximum_size=65536
-hytiny-stm32f103t.menu.device_variant.STM32F103C8.upload.ram.maximum_size=20480
-hytiny-stm32f103t.menu.device_variant.STM32F103C8.upload.flash.maximum_size=65536
 
-## STM32F103CB -------------------------
-hytiny-stm32f103t.menu.device_variant.STM32F103CB=STM32F103CB (20k RAM. 128k Flash)
-hytiny-stm32f103t.menu.device_variant.STM32F103CB.build.cpu_flags=-DMCU_STM32F103CB
-hytiny-stm32f103t.menu.device_variant.STM32F103CB.build.ldscript=ld/jtag.ld
-hytiny-stm32f103t.menu.device_variant.STM32F103CB.upload.maximum_size=131072
-hytiny-stm32f103t.menu.device_variant.STM32F103CB.upload.ram.maximum_size=20480
-hytiny-stm32f103t.menu.device_variant.STM32F103CB.upload.flash.maximum_size=131072
+hytiny-stm32f103t.build.cpu_flags=-DMCU_STM32F103CB
+hytiny-stm32f103t.build.ldscript=ld/jtag.ld
+hytiny-stm32f103t.upload.maximum_size=131072
+hytiny-stm32f103t.upload.ram.maximum_size=20480
+hytiny-stm32f103t.upload.flash.maximum_size=131072
+
 
 #---------------------------- UPLOAD METHODS ---------------------------
 

From 4bc4b1d6bd42816c935053f043b8697f5e393434 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Mon, 31 Oct 2016 22:12:04 +0100
Subject: [PATCH 006/307] remove unused functions + adapt passed parameter

- remove unused functions form usb_reg_map
- change passed buffer type to uint8 *
---
 STM32F1/cores/maple/libmaple/usb/stm32f1/usb_reg_map.c | 8 ++++----
 STM32F1/cores/maple/usb_serial.h                       | 2 +-
 STM32F1/system/libmaple/usb/stm32f1/usb_reg_map.h      | 6 +++---
 3 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_reg_map.c b/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_reg_map.c
index ea60cb3c2..3f5446aa6 100644
--- a/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_reg_map.c
+++ b/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_reg_map.c
@@ -29,7 +29,7 @@
 /* TODO these could use some improvement; they're fairly
  * straightforward ports of the analogous ST code.  The PMA blit
  * routines in particular are obvious targets for performance
- * measurement and tuning. */
+ * measurement and tuning.
 
 void usb_copy_to_pma(const uint8 *buf, uint16 len, uint16 pma_offset) {
     uint16 *dst = (uint16*)usb_pma_ptr(pma_offset);
@@ -57,7 +57,7 @@ void usb_copy_from_pma(uint8 *buf, uint16 len, uint16 pma_offset) {
         *dst = *src & 0xFF;
     }
 }
-
+ */
 static void usb_set_ep_rx_count_common(uint32 *rxc, uint16 count) {
     uint16 nblocks;
     if (count > 62) {
@@ -76,12 +76,12 @@ static void usb_set_ep_rx_count_common(uint32 *rxc, uint16 count) {
         *rxc = nblocks << 10;
     }
 }
-
+/*
 void usb_set_ep_rx_buf0_count(uint8 ep, uint16 count) {
     uint32 *rxc = usb_ep_rx_buf0_count_ptr(ep);
     usb_set_ep_rx_count_common(rxc, count);
 }
-
+*/
 void usb_set_ep_rx_count(uint8 ep, uint16 count) {
     uint32 *rxc = usb_ep_rx_count_ptr(ep);
     usb_set_ep_rx_count_common(rxc, count);
diff --git a/STM32F1/cores/maple/usb_serial.h b/STM32F1/cores/maple/usb_serial.h
index e50a16c27..96bbefc25 100644
--- a/STM32F1/cores/maple/usb_serial.h
+++ b/STM32F1/cores/maple/usb_serial.h
@@ -65,7 +65,7 @@ class USBSerial : public Stream {
 	
     size_t write(uint8);
     size_t write(const char *str);
-    size_t write(const void*, uint32);
+    size_t write(const uint8*, uint32);
 
     uint8 getRTS();
     uint8 getDTR();
diff --git a/STM32F1/system/libmaple/usb/stm32f1/usb_reg_map.h b/STM32F1/system/libmaple/usb/stm32f1/usb_reg_map.h
index 9e9214cf1..d0423fc11 100644
--- a/STM32F1/system/libmaple/usb/stm32f1/usb_reg_map.h
+++ b/STM32F1/system/libmaple/usb/stm32f1/usb_reg_map.h
@@ -345,10 +345,10 @@ static inline void usb_clear_status_out(uint8 ep) {
 /*
  * PMA conveniences
  */
-
+/*
 void usb_copy_to_pma(const uint8 *buf, uint16 len, uint16 pma_offset);
 void usb_copy_from_pma(uint8 *buf, uint16 len, uint16 pma_offset);
-
+*/
 static inline uint32 * usb_pma_ptr(uint32 offset) {
     return (uint32*)(USB_PMA_BASE + 2 * offset);
 }
@@ -567,7 +567,7 @@ static inline uint16 usb_get_ep_rx_buf0_count(uint8 ep) {
     return usb_get_ep_tx_count(ep);
 }
 
-void usb_set_ep_rx_buf0_count(uint8 ep, uint16 count);
+//void usb_set_ep_rx_buf0_count(uint8 ep, uint16 count);
 
 static inline uint32* usb_ep_rx_buf1_count_ptr(uint8 ep) {
     return usb_ep_rx_count_ptr(ep);

From 5db25232840ec8f0922a79e3a1a19a86f5397207 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Mon, 31 Oct 2016 22:29:40 +0100
Subject: [PATCH 007/307] improve SPI low level functions

- optimize code and run-time
---
 STM32F1/cores/maple/libmaple/spi.c |   6 +-
 STM32F1/libraries/SPI/src/SPI.cpp  | 178 ++++++++++-------------------
 STM32F1/libraries/SPI/src/SPI.h    |  25 ++--
 3 files changed, 74 insertions(+), 135 deletions(-)

diff --git a/STM32F1/cores/maple/libmaple/spi.c b/STM32F1/cores/maple/libmaple/spi.c
index 1020c5baf..64f06d301 100644
--- a/STM32F1/cores/maple/libmaple/spi.c
+++ b/STM32F1/cores/maple/libmaple/spi.c
@@ -84,7 +84,7 @@ void spi_slave_enable(spi_dev *dev, spi_mode mode, uint32 flags) {
 }
 
 /**
- * @brief Nonblocking SPI transmit.
+ * @brief Blocking SPI transmit.
  * @param dev SPI port to use for transmission
  * @param buf Buffer to transmit.  The sizeof buf's elements are
  *            inferred from dev's data frame format (i.e., are
@@ -95,7 +95,8 @@ void spi_slave_enable(spi_dev *dev, spi_mode mode, uint32 flags) {
 uint32 spi_tx(spi_dev *dev, const void *buf, uint32 len) {
     uint32 txed = 0;
     uint8 byte_frame = spi_dff(dev) == SPI_DFF_8_BIT;
-    while (spi_is_tx_empty(dev) && (txed < len)) {
+    while ( txed < len ) {
+		while ( spi_is_tx_empty(dev)==0 ); // wait Tx to be empty
         if (byte_frame) {
             dev->regs->DR = ((const uint8*)buf)[txed++];
         } else {
@@ -162,5 +163,6 @@ static void spi_reconfigure(spi_dev *dev, uint32 cr1_config) {
 	spi_irq_disable(dev, SPI_INTERRUPTS_ALL);
 	if ( (dev->regs->CR1&MASK)!=(cr1_config&MASK) )	spi_peripheral_disable(dev);
 	dev->regs->CR1 = cr1_config;
+	//spi_rx_dma_enable(dev);
 	spi_peripheral_enable(dev);
 }
diff --git a/STM32F1/libraries/SPI/src/SPI.cpp b/STM32F1/libraries/SPI/src/SPI.cpp
index 4eeec3811..08327912f 100644
--- a/STM32F1/libraries/SPI/src/SPI.cpp
+++ b/STM32F1/libraries/SPI/src/SPI.cpp
@@ -41,6 +41,8 @@
 #include "boards.h"
 
 //#include "HardwareSerial.h"
+/** Time in ms for DMA receive timeout */
+#define DMA_TIMEOUT 100
 
 #if CYCLES_PER_MICROSECOND != 72
 /* TODO [0.2.0?] something smarter than this */
@@ -304,138 +306,110 @@ void SPIClass::endTransaction(void)
  * I/O
  */
 
-uint8 SPIClass::read(void) {
-    uint8 buf[1];
-    this->read(buf, 1);
-    return buf[0];
+uint8 SPIClass::read(void)
+{
+	while ( spi_is_rx_nonempty(_currentSetting->spi_d)==0 ) ;
+	return (uint8)spi_rx_reg(_currentSetting->spi_d);
 }
 
-void SPIClass::read(uint8 *buf, uint32 len) {
+void SPIClass::read(uint8 *buf, uint32 len)
+{
+	spi_reg_map * regs = _currentSetting->spi_d->regs;
+	uint8 b = (regs->DR); // clear the RX buffer in case a byte is waiting on it.
     uint32 rxed = 0;
-    while (rxed < len) {
-        while (!spi_is_rx_nonempty(_currentSetting->spi_d))
-            ;
-        buf[rxed++] = (uint8)spi_rx_reg(_currentSetting->spi_d);
+	// start sequence
+    while ( rxed < len) {
+		regs->DR = 0x00FF; // " write the data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
+        while ( (regs->SR & SPI_SR_RXNE)==0 ) ; // wait till data is available in the Rx register
+        buf[rxed++] = (uint8)(regs->DR); // read and store the received byte
     }
 }
 
-void SPIClass::write(uint16 data) {
-  //  this->write(&data, 1);
-
+void SPIClass::write(uint16 data)
+{
 	/* Added for 16bit data Victor Perez. Roger Clark 
-	 * Improved speed by just directly writing the single byte to the SPI data reg and wait for completion,	 * by taking the Tx code from transfer(byte)
-	 * The original method, of calling write(*data, length) .
+	 * Improved speed by just directly writing the single byte to the SPI data reg and wait for completion,
+	 * by taking the Tx code from transfer(byte)
 	 * This almost doubles the speed of this function.
 	 */
-  
 	spi_tx_reg(_currentSetting->spi_d, data); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
 }
 
-//void SPIClass::write(uint8 byte) {
-  //  this->write(&byte, 1);
-
-	/* Roger Clark 
-	 * Improved speed by just directly writing the single byte to the SPI data reg and wait for completion,	 * by taking the Tx code from transfer(byte)
-	 * The original method, of calling write(*data, length) .
-	 * This almost doubles the speed of this function.
-	 */
-  
-//	spi_tx_reg(_currentSetting->spi_d, byte); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-//	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
-//	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
-//}
-
-void SPIClass::write(const uint8 *data, uint32 length) {
-    uint32 txed = 0;
-    while (txed < length) {
-        txed += spi_tx(_currentSetting->spi_d, data + txed, length - txed);
-    }
-	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "4. After writing the last data item into the SPI_DR register, wait until TXE=1 ..."
-	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... then wait until BSY=0, this indicates that the transmission of the last data is complete."
+void SPIClass::write(const void *data, uint32 length)
+{
+    spi_tx(_currentSetting->spi_d, data, length); // data can be array of bytes or words
+	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
 	// taken from SdSpiSTM32F1.cpp - Victor's lib, and adapted to support device selection
-	if (spi_is_rx_nonempty(_currentSetting->spi_d)) {
-		uint8_t b = spi_rx_reg(_currentSetting->spi_d);
-	}
+	uint16 b = spi_rx_reg(_currentSetting->spi_d); // dummy read, needed, don't remove!
 }
 
 uint16_t SPIClass::transfer16(uint16_t wr_data) const {
 	spi_tx_reg(_currentSetting->spi_d, wr_data); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-	while (spi_is_rx_nonempty(_currentSetting->spi_d) == 0); // "4. Wait until RXNE=1 ..."
-	uint16_t rd_data = spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
-//	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
-//	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
-	return rd_data;
+	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
+	return (uint16)spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
 }
 
 uint8 SPIClass::transfer(uint8 byte) const {
 	spi_tx_reg(_currentSetting->spi_d, byte); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-  	while (spi_is_rx_nonempty(_currentSetting->spi_d) == 0); // "4. Wait until RXNE=1 ..."
-  	uint8 b = spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
-  	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
-  	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
-    return b;
+	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
+	return (uint8)spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
 }
+
 /*  Roger Clark and Victor Perez, 2015
 *	Performs a DMA SPI transfer with at least a receive buffer.
-*	If a TX buffer is not provided, FF is sent over and over for the lenght of the transfer. 
-*	On exit TX buffer is not modified, and RX buffer cotains the received data.
+*	If a TX buffer is not provided, FF is sent over and over for the length of the transfer. 
+*	On exit TX buffer is not modified, and RX buffer contains the received data.
 *	Still in progress.
 */
-uint8 SPIClass::dmaTransfer(uint8 *transmitBuf, uint8 *receiveBuf, uint16 length) {
+uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length)
+{
 	if (length == 0) return 0;
 	uint8 b = 0;
-	if (spi_is_rx_nonempty(_currentSetting->spi_d) == 1) b = spi_rx_reg(_currentSetting->spi_d); //Clear the RX buffer in case a byte is waiting on it.
+	spi_rx_reg(_currentSetting->spi_d); //Clear the RX buffer in case a byte is waiting on it.
 //	dma1_ch3_Active=true;
     dma_init(_currentSetting->spiDmaDev);
 //	dma_attach_interrupt(DMA1, DMA_CH3, &SPIClass::DMA1_CH3_Event);
-	
+
 	// RX
 	spi_rx_dma_enable(_currentSetting->spi_d);
-	dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &_currentSetting->spi_d->regs->DR, DMA_SIZE_8BITS,
-                     receiveBuf, DMA_SIZE_8BITS, (DMA_MINC_MODE | DMA_TRNS_CMPLT));// receive buffer DMA
+	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_8BIT) ? DMA_SIZE_8BITS : DMA_SIZE_16BITS;
+	dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
+                     receiveBuf, dma_bit_size, (DMA_MINC_MODE | DMA_TRNS_CMPLT));// receive buffer DMA
 	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, length);
-	
+
 	// TX
+	uint32 flags = (DMA_MINC_MODE | DMA_FROM_MEM | DMA_TRNS_CMPLT);
 	spi_tx_dma_enable(_currentSetting->spi_d);	
-	if (!transmitBuf) {
-	static uint8_t ff = 0XFF;
-	transmitBuf = &ff;
-	dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, DMA_SIZE_8BITS,
-                       transmitBuf, DMA_SIZE_8BITS, (DMA_FROM_MEM | DMA_TRNS_CMPLT));// Transmit FF repeatedly
-	}
-	else {
-    dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, DMA_SIZE_8BITS,
-                       transmitBuf, DMA_SIZE_8BITS, (DMA_MINC_MODE |  DMA_FROM_MEM | DMA_TRNS_CMPLT));// Transmit buffer DMA 
+	if ( transmitBuf==0 ) {
+		static uint8_t ff = 0XFF;
+		transmitBuf = &ff;
+		flags ^= DMA_MINC_MODE; // remove increment mode
 	}
+    dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
+                       transmitBuf, dma_bit_size, flags);// Transmit buffer DMA 
 	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
 
 	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);// enable receive
 	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
 	
-//	while (dma1_ch3_Active);
-//	if (receiveBuf) {
     uint32_t m = millis();
 	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & 0x2)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
-      if ((millis() - m) > 100)  {
-//        dma1_ch3_Active = 0;
-		b = 2;
-		break;
-      }
+		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
     }
 	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 
-//	}
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
     dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
 	spi_rx_dma_disable(_currentSetting->spi_d); // And disable generation of DMA request from the SPI port so other peripherals can use the channels
 	spi_tx_dma_disable(_currentSetting->spi_d);
-	if (spi_is_rx_nonempty(_currentSetting->spi_d) != 0){; // "4. Wait until RXNE=1 ..."
-		uint8 x = spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
-	}
+	uint16 x = spi_rx_reg(_currentSetting->spi_d); // dummy read, needed, don't remove!
     return b;
 }
 
@@ -443,10 +417,12 @@ uint8 SPIClass::dmaTransfer(uint8 *transmitBuf, uint8 *receiveBuf, uint16 length
 *	Performs a DMA SPI send using a TX buffer.
 *	On exit TX buffer is not modified.
 *	Still in progress.
+*	2016 - stevstrong - reworked to automatically detect bit size from SPI setting
 */
-uint8 SPIClass::dmaSend(uint8 *transmitBuf, uint16 length, bool minc) {
+uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length)
+{
 	if (length == 0) return 0;
-	uint32 flags = ((DMA_MINC_MODE * minc) |  DMA_FROM_MEM | DMA_TRNS_CMPLT);
+	uint32 flags = (DMA_MINC_MODE | DMA_FROM_MEM | DMA_TRNS_CMPLT);
 	uint8 b = 0;
 //	dma1_ch3_Active=true;
     dma_init(_currentSetting->spiDmaDev);
@@ -454,55 +430,27 @@ uint8 SPIClass::dmaSend(uint8 *transmitBuf, uint16 length, bool minc) {
 
 	// TX
 	spi_tx_dma_enable(_currentSetting->spi_d);	
-    dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, DMA_SIZE_8BITS,
-                       transmitBuf, DMA_SIZE_8BITS, flags);// Transmit buffer DMA 
+	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_8BIT) ? DMA_SIZE_8BITS : DMA_SIZE_16BITS;
+    dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
+                       transmitBuf, dma_bit_size, flags);// Transmit buffer DMA 
 	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
 	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
-	
-//    while (dma1_ch3_Active);
-	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & 0x2)==0); //Avoid interrupts and just loop waiting for the flag to be set.
-	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 
-	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
-	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
-	spi_tx_dma_disable(_currentSetting->spi_d);
-	if (spi_is_rx_nonempty(_currentSetting->spi_d) != 0){; // "4. Wait until RXNE=1 ..."
-		uint8 x = spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
-	}
-    return b;
-}
-
-uint8 SPIClass::dmaSend(uint16 *transmitBuf, uint16 length, bool minc) {
-	if (length == 0) return 0;
-	uint32 flags = ((DMA_MINC_MODE * minc) |  DMA_FROM_MEM | DMA_TRNS_CMPLT);
-	uint8 b;
-	dma1_ch3_Active=true;
-    dma_init(_currentSetting->spiDmaDev);
-//	dma_attach_interrupt(DMA1, DMA_CH3, &SPIClass::DMA1_CH3_Event);
-
-	// TX
-	spi_tx_dma_enable(_currentSetting->spi_d);	
-    dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, DMA_SIZE_16BITS,
-                       transmitBuf, DMA_SIZE_16BITS, flags);// Transmit buffer DMA 
-	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
-	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
-	
 //    while (dma1_ch3_Active);
-	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & 0x2)==0); //Avoid interrupts and just loop waiting for the flag to be set.
+    uint32_t m = millis();
+	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & 0x2)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
+		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
+    }
 	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
 	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 	spi_tx_dma_disable(_currentSetting->spi_d);
-	if (spi_is_rx_nonempty(_currentSetting->spi_d) != 0){; // "4. Wait until RXNE=1 ..."
-		b = spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
-	}
+	uint16 x = spi_rx_reg(_currentSetting->spi_d); // dummy read, needed, don't remove!
     return b;
 }
 
-
 void SPIClass::attachInterrupt(void) {
 	// Should be enableInterrupt()
 }
diff --git a/STM32F1/libraries/SPI/src/SPI.h b/STM32F1/libraries/SPI/src/SPI.h
index e949051e5..0f8497ae1 100644
--- a/STM32F1/libraries/SPI/src/SPI.h
+++ b/STM32F1/libraries/SPI/src/SPI.h
@@ -249,7 +249,7 @@ class SPIClass {
      * @param buffer Bytes to transmit.
      * @param length Number of bytes in buffer to transmit.
      */
-    void write(const uint8 *buffer, uint32 length);
+    void write(const void * buffer, uint32 length);
 
     /**
      * @brief Transmit a byte, then return the next unread byte.
@@ -264,6 +264,7 @@ class SPIClass {
 	
 	/**
      * @brief Sets up a DMA Transfer for "length" bytes.
+	 * The transfer mode (8 or 16 bit mode) is evaluated from the SPI peripheral setting.
      *
      * This function transmits and receives to buffers.
      *
@@ -271,30 +272,18 @@ class SPIClass {
      * @param receiveBuf buffer Bytes to save received data. 
      * @param length Number of bytes in buffer to transmit.
 	 */
-	uint8 dmaTransfer(uint8 *transmitBuf, uint8 *receiveBuf, uint16 length);
+	uint8 dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length);
 
 	/**
-     * @brief Sets up a DMA Transmit for bytes.
+     * @brief Sets up a DMA Transmit for SPI 8 or 16 bit transfer mode.
+	 * The transfer mode (8 or 16 bit mode) is evaluated from the SPI peripheral setting.
      *
-     * This function transmits and does not care about the RX fifo.
-     *
-     * @param transmitBuf buffer Bytes to transmit,
-     * @param length Number of bytes in buffer to transmit.
-	 * @param minc Set to use Memory Increment mode, clear to use Circular mode.
-     */
-	uint8 dmaSend(uint8 *transmitBuf, uint16 length, bool minc = 1);
-	
-	/**
-     * @brief Sets up a DMA Transmit for half words.
-	 * SPI PERFIPHERAL MUST BE SET TO 16 BIT MODE BEFORE
-     *
-     * This function transmits and does not care about the RX fifo.
+     * This function only transmits and does not care about the RX fifo.
      *
      * @param data buffer half words to transmit,
      * @param length Number of bytes in buffer to transmit.
-     * @param minc Set to use Memory Increment mode (default if blank), clear to use Circular mode.
      */
-	uint8 dmaSend(uint16 *transmitBuf, uint16 length, bool minc = 1);
+	uint8 dmaSend(void * transmitBuf, uint16 length);
 
     /*
      * Pin accessors

From 2cdbbc83390b27570c9040fc92bda6e63947f160 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Thu, 10 Nov 2016 11:33:37 +1100
Subject: [PATCH 008/307] Fix issue caused by ADC PR changes that, prevented
 the GD32F103 variant from building

---
 STM32F1/variants/generic_gd32f103c/wirish/boards.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/variants/generic_gd32f103c/wirish/boards.cpp b/STM32F1/variants/generic_gd32f103c/wirish/boards.cpp
index 57d8ca006..fcb85b2ab 100644
--- a/STM32F1/variants/generic_gd32f103c/wirish/boards.cpp
+++ b/STM32F1/variants/generic_gd32f103c/wirish/boards.cpp
@@ -179,7 +179,7 @@ nvic_init((uint32)VECT_TAB_ADDR, 0);
 */
 }
 
-static void adc_default_config(const adc_dev *dev) {
+static void adc_default_config(adc_dev *dev) {
     adc_enable_single_swstart(dev);
     adc_set_sample_rate(dev, wirish::priv::w_adc_smp);
 }

From 8345e6f075b00defb134203cddb5612905fd7ecf Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Thu, 10 Nov 2016 20:06:23 +1100
Subject: [PATCH 009/307] Copied individual files from @stevestong master

---
 .../maple/libmaple/usb/stm32f1/usb_cdcacm.c   | 227 +++++++++++-------
 .../maple/libmaple/usb/stm32f1/usb_reg_map.c  |   8 +-
 STM32F1/cores/maple/usb_serial.cpp            |  41 +---
 STM32F1/cores/maple/usb_serial.h              |   4 +-
 .../system/libmaple/usb/stm32f1/usb_reg_map.h |  10 +-
 5 files changed, 159 insertions(+), 131 deletions(-)

diff --git a/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c b/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c
index 448c05dfc..7a5a772af 100644
--- a/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c
+++ b/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c
@@ -261,18 +261,28 @@ static ONE_DESCRIPTOR String_Descriptor[N_STRING_DESCRIPTORS] = {
 
 /* I/O state */
 
-#define CDC_SERIAL_BUFFER_SIZE	512
+#define CDC_SERIAL_RX_BUFFER_SIZE	256 // must be power of 2
+#define CDC_SERIAL_RX_BUFFER_SIZE_MASK (CDC_SERIAL_RX_BUFFER_SIZE-1)
 
 /* Received data */
-static volatile uint8 vcomBufferRx[CDC_SERIAL_BUFFER_SIZE];
-/* Read index into vcomBufferRx */
-static volatile uint32 rx_offset = 0;
-/* Number of bytes left to transmit */
-static volatile uint32 n_unsent_bytes = 0;
-/* Are we currently sending an IN packet? */
-static volatile uint8 transmitting = 0;
-/* Number of unread bytes */
-static volatile uint32 n_unread_bytes = 0;
+static volatile uint8 vcomBufferRx[CDC_SERIAL_RX_BUFFER_SIZE];
+/* Write index to vcomBufferRx */
+static volatile uint32 rx_head;
+/* Read index from vcomBufferRx */
+static volatile uint32 rx_tail;
+
+#define CDC_SERIAL_TX_BUFFER_SIZE	256 // must be power of 2
+#define CDC_SERIAL_TX_BUFFER_SIZE_MASK (CDC_SERIAL_TX_BUFFER_SIZE-1)
+// Tx data
+static volatile uint8 vcomBufferTx[CDC_SERIAL_TX_BUFFER_SIZE];
+// Write index to vcomBufferTx
+static volatile uint32 tx_head;
+// Read index from vcomBufferTx
+static volatile uint32 tx_tail;
+// Are we currently sending an IN packet?
+static volatile int8 transmitting;
+
+
 
 /* Other state (line coding, DTR/RTS) */
 
@@ -393,30 +403,34 @@ void usb_cdcacm_putc(char ch) {
         ;
 }
 
-/* This function is blocking.
+/* This function is non-blocking.
  *
- * It copies data from a usercode buffer into the USB peripheral TX
+ * It copies data from a user buffer into the USB peripheral TX
  * buffer, and returns the number of bytes copied. */
-uint32 usb_cdcacm_tx(const uint8* buf, uint32 len) {
-    /* Last transmission hasn't finished, so abort. */
-    while ( usb_cdcacm_is_transmitting()>0 ) ; // wait for end of transmission
+uint32 usb_cdcacm_tx(const uint8* buf, uint32 len)
+{
+	if (len==0) return 0; // no data to send
 
-    /* We can only put USB_CDCACM_TX_EPSIZE bytes in the buffer. */
-    if (len > USB_CDCACM_TX_EPSIZE) {
-        len = USB_CDCACM_TX_EPSIZE;
-    }
+	uint32 head = tx_head; // load volatile variable
+	uint32 tx_unsent = (head - tx_tail) & CDC_SERIAL_TX_BUFFER_SIZE_MASK;
 
-    /* Queue bytes for sending. */
-    if (len) {
-        usb_copy_to_pma(buf, len, USB_CDCACM_TX_ADDR);
+    // We can only put bytes in the buffer if there is place
+    if (len > (CDC_SERIAL_TX_BUFFER_SIZE-tx_unsent-1) ) {
+        len = (CDC_SERIAL_TX_BUFFER_SIZE-tx_unsent-1);
     }
-    // We still need to wait for the interrupt, even if we're sending
-    // zero bytes. (Sending zero-size packets is useful for flushing
-    // host-side buffers.)
-    usb_set_ep_tx_count(USB_CDCACM_TX_ENDP, len);
-    n_unsent_bytes = len;
-    transmitting = 1;
-    usb_set_ep_tx_stat(USB_CDCACM_TX_ENDP, USB_EP_STAT_TX_VALID);
+	if (len==0) return 0; // buffer full
+
+	uint16 i;
+	// copy data from user buffer to USB Tx buffer
+	for (i=0; i<len; i++) {
+		vcomBufferTx[head] = buf[i];
+		head = (head+1) & CDC_SERIAL_TX_BUFFER_SIZE_MASK;
+	}
+	tx_head = head; // store volatile variable
+
+	if (transmitting<0) {
+		vcomDataTxCb(); // initiate data transmission
+	}
 
     return len;
 }
@@ -424,69 +438,73 @@ uint32 usb_cdcacm_tx(const uint8* buf, uint32 len) {
 
 
 uint32 usb_cdcacm_data_available(void) {
-    return n_unread_bytes;
+    return (rx_head - rx_tail) & CDC_SERIAL_RX_BUFFER_SIZE_MASK;
 }
 
 uint8 usb_cdcacm_is_transmitting(void) {
-    return transmitting;
+    return ( transmitting>0 ? transmitting : 0);
 }
 
 uint16 usb_cdcacm_get_pending(void) {
-    return n_unsent_bytes;
+    return (tx_head - tx_tail) & CDC_SERIAL_TX_BUFFER_SIZE_MASK;
 }
 
-/* Nonblocking byte receive.
+/* Non-blocking byte receive.
  *
  * Copies up to len bytes from our private data buffer (*NOT* the PMA)
  * into buf and deq's the FIFO. */
-uint32 usb_cdcacm_rx(uint8* buf, uint32 len) {
+uint32 usb_cdcacm_rx(uint8* buf, uint32 len)
+{
     /* Copy bytes to buffer. */
     uint32 n_copied = usb_cdcacm_peek(buf, len);
 
     /* Mark bytes as read. */
-    n_unread_bytes -= n_copied;
-    rx_offset = (rx_offset + n_copied) % CDC_SERIAL_BUFFER_SIZE;
+	uint16 tail = rx_tail; // load volatile variable
+	tail = (tail + n_copied) & CDC_SERIAL_RX_BUFFER_SIZE_MASK;
+	rx_tail = tail; // store volatile variable
 
-    /* If all bytes have been read, re-enable the RX endpoint, which
-     * was set to NAK when the current batch of bytes was received. */
-    if (n_unread_bytes == 0) {
-        usb_set_ep_rx_count(USB_CDCACM_RX_ENDP, USB_CDCACM_RX_EPSIZE);
+	uint32 rx_unread = (rx_head - tail) & CDC_SERIAL_RX_BUFFER_SIZE_MASK;
+    // If buffer was emptied to a pre-set value, re-enable the RX endpoint
+    if ( rx_unread <= 64 ) { // experimental value, gives the best performance
         usb_set_ep_rx_stat(USB_CDCACM_RX_ENDP, USB_EP_STAT_RX_VALID);
-    }
-
+	}
     return n_copied;
 }
 
-/* Nonblocking byte lookahead.
+/* Non-blocking byte lookahead.
  *
  * Looks at unread bytes without marking them as read. */
-uint32 usb_cdcacm_peek(uint8* buf, uint32 len) {
+uint32 usb_cdcacm_peek(uint8* buf, uint32 len)
+{
     int i;
-    uint32 head = rx_offset;
+    uint32 tail = rx_tail;
+	uint32 rx_unread = (rx_head-tail) & CDC_SERIAL_RX_BUFFER_SIZE_MASK;
 
-    if (len > n_unread_bytes) {
-        len = n_unread_bytes;
+    if (len > rx_unread) {
+        len = rx_unread;
     }
 
     for (i = 0; i < len; i++) {
-        buf[i] = vcomBufferRx[head];
-        head = (head + 1) % CDC_SERIAL_BUFFER_SIZE;
+        buf[i] = vcomBufferRx[tail];
+        tail = (tail + 1) & CDC_SERIAL_RX_BUFFER_SIZE_MASK;
     }
 
     return len;
 }
 
-uint32 usb_cdcacm_peek_ex(uint8* buf, uint32 offset, uint32 len) {
+uint32 usb_cdcacm_peek_ex(uint8* buf, uint32 offset, uint32 len)
+{
     int i;
-    uint32 head = (rx_offset + offset) % CDC_SERIAL_BUFFER_SIZE;
+    uint32 tail = (rx_tail + offset) & CDC_SERIAL_RX_BUFFER_SIZE_MASK ;
+	uint32 rx_unread = (rx_head-tail) & CDC_SERIAL_RX_BUFFER_SIZE_MASK;
 
-    if (len + offset > n_unread_bytes) {
-        len = n_unread_bytes - offset;
+    if (len + offset > rx_unread) {
+        len = rx_unread - offset;
     }
 
     for (i = 0; i < len; i++) {
-        buf[i] = vcomBufferRx[head];
-        head = (head + 1) % CDC_SERIAL_BUFFER_SIZE;
+        buf[i] = vcomBufferRx[tail];
+        tail = (tail + 1) & CDC_SERIAL_RX_BUFFER_SIZE_MASK;
     }
 
     return len;
@@ -495,12 +513,12 @@ uint32 usb_cdcacm_peek_ex(uint8* buf, uint32 offset, uint32 len) {
 /* Roger Clark. Added. for Arduino 1.0 API support of Serial.peek() */
 int usb_cdcacm_peek_char() 
 {
-    if (n_unread_bytes == 0) 
+    if (usb_cdcacm_data_available() == 0) 
 	{
 		return -1;
     }
 
-    return vcomBufferRx[rx_offset];
+    return vcomBufferRx[rx_tail];
 }
 
 uint8 usb_cdcacm_get_dtr() {
@@ -534,41 +552,75 @@ int usb_cdcacm_get_n_data_bits(void) {
     return line_coding.bDataBits;
 }
 
-
 /*
  * Callbacks
  */
-
-static void vcomDataTxCb(void) {
-    n_unsent_bytes = 0;
-    transmitting = 0;
+static void vcomDataTxCb(void)
+{
+	uint32 tail = tx_tail; // load volatile variable
+	uint32 tx_unsent = (tx_head - tail) & CDC_SERIAL_TX_BUFFER_SIZE_MASK;
+	if (tx_unsent==0) {
+		if ( (--transmitting)==0) goto flush; // no more data to send
+		return; // it was already flushed, keep Tx endpoint disabled
+	}
+	transmitting = 1;
+    // We can only send up to USB_CDCACM_TX_EPSIZE bytes in the endpoint.
+    if (tx_unsent > USB_CDCACM_TX_EPSIZE) {
+        tx_unsent = USB_CDCACM_TX_EPSIZE;
+    }
+	// copy the bytes from USB Tx buffer to PMA buffer
+	uint32 *dst = usb_pma_ptr(USB_CDCACM_TX_ADDR);
+    uint16 tmp = 0;
+	uint16 val;
+	int i;
+	for (i = 0; i < tx_unsent; i++) {
+		val = vcomBufferTx[tail];
+		tail = (tail + 1) & CDC_SERIAL_TX_BUFFER_SIZE_MASK;
+		if (i&1) {
+			*dst++ = tmp | (val<<8);
+		} else {
+			tmp = val;
+		}
+	}
+    if ( tx_unsent&1 ) {
+        *dst = tmp;
+    }
+	tx_tail = tail; // store volatile variable
+flush:
+	// enable Tx endpoint
+    usb_set_ep_tx_count(USB_CDCACM_TX_ENDP, tx_unsent);
+    usb_set_ep_tx_stat(USB_CDCACM_TX_ENDP, USB_EP_STAT_TX_VALID);
 }
 
-static void vcomDataRxCb(void) {
-	uint32 ep_rx_size;
-	uint32 tail = (rx_offset + n_unread_bytes) % CDC_SERIAL_BUFFER_SIZE;
-	uint8 ep_rx_data[USB_CDCACM_RX_EPSIZE];
-	uint32 i;
-
-    usb_set_ep_rx_stat(USB_CDCACM_RX_ENDP, USB_EP_STAT_RX_NAK);
-    ep_rx_size = usb_get_ep_rx_count(USB_CDCACM_RX_ENDP);
-    /* This copy won't overwrite unread bytes, since we've set the RX
-     * endpoint to NAK, and will only set it to VALID when all bytes
-     * have been read. */
-    usb_copy_from_pma((uint8*)ep_rx_data, ep_rx_size,
-                      USB_CDCACM_RX_ADDR);
 
+static void vcomDataRxCb(void)
+{
+	uint32 head = rx_head; // load volatile variable
+
+	uint32 ep_rx_size = usb_get_ep_rx_count(USB_CDCACM_RX_ENDP);
+	// This copy won't overwrite unread bytes as long as there is 
+	// enough room in the USB Rx buffer for next packet
+	uint32 *src = usb_pma_ptr(USB_CDCACM_RX_ADDR);
+    uint16 tmp = 0;
+	uint8 val;
+	uint32 i;
 	for (i = 0; i < ep_rx_size; i++) {
-		vcomBufferRx[tail] = ep_rx_data[i];
-		tail = (tail + 1) % CDC_SERIAL_BUFFER_SIZE;
+		if (i&1) {
+			val = tmp>>8;
+		} else {
+			tmp = *src++;
+			val = tmp&0xFF;
+		}
+		vcomBufferRx[head] = val;
+		head = (head + 1) & CDC_SERIAL_RX_BUFFER_SIZE_MASK;
 	}
+	rx_head = head; // store volatile variable
 
-	n_unread_bytes += ep_rx_size;
-
-    if ( n_unread_bytes == 0 ) {
-        usb_set_ep_rx_count(USB_CDCACM_RX_ENDP, USB_CDCACM_RX_EPSIZE);
-        usb_set_ep_rx_stat(USB_CDCACM_RX_ENDP, USB_EP_STAT_RX_VALID);
-    }
+	uint32 rx_unread = (head - rx_tail) & CDC_SERIAL_RX_BUFFER_SIZE_MASK;
+	// only enable further Rx if there is enough room to receive one more packet
+	if ( rx_unread < (CDC_SERIAL_RX_BUFFER_SIZE-USB_CDCACM_RX_EPSIZE) ) {
+		usb_set_ep_rx_stat(USB_CDCACM_RX_ENDP, USB_EP_STAT_RX_VALID);
+	}
 
     if (rx_hook) {
         rx_hook(USB_CDCACM_HOOK_RX, 0);
@@ -646,10 +698,11 @@ static void usbReset(void) {
     SetDeviceAddress(0);
 
     /* Reset the RX/TX state */
-    n_unread_bytes = 0;
-    n_unsent_bytes = 0;
-    rx_offset = 0;
-    transmitting = 0;
+	rx_head = 0;
+	rx_tail = 0;
+	tx_head = 0;
+	tx_tail = 0;
+    transmitting = -1;
 }
 
 static RESULT usbDataSetup(uint8 request) {
diff --git a/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_reg_map.c b/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_reg_map.c
index ea60cb3c2..3f5446aa6 100644
--- a/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_reg_map.c
+++ b/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_reg_map.c
@@ -29,7 +29,7 @@
 /* TODO these could use some improvement; they're fairly
  * straightforward ports of the analogous ST code.  The PMA blit
  * routines in particular are obvious targets for performance
- * measurement and tuning. */
+ * measurement and tuning.
 
 void usb_copy_to_pma(const uint8 *buf, uint16 len, uint16 pma_offset) {
     uint16 *dst = (uint16*)usb_pma_ptr(pma_offset);
@@ -57,7 +57,7 @@ void usb_copy_from_pma(uint8 *buf, uint16 len, uint16 pma_offset) {
         *dst = *src & 0xFF;
     }
 }
-
+ */
 static void usb_set_ep_rx_count_common(uint32 *rxc, uint16 count) {
     uint16 nblocks;
     if (count > 62) {
@@ -76,12 +76,12 @@ static void usb_set_ep_rx_count_common(uint32 *rxc, uint16 count) {
         *rxc = nblocks << 10;
     }
 }
-
+/*
 void usb_set_ep_rx_buf0_count(uint8 ep, uint16 count) {
     uint32 *rxc = usb_ep_rx_buf0_count_ptr(ep);
     usb_set_ep_rx_count_common(rxc, count);
 }
-
+*/
 void usb_set_ep_rx_count(uint8 ep, uint16 count) {
     uint32 *rxc = usb_ep_rx_count_ptr(ep);
     usb_set_ep_rx_count_common(rxc, count);
diff --git a/STM32F1/cores/maple/usb_serial.cpp b/STM32F1/cores/maple/usb_serial.cpp
index ab8816bce..5eaf70efb 100644
--- a/STM32F1/cores/maple/usb_serial.cpp
+++ b/STM32F1/cores/maple/usb_serial.cpp
@@ -100,44 +100,23 @@ size_t n = 0;
 
 size_t USBSerial::write(const char *str) {
 size_t n = 0;
-    this->write(str, strlen(str));
+    this->write((const uint8*)str, strlen(str));
 	return n;
 }
 
-size_t USBSerial::write(const void *buf, uint32 len) {
+size_t USBSerial::write(const uint8 *buf, uint32 len)
+{
 size_t n = 0;
     if (!this->isConnected() || !buf) {
         return 0;
     }
 
     uint32 txed = 0;
-    uint32 old_txed = 0;
-    uint32 start = millis();
-
-    uint32 sent = 0;
-
-    while (txed < len && (millis() - start < USB_TIMEOUT)) {
-        sent = usb_cdcacm_tx((const uint8*)buf + txed, len - txed);
-        txed += sent;
-        if (old_txed != txed) {
-            start = millis();
-        }
-        old_txed = txed;
+    while (txed < len) {
+        txed += usb_cdcacm_tx((const uint8*)buf + txed, len - txed);
     }
 
-
-#if 0
-// this code leads to a serious performance drop and appears to be
-// unnecessary - everything seems to work fine without, -jcw, 2015-11-05
-// see http://stm32duino.com/posting.php?mode=quote&f=3&p=7746
-	if (sent == USB_CDCACM_TX_EPSIZE) {
-	while (usb_cdcacm_is_transmitting() != 0) {
-	}
-	/* flush out to avoid having the pc wait for more data */
-	usb_cdcacm_tx(NULL, 0);
-	}
-#endif
-		return n;
+	return n;
 }
 
 int USBSerial::available(void) {
@@ -168,14 +147,10 @@ void USBSerial::flush(void)
     return;
 }
 
-uint32 USBSerial::read(void *buf, uint32 len) {
-    if (!buf) {
-        return 0;
-    }
-
+uint32 USBSerial::read(uint8 * buf, uint32 len) {
     uint32 rxed = 0;
     while (rxed < len) {
-        rxed += usb_cdcacm_rx((uint8*)buf + rxed, len - rxed);
+        rxed += usb_cdcacm_rx(buf + rxed, len - rxed);
     }
 
     return rxed;
diff --git a/STM32F1/cores/maple/usb_serial.h b/STM32F1/cores/maple/usb_serial.h
index 740ab0fd9..96bbefc25 100644
--- a/STM32F1/cores/maple/usb_serial.h
+++ b/STM32F1/cores/maple/usb_serial.h
@@ -53,7 +53,7 @@ class USBSerial : public Stream {
 
     virtual int available(void);// Changed to virtual
 
-    uint32 read(void *buf, uint32 len);
+    uint32 read(uint8 * buf, uint32 len);
    // uint8  read(void);
 
 	// Roger Clark. added functions to support Arduino 1.0 API
@@ -65,7 +65,7 @@ class USBSerial : public Stream {
 	
     size_t write(uint8);
     size_t write(const char *str);
-    size_t write(const void*, uint32);
+    size_t write(const uint8*, uint32);
 
     uint8 getRTS();
     uint8 getDTR();
diff --git a/STM32F1/system/libmaple/usb/stm32f1/usb_reg_map.h b/STM32F1/system/libmaple/usb/stm32f1/usb_reg_map.h
index 6683264f8..d0423fc11 100644
--- a/STM32F1/system/libmaple/usb/stm32f1/usb_reg_map.h
+++ b/STM32F1/system/libmaple/usb/stm32f1/usb_reg_map.h
@@ -345,12 +345,12 @@ static inline void usb_clear_status_out(uint8 ep) {
 /*
  * PMA conveniences
  */
-
+/*
 void usb_copy_to_pma(const uint8 *buf, uint16 len, uint16 pma_offset);
 void usb_copy_from_pma(uint8 *buf, uint16 len, uint16 pma_offset);
-
-static inline void* usb_pma_ptr(uint32 offset) {
-    return (void*)(USB_PMA_BASE + 2 * offset);
+*/
+static inline uint32 * usb_pma_ptr(uint32 offset) {
+    return (uint32*)(USB_PMA_BASE + 2 * offset);
 }
 
 /*
@@ -567,7 +567,7 @@ static inline uint16 usb_get_ep_rx_buf0_count(uint8 ep) {
     return usb_get_ep_tx_count(ep);
 }
 
-void usb_set_ep_rx_buf0_count(uint8 ep, uint16 count);
+//void usb_set_ep_rx_buf0_count(uint8 ep, uint16 count);
 
 static inline uint32* usb_ep_rx_buf1_count_ptr(uint8 ep) {
     return usb_ep_rx_count_ptr(ep);

From 3469ef291baad000b3c64564623d7a09e1312356 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Fri, 11 Nov 2016 22:04:16 +0100
Subject: [PATCH 010/307] Revert "improve SPI low level functions"

This reverts commit 5db25232840ec8f0922a79e3a1a19a86f5397207.
---
 STM32F1/cores/maple/libmaple/spi.c |   6 +-
 STM32F1/libraries/SPI/src/SPI.cpp  | 178 +++++++++++++++++++----------
 STM32F1/libraries/SPI/src/SPI.h    |  25 ++--
 3 files changed, 135 insertions(+), 74 deletions(-)

diff --git a/STM32F1/cores/maple/libmaple/spi.c b/STM32F1/cores/maple/libmaple/spi.c
index 64f06d301..1020c5baf 100644
--- a/STM32F1/cores/maple/libmaple/spi.c
+++ b/STM32F1/cores/maple/libmaple/spi.c
@@ -84,7 +84,7 @@ void spi_slave_enable(spi_dev *dev, spi_mode mode, uint32 flags) {
 }
 
 /**
- * @brief Blocking SPI transmit.
+ * @brief Nonblocking SPI transmit.
  * @param dev SPI port to use for transmission
  * @param buf Buffer to transmit.  The sizeof buf's elements are
  *            inferred from dev's data frame format (i.e., are
@@ -95,8 +95,7 @@ void spi_slave_enable(spi_dev *dev, spi_mode mode, uint32 flags) {
 uint32 spi_tx(spi_dev *dev, const void *buf, uint32 len) {
     uint32 txed = 0;
     uint8 byte_frame = spi_dff(dev) == SPI_DFF_8_BIT;
-    while ( txed < len ) {
-		while ( spi_is_tx_empty(dev)==0 ); // wait Tx to be empty
+    while (spi_is_tx_empty(dev) && (txed < len)) {
         if (byte_frame) {
             dev->regs->DR = ((const uint8*)buf)[txed++];
         } else {
@@ -163,6 +162,5 @@ static void spi_reconfigure(spi_dev *dev, uint32 cr1_config) {
 	spi_irq_disable(dev, SPI_INTERRUPTS_ALL);
 	if ( (dev->regs->CR1&MASK)!=(cr1_config&MASK) )	spi_peripheral_disable(dev);
 	dev->regs->CR1 = cr1_config;
-	//spi_rx_dma_enable(dev);
 	spi_peripheral_enable(dev);
 }
diff --git a/STM32F1/libraries/SPI/src/SPI.cpp b/STM32F1/libraries/SPI/src/SPI.cpp
index 08327912f..4eeec3811 100644
--- a/STM32F1/libraries/SPI/src/SPI.cpp
+++ b/STM32F1/libraries/SPI/src/SPI.cpp
@@ -41,8 +41,6 @@
 #include "boards.h"
 
 //#include "HardwareSerial.h"
-/** Time in ms for DMA receive timeout */
-#define DMA_TIMEOUT 100
 
 #if CYCLES_PER_MICROSECOND != 72
 /* TODO [0.2.0?] something smarter than this */
@@ -306,110 +304,138 @@ void SPIClass::endTransaction(void)
  * I/O
  */
 
-uint8 SPIClass::read(void)
-{
-	while ( spi_is_rx_nonempty(_currentSetting->spi_d)==0 ) ;
-	return (uint8)spi_rx_reg(_currentSetting->spi_d);
+uint8 SPIClass::read(void) {
+    uint8 buf[1];
+    this->read(buf, 1);
+    return buf[0];
 }
 
-void SPIClass::read(uint8 *buf, uint32 len)
-{
-	spi_reg_map * regs = _currentSetting->spi_d->regs;
-	uint8 b = (regs->DR); // clear the RX buffer in case a byte is waiting on it.
+void SPIClass::read(uint8 *buf, uint32 len) {
     uint32 rxed = 0;
-	// start sequence
-    while ( rxed < len) {
-		regs->DR = 0x00FF; // " write the data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-        while ( (regs->SR & SPI_SR_RXNE)==0 ) ; // wait till data is available in the Rx register
-        buf[rxed++] = (uint8)(regs->DR); // read and store the received byte
+    while (rxed < len) {
+        while (!spi_is_rx_nonempty(_currentSetting->spi_d))
+            ;
+        buf[rxed++] = (uint8)spi_rx_reg(_currentSetting->spi_d);
     }
 }
 
-void SPIClass::write(uint16 data)
-{
+void SPIClass::write(uint16 data) {
+  //  this->write(&data, 1);
+
 	/* Added for 16bit data Victor Perez. Roger Clark 
-	 * Improved speed by just directly writing the single byte to the SPI data reg and wait for completion,
-	 * by taking the Tx code from transfer(byte)
+	 * Improved speed by just directly writing the single byte to the SPI data reg and wait for completion,	 * by taking the Tx code from transfer(byte)
+	 * The original method, of calling write(*data, length) .
 	 * This almost doubles the speed of this function.
 	 */
+  
 	spi_tx_reg(_currentSetting->spi_d, data); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
 }
 
-void SPIClass::write(const void *data, uint32 length)
-{
-    spi_tx(_currentSetting->spi_d, data, length); // data can be array of bytes or words
-	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
+//void SPIClass::write(uint8 byte) {
+  //  this->write(&byte, 1);
+
+	/* Roger Clark 
+	 * Improved speed by just directly writing the single byte to the SPI data reg and wait for completion,	 * by taking the Tx code from transfer(byte)
+	 * The original method, of calling write(*data, length) .
+	 * This almost doubles the speed of this function.
+	 */
+  
+//	spi_tx_reg(_currentSetting->spi_d, byte); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
+//	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+//	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
+//}
+
+void SPIClass::write(const uint8 *data, uint32 length) {
+    uint32 txed = 0;
+    while (txed < length) {
+        txed += spi_tx(_currentSetting->spi_d, data + txed, length - txed);
+    }
+	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "4. After writing the last data item into the SPI_DR register, wait until TXE=1 ..."
+	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... then wait until BSY=0, this indicates that the transmission of the last data is complete."
 	// taken from SdSpiSTM32F1.cpp - Victor's lib, and adapted to support device selection
-	uint16 b = spi_rx_reg(_currentSetting->spi_d); // dummy read, needed, don't remove!
+	if (spi_is_rx_nonempty(_currentSetting->spi_d)) {
+		uint8_t b = spi_rx_reg(_currentSetting->spi_d);
+	}
 }
 
 uint16_t SPIClass::transfer16(uint16_t wr_data) const {
 	spi_tx_reg(_currentSetting->spi_d, wr_data); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
-	return (uint16)spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
+	while (spi_is_rx_nonempty(_currentSetting->spi_d) == 0); // "4. Wait until RXNE=1 ..."
+	uint16_t rd_data = spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
+//	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+//	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
+	return rd_data;
 }
 
 uint8 SPIClass::transfer(uint8 byte) const {
 	spi_tx_reg(_currentSetting->spi_d, byte); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
-	return (uint8)spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
+  	while (spi_is_rx_nonempty(_currentSetting->spi_d) == 0); // "4. Wait until RXNE=1 ..."
+  	uint8 b = spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
+  	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+  	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
+    return b;
 }
-
 /*  Roger Clark and Victor Perez, 2015
 *	Performs a DMA SPI transfer with at least a receive buffer.
-*	If a TX buffer is not provided, FF is sent over and over for the length of the transfer. 
-*	On exit TX buffer is not modified, and RX buffer contains the received data.
+*	If a TX buffer is not provided, FF is sent over and over for the lenght of the transfer. 
+*	On exit TX buffer is not modified, and RX buffer cotains the received data.
 *	Still in progress.
 */
-uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length)
-{
+uint8 SPIClass::dmaTransfer(uint8 *transmitBuf, uint8 *receiveBuf, uint16 length) {
 	if (length == 0) return 0;
 	uint8 b = 0;
-	spi_rx_reg(_currentSetting->spi_d); //Clear the RX buffer in case a byte is waiting on it.
+	if (spi_is_rx_nonempty(_currentSetting->spi_d) == 1) b = spi_rx_reg(_currentSetting->spi_d); //Clear the RX buffer in case a byte is waiting on it.
 //	dma1_ch3_Active=true;
     dma_init(_currentSetting->spiDmaDev);
 //	dma_attach_interrupt(DMA1, DMA_CH3, &SPIClass::DMA1_CH3_Event);
-
+	
 	// RX
 	spi_rx_dma_enable(_currentSetting->spi_d);
-	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_8BIT) ? DMA_SIZE_8BITS : DMA_SIZE_16BITS;
-	dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
-                     receiveBuf, dma_bit_size, (DMA_MINC_MODE | DMA_TRNS_CMPLT));// receive buffer DMA
+	dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &_currentSetting->spi_d->regs->DR, DMA_SIZE_8BITS,
+                     receiveBuf, DMA_SIZE_8BITS, (DMA_MINC_MODE | DMA_TRNS_CMPLT));// receive buffer DMA
 	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, length);
-
+	
 	// TX
-	uint32 flags = (DMA_MINC_MODE | DMA_FROM_MEM | DMA_TRNS_CMPLT);
 	spi_tx_dma_enable(_currentSetting->spi_d);	
-	if ( transmitBuf==0 ) {
-		static uint8_t ff = 0XFF;
-		transmitBuf = &ff;
-		flags ^= DMA_MINC_MODE; // remove increment mode
+	if (!transmitBuf) {
+	static uint8_t ff = 0XFF;
+	transmitBuf = &ff;
+	dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, DMA_SIZE_8BITS,
+                       transmitBuf, DMA_SIZE_8BITS, (DMA_FROM_MEM | DMA_TRNS_CMPLT));// Transmit FF repeatedly
+	}
+	else {
+    dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, DMA_SIZE_8BITS,
+                       transmitBuf, DMA_SIZE_8BITS, (DMA_MINC_MODE |  DMA_FROM_MEM | DMA_TRNS_CMPLT));// Transmit buffer DMA 
 	}
-    dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
-                       transmitBuf, dma_bit_size, flags);// Transmit buffer DMA 
 	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
 
 	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);// enable receive
 	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
 	
+//	while (dma1_ch3_Active);
+//	if (receiveBuf) {
     uint32_t m = millis();
 	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & 0x2)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
-		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
+      if ((millis() - m) > 100)  {
+//        dma1_ch3_Active = 0;
+		b = 2;
+		break;
+      }
     }
 	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 
+//	}
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
     dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
 	spi_rx_dma_disable(_currentSetting->spi_d); // And disable generation of DMA request from the SPI port so other peripherals can use the channels
 	spi_tx_dma_disable(_currentSetting->spi_d);
-	uint16 x = spi_rx_reg(_currentSetting->spi_d); // dummy read, needed, don't remove!
+	if (spi_is_rx_nonempty(_currentSetting->spi_d) != 0){; // "4. Wait until RXNE=1 ..."
+		uint8 x = spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
+	}
     return b;
 }
 
@@ -417,12 +443,10 @@ uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length
 *	Performs a DMA SPI send using a TX buffer.
 *	On exit TX buffer is not modified.
 *	Still in progress.
-*	2016 - stevstrong - reworked to automatically detect bit size from SPI setting
 */
-uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length)
-{
+uint8 SPIClass::dmaSend(uint8 *transmitBuf, uint16 length, bool minc) {
 	if (length == 0) return 0;
-	uint32 flags = (DMA_MINC_MODE | DMA_FROM_MEM | DMA_TRNS_CMPLT);
+	uint32 flags = ((DMA_MINC_MODE * minc) |  DMA_FROM_MEM | DMA_TRNS_CMPLT);
 	uint8 b = 0;
 //	dma1_ch3_Active=true;
     dma_init(_currentSetting->spiDmaDev);
@@ -430,27 +454,55 @@ uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length)
 
 	// TX
 	spi_tx_dma_enable(_currentSetting->spi_d);	
-	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_8BIT) ? DMA_SIZE_8BITS : DMA_SIZE_16BITS;
-    dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
-                       transmitBuf, dma_bit_size, flags);// Transmit buffer DMA 
+    dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, DMA_SIZE_8BITS,
+                       transmitBuf, DMA_SIZE_8BITS, flags);// Transmit buffer DMA 
 	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
 	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
+	
+//    while (dma1_ch3_Active);
+	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & 0x2)==0); //Avoid interrupts and just loop waiting for the flag to be set.
+	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 
+	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
+	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+	spi_tx_dma_disable(_currentSetting->spi_d);
+	if (spi_is_rx_nonempty(_currentSetting->spi_d) != 0){; // "4. Wait until RXNE=1 ..."
+		uint8 x = spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
+	}
+    return b;
+}
+
+uint8 SPIClass::dmaSend(uint16 *transmitBuf, uint16 length, bool minc) {
+	if (length == 0) return 0;
+	uint32 flags = ((DMA_MINC_MODE * minc) |  DMA_FROM_MEM | DMA_TRNS_CMPLT);
+	uint8 b;
+	dma1_ch3_Active=true;
+    dma_init(_currentSetting->spiDmaDev);
+//	dma_attach_interrupt(DMA1, DMA_CH3, &SPIClass::DMA1_CH3_Event);
+
+	// TX
+	spi_tx_dma_enable(_currentSetting->spi_d);	
+    dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, DMA_SIZE_16BITS,
+                       transmitBuf, DMA_SIZE_16BITS, flags);// Transmit buffer DMA 
+	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
+	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
+	
 //    while (dma1_ch3_Active);
-    uint32_t m = millis();
-	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & 0x2)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
-		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
-    }
+	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & 0x2)==0); //Avoid interrupts and just loop waiting for the flag to be set.
 	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
 	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 	spi_tx_dma_disable(_currentSetting->spi_d);
-	uint16 x = spi_rx_reg(_currentSetting->spi_d); // dummy read, needed, don't remove!
+	if (spi_is_rx_nonempty(_currentSetting->spi_d) != 0){; // "4. Wait until RXNE=1 ..."
+		b = spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
+	}
     return b;
 }
 
+
 void SPIClass::attachInterrupt(void) {
 	// Should be enableInterrupt()
 }
diff --git a/STM32F1/libraries/SPI/src/SPI.h b/STM32F1/libraries/SPI/src/SPI.h
index 0f8497ae1..e949051e5 100644
--- a/STM32F1/libraries/SPI/src/SPI.h
+++ b/STM32F1/libraries/SPI/src/SPI.h
@@ -249,7 +249,7 @@ class SPIClass {
      * @param buffer Bytes to transmit.
      * @param length Number of bytes in buffer to transmit.
      */
-    void write(const void * buffer, uint32 length);
+    void write(const uint8 *buffer, uint32 length);
 
     /**
      * @brief Transmit a byte, then return the next unread byte.
@@ -264,7 +264,6 @@ class SPIClass {
 	
 	/**
      * @brief Sets up a DMA Transfer for "length" bytes.
-	 * The transfer mode (8 or 16 bit mode) is evaluated from the SPI peripheral setting.
      *
      * This function transmits and receives to buffers.
      *
@@ -272,18 +271,30 @@ class SPIClass {
      * @param receiveBuf buffer Bytes to save received data. 
      * @param length Number of bytes in buffer to transmit.
 	 */
-	uint8 dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length);
+	uint8 dmaTransfer(uint8 *transmitBuf, uint8 *receiveBuf, uint16 length);
 
 	/**
-     * @brief Sets up a DMA Transmit for SPI 8 or 16 bit transfer mode.
-	 * The transfer mode (8 or 16 bit mode) is evaluated from the SPI peripheral setting.
+     * @brief Sets up a DMA Transmit for bytes.
      *
-     * This function only transmits and does not care about the RX fifo.
+     * This function transmits and does not care about the RX fifo.
+     *
+     * @param transmitBuf buffer Bytes to transmit,
+     * @param length Number of bytes in buffer to transmit.
+	 * @param minc Set to use Memory Increment mode, clear to use Circular mode.
+     */
+	uint8 dmaSend(uint8 *transmitBuf, uint16 length, bool minc = 1);
+	
+	/**
+     * @brief Sets up a DMA Transmit for half words.
+	 * SPI PERFIPHERAL MUST BE SET TO 16 BIT MODE BEFORE
+     *
+     * This function transmits and does not care about the RX fifo.
      *
      * @param data buffer half words to transmit,
      * @param length Number of bytes in buffer to transmit.
+     * @param minc Set to use Memory Increment mode (default if blank), clear to use Circular mode.
      */
-	uint8 dmaSend(void * transmitBuf, uint16 length);
+	uint8 dmaSend(uint16 *transmitBuf, uint16 length, bool minc = 1);
 
     /*
      * Pin accessors

From b2e349ca36d245869111db0502123b08c318f5e7 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Fri, 11 Nov 2016 22:12:13 +0100
Subject: [PATCH 011/307] Revert "Revert "improve SPI low level functions""

This reverts commit 3469ef291baad000b3c64564623d7a09e1312356.
---
 STM32F1/cores/maple/libmaple/spi.c |   6 +-
 STM32F1/libraries/SPI/src/SPI.cpp  | 178 ++++++++++-------------------
 STM32F1/libraries/SPI/src/SPI.h    |  25 ++--
 3 files changed, 74 insertions(+), 135 deletions(-)

diff --git a/STM32F1/cores/maple/libmaple/spi.c b/STM32F1/cores/maple/libmaple/spi.c
index 1020c5baf..64f06d301 100644
--- a/STM32F1/cores/maple/libmaple/spi.c
+++ b/STM32F1/cores/maple/libmaple/spi.c
@@ -84,7 +84,7 @@ void spi_slave_enable(spi_dev *dev, spi_mode mode, uint32 flags) {
 }
 
 /**
- * @brief Nonblocking SPI transmit.
+ * @brief Blocking SPI transmit.
  * @param dev SPI port to use for transmission
  * @param buf Buffer to transmit.  The sizeof buf's elements are
  *            inferred from dev's data frame format (i.e., are
@@ -95,7 +95,8 @@ void spi_slave_enable(spi_dev *dev, spi_mode mode, uint32 flags) {
 uint32 spi_tx(spi_dev *dev, const void *buf, uint32 len) {
     uint32 txed = 0;
     uint8 byte_frame = spi_dff(dev) == SPI_DFF_8_BIT;
-    while (spi_is_tx_empty(dev) && (txed < len)) {
+    while ( txed < len ) {
+		while ( spi_is_tx_empty(dev)==0 ); // wait Tx to be empty
         if (byte_frame) {
             dev->regs->DR = ((const uint8*)buf)[txed++];
         } else {
@@ -162,5 +163,6 @@ static void spi_reconfigure(spi_dev *dev, uint32 cr1_config) {
 	spi_irq_disable(dev, SPI_INTERRUPTS_ALL);
 	if ( (dev->regs->CR1&MASK)!=(cr1_config&MASK) )	spi_peripheral_disable(dev);
 	dev->regs->CR1 = cr1_config;
+	//spi_rx_dma_enable(dev);
 	spi_peripheral_enable(dev);
 }
diff --git a/STM32F1/libraries/SPI/src/SPI.cpp b/STM32F1/libraries/SPI/src/SPI.cpp
index 4eeec3811..08327912f 100644
--- a/STM32F1/libraries/SPI/src/SPI.cpp
+++ b/STM32F1/libraries/SPI/src/SPI.cpp
@@ -41,6 +41,8 @@
 #include "boards.h"
 
 //#include "HardwareSerial.h"
+/** Time in ms for DMA receive timeout */
+#define DMA_TIMEOUT 100
 
 #if CYCLES_PER_MICROSECOND != 72
 /* TODO [0.2.0?] something smarter than this */
@@ -304,138 +306,110 @@ void SPIClass::endTransaction(void)
  * I/O
  */
 
-uint8 SPIClass::read(void) {
-    uint8 buf[1];
-    this->read(buf, 1);
-    return buf[0];
+uint8 SPIClass::read(void)
+{
+	while ( spi_is_rx_nonempty(_currentSetting->spi_d)==0 ) ;
+	return (uint8)spi_rx_reg(_currentSetting->spi_d);
 }
 
-void SPIClass::read(uint8 *buf, uint32 len) {
+void SPIClass::read(uint8 *buf, uint32 len)
+{
+	spi_reg_map * regs = _currentSetting->spi_d->regs;
+	uint8 b = (regs->DR); // clear the RX buffer in case a byte is waiting on it.
     uint32 rxed = 0;
-    while (rxed < len) {
-        while (!spi_is_rx_nonempty(_currentSetting->spi_d))
-            ;
-        buf[rxed++] = (uint8)spi_rx_reg(_currentSetting->spi_d);
+	// start sequence
+    while ( rxed < len) {
+		regs->DR = 0x00FF; // " write the data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
+        while ( (regs->SR & SPI_SR_RXNE)==0 ) ; // wait till data is available in the Rx register
+        buf[rxed++] = (uint8)(regs->DR); // read and store the received byte
     }
 }
 
-void SPIClass::write(uint16 data) {
-  //  this->write(&data, 1);
-
+void SPIClass::write(uint16 data)
+{
 	/* Added for 16bit data Victor Perez. Roger Clark 
-	 * Improved speed by just directly writing the single byte to the SPI data reg and wait for completion,	 * by taking the Tx code from transfer(byte)
-	 * The original method, of calling write(*data, length) .
+	 * Improved speed by just directly writing the single byte to the SPI data reg and wait for completion,
+	 * by taking the Tx code from transfer(byte)
 	 * This almost doubles the speed of this function.
 	 */
-  
 	spi_tx_reg(_currentSetting->spi_d, data); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
 }
 
-//void SPIClass::write(uint8 byte) {
-  //  this->write(&byte, 1);
-
-	/* Roger Clark 
-	 * Improved speed by just directly writing the single byte to the SPI data reg and wait for completion,	 * by taking the Tx code from transfer(byte)
-	 * The original method, of calling write(*data, length) .
-	 * This almost doubles the speed of this function.
-	 */
-  
-//	spi_tx_reg(_currentSetting->spi_d, byte); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-//	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
-//	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
-//}
-
-void SPIClass::write(const uint8 *data, uint32 length) {
-    uint32 txed = 0;
-    while (txed < length) {
-        txed += spi_tx(_currentSetting->spi_d, data + txed, length - txed);
-    }
-	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "4. After writing the last data item into the SPI_DR register, wait until TXE=1 ..."
-	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... then wait until BSY=0, this indicates that the transmission of the last data is complete."
+void SPIClass::write(const void *data, uint32 length)
+{
+    spi_tx(_currentSetting->spi_d, data, length); // data can be array of bytes or words
+	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
 	// taken from SdSpiSTM32F1.cpp - Victor's lib, and adapted to support device selection
-	if (spi_is_rx_nonempty(_currentSetting->spi_d)) {
-		uint8_t b = spi_rx_reg(_currentSetting->spi_d);
-	}
+	uint16 b = spi_rx_reg(_currentSetting->spi_d); // dummy read, needed, don't remove!
 }
 
 uint16_t SPIClass::transfer16(uint16_t wr_data) const {
 	spi_tx_reg(_currentSetting->spi_d, wr_data); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-	while (spi_is_rx_nonempty(_currentSetting->spi_d) == 0); // "4. Wait until RXNE=1 ..."
-	uint16_t rd_data = spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
-//	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
-//	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
-	return rd_data;
+	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
+	return (uint16)spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
 }
 
 uint8 SPIClass::transfer(uint8 byte) const {
 	spi_tx_reg(_currentSetting->spi_d, byte); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-  	while (spi_is_rx_nonempty(_currentSetting->spi_d) == 0); // "4. Wait until RXNE=1 ..."
-  	uint8 b = spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
-  	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
-  	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
-    return b;
+	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
+	return (uint8)spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
 }
+
 /*  Roger Clark and Victor Perez, 2015
 *	Performs a DMA SPI transfer with at least a receive buffer.
-*	If a TX buffer is not provided, FF is sent over and over for the lenght of the transfer. 
-*	On exit TX buffer is not modified, and RX buffer cotains the received data.
+*	If a TX buffer is not provided, FF is sent over and over for the length of the transfer. 
+*	On exit TX buffer is not modified, and RX buffer contains the received data.
 *	Still in progress.
 */
-uint8 SPIClass::dmaTransfer(uint8 *transmitBuf, uint8 *receiveBuf, uint16 length) {
+uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length)
+{
 	if (length == 0) return 0;
 	uint8 b = 0;
-	if (spi_is_rx_nonempty(_currentSetting->spi_d) == 1) b = spi_rx_reg(_currentSetting->spi_d); //Clear the RX buffer in case a byte is waiting on it.
+	spi_rx_reg(_currentSetting->spi_d); //Clear the RX buffer in case a byte is waiting on it.
 //	dma1_ch3_Active=true;
     dma_init(_currentSetting->spiDmaDev);
 //	dma_attach_interrupt(DMA1, DMA_CH3, &SPIClass::DMA1_CH3_Event);
-	
+
 	// RX
 	spi_rx_dma_enable(_currentSetting->spi_d);
-	dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &_currentSetting->spi_d->regs->DR, DMA_SIZE_8BITS,
-                     receiveBuf, DMA_SIZE_8BITS, (DMA_MINC_MODE | DMA_TRNS_CMPLT));// receive buffer DMA
+	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_8BIT) ? DMA_SIZE_8BITS : DMA_SIZE_16BITS;
+	dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
+                     receiveBuf, dma_bit_size, (DMA_MINC_MODE | DMA_TRNS_CMPLT));// receive buffer DMA
 	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, length);
-	
+
 	// TX
+	uint32 flags = (DMA_MINC_MODE | DMA_FROM_MEM | DMA_TRNS_CMPLT);
 	spi_tx_dma_enable(_currentSetting->spi_d);	
-	if (!transmitBuf) {
-	static uint8_t ff = 0XFF;
-	transmitBuf = &ff;
-	dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, DMA_SIZE_8BITS,
-                       transmitBuf, DMA_SIZE_8BITS, (DMA_FROM_MEM | DMA_TRNS_CMPLT));// Transmit FF repeatedly
-	}
-	else {
-    dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, DMA_SIZE_8BITS,
-                       transmitBuf, DMA_SIZE_8BITS, (DMA_MINC_MODE |  DMA_FROM_MEM | DMA_TRNS_CMPLT));// Transmit buffer DMA 
+	if ( transmitBuf==0 ) {
+		static uint8_t ff = 0XFF;
+		transmitBuf = &ff;
+		flags ^= DMA_MINC_MODE; // remove increment mode
 	}
+    dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
+                       transmitBuf, dma_bit_size, flags);// Transmit buffer DMA 
 	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
 
 	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);// enable receive
 	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
 	
-//	while (dma1_ch3_Active);
-//	if (receiveBuf) {
     uint32_t m = millis();
 	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & 0x2)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
-      if ((millis() - m) > 100)  {
-//        dma1_ch3_Active = 0;
-		b = 2;
-		break;
-      }
+		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
     }
 	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 
-//	}
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
     dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
 	spi_rx_dma_disable(_currentSetting->spi_d); // And disable generation of DMA request from the SPI port so other peripherals can use the channels
 	spi_tx_dma_disable(_currentSetting->spi_d);
-	if (spi_is_rx_nonempty(_currentSetting->spi_d) != 0){; // "4. Wait until RXNE=1 ..."
-		uint8 x = spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
-	}
+	uint16 x = spi_rx_reg(_currentSetting->spi_d); // dummy read, needed, don't remove!
     return b;
 }
 
@@ -443,10 +417,12 @@ uint8 SPIClass::dmaTransfer(uint8 *transmitBuf, uint8 *receiveBuf, uint16 length
 *	Performs a DMA SPI send using a TX buffer.
 *	On exit TX buffer is not modified.
 *	Still in progress.
+*	2016 - stevstrong - reworked to automatically detect bit size from SPI setting
 */
-uint8 SPIClass::dmaSend(uint8 *transmitBuf, uint16 length, bool minc) {
+uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length)
+{
 	if (length == 0) return 0;
-	uint32 flags = ((DMA_MINC_MODE * minc) |  DMA_FROM_MEM | DMA_TRNS_CMPLT);
+	uint32 flags = (DMA_MINC_MODE | DMA_FROM_MEM | DMA_TRNS_CMPLT);
 	uint8 b = 0;
 //	dma1_ch3_Active=true;
     dma_init(_currentSetting->spiDmaDev);
@@ -454,55 +430,27 @@ uint8 SPIClass::dmaSend(uint8 *transmitBuf, uint16 length, bool minc) {
 
 	// TX
 	spi_tx_dma_enable(_currentSetting->spi_d);	
-    dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, DMA_SIZE_8BITS,
-                       transmitBuf, DMA_SIZE_8BITS, flags);// Transmit buffer DMA 
+	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_8BIT) ? DMA_SIZE_8BITS : DMA_SIZE_16BITS;
+    dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
+                       transmitBuf, dma_bit_size, flags);// Transmit buffer DMA 
 	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
 	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
-	
-//    while (dma1_ch3_Active);
-	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & 0x2)==0); //Avoid interrupts and just loop waiting for the flag to be set.
-	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 
-	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
-	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
-	spi_tx_dma_disable(_currentSetting->spi_d);
-	if (spi_is_rx_nonempty(_currentSetting->spi_d) != 0){; // "4. Wait until RXNE=1 ..."
-		uint8 x = spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
-	}
-    return b;
-}
-
-uint8 SPIClass::dmaSend(uint16 *transmitBuf, uint16 length, bool minc) {
-	if (length == 0) return 0;
-	uint32 flags = ((DMA_MINC_MODE * minc) |  DMA_FROM_MEM | DMA_TRNS_CMPLT);
-	uint8 b;
-	dma1_ch3_Active=true;
-    dma_init(_currentSetting->spiDmaDev);
-//	dma_attach_interrupt(DMA1, DMA_CH3, &SPIClass::DMA1_CH3_Event);
-
-	// TX
-	spi_tx_dma_enable(_currentSetting->spi_d);	
-    dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, DMA_SIZE_16BITS,
-                       transmitBuf, DMA_SIZE_16BITS, flags);// Transmit buffer DMA 
-	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
-	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
-	
 //    while (dma1_ch3_Active);
-	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & 0x2)==0); //Avoid interrupts and just loop waiting for the flag to be set.
+    uint32_t m = millis();
+	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & 0x2)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
+		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
+    }
 	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
 	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 	spi_tx_dma_disable(_currentSetting->spi_d);
-	if (spi_is_rx_nonempty(_currentSetting->spi_d) != 0){; // "4. Wait until RXNE=1 ..."
-		b = spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
-	}
+	uint16 x = spi_rx_reg(_currentSetting->spi_d); // dummy read, needed, don't remove!
     return b;
 }
 
-
 void SPIClass::attachInterrupt(void) {
 	// Should be enableInterrupt()
 }
diff --git a/STM32F1/libraries/SPI/src/SPI.h b/STM32F1/libraries/SPI/src/SPI.h
index e949051e5..0f8497ae1 100644
--- a/STM32F1/libraries/SPI/src/SPI.h
+++ b/STM32F1/libraries/SPI/src/SPI.h
@@ -249,7 +249,7 @@ class SPIClass {
      * @param buffer Bytes to transmit.
      * @param length Number of bytes in buffer to transmit.
      */
-    void write(const uint8 *buffer, uint32 length);
+    void write(const void * buffer, uint32 length);
 
     /**
      * @brief Transmit a byte, then return the next unread byte.
@@ -264,6 +264,7 @@ class SPIClass {
 	
 	/**
      * @brief Sets up a DMA Transfer for "length" bytes.
+	 * The transfer mode (8 or 16 bit mode) is evaluated from the SPI peripheral setting.
      *
      * This function transmits and receives to buffers.
      *
@@ -271,30 +272,18 @@ class SPIClass {
      * @param receiveBuf buffer Bytes to save received data. 
      * @param length Number of bytes in buffer to transmit.
 	 */
-	uint8 dmaTransfer(uint8 *transmitBuf, uint8 *receiveBuf, uint16 length);
+	uint8 dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length);
 
 	/**
-     * @brief Sets up a DMA Transmit for bytes.
+     * @brief Sets up a DMA Transmit for SPI 8 or 16 bit transfer mode.
+	 * The transfer mode (8 or 16 bit mode) is evaluated from the SPI peripheral setting.
      *
-     * This function transmits and does not care about the RX fifo.
-     *
-     * @param transmitBuf buffer Bytes to transmit,
-     * @param length Number of bytes in buffer to transmit.
-	 * @param minc Set to use Memory Increment mode, clear to use Circular mode.
-     */
-	uint8 dmaSend(uint8 *transmitBuf, uint16 length, bool minc = 1);
-	
-	/**
-     * @brief Sets up a DMA Transmit for half words.
-	 * SPI PERFIPHERAL MUST BE SET TO 16 BIT MODE BEFORE
-     *
-     * This function transmits and does not care about the RX fifo.
+     * This function only transmits and does not care about the RX fifo.
      *
      * @param data buffer half words to transmit,
      * @param length Number of bytes in buffer to transmit.
-     * @param minc Set to use Memory Increment mode (default if blank), clear to use Circular mode.
      */
-	uint8 dmaSend(uint16 *transmitBuf, uint16 length, bool minc = 1);
+	uint8 dmaSend(void * transmitBuf, uint16 length);
 
     /*
      * Pin accessors

From 1892447080db8c03799e564b295d3986a0d1394e Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sat, 12 Nov 2016 18:34:58 +1100
Subject: [PATCH 012/307] Fix issue 196, for Servo library

---
 .../libraries/Servo/examples/Knob/Knob.ino    | 27 ++++++++++++++++
 .../libraries/Servo/examples/Sweep/Sweep.ino  | 32 +++++++++++++++++++
 STM32F1/libraries/Servo/keywords.txt          | 24 ++++++++++++++
 STM32F1/libraries/Servo/library.properties    |  9 ++++++
 STM32F1/libraries/Servo/rules.mk              | 29 -----------------
 STM32F1/libraries/Servo/{ => src}/Servo.cpp   |  0
 STM32F1/libraries/Servo/{ => src}/Servo.h     |  0
 7 files changed, 92 insertions(+), 29 deletions(-)
 create mode 100644 STM32F1/libraries/Servo/examples/Knob/Knob.ino
 create mode 100644 STM32F1/libraries/Servo/examples/Sweep/Sweep.ino
 create mode 100644 STM32F1/libraries/Servo/keywords.txt
 create mode 100644 STM32F1/libraries/Servo/library.properties
 delete mode 100644 STM32F1/libraries/Servo/rules.mk
 rename STM32F1/libraries/Servo/{ => src}/Servo.cpp (100%)
 rename STM32F1/libraries/Servo/{ => src}/Servo.h (100%)

diff --git a/STM32F1/libraries/Servo/examples/Knob/Knob.ino b/STM32F1/libraries/Servo/examples/Knob/Knob.ino
new file mode 100644
index 000000000..0db8770bd
--- /dev/null
+++ b/STM32F1/libraries/Servo/examples/Knob/Knob.ino
@@ -0,0 +1,27 @@
+/*
+ Controlling a servo position using a potentiometer (variable resistor)
+ by Michal Rinott <http://people.interaction-ivrea.it/m.rinott>
+
+ modified on 8 Nov 2013
+ by Scott Fitzgerald
+ http://www.arduino.cc/en/Tutorial/Knob
+*/
+
+#include <Servo.h>
+
+Servo myservo;  // create servo object to control a servo
+
+int potpin = 0;  // analog pin used to connect the potentiometer
+int val;    // variable to read the value from the analog pin
+
+void setup() {
+  myservo.attach(9);  // attaches the servo on pin 9 to the servo object
+}
+
+void loop() {
+  val = analogRead(potpin);            // reads the value of the potentiometer (value between 0 and 1023)
+  val = map(val, 0, 1023, 0, 180);     // scale it to use it with the servo (value between 0 and 180)
+  myservo.write(val);                  // sets the servo position according to the scaled value
+  delay(15);                           // waits for the servo to get there
+}
+
diff --git a/STM32F1/libraries/Servo/examples/Sweep/Sweep.ino b/STM32F1/libraries/Servo/examples/Sweep/Sweep.ino
new file mode 100644
index 000000000..df904afb1
--- /dev/null
+++ b/STM32F1/libraries/Servo/examples/Sweep/Sweep.ino
@@ -0,0 +1,32 @@
+/* Sweep
+ by BARRAGAN <http://barraganstudio.com>
+ This example code is in the public domain.
+
+ modified 8 Nov 2013
+ by Scott Fitzgerald
+ http://www.arduino.cc/en/Tutorial/Sweep
+*/
+
+#include <Servo.h>
+
+Servo myservo;  // create servo object to control a servo
+// twelve servo objects can be created on most boards
+
+int pos = 0;    // variable to store the servo position
+
+void setup() {
+  myservo.attach(9);  // attaches the servo on pin 9 to the servo object
+}
+
+void loop() {
+  for (pos = 0; pos <= 180; pos += 1) { // goes from 0 degrees to 180 degrees
+    // in steps of 1 degree
+    myservo.write(pos);              // tell servo to go to position in variable 'pos'
+    delay(15);                       // waits 15ms for the servo to reach the position
+  }
+  for (pos = 180; pos >= 0; pos -= 1) { // goes from 180 degrees to 0 degrees
+    myservo.write(pos);              // tell servo to go to position in variable 'pos'
+    delay(15);                       // waits 15ms for the servo to reach the position
+  }
+}
+
diff --git a/STM32F1/libraries/Servo/keywords.txt b/STM32F1/libraries/Servo/keywords.txt
new file mode 100644
index 000000000..0a7ca1e3d
--- /dev/null
+++ b/STM32F1/libraries/Servo/keywords.txt
@@ -0,0 +1,24 @@
+#######################################
+# Syntax Coloring Map Servo
+#######################################
+
+#######################################
+# Datatypes (KEYWORD1)
+#######################################
+
+Servo	KEYWORD1	Servo
+
+#######################################
+# Methods and Functions (KEYWORD2)
+#######################################
+attach	KEYWORD2
+detach	KEYWORD2
+write	KEYWORD2
+read	KEYWORD2
+attached	KEYWORD2
+writeMicroseconds	KEYWORD2
+readMicroseconds	KEYWORD2
+
+#######################################
+# Constants (LITERAL1)
+#######################################
diff --git a/STM32F1/libraries/Servo/library.properties b/STM32F1/libraries/Servo/library.properties
new file mode 100644
index 000000000..68ac78d55
--- /dev/null
+++ b/STM32F1/libraries/Servo/library.properties
@@ -0,0 +1,9 @@
+name=Servo(STM32F1)
+version=1.1.2
+author=Unknown (possibly LeafLabs)
+maintainer=Roger Clark (roger@rogerclark.net)
+sentence=Allows STM32 boards to control a variety of servo motors. 
+paragraph=
+category=Device Control
+url=http://www.arduino.cc/en/Reference/Servo
+architectures=STM32F1
\ No newline at end of file
diff --git a/STM32F1/libraries/Servo/rules.mk b/STM32F1/libraries/Servo/rules.mk
deleted file mode 100644
index e013754a6..000000000
--- a/STM32F1/libraries/Servo/rules.mk
+++ /dev/null
@@ -1,29 +0,0 @@
-# Standard things
-sp := $(sp).x
-dirstack_$(sp) := $(d)
-d := $(dir)
-BUILDDIRS += $(BUILD_PATH)/$(d)
-
-# Local flags
-CXXFLAGS_$(d) := $(WIRISH_INCLUDES) $(LIBMAPLE_INCLUDES)
-
-# Local rules and targets
-cSRCS_$(d) :=
-
-cppSRCS_$(d) := Servo.cpp
-
-cFILES_$(d) := $(cSRCS_$(d):%=$(d)/%)
-cppFILES_$(d) := $(cppSRCS_$(d):%=$(d)/%)
-
-OBJS_$(d) := $(cFILES_$(d):%.c=$(BUILD_PATH)/%.o) \
-             $(cppFILES_$(d):%.cpp=$(BUILD_PATH)/%.o)
-DEPS_$(d) := $(OBJS_$(d):%.o=%.d)
-
-$(OBJS_$(d)): TGT_CXXFLAGS := $(CXXFLAGS_$(d))
-
-TGT_BIN += $(OBJS_$(d))
-
-# Standard things
--include $(DEPS_$(d))
-d := $(dirstack_$(sp))
-sp := $(basename $(sp))
\ No newline at end of file
diff --git a/STM32F1/libraries/Servo/Servo.cpp b/STM32F1/libraries/Servo/src/Servo.cpp
similarity index 100%
rename from STM32F1/libraries/Servo/Servo.cpp
rename to STM32F1/libraries/Servo/src/Servo.cpp
diff --git a/STM32F1/libraries/Servo/Servo.h b/STM32F1/libraries/Servo/src/Servo.h
similarity index 100%
rename from STM32F1/libraries/Servo/Servo.h
rename to STM32F1/libraries/Servo/src/Servo.h

From dcfe2ae817a4b3ed57a8a8aae7ff5df105b6868c Mon Sep 17 00:00:00 2001
From: Phisatho <phisatho@gmail.com>
Date: Fri, 18 Nov 2016 02:29:12 +0400
Subject: [PATCH 013/307] Create pins_arduino.h

---
 STM32F1/variants/STM32VLD/pins_arduino.h | 6 ++++++
 1 file changed, 6 insertions(+)
 create mode 100644 STM32F1/variants/STM32VLD/pins_arduino.h

diff --git a/STM32F1/variants/STM32VLD/pins_arduino.h b/STM32F1/variants/STM32VLD/pins_arduino.h
new file mode 100644
index 000000000..9f8632dfe
--- /dev/null
+++ b/STM32F1/variants/STM32VLD/pins_arduino.h
@@ -0,0 +1,6 @@
+
+
+
+
+// API compatibility
+#include "variant.h"

From f43d07efb3f3efec500faeb3399fbece670b25eb Mon Sep 17 00:00:00 2001
From: Phisatho <phisatho@gmail.com>
Date: Fri, 18 Nov 2016 02:30:20 +0400
Subject: [PATCH 014/307] Add files via upload

---
 STM32F1/variants/STM32VLD/board.cpp           | 161 ++++++++++++
 STM32F1/variants/STM32VLD/board/board.h       |  92 +++++++
 STM32F1/variants/STM32VLD/ld/common.inc       | 220 +++++++++++++++++
 STM32F1/variants/STM32VLD/ld/extra_libs.inc   |   7 +
 STM32F1/variants/STM32VLD/ld/jtag.ld          |  36 +++
 .../variants/STM32VLD/ld/vector_symbols.inc   |  78 ++++++
 STM32F1/variants/STM32VLD/variant.h           |  20 ++
 STM32F1/variants/STM32VLD/wirish/boards.cpp   | 229 ++++++++++++++++++
 .../variants/STM32VLD/wirish/boards_setup.cpp | 104 ++++++++
 STM32F1/variants/STM32VLD/wirish/start.S      |  57 +++++
 STM32F1/variants/STM32VLD/wirish/start_c.c    |  95 ++++++++
 STM32F1/variants/STM32VLD/wirish/syscalls.c   | 176 ++++++++++++++
 12 files changed, 1275 insertions(+)
 create mode 100644 STM32F1/variants/STM32VLD/board.cpp
 create mode 100644 STM32F1/variants/STM32VLD/board/board.h
 create mode 100644 STM32F1/variants/STM32VLD/ld/common.inc
 create mode 100644 STM32F1/variants/STM32VLD/ld/extra_libs.inc
 create mode 100644 STM32F1/variants/STM32VLD/ld/jtag.ld
 create mode 100644 STM32F1/variants/STM32VLD/ld/vector_symbols.inc
 create mode 100644 STM32F1/variants/STM32VLD/variant.h
 create mode 100644 STM32F1/variants/STM32VLD/wirish/boards.cpp
 create mode 100644 STM32F1/variants/STM32VLD/wirish/boards_setup.cpp
 create mode 100644 STM32F1/variants/STM32VLD/wirish/start.S
 create mode 100644 STM32F1/variants/STM32VLD/wirish/start_c.c
 create mode 100644 STM32F1/variants/STM32VLD/wirish/syscalls.c

diff --git a/STM32F1/variants/STM32VLD/board.cpp b/STM32F1/variants/STM32VLD/board.cpp
new file mode 100644
index 000000000..1cecbd932
--- /dev/null
+++ b/STM32F1/variants/STM32VLD/board.cpp
@@ -0,0 +1,161 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file   wirish/boards/maple_mini/board.cpp
+ * @author Marti Bolivar <mbolivar@leaflabs.com>
+ * @brief  Maple Mini board file.
+ */
+
+#include <board/board.h>
+
+#include <libmaple/gpio.h>
+#include <libmaple/timer.h>
+
+/* Roger Clark. Added next to includes for changes to Serial */
+#include <libmaple/usart.h>
+#include <HardwareSerial.h>
+
+#include <wirish_debug.h>
+#include <wirish_types.h>
+
+/* Since we want the Serial Wire/JTAG pins as GPIOs, disable both SW
+ * and JTAG debug support, unless configured otherwise. */
+void boardInit(void) {
+#ifndef CONFIG_MAPLE_MINI_NO_DISABLE_DEBUG
+    disableDebugPorts();
+#endif
+}
+
+// Note. See the enum of pin names in board.h
+
+extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
+
+
+    {&gpioa, &timer2, &adc1,  0, 1,    0}, /* PA0 */
+    {&gpioa, &timer2, &adc1,  1, 2,    1}, /* PA1 */
+    {&gpioa, &timer2, &adc1,  2, 3,    2}, /* PA2 */	
+    {&gpioa, &timer2, &adc1,  3, 4,    3}, /* PA3 */
+    {&gpioa,   	NULL, &adc1,  4, 0,    4}, /* PA4 */
+    {&gpioa,   	NULL, &adc1,  5, 0,    5}, /* PA5 */
+    {&gpioa, &timer3, &adc1,  6, 1,    6}, /* PA6 */
+    {&gpioa, &timer3, &adc1,  7, 2,    7}, /* PA7 */
+    {&gpioa, &timer1, NULL,  8, 1, ADCx}, /* PA8 */	
+    {&gpioa, &timer1, NULL,  9, 2, ADCx}, /* PA9 */	
+    {&gpioa, &timer1, NULL, 10, 3, ADCx}, /* PA10 */
+    {&gpioa,	NULL, NULL, 11, 0, ADCx}, /* PA11 */
+    {&gpioa,   	NULL, NULL, 12, 0, ADCx}, /* PA12 */	
+    {&gpioa,   	NULL, NULL, 13, 0, ADCx}, /* PA13 */	
+    {&gpioa,   	NULL, NULL, 14, 0, ADCx}, /* PA14 */
+    {&gpioa,   	NULL, NULL, 15, 0, ADCx}, /* PA15 */
+	
+    {&gpiob, &timer3, &adc1,  0, 3,    8}, /* PB0 */	
+    {&gpiob, &timer3, &adc1,  1, 4,    9}, /* PB1 */
+    {&gpiob,   	NULL, NULL,  2, 0, ADCx}, /* PB2 */
+    {&gpiob,   	NULL, NULL,  3, 0, ADCx}, /* PB3 */
+    {&gpiob,   NULL, NULL,  4, 0, ADCx}, /* PB4 */
+    {&gpiob,   NULL, NULL,  5, 0, ADCx}, /* PB5 */
+    {&gpiob, &timer4, NULL,  6, 1, ADCx}, /* PB6 */
+    {&gpiob, &timer4, NULL,  7, 2, ADCx}, /* PB7 */	
+    {&gpiob, &timer4, NULL,  8, 3, ADCx}, /* PB8 */	
+    {&gpiob, &timer4, NULL,  9, 4, ADCx}, /* PB9 */	
+    {&gpiob,   NULL, NULL, 10, 0, ADCx}, /* PB10 */	
+    {&gpiob,   NULL, NULL, 11, 0, ADCx}, /* PB11 */
+    {&gpiob,   NULL, NULL, 12, 0, ADCx}, /* PB12 */
+    {&gpiob,   NULL, NULL, 13, 0, ADCx}, /* PB13 */
+    {&gpiob,   NULL, NULL, 14, 0, ADCx}, /* PB14 */
+    {&gpiob,   NULL, NULL, 15, 0, ADCx}, /* PB15 */
+
+/* Andy Hull - the R8 is similar to the C8 but exposes more GPIO as follows */
+    {&gpioc,   NULL, &adc1, 0, 0, 10},  /* PC0 */
+    {&gpioc,   NULL, &adc1, 1, 0, 11},  /* PC1 */
+    {&gpioc,   NULL, &adc1, 2, 0, 12},  /* PC2 */
+    {&gpioc,   NULL, &adc1, 3, 0, 13},  /* PC3 */
+    {&gpioc,   NULL, &adc1, 4, 0, 14},  /* PC4 */
+    {&gpioc,   NULL, &adc1, 5, 0, 15},  /* PC5 */
+
+    {&gpioc,   NULL, NULL, 6, 0, ADCx},  /* PC6 */
+    {&gpioc,   NULL, NULL, 7, 0, ADCx},  /* PC7 */
+    {&gpioc,   NULL, NULL, 8, 0, ADCx},  /* PC8 */
+    {&gpioc,   NULL, NULL, 9, 0, ADCx},  /* PC9 */
+
+    {&gpioc,   NULL, NULL, 10, 0, ADCx}, /* PC10 */
+    {&gpioc,   NULL, NULL, 11, 0, ADCx}, /* PC11 */
+    {&gpioc,   NULL, NULL, 12, 0, ADCx}, /* PC12 */
+    {&gpioc,   NULL, NULL, 13, 0, ADCx}, /* PC13 */	
+    {&gpioc,   NULL, NULL, 14, 0, ADCx}, /* PC14 */
+    {&gpioc,   NULL, NULL, 15, 0, ADCx}, /* PC15 */
+
+    {&gpiod,   NULL, NULL, 0, 0, ADCx},  /* PD2 */
+	{&gpiod,   NULL, NULL, 1, 0, ADCx},  /* PD2 */
+	{&gpiod,   NULL, NULL, 2, 0, ADCx},  /* PD2 */
+};
+
+extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
+    PA0, PA1, PA2, PA3, PA6, PA7, PA8, PA9, PA10, PB0, PB1, PB6, PB7, PB8, PB9
+};
+
+extern const uint8 boardADCPins[BOARD_NR_ADC_PINS] __FLASH__ = {
+    PA0, PA1, PA2 , PA3 , PA4 , PA5 , PA6 , PA7 , PB0 , PB1, PC0, PC1, PC2, PC3, PC4, PC5
+};
+
+// Note. These defines are not really used by generic boards. They are for  Maple Serial USB
+//#define USB_DP PA12
+//#define USB_DM PA11
+
+// NOte. These definitions are not really used for generic boards, they only relate to boards modified to behave like Maple boards
+extern const uint8 boardUsedPins[BOARD_NR_USED_PINS] __FLASH__ = {
+     BOARD_LED_PIN, BOARD_BUTTON_PIN, BOARD_JTMS_SWDIO_PIN,
+    BOARD_JTCK_SWCLK_PIN, BOARD_JTDI_PIN, BOARD_JTDO_PIN, BOARD_NJTRST_PIN
+	 //USB_DP, USB_DM
+};
+
+
+/* 
+ * Roger Clark
+ * 
+ * 2015/05/28
+ *
+ * Moved definitions for Hardware Serial devices from HardwareSerial.cpp so that each board can define which Arduino "Serial" instance
+ * Maps to which hardware serial port on the microprocessor
+ */
+						
+#ifdef SERIAL_USB
+	DEFINE_HWSERIAL(Serial1, 1);
+
+	DEFINE_HWSERIAL(Serial2, 2);
+
+	DEFINE_HWSERIAL(Serial3, 3);
+
+#else
+	DEFINE_HWSERIAL(Serial, 1);
+
+	DEFINE_HWSERIAL(Serial1, 2);
+
+	DEFINE_HWSERIAL(Serial2, 3);
+
+
+#endif
diff --git a/STM32F1/variants/STM32VLD/board/board.h b/STM32F1/variants/STM32VLD/board/board.h
new file mode 100644
index 000000000..ba8d556c8
--- /dev/null
+++ b/STM32F1/variants/STM32VLD/board/board.h
@@ -0,0 +1,92 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file   wirish/boards/maple_mini/include/board/board.h
+ * @author Marti Bolivar <mbolivar@leaflabs.com>
+ * @brief  Maple Mini board header.
+ *
+ * See wirish/boards/maple/include/board/board.h for more information
+ * on these definitions.
+ */
+
+#ifndef _BOARD_STM32VLD_H_
+#define _BOARD_STM32VLD_H_
+
+
+
+#define CYCLES_PER_MICROSECOND    24
+//#define SYSTICK_RELOAD_VAL     (F_CPU/1000) - 1 /* takes a cycle to reload */
+#define SYSTICK_RELOAD_VAL      23999  /* takes a cycle to reload */
+
+#define BOARD_LED_PIN           PC8  /* BlueLED(PC8) */
+#define BOARD_BUTTON_PIN        PA0  /* USR SW(PA0) */
+
+#define LED_G					PC9
+#define LED_B					PC8
+
+#define BOARD_NR_USARTS           3
+#define BOARD_USART1_TX_PIN       PA9
+#define BOARD_USART1_RX_PIN       PA10
+#define BOARD_USART2_TX_PIN       PA2
+#define BOARD_USART2_RX_PIN       PA3
+#define BOARD_USART3_TX_PIN       PB10
+#define BOARD_USART3_RX_PIN       PB11
+
+#define BOARD_NR_SPI              2
+#define BOARD_SPI1_NSS_PIN        PA4
+#define BOARD_SPI1_MOSI_PIN       PA7
+#define BOARD_SPI1_MISO_PIN       PA6
+#define BOARD_SPI1_SCK_PIN        PA5
+#define BOARD_SPI2_NSS_PIN        PB12
+#define BOARD_SPI2_MOSI_PIN       PB15
+#define BOARD_SPI2_MISO_PIN       PB14
+#define BOARD_SPI2_SCK_PIN        PB13
+
+#define BOARD_NR_GPIO_PINS        51
+#define BOARD_NR_PWM_PINS         15
+#define BOARD_NR_ADC_PINS         16
+#define BOARD_NR_USED_PINS        7
+
+#define BOARD_JTMS_SWDIO_PIN    PA13
+#define BOARD_JTCK_SWCLK_PIN    PA14
+#define BOARD_JTDI_PIN          PA15
+#define BOARD_JTDO_PIN          PB3
+#define BOARD_NJTRST_PIN        PB4
+
+
+#define BOARD_USB_DISC_DEV        GPIOB
+#define BOARD_USB_DISC_BIT        10
+
+// Note this needs to match with the PIN_MAP array in board.cpp
+enum {
+        PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13, PA14, PA15,
+	PB0, PB1, PB2, PB3, PB4, PB5, PB6, PB7, PB8, PB9, PB10, PB11, PB12, PB13, PB14, PB15,
+	PC0, PC1, PC2, PC3, PC4, PC5, PC6, PC7, PC8, PC9, PC10, PC11, PC12, PC13, PC14, PC15,
+    PD0, PD1, PD2
+};
+
+#endif
diff --git a/STM32F1/variants/STM32VLD/ld/common.inc b/STM32F1/variants/STM32VLD/ld/common.inc
new file mode 100644
index 000000000..0c2b6a42b
--- /dev/null
+++ b/STM32F1/variants/STM32VLD/ld/common.inc
@@ -0,0 +1,220 @@
+/*
+ * Linker script for libmaple.
+ *
+ * Original author "lanchon" from ST forums, with modifications by LeafLabs.
+ */
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+
+/*
+ * Configure other libraries we want in the link.
+ *
+ * libgcc, libc, and libm are common across supported toolchains.
+ * However, some toolchains require additional archives which aren't
+ * present everywhere (e.g. ARM's gcc-arm-embedded releases).
+ *
+ * To hack around this, we let the build system specify additional
+ * archives by putting the right extra_libs.inc (in a directory under
+ * toolchains/) in our search path.
+ */
+GROUP(libgcc.a libc.a libm.a)
+INCLUDE extra_libs.inc
+
+/*
+ * These force the linker to search for vector table symbols.
+ *
+ * These symbols vary by STM32 family (and also within families).
+ * It's up to the build system to configure the link's search path
+ * properly for the target MCU.
+ */
+INCLUDE vector_symbols.inc
+
+/* STM32 vector table. */
+EXTERN(__stm32_vector_table)
+
+/* C runtime initialization function. */
+EXTERN(start_c)
+
+/* main entry point */
+EXTERN(main)
+
+/* Initial stack pointer value. */
+EXTERN(__msp_init)
+PROVIDE(__msp_init = ORIGIN(ram) + LENGTH(ram));
+
+/* Reset vector and chip reset entry point */
+EXTERN(__start__)
+ENTRY(__start__)
+PROVIDE(__exc_reset = __start__);
+
+/* Heap boundaries, for libmaple */
+EXTERN(_lm_heap_start);
+EXTERN(_lm_heap_end);
+
+SECTIONS
+{
+    .text :
+      {
+        __text_start__ = .;
+        /*
+         * STM32 vector table.  Leave this here.  Yes, really.
+         */
+        *(.stm32.interrupt_vector)
+
+        /*
+         * Program code and vague linking
+         */
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.plt)
+        *(.gnu.warning)
+        *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+        *(.gcc_except_table)
+        *(.eh_frame_hdr)
+        *(.eh_frame)
+
+        . = ALIGN(4);
+        KEEP(*(.init))
+
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+      } > REGION_TEXT
+
+    /*
+     * End of text
+     */
+    .text.align :
+      {
+        . = ALIGN(8);
+        __text_end__ = .;
+      } > REGION_TEXT
+
+    /*
+     * .ARM.exidx exception unwinding; mandated by ARM's C++ ABI
+     */
+    __exidx_start = .;
+    .ARM.exidx :
+      {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+      } > REGION_RODATA
+    __exidx_end = .;
+
+    /*
+     * .data
+     */
+    .data :
+      {
+        __data_start__ = .;
+      	LONG(0)
+        . = ALIGN(8);
+
+        *(.got.plt) *(.got)
+        *(.data .data.* .gnu.linkonce.d.*)
+
+        . = ALIGN(8);
+        __data_end__ = .;
+      } > REGION_DATA AT> REGION_RODATA
+
+    /*
+     * Read-only data
+     */
+    .rodata :
+      {
+        *(.rodata .rodata.* .gnu.linkonce.r.*)
+        /* .USER_FLASH: We allow users to allocate into Flash here */
+        *(.USER_FLASH)
+        /* ROM image configuration; for C startup */
+        . = ALIGN(4);
+        _lm_rom_img_cfgp = .;
+        LONG(LOADADDR(.data));
+        /*
+         * Heap: Linker scripts may choose a custom heap by overriding
+         * _lm_heap_start and _lm_heap_end. Otherwise, the heap is in
+         * internal SRAM, beginning after .bss, and growing towards
+         * the stack.
+         *
+         * I'm shoving these here naively; there's probably a cleaner way
+         * to go about this. [mbolivar]
+         */
+        _lm_heap_start = DEFINED(_lm_heap_start) ? _lm_heap_start : _end;
+        _lm_heap_end   = DEFINED(_lm_heap_end) ? _lm_heap_end : __msp_init;
+      } > REGION_RODATA
+
+    /*
+     * .bss
+     */
+    .bss :
+      {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss .bss.* .gnu.linkonce.b.*)
+        *(COMMON)
+        . = ALIGN (8);
+        __bss_end__ = .;
+        _end = __bss_end__;
+      } > REGION_BSS
+
+    /*
+     * Debugging sections
+     */
+    .stab 0 (NOLOAD) : { *(.stab) }
+    .stabstr 0 (NOLOAD) : { *(.stabstr) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+
+    .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+    .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+    /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/STM32F1/variants/STM32VLD/ld/extra_libs.inc b/STM32F1/variants/STM32VLD/ld/extra_libs.inc
new file mode 100644
index 000000000..4413a5334
--- /dev/null
+++ b/STM32F1/variants/STM32VLD/ld/extra_libs.inc
@@ -0,0 +1,7 @@
+/*
+ * Extra archives needed by ARM's GCC ARM Embedded arm-none-eabi-
+ * releases (https://launchpad.net/gcc-arm-embedded/).
+ */
+
+/* This is for the provided newlib. */
+GROUP(libnosys.a)
diff --git a/STM32F1/variants/STM32VLD/ld/jtag.ld b/STM32F1/variants/STM32VLD/ld/jtag.ld
new file mode 100644
index 000000000..4cfd39afb
--- /dev/null
+++ b/STM32F1/variants/STM32VLD/ld/jtag.ld
@@ -0,0 +1,36 @@
+/*
+ * This file is part of the libopencm3 project.
+ *
+ * Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
+ *
+ * This program is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/>.
+ */
+
+/* Linker script for STM32F100RB */
+
+/* Define memory regions. */
+MEMORY
+{
+	rom (rx) : ORIGIN = 0x08000000, LENGTH = 128K
+	ram (rwx) : ORIGIN = 0x20000000, LENGTH = 8K
+}
+
+REGION_ALIAS("REGION_TEXT", rom);
+REGION_ALIAS("REGION_DATA", ram);
+REGION_ALIAS("REGION_BSS", ram);
+REGION_ALIAS("REGION_RODATA", rom);
+
+
+INCLUDE common.inc
+
diff --git a/STM32F1/variants/STM32VLD/ld/vector_symbols.inc b/STM32F1/variants/STM32VLD/ld/vector_symbols.inc
new file mode 100644
index 000000000..a40012a2d
--- /dev/null
+++ b/STM32F1/variants/STM32VLD/ld/vector_symbols.inc
@@ -0,0 +1,78 @@
+EXTERN(__msp_init)
+EXTERN(__exc_reset)
+EXTERN(__exc_nmi)
+EXTERN(__exc_hardfault)
+EXTERN(__exc_memmanage)
+EXTERN(__exc_busfault)
+EXTERN(__exc_usagefault)
+EXTERN(__stm32reservedexception7)
+EXTERN(__stm32reservedexception8)
+EXTERN(__stm32reservedexception9)
+EXTERN(__stm32reservedexception10)
+EXTERN(__exc_svc)
+EXTERN(__exc_debug_monitor)
+EXTERN(__stm32reservedexception13)
+EXTERN(__exc_pendsv)
+EXTERN(__exc_systick)
+
+EXTERN(__irq_wwdg)
+EXTERN(__irq_pvd)
+EXTERN(__irq_tamper)
+EXTERN(__irq_rtc)
+EXTERN(__irq_flash)
+EXTERN(__irq_rcc)
+EXTERN(__irq_exti0)
+EXTERN(__irq_exti1)
+EXTERN(__irq_exti2)
+EXTERN(__irq_exti3)
+EXTERN(__irq_exti4)
+EXTERN(__irq_dma1_channel1)
+EXTERN(__irq_dma1_channel2)
+EXTERN(__irq_dma1_channel3)
+EXTERN(__irq_dma1_channel4)
+EXTERN(__irq_dma1_channel5)
+EXTERN(__irq_dma1_channel6)
+EXTERN(__irq_dma1_channel7)
+EXTERN(__irq_adc)
+EXTERN(__irq_usb_hp_can_tx)
+EXTERN(__irq_usb_lp_can_rx0)
+EXTERN(__irq_can_rx1)
+EXTERN(__irq_can_sce)
+EXTERN(__irq_exti9_5)
+EXTERN(__irq_tim1_brk)
+EXTERN(__irq_tim1_up)
+EXTERN(__irq_tim1_trg_com)
+EXTERN(__irq_tim1_cc)
+EXTERN(__irq_tim2)
+EXTERN(__irq_tim3)
+EXTERN(__irq_tim4)
+EXTERN(__irq_i2c1_ev)
+EXTERN(__irq_i2c1_er)
+EXTERN(__irq_i2c2_ev)
+EXTERN(__irq_i2c2_er)
+EXTERN(__irq_spi1)
+EXTERN(__irq_spi2)
+EXTERN(__irq_usart1)
+EXTERN(__irq_usart2)
+EXTERN(__irq_usart3)
+EXTERN(__irq_exti15_10)
+EXTERN(__irq_rtcalarm)
+EXTERN(__irq_usbwakeup)
+
+EXTERN(__irq_tim8_brk)
+EXTERN(__irq_tim8_up)
+EXTERN(__irq_tim8_trg_com)
+EXTERN(__irq_tim8_cc)
+EXTERN(__irq_adc3)
+EXTERN(__irq_fsmc)
+EXTERN(__irq_sdio)
+EXTERN(__irq_tim5)
+EXTERN(__irq_spi3)
+EXTERN(__irq_uart4)
+EXTERN(__irq_uart5)
+EXTERN(__irq_tim6)
+EXTERN(__irq_tim7)
+EXTERN(__irq_dma2_channel1)
+EXTERN(__irq_dma2_channel2)
+EXTERN(__irq_dma2_channel3)
+EXTERN(__irq_dma2_channel4_5)
diff --git a/STM32F1/variants/STM32VLD/variant.h b/STM32F1/variants/STM32VLD/variant.h
new file mode 100644
index 000000000..52b39a629
--- /dev/null
+++ b/STM32F1/variants/STM32VLD/variant.h
@@ -0,0 +1,20 @@
+#ifndef _VARIANT_ARDUINO_STM32_
+#define _VARIANT_ARDUINO_STM32_
+
+#define digitalPinToPort(P)        ( PIN_MAP[P].gpio_device )
+#define digitalPinToBitMask(P)     ( BIT(PIN_MAP[P].gpio_bit) )
+#define portOutputRegister(port)   ( &(port->regs->ODR) )
+#define portInputRegister(port)    ( &(port->regs->IDR) )
+
+#define portSetRegister(pin)		( &(PIN_MAP[pin].gpio_device->regs->BSRR) )
+#define portClearRegister(pin)		( &(PIN_MAP[pin].gpio_device->regs->BRR) )
+
+#define portConfigRegister(pin)		( &(PIN_MAP[pin].gpio_device->regs->CRL) )
+
+static const uint8_t SS   = BOARD_SPI1_NSS_PIN;
+static const uint8_t SS1  = BOARD_SPI2_NSS_PIN;
+static const uint8_t MOSI = BOARD_SPI1_MOSI_PIN;
+static const uint8_t MISO = BOARD_SPI1_MISO_PIN;
+static const uint8_t SCK  = BOARD_SPI1_SCK_PIN;
+
+#endif /* _VARIANT_ARDUINO_STM32_ */
\ No newline at end of file
diff --git a/STM32F1/variants/STM32VLD/wirish/boards.cpp b/STM32F1/variants/STM32VLD/wirish/boards.cpp
new file mode 100644
index 000000000..5274e7a93
--- /dev/null
+++ b/STM32F1/variants/STM32VLD/wirish/boards.cpp
@@ -0,0 +1,229 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Perry Hung.
+ * Copyright (c) 2011, 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file wirish/boards.cpp
+ * @brief init() and board routines.
+ *
+ * This file is mostly interesting for the init() function, which
+ * configures Flash, the core clocks, and a variety of other available
+ * peripherals on the board so the rest of Wirish doesn't have to turn
+ * things on before using them.
+ *
+ * Prior to returning, init() calls boardInit(), which allows boards
+ * to perform any initialization they need to. This file includes a
+ * weak no-op definition of boardInit(), so boards that don't need any
+ * special initialization don't have to define their own.
+ *
+ * How init() works is chip-specific. See the boards_setup.cpp files
+ * under e.g. wirish/stm32f1/, wirish/stmf32f2 for the details, but be
+ * advised: their contents are unstable, and can/will change without
+ * notice.
+ */
+
+#include <boards.h>
+#include <libmaple/libmaple_types.h>
+#include <libmaple/flash.h>
+#include <libmaple/nvic.h>
+#include <libmaple/systick.h>
+#include "boards_private.h"
+
+static void setup_flash(void);
+static void setup_clocks(void);
+static void setup_nvic(void);
+static void setup_adcs(void);
+static void setup_timers(void);
+
+/*
+ * Exported functions
+ */
+
+void init(void) {
+    setup_flash();
+    setup_clocks();
+    setup_nvic();
+    systick_init(SYSTICK_RELOAD_VAL);
+    wirish::priv::board_setup_gpio();
+    setup_adcs();
+    setup_timers();
+    wirish::priv::board_setup_usb();
+    wirish::priv::series_init();
+    boardInit();
+}
+
+/* Provide a default no-op boardInit(). */
+__weak void boardInit(void) {
+}
+
+/* You could farm this out to the files in boards/ if e.g. it takes
+ * too long to test on boards with lots of pins. */
+bool boardUsesPin(uint8 pin) {
+    for (int i = 0; i < BOARD_NR_USED_PINS; i++) {
+        if (pin == boardUsedPins[i]) {
+            return true;
+        }
+    }
+    return false;
+}
+
+/*
+ * Auxiliary routines
+ */
+
+static void setup_flash(void) {
+    // Turn on as many Flash "go faster" features as
+    // possible. flash_enable_features() just ignores any flags it
+    // can't support.
+    flash_enable_features(FLASH_PREFETCH | FLASH_ICACHE | FLASH_DCACHE);
+    // Configure the wait states, assuming we're operating at "close
+    // enough" to 3.3V.
+    flash_set_latency(FLASH_SAFE_WAIT_STATES);
+}
+
+static void setup_clocks(void) {
+    // Turn on HSI. We'll switch to and run off of this while we're
+    // setting up the main PLL.
+    rcc_turn_on_clk(RCC_CLK_HSI);
+
+    // Turn off and reset the clock subsystems we'll be using, as well
+    // as the clock security subsystem (CSS). Note that resetting CFGR
+    // to its default value of 0 implies a switch to HSI for SYSCLK.
+    RCC_BASE->CFGR = 0x00000000;
+    rcc_disable_css();
+    rcc_turn_off_clk(RCC_CLK_PLL);
+    rcc_turn_off_clk(RCC_CLK_HSE);
+    wirish::priv::board_reset_pll();
+    // Clear clock readiness interrupt flags and turn off clock
+    // readiness interrupts.
+    RCC_BASE->CIR = 0x00000000;
+
+    // Enable HSE, and wait until it's ready.
+    rcc_turn_on_clk(RCC_CLK_HSE);
+    while (!rcc_is_clk_ready(RCC_CLK_HSE))
+        ;
+
+    // Configure AHBx, APBx, etc. prescalers and the main PLL.
+    wirish::priv::board_setup_clock_prescalers();
+    rcc_configure_pll(&wirish::priv::w_board_pll_cfg);
+
+    // Enable the PLL, and wait until it's ready.
+    rcc_turn_on_clk(RCC_CLK_PLL);
+    while(!rcc_is_clk_ready(RCC_CLK_PLL))
+        ;
+
+    // Finally, switch to the now-ready PLL as the main clock source.
+    rcc_switch_sysclk(RCC_CLKSRC_PLL);
+}
+
+/*
+ * These addresses are where usercode starts when a bootloader is
+ * present. If no bootloader is present, the user NVIC usually starts
+ * at the Flash base address, 0x08000000.
+ */
+#if defined(BOOTLOADER_maple)
+	#define USER_ADDR_ROM 0x08005000
+#else
+	#if defined(BOOTLOADER_robotis)
+		#define USER_ADDR_ROM 0x08003000
+	#else
+		#define USER_ADDR_ROM 0x08000000
+	#endif
+#endif
+#define USER_ADDR_RAM 0x20000C00
+extern char __text_start__;
+
+static void setup_nvic(void) {
+
+nvic_init((uint32)VECT_TAB_ADDR, 0);
+
+/* Roger Clark. We now control nvic vector table in boards.txt using the build.vect paramater
+#ifdef VECT_TAB_FLASH
+    nvic_init(USER_ADDR_ROM, 0);
+#elif defined VECT_TAB_RAM
+    nvic_init(USER_ADDR_RAM, 0);
+#elif defined VECT_TAB_BASE
+    nvic_init((uint32)0x08000000, 0);
+#elif defined VECT_TAB_ADDR
+    // A numerically supplied value
+    nvic_init((uint32)VECT_TAB_ADDR, 0);
+#else
+    // Use the __text_start__ value from the linker script; this
+    // should be the start of the vector table.
+    nvic_init((uint32)&__text_start__, 0);
+#endif
+
+*/
+}
+
+static void adc_default_config(adc_dev *dev) {
+    adc_enable_single_swstart(dev);
+    adc_set_sample_rate(dev, wirish::priv::w_adc_smp);
+}
+
+static void setup_adcs(void) {
+    adc_set_prescaler(wirish::priv::w_adc_pre);
+    adc_foreach(adc_default_config);
+}
+
+static void timer_default_config(timer_dev *dev) {
+    timer_adv_reg_map *regs = (dev->regs).adv;
+    const uint16 full_overflow = 0xFFFF;
+    const uint16 half_duty = 0x8FFF;
+
+    timer_init(dev);
+    timer_pause(dev);
+
+    regs->CR1 = TIMER_CR1_ARPE;
+    regs->PSC = 1;
+    regs->SR = 0;
+    regs->DIER = 0;
+    regs->EGR = TIMER_EGR_UG;
+    switch (dev->type) {
+    case TIMER_ADVANCED:
+        regs->BDTR = TIMER_BDTR_MOE | TIMER_BDTR_LOCK_OFF;
+        // fall-through
+    case TIMER_GENERAL:
+        timer_set_reload(dev, full_overflow);
+        for (uint8 channel = 1; channel <= 4; channel++) {
+            if (timer_has_cc_channel(dev, channel)) {
+                timer_set_compare(dev, channel, half_duty);
+                timer_oc_set_mode(dev, channel, TIMER_OC_MODE_PWM_1,
+                                  TIMER_OC_PE);
+            }
+        }
+        // fall-through
+    case TIMER_BASIC:
+        break;
+    }
+
+    timer_generate_update(dev);
+    timer_resume(dev);
+}
+
+static void setup_timers(void) {
+    timer_foreach(timer_default_config);
+}
diff --git a/STM32F1/variants/STM32VLD/wirish/boards_setup.cpp b/STM32F1/variants/STM32VLD/wirish/boards_setup.cpp
new file mode 100644
index 000000000..9de4d5396
--- /dev/null
+++ b/STM32F1/variants/STM32VLD/wirish/boards_setup.cpp
@@ -0,0 +1,104 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+*****************************************************************************/
+
+/**
+ * @file wirish/stm32f1/boards_setup.cpp
+ * @author Marti Bolivar <mbolivar@leaflabs.com>
+ * @brief STM32F1 chip setup.
+ *
+ * This file controls how init() behaves on the STM32F1. Be very
+ * careful when changing anything here. Many of these values depend
+ * upon each other.
+ */
+
+#include "boards_private.h"
+
+#include <libmaple/gpio.h>
+#include <libmaple/timer.h>
+
+#include <boards.h>
+#include <usb_serial.h>
+
+// Allow boards to provide a PLL multiplier. This is useful for
+// e.g. STM32F100 value line MCUs, which use slower multipliers.
+// (We're leaving the default to RCC_PLLMUL_9 for now, since that
+// works for F103 performance line MCUs, which is all that LeafLabs
+// currently officially supports).
+#ifndef BOARD_RCC_PLLMUL
+#define BOARD_RCC_PLLMUL RCC_PLLMUL_3
+#endif
+
+namespace wirish {
+    namespace priv {
+
+        static stm32f1_rcc_pll_data pll_data = {BOARD_RCC_PLLMUL};
+        __weak rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSE, &pll_data};
+        __weak adc_prescaler w_adc_pre = ADC_PRE_PCLK2_DIV_6;
+        __weak adc_smp_rate w_adc_smp = ADC_SMPR_55_5;
+
+        __weak void board_reset_pll(void) {
+            // TODO
+        }
+
+        __weak void board_setup_clock_prescalers(void) {
+            rcc_set_prescaler(RCC_PRESCALER_AHB, RCC_AHB_SYSCLK_DIV_1);
+            rcc_set_prescaler(RCC_PRESCALER_APB1, RCC_APB1_HCLK_DIV_2);
+            rcc_set_prescaler(RCC_PRESCALER_APB2, RCC_APB2_HCLK_DIV_1);
+			rcc_clk_disable(RCC_USB);
+			#if F_CPU == 72000000
+			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);
+			#elif F_CPU == 48000000
+			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);			
+			#endif	
+        }
+
+        __weak void board_setup_gpio(void) {
+            gpio_init_all();
+        }
+
+        __weak void board_setup_usb(void) {
+#ifdef SERIAL_USB
+			
+#ifdef GENERIC_BOOTLOADER			
+			//Reset the USB interface on generic boards - developed by Victor PV
+			gpio_set_mode(PIN_MAP[PA12].gpio_device, PIN_MAP[PA12].gpio_bit, GPIO_OUTPUT_PP);
+			gpio_write_bit(PIN_MAP[PA12].gpio_device, PIN_MAP[PA12].gpio_bit,0);
+			
+			for(volatile unsigned int i=0;i<512;i++);// Only small delay seems to be needed, and USB pins will get configured in Serial.begin
+			gpio_set_mode(PIN_MAP[PA12].gpio_device, PIN_MAP[PA12].gpio_bit, GPIO_INPUT_FLOATING);
+#endif			
+			Serial.begin();// Roger Clark. Changed SerialUSB to Serial for Arduino sketch compatibility
+#endif
+		}
+
+        __weak void series_init(void) {
+            // Initialize AFIO here, too, so peripheral remaps and external
+            // interrupts work out of the box.
+            afio_init();
+        }
+
+    }
+}
diff --git a/STM32F1/variants/STM32VLD/wirish/start.S b/STM32F1/variants/STM32VLD/wirish/start.S
new file mode 100644
index 000000000..a04f2220a
--- /dev/null
+++ b/STM32F1/variants/STM32VLD/wirish/start.S
@@ -0,0 +1,57 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/*
+ * This file is a modified version of a file obtained from
+ * CodeSourcery Inc. (now part of Mentor Graphics Corp.), in which the
+ * following text appeared:
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+        .text
+        .code 16
+        .thumb_func
+
+        .globl __start__
+        .type __start__, %function
+__start__:
+        .fnstart
+        ldr r1,=__msp_init
+        mov sp,r1
+        ldr r1,=start_c
+        bx r1
+        .pool
+        .cantunwind
+        .fnend
diff --git a/STM32F1/variants/STM32VLD/wirish/start_c.c b/STM32F1/variants/STM32VLD/wirish/start_c.c
new file mode 100644
index 000000000..05df0602e
--- /dev/null
+++ b/STM32F1/variants/STM32VLD/wirish/start_c.c
@@ -0,0 +1,95 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/*
+ * This file is a modified version of a file obtained from
+ * CodeSourcery Inc. (now part of Mentor Graphics Corp.), in which the
+ * following text appeared:
+ *
+ * Copyright (c) 2006, 2007 CodeSourcery Inc
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+#include <stddef.h>
+
+extern void __libc_init_array(void);
+
+extern int main(int, char**, char**);
+
+extern void exit(int) __attribute__((noreturn, weak));
+
+/* The linker must ensure that these are at least 4-byte aligned. */
+extern char __data_start__, __data_end__;
+extern char __bss_start__, __bss_end__;
+
+struct rom_img_cfg {
+    int *img_start;
+};
+
+extern char _lm_rom_img_cfgp;
+
+void __attribute__((noreturn)) start_c(void) {
+    struct rom_img_cfg *img_cfg = (struct rom_img_cfg*)&_lm_rom_img_cfgp;
+    int *src = img_cfg->img_start;
+    int *dst = (int*)&__data_start__;
+    int exit_code;
+
+    /* Initialize .data, if necessary. */
+    if (src != dst) {
+        int *end = (int*)&__data_end__;
+        while (dst < end) {
+            *dst++ = *src++;
+        }
+    }
+
+    /* Zero .bss. */
+    dst = (int*)&__bss_start__;
+    while (dst < (int*)&__bss_end__) {
+        *dst++ = 0;
+    }
+
+    /* Run initializers. */
+    __libc_init_array();
+
+    /* Jump to main. */
+    exit_code = main(0, 0, 0);
+    if (exit) {
+        exit(exit_code);
+    }
+
+    /* If exit is NULL, make sure we don't return. */
+    for (;;)
+        continue;
+}
diff --git a/STM32F1/variants/STM32VLD/wirish/syscalls.c b/STM32F1/variants/STM32VLD/wirish/syscalls.c
new file mode 100644
index 000000000..d42536c58
--- /dev/null
+++ b/STM32F1/variants/STM32VLD/wirish/syscalls.c
@@ -0,0 +1,176 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Perry Hung.
+ * Copyright (c) 2011, 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file wirish/syscalls.c
+ * @brief newlib stubs
+ *
+ * Low level system routines used by newlib for basic I/O and memory
+ * allocation. You can override most of these.
+ */
+
+#include <libmaple/libmaple.h>
+
+#include <sys/stat.h>
+#include <errno.h>
+#include <stddef.h>
+
+/* If CONFIG_HEAP_START (or CONFIG_HEAP_END) isn't defined, then
+ * assume _lm_heap_start (resp. _lm_heap_end) is appropriately set by
+ * the linker */
+#ifndef CONFIG_HEAP_START
+extern char _lm_heap_start;
+#define CONFIG_HEAP_START               ((void *)&_lm_heap_start)
+#endif
+#ifndef CONFIG_HEAP_END
+extern char _lm_heap_end;
+#define CONFIG_HEAP_END                 ((void *)&_lm_heap_end)
+#endif
+
+/*
+ * _sbrk -- Increment the program break.
+ *
+ * Get incr bytes more RAM (for use by the heap).  malloc() and
+ * friends call this function behind the scenes.
+ */
+void *_sbrk(int incr) {
+    static void * pbreak = NULL; /* current program break */
+    void * ret;
+
+    if (pbreak == NULL) {
+        pbreak = CONFIG_HEAP_START;
+    }
+
+    if ((CONFIG_HEAP_END - pbreak < incr) ||
+        (pbreak - CONFIG_HEAP_START < -incr)) {
+        errno = ENOMEM;
+        return (void *)-1;
+    }
+
+    ret = pbreak;
+    pbreak += incr;
+    return ret;
+}
+
+__weak int _open(const char *path, int flags, ...) {
+    return 1;
+}
+
+__weak int _close(int fd) {
+    return 0;
+}
+
+__weak int _fstat(int fd, struct stat *st) {
+    st->st_mode = S_IFCHR;
+    return 0;
+}
+
+__weak int _isatty(int fd) {
+    return 1;
+}
+
+__weak int isatty(int fd) {
+    return 1;
+}
+
+__weak int _lseek(int fd, off_t pos, int whence) {
+    return -1;
+}
+
+__weak unsigned char getch(void) {
+    return 0;
+}
+
+
+__weak int _read(int fd, char *buf, size_t cnt) {
+    *buf = getch();
+
+    return 1;
+}
+
+__weak void putch(unsigned char c) {
+}
+
+__weak void cgets(char *s, int bufsize) {
+    char *p;
+    int c;
+    int i;
+
+    for (i = 0; i < bufsize; i++) {
+        *(s+i) = 0;
+    }
+//    memset(s, 0, bufsize);
+
+    p = s;
+
+    for (p = s; p < s + bufsize-1;) {
+        c = getch();
+        switch (c) {
+        case '\r' :
+        case '\n' :
+            putch('\r');
+            putch('\n');
+            *p = '\n';
+            return;
+
+        case '\b' :
+            if (p > s) {
+                *p-- = 0;
+                putch('\b');
+                putch(' ');
+                putch('\b');
+            }
+            break;
+
+        default :
+            putch(c);
+            *p++ = c;
+            break;
+        }
+    }
+    return;
+}
+
+__weak int _write(int fd, const char *buf, size_t cnt) {
+    int i;
+
+    for (i = 0; i < cnt; i++)
+        putch(buf[i]);
+
+    return cnt;
+}
+
+/* Override fgets() in newlib with a version that does line editing */
+__weak char *fgets(char *s, int bufsize, void *f) {
+    cgets(s, bufsize);
+    return s;
+}
+
+__weak void _exit(int exitcode) {
+    while (1)
+        ;
+}

From 6266342b1deea3d18dc4b6e9087b160c3807abc7 Mon Sep 17 00:00:00 2001
From: Phisatho <phisatho@gmail.com>
Date: Fri, 18 Nov 2016 02:33:59 +0400
Subject: [PATCH 015/307] Update boards.txt

---
 STM32F1/boards.txt | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/STM32F1/boards.txt b/STM32F1/boards.txt
index 8cbd57b63..95a5f8635 100644
--- a/STM32F1/boards.txt
+++ b/STM32F1/boards.txt
@@ -580,3 +580,34 @@ genericGD32F103C.menu.cpu_speed.speed_96mhz.build.f_cpu=96000000L
 
 genericGD32F103C.menu.cpu_speed.speed_72mhz=72Mhz (compatibility)
 genericGD32F103C.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
+
+########################### STM32VLD to FLASH ###########################
+
+STM32VLD.name=STM32VLD to FLASH
+#STM32VLD.vid.0=0x1EAF
+#STM32VLD.pid.0=0x0004
+
+STM32VLD.build.vect=VECT_TAB_ADDR=0x8000000
+STM32VLD.build.core=maple
+STM32VLD.build.board=STM32VLD
+STM32VLD.build.variant=STM32VLD
+STM32VLD.build.ldscript=ld/jtag.ld
+
+STM32VLD.build.family=cortex-m3
+STM32VLD.build.f_cpu=24000000L
+STM32VLD.upload.use_1200bps_touch=false
+STM32VLD.upload.file_type=bin
+STM32VLD.upload.auto_reset=true
+STM32VLD.upload.params.quiet=no
+
+STM32VLD.build.cpu_flags=-DMCU_STM32F100RB
+##---------------------------- UPLOAD METHODS ---------------------------
+
+
+STM32VLD.menu.upload_method.STLinkMethod=STLink
+STM32VLD.menu.upload_method.STLinkMethod.upload.protocol=STLink
+STM32VLD.menu.upload_method.STLinkMethod.upload.tool=stlink_upload
+STM32VLD.menu.upload_method.STLinkMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG  
+
+
+################################################################################

From 69413ee56e062a24de04bdae0d3385fb7f66248f Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sun, 27 Nov 2016 10:10:42 +1100
Subject: [PATCH 016/307] Update InternalTempSensor.ino

Fixed issue caused by https://github.com/rogerclarkmelbourne/Arduino_STM32/pull/132/files
---
 .../examples/General/InternalTempSensor/InternalTempSensor.ino  | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/libraries/A_STM32_Examples/examples/General/InternalTempSensor/InternalTempSensor.ino b/STM32F1/libraries/A_STM32_Examples/examples/General/InternalTempSensor/InternalTempSensor.ino
index e207a3166..d6000cdf8 100644
--- a/STM32F1/libraries/A_STM32_Examples/examples/General/InternalTempSensor/InternalTempSensor.ino
+++ b/STM32F1/libraries/A_STM32_Examples/examples/General/InternalTempSensor/InternalTempSensor.ino
@@ -19,7 +19,7 @@ void setup_temperature_sensor() {
 //    temperature sensor from power down mode.  Do this first 'cause according to
 //    the Datasheet section 5.3.21 it takes from 4 to 10 uS to power up the sensor.
 
-  regs->CR2 |= ADC_CR2_TSEREFE;
+  regs->CR2 |= ADC_CR2_TSVREFE;
 
 // 2. Select a sample time of 17.1 μs
 // set channel 16 sample time to 239.5 cycles

From a6999719d77773f674e7a525eefd4007cc90c254 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Mon, 28 Nov 2016 17:57:42 +1100
Subject: [PATCH 017/307] STM32F4 add Export compile binary option

---
 STM32F4/platform.txt | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/STM32F4/platform.txt b/STM32F4/platform.txt
index 91aeca91e..7d5395991 100755
--- a/STM32F4/platform.txt
+++ b/STM32F4/platform.txt
@@ -96,6 +96,10 @@ recipe.size.pattern="{compiler.path}{compiler.size.cmd}" -A "{build.path}/{build
 recipe.size.regex=^(?:\.text|\.rodata|\.ARM.exidx)\s+([0-9]+).*
 recipe.size.regex.data=^(?:\.data|\.bss|\.noinit)\s+([0-9]+).*
 
+## Save Compiled Binary
+recipe.output.tmp_file={build.project_name}.bin
+recipe.output.save_file={build.project_name}.{build.variant}.bin
+
 # Uploader tools
 # -------------------
 

From dbcba3e01225222a7dad284fcbe819d653a63dd7 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Mon, 28 Nov 2016 19:47:43 +1100
Subject: [PATCH 018/307] STM32F4 fixed issue with stlink uploads, and added
 windows driver bat for STM Virtual com ports

---
 STM32F4/boards.txt   |  2 +-
 STM32F4/platform.txt | 26 ++++++--------------------
 2 files changed, 7 insertions(+), 21 deletions(-)

diff --git a/STM32F4/boards.txt b/STM32F4/boards.txt
index 453d520db..7577d1949 100644
--- a/STM32F4/boards.txt
+++ b/STM32F4/boards.txt
@@ -3,7 +3,7 @@
 ##############################################################
 discovery_f407.name=STM32 Discovery F407
 
-discovery_f407.upload.tool=stlink
+discovery_f407.upload.tool=stlink_upload
 discovery_f407.upload.protocol=stlink
 
 #discovery_f407.upload.use_1200bps_touch=false
diff --git a/STM32F4/platform.txt b/STM32F4/platform.txt
index 7d5395991..99ae55549 100755
--- a/STM32F4/platform.txt
+++ b/STM32F4/platform.txt
@@ -117,28 +117,14 @@ tools.maple_upload.upload.pattern="{path}/{cmd}" {serial.port.file} {upload.altI
 # Generic STM32 upload via serial to Serial Port 1 (pins PA9 and PA10) - note. Boot0 line needs to high on board reset to enable upload via serial
 # at the end of the upload the program is automatically run, without the board being reset
 
-tools.serial_upload.cmd=serial_upload
-tools.serial_upload.cmd.windows=serial_upload.bat
-tools.serial_upload.cmd.macosx=serial_upload
-tools.serial_upload.path={runtime.hardware.path}/tools/win
-tools.serial_upload.path.macosx={runtime.hardware.path}/tools/macosx
-tools.serial_upload.path.linux={runtime.hardware.path}/tools/linux
-tools.serial_upload.path.linux64={runtime.hardware.path}/tools/linux64
-tools.serial_upload.upload.params.verbose=-d
-tools.serial_upload.upload.params.quiet=
-tools.serial_upload.upload.pattern="{path}/{cmd}" {serial.port.file} {upload.altID} {upload.usbID} "{build.path}/{build.project_name}.bin"
-
-# STLINK/V2
-
-tools.stlink.cmd=stlink_upload
-tools.stlink.cmd.windows=stlink_upload.bat
+# stlink upload
+tools.stlink_upload.cmd=stlink_upload
+tools.stlink_upload.cmd.windows=stlink_upload.bat
 tools.stlink_upload.path.windows={runtime.hardware.path}/tools/win
 tools.stlink_upload.path.macosx={runtime.hardware.path}/tools/macosx
 tools.stlink_upload.path.linux={runtime.hardware.path}/tools/linux
 tools.stlink_upload.path.linux64={runtime.hardware.path}/tools/linux64
-tools.stlink.path.linux={runtime.hardware.path}/tools/linux/
-tools.stlink.path.macosx={runtime.hardware.path}/tools/macosx/
-tools.stlink.upload.params.verbose=-d
-tools.stlink.upload.params.quiet=
-tools.stlink.upload.pattern="{path}/{cmd}" {serial.port.file} {upload.altID} {upload.usbID} "{build.path}/{build.project_name}.bin"
+tools.stlink_upload.upload.params.verbose=-d
+tools.stlink_upload.upload.params.quiet=
+tools.stlink_upload.upload.pattern="{path}/{cmd}" {serial.port.file} {upload.altID} {upload.usbID} "{build.path}/{build.project_name}.bin"
  

From 794d078de080054ea39095f8980bdcc2de9f3020 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Tue, 29 Nov 2016 15:17:01 +1100
Subject: [PATCH 019/307] fixed problem in last 2 commits with windows bat for
 STM32 com

---
 drivers/win/install_STM_COM_drivers.bat | 8 ++++++++
 1 file changed, 8 insertions(+)
 create mode 100644 drivers/win/install_STM_COM_drivers.bat

diff --git a/drivers/win/install_STM_COM_drivers.bat b/drivers/win/install_STM_COM_drivers.bat
new file mode 100644
index 000000000..eb57c2b00
--- /dev/null
+++ b/drivers/win/install_STM_COM_drivers.bat
@@ -0,0 +1,8 @@
+@echo off
+
+echo Installing STM Serial driver...
+"%~dp0wdi-simple" --vid 0x0483 --pid 0x5740 --type 3 --name "STM Serial" --dest "%~dp0maple-serial"
+echo.
+
+pause
+

From 71a1121c9f4f9102f6ec107ae6986dfbd2e51cc3 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Tue, 29 Nov 2016 15:18:16 +1100
Subject: [PATCH 020/307] Fixed issue with tone files not actually being added
 to the repo in a previous commit

---
 STM32F1/cores/maple/tone.cpp | 194 +++++++++++++++++++++++++++++++++++
 STM32F1/cores/maple/tone.h   |  28 +++++
 2 files changed, 222 insertions(+)
 create mode 100644 STM32F1/cores/maple/tone.cpp
 create mode 100644 STM32F1/cores/maple/tone.h

diff --git a/STM32F1/cores/maple/tone.cpp b/STM32F1/cores/maple/tone.cpp
new file mode 100644
index 000000000..5fd4a3978
--- /dev/null
+++ b/STM32F1/cores/maple/tone.cpp
@@ -0,0 +1,194 @@
+///////////////////////////////////////////////////////////////////////
+//
+// tone(pin,frequency[,duration])     generate a tone on a given pin
+//
+// noTone(pin)                        switch off the tone on the pin
+//
+// setToneTimerChannel(timer,channel) force use of given timer/channel
+//
+///////////////////////////////////////////////////////////////////////
+
+#include "Arduino.h"
+#include <HardwareTimer.h>
+
+// define default timer and channel
+#ifndef TONE_TIMER
+#define TONE_TIMER 4
+#endif
+#ifndef TONE_CHANNEL
+#define TONE_CHANNEL 4
+#endif
+
+#define PinTimer(pin) (PIN_MAP[pin].timer_device->clk_id-RCC_TIMER1+1)
+#define PinChannel(pin) (PIN_MAP[pin].timer_channel)
+
+// if USE_PIN_TIMER is set, the PWM timer/channel is used for PWM pins
+#define USE_PIN_TIMER
+
+// if USE_BSRR is set the tone pin will be written via the fast BSRR register
+// instead of using the slow digitalWrite() function in the interrupt handler
+#define USE_BSRR
+
+// construct static timer array (
+HardwareTimer TTimer1(1), TTimer2(2), TTimer3(3), TTimer4(4);
+#ifdef STM32_HIGH_DENSITY
+HardwareTimer TTimer5(5), TTimer6(6), TTimer7(7), TTimer8(8);
+#endif
+HardwareTimer *TTimer[4] {
+   &TTimer1,&TTimer2,&TTimer3,&TTimer4
+#ifdef STM32_HIGH_DENSITY
+  ,&TTimer5,&TTimer6,&TTimer7,&TTimer8
+#endif
+   };
+
+uint8_t tone_force_channel = 0;                 // forced timer channel
+uint8_t tone_force_ntimer = 0;                  // forced timer
+
+HardwareTimer *tone_timer = TTimer[TONE_TIMER]; // timer used to generate frequency
+uint8_t tone_channel = TONE_CHANNEL;            // timer channel used to generate frequency
+uint8_t tone_ntimer = TONE_TIMER;               // timer used to generate frequency
+
+bool tone_state = true;             // last pin state for toggling
+short tone_pin = -1;                // pin for outputting sound
+short tone_freq = 444;              // tone frequency (0=pause)
+uint32_t tone_nhw = 0;              // tone duration in number of half waves
+uint16_t tone_tcount = 0;           // time between handler calls in 1/36 usec
+uint16_t tone_ncount = 0;           // handler call between toggling
+uint16_t tone_n = 0;                // remaining handler calls before toggling
+uint32_t tone_next = 0;             // counter value of next interrupt
+
+#ifdef USE_BSRR
+volatile uint32_t *tone_bsrr;       // BSRR set register (lower 16 bits)
+uint32_t tone_smask=0;              // BSRR set bitmask
+uint32_t tone_rmask=0;              // BSRR reset bitmask
+#endif
+ 
+
+////////////////////////////////////////////////////////////////////////////////
+// timer hander for tone with no duration specified,
+// will keep going until noTone() is called
+void tone_handler_1(void) {
+   tone_next += tone_tcount;            // comparator value for next interrupt
+   tone_timer->setCompare(tone_channel, tone_next); // and install it
+   if(--tone_n == 0){
+      tone_state = !tone_state;         // toggle tone output
+
+#ifdef USE_BSRR
+      if(tone_state)
+         *tone_bsrr = tone_smask;
+      else
+         *tone_bsrr = tone_rmask;
+#else
+      digitalWrite(tone_pin,tone_state);// and output it
+#endif
+
+      tone_n = tone_ncount;             // reset interrupt counter
+   }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// timer hander for tone with a specified duration,
+// will stop automatically when duration time is up.
+void tone_handler_2(void) {
+   tone_next += tone_tcount;
+   tone_timer->setCompare(tone_channel, tone_next);
+   if(--tone_n == 0){
+      if(tone_freq>0){ // toggle pin
+         tone_state = !tone_state;
+#ifdef USE_BSRR
+         if(tone_state)
+            *tone_bsrr = tone_smask;
+         else
+            *tone_bsrr = tone_rmask;
+#else
+         digitalWrite(tone_pin,tone_state);// and output it
+#endif
+       }
+       tone_n = tone_ncount;
+       if(!--tone_nhw){ // check if tone duration has finished
+          tone_timer->pause();       // disable timer
+          pinMode(tone_pin, INPUT); // disable tone pin
+       }
+    }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+//  play a tone on given pin with given frequency and optional duration in msec
+void tone(uint32_t pin, uint32_t freq, uint32_t duration) {
+   tone_pin = pin;
+
+#ifdef USE_PIN_TIMER
+   // if the pin has a PWM timer/channel, use it (unless the timer/channel are forced)
+   if(PinChannel(tone_pin) && !tone_force_channel){
+      tone_channel = PinChannel(tone_pin);
+      tone_ntimer = PinTimer(tone_pin);
+   } else
+#endif
+   {
+      // set timer and channel to default resp values forced with setToneTimerChannel
+      tone_ntimer = tone_force_channel?tone_force_ntimer:TONE_TIMER;
+      tone_channel = tone_force_channel?tone_force_channel:TONE_CHANNEL;
+   }
+
+   tone_timer = TTimer[tone_ntimer-1];
+   tone_freq = freq;
+   tone_nhw = 0;
+   tone_next = 0;
+
+   tone_timer->pause();
+
+   if(freq > 0 || duration >0 ){
+      uint32_t count = 18000000/freq;       // timer counts per half wave
+      tone_ncount = tone_n = (count>>16)+1; // number of 16-bit count chunk
+      tone_tcount = count/tone_ncount;      // size of count chunk
+      if(duration > 0) // number of half waves to be generated
+         tone_nhw = ((duration*(freq>0?freq:100))/1000)<<1;
+      else  // no duration specified, continuous sound until noTone() called
+         tone_nhw = 0;
+
+      pinMode(tone_pin, PWM);    // configure output pin
+      pinMode(tone_pin, OUTPUT); // configure output pin
+
+#ifdef USE_BSRR
+      // Set up BSRR register values for fast ISR
+      tone_bsrr = &((PIN_MAP[tone_pin].gpio_device)->regs->BSRR);
+      tone_smask = (BIT(PIN_MAP[tone_pin].gpio_bit));
+      tone_rmask = tone_smask<<16;
+#endif
+
+      // Set up an interrupt on given timer and channel
+      tone_next = tone_tcount; // prepare channel compare register
+      tone_timer->setMode(tone_channel,TIMER_OUTPUT_COMPARE);
+      tone_timer->setCompare(tone_channel,tone_next);
+      // attach corresponding handler routine
+      tone_timer->attachInterrupt(tone_channel,tone_nhw?tone_handler_2:tone_handler_1);
+
+      // Refresh the tone timer
+      tone_timer->refresh();
+
+      // Start the timer counting
+      tone_timer->resume();
+     
+   } else {
+
+      // detach handler routine
+      tone_timer->detachInterrupt(tone_channel);
+      // disactive pin by configuring it as input
+      pinMode(tone_pin, INPUT);
+
+   }
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// disable tone on specified pin, if any
+void noTone(uint32_t pin){
+    tone(pin,-1);  // it's all handled in tone()
+}
+
+////////////////////////////////////////////////////////////////////////////////
+// set timer and channel to some different value
+// must be called before calling tone() or after noTone() was called
+void setToneTimerChannel(uint8_t ntimer, uint8_t channel){
+   tone_force_ntimer = ntimer;
+   tone_force_channel = channel;
+}
diff --git a/STM32F1/cores/maple/tone.h b/STM32F1/cores/maple/tone.h
new file mode 100644
index 000000000..cf2705160
--- /dev/null
+++ b/STM32F1/cores/maple/tone.h
@@ -0,0 +1,28 @@
+/*
+  Copyright (c) 2015 Arduino LLC.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#pragma once
+
+#ifdef __cplusplus
+
+#include "Arduino.h"
+
+void tone(uint32_t _pin, uint32_t frequency, uint32_t duration = 0);
+void noTone(uint32_t _pin);
+
+#endif

From 20fa7b4f302b2630d96be07161f64f0fba1732c2 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Tue, 29 Nov 2016 15:52:16 +1100
Subject: [PATCH 021/307] Fixed issue with tone not compiling

---
 STM32F1/cores/maple/tone.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/cores/maple/tone.cpp b/STM32F1/cores/maple/tone.cpp
index 5fd4a3978..bfd4c0386 100644
--- a/STM32F1/cores/maple/tone.cpp
+++ b/STM32F1/cores/maple/tone.cpp
@@ -182,7 +182,7 @@ void tone(uint32_t pin, uint32_t freq, uint32_t duration) {
 ////////////////////////////////////////////////////////////////////////////////
 // disable tone on specified pin, if any
 void noTone(uint32_t pin){
-    tone(pin,-1);  // it's all handled in tone()
+   tone(pin,-1,0);  // it's all handled in tone()
 }
 
 ////////////////////////////////////////////////////////////////////////////////

From a1f154bc3772ebf7c8f7e1afa4a69c4289406492 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Wed, 30 Nov 2016 09:45:16 +1100
Subject: [PATCH 022/307] Added newer dfu-util for F4 DFU testing

---
 tools/win/dfu-util-0.9-win64/README.txt       |  26 ++++++++++++++++++
 tools/win/dfu-util-0.9-win64/dfu-prefix.exe   | Bin 0 -> 178765 bytes
 tools/win/dfu-util-0.9-win64/dfu-suffix.exe   | Bin 0 -> 179276 bytes
 .../dfu-util-0.9-win64/dfu-util-manual.pdf    | Bin 0 -> 10602 bytes
 .../dfu-util-0.9-win64/dfu-util-static.exe    | Bin 0 -> 799602 bytes
 tools/win/dfu-util-0.9-win64/dfu-util.exe     | Bin 0 -> 290852 bytes
 tools/win/dfu-util-0.9-win64/libusb-1.0.dll   | Bin 0 -> 638611 bytes
 7 files changed, 26 insertions(+)
 create mode 100644 tools/win/dfu-util-0.9-win64/README.txt
 create mode 100644 tools/win/dfu-util-0.9-win64/dfu-prefix.exe
 create mode 100644 tools/win/dfu-util-0.9-win64/dfu-suffix.exe
 create mode 100644 tools/win/dfu-util-0.9-win64/dfu-util-manual.pdf
 create mode 100644 tools/win/dfu-util-0.9-win64/dfu-util-static.exe
 create mode 100644 tools/win/dfu-util-0.9-win64/dfu-util.exe
 create mode 100644 tools/win/dfu-util-0.9-win64/libusb-1.0.dll

diff --git a/tools/win/dfu-util-0.9-win64/README.txt b/tools/win/dfu-util-0.9-win64/README.txt
new file mode 100644
index 000000000..5aa2e67ed
--- /dev/null
+++ b/tools/win/dfu-util-0.9-win64/README.txt
@@ -0,0 +1,26 @@
+dfu-util 0.9
+
+These binaries are for Microsoft Windows 64-bit
+
+They were built using MinGW-64 from MSYS2 with gcc 5.3.0,
+for build instructions please see:
+http://dfu-util.sourceforge.net/build.html
+
+Source code:
+https://sourceforge.net/p/dfu-util/dfu-util/ci/v0.9/tree/
+
+dfu-util.exe requires libusb-1.0.dll. The shipped libusb-1.0.dll
+is built from libusb 1.0.20 and can be replaced with another
+version if desired.
+
+dfu-util-static.exe has the libusb 1.0.20 code embedded and runs
+without any libusb-1.0.dll.
+
+Notes:
+1. To work around a bug in gcc/mingw, a small patch was applied, see
+   https://sourceforge.net/p/dfu-util/tickets/13/
+2. The dfu-util-static.exe includes libusb that has been patched
+   to work around a silicon bug in STM32F42X devices:
+   https://github.com/axoloti/axoloti/blob/master/platform_osx/src/libusb.stdfu.patch
+
+2016-02-11 Tormod Volden
diff --git a/tools/win/dfu-util-0.9-win64/dfu-prefix.exe b/tools/win/dfu-util-0.9-win64/dfu-prefix.exe
new file mode 100644
index 0000000000000000000000000000000000000000..5ae088804979feab4339592abc9c90e694d2b516
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diff --git a/tools/win/dfu-util-0.9-win64/dfu-suffix.exe b/tools/win/dfu-util-0.9-win64/dfu-suffix.exe
new file mode 100644
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diff --git a/tools/win/dfu-util-0.9-win64/dfu-util-manual.pdf b/tools/win/dfu-util-0.9-win64/dfu-util-manual.pdf
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diff --git a/tools/win/dfu-util-0.9-win64/dfu-util-static.exe b/tools/win/dfu-util-0.9-win64/dfu-util-static.exe
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diff --git a/tools/win/dfu-util-0.9-win64/dfu-util.exe b/tools/win/dfu-util-0.9-win64/dfu-util.exe
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diff --git a/tools/win/dfu-util-0.9-win64/libusb-1.0.dll b/tools/win/dfu-util-0.9-win64/libusb-1.0.dll
new file mode 100644
index 0000000000000000000000000000000000000000..c8d77172b4c60ae807aaaafd5391acd0066d43c8
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literal 0
HcmV?d00001


From 9237d3afc837b818eeaf50a97cc8912a824d80b7 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Wed, 30 Nov 2016 10:14:27 +1100
Subject: [PATCH 023/307] Add new.cpp from Arduino SAMD to resolve issue with
 new operator pulling in loads of library functions and taking loads of flash

---
 STM32F1/cores/maple/new.cpp | 36 ++++++++++++++++++++++++++++++++++++
 1 file changed, 36 insertions(+)
 create mode 100644 STM32F1/cores/maple/new.cpp

diff --git a/STM32F1/cores/maple/new.cpp b/STM32F1/cores/maple/new.cpp
new file mode 100644
index 000000000..f18977585
--- /dev/null
+++ b/STM32F1/cores/maple/new.cpp
@@ -0,0 +1,36 @@
+/*
+  Copyright (c) 2014 Arduino.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include <stdlib.h>
+
+void *operator new(size_t size) {
+  return malloc(size);
+}
+
+void *operator new[](size_t size) {
+  return malloc(size);
+}
+
+void operator delete(void * ptr) {
+  free(ptr);
+}
+
+void operator delete[](void * ptr) {
+  free(ptr);
+}
+

From 378cd2a6af43a360c5a7d20979863150f516f5f7 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Wed, 30 Nov 2016 17:27:21 +1100
Subject: [PATCH 024/307] Fixed #231

---
 STM32F1/cores/maple/Print.cpp | 4 +---
 STM32F4/cores/maple/Print.cpp | 4 +---
 2 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/STM32F1/cores/maple/Print.cpp b/STM32F1/cores/maple/Print.cpp
index cd371cb0f..76f386b78 100644
--- a/STM32F1/cores/maple/Print.cpp
+++ b/STM32F1/cores/maple/Print.cpp
@@ -126,9 +126,7 @@ size_t Print::print(double n, int digits) {
 
 size_t Print::print(const __FlashStringHelper *ifsh)
 {
-  size_t n = print(ifsh);
-  n += println();
-  return n;
+  return print(reinterpret_cast<const char *>(ifsh));
 }
 
 size_t Print::print(const Printable& x)
diff --git a/STM32F4/cores/maple/Print.cpp b/STM32F4/cores/maple/Print.cpp
index cd371cb0f..76f386b78 100644
--- a/STM32F4/cores/maple/Print.cpp
+++ b/STM32F4/cores/maple/Print.cpp
@@ -126,9 +126,7 @@ size_t Print::print(double n, int digits) {
 
 size_t Print::print(const __FlashStringHelper *ifsh)
 {
-  size_t n = print(ifsh);
-  n += println();
-  return n;
+  return print(reinterpret_cast<const char *>(ifsh));
 }
 
 size_t Print::print(const Printable& x)

From ed82be4c6e4fbd1e6b393fdd598e36f62cd9d22d Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Fri, 2 Dec 2016 10:32:17 +1100
Subject: [PATCH 025/307] Updated Linux 45-maple.rules

See http://stm32duino.com/viewtopic.php?f=16&t=1103&start=40#p20732
---
 tools/linux/45-maple.rules | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/tools/linux/45-maple.rules b/tools/linux/45-maple.rules
index d1bda5fb1..e53d9690b 100644
--- a/tools/linux/45-maple.rules
+++ b/tools/linux/45-maple.rules
@@ -1,5 +1,5 @@
 ATTRS{idProduct}=="1001", ATTRS{idVendor}=="0110", MODE="664", GROUP="plugdev"
 ATTRS{idProduct}=="1002", ATTRS{idVendor}=="0110", MODE="664", GROUP="plugdev"
-ATTRS{idProduct}=="0003", ATTRS{idVendor}=="1eaf", MODE="664", GROUP="plugdev" SYMLINK+="maple"
-ATTRS{idProduct}=="0004", ATTRS{idVendor}=="1eaf", MODE="664", GROUP="plugdev" SYMLINK+="maple"
+ATTRS{idProduct}=="0003", ATTRS{idVendor}=="1eaf", MODE="664", GROUP="plugdev" SYMLINK+="maple", ENV{ID_MM_DEVICE_IGNORE}="1"
+ATTRS{idProduct}=="0004", ATTRS{idVendor}=="1eaf", MODE="664", GROUP="plugdev" SYMLINK+="maple", ENV{ID_MM_DEVICE_IGNORE}="1"
 

From 2e54594f46255653f6588ebfa312d0d38d93ac47 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Fri, 2 Dec 2016 21:24:13 +1100
Subject: [PATCH 026/307] Added #define LED_BUILTIN to Maple mini and
 generic_STM32F103C

---
 STM32F1/variants/generic_stm32f103c/variant.h | 2 ++
 STM32F1/variants/maple_mini/variant.h         | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/STM32F1/variants/generic_stm32f103c/variant.h b/STM32F1/variants/generic_stm32f103c/variant.h
index 52b39a629..4a9cfcd19 100644
--- a/STM32F1/variants/generic_stm32f103c/variant.h
+++ b/STM32F1/variants/generic_stm32f103c/variant.h
@@ -17,4 +17,6 @@ static const uint8_t MOSI = BOARD_SPI1_MOSI_PIN;
 static const uint8_t MISO = BOARD_SPI1_MISO_PIN;
 static const uint8_t SCK  = BOARD_SPI1_SCK_PIN;
 
+#define LED_BUILTIN PC13
+
 #endif /* _VARIANT_ARDUINO_STM32_ */
\ No newline at end of file
diff --git a/STM32F1/variants/maple_mini/variant.h b/STM32F1/variants/maple_mini/variant.h
index 8a88623e7..22a77ceb6 100644
--- a/STM32F1/variants/maple_mini/variant.h
+++ b/STM32F1/variants/maple_mini/variant.h
@@ -17,4 +17,6 @@ static const uint8_t MOSI = BOARD_SPI1_MOSI_PIN;
 static const uint8_t MISO = BOARD_SPI1_MISO_PIN;
 static const uint8_t SCK  = BOARD_SPI1_SCK_PIN;
 
+#define LED_BUILTIN PB1
+
 #endif /* _VARIANT_ARDUINO_STM32_ */
\ No newline at end of file

From e71d176618b8b77c727af0891343a278246016fd Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Fri, 2 Dec 2016 21:33:01 +1100
Subject: [PATCH 027/307] Fixed issue with tone for high density devices

---
 STM32F1/cores/maple/tone.cpp | 9 +++++----
 1 file changed, 5 insertions(+), 4 deletions(-)

diff --git a/STM32F1/cores/maple/tone.cpp b/STM32F1/cores/maple/tone.cpp
index bfd4c0386..2bb11e5d3 100644
--- a/STM32F1/cores/maple/tone.cpp
+++ b/STM32F1/cores/maple/tone.cpp
@@ -34,12 +34,13 @@ HardwareTimer TTimer1(1), TTimer2(2), TTimer3(3), TTimer4(4);
 #ifdef STM32_HIGH_DENSITY
 HardwareTimer TTimer5(5), TTimer6(6), TTimer7(7), TTimer8(8);
 #endif
-HardwareTimer *TTimer[4] {
-   &TTimer1,&TTimer2,&TTimer3,&TTimer4
+
 #ifdef STM32_HIGH_DENSITY
-  ,&TTimer5,&TTimer6,&TTimer7,&TTimer8
+	HardwareTimer *TTimer[8] { &TTimer1,&TTimer2,&TTimer3,&TTimer4,&TTimer5,&TTimer6,&TTimer7,&TTimer8 };
+#else
+	HardwareTimer *TTimer[4] { &TTimer1,&TTimer2,&TTimer3,&TTimer4 };
 #endif
-   };
+
 
 uint8_t tone_force_channel = 0;                 // forced timer channel
 uint8_t tone_force_ntimer = 0;                  // forced timer

From 3759f2e6ae48892449d29ef84f135f9ae9090163 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Wed, 7 Dec 2016 19:55:44 +1100
Subject: [PATCH 028/307] Changed Arduino IDE version info to bring up to date

---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 70e20006c..019cb2b26 100644
--- a/README.md
+++ b/README.md
@@ -9,7 +9,7 @@ Use of these files is at your own risk.
 
 
 ##Summary:  
-This repo contains, the "Hardware" files to support STM32 based boards on Arduino version 1.6.4 and 1.6.5, and 1.6.9  including [LeafLabs Maple, and Maple mini](http://www.leaflabs.com/about-maple/), and other generic STM32F103 boards  
+This repo contains, the "Hardware" files to support STM32 based boards on Arduino version 1.6.13 or 1.6.12 (some older versions may also work)  including [LeafLabs Maple, and Maple mini](http://www.leaflabs.com/about-maple/), and other generic STM32F103 boards  
 
 ***PRIMARY SUPPORT FORUM: http://www.stm32duino.com/***
 

From dd453357b337d5a888370f708eb304ecc6603ec9 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Thu, 8 Dec 2016 20:00:20 +1100
Subject: [PATCH 029/307] Added shiftIn to F1 and F4

---
 STM32F1/cores/maple/io.h             |  2 ++
 STM32F1/cores/maple/wirish_shift.cpp | 25 +++++++++++++++++++++++++
 STM32F4/cores/maple/io.h             |  2 ++
 STM32F4/cores/maple/wirish_shift.cpp | 25 +++++++++++++++++++++++++
 4 files changed, 54 insertions(+)

diff --git a/STM32F1/cores/maple/io.h b/STM32F1/cores/maple/io.h
index ce5446108..5c8ab0e2e 100644
--- a/STM32F1/cores/maple/io.h
+++ b/STM32F1/cores/maple/io.h
@@ -160,4 +160,6 @@ uint16 analogRead(uint8 pin);
  */
 void shiftOut(uint8 dataPin, uint8 clockPin, uint8 bitOrder, uint8 value);
 
+uint32 shiftIn( uint32 ulDataPin, uint32 ulClockPin, uint32 ulBitOrder );
+
 #endif
diff --git a/STM32F1/cores/maple/wirish_shift.cpp b/STM32F1/cores/maple/wirish_shift.cpp
index 2825507c3..b5aba0c97 100644
--- a/STM32F1/cores/maple/wirish_shift.cpp
+++ b/STM32F1/cores/maple/wirish_shift.cpp
@@ -35,3 +35,28 @@ void shiftOut(uint8 dataPin, uint8 clockPin, uint8 bitOrder, uint8 value) {
 		gpio_toggle_bit(PIN_MAP[clockPin].gpio_device, PIN_MAP[clockPin].gpio_bit);// togglePin(clockPin);  
     }
 }
+
+uint32_t shiftIn( uint32_t ulDataPin, uint32_t ulClockPin, uint32_t ulBitOrder )
+{
+  uint8_t value = 0 ;
+  uint8_t i ;
+
+  
+  for ( i=0 ; i < 8 ; ++i )
+  {
+    digitalWrite( ulClockPin, HIGH ) ;
+
+    if ( ulBitOrder == LSBFIRST )
+    {
+      value |= digitalRead( ulDataPin ) << i ;
+    }
+    else
+    {
+      value |= digitalRead( ulDataPin ) << (7 - i) ;
+    }
+
+    digitalWrite( ulClockPin, LOW ) ;
+  }
+
+  return value ;
+}
diff --git a/STM32F4/cores/maple/io.h b/STM32F4/cores/maple/io.h
index 1cbe2d953..df1ab969e 100644
--- a/STM32F4/cores/maple/io.h
+++ b/STM32F4/cores/maple/io.h
@@ -218,5 +218,7 @@ uint8 waitForButtonPress(uint32 timeout_millis=0);
  */
 void shiftOut(uint8 dataPin, uint8 clockPin, uint8 bitOrder, uint8 value);
 
+uint32 shiftIn( uint32 ulDataPin, uint32 ulClockPin, uint32 ulBitOrder );
+
 #endif
 
diff --git a/STM32F4/cores/maple/wirish_shift.cpp b/STM32F4/cores/maple/wirish_shift.cpp
index f67364d1f..57ae94eaf 100644
--- a/STM32F4/cores/maple/wirish_shift.cpp
+++ b/STM32F4/cores/maple/wirish_shift.cpp
@@ -38,3 +38,28 @@ void shiftOut(uint8 dataPin, uint8 clockPin, uint8 bitOrder, uint8 val) {
         digitalWrite(clockPin, LOW);
     }
 }
+
+uint32 shiftIn( uint32 ulDataPin, uint32 ulClockPin, uint32 ulBitOrder )
+{
+  uint8_t value = 0 ;
+  uint8_t i ;
+
+  
+  for ( i=0 ; i < 8 ; ++i )
+  {
+    digitalWrite( ulClockPin, HIGH ) ;
+
+    if ( ulBitOrder == LSBFIRST )
+    {
+      value |= digitalRead( ulDataPin ) << i ;
+    }
+    else
+    {
+      value |= digitalRead( ulDataPin ) << (7 - i) ;
+    }
+
+    digitalWrite( ulClockPin, LOW ) ;
+  }
+
+  return value ;
+}
\ No newline at end of file

From e7456e191650dc54b0fa8e7b95670f5621356265 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Sat, 10 Dec 2016 22:36:21 +0100
Subject: [PATCH 030/307] further optimizations

- extend read function to 16bit
- add repeated write the same byte/word a specified number of time
- revert increment option to dmaSend
---
 STM32F1/cores/maple/libmaple/spi.c | 26 +++++++++++--------
 STM32F1/libraries/SPI/src/SPI.cpp  | 40 +++++++++++++++++++-----------
 STM32F1/libraries/SPI/src/SPI.h    | 35 +++++++++++++++-----------
 3 files changed, 61 insertions(+), 40 deletions(-)

diff --git a/STM32F1/cores/maple/libmaple/spi.c b/STM32F1/cores/maple/libmaple/spi.c
index 64f06d301..e0ee90d42 100644
--- a/STM32F1/cores/maple/libmaple/spi.c
+++ b/STM32F1/cores/maple/libmaple/spi.c
@@ -93,16 +93,21 @@ void spi_slave_enable(spi_dev *dev, spi_mode mode, uint32 flags) {
  * @return Number of elements transmitted.
  */
 uint32 spi_tx(spi_dev *dev, const void *buf, uint32 len) {
-    uint32 txed = 0;
-    uint8 byte_frame = spi_dff(dev) == SPI_DFF_8_BIT;
-    while ( txed < len ) {
-		while ( spi_is_tx_empty(dev)==0 ); // wait Tx to be empty
-        if (byte_frame) {
-            dev->regs->DR = ((const uint8*)buf)[txed++];
-        } else {
-            dev->regs->DR = ((const uint16*)buf)[txed++];
-        }
-    }
+    uint32 txed = len;
+	spi_reg_map *regs = dev->regs;
+    if ( spi_dff(dev) == SPI_DFF_8_BIT ) {
+		const uint8 * dp8 = (const uint8*)buf;
+		while ( len-- ) {
+			while ( (regs->SR & SPI_SR_TXE)==0 ) ; //while ( spi_is_tx_empty(dev)==0 ); // wait Tx to be empty
+			regs->DR = *dp8++;
+		}
+    } else {
+		const uint16 * dp16 = (const uint16*)buf;
+		while ( len-- ) {
+			while ( (regs->SR & SPI_SR_TXE)==0 ) ; //while ( spi_is_tx_empty(dev)==0 ); // wait Tx to be empty
+			regs->DR = *dp16++;
+		}
+	}
     return txed;
 }
 
@@ -163,6 +168,5 @@ static void spi_reconfigure(spi_dev *dev, uint32 cr1_config) {
 	spi_irq_disable(dev, SPI_INTERRUPTS_ALL);
 	if ( (dev->regs->CR1&MASK)!=(cr1_config&MASK) )	spi_peripheral_disable(dev);
 	dev->regs->CR1 = cr1_config;
-	//spi_rx_dma_enable(dev);
 	spi_peripheral_enable(dev);
 }
diff --git a/STM32F1/libraries/SPI/src/SPI.cpp b/STM32F1/libraries/SPI/src/SPI.cpp
index 08327912f..9b6e28e7d 100644
--- a/STM32F1/libraries/SPI/src/SPI.cpp
+++ b/STM32F1/libraries/SPI/src/SPI.cpp
@@ -160,7 +160,7 @@ void SPIClass::begin(void) {
 void SPIClass::beginSlave(void) {
     spi_init(_currentSetting->spi_d);
     configure_gpios(_currentSetting->spi_d, 0);
-    uint32 flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | _currentSetting->dataSize | SPI_SW_SLAVE);
+    uint32 flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | _currentSetting->dataSize | SPI_RX_ONLY);
 	#ifdef SPI_DEBUG
 	Serial.print("spi_slave_enable("); Serial.print(_currentSetting->dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
 	#endif
@@ -306,10 +306,10 @@ void SPIClass::endTransaction(void)
  * I/O
  */
 
-uint8 SPIClass::read(void)
+uint16 SPIClass::read(void)
 {
 	while ( spi_is_rx_nonempty(_currentSetting->spi_d)==0 ) ;
-	return (uint8)spi_rx_reg(_currentSetting->spi_d);
+	return (uint16)spi_rx_reg(_currentSetting->spi_d);
 }
 
 void SPIClass::read(uint8 *buf, uint32 len)
@@ -321,7 +321,7 @@ void SPIClass::read(uint8 *buf, uint32 len)
     while ( rxed < len) {
 		regs->DR = 0x00FF; // " write the data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
         while ( (regs->SR & SPI_SR_RXNE)==0 ) ; // wait till data is available in the Rx register
-        buf[rxed++] = (uint8)(regs->DR); // read and store the received byte
+        *buf++ = (regs->DR); // read and store the received byte
     }
 }
 
@@ -332,11 +332,21 @@ void SPIClass::write(uint16 data)
 	 * by taking the Tx code from transfer(byte)
 	 * This almost doubles the speed of this function.
 	 */
-	spi_tx_reg(_currentSetting->spi_d, data); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+	spi_tx_reg(_currentSetting->spi_d, data); // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
 }
 
+void SPIClass::write(uint16 data, uint32 n)
+{
+	// Added by stevstrong: Repeatedly send same data by the specified number of times
+	spi_reg_map * regs = _currentSetting->spi_d->regs;
+	while ( (n--)>0 ) {
+		regs->DR = data; // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
+        while ( (regs->SR & SPI_SR_TXE)==0 ) ; // wait till Tx empty
+	}
+	while ( (regs->SR & SPI_SR_BSY) != 0); // wait until BSY=0 before returning 
+}
+
 void SPIClass::write(const void *data, uint32 length)
 {
     spi_tx(_currentSetting->spi_d, data, length); // data can be array of bytes or words
@@ -346,18 +356,18 @@ void SPIClass::write(const void *data, uint32 length)
 	uint16 b = spi_rx_reg(_currentSetting->spi_d); // dummy read, needed, don't remove!
 }
 
-uint16_t SPIClass::transfer16(uint16_t wr_data) const {
-	spi_tx_reg(_currentSetting->spi_d, wr_data); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
+uint8 SPIClass::transfer(uint8 byte) const {
+	spi_tx_reg(_currentSetting->spi_d, byte); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
-	return (uint16)spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
+	return (uint8)spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
 }
 
-uint8 SPIClass::transfer(uint8 byte) const {
-	spi_tx_reg(_currentSetting->spi_d, byte); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
+uint16_t SPIClass::transfer16(uint16_t wr_data) const {
+	spi_tx_reg(_currentSetting->spi_d, wr_data); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
-	return (uint8)spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
+	return (uint16)spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
 }
 
 /*  Roger Clark and Victor Perez, 2015
@@ -419,10 +429,10 @@ uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length
 *	Still in progress.
 *	2016 - stevstrong - reworked to automatically detect bit size from SPI setting
 */
-uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length)
+uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length, bool minc)
 {
 	if (length == 0) return 0;
-	uint32 flags = (DMA_MINC_MODE | DMA_FROM_MEM | DMA_TRNS_CMPLT);
+	uint32 flags = ( (DMA_MINC_MODE*minc) | DMA_FROM_MEM | DMA_TRNS_CMPLT);
 	uint8 b = 0;
 //	dma1_ch3_Active=true;
     dma_init(_currentSetting->spiDmaDev);
@@ -438,7 +448,7 @@ uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length)
 
 //    while (dma1_ch3_Active);
     uint32_t m = millis();
-	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & 0x2)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
+	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
 		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
     }
 	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
diff --git a/STM32F1/libraries/SPI/src/SPI.h b/STM32F1/libraries/SPI/src/SPI.h
index 0f8497ae1..717a2e90c 100644
--- a/STM32F1/libraries/SPI/src/SPI.h
+++ b/STM32F1/libraries/SPI/src/SPI.h
@@ -115,6 +115,13 @@ class SPISettings {
 			init_MightInline(clock, bitOrder, dataMode, dataSize);
 		}
 	}
+	SPISettings(uint32_t clock) {
+		if (__builtin_constant_p(clock)) {
+			init_AlwaysInline(clock, MSBFIRST, SPI_MODE0, DATA_SIZE_8BIT);
+		} else {
+			init_MightInline(clock, MSBFIRST, SPI_MODE0, DATA_SIZE_8BIT);
+		}
+	}
 	SPISettings() { init_AlwaysInline(4000000, MSBFIRST, SPI_MODE0, DATA_SIZE_8BIT); }
 private:
 	void init_MightInline(uint32_t clock, BitOrder bitOrder, uint8_t dataMode, uint32_t dataSize) {
@@ -216,38 +223,38 @@ class SPIClass {
      */
 
     /**
-     * @brief Return the next unread byte.
+     * @brief Return the next unread byte/word.
      *
-     * If there is no unread byte waiting, this function will block
+     * If there is no unread byte/word waiting, this function will block
      * until one is received.
      */
-    uint8 read(void);
+    uint16 read(void);
 
     /**
      * @brief Read length bytes, storing them into buffer.
      * @param buffer Buffer to store received bytes into.
-     * @param length Number of bytes to store in buffer.  This
+     * @param length Number of bytes to store in buffer. This
      *               function will block until the desired number of
      *               bytes have been read.
      */
     void read(uint8 *buffer, uint32 length);
 
     /**
-     * @brief Transmit a byte.
-     * @param data Byte to transmit.
+     * @brief Transmit one byte/word.
+     * @param data to transmit.
      */
-//    void write(uint8 data);
-
+    void write(uint16 data);	
+	
     /**
-     * @brief Transmit a half word.
+     * @brief Transmit one byte/word a specified number of times.
      * @param data to transmit.
      */
-    void write(uint16 data);	
+    void write(uint16 data, uint32 n);	
 	
     /**
-     * @brief Transmit multiple bytes.
-     * @param buffer Bytes to transmit.
-     * @param length Number of bytes in buffer to transmit.
+     * @brief Transmit multiple bytes/words.
+     * @param buffer Bytes/words to transmit.
+     * @param length Number of bytes/words in buffer to transmit.
      */
     void write(const void * buffer, uint32 length);
 
@@ -283,7 +290,7 @@ class SPIClass {
      * @param data buffer half words to transmit,
      * @param length Number of bytes in buffer to transmit.
      */
-	uint8 dmaSend(void * transmitBuf, uint16 length);
+	uint8 dmaSend(void * transmitBuf, uint16 length, bool minc = 1);
 
     /*
      * Pin accessors

From 71a198a1d070f933f7968a757f13c88c22ca21bc Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Mon, 12 Dec 2016 17:57:50 +1100
Subject: [PATCH 031/307] Fix problems with tone functions

---
 STM32F1/cores/maple/tone.cpp | 40 +++++++++++++++++++++---------------
 STM32F1/cores/maple/wirish.h |  1 +
 2 files changed, 25 insertions(+), 16 deletions(-)

diff --git a/STM32F1/cores/maple/tone.cpp b/STM32F1/cores/maple/tone.cpp
index 2bb11e5d3..26aa67679 100644
--- a/STM32F1/cores/maple/tone.cpp
+++ b/STM32F1/cores/maple/tone.cpp
@@ -11,13 +11,6 @@
 #include "Arduino.h"
 #include <HardwareTimer.h>
 
-// define default timer and channel
-#ifndef TONE_TIMER
-#define TONE_TIMER 4
-#endif
-#ifndef TONE_CHANNEL
-#define TONE_CHANNEL 4
-#endif
 
 #define PinTimer(pin) (PIN_MAP[pin].timer_device->clk_id-RCC_TIMER1+1)
 #define PinChannel(pin) (PIN_MAP[pin].timer_channel)
@@ -30,22 +23,37 @@
 #define USE_BSRR
 
 // construct static timer array (
-HardwareTimer TTimer1(1), TTimer2(2), TTimer3(3), TTimer4(4);
-#ifdef STM32_HIGH_DENSITY
-HardwareTimer TTimer5(5), TTimer6(6), TTimer7(7), TTimer8(8);
-#endif
+
 
 #ifdef STM32_HIGH_DENSITY
-	HardwareTimer *TTimer[8] { &TTimer1,&TTimer2,&TTimer3,&TTimer4,&TTimer5,&TTimer6,&TTimer7,&TTimer8 };
+// define default timer and channel
+	#ifndef TONE_TIMER
+	#define TONE_TIMER 8
+	#endif
+	#ifndef TONE_CHANNEL
+	#define TONE_CHANNEL 8
+	#endif
+
+	HardwareTimer TTimer1(1), TTimer2(2), TTimer3(3), TTimer4(4),TTimer5(5), TTimer6(6), TTimer7(7), TTimer8(8);
+	HardwareTimer *TTimer[8] =  { &TTimer1,&TTimer2,&TTimer3,&TTimer4,&TTimer5,&TTimer6,&TTimer7,&TTimer8 };
 #else
-	HardwareTimer *TTimer[4] { &TTimer1,&TTimer2,&TTimer3,&TTimer4 };
+	// define default timer and channel
+	#ifndef TONE_TIMER
+	#define TONE_TIMER 4
+	#endif
+	#ifndef TONE_CHANNEL
+	#define TONE_CHANNEL 4
+	#endif
+
+	HardwareTimer TTimer1(1), TTimer2(2), TTimer3(3), TTimer4(4);
+	HardwareTimer *TTimer[4] =  { &TTimer1,&TTimer2,&TTimer3,&TTimer4 };
 #endif
 
 
 uint8_t tone_force_channel = 0;                 // forced timer channel
 uint8_t tone_force_ntimer = 0;                  // forced timer
 
-HardwareTimer *tone_timer = TTimer[TONE_TIMER]; // timer used to generate frequency
+HardwareTimer *tone_timer;// = TTimer[TONE_TIMER-1]; // timer used to generate frequency
 uint8_t tone_channel = TONE_CHANNEL;            // timer channel used to generate frequency
 uint8_t tone_ntimer = TONE_TIMER;               // timer used to generate frequency
 
@@ -138,7 +146,7 @@ void tone(uint32_t pin, uint32_t freq, uint32_t duration) {
 
    tone_timer->pause();
 
-   if(freq > 0 || duration >0 ){
+   if(freq > 0 && duration >0 ){
       uint32_t count = 18000000/freq;       // timer counts per half wave
       tone_ncount = tone_n = (count>>16)+1; // number of 16-bit count chunk
       tone_tcount = count/tone_ncount;      // size of count chunk
@@ -183,7 +191,7 @@ void tone(uint32_t pin, uint32_t freq, uint32_t duration) {
 ////////////////////////////////////////////////////////////////////////////////
 // disable tone on specified pin, if any
 void noTone(uint32_t pin){
-   tone(pin,-1,0);  // it's all handled in tone()
+   tone(pin,0,0);  // it's all handled in tone()
 }
 
 ////////////////////////////////////////////////////////////////////////////////
diff --git a/STM32F1/cores/maple/wirish.h b/STM32F1/cores/maple/wirish.h
index c2ab4f333..3ffee8331 100644
--- a/STM32F1/cores/maple/wirish.h
+++ b/STM32F1/cores/maple/wirish.h
@@ -76,6 +76,7 @@
 #include <stdint.h>
 
 #include <WCharacter.h>
+#include <tone.h>
 
 typedef unsigned int word;
 // typedef uint16 word;// definition from Arduino website, now appears to be incorrect for 32 bit devices

From 6030e1325878a264338c65905bbda47a8fa9d85a Mon Sep 17 00:00:00 2001
From: Testato <Testato@users.noreply.github.com>
Date: Sat, 17 Dec 2016 12:29:42 +0100
Subject: [PATCH 032/307] Update boards.txt

PR for issue https://github.com/rogerclarkmelbourne/Arduino_STM32/issues/200
---
 STM32F1/boards.txt | 82 ++++++++++++++++------------------------------
 1 file changed, 29 insertions(+), 53 deletions(-)

diff --git a/STM32F1/boards.txt b/STM32F1/boards.txt
index 95a5f8635..030a96190 100644
--- a/STM32F1/boards.txt
+++ b/STM32F1/boards.txt
@@ -25,17 +25,15 @@ mapleMini.upload.auto_reset=true
 mapleMini.menu.bootloader_version.original = Original (17k RAM,108k Flash)
 mapleMini.menu.bootloader_version.original.build.vect=VECT_TAB_ADDR=0x8005000
 mapleMini.menu.bootloader_version.original.build.ldscript=ld/flash.ld
-mapleMini.menu.bootloader_version.original.upload.ram.maximum_size=17408
-mapleMini.menu.bootloader_version.original.upload.flash.maximum_size=110592
 mapleMini.menu.bootloader_version.original.upload.maximum_size=110592
+mapleMini.menu.bootloader_version.original.upload.maximum_data_size=17408
 mapleMini.menu.bootloader_version.original.upload.altID=1
 
 mapleMini.menu.bootloader_version.bootloader20 = Bootloader 2.0 (20k RAM,120k Flash)
 mapleMini.menu.bootloader_version.bootloader20.build.vect=VECT_TAB_ADDR=0x8002000
 mapleMini.menu.bootloader_version.bootloader20.build.ldscript=ld/bootloader_20.ld
-mapleMini.menu.bootloader_version.bootloader20.upload.ram.maximum_size=20480
-mapleMini.menu.bootloader_version.bootloader20.upload.flash.maximum_size=122880
 mapleMini.menu.bootloader_version.bootloader20.upload.maximum_size=122880
+mapleMini.menu.bootloader_version.bootloader20.upload.maximum_data_size=20480
 mapleMini.menu.bootloader_version.bootloader20.upload.altID=2
 
 ##############################################################
@@ -46,10 +44,9 @@ maple.pid.0=0x0004
 maple.upload.tool=maple_upload
 maple.upload.protocol=maple_dfu
 maple.upload.maximum_size=108000
+maple.upload.maximum_data_size=17000
 maple.upload.use_1200bps_touch=false
 maple.upload.file_type=bin
-maple.upload.ram.maximum_size=17000
-maple.upload.flash.maximum_size=108000
 maple.upload.usbID=1EAF:0003
 maple.upload.altID=1
 maple.upload.auto_reset=true
@@ -77,10 +74,9 @@ mapleRET6.build.vect=VECT_TAB_ADDR=0x8005000
 mapleRET6.upload.tool=maple_upload
 mapleRET6.upload.protocol=maple_dfu
 mapleRET6.upload.maximum_size=262144
+mapleRET6.upload.maximum_data_size=49152
 mapleRET6.upload.use_1200bps_touch=false
 mapleRET6.upload.file_type=bin
-mapleRET6.upload.ram.maximum_size=49152
-mapleRET6.upload.flash.maximum_size=262144
 mapleRET6.upload.usbID=1EAF:0003
 mapleRET6.upload.altID=1
 mapleRET6.upload.auto_reset=true
@@ -94,10 +90,9 @@ microduino32_flash.pid.0=0x0004
 microduino32_flash.upload.tool=maple_upload
 microduino32_flash.upload.protocol=maple_dfu
 microduino32_flash.upload.maximum_size=108000
+microduino32_flash.upload.maximum_data_size=17000
 microduino32_flash.upload.use_1200bps_touch=false
 microduino32_flash.upload.file_type=bin
-microduino32_flash.upload.ram.maximum_size=17000
-microduino32_flash.upload.flash.maximum_size=108000
 microduino32_flash.upload.usbID=1EAF:0003
 microduino32_flash.upload.altID=1
 microduino32_flash.upload.auto_reset=true
@@ -123,10 +118,9 @@ nucleo_f103rb.name=STM Nucleo F103RB (STLink)
 nucleo_f103rb.upload.tool=stlink_upload
 nucleo_f103rb.upload.protocol=maple_dfu
 nucleo_f103rb.upload.maximum_size=108000
+nucleo_f103rb.upload.maximum_data_size=17000
 nucleo_f103rb.upload.use_1200bps_touch=false
 nucleo_f103rb.upload.file_type=bin
-nucleo_f103rb.upload.ram.maximum_size=17000
-nucleo_f103rb.upload.flash.maximum_size=108000
 nucleo_f103rb.upload.params.quiet=no
 
 nucleo_f103rb.upload.usbID=1EAF:0003
@@ -174,16 +168,14 @@ genericSTM32F103C.menu.device_variant.STM32F103C8=STM32F103C8 (20k RAM. 64k Flas
 genericSTM32F103C.menu.device_variant.STM32F103C8.build.cpu_flags=-DMCU_STM32F103C8
 genericSTM32F103C.menu.device_variant.STM32F103C8.build.ldscript=ld/jtag_c8.ld
 genericSTM32F103C.menu.device_variant.STM32F103C8.upload.maximum_size=65536
-genericSTM32F103C.menu.device_variant.STM32F103C8.upload.ram.maximum_size=20480
-genericSTM32F103C.menu.device_variant.STM32F103C8.upload.flash.maximum_size=65536
+genericSTM32F103C.menu.device_variant.STM32F103C8.upload.maximum_data_size=20480
 
 ## STM32F103CB -------------------------
 genericSTM32F103C.menu.device_variant.STM32F103CB=STM32F103CB (20k RAM. 128k Flash)
 genericSTM32F103C.menu.device_variant.STM32F103CB.build.cpu_flags=-DMCU_STM32F103CB
 genericSTM32F103C.menu.device_variant.STM32F103CB.build.ldscript=ld/jtag.ld
 genericSTM32F103C.menu.device_variant.STM32F103CB.upload.maximum_size=131072
-genericSTM32F103C.menu.device_variant.STM32F103CB.upload.ram.maximum_size=20480
-genericSTM32F103C.menu.device_variant.STM32F103CB.upload.flash.maximum_size=131072
+genericSTM32F103C.menu.device_variant.STM32F103C8.upload.maximum_data_size=20480
 
 #---------------------------- UPLOAD METHODS ---------------------------
 
@@ -211,7 +203,6 @@ genericSTM32F103C.menu.upload_method.BMPMethod.upload.protocol=gdb_bmp
 genericSTM32F103C.menu.upload_method.BMPMethod.upload.tool=bmp_upload
 genericSTM32F103C.menu.upload_method.BMPMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG
 
-
 genericSTM32F103C.menu.upload_method.jlinkMethod=JLink
 genericSTM32F103C.menu.upload_method.jlinkMethod.upload.protocol=jlink
 genericSTM32F103C.menu.upload_method.jlinkMethod.upload.tool=jlink_upload
@@ -234,22 +225,21 @@ genericSTM32F103R.menu.device_variant.STM32F103R8=STM32F103R8 (20k RAM. 64k Flas
 genericSTM32F103R.menu.device_variant.STM32F103R8.build.variant=generic_stm32f103r8
 genericSTM32F103R.menu.device_variant.STM32F103R8.build.cpu_flags=-DMCU_STM32F103R8
 genericSTM32F103R.menu.device_variant.STM32F103R8.upload.maximum_size=65536
-genericSTM32F103R.menu.device_variant.STM32F103R8.upload.ram.maximum_size=20480
-genericSTM32F103R.menu.device_variant.STM32F103R8.upload.flash.maximum_size=65536
+genericSTM32F103R.menu.device_variant.STM32F103R8.upload.maximum_data_size=20480
 genericSTM32F103R.menu.device_variant.STM32F103R8.build.ldscript=ld/stm32f103r8.ld
 
 genericSTM32F103R.menu.device_variant.STM32F103RB=STM32F103RB (20k RAM. 128k Flash)
 genericSTM32F103R.menu.device_variant.STM32F103RB.build.variant=generic_stm32f103r8
 genericSTM32F103R.menu.device_variant.STM32F103RB.build.cpu_flags=-DMCU_STM32F103RB
 genericSTM32F103R.menu.device_variant.STM32F103RB.upload.maximum_size=131072
-genericSTM32F103R.menu.device_variant.STM32F103RB.upload.ram.maximum_size=20480
-genericSTM32F103R.menu.device_variant.STM32F103RB.upload.flash.maximum_size=131072
+genericSTM32F103R.menu.device_variant.STM32F103RB.upload.maximum_data_size=20480
 genericSTM32F103R.menu.device_variant.STM32F103RB.build.ldscript=ld/stm32f103rb.ld
 
 genericSTM32F103R.menu.device_variant.STM32F103RC=STM32F103RC (48k RAM. 256k Flash)
 genericSTM32F103R.menu.device_variant.STM32F103RC.build.variant=generic_stm32f103r
 genericSTM32F103R.menu.device_variant.STM32F103RC.build.cpu_flags=-DMCU_STM32F103RC
 genericSTM32F103R.menu.device_variant.STM32F103RC.upload.maximum_size=262144
+genericSTM32F103R.menu.device_variant.STM32F103RC.upload.maximum_data_size=49152
 genericSTM32F103R.menu.device_variant.STM32F103RC.upload.ram.maximum_size=49152
 genericSTM32F103R.menu.device_variant.STM32F103RC.upload.flash.maximum_size=262144
 genericSTM32F103R.menu.device_variant.STM32F103RC.build.ldscript=ld/stm32f103rc.ld
@@ -258,8 +248,7 @@ genericSTM32F103R.menu.device_variant.STM32F103RE=STM32F103RE (64k RAM. 512k Fla
 genericSTM32F103R.menu.device_variant.STM32F103RE.build.variant=generic_stm32f103r
 genericSTM32F103R.menu.device_variant.STM32F103RE.build.cpu_flags=-DMCU_STM32F103RE
 genericSTM32F103R.menu.device_variant.STM32F103RE.upload.maximum_size=524288
-genericSTM32F103R.menu.device_variant.STM32F103RE.upload.ram.maximum_size=65536
-genericSTM32F103R.menu.device_variant.STM32F103RE.upload.flash.maximum_size=524288
+genericSTM32F103R.menu.device_variant.STM32F103RE.upload.maximum_data_size=65536
 genericSTM32F103R.menu.device_variant.STM32F103RE.build.ldscript=ld/stm32f103re.ld
 
 #---------------------------- UPLOAD METHODS ---------------------------
@@ -305,16 +294,14 @@ genericSTM32F103T.menu.device_variant.STM32F103T8=STM32F103T8 (20k RAM. 64k Flas
 genericSTM32F103T.menu.device_variant.STM32F103T8.build.cpu_flags=-DMCU_STM32F103T8
 genericSTM32F103T.menu.device_variant.STM32F103T8.build.ldscript=ld/jtag_t8.ld
 genericSTM32F103T.menu.device_variant.STM32F103T8.upload.maximum_size=65536
-genericSTM32F103T.menu.device_variant.STM32F103T8.upload.ram.maximum_size=20480
-genericSTM32F103T.menu.device_variant.STM32F103T8.upload.flash.maximum_size=65536
+genericSTM32F103T.menu.device_variant.STM32F103T8.upload.maximum_data_size=20480
 
 ## STM32F103TB -------------------------
 genericSTM32F103T.menu.device_variant.STM32F103TB=STM32F103TB (20k RAM. 128k Flash)
 genericSTM32F103T.menu.device_variant.STM32F103TB.build.cpu_flags=-DMCU_STM32F103TB
 genericSTM32F103T.menu.device_variant.STM32F103TB.build.ldscript=ld/jtag.ld
 genericSTM32F103T.menu.device_variant.STM32F103TB.upload.maximum_size=131072
-genericSTM32F103T.menu.device_variant.STM32F103TB.upload.ram.maximum_size=20480
-genericSTM32F103T.menu.device_variant.STM32F103TB.upload.flash.maximum_size=131072
+genericSTM32F103T.menu.device_variant.STM32F103TB.upload.maximum_data_size=20480
 
 #---------------------------- UPLOAD METHODS ---------------------------
 
@@ -360,22 +347,19 @@ genericSTM32F103V.build.error_led_pin=6
 genericSTM32F103V.menu.device_variant.STM32F103VC=STM32F103VC
 genericSTM32F103V.menu.device_variant.STM32F103VC.build.cpu_flags=-DMCU_STM32F103VC
 genericSTM32F103V.menu.device_variant.STM32F103VC.upload.maximum_size=262144
-genericSTM32F103V.menu.device_variant.STM32F103VC.upload.ram.maximum_size=49152
-genericSTM32F103V.menu.device_variant.STM32F103VC.upload.flash.maximum_size=262144
+genericSTM32F103V.menu.device_variant.STM32F103VC.upload.maximum_data_size=49152
 genericSTM32F103V.menu.device_variant.STM32F103VC.build.ldscript=ld/stm32f103vc.ld
 
 genericSTM32F103V.menu.device_variant.STM32F103VD=STM32F103VD
 genericSTM32F103V.menu.device_variant.STM32F103VD.build.cpu_flags=-DMCU_STM32F103VD
 genericSTM32F103V.menu.device_variant.STM32F103VD.upload.maximum_size=393216
-genericSTM32F103V.menu.device_variant.STM32F103VD.upload.ram.maximum_size=65536
-genericSTM32F103V.menu.device_variant.STM32F103VD.upload.flash.maximum_size=393216
+genericSTM32F103V.menu.device_variant.STM32F103VD.upload.maximum_data_size=65536
 genericSTM32F103V.menu.device_variant.STM32F103VD.build.ldscript=ld/stm32f103vd.ld
 
 genericSTM32F103V.menu.device_variant.STM32F103VE=STM32F103VE
 genericSTM32F103V.menu.device_variant.STM32F103VE.build.cpu_flags=-DMCU_STM32F103VE
 genericSTM32F103V.menu.device_variant.STM32F103VE.upload.maximum_size=524288
-genericSTM32F103V.menu.device_variant.STM32F103VE.upload.ram.maximum_size=65536
-genericSTM32F103V.menu.device_variant.STM32F103VE.upload.flash.maximum_size=524288
+genericSTM32F103V.menu.device_variant.STM32F103VE.upload.maximum_data_size=65536
 genericSTM32F103V.menu.device_variant.STM32F103VE.build.ldscript=ld/stm32f103ve.ld
 
 #---------------------------- UPLOAD METHODS ---------------------------
@@ -419,22 +403,19 @@ genericSTM32F103Z.upload.auto_reset=true
 genericSTM32F103Z.menu.device_variant.STM32F103ZC=STM32F103ZC
 genericSTM32F103Z.menu.device_variant.STM32F103ZC.build.cpu_flags=-DMCU_STM32F103ZC
 genericSTM32F103Z.menu.device_variant.STM32F103ZC.upload.maximum_size=262144
-genericSTM32F103Z.menu.device_variant.STM32F103ZC.upload.ram.maximum_size=49152
-genericSTM32F103Z.menu.device_variant.STM32F103ZC.upload.flash.maximum_size=262144
+genericSTM32F103Z.menu.device_variant.STM32F103ZC.upload.maximum_data_size=49152
 genericSTM32F103Z.menu.device_variant.STM32F103ZC.build.ldscript=ld/stm32f103zc.ld
 
 genericSTM32F103Z.menu.device_variant.STM32F103ZD=STM32F103ZD
 genericSTM32F103Z.menu.device_variant.STM32F103ZD.build.cpu_flags=-DMCU_STM32F103ZD
 genericSTM32F103Z.menu.device_variant.STM32F103ZD.upload.maximum_size=393216
-genericSTM32F103Z.menu.device_variant.STM32F103ZD.upload.ram.maximum_size=65536
-genericSTM32F103Z.menu.device_variant.STM32F103ZD.upload.flash.maximum_size=393216
+genericSTM32F103Z.menu.device_variant.STM32F103ZD.upload.maximum_data_size=65536
 genericSTM32F103Z.menu.device_variant.STM32F103ZD.build.ldscript=ld/stm32f103zd.ld
 
 genericSTM32F103Z.menu.device_variant.STM32F103ZE=STM32F103ZE
 genericSTM32F103Z.menu.device_variant.STM32F103ZE.build.cpu_flags=-DMCU_STM32F103ZE
 genericSTM32F103Z.menu.device_variant.STM32F103ZE.upload.maximum_size=524288
-genericSTM32F103Z.menu.device_variant.STM32F103ZE.upload.ram.maximum_size=65536
-genericSTM32F103Z.menu.device_variant.STM32F103ZE.upload.flash.maximum_size=524288
+genericSTM32F103Z.menu.device_variant.STM32F103ZE.upload.maximum_data_size=65536
 genericSTM32F103Z.menu.device_variant.STM32F103ZE.build.ldscript=ld/stm32f103ze.ld
 
 #---------------------------- UPLOAD METHODS ---------------------------
@@ -479,9 +460,7 @@ hytiny-stm32f103t.upload.auto_reset=true
 hytiny-stm32f103t.build.cpu_flags=-DMCU_STM32F103CB
 hytiny-stm32f103t.build.ldscript=ld/jtag.ld
 hytiny-stm32f103t.upload.maximum_size=131072
-hytiny-stm32f103t.upload.ram.maximum_size=20480
-hytiny-stm32f103t.upload.flash.maximum_size=131072
-
+hytiny-stm32f103t.upload.maximum_data_size=20480
 
 #---------------------------- UPLOAD METHODS ---------------------------
 
@@ -529,20 +508,17 @@ genericGD32F103C.upload.auto_reset=true
 genericGD32F103C.build.cpu_flags=-DMCU_STM32F103CB  
 genericGD32F103C.build.f_cpu=72000000L
 
-## GD32F103CB -------------------------
-genericGD32F103C.menu.device_variant.GD32F103CB=GD32F103CB (20k RAM. 128k Flash)
-genericGD32F103C.menu.device_variant.GD32F103CB.build.ldscript=ld/jtag.ld
-genericGD32F103C.menu.device_variant.GD32F103CB.upload.maximum_size=131072
-genericGD32F103C.menu.device_variant.GD32F103CB.upload.ram.maximum_size=20480
-genericGD32F103C.menu.device_variant.GD32F103CB.upload.flash.maximum_size=131072
-
-
 ## GD32F103C8 -------------------------
 genericGD32F103C.menu.device_variant.GD32F103C8=GD32F103C8 (20k RAM. 64k Flash)
 genericGD32F103C.menu.device_variant.GD32F103C8.build.ldscript=ld/jtag_c8.ld
 genericGD32F103C.menu.device_variant.GD32F103C8.upload.maximum_size=65536
-genericGD32F103C.menu.device_variant.GD32F103C8.upload.ram.maximum_size=20480
-genericGD32F103C.menu.device_variant.GD32F103C8.upload.flash.maximum_size=65536
+genericGD32F103C.menu.device_variant.GD32F103C8.upload.maximum_data_size=20480
+
+## GD32F103CB -------------------------
+genericGD32F103C.menu.device_variant.GD32F103CB=GD32F103CB (20k RAM. 128k Flash)
+genericGD32F103C.menu.device_variant.GD32F103CB.build.ldscript=ld/jtag.ld
+genericGD32F103C.menu.device_variant.GD32F103CB.upload.maximum_size=131072
+genericGD32F103C.menu.device_variant.GD32F103CB.upload.maximum_data_size=20480
 
 #---------------------------- UPLOAD METHODS ---------------------------
 
@@ -601,8 +577,8 @@ STM32VLD.upload.auto_reset=true
 STM32VLD.upload.params.quiet=no
 
 STM32VLD.build.cpu_flags=-DMCU_STM32F100RB
-##---------------------------- UPLOAD METHODS ---------------------------
 
+#---------------------------- UPLOAD METHODS ---------------------------
 
 STM32VLD.menu.upload_method.STLinkMethod=STLink
 STM32VLD.menu.upload_method.STLinkMethod.upload.protocol=STLink

From 99ba590bd491df803d7fc6f4fb2ca1859c0f1a18 Mon Sep 17 00:00:00 2001
From: Testato <Testato@users.noreply.github.com>
Date: Sat, 17 Dec 2016 12:38:20 +0100
Subject: [PATCH 033/307] Update boards.txt

PR for issue https://github.com/rogerclarkmelbourne/Arduino_STM32/issues/200

- replaced `upload.flash.maximum_size` and `upload.ram.maximum_size` by the new arduino standard `upload.maximum_size` and `upload.maximum_data_size`
- corrected Flash and Ram value
- Tested by builded
---
 STM32F3/boards.txt | 5 ++---
 1 file changed, 2 insertions(+), 3 deletions(-)

diff --git a/STM32F3/boards.txt b/STM32F3/boards.txt
index 82b2bc5ae..6c011bce3 100644
--- a/STM32F3/boards.txt
+++ b/STM32F3/boards.txt
@@ -8,9 +8,8 @@ discovery_f3.upload.protocol=stlink
 
 #discovery_f407.upload.use_1200bps_touch=false
 discovery_f3.upload.file_type=bin
-discovery_f3.upload.ram.maximum_size=17000
-discovery_f3.upload.flash.maximum_size=108000
-discovery_f3.upload.maximum_size=108000
+discovery_f3.upload.maximum_size=262144
+discovery_f3.upload.maximum_data_size=49152
 
 #discovery_f3.upload.usbID=1EAF:0003
 #discovery_f3.upload.altID=1

From 54d67d77c4b01f22fa4910b841d13f61da8163af Mon Sep 17 00:00:00 2001
From: Testato <Testato@users.noreply.github.com>
Date: Sat, 17 Dec 2016 12:41:23 +0100
Subject: [PATCH 034/307] Update boards.txt

PR for issue https://github.com/rogerclarkmelbourne/Arduino_STM32/issues/200

- replaced `upload.flash.maximum_size` and `upload.ram.maximum_size` by the new arduino standard `upload.maximum_size` and `upload.maximum_data_size`
- corrected Flash and Ram value
- Tested by builded every MCU on every Variant
---
 STM32F4/boards.txt | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/STM32F4/boards.txt b/STM32F4/boards.txt
index 7577d1949..daa1a0492 100644
--- a/STM32F4/boards.txt
+++ b/STM32F4/boards.txt
@@ -8,9 +8,8 @@ discovery_f407.upload.protocol=stlink
 
 #discovery_f407.upload.use_1200bps_touch=false
 discovery_f407.upload.file_type=bin
-discovery_f407.upload.ram.maximum_size=17000
-discovery_f407.upload.flash.maximum_size=1048576
 discovery_f407.upload.maximum_size=1048576
+discovery_f407.upload.maximum_data_size=196608
 
 #discovery_f407.upload.usbID=1EAF:0003
 #discovery_f407.upload.altID=1
@@ -37,9 +36,8 @@ stm32f4stamp.upload.protocol=maple_dfu
 
 #stm32f4stamp.upload.use_1200bps_touch=false
 stm32f4stamp.upload.file_type=bin
-stm32f4stamp.upload.ram.maximum_size=196608
-stm32f4stamp.upload.flash.maximum_size=1048576
 stm32f4stamp.upload.maximum_size=1048576
+stm32f4stamp.upload.maximum_data_size=196608
 
 stm32f4stamp.upload.usbID=0483:df11
 stm32f4stamp.upload.altID=0
@@ -67,9 +65,8 @@ netduino2plus.upload.protocol=maple_dfu
 
 #netduino2plus.upload.use_1200bps_touch=false
 netduino2plus.upload.file_type=bin
-netduino2plus.upload.ram.maximum_size=196608
-netduino2plus.upload.flash.maximum_size=1048576
 netduino2plus.upload.maximum_size=1048576
+netduino2plus.upload.maximum_data_size=196608
 
 netduino2plus.upload.usbID=0483:df11
 netduino2plus.upload.altID=0

From 76dcee39a93618ad5c188e4e30afdbf537a64878 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Fri, 23 Dec 2016 09:48:43 +1100
Subject: [PATCH 035/307] Removed old - mainly non functional Due related
 display examples

---
 .../libraries/ILI9341_due_STM/ILI9341_due.cpp | 1670 --------------
 .../libraries/ILI9341_due_STM/ILI9341_due.h   | 1171 ----------
 .../ILI9341_due_STM/ILI9341_due_gText.cpp     | 1936 -----------------
 .../ILI9341_due_STM/ILI9341_due_gText.h       |  385 ----
 .../ILI9341_due_STM/ILI_SdFatConfig.h         |  196 --
 STM32F1/libraries/ILI9341_due_STM/ILI_SdSpi.h |  188 --
 .../ILI9341_due_STM/ILI_SdSpiSAM3X.cpp        |  411 ----
 STM32F1/libraries/ILI9341_due_STM/README.md   |   48 -
 .../ILI9341_due_STM/examples/arcs/arcs.ino    |  243 ---
 .../ILI9341_due_STM/examples/arcs/roboto16.h  |  167 --
 .../ILI9341_due_STM/examples/arcs/roboto32.h  |  165 --
 .../ILI9341_due_STM/examples/arcs/roboto70.h  |   74 -
 .../examples/gTextBigFont/gTextBigFont.ino    |   63 -
 .../gTextHelloWorld/gTextHelloWorld.ino       |   39 -
 .../examples/graphicstest/graphicstest.ino    |  410 ----
 .../graphicstestWithStats.ino                 |  427 ----
 .../sdFatTftBitmap/images/blacklab.565        |  Bin 153654 -> 0 bytes
 .../sdFatTftBitmap/images/blacklab.bmp        |  Bin 230454 -> 0 bytes
 .../sdFatTftBitmap/images/giraffe.565         |  Bin 153654 -> 0 bytes
 .../sdFatTftBitmap/images/giraffe.bmp         |  Bin 230454 -> 0 bytes
 .../sdFatTftBitmap/images/gloomyTears.565     |  Bin 153654 -> 0 bytes
 .../sdFatTftBitmap/images/gloomyTears.bmp     |  Bin 230454 -> 0 bytes
 .../examples/sdFatTftBitmap/images/health.565 |  Bin 153654 -> 0 bytes
 .../examples/sdFatTftBitmap/images/health.bmp |  Bin 230454 -> 0 bytes
 .../examples/sdFatTftBitmap/images/lambo.565  |  Bin 153654 -> 0 bytes
 .../examples/sdFatTftBitmap/images/lambo.bmp  |  Bin 230454 -> 0 bytes
 .../sdFatTftBitmap/images/motivation.565      |  Bin 153654 -> 0 bytes
 .../sdFatTftBitmap/images/motivation.bmp      |  Bin 230454 -> 0 bytes
 .../examples/sdFatTftBitmap/images/origP.565  |  Bin 153654 -> 0 bytes
 .../examples/sdFatTftBitmap/images/origP.bmp  |  Bin 230454 -> 0 bytes
 .../examples/sdFatTftBitmap/images/radioP.565 |  Bin 153654 -> 0 bytes
 .../examples/sdFatTftBitmap/images/radioP.bmp |  Bin 230454 -> 0 bytes
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diff --git a/STM32F1/libraries/ILI9341_due_STM/ILI9341_due.cpp b/STM32F1/libraries/ILI9341_due_STM/ILI9341_due.cpp
deleted file mode 100644
index 1338e5aa0..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/ILI9341_due.cpp
+++ /dev/null
@@ -1,1670 +0,0 @@
-/*
-ILI9341_due_.cpp - Arduino Due library for interfacing with ILI9341-based TFTs
-
-Copyright (c) 2014  Marek Buriak
-Modified 03/19/2015 by Victor Perez to add STM32F1 Maple mini DMA support
-
-This library is based on ILI9341_t3 library from Paul Stoffregen
-(https://github.com/PaulStoffregen/ILI9341_t3), Adafruit_ILI9341
-and Adafruit_GFX libraries from Limor Fried/Ladyada
-(https://github.com/adafruit/Adafruit_ILI9341).
-
-This file is part of the Arduino ILI9341_due library.
-Sources for this library can be found at https://github.com/marekburiak/ILI9341_Due.
-
-ILI9341_due is free software: you can redistribute it and/or modify
-it under the terms of the GNU Lesser General Public License as published by
-the Free Software Foundation, either version 2.1 of the License, or
-(at your option) any later version.
-
-ILI9341_due is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU Lesser General Public License for more details.
-
-You should have received a copy of the GNU Lesser General Public License
-along with ILI9341_due.  If not, see <http://www.gnu.org/licenses/>.
-
-*/
-
-/***************************************************
-This is our library for the Adafruit ILI9341 Breakout and Shield
-----> http://www.adafruit.com/products/1651
-
-Check out the links above for our tutorials and wiring diagrams
-These displays use SPI to communicate, 4 or 5 pins are required to
-interface (RST is optional)
-Adafruit invests time and resources providing this open source code,
-please support Adafruit and open-source hardware by purchasing
-products from Adafruit!
-
-Written by Limor Fried/Ladyada for Adafruit Industries.
-MIT license, all text above must be included in any redistribution
-****************************************************/
-
-#include "ILI9341_due.h"
-#if SPI_MODE_NORMAL | SPI_MODE_EXTENDED
-#include <SPI.h>
-#elif SPI_MODE_DMA
-#include "ILI_SdSpi.h"
-#include <libmaple/dma.h>
-#endif
-//#include "..\Streaming\Streaming.h"
-
-
-static const uint8_t init_commands[] PROGMEM = {
-	4, 0xEF, 0x03, 0x80, 0x02,
-	4, 0xCF, 0x00, 0XC1, 0X30,
-	5, 0xED, 0x64, 0x03, 0X12, 0X81,
-	4, 0xE8, 0x85, 0x00, 0x78,
-	6, 0xCB, 0x39, 0x2C, 0x00, 0x34, 0x02,
-	2, 0xF7, 0x20,
-	3, 0xEA, 0x00, 0x00,
-	2, ILI9341_PWCTR1, 0x23, // Power control
-	2, ILI9341_PWCTR2, 0x10, // Power control
-	3, ILI9341_VMCTR1, 0x3e, 0x28, // VCM control
-	2, ILI9341_VMCTR2, 0x86, // VCM control2
-	2, ILI9341_MADCTL, 0x48, // Memory Access Control
-	2, ILI9341_PIXFMT, 0x55,
-	3, ILI9341_FRMCTR1, 0x00, 0x18,
-	4, ILI9341_DFUNCTR, 0x08, 0x82, 0x27, // Display Function Control
-	2, 0xF2, 0x00, // Gamma Function Disable
-	2, ILI9341_GAMMASET, 0x01, // Gamma curve selected
-	16, ILI9341_GMCTRP1, 0x0F, 0x31, 0x2B, 0x0C, 0x0E, 0x08,
-	0x4E, 0xF1, 0x37, 0x07, 0x10, 0x03, 0x0E, 0x09, 0x00, // Set Gamma
-	16, ILI9341_GMCTRN1, 0x00, 0x0E, 0x14, 0x03, 0x11, 0x07,
-	0x31, 0xC1, 0x48, 0x08, 0x0F, 0x0C, 0x31, 0x36, 0x0F, // Set Gamma
-	0
-};
-
-
-ILI9341_due::ILI9341_due(uint8_t cs, uint8_t dc, uint8_t rst)
-{
-	_cs = cs;
-	_dc = dc;
-	_rst = rst;
-	_width = ILI9341_TFTWIDTH;
-	_height = ILI9341_TFTHEIGHT;
-	_rotation = iliRotation0;
-#ifdef FEATURE_PRINT_ENABLED
-	_cursorY = _cursorX = 0;
-	_textsize = 1;
-	_textcolor = _textbgcolor = 0xFFFF;
-	_wrap = true;
-#endif
-#ifdef FEATURE_ARC_ENABLED
-	_arcAngleMax = ARC_ANGLE_MAX;
-	_arcAngleOffset = ARC_ANGLE_OFFSET;
-#endif
-}
-
-
-bool ILI9341_due::begin(void)
-{
-	if (pinIsChipSelect(_cs)) {
-		pinMode(_dc, OUTPUT);
-		_dcport = portOutputRegister(digitalPinToPort(_dc));
-		_dcpinmask = digitalPinToBitMask(_dc);
-
-#if SPI_MODE_NORMAL | SPI_MODE_DMA
-		pinMode(_cs, OUTPUT);
-		_csport = portOutputRegister(digitalPinToPort(_cs));
-		_cspinmask = digitalPinToBitMask(_cs);
-#endif
-
-#if SPI_MODE_NORMAL
-		SPI.begin();
-		SPI.setClockDivider(ILI9341_SPI_CLKDIVIDER);
-		SPI.setBitOrder(MSBFIRST);
-		SPI.setDataMode(SPI_MODE0);
-#ifdef __AVR__
-		_SPCR = SPCR;
-#endif
-#elif SPI_MODE_EXTENDED
-		SPI.begin(_cs);
-		SPI.setClockDivider(_cs, ILI9341_SPI_CLKDIVIDER);
-		SPI.setBitOrder(_cs, MSBFIRST);
-		SPI.setDataMode(_cs, SPI_MODE0);
-#elif SPI_MODE_DMA
-		_dmaSpi.begin();
-		_dmaSpi.init(ILI9341_SPI_CLKDIVIDER);
-#endif
-
-		// toggle RST low to reset
-		if (_rst < 255) {
-			pinMode(_rst, OUTPUT);
-			digitalWrite(_rst, HIGH);
-			delay(5);
-			digitalWrite(_rst, LOW);
-			delay(20);
-			digitalWrite(_rst, HIGH);
-			delay(150);
-		}
-
-		const uint8_t *addr = init_commands;
-		while (1) {
-			uint8_t count = pgm_read_byte(addr++);
-			if (count-- == 0) break;
-			writecommand_cont(pgm_read_byte(addr++));
-			while (count-- > 0) {
-				writedata8_cont(pgm_read_byte(addr++));
-			}
-		}
-
-		writecommand_last(ILI9341_SLPOUT);    // Exit Sleep
-		delay(120);
-		writecommand_last(ILI9341_DISPON);    // Display on
-		delay(120);
-		_isInSleep = _isIdle = false;
-
-		uint8_t x = readcommand8(ILI9341_RDMODE);
-		Serial.print(F("\nDisplay Power Mode: 0x")); Serial.println(x, HEX);
-		x = readcommand8(ILI9341_RDMADCTL);
-		Serial.print(F("\nMADCTL Mode: 0x")); Serial.println(x, HEX);
-		x = readcommand8(ILI9341_RDPIXFMT);
-		Serial.print(F("\nPixel Format: 0x")); Serial.println(x, HEX);
-		x = readcommand8(ILI9341_RDIMGFMT);
-		Serial.print(F("\nImage Format: 0x")); Serial.println(x, HEX);
-		x = readcommand8(ILI9341_RDSELFDIAG);
-		Serial.print(F("\nSelf Diagnostic: 0x")); Serial.println(x, HEX);
-
-		return true;
-	}
-	else {
-		return false;
-	}
-}
-
-bool ILI9341_due::pinIsChipSelect(uint8_t cs)
-{
-#if SPI_MODE_EXTENDED
-	if(cs == 4 || cs == 10 || cs == 52)	// in Extended SPI mode only these pins are valid
-	{
-		return true;
-	}
-	else
-	{
-		Serial.print("Pin ");
-		Serial.print(_cs);
-		Serial.println(" is not a valid Chip Select pin for SPI Extended Mode. Valid pins are 4, 10, 52");
-		return false;
-	}
-#elif SPI_MODE_NORMAL | SPI_MODE_DMA
-	return true;
-#endif
-}
-
-void ILI9341_due::setAddrWindow(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1)
-{
-	setAddrAndRW_cont(x0, y0, x1, y1);
-	disableCS();
-}
-
-void ILI9341_due::setSPIClockDivider(uint8_t divider)
-{
-#if SPI_MODE_NORMAL
-	SPI.setClockDivider(divider);
-#elif SPI_MODE_EXTENDED
-	SPI.setClockDivider(_cs, divider);
-#elif SPI_MODE_DMA
-	_dmaSpi.init(divider);
-#endif
-}
-
-void ILI9341_due::pushColor(uint16_t color)
-{
-	enableCS();
-	writedata16_last(color);
-}
-
-void ILI9341_due::pushColors(uint16_t *colors, uint16_t offset, uint16_t len) {
-	enableCS();
-	setDCForData();
-	colors = colors + offset * 2;
-#if SPI_MODE_NORMAL | SPI_MODE_EXTENDED
-	for (uint16_t i = 0; i < len; i++) {
-		write16_cont(colors[i]);
-	}
-#elif SPI_MODE_DMA
-	for (uint16_t i = 0; i < (len << 1); i += 2) {
-		uint16_t color = *colors;
-		_scanlineBuffer[i] = highByte(color);
-		_scanlineBuffer[i + 1] = lowByte(color);
-		colors++;
-	}
-	writeScanline_cont(len);
-#endif
-	disableCS();
-}
-
-// pushes pixels stored in the colors array (one color is 2 bytes) 
-// in big endian (high byte first)
-// len should be the length of the array (so to push 320 pixels,
-// you have to have a 640-byte array and len should be 640)
-void ILI9341_due::pushColors565(uint8_t *colors, uint16_t offset, uint16_t len) {
-	enableCS();
-	setDCForData();
-	colors = colors + offset;
-
-#if SPI_MODE_NORMAL | SPI_MODE_EXTENDED
-	for (uint16_t i = 0; i < len; i++) {
-		write8_cont(colors[i]);
-	}
-#elif SPI_MODE_DMA
-	write_cont(colors, len);
-#endif
-	disableCS();
-}
-
-
-void ILI9341_due::drawPixel(int16_t x, int16_t y, uint16_t color) {
-
-	if ((x < 0) || (x >= _width) || (y < 0) || (y >= _height)) return;
-	writePixel_last(x, y, color);
-}
-
-void ILI9341_due::drawPixel_cont(int16_t x, int16_t y, uint16_t color) {
-
-	if ((x < 0) || (x >= _width) || (y < 0) || (y >= _height)) return;
-	writePixel_cont(x, y, color);
-}
-
-void ILI9341_due::drawFastVLine(int16_t x, int16_t y, int16_t h, uint16_t color)
-{
-	// Rudimentary clipping
-	if ((x >= _width) || (y >= _height || h == 0)) return;
-	if ((y + h - 1) >= _height) h = _height - y;
-
-	setAddrAndRW_cont(x, y, x, y + h - 1);
-#if SPI_MODE_NORMAL | SPI_MODE_EXTENDED
-	setDCForData();
-	while (h-- > 1) {
-		write16_cont(color);
-	}
-	write16_last(color);
-#elif SPI_MODE_DMA
-	fillScanline(color, h);
-	writeScanline_last(h);
-#endif
-}
-
-void ILI9341_due::drawFastVLine_cont_noFill(int16_t x, int16_t y, int16_t h, uint16_t color)
-{
-	// Rudimentary clipping
-	if ((x >= _width) || (y >= _height || h == 0)) return;
-	if ((y + h - 1) >= _height) h = _height - y;
-
-	setAddrAndRW_cont(x, y, x, y + h - 1);
-#if SPI_MODE_NORMAL | SPI_MODE_EXTENDED
-	setDCForData();
-	while (h-- > 0) {
-		write16_cont(color);
-	}
-#elif SPI_MODE_DMA
-	writeScanline_cont(h);
-#endif
-}
-
-void ILI9341_due::drawFastHLine(int16_t x, int16_t y, int16_t w, uint16_t color)
-{
-	// Rudimentary clipping
-	if ((x >= _width) || (y >= _height || w == 0)) return;
-	if ((x + w - 1) >= _width)  w = _width - x;
-
-	setAddrAndRW_cont(x, y, x + w - 1, y);
-#if SPI_MODE_NORMAL | SPI_MODE_EXTENDED
-	setDCForData();
-	while (w-- > 1) {
-		write16_cont(color);
-	}
-	writedata16_last(color);
-#elif SPI_MODE_DMA
-	fillScanline(color, w);
-	writeScanline_last(w);
-#endif
-}
-
-void ILI9341_due::fillScreen(uint16_t color)
-{
-#if SPI_MODE_NORMAL | SPI_MODE_EXTENDED
-	fillRect(0, 0, _width, _height, color);
-#elif SPI_MODE_DMA
-
-	fillScanline(color);
-
-	setAddrAndRW_cont(0, 0, _width - 1, _height - 1);
-	setDCForData();
-	const uint16_t bytesToWrite = _width << 1;
-	for (uint16_t y = 0; y < _height; y++)
-	{
-		write_cont(_scanlineBuffer, bytesToWrite);
-	}
-	disableCS();
-
-#endif
-}
-
-// fill a rectangle
-void ILI9341_due::fillRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color)
-{
-	//Serial << "x:" << x << " y:" << y << " w:" << x << " h:" << h << " width:" << _width << " height:" << _height <<endl;
-	// rudimentary clipping (drawChar w/big text requires this)
-	if ((x >= _width) || (y >= _height || w == 0 || h == 0)) return;
-	if ((x + w - 1) >= _width)  w = _width - x;
-	if ((y + h - 1) >= _height) h = _height - y;
-
-	setAddrAndRW_cont(x, y, x + w - 1, y + h - 1);
-#if SPI_MODE_DMA
-	const uint16_t maxNumLinesInScanlineBuffer = (SCANLINE_BUFFER_SIZE >> 1) / w;
-	const uint16_t numPixelsInOneGo = w*maxNumLinesInScanlineBuffer;
-
-	fillScanline(color, numPixelsInOneGo);
-
-	for (uint16_t p = 0; p < h / maxNumLinesInScanlineBuffer; p++)
-	{
-		writeScanline_cont(numPixelsInOneGo);
-	}
-	writeScanline_last((w*h) % numPixelsInOneGo);
-
-#elif SPI_MODE_NORMAL | SPI_MODE_EXTENDED
-	// TODO: this can result in a very long transaction time
-	// should break this into multiple transactions, even though
-	// it'll cost more overhead, so we don't stall other SPI libs
-	//enableCS();	//setAddrAndRW_cont will enable CS 
-	setDCForData();
-
-	y=h;
-	while(y--) {
-		x=w;
-		while(x--)
-		{
-			write16_cont(color);
-		}
-	}
-
-	disableCS();
-#endif
-}
-
-
-#define MADCTL_MY  0x80
-#define MADCTL_MX  0x40
-#define MADCTL_MV  0x20
-#define MADCTL_ML  0x10
-#define MADCTL_RGB 0x00
-#define MADCTL_BGR 0x08
-#define MADCTL_MH  0x04
-
-void ILI9341_due::setRotation(iliRotation r)
-{
-	writecommand_cont(ILI9341_MADCTL);
-	_rotation = r;
-	switch (r) {
-	case iliRotation0:
-		writedata8_last(MADCTL_MX | MADCTL_BGR);
-		_width = ILI9341_TFTWIDTH;
-		_height = ILI9341_TFTHEIGHT;
-		break;
-	case iliRotation90:
-		writedata8_last(MADCTL_MV | MADCTL_BGR);
-		_width = ILI9341_TFTHEIGHT;
-		_height = ILI9341_TFTWIDTH;
-		break;
-	case iliRotation180:
-		writedata8_last(MADCTL_MY | MADCTL_BGR);
-		_width = ILI9341_TFTWIDTH;
-		_height = ILI9341_TFTHEIGHT;
-		break;
-	case iliRotation270:
-		writedata8_last(MADCTL_MX | MADCTL_MY | MADCTL_MV | MADCTL_BGR);
-		_width = ILI9341_TFTHEIGHT;
-		_height = ILI9341_TFTWIDTH;
-		break;
-	}
-}
-
-
-void ILI9341_due::invertDisplay(boolean i)
-{
-	writecommand_last(i ? ILI9341_INVON : ILI9341_INVOFF);
-}
-
-
-uint8_t ILI9341_due::readcommand8(uint8_t c, uint8_t index) {
-	writecommand_cont(0xD9);  // woo sekret command?
-	writedata8_last(0x10 + index);
-	writecommand_cont(c);
-
-	return readdata8_last();
-}
-
-// Reads one pixel/color from the TFT's GRAM
-uint16_t ILI9341_due::readPixel(int16_t x, int16_t y)
-{
-	setAddr_cont(x, y, x + 1, y + 1);
-	writecommand_cont(ILI9341_RAMRD); // read from RAM
-	readdata8_cont(); // dummy read
-	uint8_t red = read8_cont();
-	uint8_t green = read8_cont();
-	uint8_t blue = read8_last();
-	return color565(red, green, blue);
-}
-
-//void ILI9341_due::drawArc(uint16_t cx, uint16_t cy, uint16_t radius, uint16_t thickness, uint16_t start, uint16_t end, uint16_t color) {
-//	//void graphics_draw_arc(GContext *ctx, GPoint p, int radius, int thickness, int start, int end) {
-//	start = start % 360;
-//	end = end % 360;
-//
-//	while (start < 0) start += 360;
-//	while (end < 0) end += 360;
-//
-//	if (end == 0) end = 360;
-//
-//	//Serial << "start: " << start << " end:" << end << endl;
-//
-//	// Serial <<  (float)cos_lookup(start * ARC_MAX_STEPS / 360) << " x " << (float)sin_lookup(start * ARC_MAX_STEPS / 360) << endl;
-//
-//	float sslope = (float)cos_lookup(start * ARC_MAX_STEPS / 360) / (float)sin_lookup(start * ARC_MAX_STEPS / 360);
-//	float eslope = (float)cos_lookup(end * ARC_MAX_STEPS / 360) / (float)sin_lookup(end * ARC_MAX_STEPS / 360);
-//
-//	//Serial << "sslope: " << sslope << " eslope:" << eslope << endl;
-//
-//	if (end == 360) eslope = -1000000;
-//
-//	int ir2 = (radius - thickness) * (radius - thickness);
-//	int or2 = radius * radius;
-//
-//	for (int x = -radius; x <= radius; x++)
-//		for (int y = -radius; y <= radius; y++)
-//		{
-//			int x2 = x * x;
-//			int y2 = y * y;
-//
-//			if (
-//				(x2 + y2 < or2 && x2 + y2 >= ir2) &&
-//				(
-//				(y > 0 && start < 180 && x <= y * sslope) ||
-//				(y < 0 && start > 180 && x >= y * sslope) ||
-//				(y < 0 && start <= 180) ||
-//				(y == 0 && start <= 180 && x < 0) ||
-//				(y == 0 && start == 0 && x > 0)
-//				) &&
-//				(
-//				(y > 0 && end < 180 && x >= y * eslope) ||
-//				(y < 0 && end > 180 && x <= y * eslope) ||
-//				(y > 0 && end >= 180) ||
-//				(y == 0 && end >= 180 && x < 0) ||
-//				(y == 0 && start == 0 && x > 0)
-//				)
-//				)
-//				drawPixel_cont(cx+x, cy+y, color);
-//		}
-//}
-
-
-
-#ifdef FEATURE_ARC_ENABLED
-// DrawArc function thanks to Jnmattern and his Arc_2.0 (https://github.com/Jnmattern)
-void ILI9341_due::drawArcOffsetted(uint16_t cx, uint16_t cy, uint16_t radius, uint16_t thickness, float start, float end, uint16_t color) {
-	int16_t xmin = 65535, xmax = -32767, ymin = 32767, ymax = -32767;
-	float cosStart, sinStart, cosEnd, sinEnd;
-	float r, t;
-	float startAngle, endAngle;
-
-	//Serial << "start: " << start << " end: " << end << endl;
-	startAngle = (start / _arcAngleMax) * 360;	// 252
-	endAngle = (end / _arcAngleMax) * 360;		// 807
-	//Serial << "startAngle: " << startAngle << " endAngle: " << endAngle << endl;
-
-	while (startAngle < 0) startAngle += 360;
-	while (endAngle < 0) endAngle += 360;
-	while (startAngle > 360) startAngle -= 360;
-	while (endAngle > 360) endAngle -= 360;
-	//Serial << "startAngleAdj: " << startAngle << " endAngleAdj: " << endAngle << endl;
-	//if (endAngle == 0) endAngle = 360;
-
-	if (startAngle > endAngle) {
-		drawArcOffsetted(cx, cy, radius, thickness, ((startAngle) / (float)360) * _arcAngleMax, _arcAngleMax, color);
-		drawArcOffsetted(cx, cy, radius, thickness, 0, ((endAngle) / (float)360) * _arcAngleMax, color);
-	}
-	else {
-		// Calculate bounding box for the arc to be drawn
-		cosStart = cosDegrees(startAngle);
-		sinStart = sinDegrees(startAngle);
-		cosEnd = cosDegrees(endAngle);
-		sinEnd = sinDegrees(endAngle);
-
-		//Serial << cosStart << " " << sinStart << " " << cosEnd << " " << sinEnd << endl;
-
-		r = radius;
-		// Point 1: radius & startAngle
-		t = r * cosStart;
-		if (t < xmin) xmin = t;
-		if (t > xmax) xmax = t;
-		t = r * sinStart;
-		if (t < ymin) ymin = t;
-		if (t > ymax) ymax = t;
-
-		// Point 2: radius & endAngle
-		t = r * cosEnd;
-		if (t < xmin) xmin = t;
-		if (t > xmax) xmax = t;
-		t = r * sinEnd;
-		if (t < ymin) ymin = t;
-		if (t > ymax) ymax = t;
-
-		r = radius - thickness;
-		// Point 3: radius-thickness & startAngle
-		t = r * cosStart;
-		if (t < xmin) xmin = t;
-		if (t > xmax) xmax = t;
-		t = r * sinStart;
-		if (t < ymin) ymin = t;
-		if (t > ymax) ymax = t;
-
-		// Point 4: radius-thickness & endAngle
-		t = r * cosEnd;
-		if (t < xmin) xmin = t;
-		if (t > xmax) xmax = t;
-		t = r * sinEnd;
-		if (t < ymin) ymin = t;
-		if (t > ymax) ymax = t;
-
-
-		//Serial << xmin << " " << xmax << " " << ymin << " " << ymax << endl;
-		// Corrections if arc crosses X or Y axis
-		if ((startAngle < 90) && (endAngle > 90)) {
-			ymax = radius;
-		}
-
-		if ((startAngle < 180) && (endAngle > 180)) {
-			xmin = -radius;
-		}
-
-		if ((startAngle < 270) && (endAngle > 270)) {
-			ymin = -radius;
-		}
-
-		// Slopes for the two sides of the arc
-		float sslope = (float)cosStart / (float)sinStart;
-		float eslope = (float)cosEnd / (float)sinEnd;
-
-		//Serial << "sslope2: " << sslope << " eslope2:" << eslope << endl;
-
-		if (endAngle == 360) eslope = -1000000;
-
-		int ir2 = (radius - thickness) * (radius - thickness);
-		int or2 = radius * radius;
-		//Serial << "ymin: " << ymin << " ymax: " << ymax << endl;
-#if SPI_MODE_DMA
-		fillScanline(color, radius << 1);
-#endif
-		for (int x = xmin; x <= xmax; x++) {
-			bool y1StartFound = false, y2StartFound = false;
-			bool y1EndFound = false, y2EndSearching = false;
-			int y1s = 0, y1e = 0, y2s = 0, y2e = 0;
-			for (int y = ymin; y <= ymax; y++)
-			{
-				int x2 = x * x;
-				int y2 = y * y;
-
-				if (
-					(x2 + y2 < or2 && x2 + y2 >= ir2) && (
-					(y > 0 && startAngle < 180 && x <= y * sslope) ||
-					(y < 0 && startAngle > 180 && x >= y * sslope) ||
-					(y < 0 && startAngle <= 180) ||
-					(y == 0 && startAngle <= 180 && x < 0) ||
-					(y == 0 && startAngle == 0 && x > 0)
-					) && (
-					(y > 0 && endAngle < 180 && x >= y * eslope) ||
-					(y < 0 && endAngle > 180 && x <= y * eslope) ||
-					(y > 0 && endAngle >= 180) ||
-					(y == 0 && endAngle >= 180 && x < 0) ||
-					(y == 0 && startAngle == 0 && x > 0)))
-				{
-					if (!y1StartFound)	//start of the higher line found
-					{
-						y1StartFound = true;
-						y1s = y;
-					}
-					else if (y1EndFound && !y2StartFound) //start of the lower line found
-					{
-						//Serial << "Found y2 start x: " << x << " y:" << y << endl;
-						y2StartFound = true;
-						//drawPixel_cont(cx+x, cy+y, ILI9341_BLUE);
-						y2s = y;
-						y += y1e - y1s - 1;	// calculate the most probable end of the lower line (in most cases the length of lower line is equal to length of upper line), in the next loop we will validate if the end of line is really there
-						if (y > ymax - 1) // the most probable end of line 2 is beyond ymax so line 2 must be shorter, thus continue with pixel by pixel search
-						{
-							y = y2s;	// reset y and continue with pixel by pixel search
-							y2EndSearching = true;
-						}
-
-						//Serial << "Upper line length: " << (y1e - y1s) << " Setting y to " << y << endl;
-					}
-					else if (y2StartFound && !y2EndSearching)
-					{
-						// we validated that the probable end of the lower line has a pixel, continue with pixel by pixel search, in most cases next loop with confirm the end of lower line as it will not find a valid pixel
-						y2EndSearching = true;
-					}
-					//Serial << "x:" << x << " y:" << y << endl;
-					//drawPixel_cont(cx+x, cy+y, ILI9341_BLUE);
-				}
-				else
-				{
-					if (y1StartFound && !y1EndFound) //higher line end found
-					{
-						y1EndFound = true;
-						y1e = y - 1;
-						//Serial << "line: " << y1s << " - " << y1e << endl;
-						drawFastVLine_cont_noFill(cx + x, cy + y1s, y - y1s, color);
-						if (y < 0)
-						{
-							//Serial << x << " " << y << endl;
-							y = abs(y); // skip the empty middle
-						}
-						else
-							break;
-					}
-					else if (y2StartFound)
-					{
-						if (y2EndSearching)
-						{
-							//Serial << "Found final end at y: " << y << endl;
-							// we found the end of the lower line after pixel by pixel search
-							drawFastVLine_cont_noFill(cx + x, cy + y2s, y - y2s, color);
-							y2EndSearching = false;
-							break;
-						}
-						else
-						{
-							//Serial << "Expected end not found" << endl;
-							// the expected end of the lower line is not there so the lower line must be shorter
-							y = y2s;	// put the y back to the lower line start and go pixel by pixel to find the end
-							y2EndSearching = true;
-						}
-					}
-					//else
-					//drawPixel_cont(cx+x, cy+y, ILI9341_RED);
-				}
-				//
-
-				//delay(75);
-			}
-			if (y1StartFound && !y1EndFound)
-			{
-				y1e = ymax;
-				//Serial << "line: " << y1s << " - " << y1e << endl;
-				drawFastVLine_cont_noFill(cx + x, cy + y1s, y1e - y1s + 1, color);
-			}
-			else if (y2StartFound && y2EndSearching)	// we found start of lower line but we are still searching for the end
-			{										// which we haven't found in the loop so the last pixel in a column must be the end
-				drawFastVLine_cont_noFill(cx + x, cy + y2s, ymax - y2s + 1, color);
-			}
-		}
-		disableCS();
-	}
-}
-#endif
-
-void ILI9341_due::screenshotToConsole()
-{
-	uint16_t color565;
-	uint8_t lastColor[3];
-	uint8_t color[3];
-	uint32_t sameColorPixelCount = 0;
-	uint16_t sameColorPixelCount16 = 0;
-	uint32_t sameColorStartIndex = 0;
-	uint32_t totalImageDataLength = 0;
-
-	Serial.println(F("==== PIXEL DATA START ===="));
-	//uint16_t x=0;
-	//uint16_t y=0;
-	setAddr_cont(0, 0, _width - 1, _height - 1);
-	writecommand_cont(ILI9341_RAMRD); // read from RAM
-	readdata8_cont(); // dummy read, also sets DC high
-
-#if SPI_MODE_DMA
-	read_cont(color, 3);
-	lastColor[0] = color[0];
-	lastColor[1] = color[1];
-	lastColor[2] = color[2];
-#elif SPI_MODE_NORMAL | SPI_MODE_EXTENDED
-	lastColor[0] = color[0] = read8_cont();
-	lastColor[1] = color[1] = read8_cont();
-	lastColor[2] = color[2] = read8_cont();
-#endif
-	printHex8(color, 3);	//write color of the first pixel
-	totalImageDataLength += 6;
-	sameColorStartIndex = 0;
-
-	for (uint32_t i = 1; i < _width*_height; i++)
-	{
-#if SPI_MODE_DMA
-		read_cont(color, 3);
-#elif SPI_MODE_NORMAL | SPI_MODE_EXTENDED
-		color[0] = read8_cont();
-		color[1] = read8_cont();
-		color[2] = read8_cont();
-#endif
-
-		if (color[0] != lastColor[0] ||
-			color[1] != lastColor[1] ||
-			color[2] != lastColor[2])
-		{
-			sameColorPixelCount = i - sameColorStartIndex;
-			if (sameColorPixelCount > 65535)
-			{
-				sameColorPixelCount16 = 65535;
-				printHex16(&sameColorPixelCount16, 1);
-				printHex8(lastColor, 3);
-				totalImageDataLength += 10;
-				sameColorPixelCount16 = sameColorPixelCount - 65535;
-			}
-			else
-				sameColorPixelCount16 = sameColorPixelCount;
-			printHex16(&sameColorPixelCount16, 1);
-			printHex8(color, 3);
-			totalImageDataLength += 10;
-
-			sameColorStartIndex = i;
-			lastColor[0] = color[0];
-			lastColor[1] = color[1];
-			lastColor[2] = color[2];
-		}
-	}
-	sameColorPixelCount = _width*_height - sameColorStartIndex;
-	if (sameColorPixelCount > 65535)
-	{
-		sameColorPixelCount16 = 65535;
-		printHex16(&sameColorPixelCount16, 1);
-		printHex8(lastColor, 3);
-		totalImageDataLength += 10;
-		sameColorPixelCount16 = sameColorPixelCount - 65535;
-	}
-	else
-		sameColorPixelCount16 = sameColorPixelCount;
-	printHex16(&sameColorPixelCount16, 1);
-	totalImageDataLength += 4;
-	printHex32(&totalImageDataLength, 1);
-
-	/*for(uint16_t x=0; x<_width; x++)
-	{
-	for(uint16_t y=0; y<_height; y++)
-	{
-	color[0] = read8();
-	color[1] = read8();
-	color[2] = read8();
-
-	if(color[0] != lastColor[0] ||
-	color[1] != lastColor[1] ||
-	color[2] != lastColor[2])
-	{
-
-	}
-
-	PrintHex8(color, 3);
-	}
-	}*/
-	Serial.println();
-	Serial.println(F("==== PIXEL DATA END ===="));
-	Serial.print(F("Total Image Data Length: "));
-	Serial.println(totalImageDataLength);
-#if SPI_MODE_DMA
-	_dmaSpi.init(ILI9341_SPI_CLKDIVIDER);
-#endif
-	disableCS();
-}
-
-/*
-This is the core graphics library for all our displays, providing a common
-set of graphics primitives (points, lines, circles, etc.).  It needs to bex
-paired with a hardware-specific library for each display device we carry
-(to handle the lower-level functions).
-
-Adafruit invests time and resources providing this open source code, please
-support Adafruit & open-source hardware by purchasing products from Adafruit!
-
-Copyright (c) 2013 Adafruit Industries.  All rights reserved.
-
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are met:
-
-- Redistributions of source code must retain the above copyright notice,
-this list of conditions and the following disclaimer.
-- Redistributions in binary form must reproduce the above copyright notice,
-this list of conditions and the following disclaimer in the documentation
-and/or other materials provided with the distribution.
-
-THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
-AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
-IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
-ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE
-LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
-CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
-SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
-INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
-CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
-ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
-POSSIBILITY OF SUCH DAMAGE.
-*/
-
-#include "glcdfont.c"
-
-// Draw a circle outline
-void ILI9341_due::drawCircle(int16_t x0, int16_t y0, int16_t r, uint16_t color)
-{
-	int16_t f = 1 - r;
-	int16_t ddF_x = 1;
-	int16_t ddF_y = -2 * r;
-	int16_t x = 0;
-	int16_t y = r;
-
-	drawPixel_cont(x0, y0 + r, color);
-	drawPixel_cont(x0, y0 - r, color);
-	drawPixel_cont(x0 + r, y0, color);
-	drawPixel_cont(x0 - r, y0, color);
-
-	while (x < y) {
-		if (f >= 0) {
-			y--;
-			ddF_y += 2;
-			f += ddF_y;
-		}
-		x++;
-		ddF_x += 2;
-		f += ddF_x;
-
-		drawPixel_cont(x0 + x, y0 + y, color);
-		drawPixel_cont(x0 - x, y0 + y, color);
-		drawPixel_cont(x0 + x, y0 - y, color);
-		drawPixel_cont(x0 - x, y0 - y, color);
-		drawPixel_cont(x0 + y, y0 + x, color);
-		drawPixel_cont(x0 - y, y0 + x, color);
-		drawPixel_cont(x0 + y, y0 - x, color);
-		drawPixel_cont(x0 - y, y0 - x, color);
-	}
-	disableCS();
-}
-
-
-void ILI9341_due::drawCircleHelper(int16_t x0, int16_t y0,
-	int16_t r, uint8_t cornername, uint16_t color)
-{
-	int16_t f = 1 - r;
-	int16_t ddF_x = 1;
-	int16_t ddF_y = -2 * r;
-	int16_t x = 0;
-	int16_t y = r;
-
-	while (x < y) {
-		if (f >= 0) {
-			y--;
-			ddF_y += 2;
-			f += ddF_y;
-		}
-		x++;
-		ddF_x += 2;
-		f += ddF_x;
-		if (cornername & 0x4) {
-			drawPixel_cont(x0 + x, y0 + y, color);
-			drawPixel_cont(x0 + y, y0 + x, color);
-		}
-		if (cornername & 0x2) {
-			drawPixel_cont(x0 + x, y0 - y, color);
-			drawPixel_cont(x0 + y, y0 - x, color);
-		}
-		if (cornername & 0x8) {
-			drawPixel_cont(x0 - y, y0 + x, color);
-			drawPixel_cont(x0 - x, y0 + y, color);
-		}
-		if (cornername & 0x1) {
-			drawPixel_cont(x0 - y, y0 - x, color);
-			drawPixel_cont(x0 - x, y0 - y, color);
-		}
-	}
-	disableCS();
-}
-
-void ILI9341_due::fillCircle(int16_t x0, int16_t y0, int16_t r,
-	uint16_t color)
-{
-	drawFastVLine(x0, y0 - r, 2 * r + 1, color);
-	fillCircleHelper(x0, y0, r, 3, 0, color);
-}
-
-// Used to do circles and roundrects
-void ILI9341_due::fillCircleHelper(int16_t x0, int16_t y0, int16_t r,
-	uint8_t cornername, int16_t delta, uint16_t color)
-{
-
-	int16_t f = 1 - r;
-	int16_t ddF_x = 1;
-	int16_t ddF_y = -2 * r;
-	int16_t x = 0;
-	int16_t y = r;
-
-#if SPI_MODE_DMA
-	fillScanline(color, 2 * max(x, y) + 1 + delta);
-#endif
-	enableCS();
-	while (x < y) {
-		if (f >= 0) {
-			y--;
-			ddF_y += 2;
-			f += ddF_y;
-		}
-		x++;
-		ddF_x += 2;
-		f += ddF_x;
-
-		if (cornername & 0x1) {
-			drawFastVLine_cont_noFill(x0 + x, y0 - y, 2 * y + 1 + delta, color);
-			drawFastVLine_cont_noFill(x0 + y, y0 - x, 2 * x + 1 + delta, color);
-		}
-		if (cornername & 0x2) {
-			drawFastVLine_cont_noFill(x0 - x, y0 - y, 2 * y + 1 + delta, color);
-			drawFastVLine_cont_noFill(x0 - y, y0 - x, 2 * x + 1 + delta, color);
-		}
-	}
-	disableCS();
-}
-
-// Bresenham's algorithm - thx wikpedia
-void ILI9341_due::drawLine(int16_t x0, int16_t y0,
-	int16_t x1, int16_t y1, uint16_t color)
-{
-	if (y0 == y1) {
-		if (x1 > x0) {
-			drawFastHLine(x0, y0, x1 - x0 + 1, color);
-		}
-		else if (x1 < x0) {
-			drawFastHLine(x1, y0, x0 - x1 + 1, color);
-		}
-		else {
-			drawPixel(x0, y0, color);
-		}
-		return;
-	}
-	else if (x0 == x1) {
-		if (y1 > y0) {
-			drawFastVLine(x0, y0, y1 - y0 + 1, color);
-		}
-		else {
-			drawFastVLine(x0, y1, y0 - y1 + 1, color);
-		}
-		return;
-	}
-
-	bool steep = abs(y1 - y0) > abs(x1 - x0);
-	if (steep) {
-		swap(x0, y0);
-		swap(x1, y1);
-	}
-	if (x0 > x1) {
-		swap(x0, x1);
-		swap(y0, y1);
-	}
-
-	int16_t dx, dy;
-	dx = x1 - x0;
-	dy = abs(y1 - y0);
-
-	int16_t err = dx / 2;
-	int16_t ystep;
-
-	if (y0 < y1) {
-		ystep = 1;
-	}
-	else {
-		ystep = -1;
-	}
-
-	int16_t xbegin = x0;
-#if SPI_MODE_DMA
-	fillScanline(color);
-#endif
-	enableCS();
-	if (steep) {
-		for (; x0 <= x1; x0++) {
-			err -= dy;
-			if (err < 0) {
-				int16_t len = x0 - xbegin;
-				if (len) {
-					writeVLine_cont_noCS_noFill(y0, xbegin, len + 1, color);
-				}
-				else {
-					writePixel_cont_noCS(y0, x0, color);
-				}
-				xbegin = x0 + 1;
-				y0 += ystep;
-				err += dx;
-			}
-		}
-		if (x0 > xbegin + 1) {
-			writeVLine_cont_noCS_noFill(y0, xbegin, x0 - xbegin, color);
-		}
-
-	}
-	else {
-		for (; x0 <= x1; x0++) {
-			err -= dy;
-			if (err < 0) {
-				int16_t len = x0 - xbegin;
-				if (len) {
-					writeHLine_cont_noCS_noFill(xbegin, y0, len + 1, color);
-				}
-				else {
-					writePixel_cont_noCS(x0, y0, color);
-				}
-				xbegin = x0 + 1;
-				y0 += ystep;
-				err += dx;
-			}
-		}
-		if (x0 > xbegin + 1) {
-			writeHLine_cont_noCS_noFill(xbegin, y0, x0 - xbegin, color);
-		}
-	}
-	disableCS();
-}
-
-
-// Draw a rectangle
-//void ILI9341_due::drawRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color)
-//{
-//	writeHLine_cont(x, y, w, color);
-//	writeHLine_cont(x, y+h-1, w, color);
-//	writeVLine_cont(x, y, h, color);
-//	writeVLine_last(x+w-1, y, h, color);
-//}
-
-void ILI9341_due::drawRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color)
-{
-#if SPI_MODE_DMA
-	fillScanline(color, max(w, h));
-#endif
-	enableCS();
-	writeHLine_cont_noCS_noFill(x, y, w, color);
-	writeHLine_cont_noCS_noFill(x, y + h - 1, w, color);
-	writeVLine_cont_noCS_noFill(x, y, h, color);
-	writeVLine_cont_noCS_noFill(x + w - 1, y, h, color);
-	disableCS();
-}
-
-// Draw a rounded rectangle
-void ILI9341_due::drawRoundRect(int16_t x, int16_t y, int16_t w,
-	int16_t h, int16_t r, uint16_t color)
-{
-        if ( h <= 2 * r || w <= 2 * r) return;
-#if SPI_MODE_DMA
-	fillScanline(color, max(w, h));
-#endif
-	enableCS();
-	// smarter version
-	writeHLine_cont_noCS_noFill(x + r, y, w - 2 * r, color); // Top
-	writeHLine_cont_noCS_noFill(x + r, y + h - 1, w - 2 * r, color); // Bottom
-	writeVLine_cont_noCS_noFill(x, y + r, h - 2 * r, color); // Left
-	writeVLine_cont_noCS_noFill(x + w - 1, y + r, h - 2 * r, color); // Right
-	disableCS();
-	// draw four corners
-	drawCircleHelper(x + r, y + r, r, 1, color);
-	drawCircleHelper(x + w - r - 1, y + r, r, 2, color);
-	drawCircleHelper(x + w - r - 1, y + h - r - 1, r, 4, color);
-	drawCircleHelper(x + r, y + h - r - 1, r, 8, color);
-}
-
-// Fill a rounded rectangle
-void ILI9341_due::fillRoundRect(int16_t x, int16_t y, int16_t w,
-	int16_t h, int16_t r, uint16_t color)
-{
-	// smarter version
-	fillRect(x + r, y, w - 2 * r, h, color);
-
-	// draw four corners
-	fillCircleHelper(x + w - r - 1, y + r, r, 1, h - 2 * r - 1, color);
-	fillCircleHelper(x + r, y + r, r, 2, h - 2 * r - 1, color);
-}
-
-// Draw a triangle
-void ILI9341_due::drawTriangle(int16_t x0, int16_t y0,
-	int16_t x1, int16_t y1,
-	int16_t x2, int16_t y2, uint16_t color)
-{
-	drawLine(x0, y0, x1, y1, color);
-	drawLine(x1, y1, x2, y2, color);
-	drawLine(x2, y2, x0, y0, color);
-}
-
-// Fill a triangle
-void ILI9341_due::fillTriangle(int16_t x0, int16_t y0,
-	int16_t x1, int16_t y1,
-	int16_t x2, int16_t y2, uint16_t color)
-{
-
-	int16_t a, b, y, last;
-
-	// Sort coordinates by Y order (y2 >= y1 >= y0)
-	if (y0 > y1) {
-		swap(y0, y1); swap(x0, x1);
-	}
-	if (y1 > y2) {
-		swap(y2, y1); swap(x2, x1);
-	}
-	if (y0 > y1) {
-		swap(y0, y1); swap(x0, x1);
-	}
-
-	if (y0 == y2) { // Handle awkward all-on-same-line case as its own thing
-		a = b = x0;
-		if (x1 < a)      a = x1;
-		else if (x1 > b) b = x1;
-		if (x2 < a)      a = x2;
-		else if (x2 > b) b = x2;
-		drawFastHLine(a, y0, b - a + 1, color);
-		return;
-	}
-
-	int16_t
-		dx01 = x1 - x0,
-		dy01 = y1 - y0,
-		dx02 = x2 - x0,
-		dy02 = y2 - y0,
-		dx12 = x2 - x1,
-		dy12 = y2 - y1,
-		sa = 0,
-		sb = 0;
-
-	// For upper part of triangle, find scanline crossings for segments
-	// 0-1 and 0-2.  If y1=y2 (flat-bottomed triangle), the scanline y1
-	// is included here (and second loop will be skipped, avoiding a /0
-	// error there), otherwise scanline y1 is skipped here and handled
-	// in the second loop...which also avoids a /0 error here if y0=y1
-	// (flat-topped triangle).
-	if (y1 == y2) last = y1;   // Include y1 scanline
-	else         last = y1 - 1; // Skip it
-
-#if SPI_MODE_DMA
-	fillScanline(color, max(x0, max(x1, x2)) - min(x0, min(x1, x2)));	// fill scanline with the widest scanline that'll be used
-#endif
-	enableCS();
-	for (y = y0; y <= last; y++) {
-		a = x0 + sa / dy01;
-		b = x0 + sb / dy02;
-		sa += dx01;
-		sb += dx02;
-		/* longhand:
-		a = x0 + (x1 - x0) * (y - y0) / (y1 - y0);
-		b = x0 + (x2 - x0) * (y - y0) / (y2 - y0);
-		*/
-		if (a > b) swap(a, b);
-		writeHLine_cont_noCS_noFill(a, y, b - a + 1, color);
-	}
-
-	// For lower part of triangle, find scanline crossings for segments
-	// 0-2 and 1-2.  This loop is skipped if y1=y2.
-	sa = dx12 * (y - y1);
-	sb = dx02 * (y - y0);
-	for (; y <= y2; y++) {
-		a = x1 + sa / dy12;
-		b = x0 + sb / dy02;
-		sa += dx12;
-		sb += dx02;
-		/* longhand:
-		a = x1 + (x2 - x1) * (y - y1) / (y2 - y1);
-		b = x0 + (x2 - x0) * (y - y0) / (y2 - y0);
-		*/
-		if (a > b) swap(a, b);
-		writeHLine_cont_noCS_noFill(a, y, b - a + 1, color);
-	}
-	disableCS();
-}
-
-// draws monochrome (single color) bitmaps
-void ILI9341_due::drawBitmap(int16_t x, int16_t y,
-	const uint8_t *bitmap, int16_t w, int16_t h,
-	uint16_t color)
-{
-
-	int16_t i, j, byteWidth = (w + 7) / 8;
-
-#if SPI_MODE_DMA
-	_hiByte = highByte(color);
-	_loByte = lowByte(color);
-	fillScanline(color, w);
-#endif
-
-	for (j = 0; j < h; j++)
-	{
-		for (i = 0; i < w; i++)
-		{
-			if (pgm_read_byte(bitmap + j * byteWidth + i / 8) & (128 >> (i & 7))) {
-#if SPI_MODE_NORMAL | SPI_MODE_EXTENDED
-				drawPixel(x+i, y+j, color);
-#elif SPI_MODE_DMA
-				_scanlineBuffer[i << 1] = _hiByte;
-				_scanlineBuffer[(i << 1) + 1] = _loByte;
-#endif
-			}
-		}
-#if SPI_MODE_DMA
-		setAddrAndRW_cont(x + i, y + j, x + w - 1, y + j);
-		writeScanline_cont(w);
-#endif
-	}
-	disableCS();
-}
-
-#ifdef FEATURE_PRINT_ENABLED
-size_t ILI9341_due::write(uint8_t c) {
-	if (c == '\n') {
-		_cursorY += _textsize * 8;
-		_cursorX = 0;
-	}
-	else if (c == '\r') {
-		// skip em
-	}
-	else {
-		drawChar(_cursorX, _cursorY, c, _textcolor, _textbgcolor, _textsize);
-		_cursorX += _textsize * 6;
-		if (_wrap && (_cursorX > (_width - _textsize * 6))) {
-			_cursorY += _textsize * 8;
-			_cursorX = 0;
-		}
-	}
-	return 1;
-}
-
-// Draw a character
-void ILI9341_due::drawChar(int16_t x, int16_t y, unsigned char c,
-	uint16_t fgcolor, uint16_t bgcolor, uint8_t size)
-{
-	if ((x >= _width) || // Clip right
-		(y >= _height) || // Clip bottom
-		((x + 6 * size - 1) < 0) || // Clip left  TODO: is this correct?
-		((y + 8 * size - 1) < 0))   // Clip top   TODO: is this correct?
-		return;
-
-	enableCS();
-
-	if (fgcolor == bgcolor)
-	{
-		// This transparent approach is only about 20% faster	
-		if (size == 1)
-		{
-			uint8_t mask = 0x01;
-			int16_t xoff, yoff;
-#if SPI_MODE_DMA
-			fillScanline(fgcolor, 5);
-#endif
-			for (yoff = 0; yoff < 8; yoff++) {
-				uint8_t line = 0;
-				for (xoff = 0; xoff < 5; xoff++) {
-					if (font[c * 5 + xoff] & mask) line |= 1;
-					line <<= 1;
-				}
-				line >>= 1;
-				xoff = 0;
-				while (line) {
-					if (line == 0x1F) {
-						writeHLine_cont_noCS_noFill(x + xoff, y + yoff, 5, fgcolor);
-						break;
-					}
-					else if (line == 0x1E) {
-						writeHLine_cont_noCS_noFill(x + xoff, y + yoff, 4, fgcolor);
-						break;
-					}
-					else if ((line & 0x1C) == 0x1C) {
-						writeHLine_cont_noCS_noFill(x + xoff, y + yoff, 3, fgcolor);
-						line <<= 4;
-						xoff += 4;
-					}
-					else if ((line & 0x18) == 0x18) {
-						writeHLine_cont_noCS_noFill(x + xoff, y + yoff, 2, fgcolor);
-						line <<= 3;
-						xoff += 3;
-					}
-					else if ((line & 0x10) == 0x10) {
-						writePixel_cont_noCS(x + xoff, y + yoff, fgcolor);
-						line <<= 2;
-						xoff += 2;
-					}
-					else {
-						line <<= 1;
-						xoff += 1;
-					}
-				}
-				mask = mask << 1;
-			}
-		}
-		else {
-			uint8_t mask = 0x01;
-			int16_t xoff, yoff;
-			for (yoff = 0; yoff < 8; yoff++) {
-				uint8_t line = 0;
-				for (xoff = 0; xoff < 5; xoff++) {
-					if (font[c * 5 + xoff] & mask) line |= 1;
-					line <<= 1;
-				}
-				line >>= 1;
-				xoff = 0;
-				while (line) {
-					if (line == 0x1F) {
-						fillRect(x + xoff * size, y + yoff * size,
-							5 * size, size, fgcolor);
-						break;
-					}
-					else if (line == 0x1E) {
-						fillRect(x + xoff * size, y + yoff * size,
-							4 * size, size, fgcolor);
-						break;
-					}
-					else if ((line & 0x1C) == 0x1C) {
-						fillRect(x + xoff * size, y + yoff * size,
-							3 * size, size, fgcolor);
-						line <<= 4;
-						xoff += 4;
-					}
-					else if ((line & 0x18) == 0x18) {
-						fillRect(x + xoff * size, y + yoff * size,
-							2 * size, size, fgcolor);
-						line <<= 3;
-						xoff += 3;
-					}
-					else if ((line & 0x10) == 0x10) {
-						fillRect(x + xoff * size, y + yoff * size,
-							size, size, fgcolor);
-						line <<= 2;
-						xoff += 2;
-					}
-					else {
-						line <<= 1;
-						xoff += 1;
-					}
-				}
-				mask = mask << 1;
-			}
-		}
-	}
-	else {
-		// This solid background approach is about 5 time faster
-		setAddrAndRW_cont(x, y, x + 6 * size - 1, y + 8 * size);
-		setDCForData();
-		uint8_t xr, yr;
-		uint8_t mask = 0x01;
-		uint16_t color;
-		uint16_t scanlineId = 0;
-		// for each pixel row
-		for (y = 0; y < 8; y++)
-		{
-			//scanlineId = 0;
-			for (yr = 0; yr < size; yr++)
-			{
-				scanlineId = 0;
-				// draw 5px horizontal "bitmap" line
-				for (x = 0; x < 5; x++) {
-					if (font[c * 5 + x] & mask) {
-						color = fgcolor;
-					}
-					else {
-						color = bgcolor;
-					}
-					for (xr = 0; xr < size; xr++) {
-#if SPI_MODE_NORMAL | SPI_MODE_EXTENDED
-						write16_cont(color);
-#elif SPI_MODE_DMA
-						_scanlineBuffer[scanlineId++] = highByte(color);
-						_scanlineBuffer[scanlineId++] = lowByte(color);
-#endif	
-					}
-				}
-				// draw a gap between chars (1px for size of 1)
-				for (xr = 0; xr < size; xr++) {
-#if SPI_MODE_NORMAL | SPI_MODE_EXTENDED
-					write16_cont(bgcolor);
-#elif SPI_MODE_DMA
-					_scanlineBuffer[scanlineId++] = highByte(bgcolor);
-					_scanlineBuffer[scanlineId++] = lowByte(bgcolor);
-#endif	
-				}
-#if SPI_MODE_DMA
-				writeScanline_cont(scanlineId - 1);
-#endif	
-			}
-			mask = mask << 1;
-		}
-		// draw an empty line below a character
-#if SPI_MODE_NORMAL | SPI_MODE_EXTENDED
-		uint32_t n = 6 * size * size;
-		do {
-			write16_cont(bgcolor);
-			n--;
-		} while (n > 0);
-#elif SPI_MODE_DMA
-		fillScanline(bgcolor, 6 * size);
-		for (y = 0; y < size; y++)
-		{
-			writeScanline_cont(6 * size);
-		}
-#endif	
-	}
-	disableCS();
-}
-
-void ILI9341_due::setCursor(int16_t x, int16_t y) {
-	_cursorX = x;
-	_cursorY = y;
-}
-
-void ILI9341_due::setTextSize(uint8_t s) {
-	_textsize = (s > 0) ? s : 1;
-}
-
-void ILI9341_due::setTextColor(uint16_t c) {
-	// For 'transparent' background, we'll set the bg 
-	// to the same as fg instead of using a flag
-	_textcolor = _textbgcolor = c;
-}
-
-void ILI9341_due::setTextColor(uint16_t c, uint16_t b) {
-	_textcolor = c;
-	_textbgcolor = b;
-}
-
-void ILI9341_due::setTextWrap(boolean w) {
-	_wrap = w;
-}
-#endif
-
-uint8_t ILI9341_due::getRotation(void) {
-	return _rotation;
-}
-
-// if true, tft will be blank (white), 
-// display's frame buffer is unaffected
-// (you can write to it without showing content on the screen)
-void ILI9341_due::display(boolean d){
-	writecommand_last(d ? ILI9341_DISPON : ILI9341_DISPOFF);
-}
-
-// puts display in/out of sleep mode
-void ILI9341_due::sleep(boolean s)
-{
-	writecommand_last(s ? ILI9341_SLPIN : ILI9341_SLPOUT);
-	delay(120);
-}
-
-void ILI9341_due::idle(boolean i){
-	writecommand_last(i ? ILI9341_IDMON : ILI9341_IDMOFF);
-}
-
-
-void ILI9341_due::setPowerLevel(pwrLevel p)
-{
-	switch (p)
-	{
-	case PWRLEVEL_NORMAL:
-		if (_isIdle) { idle(false); _isIdle = false; }
-		if (_isInSleep) { sleep(false); _isInSleep = false; }
-		break;
-	case PWRLEVEL_IDLE:
-		if (!_isIdle) { idle(true); _isIdle = true; }
-		if (_isInSleep) { sleep(false); _isInSleep = false; }
-		break;
-	case PWRLEVEL_SLEEP:
-		if (!_isInSleep) { sleep(true); _isInSleep = true; }
-		if (_isIdle) { idle(false); _isIdle = false; }
-		break;
-	}
-}
-
-#ifdef FEATURE_ARC_ENABLED
-void ILI9341_due::setArcParams(float arcAngleMax, int arcAngleOffset)
-{
-	_arcAngleMax = arcAngleMax;
-	_arcAngleOffset = arcAngleOffset;
-}
-#endif
-
-//uint8_t ILI9341_due::spiread(void) {
-//	uint8_t r = 0;
-//
-//	//SPI.setClockDivider(_cs, 12); // 8-ish MHz (full! speed!)
-//	//SPI.setBitOrder(_cs, MSBFIRST);
-//	//SPI.setDataMode(_cs, SPI_MODE0);
-//	r = SPI.transfer(_cs, 0x00);
-//	Serial.print("read: 0x"); Serial.print(r, HEX);
-//
-//	return r;
-//}
-//
-//void ILI9341_due::spiwrite(uint8_t c) {
-//
-//	//Serial.print("0x"); Serial.print(c, HEX); Serial.print(", ");
-//
-//
-//	//SPI.setClockDivider(_cs, 12); // 8-ish MHz (full! speed!)
-//	//SPI.setBitOrder(_cs, MSBFIRST);
-//	//SPI.setDataMode(_cs, SPI_MODE0);
-//	SPI.transfer(_cs, c);
-//
-//}
-
-//void ILI9341_due::writecommand(uint8_t c) {
-//	//*dcport &=  ~dcpinmask;
-//	digitalWrite(_dc, LOW);
-//	//*clkport &= ~clkpinmask; // clkport is a NULL pointer when hwSPI==true
-//	//digitalWrite(_sclk, LOW);
-//	//*csport &= ~cspinmask;
-//	//digitalWrite(_cs, LOW);
-//
-//	spiwrite(c);
-//
-//	//*csport |= cspinmask;
-//	//digitalWrite(_cs, HIGH);
-//}
-//
-//
-//void ILI9341_due::writedata(uint8_t c) {
-//	//*dcport |=  dcpinmask;
-//	digitalWrite(_dc, HIGH);
-//	//*clkport &= ~clkpinmask; // clkport is a NULL pointer when hwSPI==true
-//	//digitalWrite(_sclk, LOW);
-//	//*csport &= ~cspinmask;
-//	//digitalWrite(_cs, LOW);
-//
-//	spiwrite(c);
-//
-//	//digitalWrite(_cs, HIGH);
-//	//*csport |= cspinmask;
-//} 
-
-void ILI9341_due::printHex8(uint8_t *data, uint8_t length) // prints 8-bit data in hex
-{
-	char tmp[length * 2 + 1];
-	byte first;
-	byte second;
-	for (int i = 0; i < length; i++) {
-		first = (data[i] >> 4) & 0x0f;
-		second = data[i] & 0x0f;
-		// base for converting single digit numbers to ASCII is 48
-		// base for 10-16 to become upper-case characters A-F is 55
-		// note: difference is 7
-		tmp[i * 2] = first + 48;
-		tmp[i * 2 + 1] = second + 48;
-		if (first > 9) tmp[i * 2] += 7;
-		if (second > 9) tmp[i * 2 + 1] += 7;
-	}
-	tmp[length * 2] = 0;
-	Serial.print(tmp);
-}
-
-
-void ILI9341_due::printHex16(uint16_t *data, uint8_t length) // prints 8-bit data in hex
-{
-	char tmp[length * 4 + 1];
-	byte first;
-	byte second;
-	byte third;
-	byte fourth;
-	for (int i = 0; i < length; i++) {
-		first = (data[i] >> 12) & 0x0f;
-		second = (data[i] >> 8) & 0x0f;
-		third = (data[i] >> 4) & 0x0f;
-		fourth = data[i] & 0x0f;
-		//Serial << first << " " << second << " " << third << " " << fourth << endl;
-		// base for converting single digit numbers to ASCII is 48
-		// base for 10-16 to become upper-case characters A-F is 55
-		// note: difference is 7
-		tmp[i * 4] = first + 48;
-		tmp[i * 4 + 1] = second + 48;
-		tmp[i * 4 + 2] = third + 48;
-		tmp[i * 4 + 3] = fourth + 48;
-		//tmp[i*5+4] = 32; // add trailing space
-		if (first > 9) tmp[i * 4] += 7;
-		if (second > 9) tmp[i * 4 + 1] += 7;
-		if (third > 9) tmp[i * 4 + 2] += 7;
-		if (fourth > 9) tmp[i * 4 + 3] += 7;
-	}
-	tmp[length * 4] = 0;
-	Serial.print(tmp);
-}
-
-void ILI9341_due::printHex32(uint32_t *data, uint8_t length) // prints 8-bit data in hex
-{
-	char tmp[length * 8 + 1];
-	byte dataByte[8];
-	for (int i = 0; i < length; i++) {
-		dataByte[0] = (data[i] >> 28) & 0x0f;
-		dataByte[1] = (data[i] >> 24) & 0x0f;
-		dataByte[2] = (data[i] >> 20) & 0x0f;
-		dataByte[3] = (data[i] >> 16) & 0x0f;
-		dataByte[4] = (data[i] >> 12) & 0x0f;
-		dataByte[5] = (data[i] >> 8) & 0x0f;
-		dataByte[6] = (data[i] >> 4) & 0x0f;
-		dataByte[7] = data[i] & 0x0f;
-		//Serial << first << " " << second << " " << third << " " << fourth << endl;
-		// base for converting single digit numbers to ASCII is 48
-		// base for 10-16 to become upper-case characters A-F is 55
-		// note: difference is 7
-		tmp[i * 4] = dataByte[0] + 48;
-		tmp[i * 4 + 1] = dataByte[1] + 48;
-		tmp[i * 4 + 2] = dataByte[2] + 48;
-		tmp[i * 4 + 3] = dataByte[3] + 48;
-		tmp[i * 4 + 4] = dataByte[4] + 48;
-		tmp[i * 4 + 5] = dataByte[5] + 48;
-		tmp[i * 4 + 6] = dataByte[6] + 48;
-		tmp[i * 4 + 7] = dataByte[7] + 48;
-		//tmp[i*5+4] = 32; // add trailing space
-		if (dataByte[0] > 9) tmp[i * 4] += 7;
-		if (dataByte[1] > 9) tmp[i * 4 + 1] += 7;
-		if (dataByte[2] > 9) tmp[i * 4 + 2] += 7;
-		if (dataByte[3] > 9) tmp[i * 4 + 3] += 7;
-		if (dataByte[4] > 9) tmp[i * 4 + 4] += 7;
-		if (dataByte[5] > 9) tmp[i * 4 + 5] += 7;
-		if (dataByte[6] > 9) tmp[i * 4 + 6] += 7;
-		if (dataByte[7] > 9) tmp[i * 4 + 7] += 7;
-	}
-	tmp[length * 8] = 0;
-	Serial.print(tmp);
-}
diff --git a/STM32F1/libraries/ILI9341_due_STM/ILI9341_due.h b/STM32F1/libraries/ILI9341_due_STM/ILI9341_due.h
deleted file mode 100644
index f06dd7153..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/ILI9341_due.h
+++ /dev/null
@@ -1,1171 +0,0 @@
-/*
-v0.94.000
-
-ILI9341_due_.h - Arduino Due library for interfacing with ILI9341-based TFTs
-
-Copyright (c) 2014  Marek Buriak
-
-2.4 TFT Pin-out
-T_IRQ T_DO T_DIN T_CS T_CLK MISO LED CLK MOSI DC RESET CS GND VCC
-
-This library is based on ILI9341_t3 library from Paul Stoffregen
-(https://github.com/PaulStoffregen/ILI9341_t3), Adafruit_ILI9341
-and Adafruit_GFX libraries from Limor Fried/Ladyada
-(https://github.com/adafruit/Adafruit_ILI9341).
-
-This file is part of the Arduino ILI9341_due library.
-Sources for this library can be found at https://github.com/marekburiak/ILI9341_Due.
-
-ILI9341_due is free software: you can redistribute it and/or modify
-it under the terms of the GNU Lesser General Public License as published by
-the Free Software Foundation, either version 2.1 of the License, or
-(at your option) any later version.
-
-ILI9341_due is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU Lesser General Public License for more details.
-
-You should have received a copy of the GNU Lesser General Public License
-along with ILI9341_due.  If not, see <http://www.gnu.org/licenses/>.
-
-*/
-
-/***************************************************
-This is our library for the Adafruit ILI9341 Breakout and Shield
-----> http://www.adafruit.com/products/1651
-
-Check out the links above for our tutorials and wiring diagrams
-These displays use SPI to communicate, 4 or 5 pins are required to
-interface (RST is optional)
-Adafruit invests time and resources providing this open source code,
-please support Adafruit and open-source hardware by purchasing
-products from Adafruit!
-
-Written by Limor Fried/Ladyada for Adafruit Industries.
-MIT license, all text above must be included in any redistribution
-****************************************************/
-
-#ifndef _ILI9341_dueH_
-#define _ILI9341_dueH_
-
-#if defined (__STM32F1__)
- #include <avr/pgmspace.h>
- #include <limits.h>
- #include <libmaple/dma.h>
-// #include "pins_arduino.h"
- #include "wiring_private.h"
- #include <SPI.h>
-#endif
-
-//#include "../Streaming/Streaming.h"
-
-// USER CONFIG SECTION START
-
-// comment out the SPI mode you want to use (does not matter for AVR)
-//#define ILI9341_SPI_MODE_NORMAL	// uses SPI library
-//#define ILI9341_SPI_MODE_EXTENDED	// uses Extended SPI in Due, make sure you use pin 4, 10 or 52 for CS
-#define ILI9341_SPI_MODE_DMA		// uses DMA in Due
-
-// set the clock divider
-#ifdef __SAM3X8E__
-#define ILI9341_SPI_CLKDIVIDER 2	// for Due
-#else
-#define ILI9341_SPI_CLKDIVIDER SPI_CLOCK_DIV2	// for Uno, Mega,...
-#endif
-
-// comment out the features you do not need to save flash memory and RAM (especially on AVR)
-
-// commenting out/disabling the ARC feature will exclude the drawArc function. It is going to save a few ROM bytes.
-#define FEATURE_ARC_ENABLED
-// commenting out/disabling the PRINT feature will exclude the drawChars and print functions, it saves around 3.6kB ROM and 1.3kB RAM(!)
-// I recommend using gText for drawing the text.
-#define FEATURE_PRINT_ENABLED
-
-// number representing the maximum angle (e.g. if 100, then if you pass in start=0 and end=50, you get a half circle)
-// this can be changed with setArcParams function at runtime
-#define ARC_ANGLE_MAX 360
-// rotational offset in degrees defining position of value 0 (-90 will put it at the top of circle)
-// this can be changed with setArcParams function at runtime
-#define ARC_ANGLE_OFFSET -90
-
-// USER CONFIG SECTION END
-
-#ifdef __AVR__
-#define SPI_MODE_NORMAL 1
-#define SPI_MODE_EXTENDED 0
-#define SPI_MODE_DMA 0
-#else
-#ifndef ILI9341_SPI_MODE_NORMAL
-#define SPI_MODE_NORMAL 0
-#else
-#define SPI_MODE_NORMAL 1
-#endif
-
-#ifndef ILI9341_SPI_MODE_EXTENDED
-#define SPI_MODE_EXTENDED 0
-#else
-#define SPI_MODE_EXTENDED 1
-#endif
-
-#ifndef ILI9341_SPI_MODE_DMA
-#define SPI_MODE_DMA 0
-#else
-#define SPI_MODE_DMA 1
-#endif
-#endif
-
-#include "Arduino.h"
-#if SPI_MODE_NORMAL | SPI_MODE_EXTENDED
-#include <SPI.h>
-#elif SPI_MODE_DMA
-#include "ILI_SdSpi.h"
-#include <SPI.h>
-#endif
-
-#ifdef __AVR__
-#include <avr/pgmspace.h>
-#endif
-
-#define ILI9341_TFTWIDTH  240
-#define ILI9341_TFTHEIGHT 320
-
-#define ILI9341_NOP     0x00
-#define ILI9341_SWRESET 0x01
-#define ILI9341_RDDID   0x04
-#define ILI9341_RDDST   0x09
-
-#define ILI9341_SLPIN   0x10
-#define ILI9341_SLPOUT  0x11
-#define ILI9341_PTLON   0x12
-#define ILI9341_NORON   0x13
-
-#define ILI9341_RDMODE  0x0A
-#define ILI9341_RDMADCTL  0x0B
-#define ILI9341_RDPIXFMT  0x0C
-#define ILI9341_RDIMGFMT  0x0A
-#define ILI9341_RDSELFDIAG  0x0F
-
-#define ILI9341_INVOFF  0x20
-#define ILI9341_INVON   0x21
-#define ILI9341_GAMMASET 0x26
-#define ILI9341_DISPOFF 0x28
-#define ILI9341_DISPON  0x29
-
-#define ILI9341_CASET   0x2A
-#define ILI9341_PASET   0x2B
-#define ILI9341_RAMWR   0x2C
-#define ILI9341_RAMRD   0x2E
-
-#define ILI9341_PTLAR   0x30
-#define ILI9341_MADCTL  0x36
-#define ILI9341_IDMOFF  0x38
-#define ILI9341_IDMON   0x39
-#define ILI9341_PIXFMT  0x3A
-
-#define ILI9341_FRMCTR1 0xB1
-#define ILI9341_FRMCTR2 0xB2
-#define ILI9341_FRMCTR3 0xB3
-#define ILI9341_INVCTR  0xB4
-#define ILI9341_DFUNCTR 0xB6
-
-#define ILI9341_PWCTR1  0xC0
-#define ILI9341_PWCTR2  0xC1
-#define ILI9341_PWCTR3  0xC2
-#define ILI9341_PWCTR4  0xC3
-#define ILI9341_PWCTR5  0xC4
-#define ILI9341_VMCTR1  0xC5
-#define ILI9341_VMCTR2  0xC7
-
-#define ILI9341_RDID1   0xDA
-#define ILI9341_RDID2   0xDB
-#define ILI9341_RDID3   0xDC
-#define ILI9341_RDID4   0xDD
-
-#define ILI9341_GMCTRP1 0xE0
-#define ILI9341_GMCTRN1 0xE1
-/*
-#define ILI9341_PWCTR6  0xFC
-
-*/
-
-// Color definitions
-#define	ILI9341_BLACK   0x0000
-#define	ILI9341_BLUE    0x001F
-#define	ILI9341_RED     0xF800
-#define	ILI9341_GREEN   0x07E0
-#define ILI9341_CYAN    0x07FF
-#define ILI9341_MAGENTA 0xF81F
-#define ILI9341_YELLOW  0xFFE0
-#define ILI9341_WHITE   0xFFFF
-
-typedef uint8_t pwrLevel;
-typedef enum {
-  iliRotation0 = 0,
-  iliRotation90 = 1,
-  iliRotation180 = 2,
-  iliRotation270 = 3
-} iliRotation;
-
-// Normal Mode On (full display), Idle Mode Off, Sleep Out.
-// In this mode, the display is able to show maximum 262,144 colors.
-#define PWRLEVEL_NORMAL 1
-
-// Normal Mode On (full display), Idle Mode On, Sleep Out.
-// In this mode, the full display area is used but with 8 colors.
-#define PWRLEVEL_IDLE 2
-
-//In this mode, the DC : DC converter, Internal oscillator and panel driver circuit are stopped. Only the MCU
-// interface and memory works with VDDI power supply. Contents of the memory are safe.
-#define PWRLEVEL_SLEEP 3
-
-#define SCANLINE_BUFFER_SIZE 640 // 320 2-byte pixels
-
-class ILI9341_due
-#ifdef FEATURE_PRINT_ENABLED
-  : public Print
-#endif
-{
-  public:
-    ILI9341_due(uint8_t cs, uint8_t dc, uint8_t rst = 255);
-#if SPI_MODE_DMA
-    ILI_SdSpi _dmaSpi;
-    uint8_t _scanlineBuffer[SCANLINE_BUFFER_SIZE];
-    uint8_t _hiByte, _loByte;
-
-#endif
-    bool _isIdle, _isInSleep;
-
-    bool begin(void);
-    void pushColor(uint16_t color);
-    void pushColors(uint16_t *colors, uint16_t offset, uint16_t len);
-    void pushColors565(uint8_t *colors, uint16_t offset, uint16_t len);
-    void fillScreen(uint16_t color);
-    void drawPixel(int16_t x, int16_t y, uint16_t color);
-    void drawPixel_cont(int16_t x, int16_t y, uint16_t color);
-    void drawFastVLine(int16_t x, int16_t y, int16_t h, uint16_t color);
-    void drawFastHLine(int16_t x, int16_t y, int16_t w, uint16_t color);
-    void drawRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color);
-    void fillRect(int16_t x, int16_t y, int16_t w, int16_t h, uint16_t color);
-    void setRotation(iliRotation r);
-    void invertDisplay(boolean i);
-    void display(boolean d);
-    void normalModeOn();
-    void sleep(boolean s);
-    void idle(boolean i);
-    void setPowerLevel(pwrLevel p);
-    void setAddrWindow(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1);
-    void setSPIClockDivider(uint8_t divider);
-
-#ifdef FEATURE_ARC_ENABLED
-    void setArcParams(float arcAngleMax, int arcAngleOffset);
-#endif
-    // Pass 8-bit (each) R,G,B, get back 16-bit packed color
-    static uint16_t color565(uint8_t r, uint8_t g, uint8_t b) {
-      return ((r & 0xF8) << 8) | ((g & 0xFC) << 3) | (b >> 3);
-    }
-
-    //uint8_t readdata(void);
-    uint8_t readcommand8(uint8_t reg, uint8_t index = 0);
-
-    // KJE Added functions to read pixel data...
-    uint16_t readPixel(int16_t x, int16_t y);
-
-
-    // from Adafruit_GFX.h
-    void drawCircle(int16_t x0, int16_t y0, int16_t r, uint16_t color);
-    void drawCircleHelper(int16_t x0, int16_t y0, int16_t r, uint8_t cornername, uint16_t color);
-    void fillCircle(int16_t x0, int16_t y0, int16_t r, uint16_t color);
-    void fillCircleHelper(int16_t x0, int16_t y0, int16_t r, uint8_t cornername, int16_t delta, uint16_t color);
-    void drawTriangle(int16_t x0, int16_t y0, int16_t x1, int16_t y1, int16_t x2, int16_t y2, uint16_t color);
-    void fillTriangle(int16_t x0, int16_t y0, int16_t x1, int16_t y1, int16_t x2, int16_t y2, uint16_t color);
-    void drawRoundRect(int16_t x0, int16_t y0, int16_t w, int16_t h, int16_t radius, uint16_t color);
-    void fillRoundRect(int16_t x0, int16_t y0, int16_t w, int16_t h, int16_t radius, uint16_t color);
-    void drawBitmap(int16_t x, int16_t y, const uint8_t *bitmap, int16_t w, int16_t h, uint16_t color);
-
-#ifdef FEATURE_PRINT_ENABLED
-    void drawChar(int16_t x, int16_t y, unsigned char c, uint16_t color, uint16_t bg, uint8_t size);
-    void setCursor(int16_t x, int16_t y);
-    void setTextColor(uint16_t c);
-    void setTextColor(uint16_t c, uint16_t bg);
-    void setTextSize(uint8_t s);
-    void setTextWrap(boolean w);
-    virtual size_t write(uint8_t);
-#endif
-    int16_t width(void)  {
-      return _width;
-    }
-    int16_t height(void) {
-      return _height;
-    }
-    uint8_t getRotation(void);
-    void drawLine(int16_t x0, int16_t y0, int16_t x1, int16_t y1, uint16_t color);
-    void screenshotToConsole();
-    void printHex8(uint8_t *data, uint8_t length);
-    void printHex16(uint16_t *data, uint8_t length);
-    void printHex32(uint32_t *data, uint8_t length);
-
-#ifdef FEATURE_ARC_ENABLED
-    inline __attribute__((always_inline))
-    void drawArc(uint16_t cx, uint16_t cy, uint16_t radius, uint16_t thickness, float start, float end, uint16_t color)
-    {
-      if (start == 0 && end == _arcAngleMax)
-        drawArcOffsetted(cx, cy, radius, thickness, 0, _arcAngleMax, color);
-      else
-        drawArcOffsetted(cx, cy, radius, thickness, start + (_arcAngleOffset / (float)360)*_arcAngleMax, end + (_arcAngleOffset / (float)360)*_arcAngleMax, color);
-    }
-
-    //int32_t cos_lookup(int32_t angle)
-    //{
-    //	float radians = (float)angle/_arcAngleMax * 2 * PI;
-    //	//Serial << "COS_LOOKUP angle:" << (float)angle << " radians:" << radians << " cos:" << cos(radians) << " return: " << cos(radians) * (double)65535 << endl;
-    //	return (cos(radians) * _arcAngleMax);
-    //}
-
-    //int32_t sin_lookup(int32_t angle)
-    //{
-    //	float radians = (float)angle/_arcAngleMax * 2 * PI;
-    //	//Serial << "SIN_LOOKUP angle:" << (float)angle << " radians:" << radians << " sin:" << sin(radians) << " return: " << sin(radians) * (double)65535 << endl;
-    //	return (sin(radians) * _arcAngleMax);
-    //}
-
-
-    float cosDegrees(float angle)
-    {
-      float radians = angle / (float)360 * 2 * PI;
-      //Serial << "COS_LOOKUP angle:" << (float)angle << " radians:" << radians << " cos:" << cos(radians) << " return: " << cos(radians) * (double)65535 << endl;
-      return cos(radians);
-    }
-
-    float sinDegrees(float angle)
-    {
-      float radians = angle / (float)360 * 2 * PI;
-      //Serial << "SIN_LOOKUP angle:" << (float)angle << " radians:" << radians << " sin:" << sin(radians) << " return: " << sin(radians) * (double)65535 << endl;
-      return sin(radians);
-    }
-#endif
-
-    inline __attribute__((always_inline))
-    void spiwrite(uint8_t c) {
-#if defined __AVR__
-      SPDR = c;
-      asm volatile("nop");
-      while (!(SPSR & _BV(SPIF))); // wait
-#elif defined __SAM3X8E__ |  __STM32F1__
-
-#if SPI_MODE_NORMAL
-      SPI.transfer(c);
-#endif
-#endif
-    }
-
-    inline __attribute__((always_inline))
-    void spiwrite16(uint16_t d) {
-#if defined __AVR__
-      SPDR = highByte(d);
-      while (!(SPSR & _BV(SPIF)));
-      SPDR = lowByte(d);
-      while (!(SPSR & _BV(SPIF)));
-#elif defined __SAM3X8E__ |  __STM32F1__
-#if SPI_MODE_NORMAL
-      SPI.transfer(highByte(d));
-      SPI.transfer(lowByte(d));
-#endif
-#endif
-    }
-
-    // writes 1 byte
-    // CS and DC have to be set prior to calling this method
-    inline __attribute__((always_inline))
-    void write8_cont(uint8_t c) {
-#if SPI_MODE_NORMAL
-      spiwrite(c);
-#elif SPI_MODE_EXTENDED
-      SPI.transfer(_cs, c, SPI_CONTINUE);
-#elif SPI_MODE_DMA
-      SPI.write(c);
-//      _dmaSpi.send(c);
-#endif
-    }
-
-    // writes 1 byte and disables CS
-    // CS and DC have to be set prior to calling this method
-    inline __attribute__((always_inline))
-    void write8_last(uint8_t c) {
-#if SPI_MODE_NORMAL
-      spiwrite(c);
-      disableCS();
-#elif SPI_MODE_EXTENDED
-      SPI.transfer(_cs, c, SPI_LAST);
-#elif SPI_MODE_DMA
-      SPI.write(c);
-//      _dmaSpi.send(c);
-      disableCS();
-#endif
-    }
-
-    // Writes 2 bytes
-    // CS, DC have to be set prior to calling this method
-    inline __attribute__((always_inline))
-    void write16_cont(uint16_t d) {
-#if SPI_MODE_NORMAL
-      spiwrite16(d);
-#elif SPI_MODE_EXTENDED
-      SPI.transfer(_cs, highByte(d), SPI_CONTINUE);
-      SPI.transfer(_cs, lowByte(d), SPI_CONTINUE);
-#elif SPI_MODE_DMA
-      SPI.transfer(highByte(d));
-      SPI.transfer(lowByte(d));
-      
-//      _dmaSpi.send(highByte(d));
-//      _dmaSpi.send(lowByte(d));
-#endif
-    }
-
-    inline __attribute__((always_inline))
-    void write16_last(uint16_t d) {
-#if SPI_MODE_NORMAL
-      spiwrite16(d);
-      disableCS();
-#elif SPI_MODE_EXTENDED
-      SPI.transfer(_cs, highByte(d), SPI_CONTINUE);
-      SPI.transfer(_cs, lowByte(d), SPI_LAST);
-#elif SPI_MODE_DMA
-      SPI.transfer(highByte(d));
-      SPI.transfer(lowByte(d));
-
-//      _dmaSpi.send(highByte(d));
-//      _dmaSpi.send(lowByte(d));
-      disableCS();
-#endif
-    }
-
-    // Writes commands to set the GRAM area where data/pixels will be written
-    void setAddr_cont(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1)
-    __attribute__((always_inline)) {
-      writecommand_cont(ILI9341_CASET); // Column addr set
-      writedata16_cont(x0);   // XSTART
-      writedata16_cont(x1);   // XEND
-      writecommand_cont(ILI9341_PASET); // Row addr set
-      writedata16_cont(y0);   // YSTART
-      writedata16_cont(y1);   // YEND
-    }
-
-    //__attribute__((always_inline))
-    //void setAddrAndRW_cont(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1)
-    //	 {
-    //		writecommand_cont(ILI9341_CASET); // Column addr set
-    //		writedata16_cont(x0);   // XSTART
-    //		writedata16_cont(x1);   // XEND
-    //		writecommand_cont(ILI9341_PASET); // Row addr set
-    //		writedata16_cont(y0);   // YSTART
-    //		writedata16_cont(y1);   // YEND
-    //		writecommand_cont(ILI9341_RAMWR); // write to RAM
-    //}
-
-    // Enables CS, writes commands to set the GRAM area where data/pixels will be written
-    //__attribute__((always_inline))
-    //	void setAddr_cont(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1)
-    //{
-    //	enableCS();
-    //	setDCForCommand();
-    //	write8_cont(ILI9341_CASET); // Column addr set
-    //	setDCForData();
-    //	write16_cont(x0);   // XSTART
-    //	write16_cont(x1);   // XEND
-    //	setDCForCommand();
-    //	write8_cont(ILI9341_PASET); // Row addr set
-    //	setDCForData();
-    //	write16_cont(y0);   // XSTART
-    //	write16_cont(y1);   // XEND
-    //}
-
-    // Enables CS, writes commands to set the GRAM area where data/pixels will be written
-    // Also sends RAM WRITE command which should be followed by writing data/pixels
-#ifdef __SAM3X8E__ |  __STM32F1__
-    inline __attribute__((always_inline))
-#endif
-    void setAddrAndRW_cont(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1)
-    {
-      enableCS();
-      setDCForCommand();
-      write8_cont(ILI9341_CASET); // Column addr set
-      setDCForData();
-      write16_cont(x0);   // XSTART
-      write16_cont(x1);   // XEND
-      setDCForCommand();
-      write8_cont(ILI9341_PASET); // Row addr set
-      setDCForData();
-      write16_cont(y0);   // XSTART
-      write16_cont(y1);   // XEND
-      setDCForCommand();
-      write8_cont(ILI9341_RAMWR); // RAM write
-    }
-
-    // Writes commands to set the GRAM area where data/pixels will be written
-    // Also sends RAM WRITE command which should be followed by writing data/pixels
-    // CS has to be enabled prior to calling this method
-    //__attribute__((always_inline))
-    //	void setAddrAndRW_cont_noCS(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1)
-    //{
-    //	setDCForCommand();
-    //	write8_cont(ILI9341_CASET); // Column addr set
-    //	setDCForData();
-    //	write16_cont(x0);   // XSTART
-    //	write16_cont(x1);   // XEND
-    //	setDCForCommand();
-    //	write8_cont(ILI9341_PASET); // Row addr set
-    //	setDCForData();
-    //	write16_cont(y0);   // XSTART
-    //	write16_cont(y1);   // XEND
-    //	setDCForCommand();
-    //	write8_cont(ILI9341_RAMWR); // Row addr set
-    //}
-
-    // Enables CS, sets DC for Command, writes 1 byte
-    // Does not disable CS
-    //	__attribute__((always_inline))
-    //	void writecommand_cont(uint8_t c) {
-    //		setDCForCommand();
-    //#if SPI_MODE_NORMAL
-    //		enableCS();
-    //		SPI.transfer(c);
-    //#elif SPI_MODE_EXTENDED
-    //		SPI.transfer(_cs, c, SPI_CONTINUE);
-    //#elif SPI_MODE_DMA
-    //		enableCS();
-    //		_dmaSpi.send(c);
-    //#endif
-    //	}
-
-    // Enables CS, sets DC for Command, writes 1 byte
-    // Does not disable CS
-    inline __attribute__((always_inline))
-    void writecommand_cont(uint8_t c) {
-      setDCForCommand();
-#if SPI_MODE_NORMAL | SPI_MODE_DMA
-      enableCS();
-#endif
-      write8_cont(c);
-    }
-
-    // Enables CS, sets DC for Command, writes 1 byte, disables CS
-    inline __attribute__((always_inline))
-    void writecommand_last(uint8_t c) {
-      setDCForCommand();
-#if SPI_MODE_NORMAL | SPI_MODE_DMA
-      enableCS();
-#endif
-      write8_cont(c);
-#if SPI_MODE_NORMAL | SPI_MODE_DMA
-      disableCS();
-#endif
-    }
-
-    // Enables CS, sets DC to Data, writes 1 byte
-    // Does not disable CS
-    inline __attribute__((always_inline))
-    void writedata8_cont(uint8_t c) {
-      setDCForData();
-#if SPI_MODE_NORMAL | SPI_MODE_DMA
-      enableCS();
-#endif
-      write8_cont(c);
-    }
-
-    // Enables CS, sets DC to Data, writes 1 byte, disables CS
-    __attribute__((always_inline))
-    void writedata8_last(uint8_t c) {
-      setDCForData();
-#if SPI_MODE_NORMAL | SPI_MODE_DMA
-      enableCS();
-#endif
-      write8_cont(c);
-#if SPI_MODE_NORMAL | SPI_MODE_DMA
-      disableCS();
-#endif
-    }
-
-    // Enables CS, sets DC to Data, writes 2 bytes
-    // Does not disable CS
-    __attribute__((always_inline))
-    void writedata16_cont(uint16_t d) {
-      setDCForData();
-#if SPI_MODE_NORMAL | SPI_MODE_DMA
-      enableCS();
-#endif
-      write16_cont(d);
-    }
-
-    // Enables CS, sets DC to Data, writes 2 bytes, disables CS
-    __attribute__((always_inline))
-    void writedata16_last(uint16_t d) {
-      setDCForData();
-#if SPI_MODE_NORMAL | SPI_MODE_DMA
-      enableCS();
-#endif
-      write16_last(d);
-    }
-
-#if SPI_MODE_DMA
-    // Enables CS, sets DC and writes n-bytes from the buffer via DMA
-    // Does not disable CS
-    /*inline __attribute__((always_inline))
-    void writedata_cont(const uint8_t* buf , size_t n) {
-    enableCS();
-    setDCForData();
-    _dmaSpi.send(buf, n);
-    }*/
-
-    // Enables CS, sets DC, writes n-bytes from the buffer via DMA, disables CS
-    /*inline __attribute__((always_inline))
-    void writedata_last(const uint8_t* buf , size_t n) {
-    setDCForData();
-    enableCS();
-    _dmaSpi.send(buf, n);
-    disableCS();
-    }*/
-
-    // Writes n-bytes from the buffer via DMA
-    // CS and DC have to be set prior to calling this method
-    inline __attribute__((always_inline))
-    void write_cont(uint8_t* buf, size_t n) {
-      _dmaSpi.send(buf, n);
-    }
-
-    inline __attribute__((always_inline))
-    void read_cont(uint8_t* buf, size_t n) {
-      _dmaSpi.receive(buf, n);
-    }
-
-    // Writes n-bytes from the buffer via DMA and disables CS
-    // DC has to be set prior to calling this method
-    /*inline __attribute__((always_inline))
-    void write_last(const uint8_t* buf , size_t n) {
-    _dmaSpi.send(buf, n << 1);
-    disableCS();
-    }*/
-
-    // Enables CS, sets DC and writes n-bytes from the scanline buffer via DMA
-    // Does not disable CS
-    inline __attribute__((always_inline))
-    void writeScanline_cont(size_t n) {
-      setDCForData();
-      enableCS();
-      _dmaSpi.send(_scanlineBuffer, n << 1);	// each pixel is 2 bytes
-    }
-
-    // writes n-bytes from the scanline buffer via DMA
-    // Does not enable CS nor sets DS nor disables CS
-    //inline __attribute__((always_inline))
-    //	void writeScanline_cont_noCS_noDC(size_t n) {
-    //		_dmaSpi.send(_scanlineBuffer, n << 1);	// each pixel is 2 bytes
-    //}
-
-    // Enables CS, sets DC, writes n-bytes from the scanline buffer via DMA and disabled CS
-    inline __attribute__((always_inline))
-    void writeScanline_last(size_t n) {
-      setDCForData();
-      enableCS();
-      _dmaSpi.send(_scanlineBuffer, n << 1);	// each pixel is 2 bytes
-      disableCS();
-    }
-
-#endif
-
-    // Reads 1 byte
-    __attribute__((always_inline))
-    uint8_t read8_cont()  {
-#if SPI_MODE_NORMAL
-      return SPI.transfer(ILI9341_NOP);
-#elif SPI_MODE_EXTENDED
-      return SPI.transfer(_cs, ILI9341_NOP, SPI_CONTINUE);
-#elif SPI_MODE_DMA
-      return _dmaSpi.receive();
-#endif
-    }
-
-    __attribute__((always_inline))
-    uint8_t read8_last() {
-#if SPI_MODE_NORMAL
-      uint8_t r = SPI.transfer(ILI9341_NOP);
-      disableCS();
-      return r;
-#elif SPI_MODE_EXTENDED
-      return SPI.transfer(_cs, ILI9341_NOP, SPI_LAST);
-#elif SPI_MODE_DMA
-      uint8_t r = _dmaSpi.receive();
-      disableCS();
-      return r;
-#endif
-    }
-
-    // Reads 2 bytes
-    __attribute__((always_inline))
-    uint16_t read16()  {
-#if SPI_MODE_NORMAL
-      uint16_t r = SPI.transfer(ILI9341_NOP);
-      r <<= 8;
-      r |= SPI.transfer(ILI9341_NOP);
-#elif SPI_MODE_EXTENDED
-      uint16_t r = SPI.transfer(_cs, ILI9341_NOP, SPI_CONTINUE);
-      r <<= 8;
-      r |= SPI.transfer(_cs, ILI9341_NOP, SPI_CONTINUE);
-#elif SPI_MODE_DMA
-      uint16_t r = _dmaSpi.receive();
-      r <<= 8;
-      r |= _dmaSpi.receive();
-#endif
-      return r;
-    }
-
-    // Reads 2 bytes
-    __attribute__((always_inline))
-    uint16_t readPixel_start_cont() {
-#if SPI_MODE_NORMAL
-      uint16_t r = SPI.transfer(ILI9341_NOP);
-      r <<= 8;
-      r |= SPI.transfer(ILI9341_NOP);
-#elif SPI_MODE_EXTENDED
-      uint16_t r = SPI.transfer(_cs, ILI9341_NOP, SPI_CONTINUE);
-      r <<= 8;
-      r |= SPI.transfer(_cs, ILI9341_NOP, SPI_CONTINUE);
-#elif SPI_MODE_DMA
-      uint16_t r = _dmaSpi.receive();
-      r <<= 8;
-      r |= _dmaSpi.receive();
-#endif
-      return r;
-    }
-
-    // Enables CS, sets DC for Data and reads 1 byte
-    // Does not disable CS
-    __attribute__((always_inline))
-    uint8_t readdata8_cont() {
-      setDCForData();
-#if SPI_MODE_NORMAL | SPI_MODE_DMA
-      enableCS();
-#endif
-      return read8_cont();
-    }
-
-    // Enables CS, sets DC for Data, reads 1 byte and disables CS
-    __attribute__((always_inline))
-    uint8_t readdata8_last() {
-      setDCForData();
-#if SPI_MODE_NORMAL | SPI_MODE_DMA
-      enableCS();
-#endif
-      return read8_last();
-    }
-
-    // Enables CS, sets DC for Data and reads 2 bytes
-    // Does not disable CS
-    __attribute__((always_inline))
-    uint16_t readdata16_cont() {
-      setDCForData();
-#if SPI_MODE_NORMAL | SPI_MODE_DMA
-      enableCS();
-#endif
-      return read16();
-    }
-
-    // Enables CS, sets DC for Data, reads 2 bytes and disables CS
-    __attribute__((always_inline))
-    uint8_t readdata16_last() {
-      setDCForData();
-#if SPI_MODE_NORMAL | SPI_MODE_DMA
-      enableCS();
-#endif
-      uint16_t r = read16();
-#if SPI_MODE_NORMAL | SPI_MODE_DMA
-      disableCS();
-#endif
-      //TOTRY
-      /*uint8_t buff[2];	// not tested yet
-      enableCS();
-      _dmaSpi.receive(buff, 2);
-      disableCS();
-      uint16_t r = makeWord(buff[1], buff[0]);*/
-
-      return r;
-    }
-
-#if SPI_MODE_DMA
-    //void fillScanline(uint8_t color) __attribute__((always_inline)) {
-    //	//for(uint16_t i=0; i<sizeof(_scanlineBuffer); i++)
-    //	//{
-    //	//	_scanlineBuffer[i] = color;
-    //	//}
-    //	_scanlineBuffer[0]=color;
-    //	memmove(_scanlineBuffer+sizeof(_scanlineBuffer[0]), _scanlineBuffer, sizeof(_scanlineBuffer)-sizeof(_scanlineBuffer[0]));
-    //	//arr[0]=color;
-    //	//memcpy( ((uint8_t*)arr)+sizeof(arr[0]), arr, sizeof(arr)-sizeof(arr[0]) ); // this hack does not seem to work on Due
-    //}
-
-    //void fillScanline(uint8_t color, size_t seedCopyCount) __attribute__((always_inline)) {
-    //	//for(uint16_t i=0; i<seedCopyCount; i++)
-    //	//{
-    //	//	_scanlineBuffer[i] = color;
-    //	//}
-    //	_scanlineBuffer[0]=color;
-    //	memmove(_scanlineBuffer+sizeof(_scanlineBuffer[0]), _scanlineBuffer, seedCopyCount-sizeof(_scanlineBuffer[0]));
-    //	//arr[0]=color;
-    //	//memcpy( ((uint8_t*)arr)+sizeof(arr[0]), arr, seedCopyCount-sizeof(arr[0]) );
-    //}
-
-    // Sets all pixels in the scanline buffer to the specified color
-    __attribute__((always_inline))
-    void fillScanline(uint16_t color) {
-      _hiByte = highByte(color);
-      _loByte = lowByte(color);
-      for (uint16_t i = 0; i < sizeof(_scanlineBuffer); i += 2)
-      {
-        _scanlineBuffer[i] = _hiByte;
-        _scanlineBuffer[i + 1] = _loByte;
-      }
-      /*_scanlineBuffer[0]=highByte(color);
-      _scanlineBuffer[1]=lowByte(color);
-      _scanlineBuffer[2]=_scanlineBuffer[0];
-      _scanlineBuffer[3]=_scanlineBuffer[1];
-
-      memcpy(_scanlineBuffer+4, _scanlineBuffer, 4);
-      memcpy(_scanlineBuffer+8, _scanlineBuffer, 8);
-      memcpy(_scanlineBuffer+16, _scanlineBuffer, 16);
-      memcpy(_scanlineBuffer+32, _scanlineBuffer, 32);
-      memcpy(_scanlineBuffer+64, _scanlineBuffer, 64);
-      memcpy(_scanlineBuffer+128, _scanlineBuffer, 128);
-      memcpy(_scanlineBuffer+256, _scanlineBuffer, 256);
-      memcpy(_scanlineBuffer+512, _scanlineBuffer, 128);*/
-
-      /*for(uint16_t i=0; i<sizeof(_scanlineBuffer); i+=2)
-      {
-      memcpy(_scanlineBuffer+i, _scanlineBuffer, 2);
-      }*/
-
-      //arr[0]=highByte(color);
-      //arr[1]=lowByte(color);
-      //memcpy( ((uint8_t*)arr)+2*sizeof(arr[0]), arr, sizeof(arr)-2*sizeof(arr[0]) );
-    }
-
-    // Sets first n pixels in scanline buffer to the specified color
-    __attribute__((always_inline))
-    void fillScanline(uint16_t color, size_t n) {
-      _hiByte = highByte(color);
-      _loByte = lowByte(color);
-      for (uint16_t i = 0; i < (n << 1); i += 2)
-      {
-        _scanlineBuffer[i] = _hiByte;
-        _scanlineBuffer[i + 1] = _loByte;
-      }
-
-      /*_scanlineBuffer[0]=highByte(color);
-      _scanlineBuffer[1]=lowByte(color);
-      memmove(((uint8_t*)_scanlineBuffer)+2*sizeof(_scanlineBuffer[0]), _scanlineBuffer, (n << 1) -2*sizeof(_scanlineBuffer[0]));
-      */
-    }
-
-    //inline __attribute__((always_inline))
-    //	void *memcpy_forward(uint8_t *dst, const uint8_t *src, size_t n)
-    //{
-    //	uint8_t *pdst;
-    //	const uint8_t *psrc;
-
-    //	for (pdst = dst, psrc = src; n > 0; --n, ++pdst, ++psrc)
-    //		*pdst = *psrc;
-
-    //	return dst;
-    //}
-#endif
-
-    //	// Writes a sequence that will render a horizontal line
-    //	// At the end CS is kept enabled.
-    //	// In case of DMA mode, the content of scanline buffer is written
-    //	__attribute__((always_inline))
-    //		void writeHLine_cont(int16_t x, int16_t y, int16_t w, uint16_t color)
-    //	{
-    //#if SPI_MODE_DMA
-    //		//TOTRY move this down
-    //		fillScanline(color, w);
-    //#endif
-    //		setAddrAndRW_cont(x, y, x+w-1, y);
-    //#if SPI_MODE_NORMAL | SPI_MODE_EXTENDED
-    //		setDCForData();
-    //		do { write16_cont(color); } while (--w > 0);
-    //#elif SPI_MODE_DMA
-    //		writeScanline_cont(w);
-    //#endif
-    //	}
-
-    //	// Writes a sequence that will render a horizontal line
-    //	// At the end CS is disabled.
-    //	// In case of DMA mode, the content of scanline buffer is written
-    //	__attribute__((always_inline))
-    //		void writeHLine_last(int16_t x, int16_t y, int16_t w, uint16_t color)
-    //	{
-    //#if SPI_MODE_DMA
-    //		//TOTRY move this down
-    //		fillScanline(color, w);
-    //#endif
-    //		setAddrAndRW_cont(x, y, x+w-1, y);
-    //#if SPI_MODE_NORMAL | SPI_MODE_EXTENDED
-    //		setDCForData();
-    //		while (w-- > 1) {
-    //			write16_cont(color);
-    //		}
-    //		write16_last(color);
-    //#elif SPI_MODE_DMA
-    //		writeScanline_last(w);
-    //#endif
-    //	}
-
-    //	// Writes a sequence that will render a vertical line
-    //	// At the end CS is kept enabled.
-    //	// In case of DMA mode, the content of scanline buffer is filled and written
-    //	__attribute__((always_inline))
-    //		void writeVLine_cont(int16_t x, int16_t y, int16_t h, uint16_t color)
-    //	{
-    //#if SPI_MODE_DMA
-    //		// TRY move this down
-    //		fillScanline(color, h);
-    //#endif
-    //		setAddrAndRW_cont(x, y, x, y+h-1);
-    //#if SPI_MODE_NORMAL | SPI_MODE_EXTENDED
-    //		setDCForData();
-    //		do { write16_cont(color); } while (--h > 0);
-    //#elif SPI_MODE_DMA
-    //		writeScanline_cont(h);
-    //#endif
-    //	}
-
-    //	// Writes a sequence that will render a vertical line
-    //	// At the end CS is disabled.
-    //	// In case of DMA mode, the content of scanline buffer is filled and written
-    //	__attribute__((always_inline))
-    //		void writeVLine_last(int16_t x, int16_t y, int16_t h, uint16_t color)
-    //	{
-    //#if SPI_MODE_DMA
-    //		fillScanline(color, h);
-    //#endif
-    //		setAddrAndRW_cont(x, y, x, y+h-1);
-    //#if SPI_MODE_NORMAL | SPI_MODE_EXTENDED
-    //		while (h-- > 1) {
-    //			write16_cont(color);
-    //		}
-    //		write16_last(color);
-    //#elif SPI_MODE_DMA
-    //		writeScanline_last(h);
-    //#endif
-    //	}
-
-    // Writes a sequence that will render a horizontal line
-    // CS must be set prior to calling this method
-    // for DMA mode, scanline buffer must be filled with the desired color
-    // Advantage over writeHLine_cont is that CS line is not being set and
-    // the scanlineBuffer not filled on every call
-    inline __attribute__((always_inline))
-    void writeHLine_cont_noCS_noFill(int16_t x, int16_t y, int16_t w, uint16_t color)
-    __attribute__((always_inline)) {
-      //setAddrAndRW_cont(x, y, x+w-1, y);
-      setDCForCommand();
-      write8_cont(ILI9341_CASET); // Column addr set
-      setDCForData();
-      write16_cont(x);   // XSTART
-      write16_cont(x + w - 1);   // XEND
-      setDCForCommand();
-      write8_cont(ILI9341_PASET); // Row addr set
-      setDCForData();
-      write16_cont(y);   // XSTART
-      write16_cont(y);   // XEND
-      setDCForCommand();
-      write8_cont(ILI9341_RAMWR);
-      setDCForData();
-#if SPI_MODE_NORMAL | SPI_MODE_EXTENDED
-      do {
-        write16_cont(color);
-      } while (--w > 0);
-#elif SPI_MODE_DMA
-      write_cont(_scanlineBuffer, w << 1);
-#endif
-    }
-
-    // Writes a sequence that will render a vertical line
-    // CS must be set prior to calling this method
-    // for DMA mode, scanline buffer must be filled with the desired color
-    // Advantage over writeVLine_cont is that CS line is not being set and
-    // the scanlineBuffer not filled on every call
-    inline __attribute__((always_inline))
-    void writeVLine_cont_noCS_noFill(int16_t x, int16_t y, int16_t h, uint16_t color)
-    __attribute__((always_inline)) {
-      setDCForCommand();
-      write8_cont(ILI9341_CASET); // Column addr set
-      setDCForData();
-      write16_cont(x);   // XSTART
-      write16_cont(x);   // XEND
-      setDCForCommand();
-      write8_cont(ILI9341_PASET); // Row addr set
-      setDCForData();
-      write16_cont(y);   // XSTART
-      write16_cont(y + h - 1);   // XEND
-      setDCForCommand();
-      write8_cont(ILI9341_RAMWR);
-      setDCForData();
-#if SPI_MODE_NORMAL | SPI_MODE_EXTENDED
-      do {
-        write16_cont(color);
-      } while (--h > 0);
-#elif SPI_MODE_DMA
-      write_cont(_scanlineBuffer, h << 1);
-#endif
-    }
-
-
-    //void HLine_cont(int16_t x, int16_t y, int16_t w, uint16_t color)
-    //	__attribute__((always_inline)) {
-    //		setAddrAndRW_cont(x, y, x+w-1, y);
-    //		do { writedata16_cont(color); } while (--w > 0);
-    //}
-    //void VLine_cont(int16_t x, int16_t y, int16_t h, uint16_t color)
-    //	__attribute__((always_inline)) {
-    //		setAddrAndRW_cont(x, y, x, y+h-1);
-    //		do { writedata16_cont(color); } while (--h > 0);
-    //}
-
-    // Writes a sequence that will render a pixel
-    // CS must be enabled prior to calling this method
-    // Advantage over writePixel_cont is that CS line is not set on every call
-    inline __attribute__((always_inline))
-    void writePixel_cont_noCS(int16_t x, int16_t y, uint16_t color)
-    {
-      setDCForCommand();
-      write8_cont(ILI9341_CASET); // Column addr set
-      setDCForData();
-      write16_cont(x);   // XSTART
-      write16_cont(x);   // XEND
-      setDCForCommand();
-      write8_cont(ILI9341_PASET); // Row addr set
-      setDCForData();
-      write16_cont(y);   // XSTART
-      write16_cont(y);   // XEND
-      setDCForCommand();
-      write8_cont(ILI9341_RAMWR);
-      setDCForData();
-      write16_cont(color);
-    }
-
-    inline __attribute__((always_inline))
-    void writePixel_cont(int16_t x, int16_t y, uint16_t color)
-    {
-      enableCS();
-      setDCForCommand();
-      write8_cont(ILI9341_CASET); // Column addr set
-      setDCForData();
-      write16_cont(x);   // XSTART
-      write16_cont(x);   // XEND
-      setDCForCommand();
-      write8_cont(ILI9341_PASET); // Row addr set
-      setDCForData();
-      write16_cont(y);   // XSTART
-      write16_cont(y);   // XEND
-      setDCForCommand();
-      write8_cont(ILI9341_RAMWR);
-      setDCForData();
-      write16_cont(color);
-    }
-
-    // Enables CS, writes a sequence that will render a pixel and disables CS
-    inline __attribute__((always_inline))
-    void writePixel_last(int16_t x, int16_t y, uint16_t color)
-    {
-      setAddrAndRW_cont(x, y, x, y);
-      setDCForData();
-      write16_last(color);
-    }
-
-    // Enables CS
-    inline __attribute__((always_inline))
-    void enableCS() {
-#if SPI_MODE_NORMAL | SPI_MODE_DMA
-      *_csport &= ~_cspinmask;
-#endif
-    }
-
-    // Disables CS
-    inline __attribute__((always_inline))
-    void disableCS() {
-#if SPI_MODE_NORMAL | SPI_MODE_DMA
-      *_csport |= _cspinmask;
-      //csport->PIO_SODR  |=  cspinmask;
-#elif SPI_MODE_EXTENDED
-      writecommand_last(ILI9341_NOP);	// have to send a byte to disable CS
-#endif
-    }
-
-    // Sets DC to Data (1)
-    inline __attribute__((always_inline))
-    void setDCForData() {
-      *_dcport |= _dcpinmask;
-      //_dcport->PIO_SODR |= _dcpinmask;
-    }
-
-    // Sets DC to Command (0)
-    inline __attribute__((always_inline))
-    void setDCForCommand() {
-      *_dcport &= ~_dcpinmask;
-    }
-
-  protected:
-    int16_t _width, _height; // Display w/h as modified by current rotation
-#ifdef FEATURE_PRINT_ENABLED
-    int16_t	_cursorX, _cursorY;
-    uint16_t _textcolor, _textbgcolor;
-    uint8_t	_textsize;
-    boolean _wrap; // If set, 'wrap' text at right edge of display
-#endif
-    iliRotation	_rotation;
-
-#ifdef FEATURE_ARC_ENABLED
-    float _arcAngleMax;
-    int _arcAngleOffset;
-#endif
-
-    void drawFastVLine_cont_noFill(int16_t x, int16_t y, int16_t h, uint16_t color);
-
-#ifdef FEATURE_ARC_ENABLED
-    void drawArcOffsetted(uint16_t cx, uint16_t cy, uint16_t radius, uint16_t thickness, float startAngle, float endAngle, uint16_t color);
-#endif
-
-  private:
-    uint8_t  _rst;
-    //Pio *_dcport;
-#ifdef __SAM3X8E__
-    volatile RwReg *_dcport;
-    uint32_t  _cs, _dc, _dcpinmask;
-#elif defined (__STM32F1__)
-    volatile uint32 *_dcport;
-    uint32_t  _cs, _dc, _dcpinmask;
-#else
-    volatile uint8_t *_dcport, *_csport;
-    uint8_t  _cs, _dc, _cspinmask, _dcpinmask, _SPCR, _backupSPCR;
-#endif
-
-
-#if SPI_MODE_NORMAL | SPI_MODE_DMA
-#ifdef __SAM3X8E__
-    //Pio *_csport;
-    volatile RwReg *_csport;
-    uint32_t _cspinmask;
-#elif defined (__STM32F1__)
-    volatile uint32 *_csport;
-    uint32_t   _cspinmask;
-
-#endif
-#endif
-    bool pinIsChipSelect(uint8_t cs);
-};
-
-#ifndef swap
-#define swap(a, b) { typeof(a) t = a; a = b; b = t; }
-#endif
-
-#endif
diff --git a/STM32F1/libraries/ILI9341_due_STM/ILI9341_due_gText.cpp b/STM32F1/libraries/ILI9341_due_STM/ILI9341_due_gText.cpp
deleted file mode 100644
index 89cdc9630..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/ILI9341_due_gText.cpp
+++ /dev/null
@@ -1,1936 +0,0 @@
-/*
-ILI9341_due_gText.cpp - Used for rendering GLCD fonts on Arduino Due
-
-Copyright (c) 2014  Marek Buriak
-
-The library is based on GLCD library by Bill Perry and Michael Margolis: 
-https://code.google.com/p/glcd-arduino
-
-This file is part of the Arduino ILI9341_due library. 
-Sources for this library can be found at https://github.com/marekburiak/ILI9341_Due.
-
-Fonts .h files can be created with GLCDFontCreator2 (not the one MikroElektronika):
-https://code.google.com/p/glcd-arduino/downloads/detail?name=GLCDFontCreator2.zip&can=2&q=
-
-
-ILI9341_due is free software: you can redistribute it and/or modify
-it under the terms of the GNU Lesser General Public License as published by
-the Free Software Foundation, either version 2.1 of the License, or
-(at your option) any later version.
-
-ILI9341_due is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU Lesser General Public License for more details.
-
-You should have received a copy of the GNU Lesser General Public License
-along with ILI9341_due.  If not, see <http://www.gnu.org/licenses/>.
-
-*/
-
-#include "ILI9341_due.h"
-#include "ILI9341_due_gText.h"
-
-//#include "..\Streaming\Streaming.h"
-
-//extern glcd_Device GLCD; // this is the global GLCD instance, here upcast to the base glcd_Device class 
-
-// This constructor creates a text area using the entire display
-// The device pointer is initialized using the global GLCD instance
-// New constuctors can be added to take an exlicit glcd instance pointer
-// if multiple glcd instances need to be supported
-ILI9341_due_gText::ILI9341_due_gText(ILI9341_due *ili)
-{
-	// device = (glcd_Device*)&GLCD; 
-	_ili = ili;
-	_fontMode = gTextFontMode_Solid;
-	_fontBgColor = ILI9341_BLACK;
-	_fontColor = ILI9341_WHITE;
-	_letterSpacing = 2;
-	_isLastChar = false;
-	defineArea(0,0, _ili->width() -1, _ili->height() -1, DEFAULT_SCROLLDIR); // this should never fail
-
-}
-
-// This constructor creates a text area with the given coordinates
-// full display area is used if any coordinate is invalid
-ILI9341_due_gText::ILI9341_due_gText(ILI9341_due *ili, int16_t x1, int16_t y1, int16_t x2, int16_t y2) //, textMode mode) 
-{
-	//device = (glcd_Device*)&GLCD; 
-	_ili = ili;
-	if( ! defineArea(x1,y1,x2,y2)) //,mode))
-		defineArea(0,0, _ili->width() -1,_ili->height() -1); //,mode); // this should never fail
-}
-
-#if INCLUDE_NOT_WORKING_YET
-ILI9341_due_gText::ILI9341_due_gText(ILI9341_due *ili, predefinedArea selection) //, textMode mode)
-{
-	//device = (glcd_Device*)&GLCD; 
-	_ili = ili;
-	if( ! defineArea(selection)) //,mode))
-		defineArea(0,0, _ili->width() -1,_ili->height() -1,mode); // this should never fail
-
-}
-#endif
-
-ILI9341_due_gText::ILI9341_due_gText(ILI9341_due *ili, int16_t x1, int16_t y1, int16_t columns, int16_t rows, gTextFont font) //, textMode mode)
-{
-	//device = (glcd_Device*)&GLCD; 
-	_ili = ili;
-	if( ! defineArea(x1,y1,columns,rows,font)) //, mode))
-	{
-		defineArea(0,0, _ili->width() -1,_ili->height() -1); //,mode); // this should never fail
-		selectFont(font);
-	}
-}
-
-/**
-* Clear text area with the current font background color
-* and home the cursor to upper left corner of the text area.
-*
-* @see defineArea()
-*/
-void ILI9341_due_gText::clearArea(uint16_t color)
-{
-	/*
-	* fill the area with font background color
-	*/
-	//Serial << "clearing area from " << _area.x1 << " to " << _area.x2 << endl;
-	_ili->fillRect(_area.x1, _area.y1, _area.x2 - _area.x1+1, _area.y2-_area.y1+1, color);
-
-	/*glcd_Device::SetPixels(_area.x1, _area.y1, 
-	_area.x2, _area.y2, 
-	_fontColor == BLACK ? WHITE : BLACK);*/
-	/*
-	* put cursor at home position of text area to ensure we are always inside area.
-	*/
-
-	//cursorToXY(0,0);
-}
-
-/**
-* Define a Text area by columns and rows
-*
-* @param x X coordinate of upper left corner
-* @param y Y coordinate of upper left corner
-* @param columns number of text columns
-* @param rows number of text rows
-* @param font a font definition
-* @param mode constants SCROLL_DOWN and SCROLL_UP control scroll direction
-*
-*
-* Defines a text area sized to hold columns characters across and rows characters tall.
-* It is properly sized for the specified font.
-* 
-* The area within the newly defined text area is intentionally not cleared.
-*
-* While intended for fixed width fonts, sizing will work for variable
-* width fonts.
-*
-* When variable width fonts are used, the column is based on assuming a width
-* of the widest character.
-*
-* x,y is an absolute coordinate and is relateive to the 0,0 origin of the
-* display.
-*
-* mode is an optional parameter and defaults to normal/up scrolling
-*
-* @note
-* Upon defining the text area, the cursor position for the text area will be set to x,y
-*
-* @see ClearArea()
-*/
-
-bool ILI9341_due_gText::defineArea(int16_t x, int16_t y, int16_t columns, int16_t rows, gTextFont font) //, textMode mode)
-{
-	textMode mode = DEFAULT_SCROLLDIR;
-	uint16_t x2,y2;
-
-	selectFont(font);
-
-	x2 = x + columns * (pgm_read_byte(_font+GTEXT_FONT_FIXED_WIDTH)+1) -1;
-	y2 = y + rows * (fontHeight()+1) -1;
-
-	return defineArea(x, y, x2, y2); //, mode);
-}
-
-/**
-* Define a text area by absolute coordinates
-*
-* @param x1 X coordinate of upper left corner
-* @param y1 Y coordinate of upper left corner
-* @param x2 X coordinate of lower right corner
-* @param y2 Y coordinate of lower right corner
-* @param mode constants SCROLL_DOWN and SCROLL_UP control scroll direction
-*
-* Defines a text area based on absolute coordinates.
-* The pixel coordinates for the text area are inclusive so x2,y2 is the lower right
-* pixel of the text area.
-*
-* x1,y1 and x2,y2 are an absolute coordinates and are relateive to the 0,0 origin of the
-* display.
-*
-* The area within the newly defined text area is intentionally not cleared.
-*
-* mode is an optional parameter and defaults to normal/up scrolling
-*
-* @returns true with the given area selected if all the coordinates are valid,
-* otherwise returns returns false with the area set to the full display
-*
-* @note
-* Upon creation of the text area, the cursor position for the text area will be set to x1, y1
-*
-* @see ClearArea()
-*
-*/
-
-bool ILI9341_due_gText::defineArea(int16_t x1, int16_t y1, int16_t x2, int16_t y2) //, textMode mode)
-{
-	textMode mode = DEFAULT_SCROLLDIR;
-	//Serial << "defineArea input " << x1 << " " << y1 << " " << x2 << " " << y2 << endl;
-	uint8_t ret = false;
-
-	int16_t disp_width = _ili->width();
-	int16_t disp_height = _ili->height();
-
-	//if(		(x1 >= x2)
-	//	||	(y1 >= y2)
-	//	||	(x1 >= disp_width)
-	//	||	(y1 >= disp_height)
-	//	||	(x2 >= disp_width)
-	//	||	(y2 >= disp_height)
-	//	)
-	//{
-	//	// failed sanity check so set defaults and return false 
-	//	_area.x1 = 0;
-	//	_area.y1 = 0;
-	//	_area.x2 = disp_width -1;
-	//	_area.y2 = disp_height -1;
-	//	_area.mode = DEFAULT_SCROLLDIR;
-	//} 		
-	//else
-	{  
-		_area.x1 = x1; 
-		_area.y1 = y1; 
-		_area.x2 = x2; 
-		_area.y2 = y2; 		
-		_area.mode = mode; // not yet sanity checked
-		ret = true;
-	}		
-	//Serial << "defineArea set " << _area.x1 << " " << _area.y1 << " " << _area.x2 << " " << _area.y2 << endl;
-	/*
-	* set cursor position for the area
-	*/
-	_x = x1;
-	_y = y1;	
-	_scale = 1;
-
-#ifndef GLCD_NODEFER_SCROLL
-	/*
-	* Make sure to clear a deferred scroll operation when re defining areas.
-	*/
-	_needScroll = 0;
-#endif
-	return ret;
-}
-
-/**
-* Define a predefined generic text area
-*
-* @param selection a value from @ref predefinedArea
-* @param mode constants SCROLL_DOWN and SCROLL_UP control scroll direction
-*
-* Defines a text area using a selection form a set of predefined areas.
-*
-* The area within the newly defined text area is intentionally not cleared.
-*
-* mode is an optional parameter and defaults to normal/up scrolling
-*
-* @return returns @em true if successful.
-*
-*
-* @note
-* Upon defining the text area, the cursor position for the text area will be set to 
-* the upper left coordinate of the given predefined area
-*
-* @see ClearArea()
-* @see predefinedArea
-*
-*/
-#if INCLUDE_NOT_WORKING_YET
-bool ILI9341_due_gText::defineArea(predefinedArea selection, textMode mode)
-{
-	int16_t x1,y1,x2,y2;
-	TareaToken tok;
-
-	tok.token = selection;
-
-	x1 =  tok.coord.x1;
-	y1 =  tok.coord.y1;
-	x2 =  tok.coord.x2;
-	y2 =  tok.coord.y2;
-
-	return defineArea(x1,y1,x2,y2, mode);
-}
-#endif
-/*
-* Scroll a pixel region up.
-* 	Area scrolled is defined by x1,y1 through x2,y2 inclusive.
-*  x1,y1 is upper left corder, x2,y2 is lower right corner.
-*
-*	color is the color to be used for the created space along the
-*	bottom.
-*
-*	pixels is the *exact* pixels to scroll. 1 is 1 and 9 is 9 it is
-*  not 1 less or 1 more than what you want. It is *exact*.
-*/
-
-//void ILI9341_due_gText::ScrollUp(uint8_t x1, uint8_t y1, uint8_t x2, uint8_t y2, 
-//	uint8_t pixels, uint8_t color)
-//{
-//uint8_t dy;
-//uint8_t dbyte;
-//uint8_t sy;
-//uint8_t sbyte;
-//uint8_t col;
-//
-//	/*
-//	 * Scrolling up more than area height?
-//	 */
-//	if(y1 + pixels > y2)
-//	{
-//		/*
-//		 * fill the region with "whitespace" because
-//		 * it is being totally scrolled out.
-//		 */
-//		_ili->fillRect(x1, y1, x2 - x1, y2 - y1, color);
-//		return;
-//	}
-//
-//	for(col = x1; col <= x2; col++)
-//	{
-//		dy = y1;
-//		GotoXY(col, dy & ~7);
-//		dbyte = glcd_Device::ReadData();
-//
-//
-//		/*
-//		 * preserve bits outside/above scroll region
-//		 */
-//
-//		dbyte &= (_BV((dy & 7)) - 1);
-//
-//		sy = dy + pixels;
-//		glcd_Device::GotoXY(col, sy & ~7);
-//		sbyte = glcd_Device::ReadData();
-//
-//		while(sy <= y2)
-//		{
-//			if(sbyte & _BV(sy & 7))
-//			{
-//				dbyte |= _BV(dy & 7);
-//			}
-//
-//			sy++;
-//			if((sy & 7) == 0)
-//			{
-//				/*
-//				 * If we just crossed over, then we should be done.
-//				 */
-//				if(sy < DISPLAY_HEIGHT)
-//				{
-//					glcd_Device::GotoXY(col, sy & ~7);
-//					sbyte = glcd_Device::ReadData();
-//				}
-//			}
-//
-//			if((dy & 7) == 7)
-//			{
-//				glcd_Device::GotoXY(col, dy & ~7);	// Should be able to remove this
-//				glcd_Device::WriteData(dbyte);
-//				dbyte = 0;
-//			}
-//			dy++;
-//		}
-//
-//		/*
-//		 * Handle the new area at the bottom of the region
-//		 */
-//
-//		for(uint8_t p = pixels; p; p--)
-//		{
-//			if(color == BLACK)
-//			{
-//				dbyte |= _BV(dy & 7);
-//			}
-//			else
-//			{
-//				dbyte &= ~_BV(dy & 7);
-//			}
-//
-//			if((dy & 7) == 7)
-//			{
-//				glcd_Device::GotoXY(col, dy & ~7); // should be able to remove this.
-//				glcd_Device::WriteData(dbyte);
-//				dbyte = 0;
-//			}
-//			dy++;
-//		}
-//
-//		/*
-//		 * Flush out the final destination byte
-//		 */
-//
-//
-//		if(dy & 7)
-//		{
-//			dy--;
-//
-//			glcd_Device::GotoXY(col, dy & ~7);
-//			sbyte = glcd_Device::ReadData();
-//			/*
-//			 * Preserver bits outside/below region
-//			 */
-//
-//			dy++;
-//			sbyte &= ~(_BV((dy & 7)) - 1);
-//			dbyte |= sbyte;
-//
-//			glcd_Device::WriteData(dbyte);
-//		}
-//	}
-//
-//}
-
-//#ifndef GLCD_NO_SCROLLDOWN
-//
-//void ILI9341_due_gText::ScrollDown(uint8_t x1, uint8_t y1, uint8_t x2, uint8_t y2, 
-//	uint8_t pixels, uint8_t color)
-//{
-//uint8_t dy;
-//uint8_t dbyte;
-//uint8_t sy;
-//uint8_t sbyte;
-//uint8_t col;
-//
-//	/*
-//	 * Scrolling up more than area height?
-//	 */
-//	if(y1 + pixels > y2)
-//	{
-//		/*
-//		 * fill the region with "whitespace" because
-//		 * it is being totally scrolled out.
-//		 */
-//		glcd_Device::SetPixels(x1, y1, x2, y2, color);
-//		return;
-//	}
-//
-//	/*
-//	 * Process region from left to right
-//	 */
-//	for(col = x1; col <= x2; col++)
-//	{
-//		dy = y2;
-//		glcd_Device::GotoXY(col, dy & ~7);
-//		dbyte = glcd_Device::ReadData();
-//
-//		/*
-//		 * preserve bits outside/below scroll region
-//		 */
-//
-//		dbyte &= ~(_BV(((dy & 7)+1)) - 1);
-//		sy = dy - pixels;
-//		glcd_Device::GotoXY(col, sy & ~7);
-//		sbyte = glcd_Device::ReadData();
-//
-//		while(sy >= y1)
-//		{
-//			if(sbyte & _BV(sy & 7))
-//			{
-//				dbyte |= _BV(dy & 7);
-//			}
-//			if((dy & 7) == 0)
-//			{
-//				glcd_Device::GotoXY(col, dy & ~7);	// Should be able to remove this
-//				glcd_Device::WriteData(dbyte);
-//				dbyte = 0;
-//			}
-//			dy--;
-//
-//			if(!sy)
-//				break; /* if we bottomed out, we are done */
-//			sy--;
-//			if((sy & 7) == 7)
-//			{
-//				glcd_Device::GotoXY(col, sy & ~7);
-//				sbyte = glcd_Device::ReadData();
-//			}
-//
-//		}
-//
-//		/*
-//		 * Handle the new area at the top of the column
-//		 */
-//
-//		for(uint8_t p = pixels; p; p--)
-//		{
-//			if(color == BLACK)
-//			{
-//				dbyte |= _BV(dy & 7);
-//			}
-//			else
-//			{
-//				dbyte &= ~_BV(dy & 7);
-//			}
-//
-//			if((dy & 7) == 0)
-//			{
-//				glcd_Device::GotoXY(col, dy & ~7); // should be able to remove this.
-//				glcd_Device::WriteData(dbyte);
-//				dbyte = 0;
-//			}
-//			dy--;
-//		}
-//
-//		dy++; /* point dy back to last destination row */
-//
-//		/*
-//		 * Flush out the final destination byte
-//		 */
-//
-//		if(dy & 7)
-//		{
-//			glcd_Device::GotoXY(col, dy & ~7);
-//			sbyte = glcd_Device::ReadData();
-//			/*
-//			 * Preserve bits outside/above region
-//			 */
-//
-//			sbyte &= (_BV((dy & 7)) - 1);
-//			dbyte |= sbyte;
-//			glcd_Device::WriteData(dbyte);
-//		}
-//
-//	}
-//
-//}
-//#endif //GLCD_NO_SCROLLDOWN
-
-
-
-
-
-/*
-* Handle all special processing characters
-*/
-void ILI9341_due_gText::specialChar(uint8_t c)
-{
-
-
-	if(c == '\n')
-	{
-		uint8_t height = fontHeight();
-
-		/*
-		* Erase all pixels remaining to edge of text area.on all wraps
-		* It looks better when using inverted (WHITE) text, on proportional fonts, and
-		* doing WHITE scroll fills.
-		*
-		*/
-
-
-		if(_x < _area.x2)
-			_ili->fillRect(_x, _y, _area.x2 - _x, height, _fontBgColor);
-		//glcd_Device::SetPixels(_x, _y, _area.x2, _y+height, _fontColor == BLACK ? WHITE : BLACK);
-
-		/*
-		* Check for scroll up vs scroll down (scrollup is normal)
-		*/
-#ifndef GLCD_NO_SCROLLDOWN
-		if(_area.mode == SCROLL_UP)
-#endif
-		{
-
-			/*
-			* Normal/up scroll
-			*/
-
-			/*
-			* Note this comparison and the pixel calcuation below takes into 
-			* consideration that fonts
-			* are atually 1 pixel taller when rendered. 
-			* This extra pixel is along the bottom for a "gap" between the character below.
-			*/
-			if(_y + 2*height >= _area.y2)
-			{
-#ifndef GLCD_NODEFER_SCROLL
-				if(!_needScroll)
-				{
-					_needScroll = 1;
-					return;
-				}
-#endif
-
-				/*
-				* forumula for pixels to scroll is:
-				*	(assumes "height" is one less than rendered height)
-				*
-				*		pixels = height - ((_area.y2 - _y)  - height) +1;
-				*
-				*		The forumala below is unchanged 
-				*		But has been re-written/simplified in hopes of better code
-				*
-				*/
-
-				uint8_t pixels = 2*height + _y - _area.y2 +1;
-
-				/*
-				* Scroll everything to make room
-				* * NOTE: (FIXME, slight "bug")
-				* When less than the full character height of pixels is scrolled,
-				* There can be an issue with the newly created empty line.
-				* This is because only the # of pixels scrolled will be colored.
-				* What it means is that if the area starts off as white and the text
-				* color is also white, the newly created empty text line after a scroll 
-				* operation will not be colored BLACK for the full height of the character.
-				* The only way to fix this would be alter the code use a "move pixels"
-				* rather than a scroll pixels, and then do a clear to end line immediately
-				* after the move and wrap.
-				*
-				* Currently this only shows up when
-				* there are are less than 2xheight pixels below the current Y coordinate to
-				* the bottom of the text area
-				* and the current background of the pixels below the current text line
-				* matches the text color
-				* and  a wrap was just completed.
-				*
-				* After a full row of text is printed, the issue will resolve itself.
-				* 
-				* 
-				*/
-				//ScrollUp(_area.x1, _area.y1, _area.x2, _area.y2, pixels, _fontBgColor);
-
-				_x = _area.x1;
-				_y = _area.y2 - height;
-			}
-			else
-			{
-				/*
-				* Room for simple wrap
-				*/
-
-				_x = _area.x1;
-				_y = _y+height+1;
-			}
-		}
-#ifndef GLCD_NO_SCROLLDOWN
-		else
-		{
-			/*
-			* Reverse/Down scroll
-			*/
-
-			/*
-			* Check for Wrap vs scroll.
-			*
-			* Note this comparison and the pixel calcuation below takes into 
-			* consideration that fonts
-			* are atually 1 pixel taller when rendered. 
-			*
-			*/
-			if(_y > _area.y1 + height)
-			{
-				/*
-				* There is room so just do a simple wrap
-				*/
-				_x = _area.x1;
-				_y = _y - (height+1);
-			}
-			else
-			{
-#ifndef GLCD_NODEFER_SCROLL
-				if(!_needScroll)
-				{
-					_needScroll = 1;
-					return;
-				}
-#endif
-
-				/*
-				* Scroll down everything to make room for new line
-				*	(assumes "height" is one less than rendered height)
-				*/
-
-				uint8_t pixels = height+1 - (_area.y1 - _y);
-
-				//ScrollDown(_area.x1, _area.y1, _area.x2, _area.y2, pixels, _fontBgColor);
-
-				_x = _area.x1;
-				_y = _area.y1;
-			}
-		}
-#endif
-	}
-
-}
-
-/**
-* output a character
-*
-* @param c the character to output
-*
-* If the character will not fit on the current text line
-* inside the text area,
-* the text position is wrapped to the next line. This might be
-* the next lower or the next higher line depending on the
-* scroll direction.
-*
-* If there is not enough room to fit a full line of new text after
-* wrapping, the entire text area will be scrolled to make room for a new
-* line of text. The scroll direction will be up or down
-* depending on the scroll direction for the text area.
-*/
-
-int ILI9341_due_gText::putChar(uint8_t c)
-{
-	if(_font == 0)
-	{
-		Serial.println(F("No font selected"));
-		return 0; // no font selected
-	}
-
-	/*
-	* check for special character processing
-	*/
-
-	if(c < 0x20)
-	{
-		//specialChar(c);
-		return 1;
-	}
-	uint16_t charWidth = 0;
-	uint16_t charHeight = fontHeight();
-	uint8_t charHeightInBytes = (charHeight+7)/8; /* calculates height in rounded up bytes */
-
-	uint8_t firstChar = pgm_read_byte(_font+GTEXT_FONT_FIRST_CHAR);
-	uint8_t charCount = pgm_read_byte(_font+GTEXT_FONT_CHAR_COUNT);
-
-	uint16_t index = 0;
-	uint8_t thielefont;
-
-	if(c < firstChar || c >= (firstChar+charCount)) {
-		return 0; // invalid char
-	}
-	c-= firstChar;
-
-	if( isFixedWidthFont(_font) {
-		thielefont = 0;
-		charWidth = pgm_read_byte(_font+GTEXT_FONT_FIXED_WIDTH); 
-		index = c*charHeightInBytes*charWidth+GTEXT_FONT_WIDTH_TABLE;
-	}
-	else{
-		// variable width font, read width data, to get the index
-		thielefont = 1;
-		/*
-		* Because there is no table for the offset of where the data
-		* for each character glyph starts, run the table and add up all the
-		* widths of all the characters prior to the character we
-		* need to locate.
-		*/
-		for(uint8_t i=0; i<c; i++) {  
-			index += pgm_read_byte(_font+GTEXT_FONT_WIDTH_TABLE+i);
-		}
-		/*
-		* Calculate the offset of where the font data
-		* for our character starts.
-		* The index value from above has to be adjusted because
-		* there is potentialy more than 1 byte per column in the glyph,
-		* when the characgter is taller than 8 bits.
-		* To account for this, index has to be multiplied
-		* by the height in bytes because there is one byte of font
-		* data for each vertical 8 pixels.
-		* The index is then adjusted to skip over the font width data
-		* and the font header information.
-		*/
-
-		index = index*charHeightInBytes+charCount+GTEXT_FONT_WIDTH_TABLE;
-
-		/*
-		* Finally, fetch the width of our character
-		*/
-		charWidth = pgm_read_byte(_font+GTEXT_FONT_WIDTH_TABLE+c);
-	}
-
-#ifndef GLCD_NODEFER_SCROLL
-	/*
-	* check for a defered scroll
-	* If there is a deferred scroll,
-	* Fake a newline to complete it.
-	*/
-
-	if(_needScroll)
-	{
-		putChar('\n'); // fake a newline to cause wrap/scroll
-		_needScroll = 0;
-	}
-#endif
-
-	/*
-	* If the character won't fit in the text area,
-	* fake a newline to get the text area to wrap and 
-	* scroll if necessary.
-	* NOTE/WARNING: the below calculation assumes a 1 pixel pad.
-	* This will need to be changed if/when configurable pixel padding is supported.
-	*/
-	if(_x + charWidth > _area.x2)
-	{
-		putChar('\n'); // fake a newline to cause wrap/scroll
-#ifndef GLCD_NODEFER_SCROLL
-		/*
-		* We can't defer a scroll at this point since we need to ouput
-		* a character right now.
-		*/
-		if(_needScroll)
-		{
-			putChar('\n'); // fake a newline to cause wrap/scroll
-			_needScroll = 0;
-		}
-#endif
-	}
-
-	if(_fontMode == gTextFontMode_Solid)
-		drawSolidChar(c, index, charWidth, charHeight);
-	else if(_fontMode == gTextFontMode_Transparent)
-		drawTransparentChar(c, index, charWidth, charHeight);
-
-	// last but not least, draw the character
-
-	//glcd_Device::GotoXY(_x, _y);
-
-
-	/*
-	* Draw each column of the glyph (character) horizontally
-	* 8 bits (1 page) at a time.
-	* i.e. if a font is taller than 8 bits, draw upper 8 bits first,
-	* Then drop down and draw next 8 bits and so on, until done.
-	* This code depends on WriteData() doing writes that span LCD
-	* memory pages, which has issues because the font data isn't
-	* always a multiple of 8 bits.
-	*/
-
-
-	return 1; // valid char
-}
-
-void ILI9341_due_gText::drawSolidChar(char c, uint16_t index, uint16_t charWidth, uint16_t charHeight)
-{
-	uint8_t bitId=0;
-	int16_t cx = _x;
-	int16_t cy = _y;
-#if SPI_MODE_DMA
-	uint8_t* scanlineBuff = _ili->_scanlineBuffer;
-	uint8_t fontColorHi = highByte(_fontColor);
-	uint8_t fontColorLo = lowByte(_fontColor);
-	uint8_t fontBgColorHi = highByte(_fontBgColor);
-	uint8_t fontBgColorLo = lowByte(_fontBgColor);
-#endif
-	uint8_t charHeightInBytes = (charHeight+7)/8; /* calculates height in rounded up bytes */
-
-	uint16_t lineId=0;
-	uint8_t numRenderBits = 8;
-	const uint8_t numRemainingBits = charHeight % 8;
-	//_ili->enableCS();
-	for(uint16_t j=0; j<charWidth; j++) /* each column */
-	{
-		//Serial << "Printing row" << endl;
-		lineId = 0;
-		numRenderBits = 8;
-		_ili->setAddrAndRW_cont(cx, cy, cx, cy+charHeight -1);
-		//_ili->setDCForData();
-		for(uint8_t i=0; i<charHeightInBytes; i++)	/* each vertical byte */
-		{
-			uint16_t page = i*charWidth; // page must be 16 bit to prevent overflow
-			uint8_t data = pgm_read_byte(_font+index+page+j);
-
-			/*
-			* This funkyness is because when the character glyph is not a
-			* multiple of 8 in height, the residual bits in the font data
-			* were aligned to the incorrect end of the byte with respect 
-			* to the GLCD. I believe that this was an initial oversight (bug)
-			* in Thieles font creator program. It is easily fixed
-			* in the font program but then creates a potential backward
-			* compatiblity problem.
-			*	--- bperrybap
-			*/
-			if(charHeight > 8 && charHeight < (i+1)*8)	/* is it last byte of multibyte tall font? */
-			{
-				data >>= ((i+1) << 3) - charHeight;	// (i+1)*8
-			}
-			//Serial << "data:" <<data << " x:" << cx << " y:" << cy << endl;
-
-
-			if(i == charHeightInBytes - 1)	// last byte in column
-				numRenderBits = numRemainingBits;
-
-			for( bitId = 0; bitId < numRenderBits; bitId++ )
-			{
-				if ( (data & 0x01) == 0 )
-				{
-#if SPI_MODE_NORMAL | SPI_MODE_EXTENDED
-					_ili->writedata16_cont(_fontBgColor);
-#elif SPI_MODE_DMA
-					scanlineBuff[lineId++] = fontBgColorHi;
-					scanlineBuff[lineId++] = fontBgColorLo;
-#endif
-				}
-				else
-				{
-#if SPI_MODE_NORMAL | SPI_MODE_EXTENDED
-					_ili->writedata16_cont(_fontColor);
-#elif SPI_MODE_DMA
-					scanlineBuff[lineId++] = fontColorHi;
-					scanlineBuff[lineId++] = fontColorLo;
-#endif
-				}
-				data>>=1;
-			} 
-			//delay(50);
-		}
-		//Serial << endl;
-		cx++;
-#if SPI_MODE_DMA
-		_ili->writeScanline_cont(charHeight);	// height in px * 2 bytes per px
-#endif
-
-	}
-	_ili->disableCS();	// to put CS line back up
-
-	_x += charWidth;
-
-	//Serial << " ending at " << _x  << " lastChar " << _lastChar <<endl;
-
-	if(_letterSpacing > 0 && !_isLastChar)
-	{
-		_ili->fillRect(_x, _y, _letterSpacing, charHeight, _fontBgColor);
-		_x+=_letterSpacing;
-	}
-	//Serial << "letterSpacing " << _letterSpacing <<" x: " << _x <<endl;
-}
-
-void ILI9341_due_gText::drawTransparentChar(char c, uint16_t index, uint16_t charWidth, uint16_t charHeight)
-{
-	uint8_t bitId=0;
-	uint8_t bit=0, lastBit=0;
-	int16_t cx = _x;
-	int16_t cy = _y;
-	uint16_t lineStart = 0;
-	uint16_t lineEnd = 0;
-
-#if SPI_MODE_DMA
-	_ili->fillScanline(_fontColor);	//pre-fill the scanline, we will be drawing different lenghts of it
-#endif
-
-	uint8_t charHeightInBytes = (charHeight+7)/8; /* calculates height in rounded up bytes */
-
-	uint16_t lineId=0;
-	uint8_t numRenderBits = 8;
-	const uint8_t numRemainingBits = charHeight % 8;
-
-	_ili->enableCS();
-
-	for(uint8_t j=0; j<charWidth; j++) /* each column */
-	{
-		//Serial << "Printing row" << endl;
-		lineId = 0;
-		numRenderBits = 8;
-
-		for(uint8_t i=0; i<charHeightInBytes; i++)	/* each vertical byte */
-		{
-			uint16_t page = i*charWidth; // page must be 16 bit to prevent overflow
-			uint8_t data = pgm_read_byte(_font+index+page+j);
-
-			/*
-			* This funkyness is because when the character glyph is not a
-			* multiple of 8 in height, the residual bits in the font data
-			* were aligned to the incorrect end of the byte with respect 
-			* to the GLCD. I believe that this was an initial oversight (bug)
-			* in Thieles font creator program. It is easily fixed
-			* in the font program but then creates a potential backward
-			* compatiblity problem.
-			*	--- bperrybap
-			*/
-			if(charHeight > 8 && charHeight < (i+1)*8)	/* is it last byte of multibyte tall font? */
-			{
-				data >>= ((i+1) << 3) - charHeight;	// (i+1)*8
-			}
-			//Serial << "data:" <<data << " x:" << cx << " y:" << cy << endl;
-
-			if(i == 0)
-			{
-				bit = lastBit = lineStart = 0;
-			}
-			else if(i == charHeightInBytes - 1)	// last byte in column
-				numRenderBits = numRemainingBits;
-
-			for( bitId = 0; bitId < numRenderBits; bitId++ )
-			{
-				bit = data & 0x01;
-				if(bit ^ lastBit)	// same as bit != lastBit
-				{
-					if(bit ^ 0x00) // if bit != 0 (so it's 1)
-					{	
-						lineStart = lineEnd = i*8+bitId;
-					} 
-					else 
-					{
-						_ili->setAddrAndRW_cont(cx, cy+lineStart, cx, cy+lineEnd);
-
-#if SPI_MODE_NORMAL | SPI_MODE_EXTENDED
-						_ili->setDCForData();
-						for(int p=0; p<lineEnd-lineStart+1; p++)
-						{
-							_ili->write16_cont(_fontColor);
-						}
-#elif SPI_MODE_DMA
-						_ili->writeScanline_cont(lineEnd-lineStart+1);
-#endif
-					}
-					lastBit = bit;
-				} 
-				else if(bit ^ 0x00)	// increment only if bit is 1
-				{
-					lineEnd++;
-				}
-
-				data>>=1;
-			}
-
-			if(lineEnd == charHeight - 1)	// we have a line that goes all the way to the bottom
-			{
-				_ili->setAddrAndRW_cont(cx, cy+lineStart, cx, cy+lineEnd);
-#if SPI_MODE_NORMAL | SPI_MODE_EXTENDED
-				_ili->setDCForData();
-				for(int p=0; p<lineEnd-lineStart+1; p++)
-				{
-					_ili->write16_cont(_fontColor);
-				}
-#elif SPI_MODE_DMA
-				_ili->writeScanline_cont(lineEnd-lineStart+1);
-#endif
-			}
-			//delay(25);
-		}
-		//Serial << endl;
-		cx++;
-	}
-	_ili->disableCS();	// to put CS line back up
-
-	_x += charWidth;
-
-	if(_letterSpacing > 0 && !_isLastChar)
-	{
-		_x+=_letterSpacing;
-	}
-}
-
-/**
-* output a character string
-*
-* @param str pointer to a null terminated character string.
-*
-* Outputs all the characters in the string to the text area. 
-* See putChar() for a full description of how characters are
-* written to the text area.
-*/
-
-void ILI9341_due_gText::puts(char *str)
-{
-	while(*str)
-	{
-		if(*(str+1) == 0)
-			_isLastChar = true;
-		putChar((uint8_t)*str);
-		str++;
-	}
-	_isLastChar = false;
-}
-
-/**
-* output a String class string
-*
-* @param str String class string
-*
-* Outputs all the characters in the string to the text area. 
-* See putChar() for a full description of how characters are
-* written to the text area.
-*
-*/
-void ILI9341_due_gText::puts(const String &str)
-{
-	for (int i = 0; i < str.length(); i++)
-	{
-		write(str[i]);
-	}
-}
-
-/**
-* output a program memory character string
-*
-* @param str pointer to a null terminated character string stored in program memory
-*
-* Outputs all the characters in the string to the text area. 
-* See putChar() for a full description of how characters are
-* written to the text area.
-*
-* @see putChar()
-* @see puts()
-* @see drawString()
-* @see drawString_P()
-* @see write()
-*/
-
-void ILI9341_due_gText::puts_P(PGM_P str)
-{
-	uint8_t c;
-
-	while((c = pgm_read_byte(str)) != 0)
-	{
-		putChar(c);
-		str++;
-	}
-}
-
-/**
-* output a String class string at x,y coordinate
-*
-* @param str pointer to a null terminated character string
-* @param x specifies the horizontal location
-* @param y specifies the vertical location
-*
-*
-* Outputs all the characters in the string to the text area. 
-* X & Y are zero based pixel coordinates and are relative to 
-* the upper left corner of the text area.
-*
-* See putChar() for a full description of how characters are
-* written to the text area.
-*/
-void ILI9341_due_gText::drawString(String &str, int16_t x, int16_t y)
-{
-	cursorToXY(x,y);
-	puts(str);
-}
-
-/**
-* output a program memory character string at x,y coordinate
-*
-* @param str pointer to a null terminated character string stored in program memory
-* @param x specifies the horizontal location
-* @param y specifies the vertical location
-*
-*
-* Outputs all the characters in the string to the text area. 
-* X & Y are zero based pixel coordinates and are relative to 
-* the upper left corner of the text area.
-*
-* See putChar() for a full description of how characters are
-* written to the text area.
-*/
-
-void ILI9341_due_gText::drawString_P(PGM_P str, int16_t x, int16_t y)
-{
-	cursorToXY(x,y);
-	puts_P(str);
-}
-
-/**
-* output a character string at x,y coordinate
-*
-* @param str String class string
-* @param x specifies the horizontal location
-* @param y specifies the vertical location
-*
-*
-* Outputs all the characters in the string to the text area. 
-* X & Y are zero based pixel coordinates and are relative to 
-* the upper left corner of the text area.
-*
-* See putChar() for a full description of how characters are
-* written to the text area.
-*/
-
-void ILI9341_due_gText::drawString(char *str, int16_t x, int16_t y)
-{
-	cursorToXY(x,y);
-	puts(str);
-}
-
-void ILI9341_due_gText::drawString(char *str, int16_t x, int16_t y, uint16_t pixelsClearedOnLeft, uint16_t pixelsClearedOnRight)
-{
-	cursorToXY(x,y);
-
-	// CLEAR PIXELS ON THE LEFT
-	if(pixelsClearedOnLeft > 0)
-		_ili->fillRect(_x-pixelsClearedOnLeft, _y, pixelsClearedOnLeft, fontHeight(), _fontBgColor); 
-
-	puts(str);
-
-	// CLEAR PIXELS ON THE RIGHT
-	if(pixelsClearedOnRight > 0)
-		_ili->fillRect(_x, _y, pixelsClearedOnRight, fontHeight(), _fontBgColor); 
-}
-
-void ILI9341_due_gText::drawString(char *str, int16_t x, int16_t y, gTextEraseLine eraseLine)
-{
-	cursorToXY(x,y);
-
-	// CLEAR PIXELS ON THE LEFT
-	if(eraseLine == gTextEraseFromBOL || eraseLine == gTextEraseFullLine)
-	{
-		uint16_t clearX1 = max(min(_x, _area.x1), _x-1024);		
-		_ili->fillRect(clearX1, _y, _x - clearX1, fontHeight(), _fontBgColor); 
-	}
-
-	puts(str);
-
-	// CLEAR PIXELS ON THE RIGHT
-	if(eraseLine == gTextEraseToEOL || eraseLine == gTextEraseFullLine)
-	{
-		uint16_t clearX2 = min(max(_x,_area.x2), _x+1024);
-		_ili->fillRect(_x, _y, clearX2 - _x, fontHeight(), _fontBgColor); 
-	}
-}
-
-void ILI9341_due_gText::drawString(char *str, gTextAlign align)
-{
-	drawStringPivotedOffseted(str, align, gTextPivotDefault, 0, 0, 0, 0);
-}
-
-void ILI9341_due_gText::drawString(char *str, gTextAlign align, gTextEraseLine eraseLine)
-{
-	uint16_t pixelsClearedOnLeft = 0;
-	uint16_t pixelsClearedOnRight = 0;
-	if(eraseLine == gTextEraseFromBOL || eraseLine == gTextEraseFullLine)
-		pixelsClearedOnLeft = 1024;
-	if(eraseLine == gTextEraseToEOL || eraseLine == gTextEraseFullLine)
-		pixelsClearedOnRight = 1024;
-	drawStringPivotedOffseted(str, align, gTextPivotDefault, 0, 0, pixelsClearedOnLeft, pixelsClearedOnRight);
-}
-
-void ILI9341_due_gText::drawString(char *str, gTextAlign align, uint16_t pixelsClearedOnLeft, uint16_t pixelsClearedOnRight)
-{
-	drawStringPivotedOffseted(str, align, gTextPivotDefault, 0, 0, pixelsClearedOnLeft, pixelsClearedOnRight);
-}
-
-void ILI9341_due_gText::drawStringOffseted(char *str, gTextAlign align, uint16_t offsetX, uint16_t offsetY)
-{
-	drawStringPivotedOffseted(str, align, gTextPivotDefault,offsetX, offsetY, 0, 0);
-}
-
-void ILI9341_due_gText::drawStringOffseted(char *str, gTextAlign align, uint16_t offsetX, uint16_t offsetY, gTextEraseLine eraseLine)
-{
-	uint16_t pixelsClearedOnLeft = 0;
-	uint16_t pixelsClearedOnRight = 0;
-	if(eraseLine == gTextEraseFromBOL || eraseLine == gTextEraseFullLine)
-		pixelsClearedOnLeft = 1024;
-	if(eraseLine == gTextEraseToEOL || eraseLine == gTextEraseFullLine)
-		pixelsClearedOnRight = 1024;
-	drawStringPivotedOffseted(str, align, gTextPivotDefault,offsetX, offsetY, pixelsClearedOnLeft, pixelsClearedOnRight);
-}
-
-void ILI9341_due_gText::drawStringOffseted(char *str, gTextAlign align, uint16_t offsetX, uint16_t offsetY, uint16_t pixelsClearedOnLeft, uint16_t pixelsClearedOnRight)
-{
-	drawStringPivotedOffseted(str, align, gTextPivotDefault,offsetX, offsetY, pixelsClearedOnLeft, pixelsClearedOnRight);
-}
-
-void ILI9341_due_gText::drawStringPivoted(char *str, int16_t x, int16_t y, gTextPivot pivot)
-{
-	cursorToXY(x,y);
-
-	if(pivot != gTextPivotTopLeft && pivot != gTextPivotDefault)
-		applyPivot(str, pivot);
-
-	puts(str);
-}
-
-void ILI9341_due_gText::drawStringPivoted(char *str, gTextAlign align, gTextPivot pivot)
-{
-	drawStringPivotedOffseted(str, align, pivot, 0, 0, 0, 0);
-}
-
-void ILI9341_due_gText::drawStringPivoted(char *str, gTextAlign align, gTextPivot pivot, gTextEraseLine eraseLine)
-{
-	uint16_t pixelsClearedOnLeft = 0;
-	uint16_t pixelsClearedOnRight = 0;
-	if(eraseLine == gTextEraseFromBOL || eraseLine == gTextEraseFullLine)
-		pixelsClearedOnLeft = 1024;
-	if(eraseLine == gTextEraseToEOL || eraseLine == gTextEraseFullLine)
-		pixelsClearedOnRight = 1024;
-	drawStringPivotedOffseted(str, align, pivot, 0, 0, pixelsClearedOnLeft, pixelsClearedOnRight);
-}
-
-void ILI9341_due_gText::drawStringPivoted(char *str, gTextAlign align, gTextPivot pivot, uint16_t pixelsClearedOnLeft, uint16_t pixelsClearedOnRight)
-{
-	drawStringPivotedOffseted(str, align, pivot, 0, 0, pixelsClearedOnLeft, pixelsClearedOnRight);
-}
-
-void ILI9341_due_gText::drawStringPivotedOffseted(char *str, gTextAlign align, gTextPivot pivot, uint16_t offsetX, uint16_t offsetY)
-{
-	drawStringPivotedOffseted(str, align, pivot, offsetX, offsetY, 0, 0);
-}
-
-void ILI9341_due_gText::drawStringPivotedOffseted(char *str, gTextAlign align, gTextPivot pivot, uint16_t offsetX, uint16_t offsetY, gTextEraseLine eraseLine)
-{
-	uint16_t pixelsClearedOnLeft = 0;
-	uint16_t pixelsClearedOnRight = 0;
-	if(eraseLine == gTextEraseFromBOL || eraseLine == gTextEraseFullLine)
-		pixelsClearedOnLeft = 1024;
-	if(eraseLine == gTextEraseToEOL || eraseLine == gTextEraseFullLine)
-		pixelsClearedOnRight = 1024;
-	drawStringPivotedOffseted(str, align, pivot, offsetX, offsetY, pixelsClearedOnLeft, pixelsClearedOnRight);
-}
-
-void ILI9341_due_gText::drawStringPivotedOffseted(char *str, gTextAlign align, gTextPivot pivot, uint16_t offsetX, uint16_t offsetY, uint16_t pixelsClearedOnLeft, uint16_t pixelsClearedOnRight)
-{
-	//Serial << pixelsClearedOnLeft << " " << pixelsClearedOnRight << endl;
-	_x = _area.x1;
-	_y = _area.y1;
-
-	//PIVOT
-	if(pivot == gTextPivotDefault)
-	{
-		switch(align)
-		{
-		case gTextAlignTopLeft: { pivot = gTextPivotTopLeft; break;	}
-		case gTextAlignTopCenter: { pivot = gTextPivotTopCenter; break;	}
-		case gTextAlignTopRight: { pivot = gTextPivotTopRight; break; }
-		case gTextAlignMiddleLeft: { pivot = gTextPivotMiddleLeft; break; }
-		case gTextAlignMiddleCenter: { pivot = gTextPivotMiddleCenter; break; }
-		case gTextAlignMiddleRight: { pivot = gTextPivotMiddleRight; break; }
-		case gTextAlignBottomLeft: { pivot = gTextPivotBottomLeft; break; }
-		case gTextAlignBottomCenter: { pivot = gTextPivotBottomCenter; break; }
-		case gTextAlignBottomRight: { pivot = gTextPivotBottomRight; break; }
-		}
-	}
-
-	if(pivot != gTextPivotTopLeft)
-		applyPivot(str, pivot);
-
-	// ALIGN
-	if(align != gTextAlignTopLeft)
-	{
-		switch(align)
-		{
-		case gTextAlignTopCenter:
-			{
-				_x += (_area.x2 - _area.x1)/2;
-				break;
-			}
-		case gTextAlignTopRight:
-			{
-				_x += _area.x2 - _area.x1;
-				break;
-			}
-		case gTextAlignMiddleLeft:
-			{
-				_y += (_area.y2-_area.y1)/2;
-				break;
-			}
-		case gTextAlignMiddleCenter:
-			{
-				_x += (_area.x2 - _area.x1)/2;
-				_y += (_area.y2 - _area.y1)/2;
-				break;
-			}
-		case gTextAlignMiddleRight:
-			{
-				_x += _area.x2 - _area.x1;
-				_y += (_area.y2 - _area.y1)/2;
-				break;
-			}
-		case gTextAlignBottomLeft:
-			{
-				_y += _area.y2 - _area.y1;
-				break;
-			}
-		case gTextAlignBottomCenter:
-			{
-				_x += (_area.x2 - _area.x1)/2;
-				_y += _area.y2 - _area.y1;
-				break;
-			}
-		case gTextAlignBottomRight:
-			{
-				_x += _area.x2 - _area.x1;
-				_y += _area.y2 - _area.y1;
-				break;
-			}
-		}
-	}
-
-	// OFFSET
-	_x+=offsetX;
-	_y+=offsetY;
-
-	// CLEAR PIXELS ON THE LEFT
-	if(pixelsClearedOnLeft > 0)
-	{
-		int16_t clearX1 = max(min(_x, (int16_t)_area.x1), _x-(int16_t)pixelsClearedOnLeft);		
-		//Serial.println(clearX1);
-		_ili->fillRect(clearX1, _y, _x - clearX1, fontHeight(), _fontBgColor); 
-	}
-
-	puts(str);
-
-	// CLEAR PIXELS ON THE RIGHT
-	if(pixelsClearedOnRight > 0)
-	{
-		int16_t clearX2 = min(max(_x, _area.x2), _x+pixelsClearedOnRight);
-		//Serial << "area from " << _area.x1 << " to " << _area.x2 << endl;
-		//Serial << "clearing on right from " << _x << " to " << clearX2 << endl;
-		_ili->fillRect(_x, _y, clearX2 - _x, fontHeight(), _fontBgColor); 
-	}
-}
-
-void ILI9341_due_gText::applyPivot(char *str, gTextPivot pivot)
-{
-	switch(pivot)
-	{
-	case gTextPivotTopCenter:
-		{
-			_x -= stringWidth(str)/2;
-			break;
-		}
-	case gTextPivotTopRight:
-		{
-			_x -= stringWidth(str);
-			break;
-		}
-	case gTextPivotMiddleLeft:
-		{
-			_y -= fontHeight()/2;
-			break;
-		}
-	case gTextPivotMiddleCenter:
-		{
-			_x -= stringWidth(str)/2;
-			_y -= fontHeight()/2;			
-			break;
-		}
-	case gTextPivotMiddleRight:
-		{
-			_x -= stringWidth(str);
-			_y -= fontHeight()/2;
-			break;
-		}
-	case gTextPivotBottomLeft:
-		{
-			_y -= fontHeight();
-			break;
-		}
-	case gTextPivotBottomCenter:
-		{
-			_x -= stringWidth(str)/2;
-			_y -= fontHeight();
-			break;
-		}
-	case gTextPivotBottomRight:
-		{
-			_x -= stringWidth(str);
-			_y -= fontHeight();
-			break;
-		}
-	}
-}
-
-/**
-* Positions cursor to a character based column and row.
-*
-* @param column specifies the horizontal position 
-* @param row  specifies the vertical position
-*
-*	Column and Row are zero based character positions
-*	and are relative the the upper left corner of the
-*	text area base on the size of the currently selected font.
-*
-* While intended for fixed width fonts, positioning will work for variable
-* width fonts.
-*
-* When variable width fonts are used, the column is based on assuming a width
-* of the widest character.
-*
-* @see cursorToXY()
-*/
-
-void ILI9341_due_gText::cursorTo( uint8_t column, uint8_t row)
-{
-	if(_font == 0)
-		return; // no font selected
-
-	/*
-	* Text position is relative to current text area
-	*/
-
-	_x = column * (pgm_read_byte(_font+GTEXT_FONT_FIXED_WIDTH)+1) + _area.x1;
-	_y = row * (fontHeight()+1) + _area.y1;
-
-#ifndef GLCD_NODEFER_SCROLL
-	/*
-	* Make sure to clear a deferred scroll operation when repositioning
-	*/
-	_needScroll = 0;
-#endif
-}
-
-// Bill, I think the following would be a useful addition to the API
-// Should we add a sanity check to these?
-/**
-* Positions cursor to a character based column on the current row.
-*
-* @param column specifies the horizontal position 
-*
-*	Column is a 0 based character position
-*	based on the size of the currently selected font.
-*
-* If column is negative then the column position is relative to the current cursor
-* position.
-*
-* @warning
-* While intended only for fixed width fonts, cursor repositioning will be done for variable
-* width fonts.
-* When variable width fonts are used, the column is based on assuming a width
-* of the widest character in the font.
-* Because the widest character is used for the amount of cursor movement, the amount
-* of cursor movement when using relative positioning will often not be consistent with
-* the number characters previously rendered. For example, if a letter "l" was written
-* and the cursor was reposisitioned with a -1, the amount backed up will be much larger
-* than the width of the "l".
-*
-*
-* @see cursorToXY()
-*/
-void ILI9341_due_gText::cursorTo(int8_t column)
-{
-	if(_font == 0)
-		return; // no font selected
-	/*
-	* Text position is relative to current text area
-	* negative value moves the cursor backwards
-	*/
-	if(column >= 0) 
-		_x = column * (pgm_read_byte(_font+GTEXT_FONT_FIXED_WIDTH)+1) + _area.x1;
-	else
-		_x -= column * (pgm_read_byte(_font+GTEXT_FONT_FIXED_WIDTH)+1);   	
-
-#ifndef GLCD_NODEFER_SCROLL
-	/*
-	* Make sure to clear a deferred scroll operation when repositioning
-	*/
-	_needScroll = 0;
-#endif
-}
-
-
-/**
-* Positions cursor to a X,Y position
-*
-* @param x specifies the horizontal location
-* @param y specifies the vertical location
-*
-*	X & Y are zero based pixel coordinates and are relative to 
-*	the upper left corner of the text area.
-*
-* @see cursorTo()
-*/
-
-void ILI9341_due_gText::cursorToXY( int16_t x, int16_t y)
-{
-
-	/*
-	* Text position is relative to current text area
-	*/
-
-	_x = _area.x1 + x;
-	_y = _area.y1 + y;
-	//Serial << F("cursorToXY x:") << x << F(" y:") << y << endl;
-
-#ifndef GLCD_NODEFER_SCROLL
-	/*
-	* Make sure to clear a deferred scroll operation when repositioning
-	*/
-	_needScroll = 0;
-#endif
-}
-
-/**
-* Erase in Line
-*
-* @param type type of line erase
-*
-* @arg \ref eraseTO_EOL Erase from cursor to end of line
-* @arg \ref eraseFROM_BOL Erase from beginning of line to cursor
-* @arg \ref eraseFULL_LINE Erase entire line
-*
-* Erases all or part of a line of text depending on the type
-* of erase specified.
-*
-* If type is not specified it is assumed to be \ref eraseTO_EOL
-*
-* The cursor position does not change.
-*
-* @see ClearArea()
-* @see eraseLine_t
-*/
-
-void ILI9341_due_gText::eraseTextLine(uint16_t color, gTextEraseLine type) 
-{
-	int16_t x = _x;
-	int16_t y = _y;
-	int16_t height = fontHeight();
-	//uint8_t color = (_fontColor == BLACK) ? WHITE : BLACK;
-
-	switch(type)
-	{
-	case gTextEraseToEOL:
-		_ili->fillRect(x, y, _area.x2-x, height, color);
-		//glcd_Device::SetPixels(x, y, _area.x2, y+height, color);
-		break;
-	case gTextEraseFromBOL:
-		_ili->fillRect(_area.x1, y, x - _area.x1, height, color);
-		//glcd_Device::SetPixels(_area.x1, y, x, y+height, color);
-		break;
-	case gTextEraseFullLine:
-		_ili->fillRect(_area.x1, y, _area.x2 - _area.x1, height, color);
-		//glcd_Device::SetPixels(_area.x1, y, _area.x2, y+height, color);
-		break;
-	}
-
-	/*
-	* restore cursor position
-	*/
-	cursorToXY(x,y);
-}
-
-/**
-* Erase Text Line
-*
-* @param row row # of text to earase
-*
-* Erases a line of text and moves the cursor
-* to the begining of the line. Rows are zero based so
-* the top line/row of a text area is 0.
-*
-* @see ClearArea()
-*/
-
-void ILI9341_due_gText::eraseTextLine(uint16_t color, uint8_t row)
-{
-	cursorTo(0, row);
-	eraseTextLine(color, gTextEraseToEOL);	
-}
-
-
-/**
-* Select a Font and font color
-*
-* @param font a font definition
-* @param color  can be WHITE or BLACK and defaults to black
-* @param callback optional font read routine
-*
-*
-* Selects the font definition as the current font for the text area.
-*
-* All subsequent printing functions will use this font. 
-*
-* Font definitions from included font definition files are stored in program memory 
-* You can have as many fonts defines as will fit in program memory up to 64k and can
-* switch between them with this function.
-*
-* If the optional callback argument is ommitted, a default routine
-* is selected that assumes that the font is in program memory (flash).
-*
-* @note
-* When the display is initilized in normal mode, BLACK renders dark 
-* pixels on a white background and WHITE renders white pixels on 
-* black background; however, if the display is set to INVERTED mode
-* all colors are inverted. 
-*
-* @see setFontColor()
-* @see SetTextMode()
-*/
-
-void ILI9341_due_gText::selectFont(gTextFont font)
-{
-	_font = font;
-}
-
-void ILI9341_due_gText::selectFont(gTextFont font, uint16_t fontColor)
-{
-	_font = font;
-	_fontColor = fontColor;
-}
-
-void ILI9341_due_gText::selectFont(gTextFont font, uint16_t fontColor, uint16_t backgroundColor)
-{
-	_font = font;
-	_fontColor = fontColor;
-	_fontBgColor = backgroundColor;
-}
-
-/**
-* Select a font color
-*
-* @param color  can be WHITE or BLACK
-*
-*
-* @see selectFont()
-* @see SetTextMode()
-*/
-
-void ILI9341_due_gText::setFontColor(uint16_t color)
-{
-	_fontColor = color;
-}
-
-void ILI9341_due_gText::setFontColor(uint8_t R, uint8_t G, uint8_t B)
-{
-	_fontColor = _ili->color565(R,G,B);
-}
-
-void ILI9341_due_gText::setFontColor(uint16_t color, uint16_t backgroundColor)
-{
-	_fontColor = color;
-	_fontBgColor = backgroundColor;
-}
-
-void ILI9341_due_gText::setFontColor(uint8_t R, uint8_t G, uint8_t B, uint8_t bgR, uint8_t bgG, uint8_t bgB)
-{
-	_fontColor = _ili->color565(R,G,B);
-	_fontBgColor = _ili->color565(bgR,bgG,bgB);
-}
-
-
-void ILI9341_due_gText::setFontLetterSpacing(uint8_t letterSpacing)
-{
-	_letterSpacing = letterSpacing;
-}
-
-
-void ILI9341_due_gText::setFontMode(gTextFontMode fontMode)
-{
-	if(fontMode == gTextFontMode_Solid || fontMode == gTextFontMode_Transparent)
-		_fontMode = fontMode;
-}
-
-/**
-* Set TextArea mode
-*
-* @param mode  text area mode
-*
-* Currently mode is a scroll direction
-* @arg SCROLL_UP
-* @arg SCROLL_DOWN
-*
-* @see selectFont()
-* @see setFontColor()
-* @see defineArea()
-*/
-/*
-*/
-#if INLCUDE_NOT_WORKING_YET
-void ILI9341_due_gText::SetTextMode(textMode mode)
-{
-
-	/*
-	* when other modes are added the tarea.mode variable will hold a bitmask or enum for the modde and should be renamed
-	*/
-	_area.mode = mode; 
-} 
-#endif
-
-
-
-
-/**
-* Returns the pixel width of a character
-*
-* @param c character to be sized
-*
-* @return The width in pixels of the given character
-* including any inter-character gap pixels following the character when the character is
-* rendered on the display.
-*
-* @note The font for the character is the most recently selected font.
-*
-* @see StringWidth()
-* @see StringWidth_P()
-*/
-
-uint16_t ILI9341_due_gText::charWidth(uint8_t c)
-{
-	int16_t width = 0;
-
-	if(isFixedWidthFont(_font){
-		width = pgm_read_byte(_font+GTEXT_FONT_FIXED_WIDTH);
-	} 
-	else{ 
-		// variable width font 
-		uint8_t firstChar = pgm_read_byte(_font+GTEXT_FONT_FIRST_CHAR);
-		uint8_t charCount = pgm_read_byte(_font+GTEXT_FONT_CHAR_COUNT);
-
-		// read width data
-		if(c >= firstChar && c < (firstChar+charCount)) {
-			c -= firstChar;
-			width = pgm_read_byte(_font+GTEXT_FONT_WIDTH_TABLE+c);
-			//Serial << "strWidth of " << c << " : " << width << endl;
-		}
-	}	
-	return width;
-}
-
-/**
-* Returns the pixel width of a string
-*
-* @param str pointer to string stored in RAM
-*
-* @return the width in pixels of the sum of all the characters in the
-* the string pointed to by str. 
-*
-* @see charWidth()
-* @see StringWidth_P()
-*/
-
-uint16_t ILI9341_due_gText::stringWidth(const char* str)
-{
-	uint16_t width = 0;
-
-	while(*str != 0) {
-		width += charWidth(*str++) + _letterSpacing;
-	}
-	if(width > 0)
-		width -= _letterSpacing;
-	return width;
-}
-
-/**
-* Returns the pixel width of a character
-*
-* @param str pointer to string stored in program memory
-*
-* @return the width in pixels of the sum of all the characters in the
-* the string pointed to by str. 
-*
-* @see charWidth()
-* @see StringWidth()
-*/
-
-uint16_t ILI9341_due_gText::stringWidth_P(PGM_P str)
-{
-	uint16_t width = 0;
-
-	while(pgm_read_byte(str) != 0) {
-		width += charWidth(pgm_read_byte(str++)) + _letterSpacing;
-	}
-	width -= _letterSpacing;
-	return width;
-}
-
-/**
-* Returns the pixel width of a character
-*
-* @param str String class string
-*
-* @return the width in pixels of the sum of all the characters in the
-* the string pointed to by str. 
-*
-* @see charWidth()
-* @see StringWidth()
-*/
-
-uint16_t ILI9341_due_gText::stringWidth_P(String &str)
-{
-	uint16_t width = 0;
-
-	for (int i = 0; i < str.length(); i++)
-	{
-		width += charWidth(str[i]) + _letterSpacing;
-	}
-	width -= _letterSpacing;
-	return width;
-}
-
-
-/**
-* Legacy function to print a number
-*
-* @param n is the number to print
-*
-*
-* @see print(n)
-*/
-void ILI9341_due_gText::printNumber(long n)
-{
-	uint8_t buf[10];  // prints up to 10 digits  
-	uint8_t i=0;
-	if(n==0)
-		putChar('0');
-	else{
-		if(n < 0){
-			putChar('-');
-			n = -n;
-		}
-		while(n>0 && i <= 10){
-			buf[i++] = n % 10;  // n % base
-			n /= 10;   // n/= base
-		}
-		for(; i >0; i--)
-			putChar((char) (buf[i-1] < 10 ? '0' + buf[i-1] : 'A' + buf[i-1] - 10));	  
-	}
-}
-
-/**
-* output a character to the text area
-* @param c the character to output
-*
-* This method is needed for the Print base class
-* @see putChar()
-*/
-
-
-size_t ILI9341_due_gText::write(uint8_t c) 
-{
-	return(putChar(c));
-} 
-
-//
-//#ifndef USE_ARDUINO_FLASHSTR
-//// functions to store and print strings in Progmem
-//// these should be removed when Arduino supports FLASH strings in the base print class
-///**
-//* print a flash based string
-//* @param str pointer to a null terminated character string stored in program memory
-//*
-//* @see puts_P()
-//*/
-//void ILI9341_due_gText::printFlash(FLASHSTRING str)
-//{
-//	puts_P((PGM_P) str);
-//}
-//
-///**
-//* print a flash based string
-//* @param str pointer to a null terminated character string stored in program memory
-//*
-//* The string is output followed by a newline.
-//*
-//* @see puts_P()
-//*/
-//void ILI9341_due_gText::printFlashln(FLASHSTRING str)
-//{
-//	printFlash(str);
-//	write('\n');
-//}
-//#endif
-
-
diff --git a/STM32F1/libraries/ILI9341_due_STM/ILI9341_due_gText.h b/STM32F1/libraries/ILI9341_due_STM/ILI9341_due_gText.h
deleted file mode 100644
index 415d853e2..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/ILI9341_due_gText.h
+++ /dev/null
@@ -1,385 +0,0 @@
-/*
-ILI9341_due_gText.cpp - Used for rendering GLCD fonts on Arduino Due
-
-Copyright (c) 2014  Marek Buriak
-
-The library is based on GLCD library by Bill Perry and Michael Margolis: 
-https://code.google.com/p/glcd-arduino
-
-This file is part of the Arduino ILI9341_due library. 
-Sources for this library can be found at https://github.com/marekburiak/ILI9341_Due.
-
-Fonts .h files can be created with GLCDFontCreator2 (not the one MikroElektronika):
-https://code.google.com/p/glcd-arduino/downloads/detail?name=GLCDFontCreator2.zip&can=2&q=
-
-
-ILI9341_due is free software: you can redistribute it and/or modify
-it under the terms of the GNU Lesser General Public License as published by
-the Free Software Foundation, either version 2.1 of the License, or
-(at your option) any later version.
-
-ILI9341_due is distributed in the hope that it will be useful,
-but WITHOUT ANY WARRANTY; without even the implied warranty of
-MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-GNU Lesser General Public License for more details.
-
-You should have received a copy of the GNU Lesser General Public License
-along with ILI9341_due.  If not, see <http://www.gnu.org/licenses/>.
-
-*/
-
-#ifndef	ILI9341_GTEXT_H
-#define ILI9341_GTEXT_H
-
-//#include "WString.h"
-//#include "../Streaming/Streaming.h" 
-#include "ILI9341_due.h"
-
-#define INCLUDE_NOT_WORKING_YET 0
-
-#define GTEXT_VERSION 1 // software version of this code
-
-// Font Indices
-#define GTEXT_FONT_LENGTH			0
-#define GTEXT_FONT_FIXED_WIDTH	2
-#define GTEXT_FONT_HEIGHT			3
-#define GTEXT_FONT_FIRST_CHAR		4
-#define GTEXT_FONT_CHAR_COUNT		5
-#define GTEXT_FONT_WIDTH_TABLE	6
-
-#define GTEXT_DRAW_DIRECTION_RIGHT 0
-#define GTEXT_DRAW_DIRECTION_DOWN 1
-#define GTEXT_DRAW_DIRECTION_LEFT 2
-#define GTEXT_DRAW_DIRECTION_UP 3
-
-typedef enum  {
-	gTextFontMode_Solid = 0,
-	gTextFontMode_Transparent = 1
-} gTextFontMode;
-
-
-// the following returns true if the given font is fixed width
-// zero length is flag indicating fixed width font (array does not contain width data entries)
-#define isFixedWidthFont(font)  (pgm_read_byte(font+GTEXT_FONT_LENGTH) == 0 && pgm_read_byte(font+GTEXT_FONT_LENGTH+1) == 0))
-
-/*
-* Coodinates for predefined areas are compressed into a single 32 bit token.
-*
-* This works as the coordinates are cuurenly only 8 bit values.
-*
-* This allows the creatation of an unlmited number of predefined areas with zero code or
-* data space overhead.
-* 
-* A macro is used to create the tokens from a set of x1,y1 x2,y2 coordinates.
-*
-* A union is used to extract the coordinates from the 32 bit token.
-*
-* WARNING:
-*	This is non portable code in that it will only work on little endian processors.
-*	If you use big endian you have to switch the byte ordering in the union.
-*/
-
-#define MK_TareaToken(x1, y1, x2, y2) \
-	(uint32_t) (((uint32_t) (x1) << 24) | ((uint32_t)(y1) << 16) | ((uint32_t)(x2) << 8) | (uint32_t)(y2))
-
-/// @cond hide_from_doxygen
-typedef union
-{       
-	struct
-	{      
-		uint8_t y2;
-		uint8_t x2;
-		uint8_t y1;
-		uint8_t x1;
-	}coord;
-
-	uint32_t token; // swap byte order above for big endian
-
-}TareaToken;
-/// @endcond
-
-typedef uint8_t textMode;  // type holding mode for scrolling and future attributes like padding etc.
-// the only textMode supported in the current release is scrolling
-
-const textMode SCROLL_UP = 0;
-const textMode SCROLL_DOWN = 1; // this was changed from -1 so it can used in a bitmask 
-const textMode DEFAULT_SCROLLDIR = SCROLL_UP;
-
-/**
-* @defgroup glcd_enum GLCD enumerations
-*/
-
-/**
-* @ingroup glcd_enum
-* @hideinitializer
-* @brief Pre Defined Text areas
-*
-* These enumerations are used to easily define text areas 
-* using predefined display areas.\n
-* They are used with the
-* \ref gText::DefineArea(predefinedArea selection, textMode mode) "DefineArea()" function call.
-*/
-typedef enum  {
-
-	//textAreaFULL         = MK_TareaToken( 0,               0,                DISPLAY_WIDTH -1,   DISPLAY_HEIGHT -1   ),
-	///**<Entire GLCD display */
-
-	//textAreaTOP          = MK_TareaToken( 0,               0,                DISPLAY_WIDTH -1,   DISPLAY_HEIGHT/2 -1 ),
-	///**<Top half of GLCD display */
-
-	//textAreaBOTTOM       = MK_TareaToken( 0,               DISPLAY_HEIGHT/2, DISPLAY_WIDTH -1,   DISPLAY_HEIGHT -1   ),
-	///**<Bottom half of GLCD display */
-
-	//textAreaLEFT         = MK_TareaToken( 0,               0,                DISPLAY_WIDTH/2 -1, DISPLAY_HEIGHT -1   ),
-	///**<Left side of GLCD display */
-
-	//textAreaRIGHT        = MK_TareaToken( DISPLAY_WIDTH/2, 0,                DISPLAY_WIDTH -1,   DISPLAY_HEIGHT -1   ),
-	///**<Right side of GLCD display */
-
-	//textAreaTOPLEFT      = MK_TareaToken( 0,               0,                DISPLAY_WIDTH/2 -1, DISPLAY_HEIGHT/2 -1 ),
-	///**<Upper left quarter of GLCD display */
-
-	//textAreaTOPRIGHT     = MK_TareaToken( DISPLAY_WIDTH/2, 0,                DISPLAY_WIDTH -1,   DISPLAY_HEIGHT/2 -1 ),
-	///**<Upper right quarter of GLCD display */
-
-	//textAreaBOTTOMLEFT   = MK_TareaToken( 0,               DISPLAY_HEIGHT/2, DISPLAY_WIDTH/2 -1, DISPLAY_HEIGHT -1   ),
-	///**<Buttom left quarter of GLCD display */
-
-	//textAreaBOTTOMRIGHT  = MK_TareaToken( DISPLAY_WIDTH/2, DISPLAY_HEIGHT/2, DISPLAY_WIDTH -1,   DISPLAY_HEIGHT -1   )
-	///**<Bottom right quarter of GLCD display */
-
-} predefinedArea;
-
-
-typedef enum  {
-	gTextAlignTopLeft,
-	gTextAlignTopCenter,
-	gTextAlignTopRight,
-	gTextAlignMiddleLeft,
-	gTextAlignMiddleCenter,
-	gTextAlignMiddleRight,
-	gTextAlignBottomLeft,
-	gTextAlignBottomCenter,
-	gTextAlignBottomRight
-} gTextAlign;
-
-typedef enum {
-	gTextPivotDefault,
-	gTextPivotTopLeft,
-	gTextPivotTopCenter,
-	gTextPivotTopRight,
-	gTextPivotMiddleLeft,
-	gTextPivotMiddleCenter,
-	gTextPivotMiddleRight,
-	gTextPivotBottomLeft,
-	gTextPivotBottomCenter,
-	gTextPivotBottomRight
-} gTextPivot;
-
-
-/*
-* enums for ansi style erase function
-* These values match the ANSI EraseInLine terminal primitive: CSI n K
-*/  
-/**
-* @ingroup glcd_enum
-* @hideinitializer
-* @brief Erase line options
-* @details
-* These enumerations are used with the
-* \ref gText::EraseTextLine( eraseLine_t type) "EraseTextLine()" function call.\n
-* They provide similar functionality to the
-* ANSI EraseInLine terminal primitive: CSI n K
-*
-*/
-typedef enum {
-	gTextEraseToEOL = 0x01, 	/**< Erase From cursor to end of Line */
-	gTextEraseFromBOL = 0x02,	/**< Erase From Begining of Line to Cursor*/
-	gTextEraseFullLine = 0x03	/**< Erase Entire line */
-} gTextEraseLine;
-
-typedef const uint8_t* gTextFont;
-//typedef uint8_t (*FontCallback)(gTextFont);
-
-
-//static glcd_Device    *device;              // static pointer to the device instance
-
-/// @cond hide_from_doxygen
-typedef struct _area
-{
-	uint16_t x1;
-	uint16_t y1;
-	uint16_t x2;
-	uint16_t y2;
-	int8_t  mode;
-} area;
-/// @endcond
-
-/**
-* @class gText
-* @brief Functions for Text Areas
-* @details
-* A text area acts like a terminal monitor and text output is displayed 
-* within the confines of a rectangle given in the DefineArea command.
-* All of the following text area functions operate on a user defined text area.
-*/
-
-// graphical device text routines
-class ILI9341_due_gText : public Print
-{
-private:
-	ILI9341_due *_ili;
-	//FontCallback	ucg_pgm_read;     // now static, move back here if each instance needs its own callback
-	uint16_t _fontColor;
-	uint16_t _fontBgColor;
-	gTextFont _font;
-	area _area;
-	int16_t	_x;
-	int16_t	_y;
-	uint8_t _scale;
-	uint8_t _letterSpacing;
-	bool _isLastChar;
-	uint8_t _fontMode;
-	
-#ifndef GLCD_NODEFER_SCROLL
-	uint8_t			_needScroll; // set when text scroll has been defered
-#endif
-	void specialChar(uint8_t c);
-	void drawSolidChar(char c, uint16_t index, uint16_t charWidth, uint16_t charHeight);
-	void drawTransparentChar(char c, uint16_t index, uint16_t charWidth, uint16_t charHeight);
-	// Scroll routines are private for now
-	void ScrollUp(uint8_t x1, uint8_t y1, uint8_t x2, uint8_t y2, uint8_t pixels, uint8_t color);
-	void ScrollDown(uint8_t x1, uint8_t y1, uint8_t x2, uint8_t y2, uint8_t pixels, uint8_t color);
-	void applyPivot(char *str, gTextPivot pivot);
-
-public:
-	ILI9341_due_gText(ILI9341_due *ili); // default - uses the entire display
-	ILI9341_due_gText(ILI9341_due *ili, int16_t x1, int16_t y1, int16_t x2, int16_t y2); //, textMode mode=DEFAULT_SCROLLDIR);
-
-	ILI9341_due_gText(ILI9341_due *ili, int16_t x1, int16_t y1, int16_t columns, int16_t rows, gTextFont font); //, textMode mode=DEFAULT_SCROLLDIR);
-
-
-	bool defineArea(int16_t x1, int16_t y1, int16_t x2, int16_t y2); //, textMode mode=DEFAULT_SCROLLDIR);
-	bool defineArea(int16_t x1, int16_t y1, int16_t columns, int16_t rows, gTextFont font); //, textMode mode=DEFAULT_SCROLLDIR);
-	void clearArea(uint16_t color);
-
-	// Font Functions
-	void selectFont(gTextFont font);
-	void selectFont(gTextFont font, uint16_t color);
-	void selectFont(gTextFont font, uint16_t color, uint16_t backgroundColor);
-	void setFontColor(uint16_t color);
-	void setFontColor(uint8_t R, uint8_t G, uint8_t B);
-	void setFontColor(uint16_t color, uint16_t backgroundColor);
-	void setFontColor(uint8_t R, uint8_t G, uint8_t B, uint8_t bgR, uint8_t bgG, uint8_t bgB);
-	void setFontLetterSpacing(uint8_t letterSpacing);
-	uint8_t getFontLetterSpacing()	{
-		return _letterSpacing; 
-	};
-	void setFontMode(gTextFontMode fontMode);
-
-	int putChar(uint8_t c);
-	void puts(char *str);
-	void puts(const String &str); // for Arduino String Class
-	void puts_P(PGM_P str);
-
-
-	void drawString(String &str, int16_t x, int16_t y); // for Arduino String class
-	void drawString_P(PGM_P str, int16_t x, int16_t y);
-
-	void drawString(char *str, int16_t x, int16_t y);
-	void drawString(char *str, int16_t x, int16_t y, gTextEraseLine eraseLine);
-	void drawString(char *str, int16_t x, int16_t y, uint16_t pixelsClearedOnLeft, uint16_t pixelsClearedOnRight);
-	void drawString(char *str, gTextAlign align);
-	void drawString(char *str, gTextAlign align, gTextEraseLine eraseLine);
-	void drawString(char *str, gTextAlign align, uint16_t pixelsClearedOnLeft, uint16_t pixelsClearedOnRight);
-
-	void drawStringOffseted(char *str, gTextAlign align, uint16_t offsetX, uint16_t offsetY);
-	void drawStringOffseted(char *str, gTextAlign align, uint16_t offsetX, uint16_t offsetY, gTextEraseLine eraseLine);
-	void drawStringOffseted(char *str, gTextAlign align, uint16_t offsetX, uint16_t offsetY, uint16_t pixelsClearedOnLeft, uint16_t pixelsClearedOnRight);
-
-	void drawStringPivoted(char *str, int16_t x, int16_t y, gTextPivot pivot);
-	void drawStringPivoted(char *str, gTextAlign align, gTextPivot pivot);
-	void drawStringPivoted(char *str, gTextAlign align, gTextPivot pivot, gTextEraseLine eraseLine);
-	void drawStringPivoted(char *str, gTextAlign align, gTextPivot pivot, uint16_t pixelsClearedOnLeft, uint16_t pixelsClearedOnRight);
-
-	void drawStringPivotedOffseted(char *str, gTextAlign align, gTextPivot pivot, uint16_t offsetX, uint16_t offsetY);
-	void drawStringPivotedOffseted(char *str, gTextAlign align, gTextPivot pivot, uint16_t offsetX, uint16_t offsetY, gTextEraseLine eraseLine);
-	void drawStringPivotedOffseted(char *str, gTextAlign align, gTextPivot pivot, uint16_t offsetX, uint16_t offsetY, uint16_t pixelsClearedOnLeft, uint16_t pixelsClearedOnRight);
-
-	size_t write(uint8_t c);  // character output for print base class
-
-	void cursorTo( uint8_t column, uint8_t row); // 0 based coordinates for character columns and rows
-	void cursorTo( int8_t column); // move cursor on the current row
-	void cursorToXY( int16_t x, int16_t y); // coordinates relative to active text area
-
-	inline __attribute__((always_inline))
-		uint8_t fontHeight()	{
-			return pgm_read_byte(_font+GTEXT_FONT_HEIGHT);
-	};
-
-	inline __attribute__((always_inline))
-		uint8_t fontHeight(gTextFont font) {
-			return pgm_read_byte(font+GTEXT_FONT_HEIGHT);
-	};
-
-	uint16_t charWidth(uint8_t c);
-	uint16_t stringWidth(const char* str);
-	uint16_t stringWidth_P(PGM_P str);
-	uint16_t stringWidth_P(String &str);
-
-	void eraseTextLine(uint16_t color, gTextEraseLine type=gTextEraseToEOL); //ansi like line erase function 
-	void eraseTextLine(uint16_t color, uint8_t row); // erase the entire text line in the given row and move cursor to left position
-
-	void printNumber(long n);
-
-#if INCLUDE_NOT_WORKING_YET
-	ILI9341_due_gText(ILI9341_due *ili, predefinedArea selection); //, textMode mode=DEFAULT_SCROLLDIR);
-	bool defineArea(predefinedArea selection); //, textMode mode=DEFAULT_SCROLLDIR);
-	void setTextMode(textMode mode); // change to the given text mode
-#endif
-
-	static uint16_t charWidth(uint8_t c, gTextFont font)
-	{
-		int16_t width = 0;
-
-		if(isFixedWidthFont(font){
-			width = pgm_read_byte(font+GTEXT_FONT_FIXED_WIDTH);
-		} 
-		else{ 
-			// variable width font 
-			uint8_t firstChar = pgm_read_byte(font+GTEXT_FONT_FIRST_CHAR);
-			uint8_t charCount = pgm_read_byte(font+GTEXT_FONT_CHAR_COUNT);
-
-			// read width data
-			if(c >= firstChar && c < (firstChar+charCount)) {
-				c -= firstChar;
-				width = pgm_read_byte(font+GTEXT_FONT_WIDTH_TABLE+c);
-			}
-		}	
-		return width;
-	};
-
-	static uint16_t stringWidth(const char* str, gTextFont font, uint8_t letterSpacing)
-	{
-		uint16_t width = 0;
-
-		while(*str != 0) {
-			width += ILI9341_due_gText::charWidth(*str++, font) + letterSpacing;
-		}
-		if(width > 0)
-			width -= letterSpacing;
-
-		return width;
-	};
-
-	//#ifndef USE_ARDUINO_FLASHSTR	
-	//	// when the following function is supported in arduino it will be removed from this library
-	//	void printFlash(FLASHSTRING str); //this overrides the Arduino print function to implicilty store the string in flash (progmem)
-	//    void printFlashln(FLASHSTRING str);
-	//#endif
-
-	/*@}*/
-
-};
-
-#endif
diff --git a/STM32F1/libraries/ILI9341_due_STM/ILI_SdFatConfig.h b/STM32F1/libraries/ILI9341_due_STM/ILI_SdFatConfig.h
deleted file mode 100644
index 84ad39a35..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/ILI_SdFatConfig.h
+++ /dev/null
@@ -1,196 +0,0 @@
-/* Arduino SdFat Library
- * Copyright (C) 2012 by William Greiman
- *
- * This file is part of the Arduino SdFat Library
- *
- * This Library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This Library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with the Arduino SdFat Library.  If not, see
- * <http://www.gnu.org/licenses/>.
- */
-/**
- * \file
- * \brief configuration definitions
- */
-#ifndef ILI_SdFatConfig_h
-#define ILI_SdFatConfig_h
-#include <stdint.h>
-
-//------------------------------------------------------------------------------
-/**
- * Set USE_SEPARATE_FAT_CACHE nonzero to use a second 512 byte cache
- * for FAT table entries.  Improves performance for large writes that
- * are not a multiple of 512 bytes.
- */
-#ifdef __arm__
-#define ILI_USE_SEPARATE_FAT_CACHE 1
-#else  // __arm__
-#define ILI_USE_SEPARATE_FAT_CACHE 0
-#endif  // __arm__
-//------------------------------------------------------------------------------
-/**
- * Set USE_MULTI_BLOCK_SD_IO nonzero to use multi-block SD read/write.
- *
- * Don't use mult-block read/write on small AVR boards.
- */
-#if defined(RAMEND) && RAMEND < 3000
-#define ILI_USE_MULTI_BLOCK_SD_IO 0
-#else
-#define ILI_USE_MULTI_BLOCK_SD_IO 1
-#endif
-
-//------------------------------------------------------------------------------
-/**
- * To enable SD card CRC checking set USE_SD_CRC nonzero.
- *
- * Set USE_SD_CRC to 1 to use a smaller slower CRC-CCITT function.
- *
- * Set USE_SD_CRC to 2 to used a larger faster table driven CRC-CCITT function.
- */
-#define ILI_USE_SD_CRC 0
-//------------------------------------------------------------------------------
-/**
- * To use multiple SD cards set USE_MULTIPLE_CARDS nonzero.
- *
- * Using multiple cards costs about 200  bytes of flash.
- *
- * Each card requires about 550 bytes of SRAM so use of a Mega is recommended.
- */
-#define ILI_USE_MULTIPLE_CARDS 0
-//------------------------------------------------------------------------------
-/**
- * Set DESTRUCTOR_CLOSES_FILE nonzero to close a file in its destructor.
- *
- * Causes use of lots of heap in ARM.
- */
-#define ILI_DESTRUCTOR_CLOSES_FILE 0
-//------------------------------------------------------------------------------
-/**
- * For AVR
- *
- * Set USE_SERIAL_FOR_STD_OUT nonzero to use Serial (the HardwareSerial class)
- * for error messages and output from print functions like ls().
- *
- * If USE_SERIAL_FOR_STD_OUT is zero, a small non-interrupt driven class
- * is used to output messages to serial port zero.  This allows an alternate
- * Serial library like SerialPort to be used with SdFat.
- *
- * You can redirect stdOut with SdFat::setStdOut(Print* stream) and
- * get the current stream with SdFat::stdOut().
- */
-#define ILI_USE_SERIAL_FOR_STD_OUT 0
-//------------------------------------------------------------------------------
-/**
- * Call flush for endl if ENDL_CALLS_FLUSH is nonzero
- *
- * The standard for iostreams is to call flush.  This is very costly for
- * SdFat.  Each call to flush causes 2048 bytes of I/O to the SD.
- *
- * SdFat has a single 512 byte buffer for SD I/O so it must write the current
- * data block to the SD, read the directory block from the SD, update the
- * directory entry, write the directory block to the SD and read the data
- * block back into the buffer.
- *
- * The SD flash memory controller is not designed for this many rewrites
- * so performance may be reduced by more than a factor of 100.
- *
- * If ENDL_CALLS_FLUSH is zero, you must call flush and/or close to force
- * all data to be written to the SD.
- */
-#define ILI_ENDL_CALLS_FLUSH 0
-//------------------------------------------------------------------------------
-/**
- * Allow FAT12 volumes if FAT12_SUPPORT is nonzero.
- * FAT12 has not been well tested.
- */
-#define ILI_FAT12_SUPPORT 0
-//------------------------------------------------------------------------------
-/**
- * SPI SCK divisor for SD initialization commands.
- * or greater
- */
-#ifdef __AVR__
-const uint8_t ILI_SPI_SCK_INIT_DIVISOR = 64;
-#else
-const uint8_t ILI_SPI_SCK_INIT_DIVISOR = 128;
-#endif
-//------------------------------------------------------------------------------
-/**
- * Set ENABLE_SPI_TRANSACTION nonzero to enable the SPI transaction feature
- * of the standard Arduino SPI library.  You must include SPI.h in your
- * sketches when ENABLE_SPI_TRANSACTION is nonzero.
- */
-#define ILI_ENABLE_SPI_TRANSACTION 0
-//------------------------------------------------------------------------------
-/**
- * Set ENABLE_SPI_YIELD nonzero to enable release of the SPI bus during
- * SD card busy waits.  
- *
- * This will allow interrupt routines to access the SPI bus if 
- * ENABLE_SPI_TRANSACTION is nonzero.
- * 
- * Setting ENABLE_SPI_YIELD will introduce some extra overhead and will
- * slightly slow transfer rates.  A few older SD cards may fail when 
- * ENABLE_SPI_YIELD is nonzero.
- */
-#define ILI_ENABLE_SPI_YIELD 0
-//------------------------------------------------------------------------------
-/**
- * Force use of Arduino Standard SPI library if USE_ARDUINO_SPI_LIBRARY
- * is nonzero. This will override native and software SPI for all boards.
- */
-#define ILI_USE_ARDUINO_SPI_LIBRARY 0
-//------------------------------------------------------------------------------
-/**
- * Define AVR_SOF_SPI nonzero to use software SPI on all AVR Arduinos.
- */
-#define ILI_AVR_SOFT_SPI 0
-//------------------------------------------------------------------------------
-/**
- * Define DUE_SOFT_SPI nonzero to use software SPI on Due Arduinos.
- */
-#define ILI_DUE_SOFT_SPI 0
-//------------------------------------------------------------------------------
-
-/**
- * Define LEONARDO_SOFT_SPI nonzero to use software SPI on Leonardo Arduinos.
- * LEONARDO_SOFT_SPI allows an unmodified 328 Shield to be used
- * on Leonardo Arduinos.
- */
-#define ILI_LEONARDO_SOFT_SPI 0
-//------------------------------------------------------------------------------
-/**
- * Define MEGA_SOFT_SPI nonzero to use software SPI on Mega Arduinos.
- * MEGA_SOFT_SPI allows an unmodified 328 Shield to be used
- * on Mega Arduinos.
- */
-#define ILI_MEGA_SOFT_SPI 0
-//------------------------------------------------------------------------------
-/**
- * Set TEENSY3_SOFT_SPI nonzero to use software SPI on Teensy 3.x boards.
- */
-#define ILI_TEENSY3_SOFT_SPI 0
-//------------------------------------------------------------------------------
-/** 
- * Define software SPI pins.  Default allows Uno shields to be used on other 
- * boards.
- */
-// define software SPI pins
-/** Default Software SPI chip select pin */
-uint8_t const ILI_SOFT_SPI_CS_PIN = 10;
-/** Software SPI Master Out Slave In pin */
-uint8_t const ILI_SOFT_SPI_MOSI_PIN = 11;
-/** Software SPI Master In Slave Out pin */
-uint8_t const ILI_SOFT_SPI_MISO_PIN = 12;
-/** Software SPI Clock pin */
-uint8_t const ILI_SOFT_SPI_SCK_PIN = 13;
-#endif  // SdFatConfig_h
diff --git a/STM32F1/libraries/ILI9341_due_STM/ILI_SdSpi.h b/STM32F1/libraries/ILI9341_due_STM/ILI_SdSpi.h
deleted file mode 100644
index ee4102416..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/ILI_SdSpi.h
+++ /dev/null
@@ -1,188 +0,0 @@
-/* Arduino SdSpi Library
- * Copyright (C) 2013 by William Greiman
- *
- * This file is part of the Arduino SdSpi Library
- *
- * This Library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This Library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with the Arduino SdSpi Library.  If not, see
- * <http://www.gnu.org/licenses/>.
- */
- /**
- * \file
- * \brief SdSpi class for V2 SD/SDHC cards
- */
-#ifndef ILI_SdSpi_h
-#define ILI_SdSpi_h
-#include <Arduino.h>
-#include "ILI_SdFatConfig.h"
-
-#if !ILI_USE_ARDUINO_SPI_LIBRARY
-// AVR Arduinos
-#ifdef __AVR__
-#if ILI_AVR_SOFT_SPI
-#define ILI_USE_SOFTWARE_SPI 1
-#elif ILI_LEONARDO_SOFT_SPI && defined(__AVR_ATmega32U4__) && !defined(CORE_TEENSY)
-#define ILI_USE_SOFTWARE_SPI 1
-#elif ILI_MEGA_SOFT_SPI && (defined(__AVR_ATmega1280__)\
-      ||defined(__AVR_ATmega2560__))
-#define ILI_USE_SOFTWARE_SPI 1
-#else  // ILI_USE_SOFTWARE_SPI
-#define ILI_USE_NATIVE_AVR_SPI 1
-#endif  // ILI_USE_SOFTWARE_SPI
-#endif  // __AVR__
-// Due
-#if defined(__arm__) && !defined(CORE_TEENSY) && !defined(__STM32F1__)
-#if ILI_DUE_SOFT_SPI
-#define ILI_USE_SOFTWARE_SPI 1
-#else  // ILI_DUE_SOFT_SPI
-/** Nonzero - use native SAM3X SPI */
-#define ILI_USE_NATIVE_SAM3X_SPI 1
-#endif  // ILI_DUE_SOFT_SPI
-#endif  // defined(__arm__) && !defined(CORE_TEENSY | __STM32F1__)
-
-// STM32F1 Maple Mini
-#if defined(__arm__) && defined(__STM32F1__)
-#if ILI_DUE_SOFT_SPI
-#define ILI_USE_SOFTWARE_SPI 1
-#else  // ILI_DUE_SOFT_SPI
-/** Nonzero - use native STM32F1 SPI */
-#define ILI_USE_NATIVE_STM32F1_SPI 1
-#endif  // ILI_DUE_SOFT_SPI
-#endif  // defined(__arm__) && defined(__STM32F1__)
-
-// Teensy 3.0
-#if defined(__arm__) && defined(CORE_TEENSY)
-#if ILI_TEENSY3_SOFT_SPI
-#define ILI_USE_SOFTWARE_SPI 1
-#else  // ILI_TEENSY3_SOFT_SPI
-/** Nonzero - use native MK20DX128 SPI */
-#define ILI_USE_NATIVE_TEENSY3_SPI 1
-#endif  // ILI_TEENSY3_SOFT_SPI
-#endif  // defined(__arm__) && defined(CORE_TEENSY)
-#endif  // !ILI_USE_ARDUINO_SPI_LIBRARY
-
-#ifndef ILI_USE_SOFTWARE_SPI
-#define ILI_USE_SOFTWARE_SPI 0
-#endif  //  ILI_USE_SOFTWARE_SPI
-
-#ifndef ILI_USE_NATIVE_AVR_SPI
-#define ILI_USE_NATIVE_AVR_SPI 0
-#endif
-
-#ifndef ILI_USE_NATIVE_SAM3X_SPI
-#define ILI_USE_NATIVE_SAM3X_SPI 0
-#endif  // ILI_USE_NATIVE_SAM3X_SPI
-
-#ifndef ILI_USE_NATIVE_STM32F1_SPI
-#define ILI_USE_NATIVE_STM32F1_SPI 0
-#endif  // ILI_USE_NATIVE_STM32F1_SPI
-
-#ifndef ILI_USE_NATIVE_TEENSY3_SPI
-#define ILI_USE_NATIVE_TEENSY3_SPI 0
-#endif  // ILI_USE_NATIVE_TEENSY3_SPI
-//------------------------------------------------------------------------------
-// define default chip select pin
-//
-#if !ILI_USE_SOFTWARE_SPI
-/** The default chip select pin for the SD card is SS. */
-uint8_t const  ILI_SD_CHIP_SELECT_PIN = SS;
-#else  // USE_AVR_SOFTWARE_SPI
-/** SPI chip select pin for software SPI. */
-uint8_t const ILI_SD_CHIP_SELECT_PIN = SOFT_SPI_CS_PIN;
-#endif  // USE_AVR_SOFTWARE_SPI
-
-//------------------------------------------------------------------------------
-/**
- * \class SdSpi
- * \brief SPI class for access to SD and SDHC flash memory cards.
- */
-class ILI_SdSpi {
- public:
-  /** Initialize the SPI bus */
-  void begin();
-  /** Set SPI options for access to SD/SDHC cards.
-   * 
-   * \param[in] spiDivisor SCK clock divider relative to the system clock.
-   */
-  void init(uint8_t spiDivisor);
-  /** Receive a byte. 
-   *
-   * \return The byte.
-   */
-  uint8_t receive();
-  /** Receive multiple bytes.
-   *
-   * \param[out] buf Buffer to receive the data.   
-   * \param[in] n Number of bytes to receive.
-   *
-   * \return Zero for no error or nonzero error code.
-   */   
-  uint8_t receive(uint8_t* buf, size_t n);
-  /** Send a byte.
-   *
-   * \param[in] data Byte to send
-   */
-  void send(uint8_t data);
-   /** Send multiple bytes.
-   *
-   * \param[in] buf Buffer for data to be sent.   
-   * \param[in] n Number of bytes to send.
-   */   
-  void send(uint8_t* buf, size_t n);
-};
-//------------------------------------------------------------------------------
-// Use of inline for AVR results in up to 10% better write performance.
-// Inline also save a little flash memory.
-/** inline avr native functions if nonzero. */
-#define ILI_USE_AVR_NATIVE_SPI_INLINE 1
-#if ILI_USE_NATIVE_AVR_SPI && ILI_USE_AVR_NATIVE_SPI_INLINE
-inline uint8_t ILI_SdSpi::receive() {
-  SPDR = 0XFF;
-  while (!(SPSR & (1 << SPIF))) {}
-  return SPDR;
-}
-inline uint8_t ILI_SdSpi::receive(uint8_t* buf, size_t n) {
-  if (n-- == 0) return 0;
-  SPDR = 0XFF;
-  for (size_t i = 0; i < n; i++) {
-    while (!(SPSR & (1 << SPIF))) {}
-    uint8_t b = SPDR;
-    SPDR = 0XFF;
-    buf[i] = b;
-  }
-  while (!(SPSR & (1 << SPIF))) {}
-  buf[n] = SPDR;
-  return 0;
-}
-inline void ILI_SdSpi::send(uint8_t data) {
-  SPDR = data;
-  while (!(SPSR & (1 << SPIF))) {}
-}
-inline void ILI_SdSpi::send(const uint8_t* buf , size_t n) {
-  if (n == 0) return;
-  SPDR = buf[0];
-  if (n > 1) {
-    uint8_t b = buf[1];
-    size_t i = 2;
-    while (1) {
-      while (!(SPSR & (1 << SPIF))) {}
-      SPDR = b;
-      if (i == n) break;
-      b = buf[i++];
-    }
-  }
-  while (!(SPSR & (1 << SPIF))) {}
-}
-#endif  // ILI_USE_NATIVE_AVR_SPI && ILI_USE_AVR_NATIVE_SPI_INLINE
-#endif  // ILI_SdSpi_h
-
diff --git a/STM32F1/libraries/ILI9341_due_STM/ILI_SdSpiSAM3X.cpp b/STM32F1/libraries/ILI9341_due_STM/ILI_SdSpiSAM3X.cpp
deleted file mode 100644
index 1108e60ed..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/ILI_SdSpiSAM3X.cpp
+++ /dev/null
@@ -1,411 +0,0 @@
-/* Arduino SdSpi Library
- * Copyright (C) 2013 by William Greiman
- *
- * This file is part of the Arduino SdSpi Library
- *
- * This Library is free software: you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation, either version 3 of the License, or
- * (at your option) any later version.
- *
- * This Library is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with the Arduino SdSpi Library.  If not, see
- * <http://www.gnu.org/licenses/>.
- */
-#include "ILI_SdSpi.h"
-#if ILI_USE_NATIVE_SAM3X_SPI
-/** Use SAM3X DMAC if nonzero */
-#define ILI_USE_SAM3X_DMAC 1
-/** Use extra Bus Matrix arbitration fix if nonzero */
-#define ILI_USE_SAM3X_BUS_MATRIX_FIX 0
-/** Time in ms for DMA receive timeout */
-#define ILI_SAM3X_DMA_TIMEOUT 100
-/** chip select register number */
-#define ILI_SPI_CHIP_SEL 3
-/** DMAC receive channel */
-#define ILI_SPI_DMAC_RX_CH  1
-/** DMAC transmit channel */
-#define ILI_SPI_DMAC_TX_CH  0
-/** DMAC Channel HW Interface Number for SPI TX. */
-#define ILI_SPI_TX_IDX  1
-/** DMAC Channel HW Interface Number for SPI RX. */
-#define ILI_SPI_RX_IDX  2
-//------------------------------------------------------------------------------
-/** Disable DMA Controller. */
-static void ILI_dmac_disable() {
-  DMAC->DMAC_EN &= (~DMAC_EN_ENABLE);
-}
-/** Enable DMA Controller. */
-static void ILI_dmac_enable() {
-  DMAC->DMAC_EN = DMAC_EN_ENABLE;
-}
-/** Disable DMA Channel. */
-static void ILI_dmac_channel_disable(uint32_t ul_num) {
-  DMAC->DMAC_CHDR = DMAC_CHDR_DIS0 << ul_num;
-}
-/** Enable DMA Channel. */
-static void ILI_dmac_channel_enable(uint32_t ul_num) {
-  DMAC->DMAC_CHER = DMAC_CHER_ENA0 << ul_num;
-}
-/** Poll for transfer complete. */
-static bool ILI_dmac_channel_transfer_done(uint32_t ul_num) {
-  return (DMAC->DMAC_CHSR & (DMAC_CHSR_ENA0 << ul_num)) ? false : true;
-}
-//------------------------------------------------------------------------------
-void ILI_SdSpi::begin() {
-  PIO_Configure(
-    g_APinDescription[PIN_SPI_MOSI].pPort,
-    g_APinDescription[PIN_SPI_MOSI].ulPinType,
-    g_APinDescription[PIN_SPI_MOSI].ulPin,
-    g_APinDescription[PIN_SPI_MOSI].ulPinConfiguration);
-  PIO_Configure(
-    g_APinDescription[PIN_SPI_MISO].pPort,
-    g_APinDescription[PIN_SPI_MISO].ulPinType,
-    g_APinDescription[PIN_SPI_MISO].ulPin,
-    g_APinDescription[PIN_SPI_MISO].ulPinConfiguration);
-  PIO_Configure(
-    g_APinDescription[PIN_SPI_SCK].pPort,
-    g_APinDescription[PIN_SPI_SCK].ulPinType,
-    g_APinDescription[PIN_SPI_SCK].ulPin,
-    g_APinDescription[PIN_SPI_SCK].ulPinConfiguration);
-  pmc_enable_periph_clk(ID_SPI0);
-#if ILI_USE_SAM3X_DMAC
-  pmc_enable_periph_clk(ID_DMAC);
-  ILI_dmac_disable();
-  DMAC->DMAC_GCFG = DMAC_GCFG_ARB_CFG_FIXED;
-  ILI_dmac_enable();
-#if ILI_USE_SAM3X_BUS_MATRIX_FIX
-  MATRIX->MATRIX_WPMR = 0x4d415400;
-  MATRIX->MATRIX_MCFG[1] = 1;
-  MATRIX->MATRIX_MCFG[2] = 1;
-  MATRIX->MATRIX_SCFG[0] = 0x01000010;
-  MATRIX->MATRIX_SCFG[1] = 0x01000010;
-  MATRIX->MATRIX_SCFG[7] = 0x01000010;
-#endif  // ILI_USE_SAM3X_BUS_MATRIX_FIX
-#endif  // ILI_USE_SAM3X_DMAC
-}
-//------------------------------------------------------------------------------
-// start RX DMA
-static void ILI_spiDmaRX(uint8_t* dst, uint16_t count) {
-  ILI_dmac_channel_disable(ILI_SPI_DMAC_RX_CH);
-  DMAC->DMAC_CH_NUM[ILI_SPI_DMAC_RX_CH].DMAC_SADDR = (uint32_t)&SPI0->SPI_RDR;
-  DMAC->DMAC_CH_NUM[ILI_SPI_DMAC_RX_CH].DMAC_DADDR = (uint32_t)dst;
-  DMAC->DMAC_CH_NUM[ILI_SPI_DMAC_RX_CH].DMAC_DSCR =  0;
-  DMAC->DMAC_CH_NUM[ILI_SPI_DMAC_RX_CH].DMAC_CTRLA = count |
-      DMAC_CTRLA_SRC_WIDTH_BYTE | DMAC_CTRLA_DST_WIDTH_BYTE;
-  DMAC->DMAC_CH_NUM[ILI_SPI_DMAC_RX_CH].DMAC_CTRLB = DMAC_CTRLB_SRC_DSCR |
-      DMAC_CTRLB_DST_DSCR | DMAC_CTRLB_FC_PER2MEM_DMA_FC |
-      DMAC_CTRLB_SRC_INCR_FIXED | DMAC_CTRLB_DST_INCR_INCREMENTING;
-  DMAC->DMAC_CH_NUM[ILI_SPI_DMAC_RX_CH].DMAC_CFG = DMAC_CFG_SRC_PER(ILI_SPI_RX_IDX) |
-      DMAC_CFG_SRC_H2SEL | DMAC_CFG_SOD | DMAC_CFG_FIFOCFG_ASAP_CFG;
-  ILI_dmac_channel_enable(ILI_SPI_DMAC_RX_CH);
-}
-//------------------------------------------------------------------------------
-// start TX DMA
-static void ILI_spiDmaTX(const uint8_t* src, uint16_t count) {
-  static uint8_t ff = 0XFF;
-  uint32_t src_incr = DMAC_CTRLB_SRC_INCR_INCREMENTING;
-  if (!src) {
-    src = &ff;
-    src_incr = DMAC_CTRLB_SRC_INCR_FIXED;
-  }
-  ILI_dmac_channel_disable(ILI_SPI_DMAC_TX_CH);
-  DMAC->DMAC_CH_NUM[ILI_SPI_DMAC_TX_CH].DMAC_SADDR = (uint32_t)src;
-  DMAC->DMAC_CH_NUM[ILI_SPI_DMAC_TX_CH].DMAC_DADDR = (uint32_t)&SPI0->SPI_TDR;
-  DMAC->DMAC_CH_NUM[ILI_SPI_DMAC_TX_CH].DMAC_DSCR =  0;
-  DMAC->DMAC_CH_NUM[ILI_SPI_DMAC_TX_CH].DMAC_CTRLA = count |
-      DMAC_CTRLA_SRC_WIDTH_BYTE | DMAC_CTRLA_DST_WIDTH_BYTE;
-
-  DMAC->DMAC_CH_NUM[ILI_SPI_DMAC_TX_CH].DMAC_CTRLB =  DMAC_CTRLB_SRC_DSCR |
-      DMAC_CTRLB_DST_DSCR | DMAC_CTRLB_FC_MEM2PER_DMA_FC |
-      src_incr | DMAC_CTRLB_DST_INCR_FIXED;
-
-  DMAC->DMAC_CH_NUM[ILI_SPI_DMAC_TX_CH].DMAC_CFG = DMAC_CFG_DST_PER(ILI_SPI_TX_IDX) |
-      DMAC_CFG_DST_H2SEL | DMAC_CFG_SOD | DMAC_CFG_FIFOCFG_ALAP_CFG;
-
-  ILI_dmac_channel_enable(ILI_SPI_DMAC_TX_CH);
-}
-//------------------------------------------------------------------------------
-//  initialize SPI controller
-void ILI_SdSpi::init(uint8_t sckDivisor) {
-  uint8_t scbr = sckDivisor;
-  Spi* pSpi = SPI0;
-  //  disable SPI
-  pSpi->SPI_CR = SPI_CR_SPIDIS;
-  // reset SPI
-  pSpi->SPI_CR = SPI_CR_SWRST;
-  // no mode fault detection, set master mode
-  pSpi->SPI_MR = SPI_PCS(ILI_SPI_CHIP_SEL) | SPI_MR_MODFDIS | SPI_MR_MSTR;
-  // mode 0, 8-bit,
-  pSpi->SPI_CSR[ILI_SPI_CHIP_SEL] = SPI_CSR_SCBR(scbr) | SPI_CSR_NCPHA;
-  // enable SPI
-  pSpi->SPI_CR |= SPI_CR_SPIEN;
-}
-//------------------------------------------------------------------------------
-static inline uint8_t ILI_spiTransfer(uint8_t b) {
-  Spi* pSpi = SPI0;
-
-  pSpi->SPI_TDR = b;
-  while ((pSpi->SPI_SR & SPI_SR_RDRF) == 0) {}
-  b = pSpi->SPI_RDR;
-  return b;
-}
-//------------------------------------------------------------------------------
-/** SPI receive a byte */
-uint8_t ILI_SdSpi::receive() {
-  return ILI_spiTransfer(0XFF);
-}
-//------------------------------------------------------------------------------
-/** SPI receive multiple bytes */
-uint8_t ILI_SdSpi::receive(uint8_t* buf, size_t n) {
-  Spi* pSpi = SPI0;
-  int rtn = 0;
-#if ILI_USE_SAM3X_DMAC
-  // clear overrun error
-  uint32_t s = pSpi->SPI_SR;
-
-  ILI_spiDmaRX(buf, n);
-  ILI_spiDmaTX(0, n);
-
-  uint32_t m = millis();
-  while (!ILI_dmac_channel_transfer_done(ILI_SPI_DMAC_RX_CH)) {
-    if ((millis() - m) > ILI_SAM3X_DMA_TIMEOUT)  {
-      ILI_dmac_channel_disable(ILI_SPI_DMAC_RX_CH);
-      ILI_dmac_channel_disable(ILI_SPI_DMAC_TX_CH);
-      rtn = 2;
-      break;
-    }
-  }
-  if (pSpi->SPI_SR & SPI_SR_OVRES) rtn |= 1;
-#else  // ILI_USE_SAM3X_DMAC
-  for (size_t i = 0; i < n; i++) {
-    pSpi->SPI_TDR = 0XFF;
-    while ((pSpi->SPI_SR & SPI_SR_RDRF) == 0) {}
-    buf[i] = pSpi->SPI_RDR;
-  }
-#endif  // ILI_USE_SAM3X_DMAC
-  return rtn;
-}
-//------------------------------------------------------------------------------
-/** SPI send a byte */
-void ILI_SdSpi::send(uint8_t b) {
-  ILI_spiTransfer(b);
-}
-//------------------------------------------------------------------------------
-void ILI_SdSpi::send(const uint8_t* buf , size_t n) {
-  Spi* pSpi = SPI0;
-#if ILI_USE_SAM3X_DMAC
-  ILI_spiDmaTX(buf, n);
-  while (!ILI_dmac_channel_transfer_done(ILI_SPI_DMAC_TX_CH)) {}
-#else  // #if ILI_USE_SAM3X_DMAC
-  while ((pSpi->SPI_SR & SPI_SR_TXEMPTY) == 0) {}
-  for (size_t i = 0; i < n; i++) {
-    pSpi->SPI_TDR = buf[i];
-    while ((pSpi->SPI_SR & SPI_SR_TDRE) == 0) {}
-  }
-#endif  // #if ILI_USE_SAM3X_DMAC
-  while ((pSpi->SPI_SR & SPI_SR_TXEMPTY) == 0) {}
-  // leave RDR empty
-  uint8_t b = pSpi->SPI_RDR;
-}
-#endif  // ILI_USE_NATIVE_SAM3X_SPI
-
-//*********************************************************
-// STM32F1 section
-//*********************************************************
-
-#if ILI_USE_NATIVE_STM32F1_SPI
-#include <SPI.h>
-#include <libmaple/dma.h>
-/** Use SAM3X DMAC if nonzero */
-#define ILI_USE_STM32F1_DMAC 1
-/** Time in ms for DMA receive timeout */
-#define ILI_STM32F1_DMA_TIMEOUT 100
-/** chip select register number */
-#define ILI_SPI_CHIP_SEL 3
-/** DMAC receive channel */
-#define ILI_SPI_DMAC_RX_CH  DMA_CH2
-/** DMAC transmit channel */
-#define ILI_SPI_DMAC_TX_CH  DMA_CH3
-/** DMAC Channel HW Interface Number for SPI TX. */
-#define ILI_SPI_TX_IDX  1
-/** DMAC Channel HW Interface Number for SPI RX. */
-#define ILI_SPI_RX_IDX  2
-
-volatile bool SPI_DMA_TX_Active = false;
-volatile bool SPI_DMA_RX_Active = false;
-
-inline void SPI_DMA_TX_Event() {
-  SPI_DMA_TX_Active = false;
-  dma_disable(DMA1, DMA_CH3);
-}
-
-inline void SPI_DMA_RX_Event() {
-  SPI_DMA_RX_Active = false;
-  dma_disable(DMA1, DMA_CH2);
-}
-//------------------------------------------------------------------------------
-/** Disable DMA Controller. */
-//static void ILI_dmac_disable() {
-//  DMAC->DMAC_EN &= (~DMAC_EN_ENABLE);
-//}
-/** Enable DMA Controller. */
-//static void ILI_dmac_enable() {
-//  DMAC->DMAC_EN = DMAC_EN_ENABLE;
-//}
-/** Disable DMA Channel. */
-static void ILI_dmac_channel_disable(dma_channel ul_num) {
-  dma_disable(DMA1, ul_num);
-}
-/** Enable DMA Channel. */
-static void ILI_dmac_channel_enable(dma_channel ul_num) {
-  dma_enable(DMA1, ul_num);
-}
-/** Poll for transfer complete. */
-//static bool ILI_dmac_channel_transfer_done(dma_tube tube) {
-//    uint8 shift = (tube - 1) * 4;
-//    return ((DMA1->regs->ISR >> shift) & 0x02) ? false : true;
-
-//  return (DMAC->DMAC_CHSR & (DMAC_CHSR_ENA0 << ul_num)) ? false : true;
-//}
-//------------------------------------------------------------------------------
-void ILI_SdSpi::begin() {
-  SPI.begin();
-  SPI.setClockDivider(SPI_CLOCK_DIV2);
-  SPI.setBitOrder(MSBFIRST);
-  SPI.setDataMode(SPI_MODE0);
-  // DMA setup stuff. We use a line buffer and usa DMA for filling lines and blocks.
-
-
-
-#if ILI_USE_STM32F1_DMAC
-  dma_init(DMA1);
-  dma_attach_interrupt(DMA1, DMA_CH3, SPI_DMA_TX_Event);
-  dma_attach_interrupt(DMA1, DMA_CH2, SPI_DMA_RX_Event);
-  spi_tx_dma_enable(SPI1);
-  spi_rx_dma_enable(SPI1);
-
-
-#endif  // ILI_USE_STM32F1_DMAC
-}
-//------------------------------------------------------------------------------
-// start RX DMA
-
-static void ILI_spiDmaRX(uint8_t* dst, uint16_t count) {
-//  spi_rx_dma_enable(SPI1);
-  if (count < 1) return;
-  dma_setup_transfer(DMA1, DMA_CH2, &SPI1->regs->DR, DMA_SIZE_8BITS,
-                     dst, DMA_SIZE_8BITS, (DMA_MINC_MODE | DMA_TRNS_CMPLT));
-  dma_set_num_transfers(DMA1, DMA_CH2, count); // 2 bytes per pixel
-  SPI_DMA_RX_Active = true;
-  dma_enable(DMA1, DMA_CH2);
-
-
-}
-//------------------------------------------------------------------------------
-// start TX DMA
-static void ILI_spiDmaTX(uint8_t* src, uint16_t count) {
-  if (count < 1) return;
-  static uint8_t ff = 0XFF;
-//  spi_tx_dma_enable(SPI1);
-  //    dma_init(DMA1);
-  //    dma_attach_interrupt(DMA1, DMA_CH3, SPI_DMA_TX_Event);
-
-
-  if (!src) {
-    src = &ff;
-    dma_setup_transfer(DMA1, DMA_CH3, &SPI1->regs->DR, DMA_SIZE_8BITS,
-                       src, DMA_SIZE_8BITS, (DMA_FROM_MEM | DMA_TRNS_CMPLT));
-  }
-  else {
-    dma_setup_transfer(DMA1, DMA_CH3, &SPI1->regs->DR, DMA_SIZE_8BITS,
-                       src, DMA_SIZE_8BITS, (DMA_MINC_MODE  |  DMA_FROM_MEM | DMA_TRNS_CMPLT));
-  }
-  dma_set_num_transfers(DMA1, DMA_CH3, count); // 2 bytes per pixel
-  SPI_DMA_TX_Active = true;
-  dma_enable(DMA1, DMA_CH3);
-
-}
-//------------------------------------------------------------------------------
-//  initialize SPI controller STM32F1
-void ILI_SdSpi::init(uint8_t sckDivisor) {
-  SPI.setClockDivider(sckDivisor);
-  SPI.setBitOrder(MSBFIRST);
-  SPI.setDataMode(SPI_MODE0);
-  spi_tx_dma_enable(SPI1);
-  spi_rx_dma_enable(SPI1);
-
-}
-//------------------------------------------------------------------------------
-// STM32
-static inline uint8_t ILI_spiTransfer(uint8_t b) {
-  return SPI.transfer(b);
-}
-//------------------------------------------------------------------------------
-// should be valid for STM32
-/** SPI receive a byte */
-uint8_t ILI_SdSpi::receive() {
-  return ILI_spiTransfer(0xFF);
-}
-//------------------------------------------------------------------------------
-/** SPI receive multiple bytes */
-// check and finish.
-
-uint8_t ILI_SdSpi::receive(uint8_t* buf, size_t n) {
-  int rtn = 0;
-
-#if ILI_USE_STM32F1_DMAC
-  // clear overrun error
-  //  uint32_t s = pSpi->SPI_SR;
-  ILI_spiDmaRX(buf, n);
-  ILI_spiDmaTX(0, n);
-
-
-  uint32_t m = millis();
-  while (SPI_DMA_RX_Active) {
-    if ((millis() - m) > ILI_STM32F1_DMA_TIMEOUT)  {
-      ILI_dmac_channel_disable(ILI_SPI_DMAC_RX_CH);
-      ILI_dmac_channel_disable(ILI_SPI_DMAC_TX_CH);
-      rtn = 2;
-      break;
-    }
-  }
-  //  if (pSpi->SPI_SR & SPI_SR_OVRES) rtn |= 1;
-#else  // ILI_USE_STM32F1_DMAC
-  for (size_t i = 0; i < n; i++) {
-    buf[i] = SPI.transfer (0xFF);
-  }
-#endif  // ILI_USE_STM32F1_DMAC
-  return rtn;
-}
-//------------------------------------------------------------------------------
-/** SPI send a byte */
-void ILI_SdSpi::send(uint8_t b) {
-  ILI_spiTransfer(b);
-}
-//------------------------------------------------------------------------------
-void ILI_SdSpi::send(uint8_t* buf , size_t n) {
-
-#if ILI_USE_STM32F1_DMAC
-  ILI_spiDmaTX(buf, n);
-  while (SPI_DMA_TX_Active) {}
-
-  //  uint32_t m = millis();
-  //  while (SPI_DMA_TX_Active) {
-  //    if ((millis() - m) > ILI_STM32F1_DMA_TIMEOUT)  {
-  //      ILI_dmac_channel_disable(ILI_SPI_DMAC_TX_CH);
-  //      break;
-  //    }
-  //  }
-#else  // #if ILI_USE_STM32F1_DMAC
-  SPI.write (buf, n)
-#endif  // #if ILI_USE_STM32F1_DMAC
-  // leave RDR empty
-  //  uint8_t b = pSpi->SPI_RDR;
-}
-#endif  // ILI_USE_NATIVE_STM32F1_SPI
diff --git a/STM32F1/libraries/ILI9341_due_STM/README.md b/STM32F1/libraries/ILI9341_due_STM/README.md
deleted file mode 100644
index 5b52f7943..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/README.md
+++ /dev/null
@@ -1,48 +0,0 @@
-ILI9341_due
-===========
-
-Please see http://marekburiak.github.io/ILI9341_due
-
-
-Version History:
-```
-v0.94.000 - Added AVR compatibility, the library can now be also used on Uno, Mega and alike.
-			Please check the github.io page for more information (especially if you want to
-			use gText)
-v0.93.000 - Breaking changes:
-                - setRotation now needs iliRotation enum as a parameter (instead of an int)
-                - the meaning of some gText drawString parameters have changed 
-                  (event though the parameter type is the same)
-          - new additions:
-                - gText drawString with new parameters
-                - new gText drawStringOffseted, drawStringPivoted, drawStringPivotedOffseted 
-                  functions
-          - gText fontLetterSpacing default value is now 2 (previously 0)
-          - examples updated
-
-v0.92.002 - Fixed drawArc
-		  - Added setArcParams function to change maxArcAngle and arcAngleOffset at runtime
-
-v0.92.001 - Added fontHeight function in gText
-          - fixes for NORMAL and EXTENDED mode
-
-v0.92.000 - Added drawArc function for drawing arcs and circles with thickness and pies
-          - Added screenshotToConsole method and ILIScreenShotViewer app for taking 
-            screenshots from the display
-          - Added alignment options for drawString in ILI9341_due_gText
-	  
-v0.91.002 - Updated graphicstestWithStats example sketch so it does not use Streaming.h
-
-v0.91.001 - Performance improvements (especially fill circle)
-          - Fixed a scanline fill bug, clean up commented out code
-
-v0.91.000 - Added functions for controlling TFT power levels (sleep, idle, setPowerLevel)
-
-v0.90.026 - Fixed fillScreen after recent changes
-
-v0.90.025 - Added PushColors565 function
-          - Added BMP24toILI565 tool
-          - Updated sdFatTftBitmap example
-
-v0.90.010 - Initial version
-```
\ No newline at end of file
diff --git a/STM32F1/libraries/ILI9341_due_STM/examples/arcs/arcs.ino b/STM32F1/libraries/ILI9341_due_STM/examples/arcs/arcs.ino
deleted file mode 100644
index a1fe0597c..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/examples/arcs/arcs.ino
+++ /dev/null
@@ -1,243 +0,0 @@
-
-//#include <SPI.h>
-#include <SPI.h> 
-#include "ILI_SdSpi.h"
-#include "ILI_SdFatConfig.h"
-#include "ILI9341_due_gText.h"
-#include "ILI9341_due.h"
-#include "Arial_bold_14.h"
-#include "roboto16.h"
-#include "roboto32.h"
-#include "roboto70.h"
-
-#define TFT_DC 10
-#define TFT_CS 8
-#define rst  9
-
-// Use hardware SPI (on Uno, #13, #12, #11) and the above for CS/DC
-ILI9341_due tft = ILI9341_due(TFT_CS, TFT_DC, rst);
-
-char textBuff[20];
-
-ILI9341_due_gText t1(&tft);
-ILI9341_due_gText t2(&tft);
-ILI9341_due_gText t3(&tft);
-uint16_t colorLightGray = tft.color565(192,192,192);
-uint16_t colorGray = tft.color565(127,127,127);
-uint16_t colorDarkGray = tft.color565(64,64,64);
-
-void setup()
-{
-	Serial.begin(9600);
-	while (!Serial) ; // wait for Arduino Serial Monitor
-
-	tft.begin();
-	tft.setRotation(iliRotation270);
-
-	screenIntro();
-	delay(2000);
-	screenLoading();
-	screenClock();
-	screenPie();
-	delay(2000);
-	screenSensors();
-}
-
-void screenIntro()
-{
-	tft.fillScreen(ILI9341_BLUE);
-	t1.defineArea(100, 100, 220, 140);
-	t1.selectFont(Arial_bold_14);
-	t1.setFontLetterSpacing(5);
-	t1.setFontColor(ILI9341_WHITE, ILI9341_BLUE);
-	strcpy(textBuff, "Arcs demo");
-	t1.drawString(textBuff, gTextAlignMiddleCenter);
-}
-
-void screenLoading()
-{
-	const uint16_t x = 159;
-	const uint16_t y = 149;
-	tft.fillScreen(ILI9341_BLACK);
-	t1.selectFont(roboto32);
-	t1.setFontLetterSpacing(5);
-	t1.setFontColor(ILI9341_WHITE, ILI9341_BLACK);
-	t1.defineArea(100, 85, 220, 140);
-	strcpy(textBuff, "Loading...");
-	t1.drawString(textBuff, gTextAlignTopCenter, 0, 0);
-	tft.drawArc(x, y, 10, 5, 0, 360, colorLightGray);
-
-	for(int i=0; i<2880; i+=4)
-	{
-		tft.drawArc(x, y, 10, 5, (i >> 1)-45, (i >> 1)+45, colorDarkGray);
-		tft.drawArc(x, y, 10, 5, (i >> 1)-45-4, (i >> 1)-45, colorLightGray);
-
-		tft.drawArc(x, y, 20, 5, 1440-i-45, 1440-i+45, colorDarkGray);
-		tft.drawArc(x, y, 20, 5, 1440-i+45, 1440-i+45+4, colorLightGray);
-	}
-}
-
-void screenClock()
-{
-	const uint16_t x = 159;
-	const uint16_t y = 119;
-	tft.fillScreen(ILI9341_BLACK);
-	t1.selectFont(roboto70);
-	t1.setFontLetterSpacing(5);
-	t1.setFontColor(ILI9341_WHITE, ILI9341_BLACK);
-	t1.drawString("15:06", gTextAlignMiddleCenter);
-	tft.drawArc(x,y,102,11,0,225, colorLightGray);	// 15 hours
-	tft.drawArc(x,y,113,8,0,36, colorGray);	// 6 minutes
-	tft.drawArc(x,y,120,5,0,360, colorDarkGray);	// seconds
-
-	for(uint16_t d=324; d<372; d++)
-	{
-		tft.drawArc(x,y,120,5,d-1,d+1, ILI9341_RED);
-		tft.drawArc(x,y,120,5,d-2,d-1, colorDarkGray);	// to erase the red
-		if(d == 360)
-		{
-			t1.drawString("15:07", gTextAlignMiddleCenter);
-			tft.drawArc(x,y,113,8,0,42, colorGray);	// 7 minutes
-		}
-		delay(166);
-	}
-}
-
-void screenPie()
-{
-	const uint16_t x = 159;
-	const uint16_t y = 119;
-	const uint16_t radius = 80;
-
-	tft.fillScreen(ILI9341_BLACK);
-	t1.selectFont(roboto16);
-	t1.setFontLetterSpacing(2);
-	tft.drawArc(x+3,y-2,radius,radius,0,60, tft.color565(198,255,13));
-	tft.drawArc(x-3,y+7,radius+10,radius+10,60,340, tft.color565(255,0,54));
-	tft.drawArc(x-2,y-3,radius,radius,340,360, tft.color565(0,255,241));
-
-	t1.defineArea(0,0,220,180);
-	t1.selectFont(roboto16);
-	t1.setFontMode(gTextFontMode_Transparent);
-	t1.setFontColor(ILI9341_BLACK);
-	t1.drawString("16%",175,70);
-	t1.drawString("78%",140,150);
-	t1.setFontColor(colorLightGray);
-	t1.drawString("6%",132,18);
-	delay(2000);
-}
-
-void screenSensors()
-{
-	const uint16_t radius = 55;
-	float temp=22.4;
-	uint16_t hum=73, lux=1154;
-
-	const uint16_t s1x = 0;
-	const uint16_t s1y = 10;
-
-	const uint16_t s2x = 110;
-	const uint16_t s2y = 70;
-
-	const uint16_t s3x = 210;
-	const uint16_t s3y = 130;
-
-	tft.fillScreen(ILI9341_BLACK);
-
-	t1.setFontMode(gTextFontMode_Solid);
-	t1.setFontLetterSpacing(3);
-	t2.setFontMode(gTextFontMode_Solid);
-	t2.setFontLetterSpacing(3);
-	t3.setFontMode(gTextFontMode_Solid);
-	t3.setFontLetterSpacing(3);
-
-	t1.defineArea(s1x,s1y,s1x+2*radius,s1y+2*radius);	
-	t2.defineArea(s2x,s2y,s2x+2*radius,s2y+2*radius);	
-	t3.defineArea(s3x,s3y,s3x+2*radius,s3y+2*radius);	
-
-	t1.setFontColor(ILI9341_WHITE);
-	tft.drawArc(s1x+radius,s1y+radius,radius,10,-3,3, tft.color565(127,0,27));
-	t1.selectFont(roboto16);
-	t1.drawStringOffseted("C", gTextAlignMiddleCenter, 0, 25);
-	t1.selectFont(roboto32);
-	sprintf(textBuff, "%4.1f", temp);
-	t1.drawString(textBuff, gTextAlignMiddleCenter);
-	tft.fillRect(s1x+radius-7,s1y+radius+17,2,2,ILI9341_WHITE);	// degrees symbol
-
-	for(uint16_t d=1; d<temp*10; d++)
-	{
-		tft.drawArc(s1x+radius,s1y+radius,radius,10,d,d+3, tft.color565(127,0,27));
-		tft.drawArc(s1x+radius,s1y+radius,radius-3,4,d-1,d, tft.color565(255,0,54));
-	}
-
-	t2.setFontColor(ILI9341_WHITE);
-	tft.drawArc(s2x+radius,s2y+radius,radius,10,-3,3, tft.color565(0,43,127));
-	t2.selectFont(roboto16);	
-	t2.drawStringOffseted("%", gTextAlignMiddleCenter, 0, 25);
-	t2.selectFont(roboto32);
-	sprintf(textBuff, "%d", hum);
-	t2.drawString(textBuff, gTextAlignMiddleCenter);
-
-	for(uint16_t d=1; d<263; d++)
-	{
-		tft.drawArc(s2x+radius,s2y+radius,radius,10,d,d+3, tft.color565(0,43,127));
-		tft.drawArc(s2x+radius,s2y+radius,radius-3,4,d-1,d, tft.color565(0,86,255));
-	}
-
-	t3.setFontColor(ILI9341_WHITE);
-	tft.drawArc(s3x+radius,s3y+radius,radius,10,-3,3, tft.color565(127,103,6));
-	t3.selectFont(roboto16);
-	t3.drawStringOffseted("lux", gTextAlignMiddleCenter, 0, 25);
-	t3.selectFont(roboto32);
-	sprintf(textBuff, "%d", lux);
-	t3.drawString(textBuff, gTextAlignMiddleCenter);
-
-	for(uint16_t d=1; d<42; d++)
-	{
-		tft.drawArc(s3x+radius,s3y+radius,radius,10,d,d+3, tft.color565(127,103,6));
-		tft.drawArc(s3x+radius,s3y+radius,radius-3,4,d-1,d,  tft.color565(255,206,13));
-	}
-
-	delay(1000);
-	for(uint16_t d=1; d<660; d++)
-	{
-		if(d<220 )
-		{
-			lux+=21;
-
-			sprintf(textBuff, "%d", lux);
-			t3.drawString(textBuff, gTextAlignMiddleCenter, 3, 3);
-			tft.drawArc(s3x+radius,s3y+radius,radius,10, ((float)lux/(float)10000)*360,((float)lux/(float)10000)*360+3, tft.color565(127,103,6));
-			tft.drawArc(s3x+radius,s3y+radius,radius-3,4,((float)lux/(float)10000)*360-4,((float)lux/(float)10000)*360, tft.color565(255,206,13));
-		}
-
-		if(d == 220)
-			delay(1000);
-
-		if(d>220 && d % 15 == 0)
-		{
-			temp+=0.1;
-			sprintf(textBuff, "%4.1f", temp);
-			t1.drawString(textBuff, gTextAlignMiddleCenter, 3, 3);
-			tft.drawArc(s1x+radius,s1y+radius,radius,10,temp*10,temp*10+3, tft.color565(127,0,27));
-			tft.drawArc(s1x+radius,s1y+radius,radius-3,4,temp*10-2,temp*10, tft.color565(255,0,54));
-			delay(random(350, 700));
-		}
-		if(d>300 && d<600 && d % 38 == 0)
-		{
-			hum+=1;
-			sprintf(textBuff, "%d", hum);
-			t2.drawString(textBuff, gTextAlignMiddleCenter, 3, 3);
-			tft.drawArc(s2x+radius,s2y+radius,radius,10,(float)hum*3.6-4,(float)hum*3.6+3, tft.color565(0,43,127));
-			tft.drawArc(s2x+radius,s2y+radius,radius-3,4,(float)hum*3.6-5,(float)hum*3.6, tft.color565(0,86,255));
-		}
-	}
-}
-
-
-void loop()
-{
-  setup ();
-	/* add main program code here */
-
-}
diff --git a/STM32F1/libraries/ILI9341_due_STM/examples/arcs/roboto16.h b/STM32F1/libraries/ILI9341_due_STM/examples/arcs/roboto16.h
deleted file mode 100644
index 89b83c62f..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/examples/arcs/roboto16.h
+++ /dev/null
@@ -1,167 +0,0 @@
-
-
-/*
- *
- * roboto16
- *
- * created with FontCreator
- * written by F. Maximilian Thiele
- *
- * http://www.apetech.de/fontCreator
- * me@apetech.de
- *
- * File Name           : roboto16.h
- * Date                : 18.09.2014
- * Font size in bytes  : 10574
- * Font width          : 10
- * Font height         : 17
- * Font first char     : 32
- * Font last char      : 145
- * Font used chars     : 113
- *
- * The font data are defined as
- *
- * struct _FONT_ {
- *     uint16_t   font_Size_in_Bytes_over_all_included_Size_it_self;
- *     uint8_t    font_Width_in_Pixel_for_fixed_drawing;
- *     uint8_t    font_Height_in_Pixel_for_all_characters;
- *     unit8_t    font_First_Char;
- *     uint8_t    font_Char_Count;
- *
- *     uint8_t    font_Char_Widths[font_Last_Char - font_First_Char +1];
- *                  // for each character the separate width in pixels,
- *                  // characters < 128 have an implicit virtual right empty row
- *
- *     uint8_t    font_data[];
- *                  // bit field of all characters
- */
-
-#include <inttypes.h>
-#include <avr/pgmspace.h>
-
-#ifndef ROBOTO16_H
-#define ROBOTO16_H
-
-#define ROBOTO16_WIDTH 10
-#define ROBOTO16_HEIGHT 17
-
-static const uint8_t roboto16[] PROGMEM = {
-    0x29, 0x4E, // size
-    0x0A, // width
-    0x11, // height
-    0x20, // first char
-    0x71, // char count
-    
-    // char widths
-    0x00, 0x01, 0x03, 0x08, 0x07, 0x0A, 0x08, 0x01, 0x04, 0x04, 
-    0x07, 0x07, 0x02, 0x04, 0x01, 0x06, 0x07, 0x03, 0x07, 0x07, 
-    0x08, 0x07, 0x07, 0x07, 0x07, 0x07, 0x01, 0x02, 0x06, 0x07, 
-    0x07, 0x06, 0x0D, 0x0A, 0x08, 0x08, 0x09, 0x08, 0x08, 0x09, 
-    0x09, 0x01, 0x06, 0x09, 0x07, 0x0B, 0x09, 0x09, 0x08, 0x09, 
-    0x09, 0x08, 0x09, 0x08, 0x0A, 0x0D, 0x09, 0x09, 0x08, 0x03, 
-    0x06, 0x03, 0x05, 0x07, 0x03, 0x07, 0x07, 0x07, 0x07, 0x07, 
-    0x04, 0x07, 0x07, 0x01, 0x02, 0x07, 0x01, 0x0C, 0x07, 0x07, 
-    0x07, 0x07, 0x04, 0x06, 0x05, 0x07, 0x08, 0x0B, 0x07, 0x08, 
-    0x06, 0x04, 0x01, 0x05, 0x09, 0x00, 0x00, 0x00, 0x00, 0x00, 
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 
-    0x00, 0x00, 0x00, 
-    
-    // font data
-    0xFC, 0x11, 0x00, // 33
-    0x1E, 0x10, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 34
-    0x20, 0x20, 0xF8, 0x24, 0x20, 0xE0, 0x3C, 0x20, 0x02, 0x1E, 0x03, 0x02, 0x1E, 0x03, 0x02, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 35
-    0x38, 0x44, 0x44, 0x83, 0x84, 0x04, 0x18, 0x0C, 0x10, 0x10, 0x70, 0x10, 0x11, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 36
-    0x3C, 0x44, 0x42, 0x3C, 0x80, 0x40, 0x30, 0x08, 0x00, 0x00, 0x00, 0x00, 0x08, 0x06, 0x01, 0x0E, 0x11, 0x11, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 37
-    0x00, 0xBC, 0x44, 0xC2, 0x24, 0x1C, 0x00, 0x00, 0x0F, 0x10, 0x10, 0x10, 0x13, 0x14, 0x08, 0x17, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 38
-    0x0E, 0x00, 0x00, // 39
-    0xE0, 0x1C, 0x02, 0x01, 0x0F, 0x30, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x80, // 40
-    0x01, 0x06, 0x18, 0xE0, 0x00, 0xC0, 0x30, 0x0F, 0x80, 0x00, 0x00, 0x00, // 41
-    0x10, 0x90, 0x50, 0x3C, 0x50, 0x90, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 42
-    0x80, 0x80, 0x80, 0xF0, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 43
-    0x00, 0x00, 0x40, 0x70, 0x00, 0x00, // 44
-    0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, // 45
-    0x00, 0x10, 0x00, // 46
-    0x00, 0x00, 0x00, 0xE0, 0x1C, 0x04, 0x20, 0x1C, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 47
-    0xF8, 0x04, 0x04, 0x02, 0x04, 0x04, 0xF8, 0x07, 0x18, 0x10, 0x10, 0x10, 0x18, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 48
-    0x04, 0x04, 0xFC, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, // 49
-    0x18, 0x04, 0x04, 0x02, 0x84, 0x6C, 0x10, 0x10, 0x18, 0x14, 0x13, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 50
-    0x18, 0x04, 0x84, 0x82, 0x84, 0xC4, 0x38, 0x0C, 0x10, 0x10, 0x10, 0x10, 0x10, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 51
-    0x00, 0x80, 0x60, 0x10, 0x0C, 0xFC, 0x00, 0x00, 0x03, 0x02, 0x02, 0x02, 0x02, 0x1F, 0x02, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 52
-    0xC0, 0xBC, 0x44, 0x44, 0x44, 0x44, 0x84, 0x04, 0x18, 0x10, 0x10, 0x10, 0x10, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 53
-    0xF0, 0x4C, 0x44, 0x24, 0x42, 0x44, 0x80, 0x07, 0x08, 0x10, 0x10, 0x10, 0x10, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 54
-    0x04, 0x04, 0x04, 0xC4, 0x24, 0x1C, 0x04, 0x00, 0x00, 0x1E, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 55
-    0x38, 0xC4, 0x84, 0x82, 0x84, 0xC4, 0x38, 0x0F, 0x10, 0x10, 0x10, 0x10, 0x10, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 56
-    0xF8, 0x04, 0x04, 0x02, 0x04, 0x8C, 0xF0, 0x00, 0x11, 0x11, 0x12, 0x11, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 57
-    0x20, 0x10, 0x00, // 58
-    0x00, 0x20, 0x40, 0x70, 0x00, 0x00, // 59
-    0x80, 0x80, 0x40, 0x40, 0x20, 0x20, 0x01, 0x01, 0x02, 0x02, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 60
-    0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 61
-    0x20, 0x20, 0x40, 0x40, 0x80, 0x80, 0x80, 0x04, 0x04, 0x02, 0x02, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 62
-    0x0C, 0x04, 0x02, 0x84, 0x6C, 0x10, 0x00, 0x00, 0x13, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 63
-    0xC0, 0x30, 0x08, 0x08, 0x84, 0x44, 0x24, 0x24, 0xC4, 0x04, 0x08, 0x30, 0xC0, 0x1F, 0x60, 0x80, 0x8F, 0x10, 0x10, 0x10, 0x08, 0x9F, 0x10, 0x10, 0x0C, 0x03, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, // 64
-    0x00, 0x00, 0x80, 0x70, 0x0C, 0x0C, 0x70, 0x80, 0x00, 0x00, 0x10, 0x0C, 0x03, 0x02, 0x02, 0x02, 0x02, 0x03, 0x0C, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 65
-    0xFC, 0x84, 0x84, 0x84, 0x84, 0xC4, 0xEC, 0x10, 0x1F, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 66
-    0xF0, 0x08, 0x04, 0x04, 0x02, 0x04, 0x04, 0x18, 0x07, 0x08, 0x10, 0x10, 0x10, 0x10, 0x10, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 67
-    0xFC, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x18, 0xE0, 0x1F, 0x10, 0x10, 0x10, 0x10, 0x10, 0x08, 0x06, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 68
-    0xFC, 0x84, 0x84, 0x84, 0x84, 0x84, 0x84, 0x04, 0x1F, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 69
-    0xFC, 0x84, 0x84, 0x84, 0x84, 0x84, 0x84, 0x04, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 70
-    0xF0, 0x08, 0x04, 0x04, 0x02, 0x04, 0x04, 0x0C, 0x10, 0x03, 0x0C, 0x10, 0x10, 0x10, 0x11, 0x11, 0x11, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 71
-    0xFC, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0xFC, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 72
-    0xFC, 0x1F, 0x00, // 73
-    0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x0C, 0x10, 0x10, 0x10, 0x10, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 74
-    0xFC, 0x80, 0x80, 0xC0, 0x20, 0x10, 0x08, 0x04, 0x04, 0x1F, 0x00, 0x00, 0x00, 0x01, 0x02, 0x0C, 0x18, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 75
-    0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 76
-    0xFC, 0x04, 0x38, 0xC0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x18, 0xFC, 0x1F, 0x00, 0x00, 0x00, 0x07, 0x18, 0x0C, 0x03, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 77
-    0xFC, 0x04, 0x18, 0x20, 0xC0, 0x00, 0x00, 0x00, 0xFC, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x01, 0x06, 0x08, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 78
-    0xF0, 0x08, 0x04, 0x04, 0x02, 0x04, 0x04, 0x08, 0xF0, 0x07, 0x08, 0x10, 0x10, 0x10, 0x10, 0x10, 0x0C, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 79
-    0xFC, 0x84, 0x84, 0x84, 0x84, 0x84, 0x84, 0x78, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 80
-    0xF0, 0x08, 0x04, 0x04, 0x02, 0x04, 0x04, 0x08, 0xF0, 0x07, 0x08, 0x10, 0x10, 0x10, 0x10, 0x10, 0x2C, 0x43, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 81
-    0xFC, 0x84, 0x84, 0x84, 0x84, 0x84, 0x44, 0x38, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x1F, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 82
-    0x38, 0x44, 0x44, 0x82, 0x82, 0x84, 0x04, 0x18, 0x0C, 0x10, 0x10, 0x10, 0x10, 0x10, 0x11, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 83
-    0x04, 0x04, 0x04, 0x04, 0xFC, 0x04, 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 84
-    0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0x07, 0x08, 0x10, 0x10, 0x10, 0x10, 0x10, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 85
-    0x04, 0x1C, 0xE0, 0x00, 0x00, 0x00, 0x80, 0x60, 0x1C, 0x04, 0x00, 0x00, 0x00, 0x03, 0x1C, 0x1C, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 86
-    0x3C, 0xC0, 0x00, 0x00, 0xE0, 0x1C, 0x1C, 0xE0, 0x00, 0x00, 0x80, 0x78, 0x04, 0x00, 0x03, 0x1C, 0x0E, 0x01, 0x00, 0x00, 0x00, 0x07, 0x18, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 87
-    0x00, 0x04, 0x08, 0x30, 0xC0, 0xC0, 0x30, 0x08, 0x04, 0x10, 0x18, 0x0C, 0x02, 0x01, 0x01, 0x02, 0x0C, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 88
-    0x04, 0x0C, 0x30, 0x40, 0x80, 0x80, 0x60, 0x18, 0x04, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 89
-    0x04, 0x04, 0x04, 0x84, 0x64, 0x14, 0x0C, 0x04, 0x18, 0x14, 0x13, 0x10, 0x10, 0x10, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 90
-    0xFF, 0x01, 0x01, 0x7F, 0x40, 0x40, 0x00, 0x00, 0x00, // 91
-    0x04, 0x1C, 0x60, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x1C, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 92
-    0x01, 0x01, 0xFF, 0x40, 0x40, 0x7F, 0x00, 0x00, 0x00, // 93
-    0x60, 0x18, 0x0C, 0x30, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 94
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 95
-    0x02, 0x0C, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 96
-    0x40, 0x20, 0x10, 0x10, 0x20, 0xE0, 0x00, 0x1E, 0x12, 0x11, 0x11, 0x11, 0x1F, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 97
-    0xFE, 0x20, 0x20, 0x10, 0x10, 0x20, 0xC0, 0x1F, 0x08, 0x10, 0x10, 0x10, 0x18, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 98
-    0xC0, 0x20, 0x10, 0x10, 0x20, 0x60, 0x80, 0x0F, 0x10, 0x10, 0x10, 0x10, 0x08, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 99
-    0xC0, 0x20, 0x10, 0x10, 0x20, 0x40, 0xFE, 0x0F, 0x10, 0x10, 0x10, 0x10, 0x08, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 100
-    0xC0, 0x20, 0x10, 0x10, 0x20, 0x60, 0x80, 0x0F, 0x19, 0x11, 0x11, 0x11, 0x19, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 101
-    0x20, 0xFE, 0x22, 0x22, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 102
-    0xC0, 0x20, 0x10, 0x10, 0x20, 0x40, 0xE0, 0x0F, 0x90, 0x90, 0x90, 0x90, 0xC8, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 103
-    0xFE, 0x20, 0x20, 0x10, 0x10, 0x20, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 104
-    0xE2, 0x1F, 0x00, // 105
-    0x00, 0xE2, 0x80, 0xFF, 0x00, 0x00, // 106
-    0xFE, 0x00, 0x00, 0x80, 0x60, 0x20, 0x00, 0x1F, 0x01, 0x01, 0x02, 0x0C, 0x18, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 107
-    0xFE, 0x1F, 0x00, // 108
-    0xE0, 0x20, 0x20, 0x10, 0x10, 0x60, 0xC0, 0x20, 0x10, 0x10, 0x20, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 109
-    0xE0, 0x20, 0x20, 0x10, 0x10, 0x20, 0xC0, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 110
-    0xC0, 0x20, 0x20, 0x10, 0x20, 0x20, 0xC0, 0x0F, 0x18, 0x10, 0x10, 0x10, 0x18, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 111
-    0xE0, 0x20, 0x20, 0x10, 0x10, 0x20, 0xC0, 0xFF, 0x08, 0x10, 0x10, 0x10, 0x18, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 112
-    0xC0, 0x20, 0x10, 0x10, 0x20, 0x40, 0xE0, 0x0F, 0x10, 0x10, 0x10, 0x10, 0x08, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 113
-    0xE0, 0x20, 0x20, 0x10, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 114
-    0xE0, 0x20, 0x10, 0x10, 0x20, 0x60, 0x08, 0x11, 0x11, 0x11, 0x12, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 115
-    0x20, 0x20, 0xFC, 0x20, 0x00, 0x00, 0x00, 0x1F, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 116
-    0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x07, 0x18, 0x10, 0x10, 0x10, 0x08, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 117
-    0x20, 0xE0, 0x00, 0x00, 0x00, 0x80, 0x60, 0x20, 0x00, 0x00, 0x03, 0x1C, 0x1C, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 118
-    0xE0, 0x00, 0x00, 0x00, 0xE0, 0xE0, 0x00, 0x00, 0x00, 0xE0, 0x20, 0x00, 0x0F, 0x18, 0x07, 0x00, 0x00, 0x07, 0x18, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 119
-    0x00, 0x20, 0x40, 0x80, 0x80, 0x40, 0x20, 0x10, 0x18, 0x0C, 0x03, 0x03, 0x0C, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 120
-    0x20, 0xE0, 0x00, 0x00, 0x00, 0x80, 0x60, 0x20, 0x00, 0x80, 0x83, 0x7C, 0x1C, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 121
-    0x20, 0x20, 0x20, 0xA0, 0x60, 0x20, 0x18, 0x14, 0x13, 0x11, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 122
-    0x00, 0xF8, 0x06, 0x02, 0x01, 0x3E, 0x40, 0x80, 0x00, 0x00, 0x00, 0x00, // 123
-    0xFC, 0x7F, 0x00, // 124
-    0x02, 0x02, 0xFC, 0x00, 0x00, 0x80, 0x80, 0x7E, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, // 125
-    0x00, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x80, 0x01, 0x00, 0x00, 0x00, 0x01, 0x02, 0x02, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 126
-    
-};
-
-#endif
diff --git a/STM32F1/libraries/ILI9341_due_STM/examples/arcs/roboto32.h b/STM32F1/libraries/ILI9341_due_STM/examples/arcs/roboto32.h
deleted file mode 100644
index 396469929..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/examples/arcs/roboto32.h
+++ /dev/null
@@ -1,165 +0,0 @@
-
-
-/*
- *
- * roboto32
- *
- * created with FontCreator
- * written by F. Maximilian Thiele
- *
- * http://www.apetech.de/fontCreator
- * me@apetech.de
- *
- * File Name           : roboto32.h
- * Date                : 18.09.2014
- * Font size in bytes  : 40065
- * Font width          : 10
- * Font height         : 33
- * Font first char     : 32
- * Font last char      : 128
- * Font used chars     : 96
- *
- * The font data are defined as
- *
- * struct _FONT_ {
- *     uint16_t   font_Size_in_Bytes_over_all_included_Size_it_self;
- *     uint8_t    font_Width_in_Pixel_for_fixed_drawing;
- *     uint8_t    font_Height_in_Pixel_for_all_characters;
- *     unit8_t    font_First_Char;
- *     uint8_t    font_Char_Count;
- *
- *     uint8_t    font_Char_Widths[font_Last_Char - font_First_Char +1];
- *                  // for each character the separate width in pixels,
- *                  // characters < 128 have an implicit virtual right empty row
- *
- *     uint8_t    font_data[];
- *                  // bit field of all characters
- */
-
-#include <inttypes.h>
-#include <avr/pgmspace.h>
-
-#ifndef ROBOTO32_H
-#define ROBOTO32_H
-
-#define ROBOTO32_WIDTH 10
-#define ROBOTO32_HEIGHT 33
-
-static const uint8_t roboto32[] PROGMEM = {
-    0x9C, 0x81, // size
-    0x0A, // width
-    0x21, // height
-    0x20, // first char
-    0x60, // char count
-    
-    // char widths
-    0x00, 0x03, 0x05, 0x11, 0x0E, 0x14, 0x12, 0x02, 0x08, 0x08, 
-    0x0D, 0x10, 0x03, 0x07, 0x02, 0x0C, 0x0E, 0x08, 0x0E, 0x0E, 
-    0x10, 0x0D, 0x0E, 0x0F, 0x0E, 0x0F, 0x02, 0x04, 0x0D, 0x0D, 
-    0x0D, 0x0C, 0x19, 0x13, 0x0F, 0x11, 0x10, 0x0E, 0x0F, 0x11, 
-    0x11, 0x02, 0x0E, 0x11, 0x0D, 0x16, 0x11, 0x12, 0x0F, 0x12, 
-    0x10, 0x11, 0x11, 0x10, 0x12, 0x1B, 0x12, 0x12, 0x11, 0x05, 
-    0x0B, 0x05, 0x0B, 0x0E, 0x06, 0x0D, 0x0E, 0x0D, 0x0D, 0x0E, 
-    0x0A, 0x0D, 0x0D, 0x02, 0x05, 0x0E, 0x02, 0x18, 0x0D, 0x0F, 
-    0x0E, 0x0D, 0x09, 0x0C, 0x08, 0x0D, 0x0E, 0x16, 0x0E, 0x0E, 
-    0x0E, 0x09, 0x01, 0x09, 0x12, 0x00, 
-    
-    // font data
-    0x00, 0xF8, 0xF8, 0x00, 0xFF, 0xFF, 0x80, 0x87, 0x87, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00, // 33
-    0xFC, 0x1C, 0x00, 0x00, 0xFC, 0x01, 0x00, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 34
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xF8, 0x08, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x78, 0x00, 0x00, 0x00, 0x04, 0x04, 0x04, 0x04, 0xF4, 0x7F, 0x05, 0x04, 0x04, 0x04, 0xC4, 0xFE, 0x0F, 0x04, 0x04, 0x04, 0x0C, 0x0C, 0x0C, 0xCC, 0xFE, 0x0F, 0x0C, 0x0C, 0x0C, 0x0C, 0xFC, 0x7F, 0x0D, 0x0C, 0x0C, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x02, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 35
-    0x00, 0xC0, 0xF0, 0x30, 0x18, 0x18, 0x1F, 0x1F, 0x18, 0x18, 0x30, 0x70, 0xE0, 0x80, 0x00, 0x0F, 0x1E, 0x30, 0x30, 0x60, 0x60, 0xC0, 0xC0, 0x80, 0x80, 0x00, 0x03, 0x03, 0x78, 0xF8, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x83, 0xFF, 0x7C, 0x00, 0x00, 0x01, 0x03, 0x03, 0x03, 0x1E, 0x1E, 0x02, 0x03, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 36
-    0xE0, 0x30, 0x18, 0x08, 0x08, 0x18, 0x10, 0xF0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x1C, 0x10, 0x30, 0x10, 0x10, 0x18, 0x0F, 0x03, 0x80, 0xE0, 0x38, 0x0C, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xE0, 0x38, 0x0C, 0x07, 0x01, 0x00, 0xF8, 0xFE, 0x03, 0x01, 0x01, 0x01, 0x03, 0xCE, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x02, 0x02, 0x02, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 37
-    0x00, 0x00, 0x00, 0xE0, 0x70, 0x18, 0x18, 0x18, 0x18, 0x18, 0x30, 0xF0, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x87, 0xDE, 0x78, 0x60, 0xF0, 0x98, 0x0C, 0x06, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0xFE, 0xC7, 0x81, 0x00, 0x00, 0x00, 0x00, 0x03, 0x07, 0x0E, 0x1C, 0xB0, 0xE0, 0xF0, 0xBF, 0x0F, 0x00, 0x00, 0x00, 0x01, 0x01, 0x03, 0x03, 0x02, 0x02, 0x02, 0x03, 0x03, 0x01, 0x01, 0x00, 0x01, 0x03, 0x03, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 38
-    0xFC, 0x0C, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 39
-    0x00, 0x00, 0xC0, 0xF0, 0x38, 0x0C, 0x07, 0x02, 0xE0, 0xFE, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0xFF, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x0F, 0x1C, 0x70, 0xC0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, // 40
-    0x03, 0x06, 0x0C, 0x38, 0xF0, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0xFE, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x1F, 0x00, 0x80, 0xC0, 0x70, 0x1C, 0x0F, 0x01, 0x00, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 41
-    0x00, 0x80, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x80, 0x02, 0x01, 0x81, 0xE3, 0x73, 0x1A, 0x0F, 0x0F, 0x3A, 0x63, 0xC3, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 42
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xFF, 0xFF, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 43
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x20, 0x3F, 0x0F, 0x00, 0x00, 0x00, // 44
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 45
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, // 46
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xF0, 0x38, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xF0, 0x3C, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0xF0, 0x3E, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x08, 0x0E, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 47
-    0x00, 0xC0, 0x70, 0x30, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x30, 0xE0, 0xC0, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x3F, 0xFF, 0xC0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xE0, 0x7F, 0x1F, 0x00, 0x00, 0x01, 0x03, 0x03, 0x02, 0x02, 0x02, 0x02, 0x03, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 48
-    0x20, 0x30, 0x30, 0x30, 0x10, 0x10, 0xF8, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 49
-    0xC0, 0xE0, 0x30, 0x10, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x30, 0xE0, 0xC0, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0x70, 0x3F, 0x0F, 0x00, 0x00, 0x80, 0xC0, 0x60, 0x30, 0x1C, 0x0E, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 50
-    0xC0, 0xE0, 0x70, 0x30, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x30, 0xF0, 0xC0, 0x00, 0x01, 0x01, 0x00, 0x00, 0x40, 0x40, 0x40, 0x40, 0x60, 0xE0, 0xB0, 0x9F, 0x0F, 0x00, 0x70, 0xE0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC3, 0xFF, 0x3C, 0x00, 0x01, 0x01, 0x03, 0x03, 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 51
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xE0, 0x38, 0xF8, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0x70, 0x38, 0x0E, 0x07, 0x01, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x08, 0x0E, 0x0B, 0x09, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0x08, 0xFF, 0xFF, 0x08, 0x08, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 52
-    0x00, 0xF8, 0xF8, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x00, 0xFC, 0xFF, 0x20, 0x30, 0x10, 0x10, 0x18, 0x18, 0x30, 0x30, 0x60, 0xE0, 0x80, 0xF0, 0xE0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0x3F, 0x00, 0x01, 0x01, 0x03, 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 53
-    0x00, 0x80, 0xE0, 0x70, 0x30, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x10, 0x00, 0x00, 0xFC, 0xFF, 0x61, 0x30, 0x10, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x30, 0xE0, 0xC0, 0x0F, 0x7F, 0xF0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xF1, 0x7F, 0x00, 0x00, 0x00, 0x01, 0x03, 0x03, 0x02, 0x02, 0x02, 0x03, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 54
-    0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x98, 0xD8, 0x78, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xF0, 0x3C, 0x0F, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFE, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 55
-    0x80, 0xE0, 0x70, 0x30, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x30, 0xF0, 0xE0, 0x00, 0x07, 0x1F, 0xB8, 0xB0, 0xE0, 0x60, 0x40, 0x60, 0x60, 0xE0, 0xB0, 0x9C, 0x0F, 0x03, 0xFE, 0xE7, 0x81, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x81, 0xFF, 0x7E, 0x00, 0x01, 0x01, 0x03, 0x03, 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 56
-    0x00, 0xC0, 0xE0, 0x70, 0x30, 0x18, 0x18, 0x18, 0x18, 0x18, 0x10, 0x70, 0xE0, 0xC0, 0x00, 0x1E, 0xFF, 0xE1, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC1, 0xFF, 0xFC, 0x00, 0x00, 0x01, 0x03, 0x03, 0x06, 0x06, 0x06, 0x06, 0x02, 0x03, 0x81, 0xF0, 0x7F, 0x07, 0x00, 0x00, 0x01, 0x03, 0x03, 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 57
-    0x00, 0x00, 0x0C, 0x0C, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, // 58
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x0C, 0x00, 0x80, 0x80, 0x00, 0x20, 0x3F, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, // 59
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0xC0, 0x60, 0x60, 0x20, 0x30, 0x30, 0x18, 0x18, 0x0C, 0x0C, 0x06, 0x01, 0x01, 0x03, 0x03, 0x02, 0x06, 0x04, 0x0C, 0x0C, 0x18, 0x18, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 60
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 61
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x0C, 0x0C, 0x08, 0x18, 0x10, 0x30, 0x30, 0x60, 0x60, 0x40, 0xC0, 0x80, 0x30, 0x30, 0x18, 0x18, 0x0C, 0x0C, 0x04, 0x06, 0x06, 0x03, 0x03, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 62
-    0xC0, 0xE0, 0x70, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x30, 0xF0, 0xC0, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0xE0, 0x70, 0x1F, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0F, 0x0F, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 63
-    0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0x40, 0x60, 0x20, 0x30, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x30, 0x20, 0x60, 0x40, 0xC0, 0x80, 0x00, 0x00, 0xC0, 0xF8, 0x1C, 0x07, 0x01, 0x00, 0x00, 0x00, 0xC0, 0x70, 0x30, 0x18, 0x08, 0x08, 0x08, 0x18, 0xF0, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0E, 0xF8, 0xFF, 0xC3, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xCF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x60, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xE0, 0x3F, 0x01, 0x07, 0x1C, 0x30, 0x60, 0xC0, 0xC0, 0x80, 0x83, 0x03, 0x02, 0x02, 0x02, 0x03, 0x81, 0x80, 0x81, 0x83, 0x02, 0x02, 0x02, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 64
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x78, 0x78, 0xE0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x7C, 0x1F, 0x03, 0x00, 0x00, 0x01, 0x0F, 0x7C, 0xE0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x7C, 0x1F, 0x0F, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0F, 0x0F, 0x7C, 0xE0, 0x80, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 65
-    0xF8, 0xF8, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x10, 0x30, 0x70, 0xE0, 0xC0, 0x00, 0xFF, 0xFF, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0xF0, 0x9F, 0x0F, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC1, 0xFF, 0x7E, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 66
-    0x00, 0x80, 0xC0, 0x60, 0x30, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x30, 0x30, 0xE0, 0xC0, 0x00, 0xFC, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x0F, 0x3F, 0xF0, 0xC0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xE0, 0x78, 0x18, 0x00, 0x00, 0x00, 0x01, 0x01, 0x03, 0x03, 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 67
-    0xF8, 0xF8, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x10, 0x30, 0x30, 0x60, 0xC0, 0x80, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xFF, 0xFE, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0xC0, 0x70, 0x3F, 0x0F, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 68
-    0xF8, 0xF8, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0xFF, 0xFF, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 69
-    0xF8, 0xF8, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0xFF, 0xFF, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 70
-    0x00, 0x80, 0xC0, 0x60, 0x30, 0x10, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x30, 0x70, 0xE0, 0x80, 0xFC, 0xFF, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x83, 0x83, 0x07, 0x3F, 0x78, 0xC0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x03, 0x02, 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 71
-    0xF8, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xF8, 0xFF, 0xFF, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 72
-    0xF8, 0xF8, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x03, 0x00, 0x00, // 73
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x30, 0xF0, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0xFF, 0x3F, 0x00, 0x00, 0x01, 0x03, 0x03, 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 74
-    0xF8, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0xE0, 0x30, 0x18, 0x08, 0x00, 0xFF, 0xFF, 0x40, 0x40, 0x40, 0xE0, 0xF0, 0x98, 0x0C, 0x07, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x06, 0x0C, 0x38, 0x70, 0xE0, 0xC0, 0x80, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x02, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 75
-    0xF8, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 76
-    0xF8, 0xF8, 0xF8, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x78, 0xF8, 0xF8, 0xFF, 0xFF, 0x00, 0x03, 0x1F, 0x78, 0xE0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xF0, 0x3C, 0x0F, 0x01, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x01, 0x0F, 0x3C, 0xF0, 0x80, 0xC0, 0xF8, 0x1E, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 77
-    0xF8, 0xF8, 0x70, 0xC0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xF8, 0xFF, 0xFF, 0x00, 0x01, 0x03, 0x0E, 0x1C, 0x70, 0xE0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x07, 0x1C, 0x38, 0xE0, 0xC0, 0xFF, 0xFF, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 78
-    0x00, 0x80, 0xC0, 0x60, 0x30, 0x10, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x30, 0x30, 0xE0, 0xC0, 0x80, 0x00, 0xFE, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xFF, 0xFC, 0x0F, 0x3F, 0xF0, 0xC0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0x78, 0x3F, 0x07, 0x00, 0x00, 0x00, 0x01, 0x01, 0x03, 0x03, 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 79
-    0xF8, 0xF8, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x10, 0x30, 0x70, 0xE0, 0xC0, 0xFF, 0xFF, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0xC0, 0x60, 0x7F, 0x1F, 0xFF, 0xFF, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 80
-    0x00, 0x80, 0xC0, 0x60, 0x30, 0x10, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x30, 0x30, 0xE0, 0xC0, 0x80, 0x00, 0xFE, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xFF, 0xFC, 0x0F, 0x3F, 0xF0, 0xC0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0x78, 0x3F, 0x07, 0x00, 0x00, 0x00, 0x01, 0x01, 0x03, 0x03, 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x07, 0x0E, 0x1C, 0x38, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 81
-    0xF8, 0xF8, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x10, 0x30, 0x70, 0xE0, 0xC0, 0x00, 0xFF, 0xFF, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xC0, 0xE0, 0xB0, 0x3F, 0x0F, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0xFF, 0xFE, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 82
-    0x00, 0x80, 0xE0, 0x70, 0x30, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x10, 0x30, 0xE0, 0xC0, 0x00, 0x00, 0x07, 0x0F, 0x18, 0x30, 0x30, 0x60, 0x60, 0x60, 0xC0, 0xC0, 0xC0, 0x80, 0x80, 0x00, 0x03, 0x03, 0x10, 0x70, 0xE0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x81, 0xC3, 0xFE, 0x3C, 0x00, 0x00, 0x00, 0x01, 0x01, 0x03, 0x03, 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 83
-    0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0xF8, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 84
-    0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xF8, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x7F, 0xF8, 0xC0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xE0, 0x7F, 0x1F, 0x00, 0x00, 0x01, 0x01, 0x03, 0x03, 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 85
-    0x38, 0xF8, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xF8, 0x18, 0x00, 0x00, 0x07, 0x3F, 0xF8, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xF8, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0x3E, 0xF0, 0xC0, 0xC0, 0xF8, 0x3F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 86
-    0x18, 0xF8, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xF8, 0x78, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x78, 0x08, 0x00, 0x01, 0x1F, 0xFC, 0xC0, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFC, 0x1F, 0x01, 0x00, 0x03, 0x3F, 0xF8, 0x80, 0x00, 0x00, 0x00, 0x00, 0xF0, 0x7F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x1F, 0xFC, 0xC0, 0xF0, 0x7F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x1F, 0xFC, 0xC0, 0xF0, 0x7F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 87
-    0x08, 0x18, 0x78, 0xE0, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0xF0, 0x38, 0x18, 0x08, 0x00, 0x00, 0x00, 0x00, 0x03, 0x07, 0x1E, 0xB8, 0xF0, 0xF0, 0xBC, 0x0E, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xE0, 0x78, 0x1C, 0x0F, 0x03, 0x00, 0x01, 0x03, 0x0E, 0x1C, 0x70, 0xE0, 0x80, 0x00, 0x00, 0x02, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 88
-    0x18, 0x78, 0xE0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xE0, 0x70, 0x38, 0x08, 0x00, 0x00, 0x00, 0x03, 0x0F, 0x3C, 0x70, 0xC0, 0x00, 0xC0, 0xE0, 0x38, 0x1E, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 89
-    0x00, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x18, 0x98, 0xF8, 0x78, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xE0, 0x38, 0x1C, 0x07, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0x70, 0x38, 0x0E, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 90
-    0xFF, 0x03, 0x03, 0x03, 0x03, 0xFF, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x7F, 0x60, 0x60, 0x60, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, // 91
-    0x18, 0xF8, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x1F, 0xF8, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x1F, 0x78, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x0F, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 92
-    0x03, 0x03, 0x03, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x60, 0x60, 0x60, 0x7F, 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, // 93
-    0x00, 0x00, 0x00, 0x80, 0xF0, 0x18, 0xF0, 0xC0, 0x00, 0x00, 0x00, 0x40, 0x78, 0x1E, 0x07, 0x00, 0x00, 0x00, 0x07, 0x1E, 0x78, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 94
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 95
-    0x08, 0x08, 0x18, 0x30, 0x60, 0x40, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 96
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x38, 0x0C, 0x06, 0x06, 0x02, 0x02, 0x02, 0x06, 0x06, 0x1C, 0xF8, 0xE0, 0xF8, 0xDC, 0x06, 0x06, 0x02, 0x03, 0x03, 0x03, 0x03, 0x83, 0xC3, 0xFF, 0xFF, 0x00, 0x01, 0x03, 0x03, 0x02, 0x02, 0x02, 0x03, 0x01, 0x01, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 97
-    0xFC, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x18, 0x0C, 0x04, 0x06, 0x02, 0x02, 0x06, 0x06, 0x0E, 0x1C, 0xF8, 0xE0, 0xFF, 0xFF, 0xC0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0x3F, 0x03, 0x03, 0x00, 0x01, 0x03, 0x03, 0x02, 0x02, 0x02, 0x03, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 98
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xF8, 0x1C, 0x06, 0x06, 0x02, 0x02, 0x02, 0x06, 0x06, 0x0C, 0x78, 0x70, 0x7F, 0xF8, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xE0, 0x60, 0x00, 0x00, 0x01, 0x03, 0x03, 0x02, 0x02, 0x02, 0x03, 0x03, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 99
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFC, 0xE0, 0xF8, 0x1C, 0x0E, 0x06, 0x06, 0x02, 0x02, 0x06, 0x04, 0x0C, 0xFF, 0xFF, 0x3F, 0xFF, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00, 0x01, 0x03, 0x03, 0x02, 0x02, 0x02, 0x03, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 100
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x78, 0x1C, 0x0C, 0x06, 0x02, 0x02, 0x02, 0x06, 0x06, 0x0C, 0xF8, 0xF0, 0x07, 0x7F, 0xF3, 0xC3, 0x83, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x83, 0x03, 0x00, 0x00, 0x00, 0x01, 0x03, 0x03, 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 101
-    0x00, 0x00, 0x00, 0xF0, 0xFC, 0x0C, 0x06, 0x06, 0x06, 0x04, 0x06, 0x06, 0x06, 0xFF, 0xFF, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 102
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xF8, 0x1C, 0x0E, 0x06, 0x06, 0x02, 0x02, 0x06, 0x04, 0x0C, 0xF0, 0xFE, 0x3F, 0xFF, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x80, 0xC1, 0x83, 0x83, 0x82, 0x82, 0x82, 0x83, 0xC3, 0xE1, 0x7F, 0x3F, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, // 103
-    0xFC, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x30, 0x08, 0x04, 0x06, 0x02, 0x02, 0x06, 0x06, 0x0E, 0x7C, 0xF8, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 104
-    0x0C, 0x0C, 0xFE, 0xFE, 0xFF, 0xFF, 0x03, 0x03, 0x00, 0x00, // 105
-    0x00, 0x00, 0x00, 0x0C, 0x0C, 0x00, 0x00, 0x00, 0xFE, 0xFE, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x80, 0x80, 0xE0, 0x7F, 0x1F, 0x80, 0x80, 0x00, 0x00, 0x00, // 106
-    0xFC, 0xFC, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x80, 0xC0, 0x60, 0x38, 0x1C, 0x0E, 0x06, 0x02, 0x00, 0xFF, 0xFF, 0x03, 0x03, 0x03, 0x07, 0x0E, 0x18, 0x70, 0xE0, 0xC0, 0x80, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x02, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 107
-    0xFC, 0xFC, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x03, 0x00, 0x00, // 108
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFE, 0x30, 0x0C, 0x04, 0x06, 0x02, 0x02, 0x06, 0x06, 0x0E, 0xFC, 0xF0, 0x38, 0x0C, 0x04, 0x06, 0x02, 0x02, 0x06, 0x06, 0x0C, 0xFC, 0xF0, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 109
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFE, 0x30, 0x08, 0x04, 0x06, 0x02, 0x02, 0x06, 0x06, 0x0E, 0x7C, 0xF8, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 110
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0x78, 0x1C, 0x0C, 0x06, 0x06, 0x02, 0x02, 0x06, 0x06, 0x0C, 0x1C, 0xF8, 0xE0, 0x07, 0x7F, 0xF0, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0xFD, 0x3F, 0x00, 0x00, 0x00, 0x01, 0x03, 0x03, 0x02, 0x02, 0x02, 0x02, 0x03, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 111
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFE, 0x18, 0x0C, 0x06, 0x06, 0x02, 0x02, 0x06, 0x06, 0x0E, 0x1C, 0xF8, 0xE0, 0xFF, 0xFF, 0xC0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0xFF, 0x3F, 0xFF, 0xFF, 0x00, 0x01, 0x03, 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x01, 0x00, 0x00, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 112
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xF8, 0x1C, 0x0E, 0x06, 0x02, 0x02, 0x02, 0x06, 0x04, 0x0C, 0xFC, 0xFE, 0x3F, 0xFF, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xFF, 0xFF, 0x00, 0x00, 0x01, 0x03, 0x03, 0x02, 0x02, 0x02, 0x03, 0x01, 0x01, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, // 113
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFE, 0x30, 0x0C, 0x04, 0x06, 0x06, 0x06, 0x02, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 114
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x70, 0xFC, 0x8C, 0x06, 0x06, 0x02, 0x02, 0x06, 0x06, 0x0E, 0x3C, 0x38, 0xE0, 0xE0, 0x01, 0x01, 0x03, 0x03, 0x02, 0x06, 0x06, 0x0C, 0xDC, 0xF8, 0x00, 0x01, 0x03, 0x03, 0x02, 0x02, 0x02, 0x02, 0x03, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 115
-    0x00, 0x00, 0xE0, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x06, 0x06, 0xFF, 0xFF, 0x06, 0x06, 0x06, 0x06, 0x00, 0x00, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 116
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFE, 0x1F, 0xFF, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x7F, 0xFF, 0x00, 0x00, 0x01, 0x03, 0x03, 0x02, 0x02, 0x02, 0x03, 0x01, 0x01, 0x00, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 117
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x3E, 0xF8, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xF8, 0x1E, 0x06, 0x00, 0x00, 0x00, 0x07, 0x3E, 0xF0, 0x80, 0xC0, 0xF8, 0x1F, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 118
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x3E, 0xF8, 0x80, 0x00, 0x00, 0x00, 0x00, 0x80, 0xF8, 0x1E, 0x1E, 0xF8, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x80, 0xF8, 0x3E, 0x06, 0x00, 0x00, 0x03, 0x1F, 0xFC, 0xC0, 0xE0, 0x7C, 0x0F, 0x01, 0x00, 0x00, 0x01, 0x0F, 0x7C, 0xE0, 0x80, 0xF8, 0x1F, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 119
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x02, 0x06, 0x1E, 0x38, 0xE0, 0xC0, 0x00, 0x80, 0xE0, 0x70, 0x3C, 0x0E, 0x06, 0x02, 0x00, 0x00, 0xC0, 0xE0, 0x38, 0x1D, 0x07, 0x0F, 0x1C, 0x70, 0xE0, 0x80, 0x00, 0x00, 0x02, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 120
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0E, 0x3E, 0xF8, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xF8, 0x3E, 0x06, 0x00, 0x00, 0x01, 0x07, 0x3E, 0xF8, 0xC0, 0xC0, 0xF8, 0x3F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0xC0, 0x78, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 121
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x06, 0x06, 0x06, 0x06, 0x06, 0x06, 0x86, 0xC6, 0x76, 0x3E, 0x0E, 0x06, 0x00, 0x00, 0x80, 0xC0, 0x70, 0x38, 0x1C, 0x07, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 122
-    0x00, 0x00, 0x00, 0x00, 0xF0, 0xF8, 0x0C, 0x04, 0x06, 0x00, 0x00, 0x80, 0xE0, 0x7F, 0x1F, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x0E, 0xFC, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x3F, 0x60, 0xC0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 123
-    0xF8, 0xFF, 0xFF, 0x3F, 0x00, // 124
-    0x02, 0x06, 0x0C, 0x1C, 0xF8, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3F, 0xFF, 0xC0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xFC, 0x06, 0x03, 0x03, 0x80, 0xC0, 0xC0, 0x70, 0x3F, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 125
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0xC0, 0x40, 0x40, 0xC0, 0xC0, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xC0, 0x06, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x03, 0x06, 0x06, 0x04, 0x04, 0x06, 0x07, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 126
-    
-};
-
-#endif
diff --git a/STM32F1/libraries/ILI9341_due_STM/examples/arcs/roboto70.h b/STM32F1/libraries/ILI9341_due_STM/examples/arcs/roboto70.h
deleted file mode 100644
index 8cbda924f..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/examples/arcs/roboto70.h
+++ /dev/null
@@ -1,74 +0,0 @@
-
-
-/*
- *
- * roboto70
- *
- * created with FontCreator
- * written by F. Maximilian Thiele
- *
- * http://www.apetech.de/fontCreator
- * me@apetech.de
- *
- * File Name           : roboto70.h
- * Date                : 18.09.2014
- * Font size in bytes  : 15623
- * Font width          : 10
- * Font height         : 51
- * Font first char     : 48
- * Font last char      : 59
- * Font used chars     : 11
- *
- * The font data are defined as
- *
- * struct _FONT_ {
- *     uint16_t   font_Size_in_Bytes_over_all_included_Size_it_self;
- *     uint8_t    font_Width_in_Pixel_for_fixed_drawing;
- *     uint8_t    font_Height_in_Pixel_for_all_characters;
- *     unit8_t    font_First_Char;
- *     uint8_t    font_Char_Count;
- *
- *     uint8_t    font_Char_Widths[font_Last_Char - font_First_Char +1];
- *                  // for each character the separate width in pixels,
- *                  // characters < 128 have an implicit virtual right empty row
- *
- *     uint8_t    font_data[];
- *                  // bit field of all characters
- */
-
-#include <inttypes.h>
-#include <avr/pgmspace.h>
-
-#ifndef ROBOTO70_H
-#define ROBOTO70_H
-
-#define ROBOTO70_WIDTH 10
-#define ROBOTO70_HEIGHT 51
-
-static const uint8_t roboto70[] PROGMEM = {
-    0x3D, 0x07, // size
-    0x0A, // width
-    0x33, // height
-    0x30, // first char
-    0x0B, // char count
-    
-    // char widths
-    0x1F, 0x10, 0x20, 0x20, 0x24, 0x1D, 0x1F, 0x20, 0x20, 0x1F, 
-    0x04, 
-    
-    // font data
-    0x00, 0x00, 0x80, 0xE0, 0xF0, 0xF8, 0xFC, 0x3C, 0x1E, 0x1E, 0x0F, 0x0F, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x0F, 0x0F, 0x1E, 0x3E, 0x7C, 0xFC, 0xF8, 0xF0, 0xC0, 0x80, 0x00, 0x00, 0xC0, 0xFE, 0xFF, 0xFF, 0x3F, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x07, 0xFF, 0xFF, 0xFF, 0xFC, 0x80, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x1F, 0xFF, 0xFF, 0xFF, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFC, 0xFF, 0xFF, 0xFF, 0x07, 0x00, 0x01, 0x07, 0x1F, 0x3F, 0x7F, 0xFC, 0xF0, 0xE0, 0xC0, 0xC0, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0xC0, 0xC0, 0xE0, 0xF0, 0xFC, 0x7F, 0x3F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x20, 0x60, 0x60, 0x60, 0x60, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0x60, 0x60, 0x60, 0x60, 0x20, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 48
-    0x38, 0x38, 0x38, 0x38, 0x3C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1E, 0x1E, 0x1E, 0xFE, 0xFE, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x60, 0x60, 0x60, // 49
-    0x00, 0x80, 0xE0, 0xF0, 0xF8, 0x7C, 0x3C, 0x1E, 0x1E, 0x0F, 0x0F, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x0F, 0x0F, 0x1E, 0x3E, 0x7C, 0xFC, 0xF8, 0xF0, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x7E, 0x7F, 0x7F, 0x7F, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xE0, 0xF0, 0xFE, 0x7F, 0x3F, 0x0F, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0xE0, 0xF0, 0xF8, 0x7E, 0x3F, 0x1F, 0x07, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0xE0, 0xF0, 0xF8, 0x7E, 0x3F, 0x1F, 0x07, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xE0, 0xF0, 0xF8, 0xFE, 0xBF, 0x9F, 0x87, 0x83, 0x81, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x00, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, 0x60, // 50
-    0x00, 0x00, 0x80, 0xE0, 0xF0, 0xF8, 0xFC, 0x7C, 0x3E, 0x1E, 0x0F, 0x0F, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x0F, 0x0F, 0x1E, 0x1E, 0x3E, 0xFC, 0xF8, 0xF0, 0xE0, 0x80, 0x00, 0x00, 0x00, 0x1C, 0x1F, 0x1F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xCF, 0xFF, 0xFF, 0xFF, 0x78, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0xC0, 0xC0, 0xC0, 0xE0, 0xF0, 0x78, 0x7C, 0x3F, 0x1F, 0x0F, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x07, 0x07, 0x07, 0x07, 0x0E, 0x0E, 0x1E, 0x3C, 0x7C, 0xF8, 0xF0, 0xE0, 0x80, 0x00, 0x70, 0xF0, 0xF0, 0xF0, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xEF, 0xFF, 0xFF, 0xFF, 0x38, 0x00, 0x07, 0x0F, 0x3F, 0x7F, 0x7E, 0xF8, 0xF0, 0xE0, 0xC0, 0xC0, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0xC0, 0xC0, 0xE0, 0xE0, 0xF0, 0xFC, 0x7F, 0x3F, 0x0F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x20, 0x60, 0x60, 0x60, 0x60, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0x60, 0x60, 0x60, 0x60, 0x20, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 51
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xF0, 0xF8, 0xFE, 0x3F, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0xF0, 0xF8, 0xFE, 0x3F, 0x1F, 0x07, 0x03, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xE0, 0xF0, 0xFC, 0x7E, 0x3F, 0x0F, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xE0, 0xF8, 0xFC, 0x7F, 0x1F, 0x0F, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x18, 0x1E, 0x1F, 0x1F, 0x1F, 0x1F, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0xFF, 0xFF, 0xFF, 0xFF, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x60, 0x60, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 52
-    0x00, 0x00, 0x80, 0xFF, 0xFF, 0xFF, 0x3F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFF, 0xFF, 0xFF, 0xE0, 0xF0, 0x70, 0x78, 0x78, 0x38, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x3C, 0x78, 0x78, 0xF8, 0xF0, 0xE0, 0xE0, 0xC0, 0x00, 0x00, 0x00, 0x08, 0x0F, 0x0F, 0x0F, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x07, 0x1F, 0xFF, 0xFF, 0xFE, 0xF0, 0xE0, 0xE0, 0xE0, 0xE0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x03, 0x1F, 0x3F, 0x7F, 0xFC, 0xF0, 0xE0, 0xE0, 0xC0, 0xC0, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0xC0, 0xC0, 0xE0, 0xF0, 0xFC, 0x7F, 0x3F, 0x1F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x20, 0x60, 0x60, 0x60, 0x60, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0x60, 0x60, 0x60, 0x60, 0x20, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 53
-    0x00, 0x00, 0x00, 0x80, 0xE0, 0xF0, 0xF8, 0xF8, 0x7C, 0x3E, 0x1E, 0x0F, 0x0F, 0x0F, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x0F, 0x0F, 0x1E, 0x1E, 0x04, 0x00, 0x00, 0x00, 0x00, 0x80, 0xF8, 0xFE, 0xFF, 0x7F, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x80, 0xE0, 0xE0, 0x70, 0x78, 0x38, 0x3C, 0x1C, 0x1C, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1E, 0x1C, 0x3C, 0x7C, 0x78, 0xF8, 0xF0, 0xE0, 0xC0, 0x80, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x0F, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x03, 0x1F, 0xFF, 0xFF, 0xFE, 0xF0, 0x0F, 0xFF, 0xFF, 0xFF, 0xF8, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xFF, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0x07, 0x0F, 0x3F, 0x7F, 0x7C, 0xF8, 0xF0, 0xE0, 0xC0, 0xC0, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0xC0, 0xC0, 0xE0, 0xF0, 0xF8, 0x7E, 0x3F, 0x1F, 0x0F, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x20, 0x60, 0x60, 0x60, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0x60, 0x60, 0x60, 0x20, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 54
-    0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x0F, 0x8F, 0xCF, 0xFF, 0xFF, 0x7F, 0x3F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xE0, 0xF8, 0xFC, 0x3F, 0x1F, 0x07, 0x03, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xF0, 0xFC, 0xFF, 0x3F, 0x0F, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0, 0xF8, 0xFF, 0xFF, 0x3F, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFE, 0xFF, 0xFF, 0x3F, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xF8, 0xFF, 0xFF, 0xFF, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x60, 0x60, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 55
-    0x00, 0x00, 0x00, 0xC0, 0xF0, 0xF8, 0xFC, 0x7C, 0x3E, 0x1E, 0x0F, 0x0F, 0x0F, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x0F, 0x0F, 0x1F, 0x1E, 0x3E, 0xFC, 0xF8, 0xF0, 0xE0, 0xC0, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0x00, 0x00, 0x01, 0x07, 0x1F, 0x3F, 0x3E, 0x78, 0xF0, 0xE0, 0xE0, 0xC0, 0xC0, 0xC0, 0x80, 0x80, 0x80, 0x80, 0x80, 0xC0, 0xC0, 0xC0, 0xE0, 0xE0, 0xF0, 0x7C, 0x3F, 0x1F, 0x0F, 0x07, 0x01, 0x00, 0x00, 0x00, 0xC0, 0xE0, 0xF0, 0xF8, 0x3C, 0x1C, 0x1E, 0x0E, 0x07, 0x07, 0x07, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x07, 0x07, 0x07, 0x0F, 0x0E, 0x1E, 0x3C, 0x7C, 0xF8, 0xF0, 0xE0, 0xC0, 0x00, 0x78, 0xFF, 0xFF, 0xFF, 0xEF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x07, 0x1F, 0x3F, 0x7F, 0xFC, 0xF8, 0xF0, 0xE0, 0xC0, 0xC0, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0xC0, 0xC0, 0xC0, 0xE0, 0xF0, 0xF8, 0xFE, 0x7F, 0x3F, 0x0F, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x20, 0x60, 0x60, 0x60, 0x60, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0x60, 0x60, 0x60, 0x60, 0x20, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 56
-    0x00, 0x00, 0x80, 0xC0, 0xF0, 0xF8, 0xFC, 0x7C, 0x3E, 0x1E, 0x0F, 0x0F, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x0F, 0x0F, 0x1E, 0x1E, 0x3C, 0xFC, 0xF8, 0xF0, 0xE0, 0xC0, 0x00, 0x00, 0xE0, 0xFE, 0xFF, 0xFF, 0x3F, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x03, 0x1F, 0xFF, 0xFF, 0xFF, 0xF0, 0x3F, 0xFF, 0xFF, 0xFF, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x01, 0x07, 0x1F, 0x3F, 0x7F, 0xFC, 0xF8, 0xF0, 0xE0, 0xC0, 0xC0, 0xC0, 0x80, 0x80, 0x80, 0x80, 0x80, 0xC0, 0xC0, 0xC0, 0xE0, 0xE0, 0x70, 0x78, 0x3E, 0x0F, 0xFF, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x01, 0x01, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xFF, 0xFF, 0xFF, 0x3F, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xC0, 0xC0, 0xC0, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0xC0, 0xC0, 0xE0, 0xE0, 0xF0, 0xFC, 0x7F, 0x3F, 0x1F, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x20, 0x60, 0x60, 0x60, 0x60, 0x60, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0x60, 0x60, 0x60, 0x60, 0x20, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 57
-    0x00, 0x00, 0x00, 0x00, 0xE0, 0xE0, 0xE0, 0xE0, 0x03, 0x03, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xE0, 0xE0, 0xE0, 0xE0, 0x60, 0x60, 0x60, 0x60 // 58
-    
-};
-
-#endif
diff --git a/STM32F1/libraries/ILI9341_due_STM/examples/gTextBigFont/gTextBigFont.ino b/STM32F1/libraries/ILI9341_due_STM/examples/gTextBigFont/gTextBigFont.ino
deleted file mode 100644
index 66362ea78..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/examples/gTextBigFont/gTextBigFont.ino
+++ /dev/null
@@ -1,63 +0,0 @@
-#include <SPI.h> //uncomment when using SPI_MODE_NORMAL or SPI_MODE_EXTENDED
-#include <ILI_SdSpi.h>
-#include <ILI_SdFatConfig.h>
-#include <ILI9341_due_gText.h>
-#include <ILI9341_due.h>
-
-#include "fonts\jokerman_255.h"
-
-#define TFT_DC 10
-#define TFT_CS 8
-#define TFT_RST  9
-
-ILI9341_due myTFT(TFT_CS, TFT_DC, TFT_RST);
-ILI9341_due_gText t1(&myTFT);
-
-void setup()
-{
-	Serial.begin(9600);
-	
-	bool result = myTFT.begin();
-	
-	Serial.print("TFT begin successful: ");
-	Serial.println(result ? "YES" : "NO");
-	myTFT.fillScreen(ILI9341_BLACK);
-
-	t1.defineArea(18, 32, 222, 287);
-	t1.selectFont(jokerman_255);
-	//t1.setFontMode(gTextFontMode_Transparent);
-}
-
-void loop()
-{
-	t1.setFontColor(255,230,0,0,0,0);
-	t1.drawString("0", gTextAlignMiddleCenter, gTextEraseFullLine);
-	delay(750);
-	t1.setFontColor(232,157,12);
-	t1.drawString("1", gTextAlignMiddleCenter, gTextEraseFullLine);
-	delay(750);
-	t1.setFontColor(255,88,0);
-	t1.drawString("2", gTextAlignMiddleCenter, gTextEraseFullLine);
-	delay(750);
-	t1.setFontColor(232,12,15);
-	t1.drawString("3", gTextAlignMiddleCenter, gTextEraseFullLine);
-	delay(750);
-	t1.setFontColor(227,13,255);
-	t1.drawString("4", gTextAlignMiddleCenter, gTextEraseFullLine);
-	delay(750);
-	t1.setFontColor(57,0,255);
-	t1.drawString("5", gTextAlignMiddleCenter, gTextEraseFullLine);
-	delay(750);
-	t1.setFontColor(12,103,232);
-	t1.drawString("6", gTextAlignMiddleCenter, gTextEraseFullLine);
-	delay(750);
-	t1.setFontColor(0,255,243);
-	t1.drawString("7", gTextAlignMiddleCenter, gTextEraseFullLine);
-	delay(750);
-	t1.setFontColor(12,232,73);
-	t1.drawString("8", gTextAlignMiddleCenter, gTextEraseFullLine);
-	delay(750);
-	t1.setFontColor(132,255,13);
-	t1.drawString("9", gTextAlignMiddleCenter, gTextEraseFullLine);
-	delay(750);
-}
diff --git a/STM32F1/libraries/ILI9341_due_STM/examples/gTextHelloWorld/gTextHelloWorld.ino b/STM32F1/libraries/ILI9341_due_STM/examples/gTextHelloWorld/gTextHelloWorld.ino
deleted file mode 100644
index 7953374ef..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/examples/gTextHelloWorld/gTextHelloWorld.ino
+++ /dev/null
@@ -1,39 +0,0 @@
-//#include <SPI.h> //uncomment when using SPI_MODE_NORMAL or SPI_MODE_EXTENDED
-#include <ILI_SdSpi.h>
-#include <ILI_SdFatConfig.h>
-#include <ILI9341_due_gText.h>
-#include <ILI9341_due.h>
-
-#include "fonts\Arial_bold_14.h"
-
-#define TFT_CS 10
-#define TFT_DC 9
-
-ILI9341_due myTFT(TFT_CS, TFT_DC);
-
-void setup()
-{
-	Serial.begin(9600);
-	
-	bool result = myTFT.begin();
-	
-	Serial.print("TFT begin successful: ");
-	Serial.println(result ? "YES" : "NO");
-
-	myTFT.fillScreen(ILI9341_BLUE);
-	myTFT.setRotation(iliRotation270);
-
-	ILI9341_due_gText t1(&myTFT);
-	t1.defineArea(100, 110, 220, 130);
-	t1.selectFont(Arial_bold_14);
-	t1.setFontLetterSpacing(5);
-	t1.setFontColor(ILI9341_WHITE, ILI9341_BLUE);
-	t1.drawString("Hello World", gTextAlignMiddleCenter);
-}
-
-void loop()
-{
-
-	/* add main program code here */
-
-}
diff --git a/STM32F1/libraries/ILI9341_due_STM/examples/graphicstest/graphicstest.ino b/STM32F1/libraries/ILI9341_due_STM/examples/graphicstest/graphicstest.ino
deleted file mode 100644
index 09bbeebe2..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/examples/graphicstest/graphicstest.ino
+++ /dev/null
@@ -1,410 +0,0 @@
-/***************************************************
-  This is our GFX example for the Adafruit ILI9341 Breakout and Shield
-  ----> http://www.adafruit.com/products/1651
-
-  Check out the links above for our tutorials and wiring diagrams
-  These displays use SPI to communicate, 4 or 5 pins are required to
-  interface (RST is optional)
-  Adafruit invests time and resources providing this open source code,
-  please support Adafruit and open-source hardware by purchasing
-  products from Adafruit!
-
-  Written by Limor Fried/Ladyada for Adafruit Industries.
-  MIT license, all text above must be included in any redistribution
- ****************************************************/
-
-
-//#include <SPI.h>
-
-#include <SPI.h> 
-#include <ILI_SdSpi.h>
-#include <ILI_SdFatConfig.h>
-#include <ILI9341_due_gText.h>
-#include <ILI9341_due.h>
-
-// For the Adafruit shield, these are the default.
-
-// For the Adafruit shield, these are the default.
-#define TFT_DC PA15
-#define TFT_CS PB4
-#define rst  PB3
-
-// Use hardware SPI (on Uno, #13, #12, #11) and the above for CS/DC
-ILI9341_due tft = ILI9341_due(TFT_CS, TFT_DC, rst);
-
-void setup() {
-  delay (5000);
-  Serial.begin(115200);
-  while (!Serial) ; // wait for Arduino Serial Monitor
-  Serial.println("ILI9341 Test!"); 
- 
-  tft.begin();
-
-  // read diagnostics (optional but can help debug problems)
-  uint8_t x = tft.readcommand8(ILI9341_RDMODE);
-  Serial.print("Display Power Mode: 0x"); Serial.println(x, HEX);
-  x = tft.readcommand8(ILI9341_RDMADCTL);
-  Serial.print("MADCTL Mode: 0x"); Serial.println(x, HEX);
-  x = tft.readcommand8(ILI9341_RDPIXFMT);
-  Serial.print("Pixel Format: 0x"); Serial.println(x, HEX);
-  x = tft.readcommand8(ILI9341_RDIMGFMT);
-  Serial.print("Image Format: 0x"); Serial.println(x, HEX);
-  x = tft.readcommand8(ILI9341_RDSELFDIAG);
-  Serial.print("Self Diagnostic: 0x"); Serial.println(x, HEX); 
-  
-  Serial.println(F("Benchmark                Time (microseconds)"));
-
-  Serial.print(F("Screen fill              "));
-  Serial.println(testFillScreen());
-  delay(200);
-
-  Serial.print(F("Text                     "));
-  Serial.println(testText());
-  delay(600);
-
-  Serial.print(F("Lines                    "));
-  Serial.println(testLines(ILI9341_CYAN));
-  delay(200);
-
-  Serial.print(F("Horiz/Vert Lines         "));
-  Serial.println(testFastLines(ILI9341_RED, ILI9341_BLUE));
-  delay(200);
-
-  Serial.print(F("Rectangles (outline)     "));
-  Serial.println(testRects(ILI9341_GREEN));
-  delay(200);
-
-  Serial.print(F("Rectangles (filled)      "));
-  Serial.println(testFilledRects(ILI9341_YELLOW, ILI9341_MAGENTA));
-  delay(200);
-
-  Serial.print(F("Circles (filled)         "));
-  Serial.println(testFilledCircles(10, ILI9341_MAGENTA));
-
-  Serial.print(F("Circles (outline)        "));
-  Serial.println(testCircles(10, ILI9341_WHITE));
-  delay(200);
-
-  Serial.print(F("Triangles (outline)      "));
-  Serial.println(testTriangles());
-  delay(200);
-
-  Serial.print(F("Triangles (filled)       "));
-  Serial.println(testFilledTriangles());
-  delay(200);
-
-  Serial.print(F("Rounded rects (outline)  "));
-  Serial.println(testRoundRects());
-  delay(200);
-
-  Serial.print(F("Rounded rects (filled)   "));
-  Serial.println(testFilledRoundRects());
-  delay(200);
-
-  Serial.println(F("Done!"));
-
-}
-
-
-void loop(void) {
-  runTests();
-  return;
-  for(uint8_t rotation=0; rotation<4; rotation++) {
-    tft.setRotation((iliRotation)rotation);
-    testText();
-    delay(1000);
-  }
-}
-
-void runTests()
-{
-  Serial.print(F("Screen fill              "));
-  Serial.println(testFillScreen());
-//  delay(200);
-
-  Serial.print(F("Text                     "));
-  Serial.println(testText());
- // delay(600);
-
-  Serial.print(F("Lines                    "));
-  Serial.println(testLines(ILI9341_CYAN));
-//  delay(200);
-
-  Serial.print(F("Horiz/Vert Lines         "));
-  Serial.println(testFastLines(ILI9341_RED, ILI9341_BLUE));
-//  delay(200);
-
-  Serial.print(F("Rectangles (outline)     "));
-  Serial.println(testRects(ILI9341_GREEN));
-  delay(200);
-
-  Serial.print(F("Rectangles (filled)      "));
-  Serial.println(testFilledRects(ILI9341_YELLOW, ILI9341_MAGENTA));
-//  delay(200);
-
-  Serial.print(F("Circles (filled)         "));
-  Serial.println(testFilledCircles(10, ILI9341_MAGENTA));
-
-  Serial.print(F("Circles (outline)        "));
-  Serial.println(testCircles(10, ILI9341_WHITE));
-//  delay(200);
-
-  Serial.print(F("Triangles (outline)      "));
-  Serial.println(testTriangles());
-//  delay(200);
-
-  Serial.print(F("Triangles (filled)       "));
-  Serial.println(testFilledTriangles());
-//  delay(200);
-
-  Serial.print(F("Rounded rects (outline)  "));
-  Serial.println(testRoundRects());
-//  delay(200);
-
-  Serial.print(F("Rounded rects (filled)   "));
-  Serial.println(testFilledRoundRects());
-//  delay(200);
-  
-  
-}
-
-unsigned long testFillScreen() {
-  unsigned long start = micros();
-//  tft.fillScreen(ILI9341_BLACK);
-  tft.fillScreen(ILI9341_RED);
-  tft.fillScreen(ILI9341_GREEN);
-  tft.fillScreen(ILI9341_BLUE);
-  tft.fillScreen(ILI9341_BLACK);
-  return micros() - start;
-}
-
-unsigned long testText() {
-  tft.fillScreen(ILI9341_BLACK);
-  unsigned long start = micros();
-  tft.setCursor(0, 0);
-  tft.setTextColor(ILI9341_WHITE);  tft.setTextSize(1);
-  tft.println("Hello World!");
-  tft.setTextColor(ILI9341_YELLOW); tft.setTextSize(2);
-  tft.println(1234.56);
-  tft.setTextColor(ILI9341_RED);    tft.setTextSize(3);
-  tft.println(0xDEADBEEF, HEX);
-  tft.println();
-  tft.setTextColor(ILI9341_GREEN);
-  tft.setTextSize(5);
-  tft.println("Groop");
-  tft.setTextSize(2);
-  tft.println("I implore thee,");
-  tft.setTextSize(1);
-  tft.println("my foonting turlingdromes.");
-  tft.println("And hooptiously drangle me");
-  tft.println("with crinkly bindlewurdles,");
-  tft.println("Or I will rend thee");
-  tft.println("in the gobberwarts");
-  tft.println("with my blurglecruncheon,");
-  tft.println("see if I don't!");
-  return micros() - start;
-}
-
-unsigned long testLines(uint16_t color) {
-  unsigned long start, t;
-  int           x1, y1, x2, y2,
-                w = tft.width(),
-                h = tft.height();
-
-  tft.fillScreen(ILI9341_BLACK);
-
-  x1 = y1 = 0;
-  y2    = h - 1;
-  start = micros();
-  for(x2=0; x2<w; x2+=6) tft.drawLine(x1, y1, x2, y2, color);
-  x2    = w - 1;
-  for(y2=0; y2<h; y2+=6) tft.drawLine(x1, y1, x2, y2, color);
-  t     = micros() - start; // fillScreen doesn't count against timing
-
-  tft.fillScreen(ILI9341_BLACK);
-
-  x1    = w - 1;
-  y1    = 0;
-  y2    = h - 1;
-  start = micros();
-  for(x2=0; x2<w; x2+=6) tft.drawLine(x1, y1, x2, y2, color);
-  x2    = 0;
-  for(y2=0; y2<h; y2+=6) tft.drawLine(x1, y1, x2, y2, color);
-  t    += micros() - start;
-
-  tft.fillScreen(ILI9341_BLACK);
-
-  x1    = 0;
-  y1    = h - 1;
-  y2    = 0;
-  start = micros();
-  for(x2=0; x2<w; x2+=6) tft.drawLine(x1, y1, x2, y2, color);
-  x2    = w - 1;
-  for(y2=0; y2<h; y2+=6) tft.drawLine(x1, y1, x2, y2, color);
-  t    += micros() - start;
-
-  tft.fillScreen(ILI9341_BLACK);
-
-  x1    = w - 1;
-  y1    = h - 1;
-  y2    = 0;
-  start = micros();
-  for(x2=0; x2<w; x2+=6) tft.drawLine(x1, y1, x2, y2, color);
-  x2    = 0;
-  for(y2=0; y2<h; y2+=6) tft.drawLine(x1, y1, x2, y2, color);
-
-  return micros() - start;
-}
-
-unsigned long testFastLines(uint16_t color1, uint16_t color2) {
-  unsigned long start;
-  int           x, y, w = tft.width(), h = tft.height();
-
-  tft.fillScreen(ILI9341_BLACK);
-  start = micros();
-  for(y=0; y<h; y+=5) tft.drawFastHLine(0, y, w, color1);
-  for(x=0; x<w; x+=5) tft.drawFastVLine(x, 0, h, color2);
-
-  return micros() - start;
-}
-
-unsigned long testRects(uint16_t color) {
-  unsigned long start;
-  int           n, i, i2,
-                cx = tft.width()  / 2,
-                cy = tft.height() / 2;
-
-  tft.fillScreen(ILI9341_BLACK);
-  n     = min(tft.width(), tft.height());
-  start = micros();
-  for(i=2; i<n; i+=6) {
-    i2 = i / 2;
-    tft.drawRect(cx-i2, cy-i2, i, i, color);
-  }
-
-  return micros() - start;
-}
-
-unsigned long testFilledRects(uint16_t color1, uint16_t color2) {
-  unsigned long start, t = 0;
-  int           n, i, i2,
-                cx = tft.width()  / 2 - 1,
-                cy = tft.height() / 2 - 1;
-
-  tft.fillScreen(ILI9341_BLACK);
-  n = min(tft.width(), tft.height());
-  for(i=n; i>0; i-=6) {
-    i2    = i / 2;
-    start = micros();
-    tft.fillRect(cx-i2, cy-i2, i, i, color1);
-    t    += micros() - start;
-    // Outlines are not included in timing results
-    tft.drawRect(cx-i2, cy-i2, i, i, color2);
-  }
-
-  return t;
-}
-
-unsigned long testFilledCircles(uint8_t radius, uint16_t color) {
-  unsigned long start;
-  int x, y, w = tft.width(), h = tft.height(), r2 = radius * 2;
-
-  tft.fillScreen(ILI9341_BLACK);
-  start = micros();
-  for(x=radius; x<w; x+=r2) {
-    for(y=radius; y<h; y+=r2) {
-      tft.fillCircle(x, y, radius, color);
-    }
-  }
-
-  return micros() - start;
-}
-
-unsigned long testCircles(uint8_t radius, uint16_t color) {
-  unsigned long start;
-  int           x, y, r2 = radius * 2,
-                w = tft.width()  + radius,
-                h = tft.height() + radius;
-
-  // Screen is not cleared for this one -- this is
-  // intentional and does not affect the reported time.
-  start = micros();
-  for(x=0; x<w; x+=r2) {
-    for(y=0; y<h; y+=r2) {
-      tft.drawCircle(x, y, radius, color);
-    }
-  }
-
-  return micros() - start;
-}
-
-unsigned long testTriangles() {
-  unsigned long start;
-  int           n, i, cx = tft.width()  / 2 - 1,
-                      cy = tft.height() / 2 - 1;
-
-  tft.fillScreen(ILI9341_BLACK);
-  n     = min(cx, cy);
-  start = micros();
-  for(i=0; i<n; i+=5) {
-    tft.drawTriangle(
-      cx    , cy - i, // peak
-      cx - i, cy + i, // bottom left
-      cx + i, cy + i, // bottom right
-      tft.color565(0, 0, i));
-  }
-
-  return micros() - start;
-}
-
-unsigned long testFilledTriangles() {
-  unsigned long start, t = 0;
-  int           i, cx = tft.width()  / 2 - 1,
-                   cy = tft.height() / 2 - 1;
-
-  tft.fillScreen(ILI9341_BLACK);
-  start = micros();
-  for(i=min(cx,cy); i>10; i-=5) {
-    start = micros();
-    tft.fillTriangle(cx, cy - i, cx - i, cy + i, cx + i, cy + i,
-      tft.color565(0, i, i));
-    t += micros() - start;
-    tft.drawTriangle(cx, cy - i, cx - i, cy + i, cx + i, cy + i,
-      tft.color565(i, i, 0));
-  }
-
-  return t;
-}
-
-unsigned long testRoundRects() {
-  unsigned long start;
-  int           w, i, i2,
-                cx = tft.width()  / 2 - 1,
-                cy = tft.height() / 2 - 1;
-
-  tft.fillScreen(ILI9341_BLACK);
-  w     = min(tft.width(), tft.height());
-  start = micros();
-  for(i=0; i<w; i+=6) {
-    i2 = i / 2;
-    tft.drawRoundRect(cx-i2, cy-i2, i, i, i/8, tft.color565(i, 0, 0));
-  }
-
-  return micros() - start;
-}
-
-unsigned long testFilledRoundRects() {
-  unsigned long start;
-  int           i, i2,
-                cx = tft.width()  / 2 - 1,
-                cy = tft.height() / 2 - 1;
-
-  tft.fillScreen(ILI9341_BLACK);
-  start = micros();
-  for(i=min(tft.width(), tft.height()); i>20; i-=6) {
-    i2 = i / 2;
-    tft.fillRoundRect(cx-i2, cy-i2, i, i, i/8, tft.color565(0, i, 0));
-  }
-
-  return micros() - start;
-}
diff --git a/STM32F1/libraries/ILI9341_due_STM/examples/graphicstestWithStats/graphicstestWithStats.ino b/STM32F1/libraries/ILI9341_due_STM/examples/graphicstestWithStats/graphicstestWithStats.ino
deleted file mode 100644
index 74f152879..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/examples/graphicstestWithStats/graphicstestWithStats.ino
+++ /dev/null
@@ -1,427 +0,0 @@
-/***************************************************
-This is our GFX example for the Adafruit ILI9341 Breakout and Shield
-----> http://www.adafruit.com/products/1651
-
-Check out the links above for our tutorials and wiring diagrams
-These displays use SPI to communicate, 4 or 5 pins are required to
-interface (RST is optional)
-Adafruit invests time and resources providing this open source code,
-please support Adafruit and open-source hardware by purchasing
-products from Adafruit!
-
-Written by Limor Fried/Ladyada for Adafruit Industries.
-MIT license, all text above must be included in any redistribution
-****************************************************/
-#include <SPI.h> 
-#include <ILI_SdSpi.h>
-#include <ILI_SdFatConfig.h>
-#include <ILI9341_due_gText.h>
-#include <ILI9341_due.h>
-#include "fonts\Arial_bold_14.h"
-
-
-#define TFT_DC 10
-#define TFT_CS 8
-#define TFT_RST 9
-
-// Use hardware SPI (on Uno, #13, #12, #11) and the above for CS/DC
-ILI9341_due tft = ILI9341_due(TFT_CS, TFT_DC, TFT_RST);
-
-ILI9341_due_gText t1(&tft);
-long Screenfill,
-	Text,
-	Lines,
-	HorizVertLines,
-	Rectanglesoutline,
-	Rectanglesfilled,
-	Circlesfilled,
-	Circlesoutline,
-	Trianglesoutline,
-	Trianglesfilled,
-	Roundedrectsoutline,
-	Roundedrectsfilled;
-
-void setup() {
-
-
-	Serial.begin(9600);
-	while (!Serial) ; // wait for Arduino Serial Monitor
-	Serial.println("ILI9341 Test!"); 
-
-	tft.begin();
-	tft.setRotation(iliRotation270);
-	tft.fillScreen(ILI9341_BLUE);
-	t1.defineArea(30, 30, 26, 12, Arial_bold_14);
-	t1.selectFont(Arial_bold_14);
-	t1.setFontLetterSpacing(2);
-	t1.setFontColor(ILI9341_WHITE, ILI9341_BLUE);
-
-#if SPI_MODE_NORMAL
-	char mode[] = "SPI_MODE_NORMAL";
-#elif SPI_MODE_EXTENDED
-	char mode[] = "SPI_MODE_EXTENDED";
-#elif SPI_MODE_DMA
-	char mode[] = "SPI_MODE_DMA";
-
-#endif
-	t1.drawString(mode, tft.width()/2 - t1.stringWidth(mode) / 2 - 30, 80);
-
-	delay(3000);
-	tft.setRotation(iliRotation0);
-	// read diagnostics (optional but can help debug problems)
-	uint8_t x = tft.readcommand8(ILI9341_RDMODE);
-	Serial.print("Display Power Mode: 0x"); Serial.println(x, HEX);
-	x = tft.readcommand8(ILI9341_RDMADCTL);
-	Serial.print("MADCTL Mode: 0x"); Serial.println(x, HEX);
-	x = tft.readcommand8(ILI9341_RDPIXFMT);
-	Serial.print("Pixel Format: 0x"); Serial.println(x, HEX);
-	x = tft.readcommand8(ILI9341_RDIMGFMT);
-	Serial.print("Image Format: 0x"); Serial.println(x, HEX);
-	x = tft.readcommand8(ILI9341_RDSELFDIAG);
-	Serial.print("Self Diagnostic: 0x"); Serial.println(x, HEX); 
-
-	Serial.println(F("Benchmark                Time (microseconds)"));
-
-	Serial.print(F("Screen fill              "));
-	unsigned long start = micros();
-	Serial.println(Screenfill = testFillScreen());
-	// delay(200);
-
-	Serial.print(F("Text                     "));
-	Serial.println(Text = testText());
-	// delay(200);
-
-	Serial.print(F("Lines                    "));
-	Serial.println(Lines = testLines(ILI9341_CYAN));
-	// delay(200);
-
-	Serial.print(F("Horiz/Vert Lines         "));
-	Serial.println(HorizVertLines = testFastLines(ILI9341_RED, ILI9341_BLUE));
-	// delay(200);
-
-	Serial.print(F("Rectangles (outline)     "));
-	Serial.println(Rectanglesoutline = testRects(ILI9341_GREEN));
-	// delay(200);
-
-	Serial.print(F("Rectangles (filled)      "));
-	Serial.println(Rectanglesfilled = testFilledRects(ILI9341_YELLOW, ILI9341_MAGENTA));
-	// delay(200);
-
-	Serial.print(F("Circles (filled)         "));
-	Serial.println(Circlesfilled = testFilledCircles(10, ILI9341_MAGENTA));
-
-	Serial.print(F("Circles (outline)        "));
-	Serial.println(Circlesoutline = testCircles(10, ILI9341_WHITE));
-	// delay(200);
-
-	Serial.print(F("Triangles (outline)      "));
-	Serial.println(Trianglesoutline = testTriangles());
-	// delay(200);
-
-	Serial.print(F("Triangles (filled)       "));
-	Serial.println(Trianglesfilled = testFilledTriangles());
-	// delay(200);
-
-	Serial.print(F("Rounded rects (outline)  "));
-	Serial.println(Roundedrectsoutline = testRoundRects());
-	// delay(200);
-
-	Serial.print(F("Rounded rects (filled)   "));
-	Serial.println(Roundedrectsfilled = testFilledRoundRects());
-	// delay(200);
-
-
-	Serial.println(F("Done!"));
-
-	tft.fillScreen(ILI9341_BLUE);
-	tft.setRotation(iliRotation270);
-	t1.cursorToXY(45, 80);
-	t1.print("Total time: ");
-	t1.print((micros() - start)/1000);
-	t1.print(" ms");
-
-	delay(2000);
-	printStats();
-
-}
-
-void printStats()
-{
-	tft.setRotation(iliRotation270);
-	tft.fillScreen(ILI9341_BLUE);
-	t1.cursorTo(0, 0);
-	t1.print("Screen fill              "); t1.cursorTo(18); t1.print(Screenfill);
-	t1.cursorTo(0, 1);
-	t1.print("Text                     "); t1.cursorTo(18); t1.print(Text);
-	t1.cursorTo(0, 2);
-	t1.print("Lines                    "); t1.cursorTo(18); t1.print(Lines);
-	t1.cursorTo(0, 3);
-	t1.print("Horiz/Vert Lines         "); t1.cursorTo(18); t1.print(HorizVertLines);
-	t1.cursorTo(0, 4);
-	t1.print("Rectangles (outline)     "); t1.cursorTo(18); t1.print(Rectanglesoutline);
-	t1.cursorTo(0, 5);
-	t1.print("Rectangles (filled)      "); t1.cursorTo(18); t1.print(Rectanglesfilled);
-	t1.cursorTo(0, 6);
-	t1.print("Circles (filled)         "); t1.cursorTo(18); t1.print(Circlesfilled);
-	t1.cursorTo(0, 7);
-	t1.print("Circles (outline)        "); t1.cursorTo(18); t1.print(Circlesoutline);
-	t1.cursorTo(0, 8);
-	t1.print("Triangles (outline)      "); t1.cursorTo(18); t1.print(Trianglesoutline);
-	t1.cursorTo(0, 9);
-	t1.print("Triangles (filled)       "); t1.cursorTo(18); t1.print(Trianglesfilled);
-	t1.cursorTo(0, 10);
-	t1.print("Rounded rects (outline)  "); t1.cursorTo(18); t1.print(Roundedrectsoutline);
-	t1.cursorTo(0, 11);
-	t1.print("Rounded rects (filled)   "); t1.cursorTo(18); t1.print(Roundedrectsfilled);
-
-}
-
-void loop(void) {
-	/*for(uint8_t rotation=0; rotation<4; rotation++) {
-	tft.setRotation(rotation);
-	testText();
-	delay(1000);
-	}*/
-}
-
-unsigned long testFillScreen() {
-	unsigned long start = micros();
-	tft.fillScreen(ILI9341_BLACK);
-	tft.fillScreen(ILI9341_RED);
-	tft.fillScreen(ILI9341_GREEN);
-	tft.fillScreen(ILI9341_BLUE);
-	tft.fillScreen(ILI9341_BLACK);
-	return micros() - start;
-}
-
-unsigned long testText() {
-	tft.fillScreen(ILI9341_BLACK);
-	unsigned long start = micros();
-	tft.setCursor(0, 0);
-	tft.setTextColor(ILI9341_WHITE);  tft.setTextSize(1);
-	tft.println("Hello World!");
-	tft.setTextColor(ILI9341_YELLOW); tft.setTextSize(2);
-	tft.println(1234.56);
-	tft.setTextColor(ILI9341_RED);    tft.setTextSize(3);
-	tft.println(0xDEADBEEF, HEX);
-	tft.println();
-	tft.setTextColor(ILI9341_GREEN);
-	tft.setTextSize(5);
-	tft.println("Groop");
-	tft.setTextSize(2);
-	tft.println("I implore thee,");
-	tft.setTextSize(1);
-	tft.println("my foonting turlingdromes.");
-	tft.println("And hooptiously drangle me");
-	tft.println("with crinkly bindlewurdles,");
-	tft.println("Or I will rend thee");
-	tft.println("in the gobberwarts");
-	tft.println("with my blurglecruncheon,");
-	tft.println("see if I don't!");
-	return micros() - start;
-}
-
-unsigned long testLines(uint16_t color) {
-	unsigned long start, t;
-	int           x1, y1, x2, y2,
-		w = tft.width(),
-		h = tft.height();
-
-	tft.fillScreen(ILI9341_BLACK);
-
-	x1 = y1 = 0;
-	y2    = h - 1;
-	start = micros();
-	for(x2=0; x2<w; x2+=6) tft.drawLine(x1, y1, x2, y2, color);
-	x2    = w - 1;
-	for(y2=0; y2<h; y2+=6) tft.drawLine(x1, y1, x2, y2, color);
-	t     = micros() - start; // fillScreen doesn't count against timing
-
-	tft.fillScreen(ILI9341_BLACK);
-
-	x1    = w - 1;
-	y1    = 0;
-	y2    = h - 1;
-	start = micros();
-	for(x2=0; x2<w; x2+=6) tft.drawLine(x1, y1, x2, y2, color);
-	x2    = 0;
-	for(y2=0; y2<h; y2+=6) tft.drawLine(x1, y1, x2, y2, color);
-	t    += micros() - start;
-
-	tft.fillScreen(ILI9341_BLACK);
-
-	x1    = 0;
-	y1    = h - 1;
-	y2    = 0;
-	start = micros();
-	for(x2=0; x2<w; x2+=6) tft.drawLine(x1, y1, x2, y2, color);
-	x2    = w - 1;
-	for(y2=0; y2<h; y2+=6) tft.drawLine(x1, y1, x2, y2, color);
-	t    += micros() - start;
-
-	tft.fillScreen(ILI9341_BLACK);
-
-	x1    = w - 1;
-	y1    = h - 1;
-	y2    = 0;
-	start = micros();
-	for(x2=0; x2<w; x2+=6) tft.drawLine(x1, y1, x2, y2, color);
-	x2    = 0;
-	for(y2=0; y2<h; y2+=6) tft.drawLine(x1, y1, x2, y2, color);
-
-	return micros() - start;
-}
-
-unsigned long testFastLines(uint16_t color1, uint16_t color2) {
-	unsigned long start;
-	int           x, y, w = tft.width(), h = tft.height();
-
-	tft.fillScreen(ILI9341_BLACK);
-	start = micros();
-	for(y=0; y<h; y+=5) tft.drawFastHLine(0, y, w, color1);
-	for(x=0; x<w; x+=5) tft.drawFastVLine(x, 0, h, color2);
-
-	return micros() - start;
-}
-
-unsigned long testRects(uint16_t color) {
-	unsigned long start;
-	int           n, i, i2,
-		cx = tft.width()  / 2,
-		cy = tft.height() / 2;
-
-	tft.fillScreen(ILI9341_BLACK);
-	n     = min(tft.width(), tft.height());
-	start = micros();
-	for(i=2; i<n; i+=6) {
-		i2 = i / 2;
-		tft.drawRect(cx-i2, cy-i2, i, i, color);
-	}
-
-	return micros() - start;
-}
-
-unsigned long testFilledRects(uint16_t color1, uint16_t color2) {
-	unsigned long start, t = 0;
-	int           n, i, i2,
-		cx = tft.width()  / 2 - 1,
-		cy = tft.height() / 2 - 1;
-
-	tft.fillScreen(ILI9341_BLACK);
-	n = min(tft.width(), tft.height());
-	for(i=n; i>0; i-=6) {
-		i2    = i / 2;
-		start = micros();
-		tft.fillRect(cx-i2, cy-i2, i, i, color1);
-		t    += micros() - start;
-		// Outlines are not included in timing results
-		tft.drawRect(cx-i2, cy-i2, i, i, color2);
-	}
-
-	return t;
-}
-
-unsigned long testFilledCircles(uint8_t radius, uint16_t color) {
-	unsigned long start;
-	int x, y, w = tft.width(), h = tft.height(), r2 = radius * 2;
-
-	tft.fillScreen(ILI9341_BLACK);
-	start = micros();
-	for(x=radius; x<w; x+=r2) {
-		for(y=radius; y<h; y+=r2) {
-			tft.fillCircle(x, y, radius, color);
-		}
-	}
-
-	return micros() - start;
-}
-
-unsigned long testCircles(uint8_t radius, uint16_t color) {
-	unsigned long start;
-	int           x, y, r2 = radius * 2,
-		w = tft.width()  + radius,
-		h = tft.height() + radius;
-
-	// Screen is not cleared for this one -- this is
-	// intentional and does not affect the reported time.
-	start = micros();
-	for(x=0; x<w; x+=r2) {
-		for(y=0; y<h; y+=r2) {
-			tft.drawCircle(x, y, radius, color);
-		}
-	}
-
-	return micros() - start;
-}
-
-unsigned long testTriangles() {
-	unsigned long start;
-	int           n, i, cx = tft.width()  / 2 - 1,
-		cy = tft.height() / 2 - 1;
-
-	tft.fillScreen(ILI9341_BLACK);
-	n     = min(cx, cy);
-	start = micros();
-	for(i=0; i<n; i+=5) {
-		tft.drawTriangle(
-			cx    , cy - i, // peak
-			cx - i, cy + i, // bottom left
-			cx + i, cy + i, // bottom right
-			tft.color565(0, 0, i));
-	}
-
-	return micros() - start;
-}
-
-unsigned long testFilledTriangles() {
-	unsigned long start, t = 0;
-	int           i, cx = tft.width()  / 2 - 1,
-		cy = tft.height() / 2 - 1;
-
-	tft.fillScreen(ILI9341_BLACK);
-	start = micros();
-	for(i=min(cx,cy); i>10; i-=5) {
-		start = micros();
-		tft.fillTriangle(cx, cy - i, cx - i, cy + i, cx + i, cy + i,
-			tft.color565(0, i, i));
-		t += micros() - start;
-		tft.drawTriangle(cx, cy - i, cx - i, cy + i, cx + i, cy + i,
-			tft.color565(i, i, 0));
-	}
-
-	return t;
-}
-
-unsigned long testRoundRects() {
-	unsigned long start;
-	int           w, i, i2,
-		cx = tft.width()  / 2 - 1,
-		cy = tft.height() / 2 - 1;
-
-	tft.fillScreen(ILI9341_BLACK);
-	w     = min(tft.width(), tft.height());
-	start = micros();
-	for(i=0; i<w; i+=6) {
-		i2 = i / 2;
-		tft.drawRoundRect(cx-i2, cy-i2, i, i, i/8, tft.color565(i, 0, 0));
-	}
-
-	return micros() - start;
-}
-
-unsigned long testFilledRoundRects() {
-	unsigned long start;
-	int           i, i2,
-		cx = tft.width()  / 2 - 1,
-		cy = tft.height() / 2 - 1;
-
-	tft.fillScreen(ILI9341_BLACK);
-	start = micros();
-
-	for(i=min(tft.width(), tft.height()); i>20; i-=6) {
-		i2 = i / 2;
-		tft.fillRoundRect(cx-i2, cy-i2, i, i, i/8, tft.color565(0, i, 0));
-	}
-
-	return micros() - start;
-}
diff --git a/STM32F1/libraries/ILI9341_due_STM/examples/sdFatTftBitmap/images/blacklab.565 b/STM32F1/libraries/ILI9341_due_STM/examples/sdFatTftBitmap/images/blacklab.565
deleted file mode 100644
index 3fc8152b3c01f21d777feb7ad204b469e39f7eea..0000000000000000000000000000000000000000
GIT binary patch
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deleted file mode 100644
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deleted file mode 100644
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deleted file mode 100644
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deleted file mode 100644
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diff --git a/STM32F1/libraries/ILI9341_due_STM/examples/sdFatTftBitmap/sdFatTftBitmap.ino b/STM32F1/libraries/ILI9341_due_STM/examples/sdFatTftBitmap/sdFatTftBitmap.ino
deleted file mode 100644
index 22a4fe379..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/examples/sdFatTftBitmap/sdFatTftBitmap.ino
+++ /dev/null
@@ -1,320 +0,0 @@
-/*
-This sketch is demonstrating loading images from an SD card.
-To run this sketch, copy images from the images folder into the root of an SD card
-(either those with .bmp extension or those with .565 extension (those will load faster)).
-Modify the extension of the files in loop() depending on which files you copied onto SD.
-
-Depending on the length of the cables between Arduino and SD card pins you might want
-to change SD_SPI_SPEED to either SPI_FULL_SPEED (if you have a shield directly connected to
-Arduino pins) or SPI_QUARTER_SPEED if you have long cables. SPI_HALF_SPEED was the maximum
-I could use as I had the display with SD slot on a breadboard.
-Obviously you have to modify CS, DC pins for TFT and SD appropriately.
-
-You can generate your own .565 images from 24bit BMPs by using BMP24toILI565 converter which
-you can find in the Tools folder on GitHub:
-https://github.com/marekburiak/ILI9341_due/tree/master/tools
-*/
-
-#include <SPI.h>
-#include <SdFat.h>
-#include <SdFatUtil.h>
-#include <ILI_SdSpi.h>
-#include <ILI_SdFatConfig.h>
-#include <ILI9341_due_gText.h>
-#include <ILI9341_due.h>
-
-// CS and DC for the LCD
-#define LCD_CS 10	// Chip Select for LCD
-#define LCD_DC 9	// Command/Data for LCD
-
-#define SD_CS 7		// Chip Select for SD card
-
-#define BUFFPIXELCOUNT 320	// size of the buffer in pixels
-#define SD_SPI_SPEED SPI_HALF_SPEED	// SD card SPI speed, try SPI_FULL_SPEED
-
-SdFat sd; // set filesystem
-SdFile bmpFile; // set filesystem
-//ArduinoOutStream cout(Serial);
-
-ILI9341_due tft(LCD_CS, LCD_DC);
-
-// store error strings in flash to save RAM
-#define error(s) sd.errorHalt_P(PSTR(s))
-
-void setup()
-{
-	Serial.begin(9600);
-
-	tft.begin();
-	tft.setRotation(iliRotation270);	// landscape
-	progmemPrint(PSTR("Initializing SD card..."));
-
-	if (!sd.begin(SD_CS, SD_SPI_SPEED)){
-		progmemPrintln(PSTR("failed!"));
-		return;
-	}
-	progmemPrintln(PSTR("OK!"));
-}
-
-void loop()
-{
-	if (tft.getRotation() == iliRotation90 || tft.getRotation() == iliRotation270){
-		bmpDraw("giraffe.565", 0, 0);
-		delay(2000);
-		bmpDraw("SOLDHO~1.565", 0, 0);
-		delay(2000);
-		bmpDraw("GLOOMY~1.565", 0, 0);
-		delay(2000);
-	    bmpDraw("MOTIVA~1.565", 0, 0);
-	    delay(2000);
-	}
-	else
-	{
-		bmpDraw("smokeP.565", 0, 0);
-		delay(2000);
-		bmpDraw("origP.565", 0, 0);
-		delay(2000);
-		bmpDraw("radioP.565", 0, 0);
-		delay(2000);
-		bmpDraw("stopP.565", 0, 0);
-		delay(2000);
-	}
-
-}
-
-// This function opens a Windows Bitmap (BMP) file and
-// displays it at the given coordinates.  It's sped up
-// by reading many pixels worth of data at a time
-// (rather than pixel by pixel).  Increasing the buffer
-// size takes more of the Arduino's RAM but
-// makes loading a little faster.  
-
-void bmpDraw(char* filename, int x, int y) {
-
-	SdFile   bmpFile;
-	int      bmpWidth, bmpHeight;   // W+H in pixels
-	uint8_t  bmpDepth;              // Bit depth (currently must be 24)
-	uint8_t	 headerSize;
-	uint32_t bmpImageoffset;        // Start of image data in file
-	uint32_t rowSize;     // Not always = bmpWidth; may have padding
-	uint32_t fileSize;
-	boolean  goodBmp = false;       // Set to true on valid header parse
-	boolean  flip = true;        // BMP is stored bottom-to-top
-	uint16_t w, h, row, col;
-	uint8_t  r, g, b;
-	uint32_t pos = 0, startTime;
-
-	if ((x >= tft.width()) || (y >= tft.height())) return;
-
-	progmemPrint(PSTR("Loading image '"));
-	Serial.print(filename);
-	Serial.println('\'');
-	startTime = millis();
-	// Open requested file on SD card
-	if (!bmpFile.open(filename, O_READ)) {
-		Serial.println("File open failed.");
-		return;
-	}
-	else {
-		//Serial.println("File opened.");
-	}
-
-	// Parse BMP header
-	if (read16(bmpFile) == 0x4D42) { // BMP signature
-		fileSize = read32(bmpFile);
-		//progmemPrint(PSTR("File size: ")); Serial.println(fileSize);
-		(void)read32(bmpFile); // Read & ignore creator bytes
-		bmpImageoffset = read32(bmpFile); // Start of image data
-		//progmemPrint(PSTR("Image Offset: ")); Serial.println(bmpImageoffset, DEC);
-		// Read DIB header
-		headerSize = read32(bmpFile);
-		//progmemPrint(PSTR("Header size: ")); Serial.println(headerSize);
-		bmpWidth = read32(bmpFile);
-		bmpHeight = read32(bmpFile);
-		if (read16(bmpFile) == 1) { // # planes -- must be '1'
-			bmpDepth = read16(bmpFile); // bits per pixel
-			//progmemPrint(PSTR("Bit Depth: ")); Serial.println(bmpDepth);
-			if (read32(bmpFile) == 0) // 0 = uncompressed
-			{
-				//progmemPrint(PSTR("Image size: "));
-				//Serial.print(bmpWidth);
-				//Serial.print('x');
-				//Serial.println(bmpHeight);
-
-				// If bmpHeight is negative, image is in top-down order.
-				// This is not canon but has been observed in the wild.
-				if (bmpHeight < 0) {
-					bmpHeight = -bmpHeight;
-					flip = false;
-				}
-
-				// Crop area to be loaded
-				w = bmpWidth;
-				h = bmpHeight;
-				if ((x + w - 1) >= tft.width())  w = tft.width() - x;
-				if ((y + h - 1) >= tft.height()) h = tft.height() - y;
-
-				// Set TFT address window to clipped image bounds
-				tft.setAddrWindow(x, y, x + w - 1, y + h - 1);
-
-				if (bmpDepth == 16)	//565 format
-				{
-					goodBmp = true; // Supported BMP format -- proceed!
-
-					uint8_t buffer[2 * BUFFPIXELCOUNT]; // pixel buffer (contains already formatted data for ILI9341 display)
-
-					bmpFile.seekSet(54);	//skip header
-					uint32_t totalPixels = bmpWidth*bmpHeight;
-					uint16_t numFullBufferRuns = totalPixels / BUFFPIXELCOUNT;
-					for (uint32_t p = 0; p < numFullBufferRuns; p++) {
-						// read pixels into the buffer
-						bmpFile.read(buffer, 2 * BUFFPIXELCOUNT);
-						// push them to the diplay
-						tft.pushColors565(buffer, 0, 2 * BUFFPIXELCOUNT);
-					}
-
-					// render any remaining pixels that did not fully fit the buffer
-					uint32_t remainingPixels = totalPixels % BUFFPIXELCOUNT;
-					if (remainingPixels > 0)
-					{
-						bmpFile.read(buffer, 2 * remainingPixels);
-						tft.pushColors565(buffer, 0, 2 * remainingPixels);
-					}
-
-				}
-				else if (bmpDepth == 24)	// standard 24bit bmp
-				{
-					goodBmp = true; // Supported BMP format -- proceed!
-					uint16_t bufferSize = min(w, BUFFPIXELCOUNT);
-					uint8_t  sdbuffer[3 * bufferSize]; // pixel in buffer (R+G+B per pixel)
-					uint16_t lcdbuffer[bufferSize];  // pixel out buffer (16-bit per pixel)
-
-					// BMP rows are padded (if needed) to 4-byte boundary
-					rowSize = (bmpWidth * 3 + 3) & ~3;
-
-					for (row = 0; row < h; row++) { // For each scanline...
-						// Seek to start of scan line.  It might seem labor-
-						// intensive to be doing this on every line, but this
-						// method covers a lot of gritty details like cropping
-						// and scanline padding.  Also, the seek only takes
-						// place if the file position actually needs to change
-						// (avoids a lot of cluster math in SD library).
-
-						if (flip) // Bitmap is stored bottom-to-top order (normal BMP)
-							pos = bmpImageoffset + (bmpHeight - 1 - row) * rowSize;
-						else     // Bitmap is stored top-to-bottom
-							pos = bmpImageoffset + row * rowSize;
-						if (bmpFile.curPosition() != pos) { // Need seek?
-							bmpFile.seekSet(pos);
-						}
-
-						for (col = 0; col < w; col += bufferSize)
-						{
-							// read pixels into the buffer
-							bmpFile.read(sdbuffer, 3 * bufferSize);
-
-							// convert color
-							for (int p = 0; p < bufferSize; p++)
-							{
-								b = sdbuffer[3 * p];
-								g = sdbuffer[3 * p + 1];
-								r = sdbuffer[3 * p + 2];
-								lcdbuffer[p] = tft.color565(r, g, b);
-							}
-							// push buffer to TFT
-							tft.pushColors(lcdbuffer, 0, bufferSize);
-						}
-
-						// render any remaining pixels that did not fully fit the buffer
-						uint16_t remainingPixels = w % bufferSize;
-						if (remainingPixels > 0)
-						{
-							bmpFile.read(sdbuffer, 3 * remainingPixels);
-
-							for (int p = 0; p < remainingPixels; p++)
-							{
-								b = sdbuffer[3 * p];
-								g = sdbuffer[3 * p + 1];
-								r = sdbuffer[3 * p + 2];
-								lcdbuffer[p] = tft.color565(r, g, b);
-							}
-
-							tft.pushColors(lcdbuffer, 0, remainingPixels);
-						}
-					}
-				}
-				else
-				{
-					progmemPrint(PSTR("Unsupported Bit Depth."));
-				}
-
-				if (goodBmp)
-				{
-					progmemPrint(PSTR("Loaded in "));
-					Serial.print(millis() - startTime);
-					Serial.println(" ms");
-				}
-			}
-		}
-	}
-
-	bmpFile.close();
-	if (!goodBmp) progmemPrintln(PSTR("BMP format not recognized."));
-}
-
-
-// These read 16- and 32-bit types from the SD card file.
-// BMP data is stored little-endian, Arduino is little-endian too.
-// May need to reverse subscript order if porting elsewhere.
-
-uint16_t read16(SdFile& f) {
-	uint16_t result;
-	((uint8_t *)&result)[0] = f.read(); // LSB
-	((uint8_t *)&result)[1] = f.read(); // MSB
-	return result;
-}
-
-uint32_t read32(SdFile& f) {
-	uint32_t result;
-	((uint8_t *)&result)[0] = f.read(); // LSB
-	((uint8_t *)&result)[1] = f.read();
-	((uint8_t *)&result)[2] = f.read();
-	((uint8_t *)&result)[3] = f.read(); // MSB
-	return result;
-}
-
-// Copy string from flash to serial port
-// Source string MUST be inside a PSTR() declaration!
-void progmemPrint(const char *str) {
-	char c;
-	while (c = pgm_read_byte(str++)) Serial.print(c);
-}
-
-// Same as above, with trailing newline
-void progmemPrintln(const char *str) {
-	progmemPrint(str);
-	Serial.println();
-}
-
-//void PrintHex8(uint8_t *data, uint8_t length) // prints 8-bit data in hex
-//{
-//	char tmp[length*5+1];
-//	byte first;
-//	byte second;
-//	for (int i=0; i<length; i++) {
-//		first = (data[i] >> 4) & 0x0f;
-//		second = data[i] & 0x0f;
-//		// base for converting single digit numbers to ASCII is 48
-//		// base for 10-16 to become upper-case characters A-F is 55
-//		// note: difference is 7
-//		tmp[i*5] = 48; // add leading 0
-//		tmp[i*5+1] = 120; // add leading x
-//		tmp[i*5+2] = first+48;
-//		tmp[i*5+3] = second+48;
-//		tmp[i*5+4] = 32; // add trailing space
-//		if (first > 9) tmp[i*5+2] += 7;
-//		if (second > 9) tmp[i*5+3] += 7;
-//	}
-//	tmp[length*5] = 0;
-//	Serial.print(tmp);
-//}
\ No newline at end of file
diff --git a/STM32F1/libraries/ILI9341_due_STM/examples/utftDemo/utftDemo.ino b/STM32F1/libraries/ILI9341_due_STM/examples/utftDemo/utftDemo.ino
deleted file mode 100644
index 0aec4eace..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/examples/utftDemo/utftDemo.ino
+++ /dev/null
@@ -1,341 +0,0 @@
-// UTFT Demo ported to ILI9341_due library by TFTLCDCyg
-
-// Based on Demo 320x240 Serial of UTFT library 
-// UTFT-web: http://www.henningkarlsen.com/electronics
-
-#include <SPI.h>
-
-// ILI9341_due NEW lib by Marek Buriak http://marekburiak.github.io/ILI9341_due/
-#include <SPI.h> 
-#include <ILI_SdSpi.h>
-#include <ILI_SdFatConfig.h>
-#include <ILI9341_due_gText.h>
-#include <ILI9341_due.h>
-#include "fonts\Arial14.h"
-//#include "Streaming.h"
-// For the Adafruit shield, these are the default.
-
-#define TFT_DC 10
-#define TFT_CS 8
-#define rst  9
-
-// Use hardware SPI (on Uno, #13, #12, #11) and the above for CS/DC
-ILI9341_due tft = ILI9341_due(TFT_CS, TFT_DC, rst);
-
-ILI9341_due_gText t1(&tft);
-char textBuff[20];
-
-// Color set
-#define	BLACK           0x0000
-#define	RED             0xF800
-#define	GREEN           0x07E0
-//#define	BLUE            0x001F
-#define	BLUE            0x102E
-#define CYAN            0x07FF
-#define MAGENTA         0xF81F
-#define YELLOW          0xFFE0 
-#define ORANGE          0xFD20
-#define GREENYELLOW     0xAFE5 
-#define DARKGREEN       0x03E0
-#define WHITE           0xFFFF
-
-uint16_t  color;
-uint16_t  colorFONDO=BLACK;
-
-void setup()
-{
-  delay (5000);
-  randomSeed(analogRead(0));
-
-   // TFT 2.2" SPI 
-  Serial.begin(115200);
-  tft.begin();
-  tft.setRotation(iliRotation270);  
-  tft.fillScreen(colorFONDO);
-  t1.defineArea(0, 0, 320, 240);
-  t1.selectFont(Arial14);
-}
-
-void ILI9341duenodelay() 
-{
-  int buf[318];
-  int x, x2;
-  int y, y2;
-  int r;
-
- tft.fillScreen(colorFONDO);  
-
- int timeinit= millis();
-
-
-//ILI9341due NEW
-  tft.fillRect(0, 0, 320, 15,RED);
-  t1.setFontColor(WHITE, RED);
-  t1.drawString("* ILI9341_due UTFT 240x320 Demo *", 47,0);  
-  tft.fillRect(0, 226, 320, 240,tft.color565(64, 64, 64));
-  t1.setFontColor(YELLOW, tft.color565(64, 64, 64));
-  t1.drawString("<http://electronics.henningkarlsen.com>", gTextAlignBottomCenter,227);  
-
-//ILI9341due NEW
-  tft.drawRect(0, 15, 320, 211,BLUE);
-
-//ILI9341due NEW
-// Draw crosshairs
-  tft.drawLine(159, 15, 159, 224,BLUE);
-  tft.drawLine(1, 119, 318, 119,BLUE);
-  for (int i=9; i<310; i+=10)
-    tft.drawLine(i, 117, i, 121,BLUE);
-  for (int i=19; i<220; i+=10)
-    tft.drawLine(157, i, 161, i, BLUE);
-// Draw sin-, cos- and tan-lines  
-  t1.setFontColor(CYAN, BLACK);
-  t1.drawString("Sin", 5,17);    
-  for (int i=1; i<318; i++)
-  {
-    tft.drawPixel(i,119+(sin(((i*1.13)*3.14)/180)*95),CYAN);
-  }
-  t1.setFontColor(RED, BLACK);
-  t1.drawString("Cos", 5,29);    
-  for (int i=1; i<318; i++)
-  {
-    tft.drawPixel(i,119+(cos(((i*1.13)*3.14)/180)*95),RED);
-  }
-  t1.setFontColor(YELLOW, BLACK);
-  t1.drawString("Tan", 5,41);    
-  for (int i=1; i<318; i++)
-  {
-    tft.drawPixel(i,119+(tan(((i*1.13)*3.14)/180)),YELLOW);
-  }
-//  delay(2000);
-
-
-//ILI9341due NEW
-  tft.fillRect(1,16,318,209,BLACK);    
-  tft.drawLine(159, 16, 159, 224,BLUE);
-  tft.drawLine(1, 119, 318, 119,BLUE);
-
-// Draw a moving sinewave
-  x=1;
-  for (int i=1; i<(318*20); i++) 
-  {
-    x++;
-    if (x==319)
-      x=1;
-    if (i>319)
-    {
-      if ((x==159)||(buf[x-1]==119))
-        color = BLUE;
-      else
-        color = BLACK;        
-      tft.drawPixel(x,buf[x-1],color);
-    }
-    y=119+(sin(((i*1.1)*3.14)/180)*(90-(i / 100)));
-    tft.drawPixel(x,y,CYAN);
-    buf[x-1]=y;
-  }
-//  delay(2000); 
-  
-  
-//ILI9341due NEW
-  tft.fillRect(1,16,318,209,BLACK);    
-  
-// Draw some filled rectangles
-  for (int i=1; i<6; i++)
-  {
-    switch (i)
-    {
-      case 1:
-        color = MAGENTA;
-        break;
-      case 2:
-        color = RED;        
-        break;
-      case 3:
-        color = GREEN;        
-        break;
-      case 4:
-        color = BLUE;        
-        break;
-      case 5:
-        color = YELLOW;        
-        break;
-    }
-      tft.fillRect(70+(i*20), 30+(i*20), 60, 60,color);
-  }  
-//  delay(2000);
-
-  
-//ILI9341due NEW
-  tft.fillRect(1,16,318,209,BLACK);    
-  
-// Draw some filled, rounded rectangles
-  for (int i=1; i<6; i++)
-  {
-    switch (i)
-    {
-      case 1:
-        color = MAGENTA;
-        break;
-      case 2:
-        color = RED;        
-        break;
-      case 3:
-        color = GREEN;        
-        break;
-      case 4:
-        color = BLUE;        
-        break;
-      case 5:
-        color = YELLOW;
-        break;
-    }
-    tft.fillRoundRect(190-(i*20), 30+(i*20), 60, 60,3,color);
-  }  
- // delay(2000);
-
-
-//ILI9341due NEW
-  tft.fillRect(1,16,318,209,BLACK);    
-
-// Draw some filled circles
-  for (int i=1; i<6; i++)
-  {
-    switch (i)
-    {
-      case 1:
-        color = MAGENTA;
-        break;
-      case 2:
-        color = RED;        
-        break;
-      case 3:
-        color = GREEN;        
-        break;
-      case 4:
-        color = BLUE;        
-        break;
-      case 5:
-        color = YELLOW;
-        break;
-    }
-    tft.fillCircle(100+(i*20),60+(i*20), 30, color);
-  }
-// delay(2000);
-
-
-//ILI9341due NEW
-  tft.fillRect(1,16,318,209,BLACK);    
-
-// Draw some lines in a pattern
-  for (int i=17; i<222; i+=5)
-  {
-    tft.drawLine(1, i, (i*1.44)-10, 224, RED);
-  }
-  for (int i=222; i>17; i-=5)
-  {
-    tft.drawLine(318, i, (i*1.44)-11, 15,RED);
-  }
-  for (int i=222; i>17; i-=5)
-  {
-    tft.drawLine(1, i, 331-(i*1.44), 15, CYAN);
-  }
-  for (int i=17; i<222; i+=5)
-  {
-    tft.drawLine(318, i, 330-(i*1.44), 223, CYAN);
-  }
- // delay(2000);
-
-
-//ILI9341due NEW
-  tft.fillRect(1,16,318,209,BLACK);    
-  
-// Draw some random circles
-  for (int i=0; i<100; i++)
-  {
-    color = tft.color565(random(255), random(255), random(255));    
-    x=32+random(256);
-    y=45+random(146);
-    r=random(30);
-    tft.drawCircle(x, y, r, color);
-  }  
- // delay(2000);
-
-  
-//ILI9341due NEW
-  tft.fillRect(1,16,318,209,BLACK);      
-// Draw some random rectangles
-  for (int i=0; i<100; i++)
-  {
-    color = tft.color565(random(255), random(255), random(255));    
-    x=2 + random(165);
-    y=16+ random(100);
-    x2=random(165);
-    y2=random(115);
-    tft.drawRect(x, y, x2, y2, color);
-  }
-//  delay(2000);
-
-
-//ILI9341due NEW
-  tft.fillRect(1,16,318,209,BLACK);      
-// Draw some random rounded rectangles
-  for (int i=0; i<100; i++)
-  {
-    color = tft.color565(random(255), random(255), random(255));    
-    x=2+random(165);
-    y=16+random(100);
-    x2=random(165);
-    y2=random(115);
-    tft.drawRoundRect(x, y, x2, y2,3,color);
-   
-  }
- // delay(2000);
-
-//ILI9341due NEW
-  tft.fillRect(1,16,318,209,BLACK);      
-
-  for (int i=0; i<100; i++)
-  {
-    color = tft.color565(random(255), random(255), random(255));        
-    x=2+random(316);
-    y=16+random(209);
-    x2=2+random(316);
-    y2=16+random(209);
-    tft.drawLine(x, y, x2, y2, color);
-  }
-  //delay(2000);
-  
-  
-//ILI9341due NEW
-  tft.fillRect(1,16,318,209,BLACK);        
-  
-  for (int i=0; i<10000; i++)
-  {
-    color = tft.color565(random(255), random(255), random(255));            
-    tft.drawPixel(2+random(316), 16+random(209), color);
-  }  
-  int timetest = millis() -timeinit;
-  //delay(2000);
-
-
-//ILI9341due NEW
-  tft.fillRect(0,0,320,240,BLUE);        
-  tft.fillRoundRect(80, 70, 159, 99,3,RED);
-  t1.setFontColor(WHITE, RED);
-  t1.drawString("That's it!", 130,93);  
-  t1.drawString("Restarting in a", 117, 119);
-  t1.drawString("few seconds...", 117, 132);  
-  
-  t1.setFontColor(WHITE, BLUE);
-  t1.drawString("Runtime: (msecs)", 112, 210);  
-
-  sprintf(textBuff, "%d", timetest);
-  t1.drawString(textBuff, 146, 225);  
-}
-
-void loop()
-{
- ILI9341duenodelay();   
- delay(5000);  
-}  
-
diff --git a/STM32F1/libraries/ILI9341_due_STM/fonts/Arial14.h b/STM32F1/libraries/ILI9341_due_STM/fonts/Arial14.h
deleted file mode 100644
index 9536adb1d..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/fonts/Arial14.h
+++ /dev/null
@@ -1,173 +0,0 @@
-
-
-/*
- *
- * Arial_14
- *
- * created with FontCreator
- * written by F. Maximilian Thiele
- *
- * http://www.apetech.de/fontCreator
- * me@apetech.de
- *
- * File Name           : Arial14.h
- * Date                : 02.05.2008
- * Font size in bytes  : 7788
- * Font width          : 10
- * Font height         : 14
- * Font first char     : 32
- * Font last char      : 128
- * Font used chars     : 96
- *
- * The font data are defined as
- *
- * struct _FONT_ {
- *     uint16_t   font_Size_in_Bytes_over_all_included_Size_it_self;
- *     uint8_t    font_Width_in_Pixel_for_fixed_drawing;
- *     uint8_t    font_Height_in_Pixel_for_all_characters;
- *     unit8_t    font_First_Char;
- *     uint8_t    font_Char_Count;
- *
- *     uint8_t    font_Char_Widths[font_Last_Char - font_First_Char +1];
- *                  // for each character the separate width in pixels,
- *                  // characters < 128 have an implicit virtual right empty row
- *
- *     uint8_t    font_data[];
- *                  // bit field of all characters
- */
-
-#include <inttypes.h>
-#include <avr/pgmspace.h>
-
-#ifndef ARIAL_14_H
-#define ARIAL_14_H
-
-#define ARIAL_14_WIDTH 10
-#define ARIAL_14_HEIGHT 14
-
-/*
- * added to allow fontname to match header file name. 
- * as well as keep the old name for backward compability
- */
-
-#define Arial14 Arial_14 
-
-static const uint8_t Arial_14[] PROGMEM = {
-    0x1E, 0x6C, // size
-    0x0A, // width
-    0x0E, // height
-    0x20, // first char
-    0x60, // char count
-    
-    // char widths
-    0x00, 0x01, 0x03, 0x08, 0x07, 0x0A, 0x08, 0x01, 0x03, 0x03, 
-    0x05, 0x07, 0x01, 0x04, 0x01, 0x04, 0x06, 0x03, 0x06, 0x06, 
-    0x07, 0x06, 0x06, 0x06, 0x06, 0x06, 0x01, 0x01, 0x06, 0x06, 
-    0x06, 0x06, 0x0D, 0x09, 0x07, 0x08, 0x08, 0x07, 0x07, 0x09, 
-    0x07, 0x01, 0x05, 0x08, 0x07, 0x09, 0x07, 0x09, 0x07, 0x09, 
-    0x08, 0x07, 0x07, 0x07, 0x09, 0x0D, 0x08, 0x09, 0x08, 0x02, 
-    0x04, 0x02, 0x05, 0x08, 0x02, 0x06, 0x06, 0x05, 0x06, 0x06, 
-    0x04, 0x06, 0x06, 0x01, 0x02, 0x06, 0x01, 0x09, 0x06, 0x06, 
-    0x06, 0x06, 0x04, 0x05, 0x04, 0x06, 0x07, 0x09, 0x06, 0x07, 
-    0x06, 0x03, 0x01, 0x03, 0x07, 0x07, 
-    
-    // font data
-    0xFE, 0x14, // 33
-    0x1E, 0x00, 0x1E, 0x00, 0x00, 0x00, // 34
-    0x90, 0x90, 0xF8, 0x96, 0x90, 0xF8, 0x96, 0x90, 0x00, 0x1C, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, // 35
-    0x18, 0x24, 0x22, 0xFF, 0x42, 0x42, 0x84, 0x08, 0x10, 0x10, 0x3C, 0x10, 0x08, 0x04, // 36
-    0x1C, 0x22, 0x22, 0x1C, 0xC0, 0x30, 0x8C, 0x42, 0x40, 0x80, 0x00, 0x00, 0x10, 0x0C, 0x00, 0x00, 0x0C, 0x10, 0x10, 0x0C, // 37
-    0x80, 0x5C, 0x22, 0x62, 0x92, 0x0C, 0x80, 0x00, 0x0C, 0x10, 0x10, 0x10, 0x10, 0x0C, 0x08, 0x10, // 38
-    0x1E, 0x00, // 39
-    0xF0, 0x0C, 0x02, 0x1C, 0x60, 0x80, // 40
-    0x02, 0x0C, 0xF0, 0x80, 0x60, 0x1C, // 41
-    0x04, 0x14, 0x0E, 0x14, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, // 42
-    0x40, 0x40, 0x40, 0xF8, 0x40, 0x40, 0x40, 0x00, 0x00, 0x00, 0x0C, 0x00, 0x00, 0x00, // 43
-    0x00, 0x70, // 44
-    0x80, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, // 45
-    0x00, 0x10, // 46
-    0x00, 0xC0, 0x38, 0x06, 0x18, 0x04, 0x00, 0x00, // 47
-    0xFC, 0x02, 0x02, 0x02, 0x02, 0xFC, 0x0C, 0x10, 0x10, 0x10, 0x10, 0x0C, // 48
-    0x08, 0x04, 0xFE, 0x00, 0x00, 0x1C, // 49
-    0x0C, 0x02, 0x02, 0x82, 0x42, 0x3C, 0x10, 0x18, 0x14, 0x10, 0x10, 0x10, // 50
-    0x0C, 0x02, 0x22, 0x22, 0x22, 0xDC, 0x0C, 0x10, 0x10, 0x10, 0x10, 0x0C, // 51
-    0x80, 0x40, 0x30, 0x08, 0x04, 0xFE, 0x00, 0x04, 0x04, 0x04, 0x04, 0x04, 0x1C, 0x04, // 52
-    0x38, 0x16, 0x12, 0x12, 0x12, 0xE2, 0x0C, 0x10, 0x10, 0x10, 0x18, 0x04, // 53
-    0xF8, 0x44, 0x22, 0x22, 0x22, 0xC4, 0x0C, 0x10, 0x10, 0x10, 0x10, 0x0C, // 54
-    0x02, 0x02, 0x02, 0xE2, 0x1A, 0x06, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, // 55
-    0xDC, 0x22, 0x22, 0x22, 0x22, 0xDC, 0x0C, 0x10, 0x10, 0x10, 0x10, 0x0C, // 56
-    0x3C, 0x42, 0x42, 0x42, 0x22, 0xFC, 0x08, 0x10, 0x10, 0x10, 0x08, 0x04, // 57
-    0x08, 0x10, // 58
-    0x08, 0x70, // 59
-    0x40, 0xA0, 0xA0, 0x10, 0x10, 0x08, 0x00, 0x00, 0x00, 0x04, 0x04, 0x08, // 60
-    0x90, 0x90, 0x90, 0x90, 0x90, 0x90, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 61
-    0x08, 0x10, 0x10, 0xA0, 0xA0, 0x40, 0x08, 0x04, 0x04, 0x00, 0x00, 0x00, // 62
-    0x0C, 0x02, 0x82, 0x42, 0x22, 0x1C, 0x00, 0x00, 0x14, 0x00, 0x00, 0x00, // 63
-    0xE0, 0x18, 0x04, 0xC4, 0x22, 0x12, 0x12, 0x12, 0xA2, 0x72, 0x04, 0x08, 0xF0, 0x0C, 0x30, 0x40, 0x4C, 0x90, 0x90, 0x90, 0x88, 0x9C, 0x90, 0x50, 0x4C, 0x20, // 64
-    0x00, 0x80, 0xE0, 0x9C, 0x82, 0x9C, 0xE0, 0x80, 0x00, 0x18, 0x04, 0x00, 0x00, 0x00, 0x00, 0x00, 0x04, 0x18, // 65
-    0xFE, 0x22, 0x22, 0x22, 0x22, 0x22, 0xDC, 0x1C, 0x10, 0x10, 0x10, 0x10, 0x10, 0x0C, // 66
-    0xF8, 0x04, 0x02, 0x02, 0x02, 0x02, 0x04, 0x08, 0x04, 0x08, 0x10, 0x10, 0x10, 0x10, 0x08, 0x04, // 67
-    0xFE, 0x02, 0x02, 0x02, 0x02, 0x02, 0x04, 0xF8, 0x1C, 0x10, 0x10, 0x10, 0x10, 0x10, 0x08, 0x04, // 68
-    0xFE, 0x22, 0x22, 0x22, 0x22, 0x22, 0x22, 0x1C, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, // 69
-    0xFE, 0x22, 0x22, 0x22, 0x22, 0x22, 0x02, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 70
-    0xF8, 0x04, 0x02, 0x02, 0x02, 0x42, 0x42, 0x44, 0xC8, 0x04, 0x08, 0x10, 0x10, 0x10, 0x10, 0x10, 0x08, 0x04, // 71
-    0xFE, 0x20, 0x20, 0x20, 0x20, 0x20, 0xFE, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, // 72
-    0xFE, 0x1C, // 73
-    0x00, 0x00, 0x00, 0x00, 0xFE, 0x0C, 0x10, 0x10, 0x10, 0x0C, // 74
-    0xFE, 0x80, 0x40, 0x20, 0x50, 0x88, 0x04, 0x02, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x04, 0x08, 0x10, // 75
-    0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, // 76
-    0xFE, 0x0C, 0x30, 0xC0, 0x00, 0xC0, 0x30, 0x0C, 0xFE, 0x1C, 0x00, 0x00, 0x04, 0x18, 0x04, 0x00, 0x00, 0x1C, // 77
-    0xFE, 0x04, 0x18, 0x60, 0x80, 0x00, 0xFE, 0x1C, 0x00, 0x00, 0x00, 0x04, 0x08, 0x1C, // 78
-    0xF8, 0x04, 0x02, 0x02, 0x02, 0x02, 0x02, 0x04, 0xF8, 0x04, 0x08, 0x10, 0x10, 0x10, 0x10, 0x10, 0x08, 0x04, // 79
-    0xFE, 0x42, 0x42, 0x42, 0x42, 0x42, 0x3C, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 80
-    0xF8, 0x04, 0x02, 0x02, 0x02, 0x02, 0x02, 0x04, 0xF8, 0x04, 0x08, 0x10, 0x10, 0x10, 0x14, 0x08, 0x1C, 0x10, // 81
-    0xFE, 0x42, 0x42, 0x42, 0xC2, 0x42, 0x42, 0x3C, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x04, 0x08, 0x10, // 82
-    0x1C, 0x22, 0x22, 0x22, 0x42, 0x42, 0x8C, 0x0C, 0x10, 0x10, 0x10, 0x10, 0x10, 0x0C, // 83
-    0x02, 0x02, 0x02, 0xFE, 0x02, 0x02, 0x02, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, // 84
-    0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFE, 0x04, 0x08, 0x10, 0x10, 0x10, 0x08, 0x04, // 85
-    0x06, 0x18, 0x60, 0x80, 0x00, 0x80, 0x60, 0x18, 0x06, 0x00, 0x00, 0x00, 0x04, 0x18, 0x04, 0x00, 0x00, 0x00, // 86
-    0x06, 0x38, 0xC0, 0x00, 0xC0, 0x3C, 0x02, 0x3C, 0xC0, 0x00, 0xC0, 0x38, 0x06, 0x00, 0x00, 0x04, 0x18, 0x04, 0x00, 0x00, 0x00, 0x04, 0x18, 0x04, 0x00, 0x00, // 87
-    0x02, 0x0C, 0x90, 0x60, 0x60, 0x90, 0x0C, 0x02, 0x10, 0x0C, 0x00, 0x00, 0x00, 0x04, 0x0C, 0x10, // 88
-    0x02, 0x04, 0x18, 0x20, 0xC0, 0x20, 0x18, 0x04, 0x02, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x00, // 89
-    0x00, 0x02, 0x82, 0x42, 0x22, 0x1A, 0x06, 0x02, 0x10, 0x18, 0x14, 0x10, 0x10, 0x10, 0x10, 0x10, // 90
-    0xFE, 0x02, 0xFC, 0x80, // 91
-    0x06, 0x38, 0xC0, 0x00, 0x00, 0x00, 0x04, 0x18, // 92
-    0x02, 0xFE, 0x80, 0xFC, // 93
-    0x20, 0x1C, 0x02, 0x1C, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, // 94
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, // 95
-    0x02, 0x04, 0x00, 0x00, // 96
-    0x10, 0x88, 0x48, 0x48, 0x48, 0xF0, 0x0C, 0x10, 0x10, 0x10, 0x08, 0x1C, // 97
-    0xFE, 0x10, 0x08, 0x08, 0x08, 0xF0, 0x1C, 0x08, 0x10, 0x10, 0x10, 0x0C, // 98
-    0xF0, 0x08, 0x08, 0x08, 0x10, 0x0C, 0x10, 0x10, 0x10, 0x08, // 99
-    0xF0, 0x08, 0x08, 0x08, 0x10, 0xFE, 0x0C, 0x10, 0x10, 0x10, 0x08, 0x1C, // 100
-    0xF0, 0x48, 0x48, 0x48, 0x48, 0x70, 0x0C, 0x10, 0x10, 0x10, 0x10, 0x08, // 101
-    0x08, 0xFC, 0x0A, 0x0A, 0x00, 0x1C, 0x00, 0x00, // 102
-    0xF0, 0x08, 0x08, 0x08, 0x10, 0xF8, 0x4C, 0x90, 0x90, 0x90, 0x88, 0x7C, // 103
-    0xFE, 0x10, 0x08, 0x08, 0x08, 0xF0, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1C, // 104
-    0xFA, 0x1C, // 105
-    0x00, 0xFA, 0x80, 0x7C, // 106
-    0xFE, 0x80, 0x40, 0xA0, 0x10, 0x08, 0x1C, 0x00, 0x00, 0x00, 0x0C, 0x10, // 107
-    0xFE, 0x1C, // 108
-    0xF8, 0x10, 0x08, 0x08, 0xF0, 0x10, 0x08, 0x08, 0xF0, 0x1C, 0x00, 0x00, 0x00, 0x1C, 0x00, 0x00, 0x00, 0x1C, // 109
-    0xF8, 0x10, 0x08, 0x08, 0x08, 0xF0, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1C, // 110
-    0xF0, 0x08, 0x08, 0x08, 0x08, 0xF0, 0x0C, 0x10, 0x10, 0x10, 0x10, 0x0C, // 111
-    0xF8, 0x10, 0x08, 0x08, 0x08, 0xF0, 0xFC, 0x08, 0x10, 0x10, 0x10, 0x0C, // 112
-    0xF0, 0x08, 0x08, 0x08, 0x10, 0xF8, 0x0C, 0x10, 0x10, 0x10, 0x08, 0xFC, // 113
-    0xF8, 0x10, 0x08, 0x08, 0x1C, 0x00, 0x00, 0x00, // 114
-    0x30, 0x48, 0x48, 0x48, 0x90, 0x08, 0x10, 0x10, 0x10, 0x0C, // 115
-    0x08, 0xFE, 0x08, 0x08, 0x00, 0x1C, 0x10, 0x10, // 116
-    0xF8, 0x00, 0x00, 0x00, 0x00, 0xF8, 0x0C, 0x10, 0x10, 0x10, 0x08, 0x1C, // 117
-    0x18, 0x60, 0x80, 0x00, 0x80, 0x60, 0x18, 0x00, 0x00, 0x04, 0x18, 0x04, 0x00, 0x00, // 118
-    0x18, 0xE0, 0x00, 0xE0, 0x18, 0xE0, 0x00, 0xE0, 0x18, 0x00, 0x04, 0x18, 0x04, 0x00, 0x04, 0x18, 0x04, 0x00, // 119
-    0x08, 0x30, 0xC0, 0xC0, 0x30, 0x08, 0x10, 0x0C, 0x00, 0x00, 0x0C, 0x10, // 120
-    0x18, 0x60, 0x80, 0x00, 0x80, 0x60, 0x18, 0x00, 0x80, 0x8C, 0x70, 0x0C, 0x00, 0x00, // 121
-    0x08, 0x08, 0x88, 0x68, 0x18, 0x08, 0x10, 0x18, 0x14, 0x10, 0x10, 0x10, // 122
-    0x80, 0x7C, 0x02, 0x00, 0x7C, 0x80, // 123
-    0xFE, 0xFC, // 124
-    0x02, 0x7C, 0x80, 0x80, 0x7C, 0x00, // 125
-    0x40, 0x20, 0x20, 0x60, 0x40, 0x40, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 126
-    0xFC, 0x04, 0x04, 0x04, 0x04, 0x04, 0xFC, 0x1C, 0x10, 0x10, 0x10, 0x10, 0x10, 0x1C // 127
-    
-};
-
-#endif
diff --git a/STM32F1/libraries/ILI9341_due_STM/fonts/Arial_bold_14.h b/STM32F1/libraries/ILI9341_due_STM/fonts/Arial_bold_14.h
deleted file mode 100644
index bf634c6af..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/fonts/Arial_bold_14.h
+++ /dev/null
@@ -1,167 +0,0 @@
-
-
-/*
- *
- * Arial Bold 14
- *
- * created with FontCreator
- * written by F. Maximilian Thiele
- *
- * http://www.apetech.de/fontCreator
- * me@apetech.de
- *
- * File Name           : arial_bold_14
- * Date                : 29.01.2005
- * Font size in bytes  : 8712
- * Font width          : 10
- * Font height         : 14
- * Font first char     : 32
- * Font last char      : 128
- * Font used chars     : 96
- *
- * The font data are defined as
- *
- * struct _FONT_ {
- *     uint16_t   font_Size_in_Bytes_over_all_included_Size_it_self;
- *     uint8_t    font_Width_in_Pixel_for_fixed_drawing;
- *     uint8_t    font_Height_in_Pixel_for_all_characters;
- *     unit8_t    font_First_Char;
- *     uint8_t    font_Char_Count;
- *
- *     uint8_t    font_Char_Widths[font_Last_Char - font_First_Char +1];
- *                  // for each character the separate width in pixels,
- *                  // characters < 128 have an implicit virtual right empty row
- *
- *     uint8_t    font_data[];
- *                  // bit field of all characters
- */
-
-#include <inttypes.h>
-#include <avr/pgmspace.h>
-
-#ifndef ARIAL_BOLD_14_H
-#define ARIAL_BOLD_14_H
-
-#define ARIAL_BOLD_14_WIDTH 10
-#define ARIAL_BOLD_14_HEIGHT 14
-
-static const uint8_t Arial_bold_14[] PROGMEM = {
-    0x22, 0x08, // size
-    0x0A, // width
-    0x0E, // height
-    0x20, // first char
-    0x60, // char count
-    
-    // char widths
-    0x04, 0x02, 0x05, 0x06, 0x07, 0x08, 0x09, 0x02, 0x03, 0x03, 
-    0x05, 0x08, 0x02, 0x04, 0x02, 0x04, 0x07, 0x04, 0x07, 0x07, 
-    0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x02, 0x02, 0x07, 0x07, 
-    0x07, 0x08, 0x0E, 0x09, 0x08, 0x08, 0x08, 0x07, 0x07, 0x09, 
-    0x08, 0x02, 0x07, 0x08, 0x07, 0x0B, 0x08, 0x09, 0x07, 0x09, 
-    0x09, 0x07, 0x08, 0x08, 0x09, 0x0D, 0x07, 0x08, 0x08, 0x04, 
-    0x04, 0x04, 0x06, 0x08, 0x03, 0x07, 0x07, 0x06, 0x07, 0x07, 
-    0x05, 0x07, 0x07, 0x02, 0x03, 0x06, 0x02, 0x0A, 0x07, 0x07, 
-    0x07, 0x07, 0x05, 0x06, 0x05, 0x07, 0x07, 0x0B, 0x06, 0x07, 
-    0x05, 0x05, 0x01, 0x05, 0x07, 0x08, 
-    
-    // font data
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 32
-    0xFE, 0xFE, 0x18, 0x18, // 33
-    0x1E, 0x1E, 0x00, 0x1E, 0x1E, 0x00, 0x00, 0x00, 0x00, 0x00, // 34
-    0x90, 0xF8, 0x9E, 0x90, 0xF8, 0x9E, 0x1C, 0x00, 0x00, 0x1C, 0x00, 0x00, // 35
-    0x18, 0x3C, 0x26, 0xFF, 0x66, 0xCC, 0x88, 0x04, 0x0C, 0x18, 0x3C, 0x18, 0x0C, 0x04, // 36
-    0x1C, 0x22, 0x1C, 0xC0, 0x30, 0x8E, 0x40, 0x80, 0x00, 0x00, 0x18, 0x04, 0x00, 0x0C, 0x10, 0x0C, // 37
-    0x80, 0xCC, 0x7E, 0x72, 0xF2, 0xDE, 0x0C, 0x80, 0x00, 0x0C, 0x1C, 0x10, 0x10, 0x10, 0x1C, 0x0C, 0x1C, 0x10, // 38
-    0x1E, 0x1E, 0x00, 0x00, // 39
-    0xF0, 0xFC, 0x06, 0x1C, 0x7C, 0xC0, // 40
-    0x06, 0xFC, 0xF0, 0xC0, 0x7C, 0x1C, // 41
-    0x14, 0x14, 0x0E, 0x14, 0x14, 0x00, 0x00, 0x00, 0x00, 0x00, // 42
-    0x60, 0x60, 0x60, 0xFC, 0xFC, 0x60, 0x60, 0x60, 0x00, 0x00, 0x00, 0x0C, 0x0C, 0x00, 0x00, 0x00, // 43
-    0x00, 0x00, 0x58, 0x38, // 44
-    0xC0, 0xC0, 0xC0, 0xC0, 0x00, 0x00, 0x00, 0x00, // 45
-    0x00, 0x00, 0x18, 0x18, // 46
-    0x00, 0xC0, 0x38, 0x06, 0x18, 0x04, 0x00, 0x00, // 47
-    0xF8, 0xFC, 0x0E, 0x06, 0x0E, 0xFC, 0xF8, 0x04, 0x0C, 0x1C, 0x18, 0x1C, 0x0C, 0x04, // 48
-    0x18, 0x0C, 0xFE, 0xFE, 0x00, 0x00, 0x1C, 0x1C, // 49
-    0x18, 0x1C, 0x86, 0xC6, 0x66, 0x3E, 0x1C, 0x18, 0x1C, 0x1C, 0x18, 0x18, 0x18, 0x18, // 50
-    0x88, 0x8C, 0x06, 0x26, 0x26, 0xFE, 0xDC, 0x04, 0x0C, 0x1C, 0x18, 0x18, 0x0C, 0x04, // 51
-    0xC0, 0xE0, 0xB8, 0x8C, 0xFE, 0xFE, 0x80, 0x04, 0x04, 0x04, 0x04, 0x1C, 0x1C, 0x04, // 52
-    0x70, 0x7E, 0x3E, 0x36, 0x36, 0xF6, 0xC6, 0x0C, 0x1C, 0x18, 0x18, 0x18, 0x0C, 0x04, // 53
-    0xF8, 0xFC, 0x6E, 0x66, 0x66, 0xEE, 0xCC, 0x04, 0x0C, 0x18, 0x18, 0x18, 0x1C, 0x0C, // 54
-    0x06, 0x06, 0x06, 0xE6, 0x76, 0x1E, 0x06, 0x00, 0x00, 0x1C, 0x1C, 0x00, 0x00, 0x00, // 55
-    0x9C, 0xFE, 0x66, 0x66, 0x66, 0xFE, 0x9C, 0x0C, 0x1C, 0x18, 0x18, 0x18, 0x1C, 0x0C, // 56
-    0x3C, 0x7E, 0x66, 0x66, 0x66, 0xFC, 0xF8, 0x0C, 0x1C, 0x18, 0x18, 0x1C, 0x0C, 0x04, // 57
-    0x18, 0x18, 0x18, 0x18, // 58
-    0x18, 0x18, 0x58, 0x38, // 59
-    0x60, 0x60, 0xF0, 0xF0, 0x98, 0x98, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x04, 0x04, 0x0C, // 60
-    0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0xD8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 61
-    0x0C, 0x98, 0x98, 0xF0, 0xF0, 0x60, 0x60, 0x0C, 0x04, 0x04, 0x00, 0x00, 0x00, 0x00, // 62
-    0x08, 0x0C, 0x06, 0xC6, 0xE6, 0x76, 0x3C, 0x18, 0x00, 0x00, 0x00, 0x18, 0x18, 0x00, 0x00, 0x00, // 63
-    0xE0, 0x30, 0x08, 0xC4, 0xF6, 0x3A, 0x1A, 0x1A, 0xF2, 0xFA, 0x7E, 0x04, 0x08, 0xF0, 0x0C, 0x30, 0x60, 0x4C, 0x9C, 0x98, 0x98, 0x8C, 0x9C, 0x9C, 0x90, 0x48, 0x4C, 0x20, // 64
-    0x00, 0xC0, 0xF8, 0xBE, 0x86, 0xBE, 0xF8, 0xC0, 0x00, 0x18, 0x1C, 0x04, 0x04, 0x04, 0x04, 0x04, 0x1C, 0x18, // 65
-    0xFE, 0xFE, 0x66, 0x66, 0x66, 0x66, 0xFE, 0xDC, 0x1C, 0x1C, 0x18, 0x18, 0x18, 0x18, 0x1C, 0x0C, // 66
-    0xF8, 0xFC, 0x0E, 0x06, 0x06, 0x0E, 0x9C, 0x08, 0x04, 0x0C, 0x1C, 0x18, 0x18, 0x1C, 0x0C, 0x04, // 67
-    0xFE, 0xFE, 0x06, 0x06, 0x06, 0x0E, 0xFC, 0xF8, 0x1C, 0x1C, 0x18, 0x18, 0x18, 0x1C, 0x0C, 0x04, // 68
-    0xFE, 0xFE, 0x66, 0x66, 0x66, 0x66, 0x66, 0x1C, 0x1C, 0x18, 0x18, 0x18, 0x18, 0x18, // 69
-    0xFE, 0xFE, 0x66, 0x66, 0x66, 0x66, 0x06, 0x1C, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, // 70
-    0xF8, 0xFC, 0x0E, 0x06, 0x06, 0xC6, 0xCE, 0xDC, 0xC8, 0x04, 0x0C, 0x1C, 0x18, 0x18, 0x18, 0x18, 0x0C, 0x04, // 71
-    0xFE, 0xFE, 0x60, 0x60, 0x60, 0x60, 0xFE, 0xFE, 0x1C, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x1C, // 72
-    0xFE, 0xFE, 0x1C, 0x1C, // 73
-    0x80, 0x80, 0x00, 0x00, 0x00, 0xFE, 0xFE, 0x0C, 0x1C, 0x18, 0x18, 0x18, 0x1C, 0x0C, // 74
-    0xFE, 0xFE, 0x60, 0x30, 0x78, 0xEC, 0x86, 0x02, 0x1C, 0x1C, 0x00, 0x00, 0x00, 0x04, 0x1C, 0x18, // 75
-    0xFE, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x1C, 0x18, 0x18, 0x18, 0x18, 0x18, // 76
-    0xFE, 0xFE, 0x0E, 0x7C, 0xE0, 0x00, 0xE0, 0x7C, 0x0E, 0xFE, 0xFE, 0x1C, 0x1C, 0x00, 0x00, 0x0C, 0x1C, 0x0C, 0x00, 0x00, 0x1C, 0x1C, // 77
-    0xFE, 0xFE, 0x1C, 0x78, 0xE0, 0x80, 0xFE, 0xFE, 0x1C, 0x1C, 0x00, 0x00, 0x04, 0x0C, 0x1C, 0x1C, // 78
-    0xF8, 0xFC, 0x0E, 0x06, 0x06, 0x06, 0x0E, 0xFC, 0xF8, 0x04, 0x0C, 0x1C, 0x18, 0x18, 0x18, 0x1C, 0x0C, 0x04, // 79
-    0xFE, 0xFE, 0x66, 0x66, 0x66, 0x7E, 0x3C, 0x1C, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, // 80
-    0xF8, 0xFC, 0x0E, 0x06, 0x86, 0x06, 0x0E, 0xFC, 0xF8, 0x04, 0x0C, 0x1C, 0x18, 0x18, 0x1C, 0x0C, 0x1C, 0x24, // 81
-    0xFE, 0xFE, 0x66, 0x66, 0xE6, 0xE6, 0xBE, 0x1C, 0x00, 0x1C, 0x1C, 0x00, 0x00, 0x00, 0x0C, 0x1C, 0x18, 0x10, // 82
-    0x3C, 0x7E, 0x66, 0x66, 0x66, 0xEE, 0xCC, 0x0C, 0x1C, 0x18, 0x18, 0x18, 0x1C, 0x0C, // 83
-    0x06, 0x06, 0x06, 0xFE, 0xFE, 0x06, 0x06, 0x06, 0x00, 0x00, 0x00, 0x1C, 0x1C, 0x00, 0x00, 0x00, // 84
-    0xFE, 0xFE, 0x00, 0x00, 0x00, 0x00, 0xFE, 0xFE, 0x04, 0x0C, 0x1C, 0x18, 0x18, 0x1C, 0x0C, 0x04, // 85
-    0x02, 0x1E, 0xFC, 0xE0, 0x00, 0xE0, 0xFC, 0x1E, 0x02, 0x00, 0x00, 0x00, 0x1C, 0x1C, 0x1C, 0x00, 0x00, 0x00, // 86
-    0x06, 0xFE, 0xF8, 0x00, 0xF0, 0xFE, 0x0E, 0xFE, 0xF0, 0x00, 0xF8, 0xFE, 0x06, 0x00, 0x00, 0x1C, 0x1C, 0x1C, 0x00, 0x00, 0x00, 0x1C, 0x1C, 0x1C, 0x00, 0x00, // 87
-    0x06, 0x0E, 0xF8, 0xF0, 0xF8, 0x0E, 0x06, 0x18, 0x1C, 0x04, 0x00, 0x04, 0x1C, 0x18, // 88
-    0x06, 0x0E, 0x38, 0xF0, 0xF0, 0x38, 0x0E, 0x06, 0x00, 0x00, 0x00, 0x1C, 0x1C, 0x00, 0x00, 0x00, // 89
-    0x06, 0x06, 0x86, 0xE6, 0x76, 0x1E, 0x0E, 0x06, 0x18, 0x1C, 0x1C, 0x18, 0x18, 0x18, 0x18, 0x18, // 90
-    0xFE, 0xFE, 0x06, 0x06, 0xFC, 0xFC, 0xC0, 0xC0, // 91
-    0x06, 0x38, 0xC0, 0x00, 0x00, 0x00, 0x04, 0x18, // 92
-    0x06, 0x06, 0xFE, 0xFE, 0xC0, 0xC0, 0xFC, 0xFC, // 93
-    0x20, 0x38, 0x0E, 0x0E, 0x38, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 94
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, // 95
-    0x02, 0x06, 0x04, 0x00, 0x00, 0x00, // 96
-    0x10, 0x98, 0xD8, 0x58, 0xF8, 0xF0, 0x00, 0x0C, 0x1C, 0x18, 0x18, 0x0C, 0x1C, 0x10, // 97
-    0xFE, 0xFE, 0x30, 0x18, 0x38, 0xF0, 0xE0, 0x1C, 0x1C, 0x0C, 0x18, 0x1C, 0x0C, 0x04, // 98
-    0xE0, 0xF0, 0x18, 0x18, 0x38, 0x30, 0x04, 0x0C, 0x18, 0x18, 0x1C, 0x0C, // 99
-    0xE0, 0xF0, 0x38, 0x18, 0x30, 0xFE, 0xFE, 0x04, 0x0C, 0x1C, 0x18, 0x0C, 0x1C, 0x1C, // 100
-    0xE0, 0xF0, 0xD8, 0xD8, 0xD8, 0xF0, 0xE0, 0x04, 0x0C, 0x18, 0x18, 0x18, 0x18, 0x08, // 101
-    0x18, 0xFC, 0xFE, 0x1A, 0x1A, 0x00, 0x1C, 0x1C, 0x00, 0x00, // 102
-    0xE0, 0xF0, 0x38, 0x18, 0x30, 0xF8, 0xF8, 0x64, 0xEC, 0xDC, 0xD8, 0xCC, 0xFC, 0x7C, // 103
-    0xFE, 0xFE, 0x30, 0x18, 0x18, 0xF8, 0xF0, 0x1C, 0x1C, 0x00, 0x00, 0x00, 0x1C, 0x1C, // 104
-    0xFA, 0xFA, 0x1C, 0x1C, // 105
-    0x00, 0xFA, 0xFA, 0xC0, 0xFC, 0x7C, // 106
-    0xFE, 0xFE, 0xE0, 0xF0, 0x98, 0x08, 0x1C, 0x1C, 0x00, 0x04, 0x1C, 0x18, // 107
-    0xFE, 0xFE, 0x1C, 0x1C, // 108
-    0xF8, 0xF8, 0x10, 0x18, 0xF8, 0xF0, 0x18, 0x18, 0xF8, 0xF0, 0x1C, 0x1C, 0x00, 0x00, 0x1C, 0x1C, 0x00, 0x00, 0x1C, 0x1C, // 109
-    0xF8, 0xF8, 0x30, 0x18, 0x18, 0xF8, 0xF0, 0x1C, 0x1C, 0x00, 0x00, 0x00, 0x1C, 0x1C, // 110
-    0xE0, 0xF0, 0x38, 0x18, 0x38, 0xF0, 0xE0, 0x04, 0x0C, 0x1C, 0x18, 0x1C, 0x0C, 0x04, // 111
-    0xF8, 0xF8, 0x30, 0x18, 0x38, 0xF0, 0xE0, 0xFC, 0xFC, 0x0C, 0x18, 0x1C, 0x0C, 0x04, // 112
-    0xE0, 0xF0, 0x38, 0x18, 0x30, 0xF8, 0xF8, 0x04, 0x0C, 0x1C, 0x18, 0x0C, 0xFC, 0xFC, // 113
-    0xF8, 0xF8, 0x30, 0x18, 0x18, 0x1C, 0x1C, 0x00, 0x00, 0x00, // 114
-    0x70, 0xF8, 0xD8, 0xD8, 0xD8, 0x90, 0x08, 0x18, 0x18, 0x18, 0x1C, 0x0C, // 115
-    0x18, 0xFC, 0xFE, 0x18, 0x18, 0x00, 0x0C, 0x1C, 0x18, 0x18, // 116
-    0xF8, 0xF8, 0x00, 0x00, 0x00, 0xF8, 0xF8, 0x0C, 0x1C, 0x18, 0x18, 0x0C, 0x1C, 0x1C, // 117
-    0x38, 0xF8, 0xC0, 0x00, 0xC0, 0xF8, 0x38, 0x00, 0x00, 0x1C, 0x1C, 0x1C, 0x00, 0x00, // 118
-    0x18, 0xF8, 0xE0, 0x00, 0xF0, 0x38, 0xF0, 0x00, 0xE0, 0xF8, 0x18, 0x00, 0x00, 0x1C, 0x1C, 0x0C, 0x00, 0x0C, 0x1C, 0x1C, 0x00, 0x00, // 119
-    0x18, 0x38, 0xE0, 0xE0, 0x38, 0x18, 0x18, 0x1C, 0x04, 0x04, 0x1C, 0x18, // 120
-    0x18, 0xF8, 0xE0, 0x00, 0xE0, 0xF8, 0x18, 0x00, 0x84, 0xFC, 0xF8, 0x3C, 0x04, 0x00, // 121
-    0x18, 0x98, 0xD8, 0x78, 0x38, 0x1C, 0x1C, 0x18, 0x18, 0x18, // 122
-    0x80, 0xFC, 0x7E, 0x06, 0x06, 0x00, 0x7C, 0xFC, 0xC0, 0xC0, // 123
-    0xFE, 0xFC, // 124
-    0x06, 0x06, 0x7E, 0xFC, 0x80, 0xC0, 0xC0, 0xFC, 0x7C, 0x00, // 125
-    0x60, 0x30, 0x30, 0x70, 0x60, 0x60, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 126
-    0xFE, 0x02, 0x02, 0x02, 0x02, 0x02, 0x02, 0xFE, 0x1C, 0x10, 0x10, 0x10, 0x10, 0x10, 0x10, 0x1C // 127
-    
-};
-
-#endif
diff --git a/STM32F1/libraries/ILI9341_due_STM/fonts/Corsiva_12.h b/STM32F1/libraries/ILI9341_due_STM/fonts/Corsiva_12.h
deleted file mode 100644
index 74ee8d681..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/fonts/Corsiva_12.h
+++ /dev/null
@@ -1,167 +0,0 @@
-
-
-/*
- *
- * Corsiva_12
- *
- * created with FontCreator
- * written by F. Maximilian Thiele
- *
- * http://www.apetech.de/fontCreator
- * me@apetech.de
- *
- * File Name           : corsiva_12.h
- * Date                : 29.01.2005
- * Font size in bytes  : 5690
- * Font width          : 10
- * Font height         : 11
- * Font first char     : 32
- * Font last char      : 128
- * Font used chars     : 96
- *
- * The font data are defined as
- *
- * struct _FONT_ {
- *     uint16_t   font_Size_in_Bytes_over_all_included_Size_it_self;
- *     uint8_t    font_Width_in_Pixel_for_fixed_drawing;
- *     uint8_t    font_Height_in_Pixel_for_all_characters;
- *     unit8_t    font_First_Char;
- *     uint8_t    font_Char_Count;
- *
- *     uint8_t    font_Char_Widths[font_Last_Char - font_First_Char +1];
- *                  // for each character the separate width in pixels,
- *                  // characters < 128 have an implicit virtual right empty row
- *
- *     uint8_t    font_data[];
- *                  // bit field of all characters
- */
-
-#include <inttypes.h>
-#include <avr/pgmspace.h>
-
-#ifndef CORSIVA_12_H
-#define CORSIVA_12_H
-
-#define CORSIVA_12_WIDTH 10
-#define CORSIVA_12_HEIGHT 11
-
-static const uint8_t Corsiva_12[] PROGMEM = {
-    0x16, 0x3A, // size
-    0x0A, // width
-    0x0B, // height
-    0x20, // first char
-    0x60, // char count
-    
-    // char widths
-    0x03, 0x02, 0x02, 0x06, 0x05, 0x07, 0x09, 0x01, 0x03, 0x04, 
-    0x02, 0x05, 0x02, 0x03, 0x01, 0x05, 0x05, 0x04, 0x05, 0x04, 
-    0x05, 0x06, 0x05, 0x05, 0x05, 0x05, 0x02, 0x03, 0x05, 0x05, 
-    0x05, 0x04, 0x07, 0x07, 0x07, 0x06, 0x08, 0x07, 0x07, 0x07, 
-    0x0A, 0x05, 0x06, 0x09, 0x07, 0x09, 0x0A, 0x06, 0x07, 0x09, 
-    0x09, 0x06, 0x08, 0x08, 0x08, 0x0B, 0x09, 0x09, 0x07, 0x03, 
-    0x03, 0x04, 0x03, 0x06, 0x02, 0x04, 0x04, 0x04, 0x06, 0x04, 
-    0x06, 0x06, 0x04, 0x03, 0x04, 0x06, 0x03, 0x06, 0x04, 0x04, 
-    0x05, 0x05, 0x04, 0x04, 0x04, 0x04, 0x06, 0x08, 0x07, 0x05, 
-    0x06, 0x03, 0x01, 0x04, 0x05, 0x06, 
-    
-    // font data
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 32
-    0x80, 0x3E, 0x00, 0x00, // 33
-    0x08, 0x06, 0x00, 0x00, // 34
-    0xA0, 0x78, 0xAE, 0x78, 0x2E, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 35
-    0x80, 0x8C, 0xF2, 0xBF, 0x62, 0x00, 0x20, 0x00, 0x00, 0x00, // 36
-    0x1C, 0x92, 0x7E, 0x0C, 0xE2, 0x90, 0x70, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 37
-    0x70, 0xC8, 0xA8, 0xB8, 0x6C, 0xBE, 0x02, 0xC2, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x00, 0x00, // 38
-    0x08, 0x00, // 39
-    0xE0, 0x18, 0x06, 0x60, 0x80, 0x00, // 40
-    0x00, 0x00, 0xC3, 0x3C, 0x40, 0x20, 0x00, 0x00, // 41
-    0x0C, 0x0F, 0x00, 0x00, // 42
-    0x10, 0x10, 0x7C, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 43
-    0x00, 0x80, 0x40, 0x20, // 44
-    0x20, 0x20, 0x20, 0x00, 0x00, 0x00, // 45
-    0x80, 0x00, // 46
-    0x00, 0xC0, 0x30, 0x0C, 0x03, 0x60, 0x00, 0x00, 0x00, 0x00, // 47
-    0x78, 0x84, 0x82, 0x42, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, // 48
-    0x80, 0x88, 0xFC, 0x86, 0x00, 0x00, 0x00, 0x00, // 49
-    0xC0, 0xC4, 0xA2, 0x92, 0x4E, 0x00, 0x00, 0x00, 0x00, 0x00, // 50
-    0xC0, 0x80, 0xDA, 0x76, 0x00, 0x00, 0x00, 0x00, // 51
-    0x20, 0x30, 0xA8, 0x7E, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, // 52
-    0x80, 0x80, 0x84, 0x4A, 0x32, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 53
-    0x70, 0xAC, 0x94, 0x72, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, // 54
-    0xC4, 0x32, 0x0A, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, // 55
-    0xE0, 0xAC, 0x92, 0x6A, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, // 56
-    0x80, 0x9C, 0x52, 0x72, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, // 57
-    0x80, 0x08, 0x00, 0x00, // 58
-    0x00, 0x80, 0x08, 0x40, 0x20, 0x00, // 59
-    0x30, 0x30, 0x48, 0x48, 0x48, 0x00, 0x00, 0x00, 0x00, 0x00, // 60
-    0x28, 0x28, 0x28, 0x28, 0x28, 0x00, 0x00, 0x00, 0x00, 0x00, // 61
-    0x48, 0x48, 0x48, 0x30, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, // 62
-    0x80, 0x36, 0x12, 0x0C, 0x00, 0x00, 0x00, 0x00, // 63
-    0x70, 0xCC, 0xB4, 0xAA, 0xBA, 0x62, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 64
-    0x00, 0x80, 0x4C, 0x32, 0x2E, 0xFE, 0x82, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 65
-    0x38, 0x24, 0x86, 0xFA, 0x8E, 0x8A, 0x76, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 66
-    0xF0, 0x8C, 0x04, 0x02, 0x82, 0x0C, 0x00, 0x20, 0x20, 0x20, 0x00, 0x00, // 67
-    0x38, 0x4C, 0x86, 0xEA, 0x9A, 0x82, 0x46, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 68
-    0x38, 0x84, 0xE2, 0x9E, 0x92, 0xBA, 0xC6, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 69
-    0x1C, 0x86, 0xE2, 0x9E, 0x12, 0x3A, 0x06, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 70
-    0x70, 0x8C, 0x84, 0x82, 0xD2, 0x32, 0x16, 0x00, 0x80, 0x80, 0xC0, 0x20, 0x00, 0x00, // 71
-    0xC0, 0x8C, 0xC2, 0x3A, 0x16, 0x90, 0xF8, 0x86, 0x01, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 72
-    0x80, 0xC0, 0xFA, 0x06, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, // 73
-    0x00, 0x00, 0x0C, 0xC2, 0x3A, 0x06, 0x60, 0x40, 0x40, 0x20, 0x00, 0x00, // 74
-    0x8C, 0x82, 0xF2, 0x1E, 0x78, 0x88, 0x06, 0x02, 0x02, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x40, 0x40, // 75
-    0x80, 0xC0, 0xB8, 0x84, 0x82, 0x82, 0xC0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 76
-    0x80, 0x9C, 0x62, 0x1E, 0xF8, 0x60, 0x90, 0xFC, 0x0E, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 77
-    0x80, 0x0C, 0xE2, 0x12, 0x0E, 0xF0, 0x70, 0x0C, 0x02, 0x02, 0x20, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 78
-    0x78, 0xC4, 0x82, 0x82, 0x46, 0x3C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 79
-    0x38, 0xCC, 0x86, 0xFA, 0x92, 0x12, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 80
-    0x78, 0xC4, 0x82, 0x82, 0x42, 0x26, 0x1C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x60, 0xC0, 0x80, 0x80, 0x40, // 81
-    0x38, 0xA4, 0x86, 0xFA, 0x32, 0xD2, 0x0C, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x40, 0x40, // 82
-    0x80, 0x00, 0x0C, 0x92, 0xE2, 0x0E, 0x00, 0x20, 0x20, 0x20, 0x00, 0x00, // 83
-    0x1C, 0x86, 0x82, 0xF2, 0x8E, 0x02, 0x02, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 84
-    0x0C, 0x7A, 0x86, 0x80, 0x80, 0x40, 0x30, 0x0F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 85
-    0x0C, 0x06, 0xFE, 0x42, 0x20, 0x10, 0x0C, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 86
-    0x0C, 0x06, 0xFE, 0x32, 0x08, 0x04, 0xFE, 0x20, 0x10, 0x08, 0x07, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 87
-    0x00, 0x80, 0x40, 0x22, 0x1E, 0xF4, 0x82, 0x01, 0x01, 0x20, 0x20, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 88
-    0x1C, 0x04, 0x82, 0xC6, 0xBC, 0x8C, 0x02, 0x02, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 89
-    0x80, 0xC0, 0xA6, 0x92, 0x8A, 0x86, 0xC2, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 90
-    0x00, 0xF0, 0x0F, 0xC0, 0xA0, 0x00, // 91
-    0x07, 0xFC, 0x80, 0x00, 0x00, 0x60, // 92
-    0x00, 0x00, 0xF1, 0x0F, 0x80, 0xE0, 0x00, 0x00, // 93
-    0x04, 0x02, 0x04, 0x00, 0x00, 0x00, // 94
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x40, 0x40, 0x40, 0x40, 0x40, 0x40, // 95
-    0x01, 0x02, 0x00, 0x00, // 96
-    0xE0, 0x90, 0xC8, 0xB8, 0x00, 0x00, 0x00, 0x00, // 97
-    0xE0, 0x9E, 0x49, 0x39, 0x00, 0x00, 0x00, 0x00, // 98
-    0xE0, 0x90, 0x88, 0x48, 0x00, 0x00, 0x00, 0x00, // 99
-    0xE0, 0x90, 0x48, 0xF8, 0x4E, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 100
-    0xF0, 0xB0, 0xA8, 0x58, 0x00, 0x00, 0x00, 0x00, // 101
-    0x00, 0x90, 0x78, 0x16, 0x01, 0x01, 0x40, 0x20, 0x00, 0x00, 0x00, 0x00, // 102
-    0x00, 0xE0, 0x90, 0x88, 0xE8, 0x18, 0xE0, 0x80, 0x80, 0xC0, 0x60, 0x00, // 103
-    0xE0, 0x1E, 0xD1, 0xB9, 0x00, 0x00, 0x00, 0x00, // 104
-    0xE0, 0x38, 0x02, 0x00, 0x00, 0x00, // 105
-    0x00, 0x90, 0x78, 0x02, 0x80, 0x60, 0x00, 0x00, // 106
-    0xE0, 0x3E, 0xE9, 0x19, 0x00, 0x00, 0x00, 0x00, 0x00, 0x60, 0x40, 0x40, // 107
-    0xE0, 0x9C, 0x42, 0x00, 0x00, 0x00, // 108
-    0xC8, 0x38, 0xD0, 0x38, 0xF0, 0x98, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 109
-    0xE8, 0x18, 0xD0, 0xB8, 0x00, 0x00, 0x00, 0x00, // 110
-    0xF0, 0x88, 0xC8, 0x38, 0x00, 0x00, 0x00, 0x00, // 111
-    0x88, 0xF8, 0x90, 0x48, 0x38, 0xE0, 0x80, 0x00, 0x00, 0x00, // 112
-    0xE0, 0x90, 0x88, 0xE8, 0x18, 0x00, 0x80, 0xC0, 0xA0, 0x00, // 113
-    0xC8, 0x38, 0x10, 0x08, 0x00, 0x00, 0x00, 0x00, // 114
-    0xC0, 0x98, 0xE8, 0x08, 0x00, 0x00, 0x00, 0x00, // 115
-    0xE8, 0x9C, 0x88, 0x40, 0x00, 0x00, 0x00, 0x00, // 116
-    0xE8, 0x98, 0xE0, 0x98, 0x00, 0x00, 0x00, 0x00, // 117
-    0x10, 0x08, 0xF8, 0x88, 0x60, 0x18, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 118
-    0x10, 0x08, 0xF8, 0x88, 0x40, 0xF8, 0x40, 0x38, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 119
-    0x80, 0xD0, 0x58, 0xF0, 0x10, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x20, 0x40, 0x60, // 120
-    0x10, 0x18, 0xF0, 0xC0, 0x38, 0x80, 0x40, 0x20, 0x00, 0x00, // 121
-    0x80, 0xD8, 0xA8, 0x98, 0xD8, 0x08, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // 122
-    0xA0, 0xD8, 0x07, 0xE0, 0x80, 0x00, // 123
-    0xFF, 0xE0, // 124
-    0x00, 0x00, 0xD1, 0x2F, 0x80, 0xC0, 0x20, 0x00, // 125
-    0x08, 0x08, 0x18, 0x10, 0x10, 0x00, 0x00, 0x00, 0x00, 0x00, // 126
-    0xFF, 0x81, 0x81, 0x81, 0x81, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 127
-    
-};
-
-#endif
diff --git a/STM32F1/libraries/ILI9341_due_STM/fonts/SystemFont5x7.h b/STM32F1/libraries/ILI9341_due_STM/fonts/SystemFont5x7.h
deleted file mode 100644
index 8959af1ac..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/fonts/SystemFont5x7.h
+++ /dev/null
@@ -1,157 +0,0 @@
-/*
- *
- * System5x7
- *
- *
- * File Name           : System5x7.h
- * Date                : 28 Oct 2008
- * Font size in bytes  : 470
- * Font width          : 5
- * Font height         : 7
- * Font first char     : 32
- * Font last char      : 127
- * Font used chars     : 94
- *
- * The font data are defined as
- *
- * struct _FONT_ {
- *     uint16_t   font_Size_in_Bytes_over_all_included_Size_it_self;
- *     uint8_t    font_Width_in_Pixel_for_fixed_drawing;
- *     uint8_t    font_Height_in_Pixel_for_all_characters;
- *     unit8_t    font_First_Char;
- *     uint8_t    font_Char_Count;
- *
- *     uint8_t    font_Char_Widths[font_Last_Char - font_First_Char +1];
- *                  // for each character the separate width in pixels,
- *                  // characters < 128 have an implicit virtual right empty row
- *
- *     uint8_t    font_data[];
- *                  // bit field of all characters
- */
-
-#include <inttypes.h>
-#include <avr/pgmspace.h>
-
-#ifndef SYSTEM5x7_H
-#define SYSTEM5x7_H
-
-#define SYSTEM5x7_WIDTH 5
-#define SYSTEM5x7_HEIGHT 7
-
-/*
- * added to allow fontname to match header file name. 
- * as well as keep the old name for backward compability
- */
-
-#define SystemFont5x7 System5x7
-
-static const uint8_t System5x7[] PROGMEM = {
-    0x0, 0x0, // size of zero indicates fixed width font, actual length is width * height
-    0x05, // width
-    0x07, // height
-    0x20, // first char
-    0x60, // char count
-    
-    // Fixed width; char width table not used !!!!
-    
-    // font data
-    0x00, 0x00, 0x00, 0x00, 0x00,// (space)
-	0x00, 0x00, 0x5F, 0x00, 0x00,// !
-	0x00, 0x07, 0x00, 0x07, 0x00,// "
-	0x14, 0x7F, 0x14, 0x7F, 0x14,// #
-	0x24, 0x2A, 0x7F, 0x2A, 0x12,// $
-	0x23, 0x13, 0x08, 0x64, 0x62,// %
-	0x36, 0x49, 0x55, 0x22, 0x50,// &
-	0x00, 0x05, 0x03, 0x00, 0x00,// '
-	0x00, 0x1C, 0x22, 0x41, 0x00,// (
-	0x00, 0x41, 0x22, 0x1C, 0x00,// )
-	0x08, 0x2A, 0x1C, 0x2A, 0x08,// *
-	0x08, 0x08, 0x3E, 0x08, 0x08,// +
-	0x00, 0x50, 0x30, 0x00, 0x00,// ,
-	0x08, 0x08, 0x08, 0x08, 0x08,// -
-	0x00, 0x60, 0x60, 0x00, 0x00,// .
-	0x20, 0x10, 0x08, 0x04, 0x02,// /
-	0x3E, 0x51, 0x49, 0x45, 0x3E,// 0
-	0x00, 0x42, 0x7F, 0x40, 0x00,// 1
-	0x42, 0x61, 0x51, 0x49, 0x46,// 2
-	0x21, 0x41, 0x45, 0x4B, 0x31,// 3
-	0x18, 0x14, 0x12, 0x7F, 0x10,// 4
-	0x27, 0x45, 0x45, 0x45, 0x39,// 5
-	0x3C, 0x4A, 0x49, 0x49, 0x30,// 6
-	0x01, 0x71, 0x09, 0x05, 0x03,// 7
-	0x36, 0x49, 0x49, 0x49, 0x36,// 8
-	0x06, 0x49, 0x49, 0x29, 0x1E,// 9
-	0x00, 0x36, 0x36, 0x00, 0x00,// :
-	0x00, 0x56, 0x36, 0x00, 0x00,// ;
-	0x00, 0x08, 0x14, 0x22, 0x41,// <
-	0x14, 0x14, 0x14, 0x14, 0x14,// =
-	0x41, 0x22, 0x14, 0x08, 0x00,// >
-	0x02, 0x01, 0x51, 0x09, 0x06,// ?
-	0x32, 0x49, 0x79, 0x41, 0x3E,// @
-	0x7E, 0x11, 0x11, 0x11, 0x7E,// A
-	0x7F, 0x49, 0x49, 0x49, 0x36,// B
-	0x3E, 0x41, 0x41, 0x41, 0x22,// C
-	0x7F, 0x41, 0x41, 0x22, 0x1C,// D
-	0x7F, 0x49, 0x49, 0x49, 0x41,// E
-	0x7F, 0x09, 0x09, 0x01, 0x01,// F
-	0x3E, 0x41, 0x41, 0x51, 0x32,// G
-	0x7F, 0x08, 0x08, 0x08, 0x7F,// H
-	0x00, 0x41, 0x7F, 0x41, 0x00,// I
-	0x20, 0x40, 0x41, 0x3F, 0x01,// J
-	0x7F, 0x08, 0x14, 0x22, 0x41,// K
-	0x7F, 0x40, 0x40, 0x40, 0x40,// L
-	0x7F, 0x02, 0x04, 0x02, 0x7F,// M
-	0x7F, 0x04, 0x08, 0x10, 0x7F,// N
-	0x3E, 0x41, 0x41, 0x41, 0x3E,// O
-	0x7F, 0x09, 0x09, 0x09, 0x06,// P
-	0x3E, 0x41, 0x51, 0x21, 0x5E,// Q
-	0x7F, 0x09, 0x19, 0x29, 0x46,// R
-	0x46, 0x49, 0x49, 0x49, 0x31,// S
-	0x01, 0x01, 0x7F, 0x01, 0x01,// T
-	0x3F, 0x40, 0x40, 0x40, 0x3F,// U
-	0x1F, 0x20, 0x40, 0x20, 0x1F,// V
-	0x7F, 0x20, 0x18, 0x20, 0x7F,// W
-	0x63, 0x14, 0x08, 0x14, 0x63,// X
-	0x03, 0x04, 0x78, 0x04, 0x03,// Y
-	0x61, 0x51, 0x49, 0x45, 0x43,// Z
-	0x00, 0x00, 0x7F, 0x41, 0x41,// [
-	0x02, 0x04, 0x08, 0x10, 0x20,// "\"
-	0x41, 0x41, 0x7F, 0x00, 0x00,// ]
-	0x04, 0x02, 0x01, 0x02, 0x04,// ^
-	0x40, 0x40, 0x40, 0x40, 0x40,// _
-	0x00, 0x01, 0x02, 0x04, 0x00,// `
-	0x20, 0x54, 0x54, 0x54, 0x78,// a
-	0x7F, 0x48, 0x44, 0x44, 0x38,// b
-	0x38, 0x44, 0x44, 0x44, 0x20,// c
-	0x38, 0x44, 0x44, 0x48, 0x7F,// d
-	0x38, 0x54, 0x54, 0x54, 0x18,// e
-	0x08, 0x7E, 0x09, 0x01, 0x02,// f
-	0x08, 0x14, 0x54, 0x54, 0x3C,// g
-	0x7F, 0x08, 0x04, 0x04, 0x78,// h
-	0x00, 0x44, 0x7D, 0x40, 0x00,// i
-	0x20, 0x40, 0x44, 0x3D, 0x00,// j
-	0x00, 0x7F, 0x10, 0x28, 0x44,// k
-	0x00, 0x41, 0x7F, 0x40, 0x00,// l
-	0x7C, 0x04, 0x18, 0x04, 0x78,// m
-	0x7C, 0x08, 0x04, 0x04, 0x78,// n
-	0x38, 0x44, 0x44, 0x44, 0x38,// o
-	0x7C, 0x14, 0x14, 0x14, 0x08,// p
-	0x08, 0x14, 0x14, 0x18, 0x7C,// q
-	0x7C, 0x08, 0x04, 0x04, 0x08,// r
-	0x48, 0x54, 0x54, 0x54, 0x20,// s
-	0x04, 0x3F, 0x44, 0x40, 0x20,// t
-	0x3C, 0x40, 0x40, 0x20, 0x7C,// u
-	0x1C, 0x20, 0x40, 0x20, 0x1C,// v
-	0x3C, 0x40, 0x30, 0x40, 0x3C,// w
-	0x44, 0x28, 0x10, 0x28, 0x44,// x
-	0x0C, 0x50, 0x50, 0x50, 0x3C,// y
-	0x44, 0x64, 0x54, 0x4C, 0x44,// z
-	0x00, 0x08, 0x36, 0x41, 0x00,// {
-	0x00, 0x00, 0x7F, 0x00, 0x00,// |
-	0x00, 0x41, 0x36, 0x08, 0x00,// }
-	0x08, 0x08, 0x2A, 0x1C, 0x08,// ->
-	0x08, 0x1C, 0x2A, 0x08, 0x08 // <-
-    
-};
-
-#endif
diff --git a/STM32F1/libraries/ILI9341_due_STM/fonts/Verdana_digits_24.h b/STM32F1/libraries/ILI9341_due_STM/fonts/Verdana_digits_24.h
deleted file mode 100644
index 38e86143c..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/fonts/Verdana_digits_24.h
+++ /dev/null
@@ -1,116 +0,0 @@
-
-
-/*
- *
- * Verdana28
- *
- * created with FontCreator
- * written by F. Maximilian Thiele
- *
- * http://www.apetech.de/fontCreator
- * me@apetech.de
- *
- * File Name           : Verdana_digits_24
- * Date                : 01.05.2008
- * Font size in bytes  : 3833
- * Font width          : 10
- * Font height         : 24
- * Font first char     : 48
- * Font last char      : 59
- * Font used chars     : 11
- *
- * The font data are defined as
- *
- * struct _FONT_ {
- *     uint16_t   font_Size_in_Bytes_over_all_included_Size_it_self;
- *     uint8_t    font_Width_in_Pixel_for_fixed_drawing;
- *     uint8_t    font_Height_in_Pixel_for_all_characters;
- *     unit8_t    font_First_Char;
- *     uint8_t    font_Char_Count;
- *
- *     uint8_t    font_Char_Widths[font_Last_Char - font_First_Char +1];
- *                  // for each character the separate width in pixels,
- *                  // characters < 128 have an implicit virtual right empty
-row
- *
- *     uint8_t    font_data[];
- *                  // bit field of all characters
- */
-
-#include <inttypes.h>
-#include <avr/pgmspace.h>
-
-#ifndef VERDANA24_H
-#define VERDANA24_H
-
-#define VERDANA24_WIDTH 10
-#define VERDANA24_HEIGHT 24
-
-static const uint8_t Verdana24[] PROGMEM = {
-    0x0E, 0xF9, // size
-    0x0A, // width
-    0x18, // height
-    0x30, // first char
-    0x0B, // char count
-
-    // char widths
-    0x10, 0x0D, 0x0F, 0x0F, 0x11, 0x0F, 0x10, 0x10, 0x10, 0x10,
-    0x04,
-
-    // font data
-    0x80, 0xF0, 0xFC, 0x7E, 0x0E, 0x0F, 0x07, 0x07, 0x07, 0x07, 0x0F, 0x1E,
-0x7E, 0xFC, 0xF0, 0x80, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x01, 0x0F, 0x3F, 0x7E,
-0x70, 0xF0, 0xE0, 0xE0, 0xE0, 0xE0, 0xF0, 0x70, 0x7E, 0x3F, 0x0F, 0x01, //48
-
-    0x38, 0x38, 0x38, 0x38, 0x3C, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0x00, 0x00, 0x00,
-0x00, 0x00, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xFF, 0xFF, 0xFF, 0xE0, 0xE0,
-0xE0, 0xE0, 0xE0,                                                        // 49
-
-    0x00, 0x1E, 0x0E, 0x0E, 0x07, 0x07, 0x07, 0x07, 0x07, 0x0F, 0x1E, 0xFE,
-0xFC, 0xF0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0xE0, 0xF0,
-0x78, 0x3E, 0x1F, 0x07, 0x01, 0x00, 0xF0, 0xF8, 0xFC, 0xFE, 0xEF, 0xE7,
-0xE3, 0xE1, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0,                    // 50
-
-    0x00, 0x1E, 0x0E, 0x0E, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x0F, 0x1E,
-0xFE, 0xFC, 0xF8, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1C, 0x1C, 0x1C, 0x1C,
-0x1E, 0x36, 0x77, 0xF3, 0xE1, 0xC0, 0x78, 0x70, 0x70, 0xF0, 0xE0, 0xE0,
-0xE0, 0xE0, 0xE0, 0xF0, 0x70, 0x78, 0x3F, 0x1F, 0x0F,                   // 51
-
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xC0, 0xF0, 0xF8, 0x7C, 0x1E, 0xFF,
-0xFF, 0xFF, 0x00, 0x00, 0x00, 0xE0, 0xF0, 0xFC, 0xFE, 0xDF, 0xC7, 0xC3,
-0xC1, 0xC0, 0xC0, 0xC0, 0xFF, 0xFF, 0xFF, 0xC0, 0xC0, 0xC0, 0x01, 0x01,
-0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0x01, 0xFF, 0xFF, 0xFF,
-0x01, 0x01, 0x01,                                                       // 52
-
-    0x00, 0xFF, 0xFF, 0xFF, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07,
-0x07, 0x07, 0x07, 0x00, 0x1F, 0x1F, 0x0F, 0x0E, 0x0E, 0x0E, 0x0E, 0x0E,
-0x1E, 0x1C, 0x3C, 0xF8, 0xF8, 0xE0, 0x78, 0x70, 0x70, 0xF0, 0xE0, 0xE0,
-0xE0, 0xE0, 0xE0, 0xF0, 0x70, 0x7C, 0x3F, 0x1F, 0x07,                    // 53
-
-    0x00, 0xC0, 0xF0, 0xF8, 0x3C, 0x1E, 0x0E, 0x0E, 0x07, 0x07, 0x07, 0x07,
-0x07, 0x0F, 0x00, 0x00, 0xFE, 0xFF, 0xFF, 0x1C, 0x1C, 0x0E, 0x0E, 0x0E,
-0x0E, 0x0E, 0x0E, 0x1E, 0x3C, 0xF8, 0xF8, 0xE0, 0x03, 0x0F, 0x3F, 0x7C,
-0x78, 0xF0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0x70, 0x78, 0x3F, 0x1F, 0x07, //54
-
-    0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x07, 0x87,
-0xE7, 0xFF, 0x7F, 0x1F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xC0,
-0xF0, 0xFC, 0x3F, 0x0F, 0x07, 0x01, 0x00, 0x00, 0x00, 0x00, 0x80, 0xE0,
-0xF8, 0xFC, 0x3F, 0x0F, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, //55
-
-    0x00, 0xF0, 0xFC, 0xFE, 0x0E, 0x0F, 0x07, 0x07, 0x07, 0x07, 0x0F, 0x1E,
-0xFE, 0xFC, 0xF8, 0x00, 0x80, 0xE0, 0xF3, 0x77, 0x1F, 0x0E, 0x0E, 0x0C,
-0x1C, 0x1C, 0x1C, 0x3E, 0x77, 0xF3, 0xE0, 0x80, 0x0F, 0x1F, 0x3F, 0x78,
-0x70, 0xF0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0x70, 0x78, 0x3F, 0x1F, 0x0F, //56
-
-    0xE0, 0xF8, 0xFC, 0x1E, 0x0E, 0x07, 0x07, 0x07, 0x07, 0x07, 0x0F, 0x1E,
-0x3E, 0xFC, 0xF0, 0xC0, 0x07, 0x1F, 0x1F, 0x3C, 0x78, 0x70, 0x70, 0x70,
-0x70, 0x70, 0x70, 0x38, 0x38, 0xFF, 0xFF, 0x7F, 0x00, 0x00, 0xF0, 0xE0,
-0xE0, 0xE0, 0xE0, 0xE0, 0x70, 0x70, 0x78, 0x3C, 0x1F, 0x0F, 0x03, 0x00,    //57
-
-    0xC0, 0xC0, 0xC0, 0xC0, 0x03, 0x03, 0x03, 0x03, 0xF0, 0xF0, 0xF0, 0xF0 // 58
-
-};
-
-#endif
diff --git a/STM32F1/libraries/ILI9341_due_STM/fonts/allFonts.h b/STM32F1/libraries/ILI9341_due_STM/fonts/allFonts.h
deleted file mode 100644
index cafd7ebec..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/fonts/allFonts.h
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * allFonts.h font header for GLCD library 
- * The fonts listed below will be available in a sketch if this file is included
- *
- * If you create your own fonts you can add the header to this file
- *
- * Note that the build environment only holds a font in Flash if its selected 
- * so there is no penalty to including a font file here if its not used 
- */
-
-#include "SystemFont5x7.h"       // system font
-#include "Arial14.h"             // proportional font
-#include "Arial_bold_14.h"       // Bold proportional font
-#include "Corsiva_12.h"
-#include "Verdana_digits_24.h"   // large proportional font - numerals only 
-#include "fixednums7x15.h"       // fixed width font - numerals only 
-#include "fixednums8x16.h"       // fixed width font - numerals only 
-#include "fixednums15x31.h"      // fixed width font - numerals only 
diff --git a/STM32F1/libraries/ILI9341_due_STM/fonts/fixednums15x31.h b/STM32F1/libraries/ILI9341_due_STM/fonts/fixednums15x31.h
deleted file mode 100644
index 346e1298f..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/fonts/fixednums15x31.h
+++ /dev/null
@@ -1,127 +0,0 @@
-/*
- * Fixed width font for numbers
- *
- * This font is very useful when using overstrike as all characters & numbers
- * are all the same width.
- *
- * This font also contains a few special characters that are nice for certain applications
- * like clocks, signed values or decimal point values.
- * 
- * The rendering code normally inserts a pad pixel so this size allows the font to fit
- * perfectly on 32 and 64 tall glcd displays.
- *
- * Font has also been squeezed to 15 pixels wide for better alignment on 128 & 192 pixel displays.
- */
-
-#ifndef FIXEDNUMS15x31_H
-#define FIXEDNUMS15x31_H
-
-#include <inttypes.h>
-#include <avr/pgmspace.h>
-
-
-static const uint8_t fixednums15x31[] PROGMEM = {
-    0x0, 0x0,	// size of zero indicates fixed width font
-    15,		// width
-    31,		// height
-    '+',	// first char (48)
-    16,		// char count
-// char '+'
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xfc, 0xfc, 0xfc, 0xfc, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x0f, 0x0f, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-
-// char ','
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xcf, 0xcf, 0x3f, 0x3f, 0x00, 0x00, 0x00, 0x00, 0x00,
-
-// char '-'
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-
-// char '.'
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x0f, 0x0f, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00,
-
-// char '/'
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xf0, 0xff, 0xff, 0x0f,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xf0, 0xff, 0xff, 0x0f, 0x0f, 0x00, 0x00, 0x00,
-0x00, 0x00, 0xf0, 0xf0, 0xff, 0xff, 0x0f, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x0f, 0x0f, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-
-// char '0'
-0xf0, 0xf0, 0xfc, 0xfc, 0x0f, 0x0f, 0x03, 0x03, 0x03, 0xcf, 0xcf, 0xfc, 0xfc, 0xf0, 0xf0,
-0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0xc0, 0xc0, 0x3c, 0x3f, 0x03, 0xff, 0xff, 0xff, 0xff,
-0xff, 0xff, 0xff, 0xff, 0x3c, 0x3c, 0x03, 0x03, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
-0x00, 0x00, 0x03, 0x03, 0x0f, 0x0f, 0x0c, 0x0c, 0x0c, 0x0f, 0x0f, 0x03, 0x03, 0x00, 0x00,
-
-// char '1'
-0x30, 0x30, 0x30, 0x30, 0x3c, 0x3c, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0f, 0x0f, 0x0f, 0x0f, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c,
-
-// char '2'
-0xf0, 0xf0, 0xfc, 0xfc, 0x0f, 0x0f, 0x03, 0x03, 0x03, 0x03, 0x0f, 0xff, 0xfc, 0xfc, 0xf0,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xc0, 0xf0, 0xff, 0x3f, 0x3f, 0x0f,
-0xc0, 0xc0, 0xf0, 0xf0, 0x3c, 0x3c, 0x0f, 0x0f, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x0f, 0x0f, 0x0f, 0x0f, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c,
-
-// char '3'
-0xf0, 0xf0, 0xfc, 0xfc, 0x0f, 0x0f, 0x03, 0x03, 0x03, 0x03, 0x0f, 0x1f, 0xfc, 0xfc, 0xf0,
-0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0x30, 0xff, 0xdf, 0x8f,
-0xf0, 0xf0, 0xf0, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x80, 0xff, 0xff, 0xff,
-0x00, 0x00, 0x03, 0x03, 0x0f, 0x0f, 0x0c, 0x0c, 0x0c, 0x0c, 0x0f, 0x0f, 0x03, 0x03, 0x00,
-
-// char '4'
-0x00, 0x00, 0x00, 0x00, 0xf0, 0xf0, 0xff, 0xff, 0x0f, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0xfc, 0xfc, 0xff, 0xff, 0x03, 0x03, 0xc0, 0xc0, 0xc0, 0xc0, 0x00, 0x00, 0x00,
-0xff, 0xff, 0xff, 0xff, 0xc0, 0xc0, 0xc0, 0xc0, 0xff, 0xff, 0xff, 0xff, 0xc0, 0xc0, 0xc0,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x0f, 0x0f, 0x0f, 0x00, 0x00, 0x00,
-
-// char '5'
-0xff, 0xff, 0xff, 0xff, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03,
-0x0f, 0x0f, 0x0f, 0x0f, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x3c, 0xfc, 0xf0, 0xf0, 0xc0,
-0xf0, 0xf0, 0xf0, 0xf0, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
-0x00, 0x00, 0x03, 0x03, 0x0f, 0x0f, 0x0c, 0x0c, 0x0c, 0x0c, 0x0f, 0x0f, 0x03, 0x03, 0x00,
-
-// char '6'
-0x00, 0x00, 0xc0, 0xc0, 0xf0, 0xf0, 0x3c, 0x3c, 0x0f, 0x0f, 0x03, 0x03, 0x03, 0x03, 0x03,
-0xfc, 0xfc, 0xff, 0xff, 0x33, 0x33, 0x30, 0x30, 0x30, 0x30, 0xf0, 0xf0, 0xc0, 0xc0, 0x00,
-0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
-0x00, 0x00, 0x03, 0x03, 0x0f, 0x0f, 0x0c, 0x0c, 0x0c, 0x0c, 0x0f, 0x0f, 0x03, 0x03, 0x00,
-
-// char '7'
-0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0x03, 0xff, 0xff, 0xff, 0xff,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xc0, 0xff, 0xff, 0x3f, 0x3f, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0xf0, 0xf0, 0xff, 0xff, 0x0f, 0x0f, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x0f, 0x0f, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-
-// char '8'
-0xf0, 0xf0, 0xfc, 0xfc, 0x0f, 0x0f, 0x03, 0x03, 0x03, 0x0f, 0x0f, 0xfc, 0xfc, 0xf0, 0xf0,
-0x03, 0x03, 0xcf, 0xcf, 0xfc, 0xfc, 0x30, 0x30, 0x30, 0xfc, 0xfc, 0xcf, 0xcf, 0x03, 0x03,
-0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xff, 0xff, 0xff,
-0x00, 0x00, 0x03, 0x03, 0x0f, 0x0f, 0x0c, 0x0c, 0x0c, 0x0f, 0x0f, 0x03, 0x03, 0x00, 0x00,
-
-// char '9'
-0xe0, 0xf0, 0xfc, 0xfc, 0x0f, 0x0f, 0x03, 0x03, 0x03, 0x0f, 0x0f, 0xfc, 0xfc, 0xf0, 0xe0,
-0x07, 0x0f, 0x3f, 0x3f, 0xf0, 0xf0, 0xc0, 0xc0, 0xc0, 0xc0, 0xc0, 0xff, 0xff, 0xff, 0xff,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xc0, 0xc0, 0xfc, 0xfc, 0x3f, 0x3f, 0x03,
-0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0c, 0x0f, 0x0f, 0x03, 0x03, 0x00, 0x00, 0x00, 0x00, 0x00,
-
-// char ':'
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x3c, 0x3c, 0x3c, 0x3c, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x0f, 0x0f, 0x0f, 0x0f, 0x00, 0x00, 0x00, 0x00, 0x00,
-
-};
-
-#endif
diff --git a/STM32F1/libraries/ILI9341_due_STM/fonts/fixednums7x15.h b/STM32F1/libraries/ILI9341_due_STM/fonts/fixednums7x15.h
deleted file mode 100644
index 42337e366..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/fonts/fixednums7x15.h
+++ /dev/null
@@ -1,92 +0,0 @@
-/*
- * Fixed width font for numbers
- *
- * This font is very useful when using overstrike as all characters & numbers
- * are all the same width.
- *
- * This font also contains a few special characters that are nice for certain applications
- * like clocks, signed values or decimal point values.
- * 
- * When rendering code inserts a pad pixel this size allows the font to fit
- * perfectly on 32 and 64 tall glcd displays as well as 128 wide displays.
- */
-
-#ifndef FIXEDNUMS7x15_H
-#define FIXEDNUMS7x15_H
-
-#include <inttypes.h>
-#include <avr/pgmspace.h>
-
-
-static const uint8_t fixednums7x15[] PROGMEM = {
-    0x0, 0x0,	// size of zero indicates fixed width font
-    7,		// width
-    15,		// height
-    '+',	// first char (48)
-    16,		// char count
-// char '+'
-0x00, 0x80, 0x80, 0xe0, 0xe0, 0x80, 0x80,
-0x00, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00,
-
-// char ','
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x58, 0x38, 0x00, 0x00,
-
-// char '-'
-0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-
-// char '.'
-0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x30, 0x30, 0x00, 0x00,
-
-// char '/'
-0x00, 0x00, 0x00, 0xc0, 0xf0, 0x3c, 0x0f,
-0x00, 0x3c, 0x0f, 0x03, 0x00, 0x00, 0x00,
-
-// char '0'
-0xfc, 0xfe, 0x03, 0xe1, 0x1b, 0xfe, 0xfc,
-0x0f, 0x1f, 0x36, 0x21, 0x30, 0x1f, 0x0f,
-
-// char '1'
-0x04, 0x04, 0x06, 0xff, 0xff, 0x00, 0x00,
-0x20, 0x20, 0x20, 0x3f, 0x3f, 0x20, 0x20,
-
-// char '2'
-0x0c, 0x0e, 0x03, 0x01, 0x81, 0xfe, 0x7c,
-0x38, 0x3c, 0x26, 0x23, 0x21, 0x20, 0x20,
-
-// char '3'
-0x0c, 0x0e, 0x43, 0x41, 0x43, 0xfe, 0xbc,
-0x0c, 0x1c, 0x30, 0x20, 0x30, 0x1f, 0x0f,
-
-// char '4'
-0x00, 0xe0, 0xfc, 0x1f, 0x83, 0x80, 0x00,
-0x0f, 0x0f, 0x08, 0x08, 0x3f, 0x3f, 0x08,
-
-// char '5'
-0x3f, 0x3f, 0x21, 0x21, 0x61, 0xe1, 0x81,
-0x0c, 0x1c, 0x30, 0x20, 0x30, 0x3f, 0x0f,
-
-// char '6'
-0xe0, 0xf8, 0x5c, 0x46, 0xc3, 0xc1, 0x01,
-0x0f, 0x1f, 0x30, 0x20, 0x30, 0x3f, 0x0f,
-
-// char '7'
-0x01, 0x01, 0x01, 0x81, 0xf1, 0x7f, 0x0f,
-0x00, 0x00, 0x3c, 0x3f, 0x03, 0x00, 0x00,
-
-// char '8'
-0x1c, 0xbe, 0xe3, 0x41, 0xe3, 0xbe, 0x1c,
-0x0f, 0x1f, 0x30, 0x20, 0x30, 0x1f, 0x0f,
-
-// char '9'
-0x3c, 0x7e, 0xc3, 0x81, 0x81, 0xfe, 0xfc,
-0x20, 0x30, 0x38, 0x0c, 0x07, 0x03, 0x00,
-
-// char ':'
-0x00, 0x00, 0x00, 0x60, 0x60, 0x00, 0x00,
-0x00, 0x00, 0x00, 0x30, 0x30, 0x00, 0x00,
-
-};
-#endif
diff --git a/STM32F1/libraries/ILI9341_due_STM/fonts/fixednums8x16.h b/STM32F1/libraries/ILI9341_due_STM/fonts/fixednums8x16.h
deleted file mode 100644
index b1981ce81..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/fonts/fixednums8x16.h
+++ /dev/null
@@ -1,50 +0,0 @@
-/*
- * Fixed width font file for numbers only.
- *
- * This font is very useful when using overstrike as all characters & numbers
- * are all the same width.
- *
- * This font file can be used when only numbers are needed. 
- *
- * This font also contains a few special characters that are nice for certain applications
- * like clocks, signed values or decimal point values.
- * 
- * Font is really 16 tall but this file is set to indicate 15 to allow it to line up with the lcd page size.
- * It works as the the bottom row in the glyph is whitespace anyway.
- * The rendering code normally inserts a pad pixel so this size allows additional rows
- * on 32 and 64 tall glcd displays.
- *
- */
-
-#ifndef FIXEDNUMS8x16_H
-#define FIXEDNUMS8x16_H
-
-#include <inttypes.h>
-#include <avr/pgmspace.h>
-
-
-static const uint8_t fixednums8x16[] PROGMEM = {
-    0x0, 0x0,	// size of zero indicates fixed width font
-    8,		// width
-    15,		// height
-    '+',	// first char (48)
-    16,		// char count
-
-    0x80, 0x80, 0x80, 0xe0, 0xe0, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0x03, 0x03, 0x00, 0x00, 0x00, // char '+'
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xb0, 0x70, 0x00, 0x00, 0x00, // char ','
-    0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x80, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // char '-'
-    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x00, 0x00, 0x00, // char '.'
-    0x00, 0x00, 0x00, 0xc0, 0xf0, 0x3c, 0x0f, 0x03, 0x30, 0x3c, 0x0f, 0x03, 0x00, 0x00, 0x00, 0x00, // char '/'
-    0xfc, 0xfe, 0x03, 0x81, 0x61, 0x1b, 0xfe, 0xfc, 0x0f, 0x1f, 0x36, 0x21, 0x20, 0x30, 0x1f, 0x0f, // char '0'
-    0x04, 0x04, 0x06, 0xff, 0xff, 0x00, 0x00, 0x00, 0x20, 0x20, 0x20, 0x3f, 0x3f, 0x20, 0x20, 0x20, // char '1'
-    0x0c, 0x0e, 0x03, 0x01, 0x81, 0xc3, 0x7e, 0x3c, 0x38, 0x3c, 0x26, 0x23, 0x21, 0x20, 0x20, 0x20, // char '2'
-    0x0c, 0x0e, 0x43, 0x41, 0x41, 0x43, 0xfe, 0xbc, 0x0c, 0x1c, 0x30, 0x20, 0x20, 0x30, 0x1f, 0x0f, // char '3'
-    0x00, 0xe0, 0xfc, 0x1f, 0x83, 0x80, 0x00, 0x00, 0x0f, 0x0f, 0x08, 0x08, 0x3f, 0x3f, 0x08, 0x08, // char '4'
-    0x3f, 0x3f, 0x21, 0x21, 0x21, 0x61, 0xc1, 0x81, 0x0c, 0x1c, 0x30, 0x20, 0x20, 0x30, 0x1f, 0x0f, // char '5'
-    0xe0, 0xf8, 0x5c, 0x46, 0x43, 0xc1, 0x81, 0x01, 0x0f, 0x1f, 0x30, 0x20, 0x20, 0x30, 0x1f, 0x0f, // char '6'
-    0x01, 0x01, 0x01, 0x01, 0x81, 0xf1, 0x7f, 0x0f, 0x00, 0x00, 0x00, 0x3c, 0x3f, 0x03, 0x00, 0x00, // char '7'
-    0x1c, 0xbe, 0xe3, 0x41, 0x41, 0xe3, 0xbe, 0x1c, 0x0f, 0x1f, 0x30, 0x20, 0x20, 0x30, 0x1f, 0x0f, // char '8'
-    0x3c, 0x7e, 0xc3, 0x81, 0x81, 0x83, 0xfe, 0xfc, 0x20, 0x20, 0x20, 0x30, 0x18, 0x0e, 0x07, 0x01, // char '9'
-    0x00, 0x00, 0x00, 0x60, 0x60, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x30, 0x30, 0x00, 0x00, 0x00  // char ':
-};
-#endif
diff --git a/STM32F1/libraries/ILI9341_due_STM/fonts/jokerman_255.h b/STM32F1/libraries/ILI9341_due_STM/fonts/jokerman_255.h
deleted file mode 100644
index 3045ce31e..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/fonts/jokerman_255.h
+++ /dev/null
@@ -1,73 +0,0 @@
-
-
-/*
- *
- * jokerman_255
- *
- * created with FontCreator
- * written by F. Maximilian Thiele
- *
- * http://www.apetech.de/fontCreator
- * me@apetech.de
- *
- * File Name           : jokerman_255
- * Date                : 04.09.2014
- * Font size in bytes  : 362565
- * Font width          : 10
- * Font height         : 253
- * Font first char     : 48
- * Font last char      : 58
- * Font used chars     : 10
- *
- * The font data are defined as
- *
- * struct _FONT_ {
- *     uint16_t   font_Size_in_Bytes_over_all_included_Size_it_self;
- *     uint8_t    font_Width_in_Pixel_for_fixed_drawing;
- *     uint8_t    font_Height_in_Pixel_for_all_characters;
- *     unit8_t    font_First_Char;
- *     uint8_t    font_Char_Count;
- *
- *     uint8_t    font_Char_Widths[font_Last_Char - font_First_Char +1];
- *                  // for each character the separate width in pixels,
- *                  // characters < 128 have an implicit virtual right empty row
- *
- *     uint8_t    font_data[];
- *                  // bit field of all characters
- */
-
-#include <inttypes.h>
-#include <avr/pgmspace.h>
-
-#ifndef JOKERMAN_255_H
-#define JOKERMAN_255_H
-
-#define JOKERMAN_255_WIDTH 10
-#define JOKERMAN_255_HEIGHT 253
-
-static const uint8_t jokerman_255[] PROGMEM = {
-    0x88, 0x45, // size
-    0x0A, // width
-    0xFD, // height
-    0x30, // first char
-    0x0A, // char count
-    
-    // char widths
-    0x9A, 0x4D, 0x8B, 0x9E, 0xAD, 0x91, 0x8E, 0x91, 0x90, 0x9C, 
-    
-    
-    // font data
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0xC0, 0xC0, 0xC0, 0xE0, 0xE0, 0xE0, 0xE0, 0xE0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF0, 0xF8, 0xF8, 0xF8, 0xF8, 0xF8, 0xFC, 0xFC, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFE, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0x7F, 0x7F, 0x7F, 0x7F, 0x3F, 0x3F, 0x3F, 0x3F, 0x1F, 0x1F, 0x1F, 0x1F, 0x0F, 0x0F, 0x0F, 0x0F, 0x07, 0x07, 0x07, 0x07, 0x03, 0x03, 0x03, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x1F, 0x0F, 0x0F, 0x0F, 0x0F, 0x07, 0x07, 0x07, 0x07, 0x03, 0x03, 0x03, 0x03, 0x01, 0x01, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00 // 57
-    
-};
-
-#endif
diff --git a/STM32F1/libraries/ILI9341_due_STM/glcdfont.c b/STM32F1/libraries/ILI9341_due_STM/glcdfont.c
deleted file mode 100644
index d6e8af236..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/glcdfont.c
+++ /dev/null
@@ -1,263 +0,0 @@
-#ifndef FONT5X7_H
-#define FONT5X7_H
-
-// Standard ASCII 5x7 font
-
-static const unsigned char font[] = {
-        0x00, 0x00, 0x00, 0x00, 0x00,
-	0x3E, 0x5B, 0x4F, 0x5B, 0x3E,
-	0x3E, 0x6B, 0x4F, 0x6B, 0x3E,
-	0x1C, 0x3E, 0x7C, 0x3E, 0x1C,
-	0x18, 0x3C, 0x7E, 0x3C, 0x18,
-	0x1C, 0x57, 0x7D, 0x57, 0x1C,
-	0x1C, 0x5E, 0x7F, 0x5E, 0x1C,
-	0x00, 0x18, 0x3C, 0x18, 0x00,
-	0xFF, 0xE7, 0xC3, 0xE7, 0xFF,
-	0x00, 0x18, 0x24, 0x18, 0x00,
-	0xFF, 0xE7, 0xDB, 0xE7, 0xFF,
-	0x30, 0x48, 0x3A, 0x06, 0x0E,
-	0x26, 0x29, 0x79, 0x29, 0x26,
-	0x40, 0x7F, 0x05, 0x05, 0x07,
-	0x40, 0x7F, 0x05, 0x25, 0x3F,
-	0x5A, 0x3C, 0xE7, 0x3C, 0x5A,
-	0x7F, 0x3E, 0x1C, 0x1C, 0x08,
-	0x08, 0x1C, 0x1C, 0x3E, 0x7F,
-	0x14, 0x22, 0x7F, 0x22, 0x14,
-	0x5F, 0x5F, 0x00, 0x5F, 0x5F,
-	0x06, 0x09, 0x7F, 0x01, 0x7F,
-	0x00, 0x66, 0x89, 0x95, 0x6A,
-	0x60, 0x60, 0x60, 0x60, 0x60,
-	0x94, 0xA2, 0xFF, 0xA2, 0x94,
-	0x08, 0x04, 0x7E, 0x04, 0x08,
-	0x10, 0x20, 0x7E, 0x20, 0x10,
-	0x08, 0x08, 0x2A, 0x1C, 0x08,
-	0x08, 0x1C, 0x2A, 0x08, 0x08,
-	0x1E, 0x10, 0x10, 0x10, 0x10,
-	0x0C, 0x1E, 0x0C, 0x1E, 0x0C,
-	0x30, 0x38, 0x3E, 0x38, 0x30,
-	0x06, 0x0E, 0x3E, 0x0E, 0x06,
-	0x00, 0x00, 0x00, 0x00, 0x00,
-	0x00, 0x00, 0x5F, 0x00, 0x00,
-	0x00, 0x07, 0x00, 0x07, 0x00,
-	0x14, 0x7F, 0x14, 0x7F, 0x14,
-	0x24, 0x2A, 0x7F, 0x2A, 0x12,
-	0x23, 0x13, 0x08, 0x64, 0x62,
-	0x36, 0x49, 0x56, 0x20, 0x50,
-	0x00, 0x08, 0x07, 0x03, 0x00,
-	0x00, 0x1C, 0x22, 0x41, 0x00,
-	0x00, 0x41, 0x22, 0x1C, 0x00,
-	0x2A, 0x1C, 0x7F, 0x1C, 0x2A,
-	0x08, 0x08, 0x3E, 0x08, 0x08,
-	0x00, 0x80, 0x70, 0x30, 0x00,
-	0x08, 0x08, 0x08, 0x08, 0x08,
-	0x00, 0x00, 0x60, 0x60, 0x00,
-	0x20, 0x10, 0x08, 0x04, 0x02,
-	0x3E, 0x51, 0x49, 0x45, 0x3E,
-	0x00, 0x42, 0x7F, 0x40, 0x00,
-	0x72, 0x49, 0x49, 0x49, 0x46,
-	0x21, 0x41, 0x49, 0x4D, 0x33,
-	0x18, 0x14, 0x12, 0x7F, 0x10,
-	0x27, 0x45, 0x45, 0x45, 0x39,
-	0x3C, 0x4A, 0x49, 0x49, 0x31,
-	0x41, 0x21, 0x11, 0x09, 0x07,
-	0x36, 0x49, 0x49, 0x49, 0x36,
-	0x46, 0x49, 0x49, 0x29, 0x1E,
-	0x00, 0x00, 0x14, 0x00, 0x00,
-	0x00, 0x40, 0x34, 0x00, 0x00,
-	0x00, 0x08, 0x14, 0x22, 0x41,
-	0x14, 0x14, 0x14, 0x14, 0x14,
-	0x00, 0x41, 0x22, 0x14, 0x08,
-	0x02, 0x01, 0x59, 0x09, 0x06,
-	0x3E, 0x41, 0x5D, 0x59, 0x4E,
-	0x7C, 0x12, 0x11, 0x12, 0x7C,
-	0x7F, 0x49, 0x49, 0x49, 0x36,
-	0x3E, 0x41, 0x41, 0x41, 0x22,
-	0x7F, 0x41, 0x41, 0x41, 0x3E,
-	0x7F, 0x49, 0x49, 0x49, 0x41,
-	0x7F, 0x09, 0x09, 0x09, 0x01,
-	0x3E, 0x41, 0x41, 0x51, 0x73,
-	0x7F, 0x08, 0x08, 0x08, 0x7F,
-	0x00, 0x41, 0x7F, 0x41, 0x00,
-	0x20, 0x40, 0x41, 0x3F, 0x01,
-	0x7F, 0x08, 0x14, 0x22, 0x41,
-	0x7F, 0x40, 0x40, 0x40, 0x40,
-	0x7F, 0x02, 0x1C, 0x02, 0x7F,
-	0x7F, 0x04, 0x08, 0x10, 0x7F,
-	0x3E, 0x41, 0x41, 0x41, 0x3E,
-	0x7F, 0x09, 0x09, 0x09, 0x06,
-	0x3E, 0x41, 0x51, 0x21, 0x5E,
-	0x7F, 0x09, 0x19, 0x29, 0x46,
-	0x26, 0x49, 0x49, 0x49, 0x32,
-	0x03, 0x01, 0x7F, 0x01, 0x03,
-	0x3F, 0x40, 0x40, 0x40, 0x3F,
-	0x1F, 0x20, 0x40, 0x20, 0x1F,
-	0x3F, 0x40, 0x38, 0x40, 0x3F,
-	0x63, 0x14, 0x08, 0x14, 0x63,
-	0x03, 0x04, 0x78, 0x04, 0x03,
-	0x61, 0x59, 0x49, 0x4D, 0x43,
-	0x00, 0x7F, 0x41, 0x41, 0x41,
-	0x02, 0x04, 0x08, 0x10, 0x20,
-	0x00, 0x41, 0x41, 0x41, 0x7F,
-	0x04, 0x02, 0x01, 0x02, 0x04,
-	0x40, 0x40, 0x40, 0x40, 0x40,
-	0x00, 0x03, 0x07, 0x08, 0x00,
-	0x20, 0x54, 0x54, 0x78, 0x40,
-	0x7F, 0x28, 0x44, 0x44, 0x38,
-	0x38, 0x44, 0x44, 0x44, 0x28,
-	0x38, 0x44, 0x44, 0x28, 0x7F,
-	0x38, 0x54, 0x54, 0x54, 0x18,
-	0x00, 0x08, 0x7E, 0x09, 0x02,
-	0x18, 0xA4, 0xA4, 0x9C, 0x78,
-	0x7F, 0x08, 0x04, 0x04, 0x78,
-	0x00, 0x44, 0x7D, 0x40, 0x00,
-	0x20, 0x40, 0x40, 0x3D, 0x00,
-	0x7F, 0x10, 0x28, 0x44, 0x00,
-	0x00, 0x41, 0x7F, 0x40, 0x00,
-	0x7C, 0x04, 0x78, 0x04, 0x78,
-	0x7C, 0x08, 0x04, 0x04, 0x78,
-	0x38, 0x44, 0x44, 0x44, 0x38,
-	0xFC, 0x18, 0x24, 0x24, 0x18,
-	0x18, 0x24, 0x24, 0x18, 0xFC,
-	0x7C, 0x08, 0x04, 0x04, 0x08,
-	0x48, 0x54, 0x54, 0x54, 0x24,
-	0x04, 0x04, 0x3F, 0x44, 0x24,
-	0x3C, 0x40, 0x40, 0x20, 0x7C,
-	0x1C, 0x20, 0x40, 0x20, 0x1C,
-	0x3C, 0x40, 0x30, 0x40, 0x3C,
-	0x44, 0x28, 0x10, 0x28, 0x44,
-	0x4C, 0x90, 0x90, 0x90, 0x7C,
-	0x44, 0x64, 0x54, 0x4C, 0x44,
-	0x00, 0x08, 0x36, 0x41, 0x00,
-	0x00, 0x00, 0x77, 0x00, 0x00,
-	0x00, 0x41, 0x36, 0x08, 0x00,
-	0x02, 0x01, 0x02, 0x04, 0x02,
-	0x3C, 0x26, 0x23, 0x26, 0x3C,
-	0x1E, 0xA1, 0xA1, 0x61, 0x12,
-	0x3A, 0x40, 0x40, 0x20, 0x7A,
-	0x38, 0x54, 0x54, 0x55, 0x59,
-	0x21, 0x55, 0x55, 0x79, 0x41,
-	0x21, 0x54, 0x54, 0x78, 0x41,
-	0x21, 0x55, 0x54, 0x78, 0x40,
-	0x20, 0x54, 0x55, 0x79, 0x40,
-	0x0C, 0x1E, 0x52, 0x72, 0x12,
-	0x39, 0x55, 0x55, 0x55, 0x59,
-	0x39, 0x54, 0x54, 0x54, 0x59,
-	0x39, 0x55, 0x54, 0x54, 0x58,
-	0x00, 0x00, 0x45, 0x7C, 0x41,
-	0x00, 0x02, 0x45, 0x7D, 0x42,
-	0x00, 0x01, 0x45, 0x7C, 0x40,
-	0xF0, 0x29, 0x24, 0x29, 0xF0,
-	0xF0, 0x28, 0x25, 0x28, 0xF0,
-	0x7C, 0x54, 0x55, 0x45, 0x00,
-	0x20, 0x54, 0x54, 0x7C, 0x54,
-	0x7C, 0x0A, 0x09, 0x7F, 0x49,
-	0x32, 0x49, 0x49, 0x49, 0x32,
-	0x32, 0x48, 0x48, 0x48, 0x32,
-	0x32, 0x4A, 0x48, 0x48, 0x30,
-	0x3A, 0x41, 0x41, 0x21, 0x7A,
-	0x3A, 0x42, 0x40, 0x20, 0x78,
-	0x00, 0x9D, 0xA0, 0xA0, 0x7D,
-	0x39, 0x44, 0x44, 0x44, 0x39,
-	0x3D, 0x40, 0x40, 0x40, 0x3D,
-	0x3C, 0x24, 0xFF, 0x24, 0x24,
-	0x48, 0x7E, 0x49, 0x43, 0x66,
-	0x2B, 0x2F, 0xFC, 0x2F, 0x2B,
-	0xFF, 0x09, 0x29, 0xF6, 0x20,
-	0xC0, 0x88, 0x7E, 0x09, 0x03,
-	0x20, 0x54, 0x54, 0x79, 0x41,
-	0x00, 0x00, 0x44, 0x7D, 0x41,
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-	0x26, 0x29, 0x29, 0x29, 0x26,
-	0x30, 0x48, 0x4D, 0x40, 0x20,
-	0x38, 0x08, 0x08, 0x08, 0x08,
-	0x08, 0x08, 0x08, 0x08, 0x38,
-	0x2F, 0x10, 0xC8, 0xAC, 0xBA,
-	0x2F, 0x10, 0x28, 0x34, 0xFA,
-	0x00, 0x00, 0x7B, 0x00, 0x00,
-	0x08, 0x14, 0x2A, 0x14, 0x22,
-	0x22, 0x14, 0x2A, 0x14, 0x08,
-	0xAA, 0x00, 0x55, 0x00, 0xAA,
-	0xAA, 0x55, 0xAA, 0x55, 0xAA,
-	0x00, 0x00, 0x00, 0xFF, 0x00,
-	0x10, 0x10, 0x10, 0xFF, 0x00,
-	0x14, 0x14, 0x14, 0xFF, 0x00,
-	0x10, 0x10, 0xFF, 0x00, 0xFF,
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-	0x14, 0x14, 0x14, 0xFC, 0x00,
-	0x14, 0x14, 0xF7, 0x00, 0xFF,
-	0x00, 0x00, 0xFF, 0x00, 0xFF,
-	0x14, 0x14, 0xF4, 0x04, 0xFC,
-	0x14, 0x14, 0x17, 0x10, 0x1F,
-	0x10, 0x10, 0x1F, 0x10, 0x1F,
-	0x14, 0x14, 0x14, 0x1F, 0x00,
-	0x10, 0x10, 0x10, 0xF0, 0x00,
-	0x00, 0x00, 0x00, 0x1F, 0x10,
-	0x10, 0x10, 0x10, 0x1F, 0x10,
-	0x10, 0x10, 0x10, 0xF0, 0x10,
-	0x00, 0x00, 0x00, 0xFF, 0x10,
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-	0x10, 0x10, 0x10, 0x1F, 0x00,
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-	0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
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-	0xFF, 0xFF, 0xFF, 0x00, 0x00,
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-	0x06, 0x02, 0x7E, 0x02, 0x02,
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-	0x44, 0x44, 0x5F, 0x44, 0x44,
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-	0x40, 0x44, 0x4A, 0x51, 0x40,
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-	0xE0, 0x80, 0xFF, 0x00, 0x00,
-	0x08, 0x08, 0x6B, 0x6B, 0x08,
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-	0x06, 0x0F, 0x09, 0x0F, 0x06,
-	0x00, 0x00, 0x18, 0x18, 0x00,
-	0x00, 0x00, 0x10, 0x10, 0x00,
-	0x30, 0x40, 0xFF, 0x01, 0x01,
-	0x00, 0x1F, 0x01, 0x01, 0x1E,
-	0x00, 0x19, 0x1D, 0x17, 0x12,
-	0x00, 0x3C, 0x3C, 0x3C, 0x3C,
-	0x00, 0x00, 0x00, 0x00, 0x00
-};
-#endif // FONT5X7_H
diff --git a/STM32F1/libraries/ILI9341_due_STM/keywords.txt b/STM32F1/libraries/ILI9341_due_STM/keywords.txt
deleted file mode 100644
index 8278c0bfe..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/keywords.txt
+++ /dev/null
@@ -1,38 +0,0 @@
-ILI9341_due	KEYWORD1
-ILI9341_due_gText	KEYWORD1
-ILI9341_BLACK	LITERAL1
-ILI9341_BLUE	LITERAL1
-ILI9341_RED	LITERAL1
-ILI9341_GREEN	LITERAL1
-ILI9341_CYAN	LITERAL1
-ILI9341_MAGENTA	LITERAL1
-ILI9341_YELLOW	LITERAL1
-ILI9341_WHITE	LITERAL1
-pushColor	KEYWORD2
-fillScreen	KEYWORD2
-drawPixel	KEYWORD2
-drawFastVLine	KEYWORD2
-drawFastHLine	KEYWORD2
-drawRect	KEYWORD2
-fillRect	KEYWORD2
-setRotation	KEYWORD2
-invertDisplay	KEYWORD2
-setAddrWindow	KEYWORD2
-color565	KEYWORD2
-readcommand8	KEYWORD2
-readPixel	KEYWORD2
-drawCircle	KEYWORD2
-fillCircle	KEYWORD2
-drawTriangle	KEYWORD2
-fillTriangle	KEYWORD2
-drawRoundRect	KEYWORD2
-fillRoundRect	KEYWORD2
-drawBitmap	KEYWORD2
-drawChar	KEYWORD2
-setCursor	KEYWORD2
-setTextColor	KEYWORD2
-setTextSize	KEYWORD2
-setTextWrap	KEYWORD2
-drawLine	KEYWORD2
-DefineArea	KEYWORD2
-SelectFont	KEYWORD2
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/.NET/BMP24toILI565.exe b/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/.NET/BMP24toILI565.exe
deleted file mode 100644
index c8f2e5bed1e15b898ceaeb27a0c06c12b3b1e48d..0000000000000000000000000000000000000000
GIT binary patch
literal 0
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diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/.NET/src/App.config b/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/.NET/src/App.config
deleted file mode 100644
index 8e1564635..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/.NET/src/App.config
+++ /dev/null
@@ -1,6 +0,0 @@
-<?xml version="1.0" encoding="utf-8" ?>
-<configuration>
-    <startup> 
-        <supportedRuntime version="v4.0" sku=".NETFramework,Version=v4.5" />
-    </startup>
-</configuration>
\ No newline at end of file
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/.NET/src/BMP24toILI565.csproj b/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/.NET/src/BMP24toILI565.csproj
deleted file mode 100644
index 2d9c787ee..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/.NET/src/BMP24toILI565.csproj
+++ /dev/null
@@ -1,58 +0,0 @@
-<?xml version="1.0" encoding="utf-8"?>
-<Project ToolsVersion="4.0" DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
-  <Import Project="$(MSBuildExtensionsPath)\$(MSBuildToolsVersion)\Microsoft.Common.props" Condition="Exists('$(MSBuildExtensionsPath)\$(MSBuildToolsVersion)\Microsoft.Common.props')" />
-  <PropertyGroup>
-    <Configuration Condition=" '$(Configuration)' == '' ">Debug</Configuration>
-    <Platform Condition=" '$(Platform)' == '' ">AnyCPU</Platform>
-    <ProjectGuid>{D2F086B2-74B5-4256-BCEE-719106D306F9}</ProjectGuid>
-    <OutputType>Exe</OutputType>
-    <AppDesignerFolder>Properties</AppDesignerFolder>
-    <RootNamespace>BMP24toILI565</RootNamespace>
-    <AssemblyName>BMP24toILI565</AssemblyName>
-    <TargetFrameworkVersion>v4.5</TargetFrameworkVersion>
-    <FileAlignment>512</FileAlignment>
-  </PropertyGroup>
-  <PropertyGroup Condition=" '$(Configuration)|$(Platform)' == 'Debug|AnyCPU' ">
-    <PlatformTarget>AnyCPU</PlatformTarget>
-    <DebugSymbols>true</DebugSymbols>
-    <DebugType>full</DebugType>
-    <Optimize>false</Optimize>
-    <OutputPath>bin\Debug\</OutputPath>
-    <DefineConstants>DEBUG;TRACE</DefineConstants>
-    <ErrorReport>prompt</ErrorReport>
-    <WarningLevel>4</WarningLevel>
-  </PropertyGroup>
-  <PropertyGroup Condition=" '$(Configuration)|$(Platform)' == 'Release|AnyCPU' ">
-    <PlatformTarget>AnyCPU</PlatformTarget>
-    <DebugType>pdbonly</DebugType>
-    <Optimize>true</Optimize>
-    <OutputPath>bin\Release\</OutputPath>
-    <DefineConstants>TRACE</DefineConstants>
-    <ErrorReport>prompt</ErrorReport>
-    <WarningLevel>4</WarningLevel>
-  </PropertyGroup>
-  <ItemGroup>
-    <Reference Include="System" />
-    <Reference Include="System.Core" />
-    <Reference Include="System.Xml.Linq" />
-    <Reference Include="System.Data.DataSetExtensions" />
-    <Reference Include="Microsoft.CSharp" />
-    <Reference Include="System.Data" />
-    <Reference Include="System.Xml" />
-  </ItemGroup>
-  <ItemGroup>
-    <Compile Include="Program.cs" />
-    <Compile Include="Properties\AssemblyInfo.cs" />
-  </ItemGroup>
-  <ItemGroup>
-    <None Include="App.config" />
-  </ItemGroup>
-  <Import Project="$(MSBuildToolsPath)\Microsoft.CSharp.targets" />
-  <!-- To modify your build process, add your task inside one of the targets below and uncomment it. 
-       Other similar extension points exist, see Microsoft.Common.targets.
-  <Target Name="BeforeBuild">
-  </Target>
-  <Target Name="AfterBuild">
-  </Target>
-  -->
-</Project>
\ No newline at end of file
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/.NET/src/BMP24toILI565.csproj.user b/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/.NET/src/BMP24toILI565.csproj.user
deleted file mode 100644
index 509f79301..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/.NET/src/BMP24toILI565.csproj.user
+++ /dev/null
@@ -1,7 +0,0 @@
-<?xml version="1.0" encoding="utf-8"?>
-<Project ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
-  <PropertyGroup Condition="'$(Configuration)|$(Platform)' == 'Debug|AnyCPU'">
-    <StartArguments>
-    </StartArguments>
-  </PropertyGroup>
-</Project>
\ No newline at end of file
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/.NET/src/BMP24toILI565.sln b/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/.NET/src/BMP24toILI565.sln
deleted file mode 100644
index 803a209b7..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/.NET/src/BMP24toILI565.sln
+++ /dev/null
@@ -1,20 +0,0 @@
-
-Microsoft Visual Studio Solution File, Format Version 12.00
-# Visual Studio 2012
-Project("{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC}") = "BMP24toILI565", "BMP24toILI565.csproj", "{D2F086B2-74B5-4256-BCEE-719106D306F9}"
-EndProject
-Global
-	GlobalSection(SolutionConfigurationPlatforms) = preSolution
-		Debug|Any CPU = Debug|Any CPU
-		Release|Any CPU = Release|Any CPU
-	EndGlobalSection
-	GlobalSection(ProjectConfigurationPlatforms) = postSolution
-		{D2F086B2-74B5-4256-BCEE-719106D306F9}.Debug|Any CPU.ActiveCfg = Debug|Any CPU
-		{D2F086B2-74B5-4256-BCEE-719106D306F9}.Debug|Any CPU.Build.0 = Debug|Any CPU
-		{D2F086B2-74B5-4256-BCEE-719106D306F9}.Release|Any CPU.ActiveCfg = Release|Any CPU
-		{D2F086B2-74B5-4256-BCEE-719106D306F9}.Release|Any CPU.Build.0 = Release|Any CPU
-	EndGlobalSection
-	GlobalSection(SolutionProperties) = preSolution
-		HideSolutionNode = FALSE
-	EndGlobalSection
-EndGlobal
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/.NET/src/Program.cs b/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/.NET/src/Program.cs
deleted file mode 100644
index 995c29083..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/.NET/src/Program.cs
+++ /dev/null
@@ -1,210 +0,0 @@
-using System;
-using System.Collections.Generic;
-using System.IO;
-using System.Linq;
-using System.Reflection;
-using System.Text;
-using System.Threading.Tasks;
-
-namespace BMP24toILI565
-{
-    internal class Program
-    {
-        static private FileStream rgb24file;
-        static private FileStream rgb16file;
-        static private int bmpWidth, bmpHeight; // W+H in pixels
-        static private int bmpDepth; // Bit depth (currently must be 24)
-        static private UInt32 bmpImageoffset; // Start of image data in file
-        static private int rowSize; // Not always = bmpWidth; may have padding
-        static private bool goodBmp = false; // Set to true on valid header parse
-        static private bool flip = true; // BMP is stored bottom-to-top
-        static private UInt16 w, h, row, col;
-        static private byte r, g, b;
-        static private long pos = 0, startTime;
-        static private bool first = true;
-
-
-        private static void Main(string[] args)
-        {
-            string codeBase = Assembly.GetExecutingAssembly().CodeBase;
-            string exeFilename = Path.GetFileName(codeBase);
-
-            if (args.Length == 0)
-            {
-                var bmpFiles = Directory.EnumerateFiles(Directory.GetCurrentDirectory(), "*.bmp").ToList();
-                if (bmpFiles.Count == 0)
-                    Console.WriteLine("\nNo .bmp files found.");
-                else
-                    bmpFiles.ForEach(i => ConvertImage(i));
-            }
-            else
-            {
-                ConvertImage(args[0]);
-            }
-        }
-
-        static void ConvertImage(string imageFilename)
-        {
-            if (File.Exists(imageFilename))
-            {
-                try
-                {
-                    Console.WriteLine("\nConverting {0}...", imageFilename);
-                    rgb24file = new FileStream(imageFilename, FileMode.Open);
-                    if (rgb24file == null)
-                    {
-                        Console.WriteLine("Could not open {0}", imageFilename);
-                        return;
-                    }
-
-                    rgb24file.Seek(0, SeekOrigin.Begin);
-
-                    if (read16(rgb24file) != 0x4D42)
-                    {
-                        Console.WriteLine("Not a BMP file");
-                        return;
-                    }
-
-                    // BMP signature
-                    Console.WriteLine("File size: {0}", read32(rgb24file));
-                    read32(rgb24file); // Read & ignore creator bytes
-                    bmpImageoffset = read32(rgb24file); // Start of image data
-                    Console.WriteLine("Image Offset: {0}", bmpImageoffset);
-                    // Read DIB header
-                    Console.WriteLine("Header size: {0}", read32(rgb24file));
-                    bmpWidth = (UInt16)read32(rgb24file);
-                    bmpHeight = (UInt16)read32(rgb24file);
-                    if (read16(rgb24file) != 1) // # planes -- must be '1'
-                    {
-                        Console.WriteLine("Number of planes must be 1");
-                        return;
-                    }
-
-                    bmpDepth = read16(rgb24file); // bits per pixel
-                    Console.WriteLine("Bit Depth: {0}", bmpDepth);
-                    if (bmpDepth != 24)
-                    {
-                        Console.WriteLine("Image is not in 24bit");
-                        return;
-                    }
-
-                    if (read32(rgb24file) != 0) // 0 = uncompressed
-                    {
-                        Console.WriteLine("BMP must be in uncompressed format");
-                        return;
-                    }
-
-                    goodBmp = true; // Supported BMP format -- proceed!
-                    Console.WriteLine("Image size: {0}x{1}", bmpWidth, bmpHeight);
-
-                    string outFilename = Path.ChangeExtension(imageFilename, "565");
-
-                    Console.WriteLine("{0} created", outFilename);
-
-                    rgb16file = new FileStream(outFilename, FileMode.Create);
-
-                    if (rgb16file == null)
-                    {
-                        Console.WriteLine("Could not create file {0}", outFilename);
-                        return;
-                    }
-
-                    var header = new byte[54];
-
-                    rgb24file.Seek(0, SeekOrigin.Begin);
-                    rgb24file.Read(header, 0, 54);
-
-                    header[0x1C] = 16; // updage bit depth to 16 bpp
-
-                    rgb16file.Write(header, 0, 54);
-
-                    // BMP rows are padded (if needed) to 4-byte boundary
-                    rowSize = (bmpWidth * 3 + 3) & ~3;
-
-                    // If bmpHeight is negative, image is in top-down order.
-                    // This is not canon but has been observed in the wild.
-                    if (bmpHeight < 0)
-                    {
-                        bmpHeight = -bmpHeight;
-                        flip = false;
-                    }
-
-                    var inRGB = new byte[3];
-                    var outRGB = new byte[2];
-
-                    for (row = 0; row < bmpHeight; row++)
-                    {
-                        // For each scanline...
-
-                        if (flip) // Bitmap is stored bottom-to-top order (normal BMP)
-                            pos = bmpImageoffset + (bmpHeight - 1 - row) * rowSize;
-                        else // Bitmap is stored top-to-bottom
-                            pos = bmpImageoffset + row * rowSize;
-
-                        rgb24file.Seek(pos, SeekOrigin.Begin);
-
-                        for (var c = 0; c < 3 * bmpWidth; c += 3)
-                        {
-                            rgb24file.Read(inRGB, 0, 3);
-
-                            UInt16 iliColor = to565(inRGB[2], inRGB[1], inRGB[0]);
-                            outRGB[0] = (byte)(iliColor >> 8);
-                            outRGB[1] = (byte)(iliColor & 0xFF);
-                            rgb16file.Write(outRGB, 0, 2);
-                        }
-                    }
-                }
-                catch (Exception ex)
-                {
-                    Console.WriteLine(ex.Message);
-                    Console.WriteLine(ex.StackTrace);
-                }
-                finally
-                {
-                    if (rgb24file != null)
-                    {
-                        rgb24file.Close();
-                        rgb24file = null;
-                    }
-                    if (rgb16file != null)
-                    {
-                        rgb16file.Close();
-                        rgb16file = null;
-                    }
-                }
-            }
-            else
-            {
-                Console.WriteLine("File {0} does not exists");
-            }
-        }
-
-        static private UInt16 to565(byte r, byte g, byte b)
-        {
-            return (UInt16)(((r & 0xF8) << 8) | ((g & 0xFC) << 3) | (b >> 3));
-            //return ((red >> 3) << 11) | ((green >> 2) << 5) | (blue >> 3);
-        }
-
-        static UInt16 read16(FileStream file)
-        {
-            var bytes = new byte[2];
-
-            file.Read(bytes, 0, 2);
-            var word = (UInt16)(bytes[1] << 8 | bytes[0]);
-
-            return word;
-        }
-
-        static UInt32 read32(FileStream file)
-        {
-            var bytes = new byte[4];
-
-            file.Read(bytes, 0, 4);
-            var dword = (UInt32)(bytes[3] << 24 | bytes[2] << 16 | bytes[1] << 8 | bytes[0]);
-
-            return dword;
-        }
-    }
-
-
-}
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/.NET/src/Properties/AssemblyInfo.cs b/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/.NET/src/Properties/AssemblyInfo.cs
deleted file mode 100644
index c7a75dc83..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/.NET/src/Properties/AssemblyInfo.cs
+++ /dev/null
@@ -1,36 +0,0 @@
-using System.Reflection;
-using System.Runtime.CompilerServices;
-using System.Runtime.InteropServices;
-
-// General Information about an assembly is controlled through the following 
-// set of attributes. Change these attribute values to modify the information
-// associated with an assembly.
-[assembly: AssemblyTitle("BMP24toILI565")]
-[assembly: AssemblyDescription("")]
-[assembly: AssemblyConfiguration("")]
-[assembly: AssemblyCompany("Microsoft")]
-[assembly: AssemblyProduct("BMP24toILI565")]
-[assembly: AssemblyCopyright("Copyright © Microsoft 2014")]
-[assembly: AssemblyTrademark("")]
-[assembly: AssemblyCulture("")]
-
-// Setting ComVisible to false makes the types in this assembly not visible 
-// to COM components.  If you need to access a type in this assembly from 
-// COM, set the ComVisible attribute to true on that type.
-[assembly: ComVisible(false)]
-
-// The following GUID is for the ID of the typelib if this project is exposed to COM
-[assembly: Guid("79edc0d8-9635-4e86-9a00-3e845d89d64b")]
-
-// Version information for an assembly consists of the following four values:
-//
-//      Major Version
-//      Minor Version 
-//      Build Number
-//      Revision
-//
-// You can specify all the values or you can default the Build and Revision Numbers 
-// by using the '*' as shown below:
-// [assembly: AssemblyVersion("1.0.*")]
-[assembly: AssemblyVersion("1.0.0.0")]
-[assembly: AssemblyFileVersion("1.0.0.0")]
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/BMP24toILI565.exe b/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/BMP24toILI565.exe
deleted file mode 100644
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diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/BMP24toILI565.cpp b/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/BMP24toILI565.cpp
deleted file mode 100644
index db3398cad..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/BMP24toILI565.cpp
+++ /dev/null
@@ -1,210 +0,0 @@
-// BMP24toILI565.cpp : Defines the entry point for the console application.
-//
-
-#include "stdafx.h"
-#include <stdio.h>
-#include <string.h>
-#include <windows.h>
-#include "dirent.h"
-
-FILE *rgb24file;
-FILE *rgb16file;
-int bmpWidth, bmpHeight;   // W+H in pixels
-UINT16  bmpDepth;              // Bit depth (currently must be 24)
-UINT32 bmpImageoffset;        // Start of image data in file
-UINT32 rowSize;               // Not always = bmpWidth; may have padding
-boolean  goodBmp = false;       // Set to true on valid header parse
-boolean  flip    = true;        // BMP is stored bottom-to-top
-UINT16 w, h, row, col;
-UINT8  r, g, b;
-UINT32 pos = 0, startTime;
-bool  first = true;
-DIR* dir;
-struct dirent *ent;
-
-
-//inline UINT16 read16(FILE *file)
-//{
-//	UINT16 word;
-//	fread(&word, 2, 1, file);
-//	return word;
-//}
-
-//inline UINT16 read32(FILE *file)
-//{
-//	UINT32 dword;
-//	fread(&dword, 4, 1, file);
-//	return dword;
-//}
-
-UINT16 read16(FILE *file) {
-	UINT16 word;
-	fread(&(((UINT8 *)&word)[0]), 1, 1, file);
-	fread(&(((UINT8 *)&word)[1]), 1, 1, file);
-	//((UINT8 *)&word)[0] = f.read(); // LSB
-	//((UINT8 *)&word)[1] = f.read(); // MSB
-	return word;
-}
-//
-UINT32 read32(FILE *file) {
-	UINT32 dword;
-	fread(&(((UINT8 *)&dword)[0]), 1, 1, file);
-	fread(&(((UINT8 *)&dword)[1]), 1, 1, file);
-	fread(&(((UINT8 *)&dword)[2]), 1, 1, file);
-	fread(&(((UINT8 *)&dword)[3]), 1, 1, file);
-	return dword;
-}
-
-inline UINT16 to565(UINT8 r, UINT8 g, UINT8 b) 
-{
-	return ((r & 0xF8) << 8) | ((g & 0xFC) << 3) | (b >> 3);
-	//return ((red >> 3) << 11) | ((green >> 2) << 5) | (blue >> 3);
-}
-
-int convertImage(char* filename)
-{
-	try
-	{
-		printf("\n");
-		printf("Converting %s...\n", filename);
-		rgb24file = fopen(filename, "rb");
-		if (rgb24file == NULL)
-		{
-			printf("Could not find file %s \n", filename);
-			return -1;
-		}
-
-		fseek(rgb24file, 0, SEEK_SET);
-
-		if(read16(rgb24file) != 0x4D42)  // BMP signature
-		{
-			printf("Not a BMP file.\n");
-			return -1;
-		}
-
-		printf("File size: %u\n", read32(rgb24file));
-		(void)read32(rgb24file); // Read & ignore creator bytes
-		bmpImageoffset = read32(rgb24file); // Start of image data
-		printf("Image Offset: %d\n", bmpImageoffset);
-		// Read DIB header
-		printf("Header size: %d\n", read32(rgb24file));
-		bmpWidth  = read32(rgb24file);
-		bmpHeight = read32(rgb24file);
-
-		if(read16(rgb24file) != 1) // # planes -- must be '1'
-		{
-			printf("Number of planes must be 1\n");
-			return -1;
-		}
-
-		bmpDepth = read16(rgb24file); // bits per pixel
-		printf("Bit Depth: %d\n", bmpDepth);
-
-		if(bmpDepth != 24)
-		{ 
-			printf("Image is not in 24bit\n");
-			return -1;
-		}
-
-		if(read32(rgb24file) != 0)  // 0 = uncompressed
-		{
-			printf("BMP must be in uncompressed format\n");
-			return -1;
-		}
-
-		goodBmp = true; // Supported BMP format -- proceed!
-		printf("Image size: %dx%d\n", bmpWidth, bmpHeight);
-
-		char outFilename[255];
-		sprintf(outFilename, "%s", filename);
-		sprintf(outFilename+strlen(filename)-3, "565");
-
-		printf("%s created\n", outFilename);
-		rgb16file = fopen(outFilename, "wb");
-
-		if(rgb16file == NULL)
-		{
-			printf("Could not create file %s\n", outFilename);
-			return -1;
-		}
-
-		UINT8 header[54];
-		fseek(rgb24file, 0, SEEK_SET);
-		fread(header, 1, 54, rgb24file);
-
-		header[0x1C] = 16;	// updage bit depth to 16 bpp
-
-		fwrite(header, 1, 54, rgb16file);
-
-		// BMP rows are padded (if needed) to 4-byte boundary
-		rowSize = (bmpWidth * 3 + 3) & ~3;
-
-		// If bmpHeight is negative, image is in top-down order.
-		// This is not canon but has been observed in the wild.
-		if(bmpHeight < 0) {
-			bmpHeight = -bmpHeight;
-			flip      = false;
-		}
-
-		UINT8 inRGB[3], outRGB[2];
-
-		for (row=0; row<bmpHeight; row++) { // For each scanline...
-
-			if(flip) // Bitmap is stored bottom-to-top order (normal BMP)
-				pos = bmpImageoffset + (bmpHeight - 1 - row) * rowSize;
-			else     // Bitmap is stored top-to-bottom
-				pos = bmpImageoffset + row * rowSize;
-
-			fseek(rgb24file, pos, SEEK_SET);
-
-			for(UINT16 c=0; c<3*bmpWidth; c+=3)
-			{
-				fread(inRGB, 1, 3, rgb24file);
-				UINT16 iliColor = to565(inRGB[2], inRGB[1], inRGB[0]);
-				outRGB[0] = iliColor >> 8;
-				outRGB[1] = iliColor & 0xFF;
-				fwrite(outRGB, 1, 2, rgb16file);
-			}
-		}
-	}
-	catch(...)
-	{
-		printf("Error converting file\n");
-	}
-
-	_fcloseall();
-}
-
-int main(int argc, char *argv[])
-{
-	if (argc == 1)
-	{
-		if ((dir = opendir (".")) != NULL) {
-			/* print all the files and directories within directory */
-			int bmpFilesFound = 0;
-			while ((ent = readdir(dir)) != NULL) {
-				if(strncmp(ent->d_name + ent->d_namlen - 4, ".bmp", 4) == 0)
-				{
-					convertImage(ent->d_name);
-					bmpFilesFound++;
-				}
-			}
-			closedir (dir);
-			if(bmpFilesFound == 0)
-			{
-				printf("\n");
-				printf("No .bmp files found.\n");
-			}
-		} else {
-			/* could not open directory */
-			perror ("");
-			return EXIT_FAILURE;
-		}
-	}
-	else
-	{
-		convertImage(argv[1]);
-	}
-
-
-}
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/BMP24toILI565.sln b/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/BMP24toILI565.sln
deleted file mode 100644
index a3eee5bb1..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/BMP24toILI565.sln
+++ /dev/null
@@ -1,20 +0,0 @@
-
-Microsoft Visual Studio Solution File, Format Version 12.00
-# Visual Studio 2012
-Project("{8BC9CEB8-8B4A-11D0-8D11-00A0C91BC942}") = "BMP24toILI565", "BMP24toILI565.vcxproj", "{EFE947CC-711C-44E0-9FA5-605D37DD3E8C}"
-EndProject
-Global
-	GlobalSection(SolutionConfigurationPlatforms) = preSolution
-		Debug|Win32 = Debug|Win32
-		Release|Win32 = Release|Win32
-	EndGlobalSection
-	GlobalSection(ProjectConfigurationPlatforms) = postSolution
-		{EFE947CC-711C-44E0-9FA5-605D37DD3E8C}.Debug|Win32.ActiveCfg = Debug|Win32
-		{EFE947CC-711C-44E0-9FA5-605D37DD3E8C}.Debug|Win32.Build.0 = Debug|Win32
-		{EFE947CC-711C-44E0-9FA5-605D37DD3E8C}.Release|Win32.ActiveCfg = Release|Win32
-		{EFE947CC-711C-44E0-9FA5-605D37DD3E8C}.Release|Win32.Build.0 = Release|Win32
-	EndGlobalSection
-	GlobalSection(SolutionProperties) = preSolution
-		HideSolutionNode = FALSE
-	EndGlobalSection
-EndGlobal
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/BMP24toILI565.vcxproj b/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/BMP24toILI565.vcxproj
deleted file mode 100644
index 4157e33fb..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/BMP24toILI565.vcxproj
+++ /dev/null
@@ -1,95 +0,0 @@
-<?xml version="1.0" encoding="utf-8"?>
-<Project DefaultTargets="Build" ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
-  <ItemGroup Label="ProjectConfigurations">
-    <ProjectConfiguration Include="Debug|Win32">
-      <Configuration>Debug</Configuration>
-      <Platform>Win32</Platform>
-    </ProjectConfiguration>
-    <ProjectConfiguration Include="Release|Win32">
-      <Configuration>Release</Configuration>
-      <Platform>Win32</Platform>
-    </ProjectConfiguration>
-  </ItemGroup>
-  <PropertyGroup Label="Globals">
-    <ProjectGuid>{EFE947CC-711C-44E0-9FA5-605D37DD3E8C}</ProjectGuid>
-    <Keyword>Win32Proj</Keyword>
-    <RootNamespace>BMP24toILI565</RootNamespace>
-  </PropertyGroup>
-  <Import Project="$(VCTargetsPath)\Microsoft.Cpp.Default.props" />
-  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'" Label="Configuration">
-    <ConfigurationType>Application</ConfigurationType>
-    <UseDebugLibraries>true</UseDebugLibraries>
-    <PlatformToolset>v110</PlatformToolset>
-    <CharacterSet>Unicode</CharacterSet>
-  </PropertyGroup>
-  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'" Label="Configuration">
-    <ConfigurationType>Application</ConfigurationType>
-    <UseDebugLibraries>false</UseDebugLibraries>
-    <PlatformToolset>v110</PlatformToolset>
-    <WholeProgramOptimization>true</WholeProgramOptimization>
-    <CharacterSet>Unicode</CharacterSet>
-  </PropertyGroup>
-  <Import Project="$(VCTargetsPath)\Microsoft.Cpp.props" />
-  <ImportGroup Label="ExtensionSettings">
-  </ImportGroup>
-  <ImportGroup Label="PropertySheets" Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
-    <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
-  </ImportGroup>
-  <ImportGroup Label="PropertySheets" Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
-    <Import Project="$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props" Condition="exists('$(UserRootDir)\Microsoft.Cpp.$(Platform).user.props')" Label="LocalAppDataPlatform" />
-  </ImportGroup>
-  <PropertyGroup Label="UserMacros" />
-  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
-    <LinkIncremental>true</LinkIncremental>
-  </PropertyGroup>
-  <PropertyGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
-    <LinkIncremental>false</LinkIncremental>
-  </PropertyGroup>
-  <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">
-    <ClCompile>
-      <PrecompiledHeader>Use</PrecompiledHeader>
-      <WarningLevel>Level3</WarningLevel>
-      <Optimization>Disabled</Optimization>
-      <PreprocessorDefinitions>WIN32;_DEBUG;_CONSOLE;_CRT_SECURE_NO_WARNINGS;%(PreprocessorDefinitions)</PreprocessorDefinitions>
-      <SDLCheck>true</SDLCheck>
-    </ClCompile>
-    <Link>
-      <SubSystem>Console</SubSystem>
-      <GenerateDebugInformation>true</GenerateDebugInformation>
-    </Link>
-  </ItemDefinitionGroup>
-  <ItemDefinitionGroup Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">
-    <ClCompile>
-      <WarningLevel>Level3</WarningLevel>
-      <PrecompiledHeader>Use</PrecompiledHeader>
-      <Optimization>MaxSpeed</Optimization>
-      <FunctionLevelLinking>true</FunctionLevelLinking>
-      <IntrinsicFunctions>true</IntrinsicFunctions>
-      <PreprocessorDefinitions>WIN32;NDEBUG;_CONSOLE;%(PreprocessorDefinitions)</PreprocessorDefinitions>
-      <SDLCheck>true</SDLCheck>
-    </ClCompile>
-    <Link>
-      <SubSystem>Console</SubSystem>
-      <GenerateDebugInformation>true</GenerateDebugInformation>
-      <EnableCOMDATFolding>true</EnableCOMDATFolding>
-      <OptimizeReferences>true</OptimizeReferences>
-    </Link>
-  </ItemDefinitionGroup>
-  <ItemGroup>
-    <Text Include="ReadMe.txt" />
-  </ItemGroup>
-  <ItemGroup>
-    <ClInclude Include="stdafx.h" />
-    <ClInclude Include="targetver.h" />
-  </ItemGroup>
-  <ItemGroup>
-    <ClCompile Include="BMP24toILI565.cpp" />
-    <ClCompile Include="stdafx.cpp">
-      <PrecompiledHeader Condition="'$(Configuration)|$(Platform)'=='Debug|Win32'">Create</PrecompiledHeader>
-      <PrecompiledHeader Condition="'$(Configuration)|$(Platform)'=='Release|Win32'">Create</PrecompiledHeader>
-    </ClCompile>
-  </ItemGroup>
-  <Import Project="$(VCTargetsPath)\Microsoft.Cpp.targets" />
-  <ImportGroup Label="ExtensionTargets">
-  </ImportGroup>
-</Project>
\ No newline at end of file
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/BMP24toILI565.vcxproj.filters b/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/BMP24toILI565.vcxproj.filters
deleted file mode 100644
index 515d07315..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/BMP24toILI565.vcxproj.filters
+++ /dev/null
@@ -1,36 +0,0 @@
-<?xml version="1.0" encoding="utf-8"?>
-<Project ToolsVersion="4.0" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
-  <ItemGroup>
-    <Filter Include="Source Files">
-      <UniqueIdentifier>{4FC737F1-C7A5-4376-A066-2A32D752A2FF}</UniqueIdentifier>
-      <Extensions>cpp;c;cc;cxx;def;odl;idl;hpj;bat;asm;asmx</Extensions>
-    </Filter>
-    <Filter Include="Header Files">
-      <UniqueIdentifier>{93995380-89BD-4b04-88EB-625FBE52EBFB}</UniqueIdentifier>
-      <Extensions>h;hpp;hxx;hm;inl;inc;xsd</Extensions>
-    </Filter>
-    <Filter Include="Resource Files">
-      <UniqueIdentifier>{67DA6AB6-F800-4c08-8B7A-83BB121AAD01}</UniqueIdentifier>
-      <Extensions>rc;ico;cur;bmp;dlg;rc2;rct;bin;rgs;gif;jpg;jpeg;jpe;resx;tiff;tif;png;wav;mfcribbon-ms</Extensions>
-    </Filter>
-  </ItemGroup>
-  <ItemGroup>
-    <Text Include="ReadMe.txt" />
-  </ItemGroup>
-  <ItemGroup>
-    <ClInclude Include="stdafx.h">
-      <Filter>Header Files</Filter>
-    </ClInclude>
-    <ClInclude Include="targetver.h">
-      <Filter>Header Files</Filter>
-    </ClInclude>
-  </ItemGroup>
-  <ItemGroup>
-    <ClCompile Include="stdafx.cpp">
-      <Filter>Source Files</Filter>
-    </ClCompile>
-    <ClCompile Include="BMP24toILI565.cpp">
-      <Filter>Source Files</Filter>
-    </ClCompile>
-  </ItemGroup>
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\ No newline at end of file
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/ReadMe.txt b/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/ReadMe.txt
deleted file mode 100644
index b72047adb..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/ReadMe.txt
+++ /dev/null
@@ -1,40 +0,0 @@
-========================================================================
-    CONSOLE APPLICATION : BMP24toILI565 Project Overview
-========================================================================
-
-AppWizard has created this BMP24toILI565 application for you.
-
-This file contains a summary of what you will find in each of the files that
-make up your BMP24toILI565 application.
-
-
-BMP24toILI565.vcxproj
-    This is the main project file for VC++ projects generated using an Application Wizard.
-    It contains information about the version of Visual C++ that generated the file, and
-    information about the platforms, configurations, and project features selected with the
-    Application Wizard.
-
-BMP24toILI565.vcxproj.filters
-    This is the filters file for VC++ projects generated using an Application Wizard. 
-    It contains information about the association between the files in your project 
-    and the filters. This association is used in the IDE to show grouping of files with
-    similar extensions under a specific node (for e.g. ".cpp" files are associated with the
-    "Source Files" filter).
-
-BMP24toILI565.cpp
-    This is the main application source file.
-
-/////////////////////////////////////////////////////////////////////////////
-Other standard files:
-
-StdAfx.h, StdAfx.cpp
-    These files are used to build a precompiled header (PCH) file
-    named BMP24toILI565.pch and a precompiled types file named StdAfx.obj.
-
-/////////////////////////////////////////////////////////////////////////////
-Other notes:
-
-AppWizard uses "TODO:" comments to indicate parts of the source code you
-should add to or customize.
-
-/////////////////////////////////////////////////////////////////////////////
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/dirent.h b/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/dirent.h
deleted file mode 100644
index 6f959a501..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/dirent.h
+++ /dev/null
@@ -1,838 +0,0 @@
-/*
- * dirent.h - dirent API for Microsoft Visual Studio
- *
- * Copyright (C) 2006-2012 Toni Ronkko
- *
- * Permission is hereby granted, free of charge, to any person obtaining
- * a copy of this software and associated documentation files (the
- * ``Software''), to deal in the Software without restriction, including
- * without limitation the rights to use, copy, modify, merge, publish,
- * distribute, sublicense, and/or sell copies of the Software, and to
- * permit persons to whom the Software is furnished to do so, subject to
- * the following conditions:
- *
- * The above copyright notice and this permission notice shall be included
- * in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED ``AS IS'', WITHOUT WARRANTY OF ANY KIND, EXPRESS
- * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
- * IN NO EVENT SHALL TONI RONKKO BE LIABLE FOR ANY CLAIM, DAMAGES OR
- * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
- * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
- * OTHER DEALINGS IN THE SOFTWARE.
- *
- * $Id: dirent.h,v 1.20 2014/03/19 17:52:23 tronkko Exp $
- */
-#ifndef DIRENT_H
-#define DIRENT_H
-
-/*
- * Define architecture flags so we don't need to include windows.h.
- * Avoiding windows.h makes it simpler to use windows sockets in conjunction
- * with dirent.h.
- */
-#if !defined(_68K_) && !defined(_MPPC_) && !defined(_X86_) && !defined(_IA64_) && !defined(_AMD64_) && defined(_M_IX86)
-#   define _X86_
-#endif
-#if !defined(_68K_) && !defined(_MPPC_) && !defined(_X86_) && !defined(_IA64_) && !defined(_AMD64_) && defined(_M_AMD64)
-#define _AMD64_
-#endif
-
-#include <stdio.h>
-#include <stdarg.h>
-#include <windef.h>
-#include <winbase.h>
-#include <wchar.h>
-#include <string.h>
-#include <stdlib.h>
-#include <malloc.h>
-#include <sys/types.h>
-#include <sys/stat.h>
-#include <errno.h>
-
-/* Indicates that d_type field is available in dirent structure */
-#define _DIRENT_HAVE_D_TYPE
-
-/* Indicates that d_namlen field is available in dirent structure */
-#define _DIRENT_HAVE_D_NAMLEN
-
-/* Entries missing from MSVC 6.0 */
-#if !defined(FILE_ATTRIBUTE_DEVICE)
-#   define FILE_ATTRIBUTE_DEVICE 0x40
-#endif
-
-/* File type and permission flags for stat() */
-#if !defined(S_IFMT)
-#   define S_IFMT   _S_IFMT                     /* File type mask */
-#endif
-#if !defined(S_IFDIR)
-#   define S_IFDIR  _S_IFDIR                    /* Directory */
-#endif
-#if !defined(S_IFCHR)
-#   define S_IFCHR  _S_IFCHR                    /* Character device */
-#endif
-#if !defined(S_IFFIFO)
-#   define S_IFFIFO _S_IFFIFO                   /* Pipe */
-#endif
-#if !defined(S_IFREG)
-#   define S_IFREG  _S_IFREG                    /* Regular file */
-#endif
-#if !defined(S_IREAD)
-#   define S_IREAD  _S_IREAD                    /* Read permission */
-#endif
-#if !defined(S_IWRITE)
-#   define S_IWRITE _S_IWRITE                   /* Write permission */
-#endif
-#if !defined(S_IEXEC)
-#   define S_IEXEC  _S_IEXEC                    /* Execute permission */
-#endif
-#if !defined(S_IFIFO)
-#   define S_IFIFO _S_IFIFO                     /* Pipe */
-#endif
-#if !defined(S_IFBLK)
-#   define S_IFBLK   0                          /* Block device */
-#endif
-#if !defined(S_IFLNK)
-#   define S_IFLNK   0                          /* Link */
-#endif
-#if !defined(S_IFSOCK)
-#   define S_IFSOCK  0                          /* Socket */
-#endif
-
-#if defined(_MSC_VER)
-#   define S_IRUSR  S_IREAD                     /* Read user */
-#   define S_IWUSR  S_IWRITE                    /* Write user */
-#   define S_IXUSR  0                           /* Execute user */
-#   define S_IRGRP  0                           /* Read group */
-#   define S_IWGRP  0                           /* Write group */
-#   define S_IXGRP  0                           /* Execute group */
-#   define S_IROTH  0                           /* Read others */
-#   define S_IWOTH  0                           /* Write others */
-#   define S_IXOTH  0                           /* Execute others */
-#endif
-
-/* Maximum length of file name */
-#if !defined(PATH_MAX)
-#   define PATH_MAX MAX_PATH
-#endif
-#if !defined(FILENAME_MAX)
-#   define FILENAME_MAX MAX_PATH
-#endif
-#if !defined(NAME_MAX)
-#   define NAME_MAX FILENAME_MAX
-#endif
-
-/* File type flags for d_type */
-#define DT_UNKNOWN  0
-#define DT_REG      S_IFREG
-#define DT_DIR      S_IFDIR
-#define DT_FIFO     S_IFIFO
-#define DT_SOCK     S_IFSOCK
-#define DT_CHR      S_IFCHR
-#define DT_BLK      S_IFBLK
-#define DT_LNK      S_IFLNK
-
-/* Macros for converting between st_mode and d_type */
-#define IFTODT(mode) ((mode) & S_IFMT)
-#define DTTOIF(type) (type)
-
-/*
- * File type macros.  Note that block devices, sockets and links cannot be
- * distinguished on Windows and the macros S_ISBLK, S_ISSOCK and S_ISLNK are
- * only defined for compatibility.  These macros should always return false
- * on Windows.
- */
-#define	S_ISFIFO(mode) (((mode) & S_IFMT) == S_IFIFO)
-#define	S_ISDIR(mode)  (((mode) & S_IFMT) == S_IFDIR)
-#define	S_ISREG(mode)  (((mode) & S_IFMT) == S_IFREG)
-#define	S_ISLNK(mode)  (((mode) & S_IFMT) == S_IFLNK)
-#define	S_ISSOCK(mode) (((mode) & S_IFMT) == S_IFSOCK)
-#define	S_ISCHR(mode)  (((mode) & S_IFMT) == S_IFCHR)
-#define	S_ISBLK(mode)  (((mode) & S_IFMT) == S_IFBLK)
-
-/* Return the exact length of d_namlen without zero terminator */
-#define _D_EXACT_NAMLEN(p) ((p)->d_namlen)
-
-/* Return number of bytes needed to store d_namlen */
-#define _D_ALLOC_NAMLEN(p) (PATH_MAX)
-
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-
-/* Wide-character version */
-struct _wdirent {
-    long d_ino;                                 /* Always zero */
-    unsigned short d_reclen;                    /* Structure size */
-    size_t d_namlen;                            /* Length of name without \0 */
-    int d_type;                                 /* File type */
-    wchar_t d_name[PATH_MAX];                   /* File name */
-};
-typedef struct _wdirent _wdirent;
-
-struct _WDIR {
-    struct _wdirent ent;                        /* Current directory entry */
-    WIN32_FIND_DATAW data;                      /* Private file data */
-    int cached;                                 /* True if data is valid */
-    HANDLE handle;                              /* Win32 search handle */
-    wchar_t *patt;                              /* Initial directory name */
-};
-typedef struct _WDIR _WDIR;
-
-static _WDIR *_wopendir (const wchar_t *dirname);
-static struct _wdirent *_wreaddir (_WDIR *dirp);
-static int _wclosedir (_WDIR *dirp);
-static void _wrewinddir (_WDIR* dirp);
-
-
-/* For compatibility with Symbian */
-#define wdirent _wdirent
-#define WDIR _WDIR
-#define wopendir _wopendir
-#define wreaddir _wreaddir
-#define wclosedir _wclosedir
-#define wrewinddir _wrewinddir
-
-
-/* Multi-byte character versions */
-struct dirent {
-    long d_ino;                                 /* Always zero */
-    unsigned short d_reclen;                    /* Structure size */
-    size_t d_namlen;                            /* Length of name without \0 */
-    int d_type;                                 /* File type */
-    char d_name[PATH_MAX];                      /* File name */
-};
-typedef struct dirent dirent;
-
-struct DIR {
-    struct dirent ent;
-    struct _WDIR *wdirp;
-};
-typedef struct DIR DIR;
-
-static DIR *opendir (const char *dirname);
-static struct dirent *readdir (DIR *dirp);
-static int closedir (DIR *dirp);
-static void rewinddir (DIR* dirp);
-
-
-/* Internal utility functions */
-static WIN32_FIND_DATAW *dirent_first (_WDIR *dirp);
-static WIN32_FIND_DATAW *dirent_next (_WDIR *dirp);
-
-static int dirent_mbstowcs_s(
-    size_t *pReturnValue,
-    wchar_t *wcstr,
-    size_t sizeInWords,
-    const char *mbstr,
-    size_t count);
-
-static int dirent_wcstombs_s(
-    size_t *pReturnValue,
-    char *mbstr,
-    size_t sizeInBytes,
-    const wchar_t *wcstr,
-    size_t count);
-
-static void dirent_set_errno (int error);
-
-/*
- * Open directory stream DIRNAME for read and return a pointer to the
- * internal working area that is used to retrieve individual directory
- * entries.
- */
-static _WDIR*
-_wopendir(
-    const wchar_t *dirname)
-{
-    _WDIR *dirp = NULL;
-    int error;
-
-    /* Must have directory name */
-    if (dirname == NULL  ||  dirname[0] == '\0') {
-        dirent_set_errno (ENOENT);
-        return NULL;
-    }
-
-    /* Allocate new _WDIR structure */
-    dirp = (_WDIR*) malloc (sizeof (struct _WDIR));
-    if (dirp != NULL) {
-        DWORD n;
-
-        /* Reset _WDIR structure */
-        dirp->handle = INVALID_HANDLE_VALUE;
-        dirp->patt = NULL;
-        dirp->cached = 0;
-
-        /* Compute the length of full path plus zero terminator */
-        n = GetFullPathNameW (dirname, 0, NULL, NULL);
-
-        /* Allocate room for absolute directory name and search pattern */
-        dirp->patt = (wchar_t*) malloc (sizeof (wchar_t) * n + 16);
-        if (dirp->patt) {
-
-            /*
-             * Convert relative directory name to an absolute one.  This
-             * allows rewinddir() to function correctly even when current
-             * working directory is changed between opendir() and rewinddir().
-             */
-            n = GetFullPathNameW (dirname, n, dirp->patt, NULL);
-            if (n > 0) {
-                wchar_t *p;
-
-                /* Append search pattern \* to the directory name */
-                p = dirp->patt + n;
-                if (dirp->patt < p) {
-                    switch (p[-1]) {
-                    case '\\':
-                    case '/':
-                    case ':':
-                        /* Directory ends in path separator, e.g. c:\temp\ */
-                        /*NOP*/;
-                        break;
-
-                    default:
-                        /* Directory name doesn't end in path separator */
-                        *p++ = '\\';
-                    }
-                }
-                *p++ = '*';
-                *p = '\0';
-
-                /* Open directory stream and retrieve the first entry */
-                if (dirent_first (dirp)) {
-                    /* Directory stream opened successfully */
-                    error = 0;
-                } else {
-                    /* Cannot retrieve first entry */
-                    error = 1;
-                    dirent_set_errno (ENOENT);
-                }
-
-            } else {
-                /* Cannot retrieve full path name */
-                dirent_set_errno (ENOENT);
-                error = 1;
-            }
-
-        } else {
-            /* Cannot allocate memory for search pattern */
-            error = 1;
-        }
-
-    } else {
-        /* Cannot allocate _WDIR structure */
-        error = 1;
-    }
-
-    /* Clean up in case of error */
-    if (error  &&  dirp) {
-        _wclosedir (dirp);
-        dirp = NULL;
-    }
-
-    return dirp;
-}
-
-/*
- * Read next directory entry.  The directory entry is returned in dirent
- * structure in the d_name field.  Individual directory entries returned by
- * this function include regular files, sub-directories, pseudo-directories
- * "." and ".." as well as volume labels, hidden files and system files.
- */
-static struct _wdirent*
-_wreaddir(
-    _WDIR *dirp)
-{
-    WIN32_FIND_DATAW *datap;
-    struct _wdirent *entp;
-
-    /* Read next directory entry */
-    datap = dirent_next (dirp);
-    if (datap) {
-        size_t n;
-        DWORD attr;
-        
-        /* Pointer to directory entry to return */
-        entp = &dirp->ent;
-
-        /* 
-         * Copy file name as wide-character string.  If the file name is too
-         * long to fit in to the destination buffer, then truncate file name
-         * to PATH_MAX characters and zero-terminate the buffer.
-         */
-        n = 0;
-        while (n + 1 < PATH_MAX  &&  datap->cFileName[n] != 0) {
-            entp->d_name[n] = datap->cFileName[n];
-            n++;
-        }
-        dirp->ent.d_name[n] = 0;
-
-        /* Length of file name excluding zero terminator */
-        entp->d_namlen = n;
-
-        /* File type */
-        attr = datap->dwFileAttributes;
-        if ((attr & FILE_ATTRIBUTE_DEVICE) != 0) {
-            entp->d_type = DT_CHR;
-        } else if ((attr & FILE_ATTRIBUTE_DIRECTORY) != 0) {
-            entp->d_type = DT_DIR;
-        } else {
-            entp->d_type = DT_REG;
-        }
-
-        /* Reset dummy fields */
-        entp->d_ino = 0;
-        entp->d_reclen = sizeof (struct _wdirent);
-
-    } else {
-
-        /* Last directory entry read */
-        entp = NULL;
-
-    }
-
-    return entp;
-}
-
-/*
- * Close directory stream opened by opendir() function.  This invalidates the
- * DIR structure as well as any directory entry read previously by
- * _wreaddir().
- */
-static int
-_wclosedir(
-    _WDIR *dirp)
-{
-    int ok;
-    if (dirp) {
-
-        /* Release search handle */
-        if (dirp->handle != INVALID_HANDLE_VALUE) {
-            FindClose (dirp->handle);
-            dirp->handle = INVALID_HANDLE_VALUE;
-        }
-
-        /* Release search pattern */
-        if (dirp->patt) {
-            free (dirp->patt);
-            dirp->patt = NULL;
-        }
-
-        /* Release directory structure */
-        free (dirp);
-        ok = /*success*/0;
-
-    } else {
-        /* Invalid directory stream */
-        dirent_set_errno (EBADF);
-        ok = /*failure*/-1;
-    }
-    return ok;
-}
-
-/*
- * Rewind directory stream such that _wreaddir() returns the very first
- * file name again.
- */
-static void
-_wrewinddir(
-    _WDIR* dirp)
-{
-    if (dirp) {
-        /* Release existing search handle */
-        if (dirp->handle != INVALID_HANDLE_VALUE) {
-            FindClose (dirp->handle);
-        }
-
-        /* Open new search handle */
-        dirent_first (dirp);
-    }
-}
-
-/* Get first directory entry (internal) */
-static WIN32_FIND_DATAW*
-dirent_first(
-    _WDIR *dirp)
-{
-    WIN32_FIND_DATAW *datap;
-
-    /* Open directory and retrieve the first entry */
-    dirp->handle = FindFirstFileW (dirp->patt, &dirp->data);
-    if (dirp->handle != INVALID_HANDLE_VALUE) {
-
-        /* a directory entry is now waiting in memory */
-        datap = &dirp->data;
-        dirp->cached = 1;
-
-    } else {
-
-        /* Failed to re-open directory: no directory entry in memory */
-        dirp->cached = 0;
-        datap = NULL;
-
-    }
-    return datap;
-}
-
-/* Get next directory entry (internal) */
-static WIN32_FIND_DATAW*
-dirent_next(
-    _WDIR *dirp)
-{
-    WIN32_FIND_DATAW *p;
-
-    /* Get next directory entry */
-    if (dirp->cached != 0) {
-
-        /* A valid directory entry already in memory */
-        p = &dirp->data;
-        dirp->cached = 0;
-
-    } else if (dirp->handle != INVALID_HANDLE_VALUE) {
-
-        /* Get the next directory entry from stream */
-        if (FindNextFileW (dirp->handle, &dirp->data) != FALSE) {
-            /* Got a file */
-            p = &dirp->data;
-        } else {
-            /* The very last entry has been processed or an error occured */
-            FindClose (dirp->handle);
-            dirp->handle = INVALID_HANDLE_VALUE;
-            p = NULL;
-        }
-
-    } else {
-
-        /* End of directory stream reached */
-        p = NULL;
-
-    }
-
-    return p;
-}
-
-/* 
- * Open directory stream using plain old C-string.
- */
-static DIR*
-opendir(
-    const char *dirname) 
-{
-    struct DIR *dirp;
-    int error;
-
-    /* Must have directory name */
-    if (dirname == NULL  ||  dirname[0] == '\0') {
-        dirent_set_errno (ENOENT);
-        return NULL;
-    }
-
-    /* Allocate memory for DIR structure */
-    dirp = (DIR*) malloc (sizeof (struct DIR));
-    if (dirp) {
-        wchar_t wname[PATH_MAX];
-        size_t n;
-
-        /* Convert directory name to wide-character string */
-        error = dirent_mbstowcs_s (&n, wname, PATH_MAX, dirname, PATH_MAX);
-        if (!error) {
-
-            /* Open directory stream using wide-character name */
-            dirp->wdirp = _wopendir (wname);
-            if (dirp->wdirp) {
-                /* Directory stream opened */
-                error = 0;
-            } else {
-                /* Failed to open directory stream */
-                error = 1;
-            }
-
-        } else {
-            /* 
-             * Cannot convert file name to wide-character string.  This
-             * occurs if the string contains invalid multi-byte sequences or
-             * the output buffer is too small to contain the resulting
-             * string.
-             */
-            error = 1;
-        }
-
-    } else {
-        /* Cannot allocate DIR structure */
-        error = 1;
-    }
-
-    /* Clean up in case of error */
-    if (error  &&  dirp) {
-        free (dirp);
-        dirp = NULL;
-    }
-
-    return dirp;
-}
-
-/*
- * Read next directory entry.
- *
- * When working with text consoles, please note that file names returned by
- * readdir() are represented in the default ANSI code page while any output to
- * console is typically formatted on another code page.  Thus, non-ASCII
- * characters in file names will not usually display correctly on console.  The
- * problem can be fixed in two ways: (1) change the character set of console
- * to 1252 using chcp utility and use Lucida Console font, or (2) use
- * _cprintf function when writing to console.  The _cprinf() will re-encode
- * ANSI strings to the console code page so many non-ASCII characters will
- * display correcly.
- */
-static struct dirent*
-readdir(
-    DIR *dirp) 
-{
-    WIN32_FIND_DATAW *datap;
-    struct dirent *entp;
-
-    /* Read next directory entry */
-    datap = dirent_next (dirp->wdirp);
-    if (datap) {
-        size_t n;
-        int error;
-
-        /* Attempt to convert file name to multi-byte string */
-        error = dirent_wcstombs_s(
-            &n, dirp->ent.d_name, PATH_MAX, datap->cFileName, PATH_MAX);
-
-        /* 
-         * If the file name cannot be represented by a multi-byte string,
-         * then attempt to use old 8+3 file name.  This allows traditional
-         * Unix-code to access some file names despite of unicode
-         * characters, although file names may seem unfamiliar to the user.
-         *
-         * Be ware that the code below cannot come up with a short file
-         * name unless the file system provides one.  At least
-         * VirtualBox shared folders fail to do this.
-         */
-        if (error  &&  datap->cAlternateFileName[0] != '\0') {
-            error = dirent_wcstombs_s(
-                &n, dirp->ent.d_name, PATH_MAX, 
-                datap->cAlternateFileName, PATH_MAX);
-        }
-
-        if (!error) {
-            DWORD attr;
-
-            /* Initialize directory entry for return */
-            entp = &dirp->ent;
-
-            /* Length of file name excluding zero terminator */
-            entp->d_namlen = n - 1;
-
-            /* File attributes */
-            attr = datap->dwFileAttributes;
-            if ((attr & FILE_ATTRIBUTE_DEVICE) != 0) {
-                entp->d_type = DT_CHR;
-            } else if ((attr & FILE_ATTRIBUTE_DIRECTORY) != 0) {
-                entp->d_type = DT_DIR;
-            } else {
-                entp->d_type = DT_REG;
-            }
-
-            /* Reset dummy fields */
-            entp->d_ino = 0;
-            entp->d_reclen = sizeof (struct dirent);
-
-        } else {
-            /* 
-             * Cannot convert file name to multi-byte string so construct
-             * an errornous directory entry and return that.  Note that
-             * we cannot return NULL as that would stop the processing
-             * of directory entries completely.
-             */
-            entp = &dirp->ent;
-            entp->d_name[0] = '?';
-            entp->d_name[1] = '\0';
-            entp->d_namlen = 1;
-            entp->d_type = DT_UNKNOWN;
-            entp->d_ino = 0;
-            entp->d_reclen = 0;
-        }
-
-    } else {
-        /* No more directory entries */
-        entp = NULL;
-    }
-
-    return entp;
-}
-
-/*
- * Close directory stream.
- */
-static int
-closedir(
-    DIR *dirp) 
-{
-    int ok;
-    if (dirp) {
-
-        /* Close wide-character directory stream */
-        ok = _wclosedir (dirp->wdirp);
-        dirp->wdirp = NULL;
-
-        /* Release multi-byte character version */
-        free (dirp);
-
-    } else {
-
-        /* Invalid directory stream */
-        dirent_set_errno (EBADF);
-        ok = /*failure*/-1;
-
-    }
-    return ok;
-}
-
-/*
- * Rewind directory stream to beginning.
- */
-static void
-rewinddir(
-    DIR* dirp) 
-{
-    /* Rewind wide-character string directory stream */
-    _wrewinddir (dirp->wdirp);
-}
-
-/* Convert multi-byte string to wide character string */
-static int
-dirent_mbstowcs_s(
-    size_t *pReturnValue,
-    wchar_t *wcstr,
-    size_t sizeInWords,
-    const char *mbstr,
-    size_t count)
-{
-    int error;
-
-#if defined(_MSC_VER)  &&  _MSC_VER >= 1400
-
-    /* Microsoft Visual Studio 2005 or later */
-    error = mbstowcs_s (pReturnValue, wcstr, sizeInWords, mbstr, count);
-
-#else
-
-    /* Older Visual Studio or non-Microsoft compiler */
-    size_t n;
-
-    /* Convert to wide-character string (or count characters) */
-    n = mbstowcs (wcstr, mbstr, sizeInWords);
-    if (!wcstr  ||  n < count) {
-
-        /* Zero-terminate output buffer */
-        if (wcstr  &&  sizeInWords) {
-            if (n >= sizeInWords) {
-                n = sizeInWords - 1;
-            }
-            wcstr[n] = 0;
-        }
-
-        /* Length of resuting multi-byte string WITH zero terminator */
-        if (pReturnValue) {
-            *pReturnValue = n + 1;
-        }
-
-        /* Success */
-        error = 0;
-
-    } else {
-
-        /* Could not convert string */
-        error = 1;
-
-    }
-
-#endif
-
-    return error;
-}
-
-/* Convert wide-character string to multi-byte string */
-static int
-dirent_wcstombs_s(
-    size_t *pReturnValue,
-    char *mbstr,
-    size_t sizeInBytes, /* max size of mbstr */
-    const wchar_t *wcstr,
-    size_t count)
-{
-    int error;
-
-#if defined(_MSC_VER)  &&  _MSC_VER >= 1400
-
-    /* Microsoft Visual Studio 2005 or later */
-    error = wcstombs_s (pReturnValue, mbstr, sizeInBytes, wcstr, count);
-
-#else
-
-    /* Older Visual Studio or non-Microsoft compiler */
-    size_t n;
-
-    /* Convert to multi-byte string (or count the number of bytes needed) */
-    n = wcstombs (mbstr, wcstr, sizeInBytes);
-    if (!mbstr  ||  n < count) {
-
-        /* Zero-terminate output buffer */
-        if (mbstr  &&  sizeInBytes) {
-            if (n >= sizeInBytes) {
-                n = sizeInBytes - 1;
-            }
-            mbstr[n] = '\0';
-        }
-
-        /* Lenght of resulting multi-bytes string WITH zero-terminator */
-        if (pReturnValue) {
-            *pReturnValue = n + 1;
-        }
-
-        /* Success */
-        error = 0;
-
-    } else {
-
-        /* Cannot convert string */
-        error = 1;
-
-    }
-
-#endif
-
-    return error;
-}
-
-/* Set errno variable */
-static void
-dirent_set_errno(
-    int error)
-{
-#if defined(_MSC_VER)  &&  _MSC_VER >= 1400
-
-    /* Microsoft Visual Studio 2005 and later */
-    _set_errno (error);
-
-#else
-
-    /* Non-Microsoft compiler or older Microsoft compiler */
-    errno = error;
-
-#endif
-}
-
-
-#ifdef __cplusplus
-}
-#endif
-#endif /*DIRENT_H*/
-
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/stdafx.cpp b/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/stdafx.cpp
deleted file mode 100644
index f913bf52c..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/stdafx.cpp
+++ /dev/null
@@ -1,8 +0,0 @@
-// stdafx.cpp : source file that includes just the standard includes
-// BMP24toILI565.pch will be the pre-compiled header
-// stdafx.obj will contain the pre-compiled type information
-
-#include "stdafx.h"
-
-// TODO: reference any additional headers you need in STDAFX.H
-// and not in this file
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/stdafx.h b/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/stdafx.h
deleted file mode 100644
index b005a839d..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/stdafx.h
+++ /dev/null
@@ -1,15 +0,0 @@
-// stdafx.h : include file for standard system include files,
-// or project specific include files that are used frequently, but
-// are changed infrequently
-//
-
-#pragma once
-
-#include "targetver.h"
-
-#include <stdio.h>
-#include <tchar.h>
-
-
-
-// TODO: reference additional headers your program requires here
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/targetver.h b/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/targetver.h
deleted file mode 100644
index 87c0086de..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/BMP24toILI565/C/src/targetver.h
+++ /dev/null
@@ -1,8 +0,0 @@
-#pragma once
-
-// Including SDKDDKVer.h defines the highest available Windows platform.
-
-// If you wish to build your application for a previous Windows platform, include WinSDKVer.h and
-// set the _WIN32_WINNT macro to the platform you wish to support before including SDKDDKVer.h.
-
-#include <SDKDDKVer.h>
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/GLCDFontCreator2.zip b/STM32F1/libraries/ILI9341_due_STM/tools/GLCDFontCreator2.zip
deleted file mode 100644
index c1373478ab6763f58d277975fbdfe371c3606475..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/ILIScreenshotViewer.exe b/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/ILIScreenshotViewer.exe
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diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/App.config b/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/App.config
deleted file mode 100644
index 8e1564635..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/App.config
+++ /dev/null
@@ -1,6 +0,0 @@
-<?xml version="1.0" encoding="utf-8" ?>
-<configuration>
-    <startup> 
-        <supportedRuntime version="v4.0" sku=".NETFramework,Version=v4.5" />
-    </startup>
-</configuration>
\ No newline at end of file
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Form1.Designer.cs b/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Form1.Designer.cs
deleted file mode 100644
index 75a958932..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Form1.Designer.cs
+++ /dev/null
@@ -1,108 +0,0 @@
-namespace ILIScreenshotViewer
-{
-    partial class Form1
-    {
-        /// <summary>
-        /// Required designer variable.
-        /// </summary>
-        private System.ComponentModel.IContainer components = null;
-
-        /// <summary>
-        /// Clean up any resources being used.
-        /// </summary>
-        /// <param name="disposing">true if managed resources should be disposed; otherwise, false.</param>
-        protected override void Dispose(bool disposing)
-        {
-            if (disposing && (components != null))
-            {
-                components.Dispose();
-            }
-            base.Dispose(disposing);
-        }
-
-        #region Windows Form Designer generated code
-
-        /// <summary>
-        /// Required method for Designer support - do not modify
-        /// the contents of this method with the code editor.
-        /// </summary>
-        private void InitializeComponent()
-        {
-            this.pictureBox = new System.Windows.Forms.PictureBox();
-            this.btnShow = new System.Windows.Forms.Button();
-            this.lblFailed = new System.Windows.Forms.Label();
-            this.btnSaveAs = new System.Windows.Forms.Button();
-            this.saveFileDialog = new System.Windows.Forms.SaveFileDialog();
-            ((System.ComponentModel.ISupportInitialize)(this.pictureBox)).BeginInit();
-            this.SuspendLayout();
-            // 
-            // pictureBox
-            // 
-            this.pictureBox.BorderStyle = System.Windows.Forms.BorderStyle.FixedSingle;
-            this.pictureBox.Location = new System.Drawing.Point(12, 12);
-            this.pictureBox.Name = "pictureBox";
-            this.pictureBox.Size = new System.Drawing.Size(320, 240);
-            this.pictureBox.TabIndex = 0;
-            this.pictureBox.TabStop = false;
-            // 
-            // btnShow
-            // 
-            this.btnShow.Location = new System.Drawing.Point(93, 258);
-            this.btnShow.Name = "btnShow";
-            this.btnShow.Size = new System.Drawing.Size(158, 23);
-            this.btnShow.TabIndex = 2;
-            this.btnShow.Text = "Load Image from Clipboard";
-            this.btnShow.UseVisualStyleBackColor = true;
-            this.btnShow.Click += new System.EventHandler(this.btnShow_Click);
-            // 
-            // lblFailed
-            // 
-            this.lblFailed.Location = new System.Drawing.Point(47, 84);
-            this.lblFailed.Name = "lblFailed";
-            this.lblFailed.Size = new System.Drawing.Size(251, 86);
-            this.lblFailed.TabIndex = 3;
-            this.lblFailed.Text = "Failed to load an image from clipboard";
-            this.lblFailed.TextAlign = System.Drawing.ContentAlignment.MiddleCenter;
-            this.lblFailed.Visible = false;
-            // 
-            // btnSaveAs
-            // 
-            this.btnSaveAs.Location = new System.Drawing.Point(258, 258);
-            this.btnSaveAs.Name = "btnSaveAs";
-            this.btnSaveAs.Size = new System.Drawing.Size(75, 23);
-            this.btnSaveAs.TabIndex = 4;
-            this.btnSaveAs.Text = "Save As...";
-            this.btnSaveAs.UseVisualStyleBackColor = true;
-            this.btnSaveAs.Visible = false;
-            this.btnSaveAs.Click += new System.EventHandler(this.btnSaveAs_Click);
-            // 
-            // saveFileDialog
-            // 
-            this.saveFileDialog.Filter = "*.bmp|*.bmp|*.png|*.png|*.gif|*.gif|*.jpg|*.jpg|All Files (*.*)|*.*";
-            // 
-            // Form1
-            // 
-            this.AutoScaleDimensions = new System.Drawing.SizeF(6F, 13F);
-            this.AutoScaleMode = System.Windows.Forms.AutoScaleMode.Font;
-            this.ClientSize = new System.Drawing.Size(347, 294);
-            this.Controls.Add(this.btnSaveAs);
-            this.Controls.Add(this.lblFailed);
-            this.Controls.Add(this.btnShow);
-            this.Controls.Add(this.pictureBox);
-            this.Name = "Form1";
-            this.Text = "ILI Screenshot Viewer";
-            ((System.ComponentModel.ISupportInitialize)(this.pictureBox)).EndInit();
-            this.ResumeLayout(false);
-
-        }
-
-        #endregion
-
-        private System.Windows.Forms.PictureBox pictureBox;
-        private System.Windows.Forms.Button btnShow;
-        private System.Windows.Forms.Label lblFailed;
-        private System.Windows.Forms.Button btnSaveAs;
-        private System.Windows.Forms.SaveFileDialog saveFileDialog;
-    }
-}
-
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Form1.cs b/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Form1.cs
deleted file mode 100644
index bef5b3b7a..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Form1.cs
+++ /dev/null
@@ -1,141 +0,0 @@
-using System;
-using System.Collections.Generic;
-using System.ComponentModel;
-using System.Drawing;
-using System.Drawing.Imaging;
-using System.IO;
-using System.Text;
-using System.Threading.Tasks;
-using System.Windows.Forms;
-
-namespace ILIScreenshotViewer
-{
-    public partial class Form1 : Form
-    {
-        public Form1()
-        {
-            InitializeComponent();
-        }
-
-        private void btnShow_Click(object sender, EventArgs e)
-        {
-            lblFailed.Visible = false;
-            var bitmap = new Bitmap(320, 240, PixelFormat.Format24bppRgb);
-
-            //var hexString = Clipboard.GetText();
-            //for (int x = 0; x < 320; x++)
-            //{
-            //    for (int y = 0; y < 240; y++)
-            //    {
-            //        var pixelColorString = hexString.Substring(4*x + 4*320*y, 4);
-
-            //        var pix = Convert.ToUInt16(pixelColorString, 16);
-
-
-            //        //* For PixelFormat.Format16bppRgb565
-            //        //var r = BitConverter.GetBytes((UInt16)((pix & 0xF800) >> 11));
-
-            //        int red = ((pix >> 11)*527 + 23) >> 6;
-            //        int green = (((pix >> 5) & 0x003F)*259 + 33) >> 6;
-            //        int blue = ((pix & 0x001F)*527 + 23) >> 6;
-
-            //        bitmap.SetPixel(x, y, Color.FromArgb(red, green, blue));
-            //    }
-            //}
-
-
-            try
-            {
-                string hexString = Clipboard.GetText();
-                //for (int x = 0; x < 320; x++)
-                //{
-                //    for (int y = 0; y < 240; y++)
-                //    {
-                //        var pixelColorString = hexString.Substring(6 * (x + 320 * y), 6);
-
-                //        var r = Convert.ToByte(pixelColorString.Substring(0, 2), 16);
-                //        var g = Convert.ToByte(pixelColorString.Substring(2, 2), 16);
-                //        var b = Convert.ToByte(pixelColorString.Substring(4, 2), 16);
-
-                //        //* For PixelFormat.Format16bppRgb565
-                //        //var r = BitConverter.GetBytes((UInt16)((pix & 0xF800) >> 11));
-
-                //        //int red = ((pix >> 11) * 527 + 23) >> 6;
-                //        //int green = (((pix >> 5) & 0x003F) * 259 + 33) >> 6;
-                //        //int blue = ((pix & 0x001F) * 527 + 23) >> 6;
-
-                //        bitmap.SetPixel(x, y, Color.FromArgb(r, g, b));
-                //    }
-                //}
-                int x = 0, y = 0;
-                var totalImageDataSize = Convert.ToUInt32(hexString.Substring(hexString.Length - 8, 8), 16);
-                if (hexString.Length - 8 == totalImageDataSize)
-                {
-                    for (int i = 0; i < totalImageDataSize; i += 10) // 6 bytes for color, 4 bytes for length
-                    {
-                        var pixelColorString = hexString.Substring(i, 6);
-                        var r = Convert.ToByte(pixelColorString.Substring(0, 2), 16);
-                        var g = Convert.ToByte(pixelColorString.Substring(2, 2), 16);
-                        var b = Convert.ToByte(pixelColorString.Substring(4, 2), 16);
-
-                        var pixelCountString = hexString.Substring(i + 6, 4);
-                        var pixelCount = Convert.ToUInt16(pixelCountString, 16);
-
-                        for (int p = 0; p < pixelCount; p++)
-                        {
-                            bitmap.SetPixel(x, y, Color.FromArgb(r, g, b));
-                            x++;
-                            if (x > 319)
-                            {
-                                x = 0;
-                                y++;
-                            }
-                        }
-                    }
-
-                    pictureBox.Image = bitmap;
-                    btnSaveAs.Visible = true;
-                }
-                else
-                {
-                    lblFailed.Text = "Image Data length mismatch.";
-                    pictureBox.Image = null;
-                    lblFailed.Visible = true;
-                    btnSaveAs.Visible = false;
-                }
-            }
-            catch
-            {
-                lblFailed.Text = "Failed to load an image from clipboard\nTry increasing ILI9341_SPI_CLKDIVIDER or\nchange to NORMAL or EXTENDED SPI mode.";
-                pictureBox.Image = null;
-                lblFailed.Visible = true;
-                btnSaveAs.Visible = false;
-            }
-        }
-
-        private void btnSaveAs_Click(object sender, EventArgs e)
-        {
-            saveFileDialog.FileName = Path.GetFileNameWithoutExtension(saveFileDialog.FileName);
-            var result = saveFileDialog.ShowDialog();
-            if (result == DialogResult.OK)
-            {
-                ImageFormat imageFormat = ImageFormat.Bmp;
-                switch (Path.GetExtension(saveFileDialog.FileName).ToLower())
-                {
-                    case ".jpg":
-                        imageFormat = ImageFormat.Jpeg;
-                        break;
-                    case ".png":
-                        imageFormat = ImageFormat.Png;
-                        break;
-                    case ".gif":
-                        imageFormat = ImageFormat.Gif;
-                        break;
-                }
-                pictureBox.Image.Save(saveFileDialog.FileName, imageFormat);
-            }
-
-    }
-
-    }
-}
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Form1.resx b/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Form1.resx
deleted file mode 100644
index 5e7f0a6fe..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Form1.resx
+++ /dev/null
@@ -1,123 +0,0 @@
-<?xml version="1.0" encoding="utf-8"?>
-<root>
-  <!-- 
-    Microsoft ResX Schema 
-    
-    Version 2.0
-    
-    The primary goals of this format is to allow a simple XML format 
-    that is mostly human readable. The generation and parsing of the 
-    various data types are done through the TypeConverter classes 
-    associated with the data types.
-    
-    Example:
-    
-    ... ado.net/XML headers & schema ...
-    <resheader name="resmimetype">text/microsoft-resx</resheader>
-    <resheader name="version">2.0</resheader>
-    <resheader name="reader">System.Resources.ResXResourceReader, System.Windows.Forms, ...</resheader>
-    <resheader name="writer">System.Resources.ResXResourceWriter, System.Windows.Forms, ...</resheader>
-    <data name="Name1"><value>this is my long string</value><comment>this is a comment</comment></data>
-    <data name="Color1" type="System.Drawing.Color, System.Drawing">Blue</data>
-    <data name="Bitmap1" mimetype="application/x-microsoft.net.object.binary.base64">
-        <value>[base64 mime encoded serialized .NET Framework object]</value>
-    </data>
-    <data name="Icon1" type="System.Drawing.Icon, System.Drawing" mimetype="application/x-microsoft.net.object.bytearray.base64">
-        <value>[base64 mime encoded string representing a byte array form of the .NET Framework object]</value>
-        <comment>This is a comment</comment>
-    </data>
-                
-    There are any number of "resheader" rows that contain simple 
-    name/value pairs.
-    
-    Each data row contains a name, and value. The row also contains a 
-    type or mimetype. Type corresponds to a .NET class that support 
-    text/value conversion through the TypeConverter architecture. 
-    Classes that don't support this are serialized and stored with the 
-    mimetype set.
-    
-    The mimetype is used for serialized objects, and tells the 
-    ResXResourceReader how to depersist the object. This is currently not 
-    extensible. For a given mimetype the value must be set accordingly:
-    
-    Note - application/x-microsoft.net.object.binary.base64 is the format 
-    that the ResXResourceWriter will generate, however the reader can 
-    read any of the formats listed below.
-    
-    mimetype: application/x-microsoft.net.object.binary.base64
-    value   : The object must be serialized with 
-            : System.Runtime.Serialization.Formatters.Binary.BinaryFormatter
-            : and then encoded with base64 encoding.
-    
-    mimetype: application/x-microsoft.net.object.soap.base64
-    value   : The object must be serialized with 
-            : System.Runtime.Serialization.Formatters.Soap.SoapFormatter
-            : and then encoded with base64 encoding.
-
-    mimetype: application/x-microsoft.net.object.bytearray.base64
-    value   : The object must be serialized into a byte array 
-            : using a System.ComponentModel.TypeConverter
-            : and then encoded with base64 encoding.
-    -->
-  <xsd:schema id="root" xmlns="" xmlns:xsd="http://www.w3.org/2001/XMLSchema" xmlns:msdata="urn:schemas-microsoft-com:xml-msdata">
-    <xsd:import namespace="http://www.w3.org/XML/1998/namespace" />
-    <xsd:element name="root" msdata:IsDataSet="true">
-      <xsd:complexType>
-        <xsd:choice maxOccurs="unbounded">
-          <xsd:element name="metadata">
-            <xsd:complexType>
-              <xsd:sequence>
-                <xsd:element name="value" type="xsd:string" minOccurs="0" />
-              </xsd:sequence>
-              <xsd:attribute name="name" use="required" type="xsd:string" />
-              <xsd:attribute name="type" type="xsd:string" />
-              <xsd:attribute name="mimetype" type="xsd:string" />
-              <xsd:attribute ref="xml:space" />
-            </xsd:complexType>
-          </xsd:element>
-          <xsd:element name="assembly">
-            <xsd:complexType>
-              <xsd:attribute name="alias" type="xsd:string" />
-              <xsd:attribute name="name" type="xsd:string" />
-            </xsd:complexType>
-          </xsd:element>
-          <xsd:element name="data">
-            <xsd:complexType>
-              <xsd:sequence>
-                <xsd:element name="value" type="xsd:string" minOccurs="0" msdata:Ordinal="1" />
-                <xsd:element name="comment" type="xsd:string" minOccurs="0" msdata:Ordinal="2" />
-              </xsd:sequence>
-              <xsd:attribute name="name" type="xsd:string" use="required" msdata:Ordinal="1" />
-              <xsd:attribute name="type" type="xsd:string" msdata:Ordinal="3" />
-              <xsd:attribute name="mimetype" type="xsd:string" msdata:Ordinal="4" />
-              <xsd:attribute ref="xml:space" />
-            </xsd:complexType>
-          </xsd:element>
-          <xsd:element name="resheader">
-            <xsd:complexType>
-              <xsd:sequence>
-                <xsd:element name="value" type="xsd:string" minOccurs="0" msdata:Ordinal="1" />
-              </xsd:sequence>
-              <xsd:attribute name="name" type="xsd:string" use="required" />
-            </xsd:complexType>
-          </xsd:element>
-        </xsd:choice>
-      </xsd:complexType>
-    </xsd:element>
-  </xsd:schema>
-  <resheader name="resmimetype">
-    <value>text/microsoft-resx</value>
-  </resheader>
-  <resheader name="version">
-    <value>2.0</value>
-  </resheader>
-  <resheader name="reader">
-    <value>System.Resources.ResXResourceReader, System.Windows.Forms, Version=4.0.0.0, Culture=neutral, PublicKeyToken=b77a5c561934e089</value>
-  </resheader>
-  <resheader name="writer">
-    <value>System.Resources.ResXResourceWriter, System.Windows.Forms, Version=4.0.0.0, Culture=neutral, PublicKeyToken=b77a5c561934e089</value>
-  </resheader>
-  <metadata name="saveFileDialog.TrayLocation" type="System.Drawing.Point, System.Drawing, Version=4.0.0.0, Culture=neutral, PublicKeyToken=b03f5f7f11d50a3a">
-    <value>17, 17</value>
-  </metadata>
-</root>
\ No newline at end of file
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/ILIScreenshotViewer.csproj b/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/ILIScreenshotViewer.csproj
deleted file mode 100644
index 30d5cb1fb..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/ILIScreenshotViewer.csproj
+++ /dev/null
@@ -1,82 +0,0 @@
-<?xml version="1.0" encoding="utf-8"?>
-<Project ToolsVersion="4.0" DefaultTargets="Build" xmlns="http://schemas.microsoft.com/developer/msbuild/2003">
-  <Import Project="$(MSBuildExtensionsPath)\$(MSBuildToolsVersion)\Microsoft.Common.props" Condition="Exists('$(MSBuildExtensionsPath)\$(MSBuildToolsVersion)\Microsoft.Common.props')" />
-  <PropertyGroup>
-    <Configuration Condition=" '$(Configuration)' == '' ">Debug</Configuration>
-    <Platform Condition=" '$(Platform)' == '' ">AnyCPU</Platform>
-    <ProjectGuid>{AD6D4A3D-2F94-435B-836F-E617ED847F46}</ProjectGuid>
-    <OutputType>WinExe</OutputType>
-    <AppDesignerFolder>Properties</AppDesignerFolder>
-    <RootNamespace>ILIScreenshotViewer</RootNamespace>
-    <AssemblyName>ILIScreenshotViewer</AssemblyName>
-    <TargetFrameworkVersion>v4.5</TargetFrameworkVersion>
-    <FileAlignment>512</FileAlignment>
-  </PropertyGroup>
-  <PropertyGroup Condition=" '$(Configuration)|$(Platform)' == 'Debug|AnyCPU' ">
-    <PlatformTarget>AnyCPU</PlatformTarget>
-    <DebugSymbols>true</DebugSymbols>
-    <DebugType>full</DebugType>
-    <Optimize>false</Optimize>
-    <OutputPath>bin\Debug\</OutputPath>
-    <DefineConstants>DEBUG;TRACE</DefineConstants>
-    <ErrorReport>prompt</ErrorReport>
-    <WarningLevel>4</WarningLevel>
-  </PropertyGroup>
-  <PropertyGroup Condition=" '$(Configuration)|$(Platform)' == 'Release|AnyCPU' ">
-    <PlatformTarget>AnyCPU</PlatformTarget>
-    <DebugType>pdbonly</DebugType>
-    <Optimize>true</Optimize>
-    <OutputPath>bin\Release\</OutputPath>
-    <DefineConstants>TRACE</DefineConstants>
-    <ErrorReport>prompt</ErrorReport>
-    <WarningLevel>4</WarningLevel>
-  </PropertyGroup>
-  <ItemGroup>
-    <Reference Include="System" />
-    <Reference Include="System.Core" />
-    <Reference Include="System.Drawing" />
-    <Reference Include="System.Windows.Forms" />
-  </ItemGroup>
-  <ItemGroup>
-    <Compile Include="Form1.cs">
-      <SubType>Form</SubType>
-    </Compile>
-    <Compile Include="Form1.Designer.cs">
-      <DependentUpon>Form1.cs</DependentUpon>
-    </Compile>
-    <Compile Include="Program.cs" />
-    <Compile Include="Properties\AssemblyInfo.cs" />
-    <EmbeddedResource Include="Form1.resx">
-      <DependentUpon>Form1.cs</DependentUpon>
-    </EmbeddedResource>
-    <EmbeddedResource Include="Properties\Resources.resx">
-      <Generator>ResXFileCodeGenerator</Generator>
-      <LastGenOutput>Resources.Designer.cs</LastGenOutput>
-      <SubType>Designer</SubType>
-    </EmbeddedResource>
-    <Compile Include="Properties\Resources.Designer.cs">
-      <AutoGen>True</AutoGen>
-      <DependentUpon>Resources.resx</DependentUpon>
-    </Compile>
-    <None Include="Properties\Settings.settings">
-      <Generator>SettingsSingleFileGenerator</Generator>
-      <LastGenOutput>Settings.Designer.cs</LastGenOutput>
-    </None>
-    <Compile Include="Properties\Settings.Designer.cs">
-      <AutoGen>True</AutoGen>
-      <DependentUpon>Settings.settings</DependentUpon>
-      <DesignTimeSharedInput>True</DesignTimeSharedInput>
-    </Compile>
-  </ItemGroup>
-  <ItemGroup>
-    <None Include="App.config" />
-  </ItemGroup>
-  <Import Project="$(MSBuildToolsPath)\Microsoft.CSharp.targets" />
-  <!-- To modify your build process, add your task inside one of the targets below and uncomment it. 
-       Other similar extension points exist, see Microsoft.Common.targets.
-  <Target Name="BeforeBuild">
-  </Target>
-  <Target Name="AfterBuild">
-  </Target>
-  -->
-</Project>
\ No newline at end of file
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/ILIScreenshotViewer.sln b/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/ILIScreenshotViewer.sln
deleted file mode 100644
index ec191d30a..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/ILIScreenshotViewer.sln
+++ /dev/null
@@ -1,20 +0,0 @@
-
-Microsoft Visual Studio Solution File, Format Version 12.00
-# Visual Studio 2012
-Project("{FAE04EC0-301F-11D3-BF4B-00C04F79EFBC}") = "ILIScreenshotViewer", "ILIScreenshotViewer.csproj", "{AD6D4A3D-2F94-435B-836F-E617ED847F46}"
-EndProject
-Global
-	GlobalSection(SolutionConfigurationPlatforms) = preSolution
-		Debug|Any CPU = Debug|Any CPU
-		Release|Any CPU = Release|Any CPU
-	EndGlobalSection
-	GlobalSection(ProjectConfigurationPlatforms) = postSolution
-		{AD6D4A3D-2F94-435B-836F-E617ED847F46}.Debug|Any CPU.ActiveCfg = Debug|Any CPU
-		{AD6D4A3D-2F94-435B-836F-E617ED847F46}.Debug|Any CPU.Build.0 = Debug|Any CPU
-		{AD6D4A3D-2F94-435B-836F-E617ED847F46}.Release|Any CPU.ActiveCfg = Release|Any CPU
-		{AD6D4A3D-2F94-435B-836F-E617ED847F46}.Release|Any CPU.Build.0 = Release|Any CPU
-	EndGlobalSection
-	GlobalSection(SolutionProperties) = preSolution
-		HideSolutionNode = FALSE
-	EndGlobalSection
-EndGlobal
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Program.cs b/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Program.cs
deleted file mode 100644
index f2930c0a1..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Program.cs
+++ /dev/null
@@ -1,21 +0,0 @@
-using System;
-using System.Collections.Generic;
-using System.Threading.Tasks;
-using System.Windows.Forms;
-
-namespace ILIScreenshotViewer
-{
-    static class Program
-    {
-        /// <summary>
-        /// The main entry point for the application.
-        /// </summary>
-        [STAThread]
-        static void Main()
-        {
-            Application.EnableVisualStyles();
-            Application.SetCompatibleTextRenderingDefault(false);
-            Application.Run(new Form1());
-        }
-    }
-}
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Properties/AssemblyInfo.cs b/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Properties/AssemblyInfo.cs
deleted file mode 100644
index b9edad9e1..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Properties/AssemblyInfo.cs
+++ /dev/null
@@ -1,36 +0,0 @@
-using System.Reflection;
-using System.Runtime.CompilerServices;
-using System.Runtime.InteropServices;
-
-// General Information about an assembly is controlled through the following 
-// set of attributes. Change these attribute values to modify the information
-// associated with an assembly.
-[assembly: AssemblyTitle("ILIScreenshotViewer")]
-[assembly: AssemblyDescription("")]
-[assembly: AssemblyConfiguration("")]
-[assembly: AssemblyCompany("Microsoft")]
-[assembly: AssemblyProduct("ILIScreenshotViewer")]
-[assembly: AssemblyCopyright("Copyright © Microsoft 2014")]
-[assembly: AssemblyTrademark("")]
-[assembly: AssemblyCulture("")]
-
-// Setting ComVisible to false makes the types in this assembly not visible 
-// to COM components.  If you need to access a type in this assembly from 
-// COM, set the ComVisible attribute to true on that type.
-[assembly: ComVisible(false)]
-
-// The following GUID is for the ID of the typelib if this project is exposed to COM
-[assembly: Guid("bfab4204-5b3c-43c8-b397-d137817de176")]
-
-// Version information for an assembly consists of the following four values:
-//
-//      Major Version
-//      Minor Version 
-//      Build Number
-//      Revision
-//
-// You can specify all the values or you can default the Build and Revision Numbers 
-// by using the '*' as shown below:
-// [assembly: AssemblyVersion("1.0.*")]
-[assembly: AssemblyVersion("1.0.0.0")]
-[assembly: AssemblyFileVersion("1.0.0.0")]
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Properties/Resources.Designer.cs b/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Properties/Resources.Designer.cs
deleted file mode 100644
index de9c11bed..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Properties/Resources.Designer.cs
+++ /dev/null
@@ -1,71 +0,0 @@
-//------------------------------------------------------------------------------
-// <auto-generated>
-//     This code was generated by a tool.
-//     Runtime Version:4.0.30319.18063
-//
-//     Changes to this file may cause incorrect behavior and will be lost if
-//     the code is regenerated.
-// </auto-generated>
-//------------------------------------------------------------------------------
-
-namespace ILIScreenshotViewer.Properties
-{
-
-
-    /// <summary>
-    ///   A strongly-typed resource class, for looking up localized strings, etc.
-    /// </summary>
-    // This class was auto-generated by the StronglyTypedResourceBuilder
-    // class via a tool like ResGen or Visual Studio.
-    // To add or remove a member, edit your .ResX file then rerun ResGen
-    // with the /str option, or rebuild your VS project.
-    [global::System.CodeDom.Compiler.GeneratedCodeAttribute("System.Resources.Tools.StronglyTypedResourceBuilder", "4.0.0.0")]
-    [global::System.Diagnostics.DebuggerNonUserCodeAttribute()]
-    [global::System.Runtime.CompilerServices.CompilerGeneratedAttribute()]
-    internal class Resources
-    {
-
-        private static global::System.Resources.ResourceManager resourceMan;
-
-        private static global::System.Globalization.CultureInfo resourceCulture;
-
-        [global::System.Diagnostics.CodeAnalysis.SuppressMessageAttribute("Microsoft.Performance", "CA1811:AvoidUncalledPrivateCode")]
-        internal Resources()
-        {
-        }
-
-        /// <summary>
-        ///   Returns the cached ResourceManager instance used by this class.
-        /// </summary>
-        [global::System.ComponentModel.EditorBrowsableAttribute(global::System.ComponentModel.EditorBrowsableState.Advanced)]
-        internal static global::System.Resources.ResourceManager ResourceManager
-        {
-            get
-            {
-                if ((resourceMan == null))
-                {
-                    global::System.Resources.ResourceManager temp = new global::System.Resources.ResourceManager("ILIScreenshotViewer.Properties.Resources", typeof(Resources).Assembly);
-                    resourceMan = temp;
-                }
-                return resourceMan;
-            }
-        }
-
-        /// <summary>
-        ///   Overrides the current thread's CurrentUICulture property for all
-        ///   resource lookups using this strongly typed resource class.
-        /// </summary>
-        [global::System.ComponentModel.EditorBrowsableAttribute(global::System.ComponentModel.EditorBrowsableState.Advanced)]
-        internal static global::System.Globalization.CultureInfo Culture
-        {
-            get
-            {
-                return resourceCulture;
-            }
-            set
-            {
-                resourceCulture = value;
-            }
-        }
-    }
-}
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Properties/Resources.resx b/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Properties/Resources.resx
deleted file mode 100644
index af7dbebba..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Properties/Resources.resx
+++ /dev/null
@@ -1,117 +0,0 @@
-<?xml version="1.0" encoding="utf-8"?>
-<root>
-  <!-- 
-    Microsoft ResX Schema 
-    
-    Version 2.0
-    
-    The primary goals of this format is to allow a simple XML format 
-    that is mostly human readable. The generation and parsing of the 
-    various data types are done through the TypeConverter classes 
-    associated with the data types.
-    
-    Example:
-    
-    ... ado.net/XML headers & schema ...
-    <resheader name="resmimetype">text/microsoft-resx</resheader>
-    <resheader name="version">2.0</resheader>
-    <resheader name="reader">System.Resources.ResXResourceReader, System.Windows.Forms, ...</resheader>
-    <resheader name="writer">System.Resources.ResXResourceWriter, System.Windows.Forms, ...</resheader>
-    <data name="Name1"><value>this is my long string</value><comment>this is a comment</comment></data>
-    <data name="Color1" type="System.Drawing.Color, System.Drawing">Blue</data>
-    <data name="Bitmap1" mimetype="application/x-microsoft.net.object.binary.base64">
-        <value>[base64 mime encoded serialized .NET Framework object]</value>
-    </data>
-    <data name="Icon1" type="System.Drawing.Icon, System.Drawing" mimetype="application/x-microsoft.net.object.bytearray.base64">
-        <value>[base64 mime encoded string representing a byte array form of the .NET Framework object]</value>
-        <comment>This is a comment</comment>
-    </data>
-                
-    There are any number of "resheader" rows that contain simple 
-    name/value pairs.
-    
-    Each data row contains a name, and value. The row also contains a 
-    type or mimetype. Type corresponds to a .NET class that support 
-    text/value conversion through the TypeConverter architecture. 
-    Classes that don't support this are serialized and stored with the 
-    mimetype set.
-    
-    The mimetype is used for serialized objects, and tells the 
-    ResXResourceReader how to depersist the object. This is currently not 
-    extensible. For a given mimetype the value must be set accordingly:
-    
-    Note - application/x-microsoft.net.object.binary.base64 is the format 
-    that the ResXResourceWriter will generate, however the reader can 
-    read any of the formats listed below.
-    
-    mimetype: application/x-microsoft.net.object.binary.base64
-    value   : The object must be serialized with 
-            : System.Serialization.Formatters.Binary.BinaryFormatter
-            : and then encoded with base64 encoding.
-    
-    mimetype: application/x-microsoft.net.object.soap.base64
-    value   : The object must be serialized with 
-            : System.Runtime.Serialization.Formatters.Soap.SoapFormatter
-            : and then encoded with base64 encoding.
-
-    mimetype: application/x-microsoft.net.object.bytearray.base64
-    value   : The object must be serialized into a byte array 
-            : using a System.ComponentModel.TypeConverter
-            : and then encoded with base64 encoding.
-    -->
-  <xsd:schema id="root" xmlns="" xmlns:xsd="http://www.w3.org/2001/XMLSchema" xmlns:msdata="urn:schemas-microsoft-com:xml-msdata">
-    <xsd:element name="root" msdata:IsDataSet="true">
-      <xsd:complexType>
-        <xsd:choice maxOccurs="unbounded">
-          <xsd:element name="metadata">
-            <xsd:complexType>
-              <xsd:sequence>
-                <xsd:element name="value" type="xsd:string" minOccurs="0" />
-              </xsd:sequence>
-              <xsd:attribute name="name" type="xsd:string" />
-              <xsd:attribute name="type" type="xsd:string" />
-              <xsd:attribute name="mimetype" type="xsd:string" />
-            </xsd:complexType>
-          </xsd:element>
-          <xsd:element name="assembly">
-            <xsd:complexType>
-              <xsd:attribute name="alias" type="xsd:string" />
-              <xsd:attribute name="name" type="xsd:string" />
-            </xsd:complexType>
-          </xsd:element>
-          <xsd:element name="data">
-            <xsd:complexType>
-              <xsd:sequence>
-                <xsd:element name="value" type="xsd:string" minOccurs="0" msdata:Ordinal="1" />
-                <xsd:element name="comment" type="xsd:string" minOccurs="0" msdata:Ordinal="2" />
-              </xsd:sequence>
-              <xsd:attribute name="name" type="xsd:string" msdata:Ordinal="1" />
-              <xsd:attribute name="type" type="xsd:string" msdata:Ordinal="3" />
-              <xsd:attribute name="mimetype" type="xsd:string" msdata:Ordinal="4" />
-            </xsd:complexType>
-          </xsd:element>
-          <xsd:element name="resheader">
-            <xsd:complexType>
-              <xsd:sequence>
-                <xsd:element name="value" type="xsd:string" minOccurs="0" msdata:Ordinal="1" />
-              </xsd:sequence>
-              <xsd:attribute name="name" type="xsd:string" use="required" />
-            </xsd:complexType>
-          </xsd:element>
-        </xsd:choice>
-      </xsd:complexType>
-    </xsd:element>
-  </xsd:schema>
-  <resheader name="resmimetype">
-    <value>text/microsoft-resx</value>
-  </resheader>
-  <resheader name="version">
-    <value>2.0</value>
-  </resheader>
-  <resheader name="reader">
-    <value>System.Resources.ResXResourceReader, System.Windows.Forms, Version=2.0.0.0, Culture=neutral, PublicKeyToken=b77a5c561934e089</value>
-  </resheader>
-  <resheader name="writer">
-    <value>System.Resources.ResXResourceWriter, System.Windows.Forms, Version=2.0.0.0, Culture=neutral, PublicKeyToken=b77a5c561934e089</value>
-  </resheader>
-</root>
\ No newline at end of file
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Properties/Settings.Designer.cs b/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Properties/Settings.Designer.cs
deleted file mode 100644
index feddeef2d..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Properties/Settings.Designer.cs
+++ /dev/null
@@ -1,30 +0,0 @@
-//------------------------------------------------------------------------------
-// <auto-generated>
-//     This code was generated by a tool.
-//     Runtime Version:4.0.30319.18063
-//
-//     Changes to this file may cause incorrect behavior and will be lost if
-//     the code is regenerated.
-// </auto-generated>
-//------------------------------------------------------------------------------
-
-namespace ILIScreenshotViewer.Properties
-{
-
-
-    [global::System.Runtime.CompilerServices.CompilerGeneratedAttribute()]
-    [global::System.CodeDom.Compiler.GeneratedCodeAttribute("Microsoft.VisualStudio.Editors.SettingsDesigner.SettingsSingleFileGenerator", "11.0.0.0")]
-    internal sealed partial class Settings : global::System.Configuration.ApplicationSettingsBase
-    {
-
-        private static Settings defaultInstance = ((Settings)(global::System.Configuration.ApplicationSettingsBase.Synchronized(new Settings())));
-
-        public static Settings Default
-        {
-            get
-            {
-                return defaultInstance;
-            }
-        }
-    }
-}
diff --git a/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Properties/Settings.settings b/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Properties/Settings.settings
deleted file mode 100644
index 39645652a..000000000
--- a/STM32F1/libraries/ILI9341_due_STM/tools/ILIScreenshotViewer/src/Properties/Settings.settings
+++ /dev/null
@@ -1,7 +0,0 @@
-<?xml version='1.0' encoding='utf-8'?>
-<SettingsFile xmlns="http://schemas.microsoft.com/VisualStudio/2004/01/settings" CurrentProfile="(Default)">
-  <Profiles>
-    <Profile Name="(Default)" />
-  </Profiles>
-  <Settings />
-</SettingsFile>

From 7c9b1cc11ae391be547f191ceb7865a4b3925ffb Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Mon, 26 Dec 2016 20:34:11 +1100
Subject: [PATCH 036/307] Enable SWD pins for all upload types, on all F103
 boards except Maple mini and Maple

---
 STM32F1/boards.txt | 22 +++++++++++++---------
 1 file changed, 13 insertions(+), 9 deletions(-)

diff --git a/STM32F1/boards.txt b/STM32F1/boards.txt
index 95a5f8635..d9c5df511 100644
--- a/STM32F1/boards.txt
+++ b/STM32F1/boards.txt
@@ -190,7 +190,7 @@ genericSTM32F103C.menu.device_variant.STM32F103CB.upload.flash.maximum_size=1310
 genericSTM32F103C.menu.upload_method.DFUUploadMethod=STM32duino bootloader
 genericSTM32F103C.menu.upload_method.DFUUploadMethod.upload.protocol=maple_dfu
 genericSTM32F103C.menu.upload_method.DFUUploadMethod.upload.tool=maple_upload
-genericSTM32F103C.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER
+genericSTM32F103C.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER -DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG=1
 genericSTM32F103C.menu.upload_method.DFUUploadMethod.build.vect=VECT_TAB_ADDR=0x8002000
 genericSTM32F103C.menu.upload_method.DFUUploadMethod.build.ldscript=ld/bootloader_20.ld
 genericSTM32F103C.menu.upload_method.DFUUploadMethod.upload.usbID=1EAF:0003
@@ -199,7 +199,7 @@ genericSTM32F103C.menu.upload_method.DFUUploadMethod.upload.altID=2
 genericSTM32F103C.menu.upload_method.serialMethod=Serial
 genericSTM32F103C.menu.upload_method.serialMethod.upload.protocol=maple_serial
 genericSTM32F103C.menu.upload_method.serialMethod.upload.tool=serial_upload
-
+genericSTM32F103C.menu.upload_method.serialMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG
 
 genericSTM32F103C.menu.upload_method.STLinkMethod=STLink
 genericSTM32F103C.menu.upload_method.STLinkMethod.upload.protocol=STLink
@@ -267,7 +267,7 @@ genericSTM32F103R.menu.device_variant.STM32F103RE.build.ldscript=ld/stm32f103re.
 genericSTM32F103R.menu.upload_method.DFUUploadMethod=STM32duino bootloader
 genericSTM32F103R.menu.upload_method.DFUUploadMethod.upload.protocol=maple_dfu
 genericSTM32F103R.menu.upload_method.DFUUploadMethod.upload.tool=maple_upload
-genericSTM32F103R.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER
+genericSTM32F103R.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER -DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG=1
 genericSTM32F103R.menu.upload_method.DFUUploadMethod.build.vect=VECT_TAB_ADDR=0x8002000
 genericSTM32F103R.menu.upload_method.DFUUploadMethod.build.ldscript=ld/bootloader.ld
 genericSTM32F103R.menu.upload_method.DFUUploadMethod.upload.usbID=1EAF:0003
@@ -276,6 +276,7 @@ genericSTM32F103R.menu.upload_method.DFUUploadMethod.upload.altID=2
 genericSTM32F103R.menu.upload_method.serialMethod=Serial
 genericSTM32F103R.menu.upload_method.serialMethod.upload.protocol=maple_serial
 genericSTM32F103R.menu.upload_method.serialMethod.upload.tool=serial_upload
+genericSTM32F103R.menu.upload_method.serialMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG=1
 
 genericSTM32F103R.menu.upload_method.STLinkMethod=STLink
 genericSTM32F103R.menu.upload_method.STLinkMethod.upload.protocol=STLink
@@ -321,7 +322,7 @@ genericSTM32F103T.menu.device_variant.STM32F103TB.upload.flash.maximum_size=1310
 genericSTM32F103T.menu.upload_method.DFUUploadMethod=STM32duino bootloader
 genericSTM32F103T.menu.upload_method.DFUUploadMethod.upload.protocol=maple_dfu
 genericSTM32F103T.menu.upload_method.DFUUploadMethod.upload.tool=maple_upload
-genericSTM32F103T.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER
+genericSTM32F103T.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER -DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG=1
 genericSTM32F103T.menu.upload_method.DFUUploadMethod.build.vect=VECT_TAB_ADDR=0x8002000
 genericSTM32F103T.menu.upload_method.DFUUploadMethod.build.ldscript=ld/bootloader_20.ld
 genericSTM32F103T.menu.upload_method.DFUUploadMethod.upload.usbID=1EAF:0003
@@ -330,6 +331,7 @@ genericSTM32F103T.menu.upload_method.DFUUploadMethod.upload.altID=2
 genericSTM32F103T.menu.upload_method.serialMethod=Serial
 genericSTM32F103T.menu.upload_method.serialMethod.upload.protocol=maple_serial
 genericSTM32F103T.menu.upload_method.serialMethod.upload.tool=serial_upload
+genericSTM32F103T.menu.upload_method.serialMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG=1
 
 genericSTM32F103T.menu.upload_method.STLinkMethod=STLink
 genericSTM32F103T.menu.upload_method.STLinkMethod.upload.protocol=STLink
@@ -383,7 +385,7 @@ genericSTM32F103V.menu.device_variant.STM32F103VE.build.ldscript=ld/stm32f103ve.
 genericSTM32F103V.menu.upload_method.DFUUploadMethod=STM32duino bootloader
 genericSTM32F103V.menu.upload_method.DFUUploadMethod.upload.protocol=maple_dfu
 genericSTM32F103V.menu.upload_method.DFUUploadMethod.upload.tool=maple_upload
-genericSTM32F103V.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER
+genericSTM32F103V.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER -DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG=1
 genericSTM32F103V.menu.upload_method.DFUUploadMethod.build.vect=VECT_TAB_ADDR=0x8002000
 genericSTM32F103V.menu.upload_method.DFUUploadMethod.build.ldscript=ld/stm32f103veDFU.ld
 genericSTM32F103V.menu.upload_method.DFUUploadMethod.upload.usbID=1EAF:0003
@@ -392,6 +394,7 @@ genericSTM32F103V.menu.upload_method.DFUUploadMethod.upload.altID=2
 genericSTM32F103V.menu.upload_method.serialMethod=Serial
 genericSTM32F103V.menu.upload_method.serialMethod.upload.protocol=maple_serial
 genericSTM32F103V.menu.upload_method.serialMethod.upload.tool=serial_upload
+genericSTM32F103V.menu.upload_method.serialMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG=1
 
 genericSTM32F103V.menu.upload_method.STLinkMethod=STLink
 genericSTM32F103V.menu.upload_method.STLinkMethod.upload.protocol=STLink
@@ -442,7 +445,7 @@ genericSTM32F103Z.menu.device_variant.STM32F103ZE.build.ldscript=ld/stm32f103ze.
 genericSTM32F103Z.menu.upload_method.DFUUploadMethod=STM32duino bootloader
 genericSTM32F103Z.menu.upload_method.DFUUploadMethod.upload.protocol=maple_dfu
 genericSTM32F103Z.menu.upload_method.DFUUploadMethod.upload.tool=maple_upload
-genericSTM32F103Z.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER
+genericSTM32F103Z.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER -DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG=1
 genericSTM32F103Z.menu.upload_method.DFUUploadMethod.build.vect=VECT_TAB_ADDR=0x8002000
 genericSTM32F103Z.menu.upload_method.DFUUploadMethod.build.ldscript=ld/stm32f103z_dfu.ld
 genericSTM32F103Z.menu.upload_method.DFUUploadMethod.upload.usbID=1EAF:0003
@@ -451,6 +454,7 @@ genericSTM32F103Z.menu.upload_method.DFUUploadMethod.upload.altID=2
 genericSTM32F103Z.menu.upload_method.serialMethod=Serial
 genericSTM32F103Z.menu.upload_method.serialMethod.upload.protocol=maple_serial
 genericSTM32F103Z.menu.upload_method.serialMethod.upload.tool=serial_upload
+genericSTM32F103Z.menu.upload_method.serialMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG=1
 
 genericSTM32F103Z.menu.upload_method.STLinkMethod=STLink
 genericSTM32F103Z.menu.upload_method.STLinkMethod.upload.protocol=STLink
@@ -497,7 +501,7 @@ hytiny-stm32f103t.menu.upload_method.DFUUploadMethod.upload.altID=2
 hytiny-stm32f103t.menu.upload_method.serialMethod=Serial
 hytiny-stm32f103t.menu.upload_method.serialMethod.upload.protocol=maple_serial
 hytiny-stm32f103t.menu.upload_method.serialMethod.upload.tool=serial_upload
-
+hytiny-stm32f103t.menu.upload_method.serialMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG=1 
 
 hytiny-stm32f103t.menu.upload_method.STLinkMethod=STLink
 hytiny-stm32f103t.menu.upload_method.STLinkMethod.upload.protocol=STLink
@@ -550,7 +554,7 @@ genericGD32F103C.menu.upload_method.DFUUploadMethod=GD32duino bootloader
 
 genericGD32F103C.menu.upload_method.DFUUploadMethod.upload.protocol=maple_dfu
 genericGD32F103C.menu.upload_method.DFUUploadMethod.upload.tool=maple_upload
-genericGD32F103C.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER
+genericGD32F103C.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER -DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG=1
 genericGD32F103C.menu.upload_method.DFUUploadMethod.build.vect=VECT_TAB_ADDR=0x8002000
 genericGD32F103C.menu.upload_method.DFUUploadMethod.build.ldscript=ld/bootloader_20.ld
 genericGD32F103C.menu.upload_method.DFUUploadMethod.upload.usbID=1EAF:0003
@@ -559,7 +563,7 @@ genericGD32F103C.menu.upload_method.DFUUploadMethod.upload.altID=2
 genericGD32F103C.menu.upload_method.serialMethod=Serial
 genericGD32F103C.menu.upload_method.serialMethod.upload.protocol=maple_serial
 genericGD32F103C.menu.upload_method.serialMethod.upload.tool=serial_upload
-
+genericGD32F103C.menu.upload_method.serialMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG=1
 
 genericGD32F103C.menu.upload_method.STLinkMethod=STLink
 genericGD32F103C.menu.upload_method.STLinkMethod.upload.protocol=STLink

From fb823b6929e4416b0921b4ff6c9ea4fa5a186262 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Mon, 26 Dec 2016 15:26:51 +0100
Subject: [PATCH 037/307] remove unused code & bugfixes

- setDataSize shall first disable the SPI before writing new value
- dmaTransfer adapted for TFT library usage
---
 .gitignore                        |  2 ++
 STM32F1/libraries/SPI/src/SPI.cpp | 21 ++++++++++-----------
 2 files changed, 12 insertions(+), 11 deletions(-)

diff --git a/.gitignore b/.gitignore
index 05bb0a597..1fc5dc8ed 100644
--- a/.gitignore
+++ b/.gitignore
@@ -7,3 +7,5 @@ other/maple-bootloader/build
 other/maple-bootloader/*~
 *.o
 tools/src/stm32flash_serial/src/parsers/parsers.a
+*.bak
+*.1
diff --git a/STM32F1/libraries/SPI/src/SPI.cpp b/STM32F1/libraries/SPI/src/SPI.cpp
index 9b6e28e7d..45ee25ab4 100644
--- a/STM32F1/libraries/SPI/src/SPI.cpp
+++ b/STM32F1/libraries/SPI/src/SPI.cpp
@@ -214,8 +214,10 @@ void SPIClass::setBitOrder(BitOrder bitOrder)
 void SPIClass::setDataSize(uint32 datasize)
 {
 	_currentSetting->dataSize = datasize;
-	uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_DFF); 
-	_currentSetting->spi_d->regs->CR1 = cr1 | (datasize & SPI_CR1_DFF);
+	uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_DFF);
+	uint8 en = spi_is_enabled(_currentSetting->spi_d);
+	spi_peripheral_disable(_currentSetting->spi_d);
+	_currentSetting->spi_d->regs->CR1 = cr1 | (datasize & SPI_CR1_DFF) | en;
 }
 
 void SPIClass::setDataMode(uint8_t dataMode)
@@ -316,12 +318,11 @@ void SPIClass::read(uint8 *buf, uint32 len)
 {
 	spi_reg_map * regs = _currentSetting->spi_d->regs;
 	uint8 b = (regs->DR); // clear the RX buffer in case a byte is waiting on it.
-    uint32 rxed = 0;
 	// start sequence
-    while ( rxed < len) {
+    while ( (len--)>0) {
 		regs->DR = 0x00FF; // " write the data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
         while ( (regs->SR & SPI_SR_RXNE)==0 ) ; // wait till data is available in the Rx register
-        *buf++ = (regs->DR); // read and store the received byte
+        *buf++ = (uint8)(regs->DR); // read and store the received byte
     }
 }
 
@@ -333,6 +334,7 @@ void SPIClass::write(uint16 data)
 	 * This almost doubles the speed of this function.
 	 */
 	spi_tx_reg(_currentSetting->spi_d, data); // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
+	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
 }
 
@@ -387,7 +389,7 @@ uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length
 
 	// RX
 	spi_rx_dma_enable(_currentSetting->spi_d);
-	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_8BIT) ? DMA_SIZE_8BITS : DMA_SIZE_16BITS;
+	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
 	dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
                      receiveBuf, dma_bit_size, (DMA_MINC_MODE | DMA_TRNS_CMPLT));// receive buffer DMA
 	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, length);
@@ -408,7 +410,7 @@ uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length
 	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
 	
     uint32_t m = millis();
-	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & 0x2)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
+	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
 		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
     }
 	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
@@ -434,13 +436,10 @@ uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length, bool minc)
 	if (length == 0) return 0;
 	uint32 flags = ( (DMA_MINC_MODE*minc) | DMA_FROM_MEM | DMA_TRNS_CMPLT);
 	uint8 b = 0;
-//	dma1_ch3_Active=true;
     dma_init(_currentSetting->spiDmaDev);
-//	dma_attach_interrupt(DMA1, DMA_CH3, &SPIClass::DMA1_CH3_Event);
-
 	// TX
 	spi_tx_dma_enable(_currentSetting->spi_d);	
-	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_8BIT) ? DMA_SIZE_8BITS : DMA_SIZE_16BITS;
+	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
     dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
                        transmitBuf, dma_bit_size, flags);// Transmit buffer DMA 
 	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);

From 7dcbbc85b00b23a9ef7ec8692310d90623aeebc1 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Mon, 9 Jan 2017 20:27:07 +1100
Subject: [PATCH 038/307] Fix bug USB divider for 48Mhz operation. Also added
 support for 48Mhz to Maple mini and Generic F103C (Note. There is a bug in
 tone() at 48Mhz)

---
 STM32F1/boards.txt                                | 15 +++++++++++++++
 STM32F1/variants/STM32VLD/wirish/boards_setup.cpp |  2 +-
 .../generic_gd32f103c/wirish/boards_setup.cpp     |  2 +-
 .../generic_stm32f103c/wirish/boards_setup.cpp    |  8 ++++++--
 .../generic_stm32f103r/wirish/boards_setup.cpp    |  8 ++++++--
 .../generic_stm32f103r8/wirish/boards_setup.cpp   |  8 ++++++--
 .../generic_stm32f103t/wirish/boards_setup.cpp    |  8 ++++++--
 .../generic_stm32f103v/wirish/boards_setup.cpp    |  8 ++++++--
 .../generic_stm32f103z/wirish/boards_setup.cpp    |  8 ++++++--
 .../hytiny_stm32f103t/wirish/boards_setup.cpp     |  8 ++++++--
 STM32F1/variants/maple/wirish/boards_setup.cpp    |  8 ++++++--
 .../variants/maple_mini/wirish/boards_setup.cpp   |  8 ++++++--
 .../variants/maple_ret6/wirish/boards_setup.cpp   |  8 ++++++--
 .../variants/microduino/wirish/boards_setup.cpp   |  8 ++++++--
 14 files changed, 83 insertions(+), 24 deletions(-)

diff --git a/STM32F1/boards.txt b/STM32F1/boards.txt
index d9c5df511..24202fc9d 100644
--- a/STM32F1/boards.txt
+++ b/STM32F1/boards.txt
@@ -38,6 +38,14 @@ mapleMini.menu.bootloader_version.bootloader20.upload.flash.maximum_size=122880
 mapleMini.menu.bootloader_version.bootloader20.upload.maximum_size=122880
 mapleMini.menu.bootloader_version.bootloader20.upload.altID=2
 
+#-- CPU Clock frequency
+mapleMini.menu.cpu_speed.speed_72mhz=72Mhz (Normal)
+mapleMini.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
+
+mapleMini.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
+mapleMini.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
+
+
 ##############################################################
 maple.name=Maple (Rev 3)
 
@@ -217,6 +225,13 @@ genericSTM32F103C.menu.upload_method.jlinkMethod.upload.protocol=jlink
 genericSTM32F103C.menu.upload_method.jlinkMethod.upload.tool=jlink_upload
 genericSTM32F103C.menu.upload_method.jlinkMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG=1 -DSERIAL_USB -DGENERIC_BOOTLOADER 
 
+#-- CPU Clock frequency
+genericSTM32F103C.menu.cpu_speed.speed_72mhz=72Mhz (Normal)
+genericSTM32F103C.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
+
+genericSTM32F103C.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
+genericSTM32F103C.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
+
 ########################### Generic STM32F103R ###########################
 
 genericSTM32F103R.name=Generic STM32F103R series
diff --git a/STM32F1/variants/STM32VLD/wirish/boards_setup.cpp b/STM32F1/variants/STM32VLD/wirish/boards_setup.cpp
index 9de4d5396..f6a28c0d1 100644
--- a/STM32F1/variants/STM32VLD/wirish/boards_setup.cpp
+++ b/STM32F1/variants/STM32VLD/wirish/boards_setup.cpp
@@ -71,7 +71,7 @@ namespace wirish {
 			#if F_CPU == 72000000
 			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);
 			#elif F_CPU == 48000000
-			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);			
+			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1);			
 			#endif	
         }
 
diff --git a/STM32F1/variants/generic_gd32f103c/wirish/boards_setup.cpp b/STM32F1/variants/generic_gd32f103c/wirish/boards_setup.cpp
index a5a26be56..3df1fe784 100644
--- a/STM32F1/variants/generic_gd32f103c/wirish/boards_setup.cpp
+++ b/STM32F1/variants/generic_gd32f103c/wirish/boards_setup.cpp
@@ -80,7 +80,7 @@ namespace wirish {
 			#elif F_CPU == 72000000
 			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);
 			#elif F_CPU == 48000000
-			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);			
+			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1);			
 			#endif	
         }
 
diff --git a/STM32F1/variants/generic_stm32f103c/wirish/boards_setup.cpp b/STM32F1/variants/generic_stm32f103c/wirish/boards_setup.cpp
index 1f833afde..551628264 100644
--- a/STM32F1/variants/generic_stm32f103c/wirish/boards_setup.cpp
+++ b/STM32F1/variants/generic_stm32f103c/wirish/boards_setup.cpp
@@ -48,7 +48,11 @@
 // works for F103 performance line MCUs, which is all that LeafLabs
 // currently officially supports).
 #ifndef BOARD_RCC_PLLMUL
-#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+  #if F_CPU==72000000
+	#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+  #elif F_CPU==48000000
+	#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
+  #endif
 #endif
 
 namespace wirish {
@@ -71,7 +75,7 @@ namespace wirish {
 			#if F_CPU == 72000000
 			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);
 			#elif F_CPU == 48000000
-			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);			
+			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1);			
 			#endif			
         }
 
diff --git a/STM32F1/variants/generic_stm32f103r/wirish/boards_setup.cpp b/STM32F1/variants/generic_stm32f103r/wirish/boards_setup.cpp
index 25060bb22..d7774f763 100644
--- a/STM32F1/variants/generic_stm32f103r/wirish/boards_setup.cpp
+++ b/STM32F1/variants/generic_stm32f103r/wirish/boards_setup.cpp
@@ -48,7 +48,11 @@
 // works for F103 performance line MCUs, which is all that LeafLabs
 // currently officially supports).
 #ifndef BOARD_RCC_PLLMUL
-#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+  #if F_CPU==72000000
+	#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+  #elif F_CPU==48000000
+	#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
+  #endif
 #endif
 
 namespace wirish {
@@ -71,7 +75,7 @@ namespace wirish {
 			#if F_CPU == 72000000
 			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);
 			#elif F_CPU == 48000000
-			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);			
+			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1);			
 			#endif	
         }
 
diff --git a/STM32F1/variants/generic_stm32f103r8/wirish/boards_setup.cpp b/STM32F1/variants/generic_stm32f103r8/wirish/boards_setup.cpp
index 9c04e74ce..7c939771e 100644
--- a/STM32F1/variants/generic_stm32f103r8/wirish/boards_setup.cpp
+++ b/STM32F1/variants/generic_stm32f103r8/wirish/boards_setup.cpp
@@ -48,7 +48,11 @@
 // works for F103 performance line MCUs, which is all that LeafLabs
 // currently officially supports).
 #ifndef BOARD_RCC_PLLMUL
-#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+  #if F_CPU==72000000
+	#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+  #elif F_CPU==48000000
+	#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
+  #endif
 #endif
 
 namespace wirish {
@@ -71,7 +75,7 @@ namespace wirish {
 			#if F_CPU == 72000000
 			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);
 			#elif F_CPU == 48000000
-			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);			
+			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1);			
 			#endif	
         }
 
diff --git a/STM32F1/variants/generic_stm32f103t/wirish/boards_setup.cpp b/STM32F1/variants/generic_stm32f103t/wirish/boards_setup.cpp
index 1f833afde..551628264 100644
--- a/STM32F1/variants/generic_stm32f103t/wirish/boards_setup.cpp
+++ b/STM32F1/variants/generic_stm32f103t/wirish/boards_setup.cpp
@@ -48,7 +48,11 @@
 // works for F103 performance line MCUs, which is all that LeafLabs
 // currently officially supports).
 #ifndef BOARD_RCC_PLLMUL
-#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+  #if F_CPU==72000000
+	#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+  #elif F_CPU==48000000
+	#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
+  #endif
 #endif
 
 namespace wirish {
@@ -71,7 +75,7 @@ namespace wirish {
 			#if F_CPU == 72000000
 			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);
 			#elif F_CPU == 48000000
-			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);			
+			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1);			
 			#endif			
         }
 
diff --git a/STM32F1/variants/generic_stm32f103v/wirish/boards_setup.cpp b/STM32F1/variants/generic_stm32f103v/wirish/boards_setup.cpp
index 2f638f427..1f23679ab 100644
--- a/STM32F1/variants/generic_stm32f103v/wirish/boards_setup.cpp
+++ b/STM32F1/variants/generic_stm32f103v/wirish/boards_setup.cpp
@@ -48,7 +48,11 @@
 // works for F103 performance line MCUs, which is all that LeafLabs
 // currently officially supports).
 #ifndef BOARD_RCC_PLLMUL
-#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+  #if F_CPU==72000000
+	#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+  #elif F_CPU==48000000
+	#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
+  #endif
 #endif
 
 namespace wirish {
@@ -71,7 +75,7 @@ namespace wirish {
 			#if F_CPU == 72000000
 			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);
 			#elif F_CPU == 48000000
-			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);			
+			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1);			
 			#endif	
         }
 
diff --git a/STM32F1/variants/generic_stm32f103z/wirish/boards_setup.cpp b/STM32F1/variants/generic_stm32f103z/wirish/boards_setup.cpp
index 78868b20f..e2cfe4ad8 100644
--- a/STM32F1/variants/generic_stm32f103z/wirish/boards_setup.cpp
+++ b/STM32F1/variants/generic_stm32f103z/wirish/boards_setup.cpp
@@ -48,7 +48,11 @@
 // works for F103 performance line MCUs, which is all that LeafLabs
 // currently officially supports).
 #ifndef BOARD_RCC_PLLMUL
-#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+  #if F_CPU==72000000
+	#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+  #elif F_CPU==48000000
+	#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
+  #endif
 #endif
 
 namespace wirish {
@@ -71,7 +75,7 @@ namespace wirish {
 			#if F_CPU == 72000000
 			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);
 			#elif F_CPU == 48000000
-			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);			
+			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1);			
 			#endif	
         }
 
diff --git a/STM32F1/variants/hytiny_stm32f103t/wirish/boards_setup.cpp b/STM32F1/variants/hytiny_stm32f103t/wirish/boards_setup.cpp
index 5d762c7cc..df393473b 100644
--- a/STM32F1/variants/hytiny_stm32f103t/wirish/boards_setup.cpp
+++ b/STM32F1/variants/hytiny_stm32f103t/wirish/boards_setup.cpp
@@ -48,7 +48,11 @@
 // works for F103 performance line MCUs, which is all that LeafLabs
 // currently officially supports).
 #ifndef BOARD_RCC_PLLMUL
-#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+  #if F_CPU==72000000
+	#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+  #elif F_CPU==48000000
+	#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
+  #endif
 #endif
 
 namespace wirish {
@@ -71,7 +75,7 @@ namespace wirish {
 			#if F_CPU == 72000000
 			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);
 			#elif F_CPU == 48000000
-			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);			
+			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1);			
 			#endif				
         }
 
diff --git a/STM32F1/variants/maple/wirish/boards_setup.cpp b/STM32F1/variants/maple/wirish/boards_setup.cpp
index d7b8ef8af..1071d6da5 100644
--- a/STM32F1/variants/maple/wirish/boards_setup.cpp
+++ b/STM32F1/variants/maple/wirish/boards_setup.cpp
@@ -48,7 +48,11 @@
 // works for F103 performance line MCUs, which is all that LeafLabs
 // currently officially supports).
 #ifndef BOARD_RCC_PLLMUL
-#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+  #if F_CPU==72000000
+	#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+  #elif F_CPU==48000000
+	#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
+  #endif
 #endif
 
 namespace wirish {
@@ -71,7 +75,7 @@ namespace wirish {
 			#if F_CPU == 72000000
 			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);
 			#elif F_CPU == 48000000
-			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);			
+			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1);			
 			#endif	
         }
 
diff --git a/STM32F1/variants/maple_mini/wirish/boards_setup.cpp b/STM32F1/variants/maple_mini/wirish/boards_setup.cpp
index 5d762c7cc..df393473b 100644
--- a/STM32F1/variants/maple_mini/wirish/boards_setup.cpp
+++ b/STM32F1/variants/maple_mini/wirish/boards_setup.cpp
@@ -48,7 +48,11 @@
 // works for F103 performance line MCUs, which is all that LeafLabs
 // currently officially supports).
 #ifndef BOARD_RCC_PLLMUL
-#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+  #if F_CPU==72000000
+	#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+  #elif F_CPU==48000000
+	#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
+  #endif
 #endif
 
 namespace wirish {
@@ -71,7 +75,7 @@ namespace wirish {
 			#if F_CPU == 72000000
 			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);
 			#elif F_CPU == 48000000
-			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);			
+			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1);			
 			#endif				
         }
 
diff --git a/STM32F1/variants/maple_ret6/wirish/boards_setup.cpp b/STM32F1/variants/maple_ret6/wirish/boards_setup.cpp
index d7b8ef8af..1071d6da5 100644
--- a/STM32F1/variants/maple_ret6/wirish/boards_setup.cpp
+++ b/STM32F1/variants/maple_ret6/wirish/boards_setup.cpp
@@ -48,7 +48,11 @@
 // works for F103 performance line MCUs, which is all that LeafLabs
 // currently officially supports).
 #ifndef BOARD_RCC_PLLMUL
-#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+  #if F_CPU==72000000
+	#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+  #elif F_CPU==48000000
+	#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
+  #endif
 #endif
 
 namespace wirish {
@@ -71,7 +75,7 @@ namespace wirish {
 			#if F_CPU == 72000000
 			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);
 			#elif F_CPU == 48000000
-			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);			
+			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1);			
 			#endif	
         }
 
diff --git a/STM32F1/variants/microduino/wirish/boards_setup.cpp b/STM32F1/variants/microduino/wirish/boards_setup.cpp
index 6a26b9181..e8998435b 100644
--- a/STM32F1/variants/microduino/wirish/boards_setup.cpp
+++ b/STM32F1/variants/microduino/wirish/boards_setup.cpp
@@ -48,7 +48,11 @@
 // works for F103 performance line MCUs, which is all that LeafLabs
 // currently officially supports).
 #ifndef BOARD_RCC_PLLMUL
-#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+  #if F_CPU==72000000
+	#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+  #elif F_CPU==48000000
+	#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
+  #endif
 #endif
 
 namespace wirish {
@@ -71,7 +75,7 @@ namespace wirish {
 			#if F_CPU == 72000000
 			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);
 			#elif F_CPU == 48000000
-			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1_5);			
+			rcc_set_prescaler(RCC_PRESCALER_USB, RCC_USB_SYSCLK_DIV_1);			
 			#endif	
         }
 

From c2f4aa8566e6d294e544084f286a5b06f070453e Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Mon, 9 Jan 2017 21:17:28 +1100
Subject: [PATCH 039/307] Fixed tone() so it works is F_CPU is not 72Mhz

---
 STM32F1/cores/maple/tone.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/cores/maple/tone.cpp b/STM32F1/cores/maple/tone.cpp
index 26aa67679..965bfddc9 100644
--- a/STM32F1/cores/maple/tone.cpp
+++ b/STM32F1/cores/maple/tone.cpp
@@ -147,7 +147,7 @@ void tone(uint32_t pin, uint32_t freq, uint32_t duration) {
    tone_timer->pause();
 
    if(freq > 0 && duration >0 ){
-      uint32_t count = 18000000/freq;       // timer counts per half wave
+      uint32_t count = (F_CPU/4)/freq;       // timer counts per half wave
       tone_ncount = tone_n = (count>>16)+1; // number of 16-bit count chunk
       tone_tcount = count/tone_ncount;      // size of count chunk
       if(duration > 0) // number of half waves to be generated

From 8cfa60ff8419183b8ff0b7125bc43a412d673f30 Mon Sep 17 00:00:00 2001
From: "Romero B. de S. Malaquias" <romero.malaquias@gmail.com>
Date: Mon, 16 Jan 2017 03:55:16 -0200
Subject: [PATCH 040/307] Avoiding conditional directives that break statements

---
 STM32F3/cores/maple/libmaple/stm32f3/f3_adc.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/STM32F3/cores/maple/libmaple/stm32f3/f3_adc.c b/STM32F3/cores/maple/libmaple/stm32f3/f3_adc.c
index 79fcd515b..982d6ea44 100644
--- a/STM32F3/cores/maple/libmaple/stm32f3/f3_adc.c
+++ b/STM32F3/cores/maple/libmaple/stm32f3/f3_adc.c
@@ -301,11 +301,11 @@ void adc_config_gpio(const adc_dev *ignored, gpio_dev *gdev, uint8 bit) {
 }
 
 void adc_enable_single_swstart(const adc_dev *dev) {
+    int check_dev_adc = dev == ADC1;
 #if STM32_F3_LINE == STM32_F3_LINE_303
-		if ( (dev == ADC1) || (dev == ADC3) )
-#else
-		if (dev == ADC1)
+		check_dev_adc = (check_dev_adc || dev == ADC3);
 #endif
+		if (check_dev_adc)
 			adc_init(dev); /* FIXME hack needed for wirish, as master and slave ADC share the same reset register */
     adc_set_exttrig(dev, ADC_EXTTRIG_MODE_SOFTWARE);
 		adc_regulator_enable(dev);

From 7c320774b1477acec19acd330264d6303de4d67a Mon Sep 17 00:00:00 2001
From: Josh Stewart <josh@noisymime.org>
Date: Wed, 8 Feb 2017 15:17:58 +1100
Subject: [PATCH 041/307] Add EEPROM.update() function

---
 STM32F1/libraries/EEPROM/EEPROM.cpp | 22 ++++++++++++++++++++++
 STM32F1/libraries/EEPROM/EEPROM.h   |  2 ++
 2 files changed, 24 insertions(+)

diff --git a/STM32F1/libraries/EEPROM/EEPROM.cpp b/STM32F1/libraries/EEPROM/EEPROM.cpp
index 2cfd64866..289a93ad8 100644
--- a/STM32F1/libraries/EEPROM/EEPROM.cpp
+++ b/STM32F1/libraries/EEPROM/EEPROM.cpp
@@ -521,6 +521,28 @@ uint16 EEPROMClass::write(uint16 Address, uint16 Data)
 	return status;
 }
 
+/**
+  * @brief  Writes/upadtes variable data in EEPROM.
+            The value is written only if differs from the one already saved at the same address.
+  * @param  VirtAddress: Variable virtual address
+  * @param  Data: 16 bit data to be written
+  * @retval Success or error status:
+  *			- EEPROM_SAME_VALUE: If new Data matches existing EEPROM Data
+  *			- FLASH_COMPLETE: on success
+  *			- EEPROM_BAD_ADDRESS: if address = 0xFFFF
+  *			- EEPROM_PAGE_FULL: if valid page is full
+  *			- EEPROM_NO_VALID_PAGE: if no valid page was found
+  *			- EEPROM_OUT_SIZE: if no empty EEPROM variables
+  *			- Flash error code: on write Flash error
+  */
+uint16 EEPROMClass::update(uint16 Address, uint16 Data)
+{
+	if (read(Address) == Data)
+		return EEPROM_SAME_VALUE;
+	else
+	    return write(Address, Data);
+}
+
 /**
   * @brief  Return number of variable
   * @retval Number of variables
diff --git a/STM32F1/libraries/EEPROM/EEPROM.h b/STM32F1/libraries/EEPROM/EEPROM.h
index 8a8320b6b..29574767d 100644
--- a/STM32F1/libraries/EEPROM/EEPROM.h
+++ b/STM32F1/libraries/EEPROM/EEPROM.h
@@ -47,6 +47,7 @@ enum : uint16
 	EEPROM_BAD_ADDRESS		= ((uint16)0x0082),
 	EEPROM_BAD_FLASH		= ((uint16)0x0083),
 	EEPROM_NOT_INIT			= ((uint16)0x0084),
+	EEPROM_SAME_VALUE		= ((uint16)0x0085),
 	EEPROM_NO_VALID_PAGE	= ((uint16)0x00AB)
 	};
 
@@ -67,6 +68,7 @@ class EEPROMClass
 	uint16 read (uint16 address);
 	uint16 read (uint16 address, uint16 *data);
 	uint16 write(uint16 address, uint16 data);
+	uint16 update(uint16 address, uint16 data);
 	uint16 count(uint16 *);
 	uint16 maxcount(void);
 

From a8d1c1d1b614a5ed6924df3facc72a5f9980e34d Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sun, 26 Feb 2017 13:26:24 +1100
Subject: [PATCH 042/307] Disabled SWD pins for all boards when using DFU
 (bootloader) upload method

---
 STM32F1/boards.txt | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/STM32F1/boards.txt b/STM32F1/boards.txt
index 24202fc9d..d5c4ec9bf 100644
--- a/STM32F1/boards.txt
+++ b/STM32F1/boards.txt
@@ -198,7 +198,7 @@ genericSTM32F103C.menu.device_variant.STM32F103CB.upload.flash.maximum_size=1310
 genericSTM32F103C.menu.upload_method.DFUUploadMethod=STM32duino bootloader
 genericSTM32F103C.menu.upload_method.DFUUploadMethod.upload.protocol=maple_dfu
 genericSTM32F103C.menu.upload_method.DFUUploadMethod.upload.tool=maple_upload
-genericSTM32F103C.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER -DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG=1
+genericSTM32F103C.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER
 genericSTM32F103C.menu.upload_method.DFUUploadMethod.build.vect=VECT_TAB_ADDR=0x8002000
 genericSTM32F103C.menu.upload_method.DFUUploadMethod.build.ldscript=ld/bootloader_20.ld
 genericSTM32F103C.menu.upload_method.DFUUploadMethod.upload.usbID=1EAF:0003
@@ -282,7 +282,7 @@ genericSTM32F103R.menu.device_variant.STM32F103RE.build.ldscript=ld/stm32f103re.
 genericSTM32F103R.menu.upload_method.DFUUploadMethod=STM32duino bootloader
 genericSTM32F103R.menu.upload_method.DFUUploadMethod.upload.protocol=maple_dfu
 genericSTM32F103R.menu.upload_method.DFUUploadMethod.upload.tool=maple_upload
-genericSTM32F103R.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER -DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG=1
+genericSTM32F103R.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER 
 genericSTM32F103R.menu.upload_method.DFUUploadMethod.build.vect=VECT_TAB_ADDR=0x8002000
 genericSTM32F103R.menu.upload_method.DFUUploadMethod.build.ldscript=ld/bootloader.ld
 genericSTM32F103R.menu.upload_method.DFUUploadMethod.upload.usbID=1EAF:0003
@@ -337,7 +337,7 @@ genericSTM32F103T.menu.device_variant.STM32F103TB.upload.flash.maximum_size=1310
 genericSTM32F103T.menu.upload_method.DFUUploadMethod=STM32duino bootloader
 genericSTM32F103T.menu.upload_method.DFUUploadMethod.upload.protocol=maple_dfu
 genericSTM32F103T.menu.upload_method.DFUUploadMethod.upload.tool=maple_upload
-genericSTM32F103T.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER -DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG=1
+genericSTM32F103T.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER 
 genericSTM32F103T.menu.upload_method.DFUUploadMethod.build.vect=VECT_TAB_ADDR=0x8002000
 genericSTM32F103T.menu.upload_method.DFUUploadMethod.build.ldscript=ld/bootloader_20.ld
 genericSTM32F103T.menu.upload_method.DFUUploadMethod.upload.usbID=1EAF:0003
@@ -400,7 +400,7 @@ genericSTM32F103V.menu.device_variant.STM32F103VE.build.ldscript=ld/stm32f103ve.
 genericSTM32F103V.menu.upload_method.DFUUploadMethod=STM32duino bootloader
 genericSTM32F103V.menu.upload_method.DFUUploadMethod.upload.protocol=maple_dfu
 genericSTM32F103V.menu.upload_method.DFUUploadMethod.upload.tool=maple_upload
-genericSTM32F103V.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER -DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG=1
+genericSTM32F103V.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER 
 genericSTM32F103V.menu.upload_method.DFUUploadMethod.build.vect=VECT_TAB_ADDR=0x8002000
 genericSTM32F103V.menu.upload_method.DFUUploadMethod.build.ldscript=ld/stm32f103veDFU.ld
 genericSTM32F103V.menu.upload_method.DFUUploadMethod.upload.usbID=1EAF:0003
@@ -460,7 +460,7 @@ genericSTM32F103Z.menu.device_variant.STM32F103ZE.build.ldscript=ld/stm32f103ze.
 genericSTM32F103Z.menu.upload_method.DFUUploadMethod=STM32duino bootloader
 genericSTM32F103Z.menu.upload_method.DFUUploadMethod.upload.protocol=maple_dfu
 genericSTM32F103Z.menu.upload_method.DFUUploadMethod.upload.tool=maple_upload
-genericSTM32F103Z.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER -DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG=1
+genericSTM32F103Z.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER 
 genericSTM32F103Z.menu.upload_method.DFUUploadMethod.build.vect=VECT_TAB_ADDR=0x8002000
 genericSTM32F103Z.menu.upload_method.DFUUploadMethod.build.ldscript=ld/stm32f103z_dfu.ld
 genericSTM32F103Z.menu.upload_method.DFUUploadMethod.upload.usbID=1EAF:0003
@@ -569,7 +569,7 @@ genericGD32F103C.menu.upload_method.DFUUploadMethod=GD32duino bootloader
 
 genericGD32F103C.menu.upload_method.DFUUploadMethod.upload.protocol=maple_dfu
 genericGD32F103C.menu.upload_method.DFUUploadMethod.upload.tool=maple_upload
-genericGD32F103C.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER -DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG=1
+genericGD32F103C.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER 
 genericGD32F103C.menu.upload_method.DFUUploadMethod.build.vect=VECT_TAB_ADDR=0x8002000
 genericGD32F103C.menu.upload_method.DFUUploadMethod.build.ldscript=ld/bootloader_20.ld
 genericGD32F103C.menu.upload_method.DFUUploadMethod.upload.usbID=1EAF:0003

From 9b759c87f8635bf8f6551cafcadfcb5944396821 Mon Sep 17 00:00:00 2001
From: Floris Lambrechts <florisla@gmail.com>
Date: Wed, 22 Mar 2017 13:55:27 +0100
Subject: [PATCH 043/307] Fix F103T compilation error: remove const

Method adc_default_config still had the adc_dev* 'const' for F103T, but this doesn't compile.

For other boards, the 'const' was removed already.  See for example commits 0b34af3b6a29c2ea40a0005fde57f67f75829378 and
2cdbbc83390b27570c9040fc92bda6e63947f160.

Tested on Arduino IDE 1.6.13.

Compilation error message was along these lines:
STM32F1\variants\generic_stm32f103t\wirish\boards.cpp:183:34: error: invalid conversion from 'const adc_dev*' to 'adc_dev*' [-fpermissive]
STM32F1\system/libmaple/include/libmaple/adc.h:306:13: error:   initializing argument 1 of 'void adc_enable_single_swstart(adc_dev*)' [-fpermissive]
STM32F1\variants\generic_stm32f103t\wirish\boards.cpp:184:53: error: invalid conversion from 'const adc_dev*' to 'adc_dev*' [-fpermissive]
STM32F1\system/libmaple/include/libmaple/adc.h:268:6: error:   initializing argument 1 of 'void adc_set_sample_rate(adc_dev*, adc_smp_rate)' [-fpermissive]
STM32F1\variants\generic_stm32f103t\wirish\boards.cpp: In function 'void setup_adcs()':
STM32F1\variants\generic_stm32f103t\wirish\boards.cpp:189:35: error: invalid conversion from 'void (*)(const adc_dev*)' to 'void (*)(adc_dev*)' [-fpermissive]
STM32F1\system/libmaple/include/libmaple/adc.h:282:13: error:   initializing argument 1 of 'void adc_foreach(void (*)(adc_dev*))' [-fpermissive]
---
 STM32F1/variants/generic_stm32f103t/wirish/boards.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/variants/generic_stm32f103t/wirish/boards.cpp b/STM32F1/variants/generic_stm32f103t/wirish/boards.cpp
index 0c018e885..5274e7a93 100644
--- a/STM32F1/variants/generic_stm32f103t/wirish/boards.cpp
+++ b/STM32F1/variants/generic_stm32f103t/wirish/boards.cpp
@@ -179,7 +179,7 @@ nvic_init((uint32)VECT_TAB_ADDR, 0);
 */
 }
 
-static void adc_default_config(const adc_dev *dev) {
+static void adc_default_config(adc_dev *dev) {
     adc_enable_single_swstart(dev);
     adc_set_sample_rate(dev, wirish::priv::w_adc_smp);
 }

From ea81f36fa526f17bf7069474720caa001382b898 Mon Sep 17 00:00:00 2001
From: victorpv <victor_pv@hotmail.com>
Date: Sat, 25 Mar 2017 08:31:44 -0500
Subject: [PATCH 044/307] FreeRTOS900

---
 .../FreeRTOS900/MapleFreeRTOS900.cpp          |   44 +
 .../libraries/FreeRTOS900/MapleFreeRTOS900.h  |   40 +
 .../examples/rtos_blink/rtos_blink.ino        |   31 +
 .../rtos_display_blink/rtos_display_blink.ino |  212 +
 .../libraries/FreeRTOS900/utility/FreeRTOS.h  | 1063 ++++
 .../FreeRTOS900/utility/FreeRTOSConfig.h      |  144 +
 .../FreeRTOS900/utility/MemMang/heap_1.c      |  174 +
 .../FreeRTOS900/utility/MemMang/heap_2.c      |  303 ++
 .../FreeRTOS900/utility/MemMang/heap_3.c      |  135 +
 .../FreeRTOS900/utility/MemMang/heap_4.c      |  474 ++
 .../FreeRTOS900/utility/MemMang/heap_5.c      |  523 ++
 .../FreeRTOS900/utility/StackMacros.h         |  171 +
 .../libraries/FreeRTOS900/utility/croutine.c  |  395 ++
 .../libraries/FreeRTOS900/utility/croutine.h  |  762 +++
 .../utility/deprecated_definitions.h          |  321 ++
 .../FreeRTOS900/utility/event_groups.c        |  752 +++
 .../FreeRTOS900/utility/event_groups.h        |  797 +++
 .../libraries/FreeRTOS900/utility/heap_1.c    |  174 +
 STM32F1/libraries/FreeRTOS900/utility/list.c  |  240 +
 STM32F1/libraries/FreeRTOS900/utility/list.h  |  453 ++
 .../FreeRTOS900/utility/mpu_prototypes.h      |  177 +
 .../FreeRTOS900/utility/mpu_wrappers.h        |  201 +
 STM32F1/libraries/FreeRTOS900/utility/port.c  |  717 +++
 .../libraries/FreeRTOS900/utility/portable.h  |  207 +
 .../libraries/FreeRTOS900/utility/portmacro.h |  284 +
 .../libraries/FreeRTOS900/utility/projdefs.h  |  161 +
 STM32F1/libraries/FreeRTOS900/utility/queue.c | 2566 +++++++++
 STM32F1/libraries/FreeRTOS900/utility/queue.h | 1798 ++++++
 .../libraries/FreeRTOS900/utility/readme.txt  |   17 +
 .../libraries/FreeRTOS900/utility/semphr.h    | 1171 ++++
 .../FreeRTOS900/utility/stdint.readme         |   27 +
 STM32F1/libraries/FreeRTOS900/utility/task.h  | 2267 ++++++++
 STM32F1/libraries/FreeRTOS900/utility/tasks.c | 4807 +++++++++++++++++
 .../libraries/FreeRTOS900/utility/timers.c    | 1092 ++++
 .../libraries/FreeRTOS900/utility/timers.h    | 1314 +++++
 35 files changed, 24014 insertions(+)
 create mode 100644 STM32F1/libraries/FreeRTOS900/MapleFreeRTOS900.cpp
 create mode 100644 STM32F1/libraries/FreeRTOS900/MapleFreeRTOS900.h
 create mode 100644 STM32F1/libraries/FreeRTOS900/examples/rtos_blink/rtos_blink.ino
 create mode 100644 STM32F1/libraries/FreeRTOS900/examples/rtos_display_blink/rtos_display_blink.ino
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/FreeRTOS.h
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/FreeRTOSConfig.h
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/MemMang/heap_1.c
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/MemMang/heap_2.c
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/MemMang/heap_3.c
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/MemMang/heap_4.c
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/MemMang/heap_5.c
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/StackMacros.h
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/croutine.c
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/croutine.h
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/deprecated_definitions.h
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/event_groups.c
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/event_groups.h
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/heap_1.c
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/list.c
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/list.h
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/mpu_prototypes.h
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/mpu_wrappers.h
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/port.c
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/portable.h
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/portmacro.h
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/projdefs.h
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/queue.c
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/queue.h
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/readme.txt
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/semphr.h
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/stdint.readme
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/task.h
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/tasks.c
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/timers.c
 create mode 100644 STM32F1/libraries/FreeRTOS900/utility/timers.h

diff --git a/STM32F1/libraries/FreeRTOS900/MapleFreeRTOS900.cpp b/STM32F1/libraries/FreeRTOS900/MapleFreeRTOS900.cpp
new file mode 100644
index 000000000..43fc2f1be
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/MapleFreeRTOS900.cpp
@@ -0,0 +1,44 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+#include "MapleFreeRTOS900.h"
+
+extern "C" {
+
+void vApplicationStackOverflowHook(xTaskHandle *pxTask,
+                                   signed char *pcTaskName) {
+    /* This function will get called if a task overflows its stack.
+     * If the parameters are corrupt then inspect pxCurrentTCB to find
+     * which was the offending task. */
+
+    (void) pxTask;
+    (void) pcTaskName;
+
+    while (1)
+        ;
+}
+
+}
diff --git a/STM32F1/libraries/FreeRTOS900/MapleFreeRTOS900.h b/STM32F1/libraries/FreeRTOS900/MapleFreeRTOS900.h
new file mode 100644
index 000000000..4cbbb962f
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/MapleFreeRTOS900.h
@@ -0,0 +1,40 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+#ifndef __MAPLE_FREERTOS_H__
+#define __MAPLE_FREERTOS_H__
+
+#include <wirish.h>
+
+extern "C" {
+#define GCC_ARMCM3
+#include "utility/FreeRTOS.h"
+#include "utility/task.h"
+#include "utility/queue.h"
+#include "utility/semphr.h"
+}
+
+#endif
diff --git a/STM32F1/libraries/FreeRTOS900/examples/rtos_blink/rtos_blink.ino b/STM32F1/libraries/FreeRTOS900/examples/rtos_blink/rtos_blink.ino
new file mode 100644
index 000000000..a972b6c18
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/examples/rtos_blink/rtos_blink.ino
@@ -0,0 +1,31 @@
+//#include <wirish/wirish.h>
+//#include "libraries/FreeRTOS/MapleFreeRTOS.h"
+#include <MapleFreeRTOS821.h>
+
+static void vLEDFlashTask(void *pvParameters) {
+    for (;;) {
+        vTaskDelay(1000);
+        digitalWrite(BOARD_LED_PIN, HIGH);
+        vTaskDelay(50);
+        digitalWrite(BOARD_LED_PIN, LOW);
+    }
+}
+
+void setup() {
+    // initialize the digital pin as an output:
+    pinMode(BOARD_LED_PIN, OUTPUT);
+
+    xTaskCreate(vLEDFlashTask,
+                "Task1",
+                configMINIMAL_STACK_SIZE,
+                NULL,
+                tskIDLE_PRIORITY + 2,
+                NULL);
+    vTaskStartScheduler();
+}
+
+void loop() {
+    // Insert background code here
+}
+
+
diff --git a/STM32F1/libraries/FreeRTOS900/examples/rtos_display_blink/rtos_display_blink.ino b/STM32F1/libraries/FreeRTOS900/examples/rtos_display_blink/rtos_display_blink.ino
new file mode 100644
index 000000000..bd6c3e4e0
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/examples/rtos_display_blink/rtos_display_blink.ino
@@ -0,0 +1,212 @@
+#define USE_SEMAPHORE_DMA1
+#include <MapleFreeRTOS821.h>
+#include <SPI.h>
+#include <Adafruit_GFX.h>
+#include <TFT_ILI9163C.h>
+
+#define __CS 8
+#define __RST 9
+#define __DC 10
+
+TFT_ILI9163C tft = TFT_ILI9163C(__CS, __DC, __RST);
+
+xSemaphoreHandle xDisplayFree;
+
+
+const float sin_d[] = {
+  0, 0.17, 0.34, 0.5, 0.64, 0.77, 0.87, 0.94, 0.98, 1, 0.98, 0.94,
+  0.87, 0.77, 0.64, 0.5, 0.34, 0.17, 0, -0.17, -0.34, -0.5, -0.64,
+  -0.77, -0.87, -0.94, -0.98, -1, -0.98, -0.94, -0.87, -0.77,
+  -0.64, -0.5, -0.34, -0.17
+};
+const float cos_d[] = {
+  1, 0.98, 0.94, 0.87, 0.77, 0.64, 0.5, 0.34, 0.17, 0, -0.17, -0.34,
+  -0.5, -0.64, -0.77, -0.87, -0.94, -0.98, -1, -0.98, -0.94, -0.87,
+  -0.77, -0.64, -0.5, -0.34, -0.17, 0, 0.17, 0.34, 0.5, 0.64, 0.77,
+  0.87, 0.94, 0.98
+};
+const float d = 5;
+float cube1_px[] = {
+  -d,  d,  d, -d, -d,  d,  d, -d
+};
+float cube1_py[] = {
+  -d, -d,  d,  d, -d, -d,  d,  d
+};
+float cube1_pz[] = {
+  -d, -d, -d, -d,  d,  d,  d,  d
+};
+
+float cube1_p2x[] = {
+  0, 0, 0, 0, 0, 0, 0, 0
+};
+float cube1_p2y[] = {
+  0, 0, 0, 0, 0, 0, 0, 0
+};
+
+int cube1_r[] = {
+  0, 0, 0
+};
+const float d2 = 10;
+float cube2_px[] = {
+  -d2,  d2,  d2, -d2, -d2,  d2,  d2, -d2
+};
+float cube2_py[] = {
+  -d2, -d2,  d2,  d2, -d2, -d2,  d2,  d2
+};
+float cube2_pz[] = {
+  -d2, -d2, -d2, -d2,  d2,  d2,  d2,  d2
+};
+
+float cube2_p2x[] = {
+  0, 0, 0, 0, 0, 0, 0, 0
+};
+float cube2_p2y[] = {
+  0, 0, 0, 0, 0, 0, 0, 0
+};
+
+int cube2_r[] = {
+  0, 0, 0
+};
+
+uint16 cube1_x, cube1_y, cube2_x, cube2_y, cube1_color, cube2_color;
+
+static void vLEDFlashTask(void *pvParameters) {
+  for (;;) {
+    vTaskDelay(1000);
+    digitalWrite(BOARD_LED_PIN, HIGH);
+    vTaskDelay(50);
+    digitalWrite(BOARD_LED_PIN, LOW);
+  }
+}
+
+static void vCube1LoopTask(void *pvParameters) {
+  while (1) {
+    if ( xSemaphoreTake( xDisplayFree, ( portTickType ) 10 ) == pdTRUE )
+    {
+      cube(cube1_px, cube1_py, cube1_pz, cube1_p2x, cube1_p2y, cube1_r, &cube1_x, &cube1_y, &cube1_color);
+      xSemaphoreGive( xDisplayFree );
+        vTaskDelay(15);
+    }
+  }
+}
+
+static void vCube2LoopTask(void *pvParameters) {
+  while (1) {
+    if ( xSemaphoreTake( xDisplayFree, ( portTickType ) 10 ) == pdTRUE )
+    {
+      cube(cube2_px, cube2_py, cube2_pz, cube2_p2x, cube2_p2y, cube2_r, &cube2_x, &cube2_y, &cube2_color);
+      xSemaphoreGive( xDisplayFree );
+        vTaskDelay(40);
+    }
+  }
+}
+
+
+void cube(float *px, float *py, float *pz, float *p2x, float *p2y, int *r, uint16 *x, uint16 *y, uint16 *color) {
+
+  for (int i = 0; i < 3; i++) {
+    tft.drawLine(p2x[i], p2y[i], p2x[i + 1], p2y[i + 1], WHITE);
+    tft.drawLine(p2x[i + 4], p2y[i + 4], p2x[i + 5], p2y[i + 5], WHITE);
+    tft.drawLine(p2x[i], p2y[i], p2x[i + 4], p2y[i + 4], WHITE);
+  }
+  tft.drawLine(p2x[3], p2y[3], p2x[0], p2y[0], WHITE);
+  tft.drawLine(p2x[7], p2y[7], p2x[4], p2y[4], WHITE);
+  tft.drawLine(p2x[3], p2y[3], p2x[7], p2y[7], WHITE);
+
+  r[0] = r[0] + 1;
+  r[1] = r[1] + 1;
+  if (r[0] == 36) r[0] = 0;
+  if (r[1] == 36) r[1] = 0;
+  if (r[2] == 36) r[2] = 0;
+  for (int i = 0; i < 8; i++)
+  {
+    float px2 = px[i];
+    float py2 = cos_d[r[0]] * py[i] - sin_d[r[0]] * pz[i];
+    float pz2 = sin_d[r[0]] * py[i] + cos_d[r[0]] * pz[i];
+
+    float px3 = cos_d[r[1]] * px2 + sin_d[r[1]] * pz2;
+    float py3 = py2;
+    float pz3 = -sin_d[r[1]] * px2 + cos_d[r[1]] * pz2;
+
+    float ax = cos_d[r[2]] * px3 - sin_d[r[2]] * py3;
+    float ay = sin_d[r[2]] * px3 + cos_d[r[2]] * py3;
+    float az = pz3 - 190;
+
+    p2x[i] = *x + ax * 500 / az;
+    p2y[i] = *y + ay * 500 / az;
+  }
+
+  for (int i = 0; i < 3; i++) {
+    tft.drawLine(p2x[i], p2y[i], p2x[i + 1], p2y[i + 1], *color);
+    tft.drawLine(p2x[i + 4], p2y[i + 4], p2x[i + 5], p2y[i + 5], *color);
+    tft.drawLine(p2x[i], p2y[i], p2x[i + 4], p2y[i + 4], *color);
+  }
+  tft.drawLine(p2x[3], p2y[3], p2x[0], p2y[0], *color);
+  tft.drawLine(p2x[7], p2y[7], p2x[4], p2y[4], *color);
+  tft.drawLine(p2x[3], p2y[3], p2x[7], p2y[7], *color);
+}
+
+static void vSqrtTask(void *pvParameters) {
+  while (1){
+  Serial.println ("Starting Sqrt calculations...");
+  uint16 x = 0;
+  uint16 ixx[1001];
+  // Library Sqrt
+  uint32_t t0 = millis();
+  for (uint32_t n = 247583650 ; n > 247400000 ; n--) {
+    x = sqrt (n);
+  }
+  uint32_t t1 = millis() - t0;
+  Serial.print ("Sqrt calculations took (ms): ");
+  Serial.println (t1);
+  delay (5000);
+  }
+}
+
+void setup() {
+  // initialize the digital pin as an output:
+  Serial.begin(9600);
+  delay (5000);
+  Serial.println ("Running...");
+  pinMode(BOARD_LED_PIN, OUTPUT);
+  tft.begin();
+  tft.fillScreen(WHITE);
+  cube1_x = ((tft.width()) / 4);
+  cube1_y = ((tft.height()) / 4);
+  cube2_x = ((tft.width()) / 2);
+  cube2_y = ((tft.height()) / 2);
+  cube1_color = BLACK;
+  cube2_color = RED;
+  vSemaphoreCreateBinary(xDisplayFree);
+  xTaskCreate(vLEDFlashTask,
+              "Task1",
+              configMINIMAL_STACK_SIZE,
+              NULL,
+              tskIDLE_PRIORITY + 2,
+              NULL);
+  xTaskCreate(vCube1LoopTask,
+              "Cube1",
+              configMINIMAL_STACK_SIZE,
+              NULL,
+              tskIDLE_PRIORITY + 2,
+              NULL);
+  xTaskCreate(vCube2LoopTask,
+              "Cube2",
+              configMINIMAL_STACK_SIZE,
+              NULL,
+              tskIDLE_PRIORITY+1,
+              NULL);
+  xTaskCreate(vSqrtTask,
+              "Sqrt",
+              configMINIMAL_STACK_SIZE,
+              NULL,
+              tskIDLE_PRIORITY,
+              NULL);
+  vTaskStartScheduler();
+}
+
+void loop() {
+  // Do not write any code here, it would not execute.
+}
+
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/FreeRTOS.h b/STM32F1/libraries/FreeRTOS900/utility/FreeRTOS.h
new file mode 100644
index 000000000..f81172dbe
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/FreeRTOS.h
@@ -0,0 +1,1063 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#ifndef INC_FREERTOS_H
+#define INC_FREERTOS_H
+
+/*
+ * Include the generic headers required for the FreeRTOS port being used.
+ */
+#include <stddef.h>
+
+/*
+ * If stdint.h cannot be located then:
+ *   + If using GCC ensure the -nostdint options is *not* being used.
+ *   + Ensure the project's include path includes the directory in which your
+ *     compiler stores stdint.h.
+ *   + Set any compiler options necessary for it to support C99, as technically
+ *     stdint.h is only mandatory with C99 (FreeRTOS does not require C99 in any
+ *     other way).
+ *   + The FreeRTOS download includes a simple stdint.h definition that can be
+ *     used in cases where none is provided by the compiler.  The files only
+ *     contains the typedefs required to build FreeRTOS.  Read the instructions
+ *     in FreeRTOS/source/stdint.readme for more information.
+ */
+#include <stdint.h> /* READ COMMENT ABOVE. */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Application specific configuration options. */
+#include "FreeRTOSConfig.h"
+
+/* Basic FreeRTOS definitions. */
+#include "projdefs.h"
+
+/* Definitions specific to the port being used. */
+#include "portable.h"
+
+/* Must be defaulted before configUSE_NEWLIB_REENTRANT is used below. */
+#ifndef configUSE_NEWLIB_REENTRANT
+	#define configUSE_NEWLIB_REENTRANT 0
+#endif
+
+/* Required if struct _reent is used. */
+#if ( configUSE_NEWLIB_REENTRANT == 1 )
+	#include <reent.h>
+#endif
+/*
+ * Check all the required application specific macros have been defined.
+ * These macros are application specific and (as downloaded) are defined
+ * within FreeRTOSConfig.h.
+ */
+
+#ifndef configMINIMAL_STACK_SIZE
+	#error Missing definition:  configMINIMAL_STACK_SIZE must be defined in FreeRTOSConfig.h.  configMINIMAL_STACK_SIZE defines the size (in words) of the stack allocated to the idle task.  Refer to the demo project provided for your port for a suitable value.
+#endif
+
+#ifndef configMAX_PRIORITIES
+	#error Missing definition:  configMAX_PRIORITIES must be defined in FreeRTOSConfig.h.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_PREEMPTION
+	#error Missing definition:  configUSE_PREEMPTION must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_IDLE_HOOK
+	#error Missing definition:  configUSE_IDLE_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_TICK_HOOK
+	#error Missing definition:  configUSE_TICK_HOOK must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configUSE_16_BIT_TICKS
+	#error Missing definition:  configUSE_16_BIT_TICKS must be defined in FreeRTOSConfig.h as either 1 or 0.  See the Configuration section of the FreeRTOS API documentation for details.
+#endif
+
+#ifndef configMAX_PRIORITIES
+	#error configMAX_PRIORITIES must be defined to be greater than or equal to 1.
+#endif
+
+#ifndef configUSE_CO_ROUTINES
+	#define configUSE_CO_ROUTINES 0
+#endif
+
+#ifndef INCLUDE_vTaskPrioritySet
+	#define INCLUDE_vTaskPrioritySet 0
+#endif
+
+#ifndef INCLUDE_uxTaskPriorityGet
+	#define INCLUDE_uxTaskPriorityGet 0
+#endif
+
+#ifndef INCLUDE_vTaskDelete
+	#define INCLUDE_vTaskDelete 0
+#endif
+
+#ifndef INCLUDE_vTaskSuspend
+	#define INCLUDE_vTaskSuspend 0
+#endif
+
+#ifndef INCLUDE_vTaskDelayUntil
+	#define INCLUDE_vTaskDelayUntil 0
+#endif
+
+#ifndef INCLUDE_vTaskDelay
+	#define INCLUDE_vTaskDelay 0
+#endif
+
+#ifndef INCLUDE_xTaskGetIdleTaskHandle
+	#define INCLUDE_xTaskGetIdleTaskHandle 0
+#endif
+
+#ifndef INCLUDE_xTaskAbortDelay
+	#define INCLUDE_xTaskAbortDelay 0
+#endif
+
+#ifndef INCLUDE_xQueueGetMutexHolder
+	#define INCLUDE_xQueueGetMutexHolder 0
+#endif
+
+#ifndef INCLUDE_xSemaphoreGetMutexHolder
+	#define INCLUDE_xSemaphoreGetMutexHolder INCLUDE_xQueueGetMutexHolder
+#endif
+
+#ifndef INCLUDE_xTaskGetHandle
+	#define INCLUDE_xTaskGetHandle 0
+#endif
+
+#ifndef INCLUDE_uxTaskGetStackHighWaterMark
+	#define INCLUDE_uxTaskGetStackHighWaterMark 0
+#endif
+
+#ifndef INCLUDE_eTaskGetState
+	#define INCLUDE_eTaskGetState 0
+#endif
+
+#ifndef INCLUDE_xTaskResumeFromISR
+	#define INCLUDE_xTaskResumeFromISR 1
+#endif
+
+#ifndef INCLUDE_xTimerPendFunctionCall
+	#define INCLUDE_xTimerPendFunctionCall 0
+#endif
+
+#ifndef INCLUDE_xTaskGetSchedulerState
+	#define INCLUDE_xTaskGetSchedulerState 0
+#endif
+
+#ifndef INCLUDE_xTaskGetCurrentTaskHandle
+	#define INCLUDE_xTaskGetCurrentTaskHandle 0
+#endif
+
+#if configUSE_CO_ROUTINES != 0
+	#ifndef configMAX_CO_ROUTINE_PRIORITIES
+		#error configMAX_CO_ROUTINE_PRIORITIES must be greater than or equal to 1.
+	#endif
+#endif
+
+#ifndef configUSE_DAEMON_TASK_STARTUP_HOOK
+	#define configUSE_DAEMON_TASK_STARTUP_HOOK 0
+#endif
+
+#ifndef configUSE_APPLICATION_TASK_TAG
+	#define configUSE_APPLICATION_TASK_TAG 0
+#endif
+
+#ifndef configNUM_THREAD_LOCAL_STORAGE_POINTERS
+	#define configNUM_THREAD_LOCAL_STORAGE_POINTERS 0
+#endif
+
+#ifndef configUSE_RECURSIVE_MUTEXES
+	#define configUSE_RECURSIVE_MUTEXES 0
+#endif
+
+#ifndef configUSE_MUTEXES
+	#define configUSE_MUTEXES 0
+#endif
+
+#ifndef configUSE_TIMERS
+	#define configUSE_TIMERS 0
+#endif
+
+#ifndef configUSE_COUNTING_SEMAPHORES
+	#define configUSE_COUNTING_SEMAPHORES 0
+#endif
+
+#ifndef configUSE_ALTERNATIVE_API
+	#define configUSE_ALTERNATIVE_API 0
+#endif
+
+#ifndef portCRITICAL_NESTING_IN_TCB
+	#define portCRITICAL_NESTING_IN_TCB 0
+#endif
+
+#ifndef configMAX_TASK_NAME_LEN
+	#define configMAX_TASK_NAME_LEN 16
+#endif
+
+#ifndef configIDLE_SHOULD_YIELD
+	#define configIDLE_SHOULD_YIELD		1
+#endif
+
+#if configMAX_TASK_NAME_LEN < 1
+	#error configMAX_TASK_NAME_LEN must be set to a minimum of 1 in FreeRTOSConfig.h
+#endif
+
+#ifndef configASSERT
+	#define configASSERT( x )
+	#define configASSERT_DEFINED 0
+#else
+	#define configASSERT_DEFINED 1
+#endif
+
+/* The timers module relies on xTaskGetSchedulerState(). */
+#if configUSE_TIMERS == 1
+
+	#ifndef configTIMER_TASK_PRIORITY
+		#error If configUSE_TIMERS is set to 1 then configTIMER_TASK_PRIORITY must also be defined.
+	#endif /* configTIMER_TASK_PRIORITY */
+
+	#ifndef configTIMER_QUEUE_LENGTH
+		#error If configUSE_TIMERS is set to 1 then configTIMER_QUEUE_LENGTH must also be defined.
+	#endif /* configTIMER_QUEUE_LENGTH */
+
+	#ifndef configTIMER_TASK_STACK_DEPTH
+		#error If configUSE_TIMERS is set to 1 then configTIMER_TASK_STACK_DEPTH must also be defined.
+	#endif /* configTIMER_TASK_STACK_DEPTH */
+
+#endif /* configUSE_TIMERS */
+
+#ifndef portSET_INTERRUPT_MASK_FROM_ISR
+	#define portSET_INTERRUPT_MASK_FROM_ISR() 0
+#endif
+
+#ifndef portCLEAR_INTERRUPT_MASK_FROM_ISR
+	#define portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedStatusValue ) ( void ) uxSavedStatusValue
+#endif
+
+#ifndef portCLEAN_UP_TCB
+	#define portCLEAN_UP_TCB( pxTCB ) ( void ) pxTCB
+#endif
+
+#ifndef portPRE_TASK_DELETE_HOOK
+	#define portPRE_TASK_DELETE_HOOK( pvTaskToDelete, pxYieldPending )
+#endif
+
+#ifndef portSETUP_TCB
+	#define portSETUP_TCB( pxTCB ) ( void ) pxTCB
+#endif
+
+#ifndef configQUEUE_REGISTRY_SIZE
+	#define configQUEUE_REGISTRY_SIZE 0U
+#endif
+
+#if ( configQUEUE_REGISTRY_SIZE < 1 )
+	#define vQueueAddToRegistry( xQueue, pcName )
+	#define vQueueUnregisterQueue( xQueue )
+	#define pcQueueGetName( xQueue )
+#endif
+
+#ifndef portPOINTER_SIZE_TYPE
+	#define portPOINTER_SIZE_TYPE uint32_t
+#endif
+
+/* Remove any unused trace macros. */
+#ifndef traceSTART
+	/* Used to perform any necessary initialisation - for example, open a file
+	into which trace is to be written. */
+	#define traceSTART()
+#endif
+
+#ifndef traceEND
+	/* Use to close a trace, for example close a file into which trace has been
+	written. */
+	#define traceEND()
+#endif
+
+#ifndef traceTASK_SWITCHED_IN
+	/* Called after a task has been selected to run.  pxCurrentTCB holds a pointer
+	to the task control block of the selected task. */
+	#define traceTASK_SWITCHED_IN()
+#endif
+
+#ifndef traceINCREASE_TICK_COUNT
+	/* Called before stepping the tick count after waking from tickless idle
+	sleep. */
+	#define traceINCREASE_TICK_COUNT( x )
+#endif
+
+#ifndef traceLOW_POWER_IDLE_BEGIN
+	/* Called immediately before entering tickless idle. */
+	#define traceLOW_POWER_IDLE_BEGIN()
+#endif
+
+#ifndef	traceLOW_POWER_IDLE_END
+	/* Called when returning to the Idle task after a tickless idle. */
+	#define traceLOW_POWER_IDLE_END()
+#endif
+
+#ifndef traceTASK_SWITCHED_OUT
+	/* Called before a task has been selected to run.  pxCurrentTCB holds a pointer
+	to the task control block of the task being switched out. */
+	#define traceTASK_SWITCHED_OUT()
+#endif
+
+#ifndef traceTASK_PRIORITY_INHERIT
+	/* Called when a task attempts to take a mutex that is already held by a
+	lower priority task.  pxTCBOfMutexHolder is a pointer to the TCB of the task
+	that holds the mutex.  uxInheritedPriority is the priority the mutex holder
+	will inherit (the priority of the task that is attempting to obtain the
+	muted. */
+	#define traceTASK_PRIORITY_INHERIT( pxTCBOfMutexHolder, uxInheritedPriority )
+#endif
+
+#ifndef traceTASK_PRIORITY_DISINHERIT
+	/* Called when a task releases a mutex, the holding of which had resulted in
+	the task inheriting the priority of a higher priority task.
+	pxTCBOfMutexHolder is a pointer to the TCB of the task that is releasing the
+	mutex.  uxOriginalPriority is the task's configured (base) priority. */
+	#define traceTASK_PRIORITY_DISINHERIT( pxTCBOfMutexHolder, uxOriginalPriority )
+#endif
+
+#ifndef traceBLOCKING_ON_QUEUE_RECEIVE
+	/* Task is about to block because it cannot read from a
+	queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore
+	upon which the read was attempted.  pxCurrentTCB points to the TCB of the
+	task that attempted the read. */
+	#define traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue )
+#endif
+
+#ifndef traceBLOCKING_ON_QUEUE_SEND
+	/* Task is about to block because it cannot write to a
+	queue/mutex/semaphore.  pxQueue is a pointer to the queue/mutex/semaphore
+	upon which the write was attempted.  pxCurrentTCB points to the TCB of the
+	task that attempted the write. */
+	#define traceBLOCKING_ON_QUEUE_SEND( pxQueue )
+#endif
+
+#ifndef configCHECK_FOR_STACK_OVERFLOW
+	#define configCHECK_FOR_STACK_OVERFLOW 0
+#endif
+
+/* The following event macros are embedded in the kernel API calls. */
+
+#ifndef traceMOVED_TASK_TO_READY_STATE
+	#define traceMOVED_TASK_TO_READY_STATE( pxTCB )
+#endif
+
+#ifndef tracePOST_MOVED_TASK_TO_READY_STATE
+	#define tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
+#endif
+
+#ifndef traceQUEUE_CREATE
+	#define traceQUEUE_CREATE( pxNewQueue )
+#endif
+
+#ifndef traceQUEUE_CREATE_FAILED
+	#define traceQUEUE_CREATE_FAILED( ucQueueType )
+#endif
+
+#ifndef traceCREATE_MUTEX
+	#define traceCREATE_MUTEX( pxNewQueue )
+#endif
+
+#ifndef traceCREATE_MUTEX_FAILED
+	#define traceCREATE_MUTEX_FAILED()
+#endif
+
+#ifndef traceGIVE_MUTEX_RECURSIVE
+	#define traceGIVE_MUTEX_RECURSIVE( pxMutex )
+#endif
+
+#ifndef traceGIVE_MUTEX_RECURSIVE_FAILED
+	#define traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex )
+#endif
+
+#ifndef traceTAKE_MUTEX_RECURSIVE
+	#define traceTAKE_MUTEX_RECURSIVE( pxMutex )
+#endif
+
+#ifndef traceTAKE_MUTEX_RECURSIVE_FAILED
+	#define traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex )
+#endif
+
+#ifndef traceCREATE_COUNTING_SEMAPHORE
+	#define traceCREATE_COUNTING_SEMAPHORE()
+#endif
+
+#ifndef traceCREATE_COUNTING_SEMAPHORE_FAILED
+	#define traceCREATE_COUNTING_SEMAPHORE_FAILED()
+#endif
+
+#ifndef traceQUEUE_SEND
+	#define traceQUEUE_SEND( pxQueue )
+#endif
+
+#ifndef traceQUEUE_SEND_FAILED
+	#define traceQUEUE_SEND_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE
+	#define traceQUEUE_RECEIVE( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK
+	#define traceQUEUE_PEEK( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK_FROM_ISR
+	#define traceQUEUE_PEEK_FROM_ISR( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE_FAILED
+	#define traceQUEUE_RECEIVE_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_SEND_FROM_ISR
+	#define traceQUEUE_SEND_FROM_ISR( pxQueue )
+#endif
+
+#ifndef traceQUEUE_SEND_FROM_ISR_FAILED
+	#define traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE_FROM_ISR
+	#define traceQUEUE_RECEIVE_FROM_ISR( pxQueue )
+#endif
+
+#ifndef traceQUEUE_RECEIVE_FROM_ISR_FAILED
+	#define traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_PEEK_FROM_ISR_FAILED
+	#define traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue )
+#endif
+
+#ifndef traceQUEUE_DELETE
+	#define traceQUEUE_DELETE( pxQueue )
+#endif
+
+#ifndef traceTASK_CREATE
+	#define traceTASK_CREATE( pxNewTCB )
+#endif
+
+#ifndef traceTASK_CREATE_FAILED
+	#define traceTASK_CREATE_FAILED()
+#endif
+
+#ifndef traceTASK_DELETE
+	#define traceTASK_DELETE( pxTaskToDelete )
+#endif
+
+#ifndef traceTASK_DELAY_UNTIL
+	#define traceTASK_DELAY_UNTIL( x )
+#endif
+
+#ifndef traceTASK_DELAY
+	#define traceTASK_DELAY()
+#endif
+
+#ifndef traceTASK_PRIORITY_SET
+	#define traceTASK_PRIORITY_SET( pxTask, uxNewPriority )
+#endif
+
+#ifndef traceTASK_SUSPEND
+	#define traceTASK_SUSPEND( pxTaskToSuspend )
+#endif
+
+#ifndef traceTASK_RESUME
+	#define traceTASK_RESUME( pxTaskToResume )
+#endif
+
+#ifndef traceTASK_RESUME_FROM_ISR
+	#define traceTASK_RESUME_FROM_ISR( pxTaskToResume )
+#endif
+
+#ifndef traceTASK_INCREMENT_TICK
+	#define traceTASK_INCREMENT_TICK( xTickCount )
+#endif
+
+#ifndef traceTIMER_CREATE
+	#define traceTIMER_CREATE( pxNewTimer )
+#endif
+
+#ifndef traceTIMER_CREATE_FAILED
+	#define traceTIMER_CREATE_FAILED()
+#endif
+
+#ifndef traceTIMER_COMMAND_SEND
+	#define traceTIMER_COMMAND_SEND( xTimer, xMessageID, xMessageValueValue, xReturn )
+#endif
+
+#ifndef traceTIMER_EXPIRED
+	#define traceTIMER_EXPIRED( pxTimer )
+#endif
+
+#ifndef traceTIMER_COMMAND_RECEIVED
+	#define traceTIMER_COMMAND_RECEIVED( pxTimer, xMessageID, xMessageValue )
+#endif
+
+#ifndef traceMALLOC
+    #define traceMALLOC( pvAddress, uiSize )
+#endif
+
+#ifndef traceFREE
+    #define traceFREE( pvAddress, uiSize )
+#endif
+
+#ifndef traceEVENT_GROUP_CREATE
+	#define traceEVENT_GROUP_CREATE( xEventGroup )
+#endif
+
+#ifndef traceEVENT_GROUP_CREATE_FAILED
+	#define traceEVENT_GROUP_CREATE_FAILED()
+#endif
+
+#ifndef traceEVENT_GROUP_SYNC_BLOCK
+	#define traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor )
+#endif
+
+#ifndef traceEVENT_GROUP_SYNC_END
+	#define traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred
+#endif
+
+#ifndef traceEVENT_GROUP_WAIT_BITS_BLOCK
+	#define traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor )
+#endif
+
+#ifndef traceEVENT_GROUP_WAIT_BITS_END
+	#define traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred ) ( void ) xTimeoutOccurred
+#endif
+
+#ifndef traceEVENT_GROUP_CLEAR_BITS
+	#define traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear )
+#endif
+
+#ifndef traceEVENT_GROUP_CLEAR_BITS_FROM_ISR
+	#define traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear )
+#endif
+
+#ifndef traceEVENT_GROUP_SET_BITS
+	#define traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet )
+#endif
+
+#ifndef traceEVENT_GROUP_SET_BITS_FROM_ISR
+	#define traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet )
+#endif
+
+#ifndef traceEVENT_GROUP_DELETE
+	#define traceEVENT_GROUP_DELETE( xEventGroup )
+#endif
+
+#ifndef tracePEND_FUNC_CALL
+	#define tracePEND_FUNC_CALL(xFunctionToPend, pvParameter1, ulParameter2, ret)
+#endif
+
+#ifndef tracePEND_FUNC_CALL_FROM_ISR
+	#define tracePEND_FUNC_CALL_FROM_ISR(xFunctionToPend, pvParameter1, ulParameter2, ret)
+#endif
+
+#ifndef traceQUEUE_REGISTRY_ADD
+	#define traceQUEUE_REGISTRY_ADD(xQueue, pcQueueName)
+#endif
+
+#ifndef traceTASK_NOTIFY_TAKE_BLOCK
+	#define traceTASK_NOTIFY_TAKE_BLOCK()
+#endif
+
+#ifndef traceTASK_NOTIFY_TAKE
+	#define traceTASK_NOTIFY_TAKE()
+#endif
+
+#ifndef traceTASK_NOTIFY_WAIT_BLOCK
+	#define traceTASK_NOTIFY_WAIT_BLOCK()
+#endif
+
+#ifndef traceTASK_NOTIFY_WAIT
+	#define traceTASK_NOTIFY_WAIT()
+#endif
+
+#ifndef traceTASK_NOTIFY
+	#define traceTASK_NOTIFY()
+#endif
+
+#ifndef traceTASK_NOTIFY_FROM_ISR
+	#define traceTASK_NOTIFY_FROM_ISR()
+#endif
+
+#ifndef traceTASK_NOTIFY_GIVE_FROM_ISR
+	#define traceTASK_NOTIFY_GIVE_FROM_ISR()
+#endif
+
+#ifndef configGENERATE_RUN_TIME_STATS
+	#define configGENERATE_RUN_TIME_STATS 0
+#endif
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+	#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS
+		#error If configGENERATE_RUN_TIME_STATS is defined then portCONFIGURE_TIMER_FOR_RUN_TIME_STATS must also be defined.  portCONFIGURE_TIMER_FOR_RUN_TIME_STATS should call a port layer function to setup a peripheral timer/counter that can then be used as the run time counter time base.
+	#endif /* portCONFIGURE_TIMER_FOR_RUN_TIME_STATS */
+
+	#ifndef portGET_RUN_TIME_COUNTER_VALUE
+		#ifndef portALT_GET_RUN_TIME_COUNTER_VALUE
+			#error If configGENERATE_RUN_TIME_STATS is defined then either portGET_RUN_TIME_COUNTER_VALUE or portALT_GET_RUN_TIME_COUNTER_VALUE must also be defined.  See the examples provided and the FreeRTOS web site for more information.
+		#endif /* portALT_GET_RUN_TIME_COUNTER_VALUE */
+	#endif /* portGET_RUN_TIME_COUNTER_VALUE */
+
+#endif /* configGENERATE_RUN_TIME_STATS */
+
+#ifndef portCONFIGURE_TIMER_FOR_RUN_TIME_STATS
+	#define portCONFIGURE_TIMER_FOR_RUN_TIME_STATS()
+#endif
+
+#ifndef configUSE_MALLOC_FAILED_HOOK
+	#define configUSE_MALLOC_FAILED_HOOK 0
+#endif
+
+#ifndef portPRIVILEGE_BIT
+	#define portPRIVILEGE_BIT ( ( UBaseType_t ) 0x00 )
+#endif
+
+#ifndef portYIELD_WITHIN_API
+	#define portYIELD_WITHIN_API portYIELD
+#endif
+
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime )
+#endif
+
+#ifndef configEXPECTED_IDLE_TIME_BEFORE_SLEEP
+	#define configEXPECTED_IDLE_TIME_BEFORE_SLEEP 2
+#endif
+
+#if configEXPECTED_IDLE_TIME_BEFORE_SLEEP < 2
+	#error configEXPECTED_IDLE_TIME_BEFORE_SLEEP must not be less than 2
+#endif
+
+#ifndef configUSE_TICKLESS_IDLE
+	#define configUSE_TICKLESS_IDLE 0
+#endif
+
+#ifndef configPRE_SLEEP_PROCESSING
+	#define configPRE_SLEEP_PROCESSING( x )
+#endif
+
+#ifndef configPOST_SLEEP_PROCESSING
+	#define configPOST_SLEEP_PROCESSING( x )
+#endif
+
+#ifndef configUSE_QUEUE_SETS
+	#define configUSE_QUEUE_SETS 0
+#endif
+
+#ifndef portTASK_USES_FLOATING_POINT
+	#define portTASK_USES_FLOATING_POINT()
+#endif
+
+#ifndef configUSE_TIME_SLICING
+	#define configUSE_TIME_SLICING 1
+#endif
+
+#ifndef configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS
+	#define configINCLUDE_APPLICATION_DEFINED_PRIVILEGED_FUNCTIONS 0
+#endif
+
+#ifndef configUSE_STATS_FORMATTING_FUNCTIONS
+	#define configUSE_STATS_FORMATTING_FUNCTIONS 0
+#endif
+
+#ifndef portASSERT_IF_INTERRUPT_PRIORITY_INVALID
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID()
+#endif
+
+#ifndef configUSE_TRACE_FACILITY
+	#define configUSE_TRACE_FACILITY 0
+#endif
+
+#ifndef mtCOVERAGE_TEST_MARKER
+	#define mtCOVERAGE_TEST_MARKER()
+#endif
+
+#ifndef mtCOVERAGE_TEST_DELAY
+	#define mtCOVERAGE_TEST_DELAY()
+#endif
+
+#ifndef portASSERT_IF_IN_ISR
+	#define portASSERT_IF_IN_ISR()
+#endif
+
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 0
+#endif
+
+#ifndef configAPPLICATION_ALLOCATED_HEAP
+	#define configAPPLICATION_ALLOCATED_HEAP 0
+#endif
+
+#ifndef configUSE_TASK_NOTIFICATIONS
+	#define configUSE_TASK_NOTIFICATIONS 1
+#endif
+
+#ifndef portTICK_TYPE_IS_ATOMIC
+	#define portTICK_TYPE_IS_ATOMIC 0
+#endif
+
+#ifndef configSUPPORT_STATIC_ALLOCATION
+	/* Defaults to 0 for backward compatibility. */
+	#define configSUPPORT_STATIC_ALLOCATION 0
+#endif
+
+#ifndef configSUPPORT_DYNAMIC_ALLOCATION
+	/* Defaults to 1 for backward compatibility. */
+	#define configSUPPORT_DYNAMIC_ALLOCATION 1
+#endif
+
+/* Sanity check the configuration. */
+#if( configUSE_TICKLESS_IDLE != 0 )
+	#if( INCLUDE_vTaskSuspend != 1 )
+		#error INCLUDE_vTaskSuspend must be set to 1 if configUSE_TICKLESS_IDLE is not set to 0
+	#endif /* INCLUDE_vTaskSuspend */
+#endif /* configUSE_TICKLESS_IDLE */
+
+#if( ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 0 ) )
+	#error configSUPPORT_STATIC_ALLOCATION and configSUPPORT_DYNAMIC_ALLOCATION cannot both be 0, but can both be 1.
+#endif
+
+#if( ( configUSE_RECURSIVE_MUTEXES == 1 ) && ( configUSE_MUTEXES != 1 ) )
+	#error configUSE_MUTEXES must be set to 1 to use recursive mutexes
+#endif
+
+#if( portTICK_TYPE_IS_ATOMIC == 0 )
+	/* Either variables of tick type cannot be read atomically, or
+	portTICK_TYPE_IS_ATOMIC was not set - map the critical sections used when
+	the tick count is returned to the standard critical section macros. */
+	#define portTICK_TYPE_ENTER_CRITICAL() portENTER_CRITICAL()
+	#define portTICK_TYPE_EXIT_CRITICAL() portEXIT_CRITICAL()
+	#define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()
+	#define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( ( x ) )
+#else
+	/* The tick type can be read atomically, so critical sections used when the
+	tick count is returned can be defined away. */
+	#define portTICK_TYPE_ENTER_CRITICAL()
+	#define portTICK_TYPE_EXIT_CRITICAL()
+	#define portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR() 0
+	#define portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( x ) ( void ) x
+#endif
+
+/* Definitions to allow backward compatibility with FreeRTOS versions prior to
+V8 if desired. */
+#ifndef configENABLE_BACKWARD_COMPATIBILITY
+	#define configENABLE_BACKWARD_COMPATIBILITY 1
+#endif
+
+#if configENABLE_BACKWARD_COMPATIBILITY == 1
+	#define eTaskStateGet eTaskGetState
+	#define portTickType TickType_t
+	#define xTaskHandle TaskHandle_t
+	#define xQueueHandle QueueHandle_t
+	#define xSemaphoreHandle SemaphoreHandle_t
+	#define xQueueSetHandle QueueSetHandle_t
+	#define xQueueSetMemberHandle QueueSetMemberHandle_t
+	#define xTimeOutType TimeOut_t
+	#define xMemoryRegion MemoryRegion_t
+	#define xTaskParameters TaskParameters_t
+	#define xTaskStatusType	TaskStatus_t
+	#define xTimerHandle TimerHandle_t
+	#define xCoRoutineHandle CoRoutineHandle_t
+	#define pdTASK_HOOK_CODE TaskHookFunction_t
+	#define portTICK_RATE_MS portTICK_PERIOD_MS
+	#define pcTaskGetTaskName pcTaskGetName
+	#define pcTimerGetTimerName pcTimerGetName
+	#define pcQueueGetQueueName pcQueueGetName
+	#define vTaskGetTaskInfo vTaskGetInfo
+
+	/* Backward compatibility within the scheduler code only - these definitions
+	are not really required but are included for completeness. */
+	#define tmrTIMER_CALLBACK TimerCallbackFunction_t
+	#define pdTASK_CODE TaskFunction_t
+	#define xListItem ListItem_t
+	#define xList List_t
+#endif /* configENABLE_BACKWARD_COMPATIBILITY */
+
+#if( configUSE_ALTERNATIVE_API != 0 )
+	#error The alternative API was deprecated some time ago, and was removed in FreeRTOS V9.0 0
+#endif
+
+/* Set configUSE_TASK_FPU_SUPPORT to 0 to omit floating point support even
+if floating point hardware is otherwise supported by the FreeRTOS port in use.
+This constant is not supported by all FreeRTOS ports that include floating
+point support. */
+#ifndef configUSE_TASK_FPU_SUPPORT
+	#define configUSE_TASK_FPU_SUPPORT 1
+#endif
+
+/*
+ * In line with software engineering best practice, FreeRTOS implements a strict
+ * data hiding policy, so the real structures used by FreeRTOS to maintain the
+ * state of tasks, queues, semaphores, etc. are not accessible to the application
+ * code.  However, if the application writer wants to statically allocate such
+ * an object then the size of the object needs to be know.  Dummy structures
+ * that are guaranteed to have the same size and alignment requirements of the
+ * real objects are used for this purpose.  The dummy list and list item
+ * structures below are used for inclusion in such a dummy structure.
+ */
+struct xSTATIC_LIST_ITEM
+{
+	TickType_t xDummy1;
+	void *pvDummy2[ 4 ];
+};
+typedef struct xSTATIC_LIST_ITEM StaticListItem_t;
+
+/* See the comments above the struct xSTATIC_LIST_ITEM definition. */
+struct xSTATIC_MINI_LIST_ITEM
+{
+	TickType_t xDummy1;
+	void *pvDummy2[ 2 ];
+};
+typedef struct xSTATIC_MINI_LIST_ITEM StaticMiniListItem_t;
+
+/* See the comments above the struct xSTATIC_LIST_ITEM definition. */
+typedef struct xSTATIC_LIST
+{
+	UBaseType_t uxDummy1;
+	void *pvDummy2;
+	StaticMiniListItem_t xDummy3;
+} StaticList_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy.  This means the Task structure used internally by
+ * FreeRTOS is not accessible to application code.  However, if the application
+ * writer wants to statically allocate the memory required to create a task then
+ * the size of the task object needs to be know.  The StaticTask_t structure
+ * below is provided for this purpose.  Its sizes and alignment requirements are
+ * guaranteed to match those of the genuine structure, no matter which
+ * architecture is being used, and no matter how the values in FreeRTOSConfig.h
+ * are set.  Its contents are somewhat obfuscated in the hope users will
+ * recognise that it would be unwise to make direct use of the structure members.
+ */
+typedef struct xSTATIC_TCB
+{
+	void				*pxDummy1;
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+		xMPU_SETTINGS	xDummy2;
+	#endif
+	StaticListItem_t	xDummy3[ 2 ];
+	UBaseType_t			uxDummy5;
+	void				*pxDummy6;
+	uint8_t				ucDummy7[ configMAX_TASK_NAME_LEN ];
+	#if ( portSTACK_GROWTH > 0 )
+		void			*pxDummy8;
+	#endif
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+		UBaseType_t		uxDummy9;
+	#endif
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t		uxDummy10[ 2 ];
+	#endif
+	#if ( configUSE_MUTEXES == 1 )
+		UBaseType_t		uxDummy12[ 2 ];
+	#endif
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+		void			*pxDummy14;
+	#endif
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+		void			*pvDummy15[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+	#endif
+	#if ( configGENERATE_RUN_TIME_STATS == 1 )
+		uint32_t		ulDummy16;
+	#endif
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		struct	_reent	xDummy17;
+	#endif
+	#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+		uint32_t 		ulDummy18;
+		uint8_t 		ucDummy19;
+	#endif
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+		uint8_t			uxDummy20;
+	#endif
+
+} StaticTask_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy.  This means the Queue structure used internally by
+ * FreeRTOS is not accessible to application code.  However, if the application
+ * writer wants to statically allocate the memory required to create a queue
+ * then the size of the queue object needs to be know.  The StaticQueue_t
+ * structure below is provided for this purpose.  Its sizes and alignment
+ * requirements are guaranteed to match those of the genuine structure, no
+ * matter which architecture is being used, and no matter how the values in
+ * FreeRTOSConfig.h are set.  Its contents are somewhat obfuscated in the hope
+ * users will recognise that it would be unwise to make direct use of the
+ * structure members.
+ */
+typedef struct xSTATIC_QUEUE
+{
+	void *pvDummy1[ 3 ];
+
+	union
+	{
+		void *pvDummy2;
+		UBaseType_t uxDummy2;
+	} u;
+
+	StaticList_t xDummy3[ 2 ];
+	UBaseType_t uxDummy4[ 3 ];
+	uint8_t ucDummy5[ 2 ];
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+		uint8_t ucDummy6;
+	#endif
+
+	#if ( configUSE_QUEUE_SETS == 1 )
+		void *pvDummy7;
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxDummy8;
+		uint8_t ucDummy9;
+	#endif
+
+} StaticQueue_t;
+typedef StaticQueue_t StaticSemaphore_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy.  This means the event group structure used
+ * internally by FreeRTOS is not accessible to application code.  However, if
+ * the application writer wants to statically allocate the memory required to
+ * create an event group then the size of the event group object needs to be
+ * know.  The StaticEventGroup_t structure below is provided for this purpose.
+ * Its sizes and alignment requirements are guaranteed to match those of the
+ * genuine structure, no matter which architecture is being used, and no matter
+ * how the values in FreeRTOSConfig.h are set.  Its contents are somewhat
+ * obfuscated in the hope users will recognise that it would be unwise to make
+ * direct use of the structure members.
+ */
+typedef struct xSTATIC_EVENT_GROUP
+{
+	TickType_t xDummy1;
+	StaticList_t xDummy2;
+
+	#if( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxDummy3;
+	#endif
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+			uint8_t ucDummy4;
+	#endif
+
+} StaticEventGroup_t;
+
+/*
+ * In line with software engineering best practice, especially when supplying a
+ * library that is likely to change in future versions, FreeRTOS implements a
+ * strict data hiding policy.  This means the software timer structure used
+ * internally by FreeRTOS is not accessible to application code.  However, if
+ * the application writer wants to statically allocate the memory required to
+ * create a software timer then the size of the queue object needs to be know.
+ * The StaticTimer_t structure below is provided for this purpose.  Its sizes
+ * and alignment requirements are guaranteed to match those of the genuine
+ * structure, no matter which architecture is being used, and no matter how the
+ * values in FreeRTOSConfig.h are set.  Its contents are somewhat obfuscated in
+ * the hope users will recognise that it would be unwise to make direct use of
+ * the structure members.
+ */
+typedef struct xSTATIC_TIMER
+{
+	void				*pvDummy1;
+	StaticListItem_t	xDummy2;
+	TickType_t			xDummy3;
+	UBaseType_t			uxDummy4;
+	void 				*pvDummy5[ 2 ];
+	#if( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t		uxDummy6;
+	#endif
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+		uint8_t 		ucDummy7;
+	#endif
+
+} StaticTimer_t;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* INC_FREERTOS_H */
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/FreeRTOSConfig.h b/STM32F1/libraries/FreeRTOS900/utility/FreeRTOSConfig.h
new file mode 100644
index 000000000..87d6c5d8a
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/FreeRTOSConfig.h
@@ -0,0 +1,144 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#ifndef FREERTOS_CONFIG_H
+#define FREERTOS_CONFIG_H
+
+/*-----------------------------------------------------------
+ * Application specific definitions.
+ *
+ * These definitions should be adjusted for your particular hardware and
+ * application requirements.
+ *
+ * THESE PARAMETERS ARE DESCRIBED WITHIN THE 'CONFIGURATION' SECTION OF THE
+ * FreeRTOS API DOCUMENTATION AVAILABLE ON THE FreeRTOS.org WEB SITE.
+ *
+ * See http://www.freertos.org/a00110.html.
+ *----------------------------------------------------------*/
+
+#define configUSE_PREEMPTION		1
+#define configUSE_IDLE_HOOK			0
+#define configUSE_TICK_HOOK			0
+#define configCPU_CLOCK_HZ			( ( unsigned long ) F_CPU )
+#define configTICK_RATE_HZ			( ( TickType_t ) 1000 )
+#define configMAX_PRIORITIES		( 5 )
+#define configMINIMAL_STACK_SIZE	( ( unsigned short ) 120 )
+#define configTOTAL_HEAP_SIZE		( ( size_t ) ( 8 * 1024 ) )
+#define configMAX_TASK_NAME_LEN		( 16 )
+#define configUSE_TRACE_FACILITY	1
+#define configUSE_16_BIT_TICKS		0
+#define configIDLE_SHOULD_YIELD		1
+
+/* Co-routine definitions. */
+#define configUSE_CO_ROUTINES 		0
+#define configMAX_CO_ROUTINE_PRIORITIES ( 2 )
+
+#define configUSE_MUTEXES				1
+#define configUSE_COUNTING_SEMAPHORES 	1
+#define configUSE_ALTERNATIVE_API 		0
+#define configCHECK_FOR_STACK_OVERFLOW	2
+#define configUSE_RECURSIVE_MUTEXES		1
+#define configQUEUE_REGISTRY_SIZE		0
+#define configGENERATE_RUN_TIME_STATS	0
+
+/* Set the following definitions to 1 to include the API function, or zero
+to exclude the API function. */
+
+#define INCLUDE_vTaskPrioritySet		1
+#define INCLUDE_uxTaskPriorityGet		1
+#define INCLUDE_vTaskDelete				1
+#define INCLUDE_vTaskCleanUpResources	0
+#define INCLUDE_vTaskSuspend			1
+#define INCLUDE_vTaskDelayUntil			1
+#define INCLUDE_vTaskDelay				1
+
+/* This is the raw value as per the Cortex-M3 NVIC.  Values can be 255
+(lowest) to 0 (1?) (highest). */
+#define configKERNEL_INTERRUPT_PRIORITY 		255
+/* !!!! configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to zero !!!!
+See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html. */
+#define configMAX_SYSCALL_INTERRUPT_PRIORITY 	191 /* equivalent to 0xb0, or priority 11. */
+
+
+/* This is the value being used as per the ST library which permits 16
+priority values, 0 to 15.  This must correspond to the
+configKERNEL_INTERRUPT_PRIORITY setting.  Here 15 corresponds to the lowest
+NVIC value of 255. */
+#define configLIBRARY_KERNEL_INTERRUPT_PRIORITY	15
+
+/*-----------------------------------------------------------
+ * UART configuration.
+ *-----------------------------------------------------------*/
+#define configCOM0_RX_BUFFER_LENGTH		128
+#define configCOM0_TX_BUFFER_LENGTH		128
+#define configCOM1_RX_BUFFER_LENGTH		128
+#define configCOM1_TX_BUFFER_LENGTH		128
+
+#endif /* FREERTOS_CONFIG_H */
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/MemMang/heap_1.c b/STM32F1/libraries/FreeRTOS900/utility/MemMang/heap_1.c
new file mode 100644
index 000000000..178ff7c32
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/MemMang/heap_1.c
@@ -0,0 +1,174 @@
+/*
+    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+
+/*
+ * The simplest possible implementation of pvPortMalloc().  Note that this
+ * implementation does NOT allow allocated memory to be freed again.
+ *
+ * See heap_2.c, heap_3.c and heap_4.c for alternative implementations, and the
+ * memory management pages of http://www.FreeRTOS.org for more information.
+ */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* A few bytes might be lost to byte aligning the heap start address. */
+#define configADJUSTED_HEAP_SIZE	( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )
+
+/* Allocate the memory for the heap. */
+static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+static size_t xNextFreeByte = ( size_t ) 0;
+
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+void *pvReturn = NULL;
+static uint8_t *pucAlignedHeap = NULL;
+
+	/* Ensure that blocks are always aligned to the required number of bytes. */
+	#if portBYTE_ALIGNMENT != 1
+		if( xWantedSize & portBYTE_ALIGNMENT_MASK )
+		{
+			/* Byte alignment required. */
+			xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+		}
+	#endif
+
+	vTaskSuspendAll();
+	{
+		if( pucAlignedHeap == NULL )
+		{
+			/* Ensure the heap starts on a correctly aligned boundary. */
+			pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) &ucHeap[ portBYTE_ALIGNMENT ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
+		}
+
+		/* Check there is enough room left for the allocation. */
+		if( ( ( xNextFreeByte + xWantedSize ) < configADJUSTED_HEAP_SIZE ) &&
+			( ( xNextFreeByte + xWantedSize ) > xNextFreeByte )	)/* Check for overflow. */
+		{
+			/* Return the next free byte then increment the index past this
+			block. */
+			pvReturn = pucAlignedHeap + xNextFreeByte;
+			xNextFreeByte += xWantedSize;
+		}
+
+		traceMALLOC( pvReturn, xWantedSize );
+	}
+	( void ) xTaskResumeAll();
+
+	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+	}
+	#endif
+
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+	/* Memory cannot be freed using this scheme.  See heap_2.c, heap_3.c and
+	heap_4.c for alternative implementations, and the memory management pages of
+	http://www.FreeRTOS.org for more information. */
+	( void ) pv;
+
+	/* Force an assert as it is invalid to call this function. */
+	configASSERT( pv == NULL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+	/* Only required when static memory is not cleared. */
+	xNextFreeByte = ( size_t ) 0;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return ( configADJUSTED_HEAP_SIZE - xNextFreeByte );
+}
+
+
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/MemMang/heap_2.c b/STM32F1/libraries/FreeRTOS900/utility/MemMang/heap_2.c
new file mode 100644
index 000000000..a1a76747e
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/MemMang/heap_2.c
@@ -0,0 +1,303 @@
+/*
+    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/*
+ * A sample implementation of pvPortMalloc() and vPortFree() that permits
+ * allocated blocks to be freed, but does not combine adjacent free blocks
+ * into a single larger block (and so will fragment memory).  See heap_4.c for
+ * an equivalent that does combine adjacent blocks into single larger blocks.
+ *
+ * See heap_1.c, heap_3.c and heap_4.c for alternative implementations, and the
+ * memory management pages of http://www.FreeRTOS.org for more information.
+ */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* A few bytes might be lost to byte aligning the heap start address. */
+#define configADJUSTED_HEAP_SIZE	( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )
+
+/*
+ * Initialises the heap structures before their first use.
+ */
+static void prvHeapInit( void );
+
+/* Allocate the memory for the heap. */
+static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+
+/* Define the linked list structure.  This is used to link free blocks in order
+of their size. */
+typedef struct A_BLOCK_LINK
+{
+	struct A_BLOCK_LINK *pxNextFreeBlock;	/*<< The next free block in the list. */
+	size_t xBlockSize;						/*<< The size of the free block. */
+} BlockLink_t;
+
+
+static const uint16_t heapSTRUCT_SIZE	= ( ( sizeof ( BlockLink_t ) + ( portBYTE_ALIGNMENT - 1 ) ) & ~portBYTE_ALIGNMENT_MASK );
+#define heapMINIMUM_BLOCK_SIZE	( ( size_t ) ( heapSTRUCT_SIZE * 2 ) )
+
+/* Create a couple of list links to mark the start and end of the list. */
+static BlockLink_t xStart, xEnd;
+
+/* Keeps track of the number of free bytes remaining, but says nothing about
+fragmentation. */
+static size_t xFreeBytesRemaining = configADJUSTED_HEAP_SIZE;
+
+/* STATIC FUNCTIONS ARE DEFINED AS MACROS TO MINIMIZE THE FUNCTION CALL DEPTH. */
+
+/*
+ * Insert a block into the list of free blocks - which is ordered by size of
+ * the block.  Small blocks at the start of the list and large blocks at the end
+ * of the list.
+ */
+#define prvInsertBlockIntoFreeList( pxBlockToInsert )								\
+{																					\
+BlockLink_t *pxIterator;																\
+size_t xBlockSize;																	\
+																					\
+	xBlockSize = pxBlockToInsert->xBlockSize;										\
+																					\
+	/* Iterate through the list until a block is found that has a larger size */	\
+	/* than the block we are inserting. */											\
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock->xBlockSize < xBlockSize; pxIterator = pxIterator->pxNextFreeBlock )	\
+	{																				\
+		/* There is nothing to do here - just iterate to the correct position. */	\
+	}																				\
+																					\
+	/* Update the list to include the block being inserted in the correct */		\
+	/* position. */																	\
+	pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;					\
+	pxIterator->pxNextFreeBlock = pxBlockToInsert;									\
+}
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+static BaseType_t xHeapHasBeenInitialised = pdFALSE;
+void *pvReturn = NULL;
+
+	vTaskSuspendAll();
+	{
+		/* If this is the first call to malloc then the heap will require
+		initialisation to setup the list of free blocks. */
+		if( xHeapHasBeenInitialised == pdFALSE )
+		{
+			prvHeapInit();
+			xHeapHasBeenInitialised = pdTRUE;
+		}
+
+		/* The wanted size is increased so it can contain a BlockLink_t
+		structure in addition to the requested amount of bytes. */
+		if( xWantedSize > 0 )
+		{
+			xWantedSize += heapSTRUCT_SIZE;
+
+			/* Ensure that blocks are always aligned to the required number of bytes. */
+			if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0 )
+			{
+				/* Byte alignment required. */
+				xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+			}
+		}
+
+		if( ( xWantedSize > 0 ) && ( xWantedSize < configADJUSTED_HEAP_SIZE ) )
+		{
+			/* Blocks are stored in byte order - traverse the list from the start
+			(smallest) block until one of adequate size is found. */
+			pxPreviousBlock = &xStart;
+			pxBlock = xStart.pxNextFreeBlock;
+			while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+			{
+				pxPreviousBlock = pxBlock;
+				pxBlock = pxBlock->pxNextFreeBlock;
+			}
+
+			/* If we found the end marker then a block of adequate size was not found. */
+			if( pxBlock != &xEnd )
+			{
+				/* Return the memory space - jumping over the BlockLink_t structure
+				at its start. */
+				pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + heapSTRUCT_SIZE );
+
+				/* This block is being returned for use so must be taken out of the
+				list of free blocks. */
+				pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+				/* If the block is larger than required it can be split into two. */
+				if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+				{
+					/* This block is to be split into two.  Create a new block
+					following the number of bytes requested. The void cast is
+					used to prevent byte alignment warnings from the compiler. */
+					pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+
+					/* Calculate the sizes of two blocks split from the single
+					block. */
+					pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+					pxBlock->xBlockSize = xWantedSize;
+
+					/* Insert the new block into the list of free blocks. */
+					prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );
+				}
+
+				xFreeBytesRemaining -= pxBlock->xBlockSize;
+			}
+		}
+
+		traceMALLOC( pvReturn, xWantedSize );
+	}
+	( void ) xTaskResumeAll();
+
+	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+	}
+	#endif
+
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		before it. */
+		puc -= heapSTRUCT_SIZE;
+
+		/* This unexpected casting is to keep some compilers from issuing
+		byte alignment warnings. */
+		pxLink = ( void * ) puc;
+
+		vTaskSuspendAll();
+		{
+			/* Add this block to the list of free blocks. */
+			prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+			xFreeBytesRemaining += pxLink->xBlockSize;
+			traceFREE( pv, pxLink->xBlockSize );
+		}
+		( void ) xTaskResumeAll();
+	}
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+	/* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+
+	/* Ensure the heap starts on a correctly aligned boundary. */
+	pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) &ucHeap[ portBYTE_ALIGNMENT ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
+
+	/* xStart is used to hold a pointer to the first item in the list of free
+	blocks.  The void cast is used to prevent compiler warnings. */
+	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+	xStart.xBlockSize = ( size_t ) 0;
+
+	/* xEnd is used to mark the end of the list of free blocks. */
+	xEnd.xBlockSize = configADJUSTED_HEAP_SIZE;
+	xEnd.pxNextFreeBlock = NULL;
+
+	/* To start with there is a single free block that is sized to take up the
+	entire heap space. */
+	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+	pxFirstFreeBlock->xBlockSize = configADJUSTED_HEAP_SIZE;
+	pxFirstFreeBlock->pxNextFreeBlock = &xEnd;
+}
+/*-----------------------------------------------------------*/
diff --git a/STM32F1/libraries/FreeRTOS900/utility/MemMang/heap_3.c b/STM32F1/libraries/FreeRTOS900/utility/MemMang/heap_3.c
new file mode 100644
index 000000000..f3c49c06a
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/MemMang/heap_3.c
@@ -0,0 +1,135 @@
+/*
+    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+
+/*
+ * Implementation of pvPortMalloc() and vPortFree() that relies on the
+ * compilers own malloc() and free() implementations.
+ *
+ * This file can only be used if the linker is configured to to generate
+ * a heap memory area.
+ *
+ * See heap_1.c, heap_2.c and heap_4.c for alternative implementations, and the
+ * memory management pages of http://www.FreeRTOS.org for more information.
+ */
+
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+void *pvReturn;
+
+	vTaskSuspendAll();
+	{
+		pvReturn = malloc( xWantedSize );
+		traceMALLOC( pvReturn, xWantedSize );
+	}
+	( void ) xTaskResumeAll();
+
+	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+	}
+	#endif
+
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+	if( pv )
+	{
+		vTaskSuspendAll();
+		{
+			free( pv );
+			traceFREE( pv, 0 );
+		}
+		( void ) xTaskResumeAll();
+	}
+}
+
+
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/MemMang/heap_4.c b/STM32F1/libraries/FreeRTOS900/utility/MemMang/heap_4.c
new file mode 100644
index 000000000..8df0e9a79
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/MemMang/heap_4.c
@@ -0,0 +1,474 @@
+/*
+    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/*
+ * A sample implementation of pvPortMalloc() and vPortFree() that combines
+ * (coalescences) adjacent memory blocks as they are freed, and in so doing
+ * limits memory fragmentation.
+ *
+ * See heap_1.c, heap_2.c and heap_3.c for alternative implementations, and the
+ * memory management pages of http://www.FreeRTOS.org for more information.
+ */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Block sizes must not get too small. */
+#define heapMINIMUM_BLOCK_SIZE	( ( size_t ) ( xHeapStructSize * 2 ) )
+
+/* Assumes 8bit bytes! */
+#define heapBITS_PER_BYTE		( ( size_t ) 8 )
+
+/* Allocate the memory for the heap. */
+#if( configAPPLICATION_ALLOCATED_HEAP == 1 )
+	/* The application writer has already defined the array used for the RTOS
+	heap - probably so it can be placed in a special segment or address. */
+	extern uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#else
+	static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+#endif /* configAPPLICATION_ALLOCATED_HEAP */
+
+/* Define the linked list structure.  This is used to link free blocks in order
+of their memory address. */
+typedef struct A_BLOCK_LINK
+{
+	struct A_BLOCK_LINK *pxNextFreeBlock;	/*<< The next free block in the list. */
+	size_t xBlockSize;						/*<< The size of the free block. */
+} BlockLink_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Inserts a block of memory that is being freed into the correct position in
+ * the list of free memory blocks.  The block being freed will be merged with
+ * the block in front it and/or the block behind it if the memory blocks are
+ * adjacent to each other.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+
+/*
+ * Called automatically to setup the required heap structures the first time
+ * pvPortMalloc() is called.
+ */
+static void prvHeapInit( void );
+
+/*-----------------------------------------------------------*/
+
+/* The size of the structure placed at the beginning of each allocated memory
+block must by correctly byte aligned. */
+static const size_t xHeapStructSize	= ( ( sizeof( BlockLink_t ) + ( ( ( size_t ) portBYTE_ALIGNMENT_MASK ) - ( size_t ) 1 ) ) & ~( ( size_t ) portBYTE_ALIGNMENT_MASK ) );
+
+/* Create a couple of list links to mark the start and end of the list. */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/* Keeps track of the number of free bytes remaining, but says nothing about
+fragmentation. */
+static size_t xFreeBytesRemaining = 0U;
+static size_t xMinimumEverFreeBytesRemaining = 0U;
+
+/* Gets set to the top bit of an size_t type.  When this bit in the xBlockSize
+member of an BlockLink_t structure is set then the block belongs to the
+application.  When the bit is free the block is still part of the free heap
+space. */
+static size_t xBlockAllocatedBit = 0;
+
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+	vTaskSuspendAll();
+	{
+		/* If this is the first call to malloc then the heap will require
+		initialisation to setup the list of free blocks. */
+		if( pxEnd == NULL )
+		{
+			prvHeapInit();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Check the requested block size is not so large that the top bit is
+		set.  The top bit of the block size member of the BlockLink_t structure
+		is used to determine who owns the block - the application or the
+		kernel, so it must be free. */
+		if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+		{
+			/* The wanted size is increased so it can contain a BlockLink_t
+			structure in addition to the requested amount of bytes. */
+			if( xWantedSize > 0 )
+			{
+				xWantedSize += xHeapStructSize;
+
+				/* Ensure that blocks are always aligned to the required number
+				of bytes. */
+				if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+				{
+					/* Byte alignment required. */
+					xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+					configASSERT( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) == 0 );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+			{
+				/* Traverse the list from the start	(lowest address) block until
+				one	of adequate size is found. */
+				pxPreviousBlock = &xStart;
+				pxBlock = xStart.pxNextFreeBlock;
+				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+				{
+					pxPreviousBlock = pxBlock;
+					pxBlock = pxBlock->pxNextFreeBlock;
+				}
+
+				/* If the end marker was reached then a block of adequate size
+				was	not found. */
+				if( pxBlock != pxEnd )
+				{
+					/* Return the memory space pointed to - jumping over the
+					BlockLink_t structure at its start. */
+					pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + xHeapStructSize );
+
+					/* This block is being returned for use so must be taken out
+					of the list of free blocks. */
+					pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+					/* If the block is larger than required it can be split into
+					two. */
+					if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+					{
+						/* This block is to be split into two.  Create a new
+						block following the number of bytes requested. The void
+						cast is used to prevent byte alignment warnings from the
+						compiler. */
+						pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+						configASSERT( ( ( ( uint32_t ) pxNewBlockLink ) & portBYTE_ALIGNMENT_MASK ) == 0 );
+
+						/* Calculate the sizes of two blocks split from the
+						single block. */
+						pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+						pxBlock->xBlockSize = xWantedSize;
+
+						/* Insert the new block into the list of free blocks. */
+						prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+					if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+					{
+						xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The block is being returned - it is allocated and owned
+					by the application and has no "next" block. */
+					pxBlock->xBlockSize |= xBlockAllocatedBit;
+					pxBlock->pxNextFreeBlock = NULL;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		traceMALLOC( pvReturn, xWantedSize );
+	}
+	( void ) xTaskResumeAll();
+
+	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif
+
+	configASSERT( ( ( ( uint32_t ) pvReturn ) & portBYTE_ALIGNMENT_MASK ) == 0 );
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		before it. */
+		puc -= xHeapStructSize;
+
+		/* This casting is to keep the compiler from issuing warnings. */
+		pxLink = ( void * ) puc;
+
+		/* Check the block is actually allocated. */
+		configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+		configASSERT( pxLink->pxNextFreeBlock == NULL );
+
+		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+		{
+			if( pxLink->pxNextFreeBlock == NULL )
+			{
+				/* The block is being returned to the heap - it is no longer
+				allocated. */
+				pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+				vTaskSuspendAll();
+				{
+					/* Add this block to the list of free blocks. */
+					xFreeBytesRemaining += pxLink->xBlockSize;
+					traceFREE( pv, pxLink->xBlockSize );
+					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+				}
+				( void ) xTaskResumeAll();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+	return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+	/* This just exists to keep the linker quiet. */
+}
+/*-----------------------------------------------------------*/
+
+static void prvHeapInit( void )
+{
+BlockLink_t *pxFirstFreeBlock;
+uint8_t *pucAlignedHeap;
+uint32_t ulAddress;
+size_t xTotalHeapSize = configTOTAL_HEAP_SIZE;
+
+	/* Ensure the heap starts on a correctly aligned boundary. */
+	ulAddress = ( uint32_t ) ucHeap;
+
+	if( ( ulAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
+	{
+		ulAddress += ( portBYTE_ALIGNMENT - 1 );
+		ulAddress &= ~( ( uint32_t ) portBYTE_ALIGNMENT_MASK );
+		xTotalHeapSize -= ulAddress - ( uint32_t ) ucHeap;
+	}
+
+	pucAlignedHeap = ( uint8_t * ) ulAddress;
+
+	/* xStart is used to hold a pointer to the first item in the list of free
+	blocks.  The void cast is used to prevent compiler warnings. */
+	xStart.pxNextFreeBlock = ( void * ) pucAlignedHeap;
+	xStart.xBlockSize = ( size_t ) 0;
+
+	/* pxEnd is used to mark the end of the list of free blocks and is inserted
+	at the end of the heap space. */
+	ulAddress = ( ( uint32_t ) pucAlignedHeap ) + xTotalHeapSize;
+	ulAddress -= xHeapStructSize;
+	ulAddress &= ~( ( uint32_t ) portBYTE_ALIGNMENT_MASK );
+	pxEnd = ( void * ) ulAddress;
+	pxEnd->xBlockSize = 0;
+	pxEnd->pxNextFreeBlock = NULL;
+
+	/* To start with there is a single free block that is sized to take up the
+	entire heap space, minus the space taken by pxEnd. */
+	pxFirstFreeBlock = ( void * ) pucAlignedHeap;
+	pxFirstFreeBlock->xBlockSize = ulAddress - ( uint32_t ) pxFirstFreeBlock;
+	pxFirstFreeBlock->pxNextFreeBlock = pxEnd;
+
+	/* Only one block exists - and it covers the entire usable heap space. */
+	xMinimumEverFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+	xFreeBytesRemaining = pxFirstFreeBlock->xBlockSize;
+
+	/* Work out the position of the top bit in a size_t variable. */
+	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+	/* Iterate through the list until a block is found that has a higher address
+	than the block being inserted. */
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+	{
+		/* Nothing to do here, just iterate to the right position. */
+	}
+
+	/* Do the block being inserted, and the block it is being inserted after
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxIterator;
+	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+	{
+		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+		pxBlockToInsert = pxIterator;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Do the block being inserted, and the block it is being inserted before
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxBlockToInsert;
+	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+	{
+		if( pxIterator->pxNextFreeBlock != pxEnd )
+		{
+			/* Form one big block from the two blocks. */
+			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+		}
+		else
+		{
+			pxBlockToInsert->pxNextFreeBlock = pxEnd;
+		}
+	}
+	else
+	{
+		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+	}
+
+	/* If the block being inserted plugged a gab, so was merged with the block
+	before and the block after, then it's pxNextFreeBlock pointer will have
+	already been set, and should not be set here as that would make it point
+	to itself. */
+	if( pxIterator != pxBlockToInsert )
+	{
+		pxIterator->pxNextFreeBlock = pxBlockToInsert;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/MemMang/heap_5.c b/STM32F1/libraries/FreeRTOS900/utility/MemMang/heap_5.c
new file mode 100644
index 000000000..b7bcaae20
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/MemMang/heap_5.c
@@ -0,0 +1,523 @@
+/*
+    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/*
+ * A sample implementation of pvPortMalloc() that allows the heap to be defined
+ * across multiple non-contigous blocks and combines (coalescences) adjacent
+ * memory blocks as they are freed.
+ *
+ * See heap_1.c, heap_2.c, heap_3.c and heap_4.c for alternative
+ * implementations, and the memory management pages of http://www.FreeRTOS.org
+ * for more information.
+ *
+ * Usage notes:
+ *
+ * vPortDefineHeapRegions() ***must*** be called before pvPortMalloc().
+ * pvPortMalloc() will be called if any task objects (tasks, queues, event
+ * groups, etc.) are created, therefore vPortDefineHeapRegions() ***must*** be
+ * called before any other objects are defined.
+ *
+ * vPortDefineHeapRegions() takes a single parameter.  The parameter is an array
+ * of HeapRegion_t structures.  HeapRegion_t is defined in portable.h as
+ *
+ * typedef struct HeapRegion
+ * {
+ *	uint8_t *pucStartAddress; << Start address of a block of memory that will be part of the heap.
+ *	size_t xSizeInBytes;	  << Size of the block of memory.
+ * } HeapRegion_t;
+ *
+ * The array is terminated using a NULL zero sized region definition, and the
+ * memory regions defined in the array ***must*** appear in address order from
+ * low address to high address.  So the following is a valid example of how
+ * to use the function.
+ *
+ * HeapRegion_t xHeapRegions[] =
+ * {
+ * 	{ ( uint8_t * ) 0x80000000UL, 0x10000 }, << Defines a block of 0x10000 bytes starting at address 0x80000000
+ * 	{ ( uint8_t * ) 0x90000000UL, 0xa0000 }, << Defines a block of 0xa0000 bytes starting at address of 0x90000000
+ * 	{ NULL, 0 }                << Terminates the array.
+ * };
+ *
+ * vPortDefineHeapRegions( xHeapRegions ); << Pass the array into vPortDefineHeapRegions().
+ *
+ * Note 0x80000000 is the lower address so appears in the array first.
+ *
+ */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* Block sizes must not get too small. */
+#define heapMINIMUM_BLOCK_SIZE	( ( size_t ) ( uxHeapStructSize << 1 ) )
+
+/* Assumes 8bit bytes! */
+#define heapBITS_PER_BYTE		( ( size_t ) 8 )
+
+/* Define the linked list structure.  This is used to link free blocks in order
+of their memory address. */
+typedef struct A_BLOCK_LINK
+{
+	struct A_BLOCK_LINK *pxNextFreeBlock;	/*<< The next free block in the list. */
+	size_t xBlockSize;						/*<< The size of the free block. */
+} BlockLink_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Inserts a block of memory that is being freed into the correct position in
+ * the list of free memory blocks.  The block being freed will be merged with
+ * the block in front it and/or the block behind it if the memory blocks are
+ * adjacent to each other.
+ */
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert );
+
+/*-----------------------------------------------------------*/
+
+/* The size of the structure placed at the beginning of each allocated memory
+block must by correctly byte aligned. */
+static const uint32_t uxHeapStructSize	= ( ( sizeof ( BlockLink_t ) + ( portBYTE_ALIGNMENT - 1 ) ) & ~portBYTE_ALIGNMENT_MASK );
+
+/* Create a couple of list links to mark the start and end of the list. */
+static BlockLink_t xStart, *pxEnd = NULL;
+
+/* Keeps track of the number of free bytes remaining, but says nothing about
+fragmentation. */
+static size_t xFreeBytesRemaining = 0;
+static size_t xMinimumEverFreeBytesRemaining = 0;
+
+/* Gets set to the top bit of an size_t type.  When this bit in the xBlockSize
+member of an BlockLink_t structure is set then the block belongs to the
+application.  When the bit is free the block is still part of the free heap
+space. */
+static size_t xBlockAllocatedBit = 0;
+
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+BlockLink_t *pxBlock, *pxPreviousBlock, *pxNewBlockLink;
+void *pvReturn = NULL;
+
+	/* The heap must be initialised before the first call to
+	prvPortMalloc(). */
+	configASSERT( pxEnd );
+
+	vTaskSuspendAll();
+	{
+		/* Check the requested block size is not so large that the top bit is
+		set.  The top bit of the block size member of the BlockLink_t structure
+		is used to determine who owns the block - the application or the
+		kernel, so it must be free. */
+		if( ( xWantedSize & xBlockAllocatedBit ) == 0 )
+		{
+			/* The wanted size is increased so it can contain a BlockLink_t
+			structure in addition to the requested amount of bytes. */
+			if( xWantedSize > 0 )
+			{
+				xWantedSize += uxHeapStructSize;
+
+				/* Ensure that blocks are always aligned to the required number
+				of bytes. */
+				if( ( xWantedSize & portBYTE_ALIGNMENT_MASK ) != 0x00 )
+				{
+					/* Byte alignment required. */
+					xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			if( ( xWantedSize > 0 ) && ( xWantedSize <= xFreeBytesRemaining ) )
+			{
+				/* Traverse the list from the start	(lowest address) block until
+				one	of adequate size is found. */
+				pxPreviousBlock = &xStart;
+				pxBlock = xStart.pxNextFreeBlock;
+				while( ( pxBlock->xBlockSize < xWantedSize ) && ( pxBlock->pxNextFreeBlock != NULL ) )
+				{
+					pxPreviousBlock = pxBlock;
+					pxBlock = pxBlock->pxNextFreeBlock;
+				}
+
+				/* If the end marker was reached then a block of adequate size
+				was	not found. */
+				if( pxBlock != pxEnd )
+				{
+					/* Return the memory space pointed to - jumping over the
+					BlockLink_t structure at its start. */
+					pvReturn = ( void * ) ( ( ( uint8_t * ) pxPreviousBlock->pxNextFreeBlock ) + uxHeapStructSize );
+
+					/* This block is being returned for use so must be taken out
+					of the list of free blocks. */
+					pxPreviousBlock->pxNextFreeBlock = pxBlock->pxNextFreeBlock;
+
+					/* If the block is larger than required it can be split into
+					two. */
+					if( ( pxBlock->xBlockSize - xWantedSize ) > heapMINIMUM_BLOCK_SIZE )
+					{
+						/* This block is to be split into two.  Create a new
+						block following the number of bytes requested. The void
+						cast is used to prevent byte alignment warnings from the
+						compiler. */
+						pxNewBlockLink = ( void * ) ( ( ( uint8_t * ) pxBlock ) + xWantedSize );
+
+						/* Calculate the sizes of two blocks split from the
+						single block. */
+						pxNewBlockLink->xBlockSize = pxBlock->xBlockSize - xWantedSize;
+						pxBlock->xBlockSize = xWantedSize;
+
+						/* Insert the new block into the list of free blocks. */
+						prvInsertBlockIntoFreeList( ( pxNewBlockLink ) );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					xFreeBytesRemaining -= pxBlock->xBlockSize;
+
+					if( xFreeBytesRemaining < xMinimumEverFreeBytesRemaining )
+					{
+						xMinimumEverFreeBytesRemaining = xFreeBytesRemaining;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The block is being returned - it is allocated and owned
+					by the application and has no "next" block. */
+					pxBlock->xBlockSize |= xBlockAllocatedBit;
+					pxBlock->pxNextFreeBlock = NULL;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		traceMALLOC( pvReturn, xWantedSize );
+	}
+	( void ) xTaskResumeAll();
+
+	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif
+
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+uint8_t *puc = ( uint8_t * ) pv;
+BlockLink_t *pxLink;
+
+	if( pv != NULL )
+	{
+		/* The memory being freed will have an BlockLink_t structure immediately
+		before it. */
+		puc -= uxHeapStructSize;
+
+		/* This casting is to keep the compiler from issuing warnings. */
+		pxLink = ( void * ) puc;
+
+		/* Check the block is actually allocated. */
+		configASSERT( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 );
+		configASSERT( pxLink->pxNextFreeBlock == NULL );
+
+		if( ( pxLink->xBlockSize & xBlockAllocatedBit ) != 0 )
+		{
+			if( pxLink->pxNextFreeBlock == NULL )
+			{
+				/* The block is being returned to the heap - it is no longer
+				allocated. */
+				pxLink->xBlockSize &= ~xBlockAllocatedBit;
+
+				vTaskSuspendAll();
+				{
+					/* Add this block to the list of free blocks. */
+					xFreeBytesRemaining += pxLink->xBlockSize;
+					traceFREE( pv, pxLink->xBlockSize );
+					prvInsertBlockIntoFreeList( ( ( BlockLink_t * ) pxLink ) );
+				}
+				( void ) xTaskResumeAll();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return xFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetMinimumEverFreeHeapSize( void )
+{
+	return xMinimumEverFreeBytesRemaining;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInsertBlockIntoFreeList( BlockLink_t *pxBlockToInsert )
+{
+BlockLink_t *pxIterator;
+uint8_t *puc;
+
+	/* Iterate through the list until a block is found that has a higher address
+	than the block being inserted. */
+	for( pxIterator = &xStart; pxIterator->pxNextFreeBlock < pxBlockToInsert; pxIterator = pxIterator->pxNextFreeBlock )
+	{
+		/* Nothing to do here, just iterate to the right position. */
+	}
+
+	/* Do the block being inserted, and the block it is being inserted after
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxIterator;
+	if( ( puc + pxIterator->xBlockSize ) == ( uint8_t * ) pxBlockToInsert )
+	{
+		pxIterator->xBlockSize += pxBlockToInsert->xBlockSize;
+		pxBlockToInsert = pxIterator;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Do the block being inserted, and the block it is being inserted before
+	make a contiguous block of memory? */
+	puc = ( uint8_t * ) pxBlockToInsert;
+	if( ( puc + pxBlockToInsert->xBlockSize ) == ( uint8_t * ) pxIterator->pxNextFreeBlock )
+	{
+		if( pxIterator->pxNextFreeBlock != pxEnd )
+		{
+			/* Form one big block from the two blocks. */
+			pxBlockToInsert->xBlockSize += pxIterator->pxNextFreeBlock->xBlockSize;
+			pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock->pxNextFreeBlock;
+		}
+		else
+		{
+			pxBlockToInsert->pxNextFreeBlock = pxEnd;
+		}
+	}
+	else
+	{
+		pxBlockToInsert->pxNextFreeBlock = pxIterator->pxNextFreeBlock;
+	}
+
+	/* If the block being inserted plugged a gab, so was merged with the block
+	before and the block after, then it's pxNextFreeBlock pointer will have
+	already been set, and should not be set here as that would make it point
+	to itself. */
+	if( pxIterator != pxBlockToInsert )
+	{
+		pxIterator->pxNextFreeBlock = pxBlockToInsert;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions )
+{
+BlockLink_t *pxFirstFreeBlockInRegion = NULL, *pxPreviousFreeBlock;
+uint8_t *pucAlignedHeap;
+size_t xTotalRegionSize, xTotalHeapSize = 0;
+BaseType_t xDefinedRegions = 0;
+uint32_t ulAddress;
+const HeapRegion_t *pxHeapRegion;
+
+	/* Can only call once! */
+	configASSERT( pxEnd == NULL );
+
+	pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] );
+
+	while( pxHeapRegion->xSizeInBytes > 0 )
+	{
+		xTotalRegionSize = pxHeapRegion->xSizeInBytes;
+
+		/* Ensure the heap region starts on a correctly aligned boundary. */
+		ulAddress = ( uint32_t ) pxHeapRegion->pucStartAddress;
+		if( ( ulAddress & portBYTE_ALIGNMENT_MASK ) != 0 )
+		{
+			ulAddress += ( portBYTE_ALIGNMENT - 1 );
+			ulAddress &= ~portBYTE_ALIGNMENT_MASK;
+
+			/* Adjust the size for the bytes lost to alignment. */
+			xTotalRegionSize -= ulAddress - ( uint32_t ) pxHeapRegion->pucStartAddress;
+		}
+
+		pucAlignedHeap = ( uint8_t * ) ulAddress;
+
+		/* Set xStart if it has not already been set. */
+		if( xDefinedRegions == 0 )
+		{
+			/* xStart is used to hold a pointer to the first item in the list of
+			free blocks.  The void cast is used to prevent compiler warnings. */
+			xStart.pxNextFreeBlock = ( BlockLink_t * ) pucAlignedHeap;
+			xStart.xBlockSize = ( size_t ) 0;
+		}
+		else
+		{
+			/* Should only get here if one region has already been added to the
+			heap. */
+			configASSERT( pxEnd != NULL );
+
+			/* Check blocks are passed in with increasing start addresses. */
+			configASSERT( ulAddress > ( uint32_t ) pxEnd );
+		}
+
+		/* Remember the location of the end marker in the previous region, if
+		any. */
+		pxPreviousFreeBlock = pxEnd;
+
+		/* pxEnd is used to mark the end of the list of free blocks and is
+		inserted at the end of the region space. */
+		ulAddress = ( ( uint32_t ) pucAlignedHeap ) + xTotalRegionSize;
+		ulAddress -= uxHeapStructSize;
+		ulAddress &= ~portBYTE_ALIGNMENT_MASK;
+		pxEnd = ( BlockLink_t * ) ulAddress;
+		pxEnd->xBlockSize = 0;
+		pxEnd->pxNextFreeBlock = NULL;
+
+		/* To start with there is a single free block in this region that is
+		sized to take up the entire heap region minus the space taken by the
+		free block structure. */
+		pxFirstFreeBlockInRegion = ( BlockLink_t * ) pucAlignedHeap;
+		pxFirstFreeBlockInRegion->xBlockSize = ulAddress - ( uint32_t ) pxFirstFreeBlockInRegion;
+		pxFirstFreeBlockInRegion->pxNextFreeBlock = pxEnd;
+
+		/* If this is not the first region that makes up the entire heap space
+		then link the previous region to this region. */
+		if( pxPreviousFreeBlock != NULL )
+		{
+			pxPreviousFreeBlock->pxNextFreeBlock = pxFirstFreeBlockInRegion;
+		}
+
+		xTotalHeapSize += pxFirstFreeBlockInRegion->xBlockSize;
+
+		/* Move onto the next HeapRegion_t structure. */
+		xDefinedRegions++;
+		pxHeapRegion = &( pxHeapRegions[ xDefinedRegions ] );
+	}
+
+	xMinimumEverFreeBytesRemaining = xTotalHeapSize;
+	xFreeBytesRemaining = xTotalHeapSize;
+
+	/* Check something was actually defined before it is accessed. */
+	configASSERT( xTotalHeapSize );
+
+	/* Work out the position of the top bit in a size_t variable. */
+	xBlockAllocatedBit = ( ( size_t ) 1 ) << ( ( sizeof( size_t ) * heapBITS_PER_BYTE ) - 1 );
+}
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/StackMacros.h b/STM32F1/libraries/FreeRTOS900/utility/StackMacros.h
new file mode 100644
index 000000000..13c6b829b
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/StackMacros.h
@@ -0,0 +1,171 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#ifndef STACK_MACROS_H
+#define STACK_MACROS_H
+
+/*
+ * Call the stack overflow hook function if the stack of the task being swapped
+ * out is currently overflowed, or looks like it might have overflowed in the
+ * past.
+ *
+ * Setting configCHECK_FOR_STACK_OVERFLOW to 1 will cause the macro to check
+ * the current stack state only - comparing the current top of stack value to
+ * the stack limit.  Setting configCHECK_FOR_STACK_OVERFLOW to greater than 1
+ * will also cause the last few stack bytes to be checked to ensure the value
+ * to which the bytes were set when the task was created have not been
+ * overwritten.  Note this second test does not guarantee that an overflowed
+ * stack will always be recognised.
+ */
+
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack <= pxCurrentTCB->pxStack )										\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW == 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	/* Only the current stack state is to be checked. */
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+																										\
+		/* Is the currently saved stack pointer within the stack limit? */								\
+		if( pxCurrentTCB->pxTopOfStack >= pxCurrentTCB->pxEndOfStack )									\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* configCHECK_FOR_STACK_OVERFLOW == 1 */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH < 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																\
+	{																									\
+		const uint32_t * const pulStack = ( uint32_t * ) pxCurrentTCB->pxStack;							\
+		const uint32_t ulCheckValue = ( uint32_t ) 0xa5a5a5a5;											\
+																										\
+		if( ( pulStack[ 0 ] != ulCheckValue ) ||												\
+			( pulStack[ 1 ] != ulCheckValue ) ||												\
+			( pulStack[ 2 ] != ulCheckValue ) ||												\
+			( pulStack[ 3 ] != ulCheckValue ) )												\
+		{																								\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );	\
+		}																								\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) && ( portSTACK_GROWTH > 0 ) )
+
+	#define taskCHECK_FOR_STACK_OVERFLOW()																								\
+	{																																	\
+	int8_t *pcEndOfStack = ( int8_t * ) pxCurrentTCB->pxEndOfStack;																		\
+	static const uint8_t ucExpectedStackBytes[] = {	tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE,		\
+													tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE, tskSTACK_FILL_BYTE };	\
+																																		\
+																																		\
+		pcEndOfStack -= sizeof( ucExpectedStackBytes );																					\
+																																		\
+		/* Has the extremity of the task stack ever been written over? */																\
+		if( memcmp( ( void * ) pcEndOfStack, ( void * ) ucExpectedStackBytes, sizeof( ucExpectedStackBytes ) ) != 0 )					\
+		{																																\
+			vApplicationStackOverflowHook( ( TaskHandle_t ) pxCurrentTCB, pxCurrentTCB->pcTaskName );									\
+		}																																\
+	}
+
+#endif /* #if( configCHECK_FOR_STACK_OVERFLOW > 1 ) */
+/*-----------------------------------------------------------*/
+
+/* Remove stack overflow macro if not being used. */
+#ifndef taskCHECK_FOR_STACK_OVERFLOW
+	#define taskCHECK_FOR_STACK_OVERFLOW()
+#endif
+
+
+
+#endif /* STACK_MACROS_H */
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/croutine.c b/STM32F1/libraries/FreeRTOS900/utility/croutine.c
new file mode 100644
index 000000000..993e09b29
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/croutine.c
@@ -0,0 +1,395 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "croutine.h"
+
+/* Remove the whole file is co-routines are not being used. */
+#if( configUSE_CO_ROUTINES != 0 )
+
+/*
+ * Some kernel aware debuggers require data to be viewed to be global, rather
+ * than file scope.
+ */
+#ifdef portREMOVE_STATIC_QUALIFIER
+	#define static
+#endif
+
+
+/* Lists for ready and blocked co-routines. --------------------*/
+static List_t pxReadyCoRoutineLists[ configMAX_CO_ROUTINE_PRIORITIES ];	/*< Prioritised ready co-routines. */
+static List_t xDelayedCoRoutineList1;									/*< Delayed co-routines. */
+static List_t xDelayedCoRoutineList2;									/*< Delayed co-routines (two lists are used - one for delays that have overflowed the current tick count. */
+static List_t * pxDelayedCoRoutineList;									/*< Points to the delayed co-routine list currently being used. */
+static List_t * pxOverflowDelayedCoRoutineList;							/*< Points to the delayed co-routine list currently being used to hold co-routines that have overflowed the current tick count. */
+static List_t xPendingReadyCoRoutineList;								/*< Holds co-routines that have been readied by an external event.  They cannot be added directly to the ready lists as the ready lists cannot be accessed by interrupts. */
+
+/* Other file private variables. --------------------------------*/
+CRCB_t * pxCurrentCoRoutine = NULL;
+static UBaseType_t uxTopCoRoutineReadyPriority = 0;
+static TickType_t xCoRoutineTickCount = 0, xLastTickCount = 0, xPassedTicks = 0;
+
+/* The initial state of the co-routine when it is created. */
+#define corINITIAL_STATE	( 0 )
+
+/*
+ * Place the co-routine represented by pxCRCB into the appropriate ready queue
+ * for the priority.  It is inserted at the end of the list.
+ *
+ * This macro accesses the co-routine ready lists and therefore must not be
+ * used from within an ISR.
+ */
+#define prvAddCoRoutineToReadyQueue( pxCRCB )																		\
+{																													\
+	if( pxCRCB->uxPriority > uxTopCoRoutineReadyPriority )															\
+	{																												\
+		uxTopCoRoutineReadyPriority = pxCRCB->uxPriority;															\
+	}																												\
+	vListInsertEnd( ( List_t * ) &( pxReadyCoRoutineLists[ pxCRCB->uxPriority ] ), &( pxCRCB->xGenericListItem ) );	\
+}
+
+/*
+ * Utility to ready all the lists used by the scheduler.  This is called
+ * automatically upon the creation of the first co-routine.
+ */
+static void prvInitialiseCoRoutineLists( void );
+
+/*
+ * Co-routines that are readied by an interrupt cannot be placed directly into
+ * the ready lists (there is no mutual exclusion).  Instead they are placed in
+ * in the pending ready list in order that they can later be moved to the ready
+ * list by the co-routine scheduler.
+ */
+static void prvCheckPendingReadyList( void );
+
+/*
+ * Macro that looks at the list of co-routines that are currently delayed to
+ * see if any require waking.
+ *
+ * Co-routines are stored in the queue in the order of their wake time -
+ * meaning once one co-routine has been found whose timer has not expired
+ * we need not look any further down the list.
+ */
+static void prvCheckDelayedList( void );
+
+/*-----------------------------------------------------------*/
+
+BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex )
+{
+BaseType_t xReturn;
+CRCB_t *pxCoRoutine;
+
+	/* Allocate the memory that will store the co-routine control block. */
+	pxCoRoutine = ( CRCB_t * ) pvPortMalloc( sizeof( CRCB_t ) );
+	if( pxCoRoutine )
+	{
+		/* If pxCurrentCoRoutine is NULL then this is the first co-routine to
+		be created and the co-routine data structures need initialising. */
+		if( pxCurrentCoRoutine == NULL )
+		{
+			pxCurrentCoRoutine = pxCoRoutine;
+			prvInitialiseCoRoutineLists();
+		}
+
+		/* Check the priority is within limits. */
+		if( uxPriority >= configMAX_CO_ROUTINE_PRIORITIES )
+		{
+			uxPriority = configMAX_CO_ROUTINE_PRIORITIES - 1;
+		}
+
+		/* Fill out the co-routine control block from the function parameters. */
+		pxCoRoutine->uxState = corINITIAL_STATE;
+		pxCoRoutine->uxPriority = uxPriority;
+		pxCoRoutine->uxIndex = uxIndex;
+		pxCoRoutine->pxCoRoutineFunction = pxCoRoutineCode;
+
+		/* Initialise all the other co-routine control block parameters. */
+		vListInitialiseItem( &( pxCoRoutine->xGenericListItem ) );
+		vListInitialiseItem( &( pxCoRoutine->xEventListItem ) );
+
+		/* Set the co-routine control block as a link back from the ListItem_t.
+		This is so we can get back to the containing CRCB from a generic item
+		in a list. */
+		listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xGenericListItem ), pxCoRoutine );
+		listSET_LIST_ITEM_OWNER( &( pxCoRoutine->xEventListItem ), pxCoRoutine );
+
+		/* Event lists are always in priority order. */
+		listSET_LIST_ITEM_VALUE( &( pxCoRoutine->xEventListItem ), ( ( TickType_t ) configMAX_CO_ROUTINE_PRIORITIES - ( TickType_t ) uxPriority ) );
+
+		/* Now the co-routine has been initialised it can be added to the ready
+		list at the correct priority. */
+		prvAddCoRoutineToReadyQueue( pxCoRoutine );
+
+		xReturn = pdPASS;
+	}
+	else
+	{
+		xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList )
+{
+TickType_t xTimeToWake;
+
+	/* Calculate the time to wake - this may overflow but this is
+	not a problem. */
+	xTimeToWake = xCoRoutineTickCount + xTicksToDelay;
+
+	/* We must remove ourselves from the ready list before adding
+	ourselves to the blocked list as the same list item is used for
+	both lists. */
+	( void ) uxListRemove( ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+
+	/* The list item will be inserted in wake time order. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentCoRoutine->xGenericListItem ), xTimeToWake );
+
+	if( xTimeToWake < xCoRoutineTickCount )
+	{
+		/* Wake time has overflowed.  Place this item in the
+		overflow list. */
+		vListInsert( ( List_t * ) pxOverflowDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+	}
+	else
+	{
+		/* The wake time has not overflowed, so we can use the
+		current block list. */
+		vListInsert( ( List_t * ) pxDelayedCoRoutineList, ( ListItem_t * ) &( pxCurrentCoRoutine->xGenericListItem ) );
+	}
+
+	if( pxEventList )
+	{
+		/* Also add the co-routine to an event list.  If this is done then the
+		function must be called with interrupts disabled. */
+		vListInsert( pxEventList, &( pxCurrentCoRoutine->xEventListItem ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckPendingReadyList( void )
+{
+	/* Are there any co-routines waiting to get moved to the ready list?  These
+	are co-routines that have been readied by an ISR.  The ISR cannot access
+	the	ready lists itself. */
+	while( listLIST_IS_EMPTY( &xPendingReadyCoRoutineList ) == pdFALSE )
+	{
+		CRCB_t *pxUnblockedCRCB;
+
+		/* The pending ready list can be accessed by an ISR. */
+		portDISABLE_INTERRUPTS();
+		{
+			pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( (&xPendingReadyCoRoutineList) );
+			( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
+		}
+		portENABLE_INTERRUPTS();
+
+		( void ) uxListRemove( &( pxUnblockedCRCB->xGenericListItem ) );
+		prvAddCoRoutineToReadyQueue( pxUnblockedCRCB );
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckDelayedList( void )
+{
+CRCB_t *pxCRCB;
+
+	xPassedTicks = xTaskGetTickCount() - xLastTickCount;
+	while( xPassedTicks )
+	{
+		xCoRoutineTickCount++;
+		xPassedTicks--;
+
+		/* If the tick count has overflowed we need to swap the ready lists. */
+		if( xCoRoutineTickCount == 0 )
+		{
+			List_t * pxTemp;
+
+			/* Tick count has overflowed so we need to swap the delay lists.  If there are
+			any items in pxDelayedCoRoutineList here then there is an error! */
+			pxTemp = pxDelayedCoRoutineList;
+			pxDelayedCoRoutineList = pxOverflowDelayedCoRoutineList;
+			pxOverflowDelayedCoRoutineList = pxTemp;
+		}
+
+		/* See if this tick has made a timeout expire. */
+		while( listLIST_IS_EMPTY( pxDelayedCoRoutineList ) == pdFALSE )
+		{
+			pxCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedCoRoutineList );
+
+			if( xCoRoutineTickCount < listGET_LIST_ITEM_VALUE( &( pxCRCB->xGenericListItem ) ) )
+			{
+				/* Timeout not yet expired. */
+				break;
+			}
+
+			portDISABLE_INTERRUPTS();
+			{
+				/* The event could have occurred just before this critical
+				section.  If this is the case then the generic list item will
+				have been moved to the pending ready list and the following
+				line is still valid.  Also the pvContainer parameter will have
+				been set to NULL so the following lines are also valid. */
+				( void ) uxListRemove( &( pxCRCB->xGenericListItem ) );
+
+				/* Is the co-routine waiting on an event also? */
+				if( pxCRCB->xEventListItem.pvContainer )
+				{
+					( void ) uxListRemove( &( pxCRCB->xEventListItem ) );
+				}
+			}
+			portENABLE_INTERRUPTS();
+
+			prvAddCoRoutineToReadyQueue( pxCRCB );
+		}
+	}
+
+	xLastTickCount = xCoRoutineTickCount;
+}
+/*-----------------------------------------------------------*/
+
+void vCoRoutineSchedule( void )
+{
+	/* See if any co-routines readied by events need moving to the ready lists. */
+	prvCheckPendingReadyList();
+
+	/* See if any delayed co-routines have timed out. */
+	prvCheckDelayedList();
+
+	/* Find the highest priority queue that contains ready co-routines. */
+	while( listLIST_IS_EMPTY( &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) ) )
+	{
+		if( uxTopCoRoutineReadyPriority == 0 )
+		{
+			/* No more co-routines to check. */
+			return;
+		}
+		--uxTopCoRoutineReadyPriority;
+	}
+
+	/* listGET_OWNER_OF_NEXT_ENTRY walks through the list, so the co-routines
+	 of the	same priority get an equal share of the processor time. */
+	listGET_OWNER_OF_NEXT_ENTRY( pxCurrentCoRoutine, &( pxReadyCoRoutineLists[ uxTopCoRoutineReadyPriority ] ) );
+
+	/* Call the co-routine. */
+	( pxCurrentCoRoutine->pxCoRoutineFunction )( pxCurrentCoRoutine, pxCurrentCoRoutine->uxIndex );
+
+	return;
+}
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseCoRoutineLists( void )
+{
+UBaseType_t uxPriority;
+
+	for( uxPriority = 0; uxPriority < configMAX_CO_ROUTINE_PRIORITIES; uxPriority++ )
+	{
+		vListInitialise( ( List_t * ) &( pxReadyCoRoutineLists[ uxPriority ] ) );
+	}
+
+	vListInitialise( ( List_t * ) &xDelayedCoRoutineList1 );
+	vListInitialise( ( List_t * ) &xDelayedCoRoutineList2 );
+	vListInitialise( ( List_t * ) &xPendingReadyCoRoutineList );
+
+	/* Start with pxDelayedCoRoutineList using list1 and the
+	pxOverflowDelayedCoRoutineList using list2. */
+	pxDelayedCoRoutineList = &xDelayedCoRoutineList1;
+	pxOverflowDelayedCoRoutineList = &xDelayedCoRoutineList2;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList )
+{
+CRCB_t *pxUnblockedCRCB;
+BaseType_t xReturn;
+
+	/* This function is called from within an interrupt.  It can only access
+	event lists and the pending ready list.  This function assumes that a
+	check has already been made to ensure pxEventList is not empty. */
+	pxUnblockedCRCB = ( CRCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
+	( void ) uxListRemove( &( pxUnblockedCRCB->xEventListItem ) );
+	vListInsertEnd( ( List_t * ) &( xPendingReadyCoRoutineList ), &( pxUnblockedCRCB->xEventListItem ) );
+
+	if( pxUnblockedCRCB->uxPriority >= pxCurrentCoRoutine->uxPriority )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+
+#endif /* configUSE_CO_ROUTINES == 0 */
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/croutine.h b/STM32F1/libraries/FreeRTOS900/utility/croutine.h
new file mode 100644
index 000000000..4f003a0ba
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/croutine.h
@@ -0,0 +1,762 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#ifndef CO_ROUTINE_H
+#define CO_ROUTINE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include croutine.h"
+#endif
+
+#include "list.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Used to hide the implementation of the co-routine control block.  The
+control block structure however has to be included in the header due to
+the macro implementation of the co-routine functionality. */
+typedef void * CoRoutineHandle_t;
+
+/* Defines the prototype to which co-routine functions must conform. */
+typedef void (*crCOROUTINE_CODE)( CoRoutineHandle_t, UBaseType_t );
+
+typedef struct corCoRoutineControlBlock
+{
+	crCOROUTINE_CODE 	pxCoRoutineFunction;
+	ListItem_t			xGenericListItem;	/*< List item used to place the CRCB in ready and blocked queues. */
+	ListItem_t			xEventListItem;		/*< List item used to place the CRCB in event lists. */
+	UBaseType_t 		uxPriority;			/*< The priority of the co-routine in relation to other co-routines. */
+	UBaseType_t 		uxIndex;			/*< Used to distinguish between co-routines when multiple co-routines use the same co-routine function. */
+	uint16_t 			uxState;			/*< Used internally by the co-routine implementation. */
+} CRCB_t; /* Co-routine control block.  Note must be identical in size down to uxPriority with TCB_t. */
+
+/**
+ * croutine. h
+ *<pre>
+ BaseType_t xCoRoutineCreate(
+                                 crCOROUTINE_CODE pxCoRoutineCode,
+                                 UBaseType_t uxPriority,
+                                 UBaseType_t uxIndex
+                               );</pre>
+ *
+ * Create a new co-routine and add it to the list of co-routines that are
+ * ready to run.
+ *
+ * @param pxCoRoutineCode Pointer to the co-routine function.  Co-routine
+ * functions require special syntax - see the co-routine section of the WEB
+ * documentation for more information.
+ *
+ * @param uxPriority The priority with respect to other co-routines at which
+ *  the co-routine will run.
+ *
+ * @param uxIndex Used to distinguish between different co-routines that
+ * execute the same function.  See the example below and the co-routine section
+ * of the WEB documentation for further information.
+ *
+ * @return pdPASS if the co-routine was successfully created and added to a ready
+ * list, otherwise an error code defined with ProjDefs.h.
+ *
+ * Example usage:
+   <pre>
+ // Co-routine to be created.
+ void vFlashCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ static const char cLedToFlash[ 2 ] = { 5, 6 };
+ static const TickType_t uxFlashRates[ 2 ] = { 200, 400 };
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // This co-routine just delays for a fixed period, then toggles
+         // an LED.  Two co-routines are created using this function, so
+         // the uxIndex parameter is used to tell the co-routine which
+         // LED to flash and how int32_t to delay.  This assumes xQueue has
+         // already been created.
+         vParTestToggleLED( cLedToFlash[ uxIndex ] );
+         crDELAY( xHandle, uxFlashRates[ uxIndex ] );
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }
+
+ // Function that creates two co-routines.
+ void vOtherFunction( void )
+ {
+ uint8_t ucParameterToPass;
+ TaskHandle_t xHandle;
+
+     // Create two co-routines at priority 0.  The first is given index 0
+     // so (from the code above) toggles LED 5 every 200 ticks.  The second
+     // is given index 1 so toggles LED 6 every 400 ticks.
+     for( uxIndex = 0; uxIndex < 2; uxIndex++ )
+     {
+         xCoRoutineCreate( vFlashCoRoutine, 0, uxIndex );
+     }
+ }
+   </pre>
+ * \defgroup xCoRoutineCreate xCoRoutineCreate
+ * \ingroup Tasks
+ */
+BaseType_t xCoRoutineCreate( crCOROUTINE_CODE pxCoRoutineCode, UBaseType_t uxPriority, UBaseType_t uxIndex );
+
+
+/**
+ * croutine. h
+ *<pre>
+ void vCoRoutineSchedule( void );</pre>
+ *
+ * Run a co-routine.
+ *
+ * vCoRoutineSchedule() executes the highest priority co-routine that is able
+ * to run.  The co-routine will execute until it either blocks, yields or is
+ * preempted by a task.  Co-routines execute cooperatively so one
+ * co-routine cannot be preempted by another, but can be preempted by a task.
+ *
+ * If an application comprises of both tasks and co-routines then
+ * vCoRoutineSchedule should be called from the idle task (in an idle task
+ * hook).
+ *
+ * Example usage:
+   <pre>
+ // This idle task hook will schedule a co-routine each time it is called.
+ // The rest of the idle task will execute between co-routine calls.
+ void vApplicationIdleHook( void )
+ {
+	vCoRoutineSchedule();
+ }
+
+ // Alternatively, if you do not require any other part of the idle task to
+ // execute, the idle task hook can call vCoRoutineScheduler() within an
+ // infinite loop.
+ void vApplicationIdleHook( void )
+ {
+    for( ;; )
+    {
+        vCoRoutineSchedule();
+    }
+ }
+ </pre>
+ * \defgroup vCoRoutineSchedule vCoRoutineSchedule
+ * \ingroup Tasks
+ */
+void vCoRoutineSchedule( void );
+
+/**
+ * croutine. h
+ * <pre>
+ crSTART( CoRoutineHandle_t xHandle );</pre>
+ *
+ * This macro MUST always be called at the start of a co-routine function.
+ *
+ * Example usage:
+   <pre>
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }</pre>
+ * \defgroup crSTART crSTART
+ * \ingroup Tasks
+ */
+#define crSTART( pxCRCB ) switch( ( ( CRCB_t * )( pxCRCB ) )->uxState ) { case 0:
+
+/**
+ * croutine. h
+ * <pre>
+ crEND();</pre>
+ *
+ * This macro MUST always be called at the end of a co-routine function.
+ *
+ * Example usage:
+   <pre>
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static int32_t ulAVariable;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+          // Co-routine functionality goes here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }</pre>
+ * \defgroup crSTART crSTART
+ * \ingroup Tasks
+ */
+#define crEND() }
+
+/*
+ * These macros are intended for internal use by the co-routine implementation
+ * only.  The macros should not be used directly by application writers.
+ */
+#define crSET_STATE0( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = (__LINE__ * 2); return; case (__LINE__ * 2):
+#define crSET_STATE1( xHandle ) ( ( CRCB_t * )( xHandle ) )->uxState = ((__LINE__ * 2)+1); return; case ((__LINE__ * 2)+1):
+
+/**
+ * croutine. h
+ *<pre>
+ crDELAY( CoRoutineHandle_t xHandle, TickType_t xTicksToDelay );</pre>
+ *
+ * Delay a co-routine for a fixed period of time.
+ *
+ * crDELAY can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function.  This is because
+ * co-routines do not maintain their own stack.
+ *
+ * @param xHandle The handle of the co-routine to delay.  This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should delay
+ * for.  The actual amount of time this equates to is defined by
+ * configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant portTICK_PERIOD_MS
+ * can be used to convert ticks to milliseconds.
+ *
+ * Example usage:
+   <pre>
+ // Co-routine to be created.
+ void vACoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ // This may not be necessary for const variables.
+ // We are to delay for 200ms.
+ static const xTickType xDelayTime = 200 / portTICK_PERIOD_MS;
+
+     // Must start every co-routine with a call to crSTART();
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+        // Delay for 200ms.
+        crDELAY( xHandle, xDelayTime );
+
+        // Do something here.
+     }
+
+     // Must end every co-routine with a call to crEND();
+     crEND();
+ }</pre>
+ * \defgroup crDELAY crDELAY
+ * \ingroup Tasks
+ */
+#define crDELAY( xHandle, xTicksToDelay )												\
+	if( ( xTicksToDelay ) > 0 )															\
+	{																					\
+		vCoRoutineAddToDelayedList( ( xTicksToDelay ), NULL );							\
+	}																					\
+	crSET_STATE0( ( xHandle ) );
+
+/**
+ * <pre>
+ crQUEUE_SEND(
+                  CoRoutineHandle_t xHandle,
+                  QueueHandle_t pxQueue,
+                  void *pvItemToQueue,
+                  TickType_t xTicksToWait,
+                  BaseType_t *pxResult
+             )</pre>
+ *
+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
+ *
+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
+ * xQueueSend() and xQueueReceive() can only be used from tasks.
+ *
+ * crQUEUE_SEND can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function.  This is because
+ * co-routines do not maintain their own stack.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xHandle The handle of the calling co-routine.  This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param pxQueue The handle of the queue on which the data will be posted.
+ * The handle is obtained as the return value when the queue is created using
+ * the xQueueCreate() API function.
+ *
+ * @param pvItemToQueue A pointer to the data being posted onto the queue.
+ * The number of bytes of each queued item is specified when the queue is
+ * created.  This number of bytes is copied from pvItemToQueue into the queue
+ * itself.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should block
+ * to wait for space to become available on the queue, should space not be
+ * available immediately. The actual amount of time this equates to is defined
+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant
+ * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see example
+ * below).
+ *
+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
+ * data was successfully posted onto the queue, otherwise it will be set to an
+ * error defined within ProjDefs.h.
+ *
+ * Example usage:
+   <pre>
+ // Co-routine function that blocks for a fixed period then posts a number onto
+ // a queue.
+ static void prvCoRoutineFlashTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xNumberToPost = 0;
+ static BaseType_t xResult;
+
+    // Co-routines must begin with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // This assumes the queue has already been created.
+        crQUEUE_SEND( xHandle, xCoRoutineQueue, &xNumberToPost, NO_DELAY, &xResult );
+
+        if( xResult != pdPASS )
+        {
+            // The message was not posted!
+        }
+
+        // Increment the number to be posted onto the queue.
+        xNumberToPost++;
+
+        // Delay for 100 ticks.
+        crDELAY( xHandle, 100 );
+    }
+
+    // Co-routines must end with a call to crEND().
+    crEND();
+ }</pre>
+ * \defgroup crQUEUE_SEND crQUEUE_SEND
+ * \ingroup Tasks
+ */
+#define crQUEUE_SEND( xHandle, pxQueue, pvItemToQueue, xTicksToWait, pxResult )			\
+{																						\
+	*( pxResult ) = xQueueCRSend( ( pxQueue) , ( pvItemToQueue) , ( xTicksToWait ) );	\
+	if( *( pxResult ) == errQUEUE_BLOCKED )												\
+	{																					\
+		crSET_STATE0( ( xHandle ) );													\
+		*pxResult = xQueueCRSend( ( pxQueue ), ( pvItemToQueue ), 0 );					\
+	}																					\
+	if( *pxResult == errQUEUE_YIELD )													\
+	{																					\
+		crSET_STATE1( ( xHandle ) );													\
+		*pxResult = pdPASS;																\
+	}																					\
+}
+
+/**
+ * croutine. h
+ * <pre>
+  crQUEUE_RECEIVE(
+                     CoRoutineHandle_t xHandle,
+                     QueueHandle_t pxQueue,
+                     void *pvBuffer,
+                     TickType_t xTicksToWait,
+                     BaseType_t *pxResult
+                 )</pre>
+ *
+ * The macro's crQUEUE_SEND() and crQUEUE_RECEIVE() are the co-routine
+ * equivalent to the xQueueSend() and xQueueReceive() functions used by tasks.
+ *
+ * crQUEUE_SEND and crQUEUE_RECEIVE can only be used from a co-routine whereas
+ * xQueueSend() and xQueueReceive() can only be used from tasks.
+ *
+ * crQUEUE_RECEIVE can only be called from the co-routine function itself - not
+ * from within a function called by the co-routine function.  This is because
+ * co-routines do not maintain their own stack.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xHandle The handle of the calling co-routine.  This is the xHandle
+ * parameter of the co-routine function.
+ *
+ * @param pxQueue The handle of the queue from which the data will be received.
+ * The handle is obtained as the return value when the queue is created using
+ * the xQueueCreate() API function.
+ *
+ * @param pvBuffer The buffer into which the received item is to be copied.
+ * The number of bytes of each queued item is specified when the queue is
+ * created.  This number of bytes is copied into pvBuffer.
+ *
+ * @param xTickToDelay The number of ticks that the co-routine should block
+ * to wait for data to become available from the queue, should data not be
+ * available immediately. The actual amount of time this equates to is defined
+ * by configTICK_RATE_HZ (set in FreeRTOSConfig.h).  The constant
+ * portTICK_PERIOD_MS can be used to convert ticks to milliseconds (see the
+ * crQUEUE_SEND example).
+ *
+ * @param pxResult The variable pointed to by pxResult will be set to pdPASS if
+ * data was successfully retrieved from the queue, otherwise it will be set to
+ * an error code as defined within ProjDefs.h.
+ *
+ * Example usage:
+ <pre>
+ // A co-routine receives the number of an LED to flash from a queue.  It
+ // blocks on the queue until the number is received.
+ static void prvCoRoutineFlashWorkTask( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // Variables in co-routines must be declared static if they must maintain value across a blocking call.
+ static BaseType_t xResult;
+ static UBaseType_t uxLEDToFlash;
+
+    // All co-routines must start with a call to crSTART().
+    crSTART( xHandle );
+
+    for( ;; )
+    {
+        // Wait for data to become available on the queue.
+        crQUEUE_RECEIVE( xHandle, xCoRoutineQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+        if( xResult == pdPASS )
+        {
+            // We received the LED to flash - flash it!
+            vParTestToggleLED( uxLEDToFlash );
+        }
+    }
+
+    crEND();
+ }</pre>
+ * \defgroup crQUEUE_RECEIVE crQUEUE_RECEIVE
+ * \ingroup Tasks
+ */
+#define crQUEUE_RECEIVE( xHandle, pxQueue, pvBuffer, xTicksToWait, pxResult )			\
+{																						\
+	*( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), ( xTicksToWait ) );		\
+	if( *( pxResult ) == errQUEUE_BLOCKED ) 											\
+	{																					\
+		crSET_STATE0( ( xHandle ) );													\
+		*( pxResult ) = xQueueCRReceive( ( pxQueue) , ( pvBuffer ), 0 );				\
+	}																					\
+	if( *( pxResult ) == errQUEUE_YIELD )												\
+	{																					\
+		crSET_STATE1( ( xHandle ) );													\
+		*( pxResult ) = pdPASS;															\
+	}																					\
+}
+
+/**
+ * croutine. h
+ * <pre>
+  crQUEUE_SEND_FROM_ISR(
+                            QueueHandle_t pxQueue,
+                            void *pvItemToQueue,
+                            BaseType_t xCoRoutinePreviouslyWoken
+                       )</pre>
+ *
+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
+ * functions used by tasks.
+ *
+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
+ * xQueueReceiveFromISR() can only be used to pass data between a task and and
+ * ISR.
+ *
+ * crQUEUE_SEND_FROM_ISR can only be called from an ISR to send data to a queue
+ * that is being used from within a co-routine.
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xCoRoutinePreviouslyWoken This is included so an ISR can post onto
+ * the same queue multiple times from a single interrupt.  The first call
+ * should always pass in pdFALSE.  Subsequent calls should pass in
+ * the value returned from the previous call.
+ *
+ * @return pdTRUE if a co-routine was woken by posting onto the queue.  This is
+ * used by the ISR to determine if a context switch may be required following
+ * the ISR.
+ *
+ * Example usage:
+ <pre>
+ // A co-routine that blocks on a queue waiting for characters to be received.
+ static void vReceivingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ char cRxedChar;
+ BaseType_t xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Wait for data to become available on the queue.  This assumes the
+         // queue xCommsRxQueue has already been created!
+         crQUEUE_RECEIVE( xHandle, xCommsRxQueue, &uxLEDToFlash, portMAX_DELAY, &xResult );
+
+         // Was a character received?
+         if( xResult == pdPASS )
+         {
+             // Process the character here.
+         }
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to send characters received on a serial port to
+ // a co-routine.
+ void vUART_ISR( void )
+ {
+ char cRxedChar;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+     // We loop around reading characters until there are none left in the UART.
+     while( UART_RX_REG_NOT_EMPTY() )
+     {
+         // Obtain the character from the UART.
+         cRxedChar = UART_RX_REG;
+
+         // Post the character onto a queue.  xCRWokenByPost will be pdFALSE
+         // the first time around the loop.  If the post causes a co-routine
+         // to be woken (unblocked) then xCRWokenByPost will be set to pdTRUE.
+         // In this manner we can ensure that if more than one co-routine is
+         // blocked on the queue only one is woken by this ISR no matter how
+         // many characters are posted to the queue.
+         xCRWokenByPost = crQUEUE_SEND_FROM_ISR( xCommsRxQueue, &cRxedChar, xCRWokenByPost );
+     }
+ }</pre>
+ * \defgroup crQUEUE_SEND_FROM_ISR crQUEUE_SEND_FROM_ISR
+ * \ingroup Tasks
+ */
+#define crQUEUE_SEND_FROM_ISR( pxQueue, pvItemToQueue, xCoRoutinePreviouslyWoken ) xQueueCRSendFromISR( ( pxQueue ), ( pvItemToQueue ), ( xCoRoutinePreviouslyWoken ) )
+
+
+/**
+ * croutine. h
+ * <pre>
+  crQUEUE_SEND_FROM_ISR(
+                            QueueHandle_t pxQueue,
+                            void *pvBuffer,
+                            BaseType_t * pxCoRoutineWoken
+                       )</pre>
+ *
+ * The macro's crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() are the
+ * co-routine equivalent to the xQueueSendFromISR() and xQueueReceiveFromISR()
+ * functions used by tasks.
+ *
+ * crQUEUE_SEND_FROM_ISR() and crQUEUE_RECEIVE_FROM_ISR() can only be used to
+ * pass data between a co-routine and and ISR, whereas xQueueSendFromISR() and
+ * xQueueReceiveFromISR() can only be used to pass data between a task and and
+ * ISR.
+ *
+ * crQUEUE_RECEIVE_FROM_ISR can only be called from an ISR to receive data
+ * from a queue that is being used from within a co-routine (a co-routine
+ * posted to the queue).
+ *
+ * See the co-routine section of the WEB documentation for information on
+ * passing data between tasks and co-routines and between ISR's and
+ * co-routines.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvBuffer A pointer to a buffer into which the received item will be
+ * placed.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from the queue into
+ * pvBuffer.
+ *
+ * @param pxCoRoutineWoken A co-routine may be blocked waiting for space to become
+ * available on the queue.  If crQUEUE_RECEIVE_FROM_ISR causes such a
+ * co-routine to unblock *pxCoRoutineWoken will get set to pdTRUE, otherwise
+ * *pxCoRoutineWoken will remain unchanged.
+ *
+ * @return pdTRUE an item was successfully received from the queue, otherwise
+ * pdFALSE.
+ *
+ * Example usage:
+ <pre>
+ // A co-routine that posts a character to a queue then blocks for a fixed
+ // period.  The character is incremented each time.
+ static void vSendingCoRoutine( CoRoutineHandle_t xHandle, UBaseType_t uxIndex )
+ {
+ // cChar holds its value while this co-routine is blocked and must therefore
+ // be declared static.
+ static char cCharToTx = 'a';
+ BaseType_t xResult;
+
+     // All co-routines must start with a call to crSTART().
+     crSTART( xHandle );
+
+     for( ;; )
+     {
+         // Send the next character to the queue.
+         crQUEUE_SEND( xHandle, xCoRoutineQueue, &cCharToTx, NO_DELAY, &xResult );
+
+         if( xResult == pdPASS )
+         {
+             // The character was successfully posted to the queue.
+         }
+		 else
+		 {
+			// Could not post the character to the queue.
+		 }
+
+         // Enable the UART Tx interrupt to cause an interrupt in this
+		 // hypothetical UART.  The interrupt will obtain the character
+		 // from the queue and send it.
+		 ENABLE_RX_INTERRUPT();
+
+		 // Increment to the next character then block for a fixed period.
+		 // cCharToTx will maintain its value across the delay as it is
+		 // declared static.
+		 cCharToTx++;
+		 if( cCharToTx > 'x' )
+		 {
+			cCharToTx = 'a';
+		 }
+		 crDELAY( 100 );
+     }
+
+     // All co-routines must end with a call to crEND().
+     crEND();
+ }
+
+ // An ISR that uses a queue to receive characters to send on a UART.
+ void vUART_ISR( void )
+ {
+ char cCharToTx;
+ BaseType_t xCRWokenByPost = pdFALSE;
+
+     while( UART_TX_REG_EMPTY() )
+     {
+         // Are there any characters in the queue waiting to be sent?
+		 // xCRWokenByPost will automatically be set to pdTRUE if a co-routine
+		 // is woken by the post - ensuring that only a single co-routine is
+		 // woken no matter how many times we go around this loop.
+         if( crQUEUE_RECEIVE_FROM_ISR( pxQueue, &cCharToTx, &xCRWokenByPost ) )
+		 {
+			 SEND_CHARACTER( cCharToTx );
+		 }
+     }
+ }</pre>
+ * \defgroup crQUEUE_RECEIVE_FROM_ISR crQUEUE_RECEIVE_FROM_ISR
+ * \ingroup Tasks
+ */
+#define crQUEUE_RECEIVE_FROM_ISR( pxQueue, pvBuffer, pxCoRoutineWoken ) xQueueCRReceiveFromISR( ( pxQueue ), ( pvBuffer ), ( pxCoRoutineWoken ) )
+
+/*
+ * This function is intended for internal use by the co-routine macros only.
+ * The macro nature of the co-routine implementation requires that the
+ * prototype appears here.  The function should not be used by application
+ * writers.
+ *
+ * Removes the current co-routine from its ready list and places it in the
+ * appropriate delayed list.
+ */
+void vCoRoutineAddToDelayedList( TickType_t xTicksToDelay, List_t *pxEventList );
+
+/*
+ * This function is intended for internal use by the queue implementation only.
+ * The function should not be used by application writers.
+ *
+ * Removes the highest priority co-routine from the event list and places it in
+ * the pending ready list.
+ */
+BaseType_t xCoRoutineRemoveFromEventList( const List_t *pxEventList );
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* CO_ROUTINE_H */
diff --git a/STM32F1/libraries/FreeRTOS900/utility/deprecated_definitions.h b/STM32F1/libraries/FreeRTOS900/utility/deprecated_definitions.h
new file mode 100644
index 000000000..7c6721c6c
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/deprecated_definitions.h
@@ -0,0 +1,321 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#ifndef DEPRECATED_DEFINITIONS_H
+#define DEPRECATED_DEFINITIONS_H
+
+
+/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
+pre-processor definition was used to ensure the pre-processor found the correct
+portmacro.h file for the port being used.  That scheme was deprecated in favour
+of setting the compiler's include path such that it found the correct
+portmacro.h file - removing the need for the constant and allowing the
+portmacro.h file to be located anywhere in relation to the port being used.  The
+definitions below remain in the code for backward compatibility only.  New
+projects should not use them. */
+
+#ifdef OPEN_WATCOM_INDUSTRIAL_PC_PORT
+	#include "..\..\Source\portable\owatcom\16bitdos\pc\portmacro.h"
+	typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef OPEN_WATCOM_FLASH_LITE_186_PORT
+	#include "..\..\Source\portable\owatcom\16bitdos\flsh186\portmacro.h"
+	typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef GCC_MEGA_AVR
+	#include "../portable/GCC/ATMega323/portmacro.h"
+#endif
+
+#ifdef IAR_MEGA_AVR
+	#include "../portable/IAR/ATMega323/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC24_PORT
+	#include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
+#endif
+
+#ifdef MPLAB_DSPIC_PORT
+	#include "../../Source/portable/MPLAB/PIC24_dsPIC/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC18F_PORT
+	#include "../../Source/portable/MPLAB/PIC18F/portmacro.h"
+#endif
+
+#ifdef MPLAB_PIC32MX_PORT
+	#include "../../Source/portable/MPLAB/PIC32MX/portmacro.h"
+#endif
+
+#ifdef _FEDPICC
+	#include "libFreeRTOS/Include/portmacro.h"
+#endif
+
+#ifdef SDCC_CYGNAL
+	#include "../../Source/portable/SDCC/Cygnal/portmacro.h"
+#endif
+
+#ifdef GCC_ARM7
+	#include "../../Source/portable/GCC/ARM7_LPC2000/portmacro.h"
+#endif
+
+#ifdef GCC_ARM7_ECLIPSE
+	#include "portmacro.h"
+#endif
+
+#ifdef ROWLEY_LPC23xx
+	#include "../../Source/portable/GCC/ARM7_LPC23xx/portmacro.h"
+#endif
+
+#ifdef IAR_MSP430
+	#include "..\..\Source\portable\IAR\MSP430\portmacro.h"
+#endif
+
+#ifdef GCC_MSP430
+	#include "../../Source/portable/GCC/MSP430F449/portmacro.h"
+#endif
+
+#ifdef ROWLEY_MSP430
+	#include "../../Source/portable/Rowley/MSP430F449/portmacro.h"
+#endif
+
+#ifdef ARM7_LPC21xx_KEIL_RVDS
+	#include "..\..\Source\portable\RVDS\ARM7_LPC21xx\portmacro.h"
+#endif
+
+#ifdef SAM7_GCC
+	#include "../../Source/portable/GCC/ARM7_AT91SAM7S/portmacro.h"
+#endif
+
+#ifdef SAM7_IAR
+	#include "..\..\Source\portable\IAR\AtmelSAM7S64\portmacro.h"
+#endif
+
+#ifdef SAM9XE_IAR
+	#include "..\..\Source\portable\IAR\AtmelSAM9XE\portmacro.h"
+#endif
+
+#ifdef LPC2000_IAR
+	#include "..\..\Source\portable\IAR\LPC2000\portmacro.h"
+#endif
+
+#ifdef STR71X_IAR
+	#include "..\..\Source\portable\IAR\STR71x\portmacro.h"
+#endif
+
+#ifdef STR75X_IAR
+	#include "..\..\Source\portable\IAR\STR75x\portmacro.h"
+#endif
+
+#ifdef STR75X_GCC
+	#include "..\..\Source\portable\GCC\STR75x\portmacro.h"
+#endif
+
+#ifdef STR91X_IAR
+	#include "..\..\Source\portable\IAR\STR91x\portmacro.h"
+#endif
+
+#ifdef GCC_H8S
+	#include "../../Source/portable/GCC/H8S2329/portmacro.h"
+#endif
+
+#ifdef GCC_AT91FR40008
+	#include "../../Source/portable/GCC/ARM7_AT91FR40008/portmacro.h"
+#endif
+
+#ifdef RVDS_ARMCM3_LM3S102
+	#include "../../Source/portable/RVDS/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef GCC_ARMCM3_LM3S102
+	#include "../../Source/portable/GCC/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef GCC_ARMCM3
+	#include "portmacro.h"
+#endif
+
+#ifdef IAR_ARM_CM3
+	#include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef IAR_ARMCM3_LM
+	#include "../../Source/portable/IAR/ARM_CM3/portmacro.h"
+#endif
+
+#ifdef HCS12_CODE_WARRIOR
+	#include "../../Source/portable/CodeWarrior/HCS12/portmacro.h"
+#endif
+
+#ifdef MICROBLAZE_GCC
+	#include "../../Source/portable/GCC/MicroBlaze/portmacro.h"
+#endif
+
+#ifdef TERN_EE
+	#include "..\..\Source\portable\Paradigm\Tern_EE\small\portmacro.h"
+#endif
+
+#ifdef GCC_HCS12
+	#include "../../Source/portable/GCC/HCS12/portmacro.h"
+#endif
+
+#ifdef GCC_MCF5235
+    #include "../../Source/portable/GCC/MCF5235/portmacro.h"
+#endif
+
+#ifdef COLDFIRE_V2_GCC
+	#include "../../../Source/portable/GCC/ColdFire_V2/portmacro.h"
+#endif
+
+#ifdef COLDFIRE_V2_CODEWARRIOR
+	#include "../../Source/portable/CodeWarrior/ColdFire_V2/portmacro.h"
+#endif
+
+#ifdef GCC_PPC405
+	#include "../../Source/portable/GCC/PPC405_Xilinx/portmacro.h"
+#endif
+
+#ifdef GCC_PPC440
+	#include "../../Source/portable/GCC/PPC440_Xilinx/portmacro.h"
+#endif
+
+#ifdef _16FX_SOFTUNE
+	#include "..\..\Source\portable\Softune\MB96340\portmacro.h"
+#endif
+
+#ifdef BCC_INDUSTRIAL_PC_PORT
+	/* A short file name has to be used in place of the normal
+	FreeRTOSConfig.h when using the Borland compiler. */
+	#include "frconfig.h"
+	#include "..\portable\BCC\16BitDOS\PC\prtmacro.h"
+    typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef BCC_FLASH_LITE_186_PORT
+	/* A short file name has to be used in place of the normal
+	FreeRTOSConfig.h when using the Borland compiler. */
+	#include "frconfig.h"
+	#include "..\portable\BCC\16BitDOS\flsh186\prtmacro.h"
+    typedef void ( __interrupt __far *pxISR )();
+#endif
+
+#ifdef __GNUC__
+   #ifdef __AVR32_AVR32A__
+	   #include "portmacro.h"
+   #endif
+#endif
+
+#ifdef __ICCAVR32__
+   #ifdef __CORE__
+      #if __CORE__ == __AVR32A__
+	      #include "portmacro.h"
+      #endif
+   #endif
+#endif
+
+#ifdef __91467D
+	#include "portmacro.h"
+#endif
+
+#ifdef __96340
+	#include "portmacro.h"
+#endif
+
+
+#ifdef __IAR_V850ES_Fx3__
+	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx3__
+	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx3_L__
+	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Jx2__
+	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_V850ES_Hx2__
+	#include "../../Source/portable/IAR/V850ES/portmacro.h"
+#endif
+
+#ifdef __IAR_78K0R_Kx3__
+	#include "../../Source/portable/IAR/78K0R/portmacro.h"
+#endif
+
+#ifdef __IAR_78K0R_Kx3L__
+	#include "../../Source/portable/IAR/78K0R/portmacro.h"
+#endif
+
+#endif /* DEPRECATED_DEFINITIONS_H */
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/event_groups.c b/STM32F1/libraries/FreeRTOS900/utility/event_groups.c
new file mode 100644
index 000000000..b8df5fd95
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/event_groups.c
@@ -0,0 +1,752 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "event_groups.h"
+
+/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
+MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
+header files above, but not in this file, in order to generate the correct
+privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+
+/* The following bit fields convey control information in a task's event list
+item value.  It is important they don't clash with the
+taskEVENT_LIST_ITEM_VALUE_IN_USE definition. */
+#if configUSE_16_BIT_TICKS == 1
+	#define eventCLEAR_EVENTS_ON_EXIT_BIT	0x0100U
+	#define eventUNBLOCKED_DUE_TO_BIT_SET	0x0200U
+	#define eventWAIT_FOR_ALL_BITS			0x0400U
+	#define eventEVENT_BITS_CONTROL_BYTES	0xff00U
+#else
+	#define eventCLEAR_EVENTS_ON_EXIT_BIT	0x01000000UL
+	#define eventUNBLOCKED_DUE_TO_BIT_SET	0x02000000UL
+	#define eventWAIT_FOR_ALL_BITS			0x04000000UL
+	#define eventEVENT_BITS_CONTROL_BYTES	0xff000000UL
+#endif
+
+typedef struct xEventGroupDefinition
+{
+	EventBits_t uxEventBits;
+	List_t xTasksWaitingForBits;		/*< List of tasks waiting for a bit to be set. */
+
+	#if( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxEventGroupNumber;
+	#endif
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+		uint8_t ucStaticallyAllocated; /*< Set to pdTRUE if the event group is statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+} EventGroup_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Test the bits set in uxCurrentEventBits to see if the wait condition is met.
+ * The wait condition is defined by xWaitForAllBits.  If xWaitForAllBits is
+ * pdTRUE then the wait condition is met if all the bits set in uxBitsToWaitFor
+ * are also set in uxCurrentEventBits.  If xWaitForAllBits is pdFALSE then the
+ * wait condition is met if any of the bits set in uxBitsToWait for are also set
+ * in uxCurrentEventBits.
+ */
+static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer )
+	{
+	EventGroup_t *pxEventBits;
+
+		/* A StaticEventGroup_t object must be provided. */
+		configASSERT( pxEventGroupBuffer );
+
+		/* The user has provided a statically allocated event group - use it. */
+		pxEventBits = ( EventGroup_t * ) pxEventGroupBuffer; /*lint !e740 EventGroup_t and StaticEventGroup_t are guaranteed to have the same size and alignment requirement - checked by configASSERT(). */
+
+		if( pxEventBits != NULL )
+		{
+			pxEventBits->uxEventBits = 0;
+			vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
+
+			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+			{
+				/* Both static and dynamic allocation can be used, so note that
+				this event group was created statically in case the event group
+				is later deleted. */
+				pxEventBits->ucStaticallyAllocated = pdTRUE;
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+			traceEVENT_GROUP_CREATE( pxEventBits );
+		}
+		else
+		{
+			traceEVENT_GROUP_CREATE_FAILED();
+		}
+
+		return ( EventGroupHandle_t ) pxEventBits;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	EventGroupHandle_t xEventGroupCreate( void )
+	{
+	EventGroup_t *pxEventBits;
+
+		/* Allocate the event group. */
+		pxEventBits = ( EventGroup_t * ) pvPortMalloc( sizeof( EventGroup_t ) );
+
+		if( pxEventBits != NULL )
+		{
+			pxEventBits->uxEventBits = 0;
+			vListInitialise( &( pxEventBits->xTasksWaitingForBits ) );
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* Both static and dynamic allocation can be used, so note this
+				event group was allocated statically in case the event group is
+				later deleted. */
+				pxEventBits->ucStaticallyAllocated = pdFALSE;
+			}
+			#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+			traceEVENT_GROUP_CREATE( pxEventBits );
+		}
+		else
+		{
+			traceEVENT_GROUP_CREATE_FAILED();
+		}
+
+		return ( EventGroupHandle_t ) pxEventBits;
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait )
+{
+EventBits_t uxOriginalBitValue, uxReturn;
+EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
+BaseType_t xAlreadyYielded;
+BaseType_t xTimeoutOccurred = pdFALSE;
+
+	configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+	configASSERT( uxBitsToWaitFor != 0 );
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+	vTaskSuspendAll();
+	{
+		uxOriginalBitValue = pxEventBits->uxEventBits;
+
+		( void ) xEventGroupSetBits( xEventGroup, uxBitsToSet );
+
+		if( ( ( uxOriginalBitValue | uxBitsToSet ) & uxBitsToWaitFor ) == uxBitsToWaitFor )
+		{
+			/* All the rendezvous bits are now set - no need to block. */
+			uxReturn = ( uxOriginalBitValue | uxBitsToSet );
+
+			/* Rendezvous always clear the bits.  They will have been cleared
+			already unless this is the only task in the rendezvous. */
+			pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+
+			xTicksToWait = 0;
+		}
+		else
+		{
+			if( xTicksToWait != ( TickType_t ) 0 )
+			{
+				traceEVENT_GROUP_SYNC_BLOCK( xEventGroup, uxBitsToSet, uxBitsToWaitFor );
+
+				/* Store the bits that the calling task is waiting for in the
+				task's event list item so the kernel knows when a match is
+				found.  Then enter the blocked state. */
+				vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | eventCLEAR_EVENTS_ON_EXIT_BIT | eventWAIT_FOR_ALL_BITS ), xTicksToWait );
+
+				/* This assignment is obsolete as uxReturn will get set after
+				the task unblocks, but some compilers mistakenly generate a
+				warning about uxReturn being returned without being set if the
+				assignment is omitted. */
+				uxReturn = 0;
+			}
+			else
+			{
+				/* The rendezvous bits were not set, but no block time was
+				specified - just return the current event bit value. */
+				uxReturn = pxEventBits->uxEventBits;
+			}
+		}
+	}
+	xAlreadyYielded = xTaskResumeAll();
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* The task blocked to wait for its required bits to be set - at this
+		point either the required bits were set or the block time expired.  If
+		the required bits were set they will have been stored in the task's
+		event list item, and they should now be retrieved then cleared. */
+		uxReturn = uxTaskResetEventItemValue();
+
+		if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
+		{
+			/* The task timed out, just return the current event bit value. */
+			taskENTER_CRITICAL();
+			{
+				uxReturn = pxEventBits->uxEventBits;
+
+				/* Although the task got here because it timed out before the
+				bits it was waiting for were set, it is possible that since it
+				unblocked another task has set the bits.  If this is the case
+				then it needs to clear the bits before exiting. */
+				if( ( uxReturn & uxBitsToWaitFor ) == uxBitsToWaitFor )
+				{
+					pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			taskEXIT_CRITICAL();
+
+			xTimeoutOccurred = pdTRUE;
+		}
+		else
+		{
+			/* The task unblocked because the bits were set. */
+		}
+
+		/* Control bits might be set as the task had blocked should not be
+		returned. */
+		uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
+	}
+
+	traceEVENT_GROUP_SYNC_END( xEventGroup, uxBitsToSet, uxBitsToWaitFor, xTimeoutOccurred );
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait )
+{
+EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
+EventBits_t uxReturn, uxControlBits = 0;
+BaseType_t xWaitConditionMet, xAlreadyYielded;
+BaseType_t xTimeoutOccurred = pdFALSE;
+
+	/* Check the user is not attempting to wait on the bits used by the kernel
+	itself, and that at least one bit is being requested. */
+	configASSERT( xEventGroup );
+	configASSERT( ( uxBitsToWaitFor & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+	configASSERT( uxBitsToWaitFor != 0 );
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+	vTaskSuspendAll();
+	{
+		const EventBits_t uxCurrentEventBits = pxEventBits->uxEventBits;
+
+		/* Check to see if the wait condition is already met or not. */
+		xWaitConditionMet = prvTestWaitCondition( uxCurrentEventBits, uxBitsToWaitFor, xWaitForAllBits );
+
+		if( xWaitConditionMet != pdFALSE )
+		{
+			/* The wait condition has already been met so there is no need to
+			block. */
+			uxReturn = uxCurrentEventBits;
+			xTicksToWait = ( TickType_t ) 0;
+
+			/* Clear the wait bits if requested to do so. */
+			if( xClearOnExit != pdFALSE )
+			{
+				pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else if( xTicksToWait == ( TickType_t ) 0 )
+		{
+			/* The wait condition has not been met, but no block time was
+			specified, so just return the current value. */
+			uxReturn = uxCurrentEventBits;
+		}
+		else
+		{
+			/* The task is going to block to wait for its required bits to be
+			set.  uxControlBits are used to remember the specified behaviour of
+			this call to xEventGroupWaitBits() - for use when the event bits
+			unblock the task. */
+			if( xClearOnExit != pdFALSE )
+			{
+				uxControlBits |= eventCLEAR_EVENTS_ON_EXIT_BIT;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			if( xWaitForAllBits != pdFALSE )
+			{
+				uxControlBits |= eventWAIT_FOR_ALL_BITS;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Store the bits that the calling task is waiting for in the
+			task's event list item so the kernel knows when a match is
+			found.  Then enter the blocked state. */
+			vTaskPlaceOnUnorderedEventList( &( pxEventBits->xTasksWaitingForBits ), ( uxBitsToWaitFor | uxControlBits ), xTicksToWait );
+
+			/* This is obsolete as it will get set after the task unblocks, but
+			some compilers mistakenly generate a warning about the variable
+			being returned without being set if it is not done. */
+			uxReturn = 0;
+
+			traceEVENT_GROUP_WAIT_BITS_BLOCK( xEventGroup, uxBitsToWaitFor );
+		}
+	}
+	xAlreadyYielded = xTaskResumeAll();
+
+	if( xTicksToWait != ( TickType_t ) 0 )
+	{
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* The task blocked to wait for its required bits to be set - at this
+		point either the required bits were set or the block time expired.  If
+		the required bits were set they will have been stored in the task's
+		event list item, and they should now be retrieved then cleared. */
+		uxReturn = uxTaskResetEventItemValue();
+
+		if( ( uxReturn & eventUNBLOCKED_DUE_TO_BIT_SET ) == ( EventBits_t ) 0 )
+		{
+			taskENTER_CRITICAL();
+			{
+				/* The task timed out, just return the current event bit value. */
+				uxReturn = pxEventBits->uxEventBits;
+
+				/* It is possible that the event bits were updated between this
+				task leaving the Blocked state and running again. */
+				if( prvTestWaitCondition( uxReturn, uxBitsToWaitFor, xWaitForAllBits ) != pdFALSE )
+				{
+					if( xClearOnExit != pdFALSE )
+					{
+						pxEventBits->uxEventBits &= ~uxBitsToWaitFor;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			taskEXIT_CRITICAL();
+
+			/* Prevent compiler warnings when trace macros are not used. */
+			xTimeoutOccurred = pdFALSE;
+		}
+		else
+		{
+			/* The task unblocked because the bits were set. */
+		}
+
+		/* The task blocked so control bits may have been set. */
+		uxReturn &= ~eventEVENT_BITS_CONTROL_BYTES;
+	}
+	traceEVENT_GROUP_WAIT_BITS_END( xEventGroup, uxBitsToWaitFor, xTimeoutOccurred );
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )
+{
+EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
+EventBits_t uxReturn;
+
+	/* Check the user is not attempting to clear the bits used by the kernel
+	itself. */
+	configASSERT( xEventGroup );
+	configASSERT( ( uxBitsToClear & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+
+	taskENTER_CRITICAL();
+	{
+		traceEVENT_GROUP_CLEAR_BITS( xEventGroup, uxBitsToClear );
+
+		/* The value returned is the event group value prior to the bits being
+		cleared. */
+		uxReturn = pxEventBits->uxEventBits;
+
+		/* Clear the bits. */
+		pxEventBits->uxEventBits &= ~uxBitsToClear;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+
+	BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear )
+	{
+		BaseType_t xReturn;
+
+		traceEVENT_GROUP_CLEAR_BITS_FROM_ISR( xEventGroup, uxBitsToClear );
+		xReturn = xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL );
+
+		return xReturn;
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup )
+{
+UBaseType_t uxSavedInterruptStatus;
+EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
+EventBits_t uxReturn;
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		uxReturn = pxEventBits->uxEventBits;
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet )
+{
+ListItem_t *pxListItem, *pxNext;
+ListItem_t const *pxListEnd;
+List_t *pxList;
+EventBits_t uxBitsToClear = 0, uxBitsWaitedFor, uxControlBits;
+EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
+BaseType_t xMatchFound = pdFALSE;
+
+	/* Check the user is not attempting to set the bits used by the kernel
+	itself. */
+	configASSERT( xEventGroup );
+	configASSERT( ( uxBitsToSet & eventEVENT_BITS_CONTROL_BYTES ) == 0 );
+
+	pxList = &( pxEventBits->xTasksWaitingForBits );
+	pxListEnd = listGET_END_MARKER( pxList ); /*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+	vTaskSuspendAll();
+	{
+		traceEVENT_GROUP_SET_BITS( xEventGroup, uxBitsToSet );
+
+		pxListItem = listGET_HEAD_ENTRY( pxList );
+
+		/* Set the bits. */
+		pxEventBits->uxEventBits |= uxBitsToSet;
+
+		/* See if the new bit value should unblock any tasks. */
+		while( pxListItem != pxListEnd )
+		{
+			pxNext = listGET_NEXT( pxListItem );
+			uxBitsWaitedFor = listGET_LIST_ITEM_VALUE( pxListItem );
+			xMatchFound = pdFALSE;
+
+			/* Split the bits waited for from the control bits. */
+			uxControlBits = uxBitsWaitedFor & eventEVENT_BITS_CONTROL_BYTES;
+			uxBitsWaitedFor &= ~eventEVENT_BITS_CONTROL_BYTES;
+
+			if( ( uxControlBits & eventWAIT_FOR_ALL_BITS ) == ( EventBits_t ) 0 )
+			{
+				/* Just looking for single bit being set. */
+				if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) != ( EventBits_t ) 0 )
+				{
+					xMatchFound = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else if( ( uxBitsWaitedFor & pxEventBits->uxEventBits ) == uxBitsWaitedFor )
+			{
+				/* All bits are set. */
+				xMatchFound = pdTRUE;
+			}
+			else
+			{
+				/* Need all bits to be set, but not all the bits were set. */
+			}
+
+			if( xMatchFound != pdFALSE )
+			{
+				/* The bits match.  Should the bits be cleared on exit? */
+				if( ( uxControlBits & eventCLEAR_EVENTS_ON_EXIT_BIT ) != ( EventBits_t ) 0 )
+				{
+					uxBitsToClear |= uxBitsWaitedFor;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* Store the actual event flag value in the task's event list
+				item before removing the task from the event list.  The
+				eventUNBLOCKED_DUE_TO_BIT_SET bit is set so the task knows
+				that is was unblocked due to its required bits matching, rather
+				than because it timed out. */
+				( void ) xTaskRemoveFromUnorderedEventList( pxListItem, pxEventBits->uxEventBits | eventUNBLOCKED_DUE_TO_BIT_SET );
+			}
+
+			/* Move onto the next list item.  Note pxListItem->pxNext is not
+			used here as the list item may have been removed from the event list
+			and inserted into the ready/pending reading list. */
+			pxListItem = pxNext;
+		}
+
+		/* Clear any bits that matched when the eventCLEAR_EVENTS_ON_EXIT_BIT
+		bit was set in the control word. */
+		pxEventBits->uxEventBits &= ~uxBitsToClear;
+	}
+	( void ) xTaskResumeAll();
+
+	return pxEventBits->uxEventBits;
+}
+/*-----------------------------------------------------------*/
+
+void vEventGroupDelete( EventGroupHandle_t xEventGroup )
+{
+EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
+const List_t *pxTasksWaitingForBits = &( pxEventBits->xTasksWaitingForBits );
+
+	vTaskSuspendAll();
+	{
+		traceEVENT_GROUP_DELETE( xEventGroup );
+
+		while( listCURRENT_LIST_LENGTH( pxTasksWaitingForBits ) > ( UBaseType_t ) 0 )
+		{
+			/* Unblock the task, returning 0 as the event list is being deleted
+			and	cannot therefore have any bits set. */
+			configASSERT( pxTasksWaitingForBits->xListEnd.pxNext != ( ListItem_t * ) &( pxTasksWaitingForBits->xListEnd ) );
+			( void ) xTaskRemoveFromUnorderedEventList( pxTasksWaitingForBits->xListEnd.pxNext, eventUNBLOCKED_DUE_TO_BIT_SET );
+		}
+
+		#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+		{
+			/* The event group can only have been allocated dynamically - free
+			it again. */
+			vPortFree( pxEventBits );
+		}
+		#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+		{
+			/* The event group could have been allocated statically or
+			dynamically, so check before attempting to free the memory. */
+			if( pxEventBits->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+			{
+				vPortFree( pxEventBits );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+	}
+	( void ) xTaskResumeAll();
+}
+/*-----------------------------------------------------------*/
+
+/* For internal use only - execute a 'set bits' command that was pended from
+an interrupt. */
+void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet )
+{
+	( void ) xEventGroupSetBits( pvEventGroup, ( EventBits_t ) ulBitsToSet );
+}
+/*-----------------------------------------------------------*/
+
+/* For internal use only - execute a 'clear bits' command that was pended from
+an interrupt. */
+void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear )
+{
+	( void ) xEventGroupClearBits( pvEventGroup, ( EventBits_t ) ulBitsToClear );
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvTestWaitCondition( const EventBits_t uxCurrentEventBits, const EventBits_t uxBitsToWaitFor, const BaseType_t xWaitForAllBits )
+{
+BaseType_t xWaitConditionMet = pdFALSE;
+
+	if( xWaitForAllBits == pdFALSE )
+	{
+		/* Task only has to wait for one bit within uxBitsToWaitFor to be
+		set.  Is one already set? */
+		if( ( uxCurrentEventBits & uxBitsToWaitFor ) != ( EventBits_t ) 0 )
+		{
+			xWaitConditionMet = pdTRUE;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		/* Task has to wait for all the bits in uxBitsToWaitFor to be set.
+		Are they set already? */
+		if( ( uxCurrentEventBits & uxBitsToWaitFor ) == uxBitsToWaitFor )
+		{
+			xWaitConditionMet = pdTRUE;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	return xWaitConditionMet;
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 1 ) )
+
+	BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	BaseType_t xReturn;
+
+		traceEVENT_GROUP_SET_BITS_FROM_ISR( xEventGroup, uxBitsToSet );
+		xReturn = xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken );
+
+		return xReturn;
+	}
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if (configUSE_TRACE_FACILITY == 1)
+
+	UBaseType_t uxEventGroupGetNumber( void* xEventGroup )
+	{
+	UBaseType_t xReturn;
+	EventGroup_t *pxEventBits = ( EventGroup_t * ) xEventGroup;
+
+		if( xEventGroup == NULL )
+		{
+			xReturn = 0;
+		}
+		else
+		{
+			xReturn = pxEventBits->uxEventGroupNumber;
+		}
+
+		return xReturn;
+	}
+
+#endif
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/event_groups.h b/STM32F1/libraries/FreeRTOS900/utility/event_groups.h
new file mode 100644
index 000000000..7331c91c2
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/event_groups.h
@@ -0,0 +1,797 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#ifndef EVENT_GROUPS_H
+#define EVENT_GROUPS_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include event_groups.h"
+#endif
+
+/* FreeRTOS includes. */
+#include "timers.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/**
+ * An event group is a collection of bits to which an application can assign a
+ * meaning.  For example, an application may create an event group to convey
+ * the status of various CAN bus related events in which bit 0 might mean "A CAN
+ * message has been received and is ready for processing", bit 1 might mean "The
+ * application has queued a message that is ready for sending onto the CAN
+ * network", and bit 2 might mean "It is time to send a SYNC message onto the
+ * CAN network" etc.  A task can then test the bit values to see which events
+ * are active, and optionally enter the Blocked state to wait for a specified
+ * bit or a group of specified bits to be active.  To continue the CAN bus
+ * example, a CAN controlling task can enter the Blocked state (and therefore
+ * not consume any processing time) until either bit 0, bit 1 or bit 2 are
+ * active, at which time the bit that was actually active would inform the task
+ * which action it had to take (process a received message, send a message, or
+ * send a SYNC).
+ *
+ * The event groups implementation contains intelligence to avoid race
+ * conditions that would otherwise occur were an application to use a simple
+ * variable for the same purpose.  This is particularly important with respect
+ * to when a bit within an event group is to be cleared, and when bits have to
+ * be set and then tested atomically - as is the case where event groups are
+ * used to create a synchronisation point between multiple tasks (a
+ * 'rendezvous').
+ *
+ * \defgroup EventGroup
+ */
+
+
+
+/**
+ * event_groups.h
+ *
+ * Type by which event groups are referenced.  For example, a call to
+ * xEventGroupCreate() returns an EventGroupHandle_t variable that can then
+ * be used as a parameter to other event group functions.
+ *
+ * \defgroup EventGroupHandle_t EventGroupHandle_t
+ * \ingroup EventGroup
+ */
+typedef void * EventGroupHandle_t;
+
+/*
+ * The type that holds event bits always matches TickType_t - therefore the
+ * number of bits it holds is set by configUSE_16_BIT_TICKS (16 bits if set to 1,
+ * 32 bits if set to 0.
+ *
+ * \defgroup EventBits_t EventBits_t
+ * \ingroup EventGroup
+ */
+typedef TickType_t EventBits_t;
+
+/**
+ * event_groups.h
+ *<pre>
+ EventGroupHandle_t xEventGroupCreate( void );
+ </pre>
+ *
+ * Create a new event group.
+ *
+ * Internally, within the FreeRTOS implementation, event groups use a [small]
+ * block of memory, in which the event group's structure is stored.  If an event
+ * groups is created using xEventGropuCreate() then the required memory is
+ * automatically dynamically allocated inside the xEventGroupCreate() function.
+ * (see http://www.freertos.org/a00111.html).  If an event group is created
+ * using xEventGropuCreateStatic() then the application writer must instead
+ * provide the memory that will get used by the event group.
+ * xEventGroupCreateStatic() therefore allows an event group to be created
+ * without using any dynamic memory allocation.
+ *
+ * Although event groups are not related to ticks, for internal implementation
+ * reasons the number of bits available for use in an event group is dependent
+ * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h.  If
+ * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit
+ * 0 to bit 7).  If configUSE_16_BIT_TICKS is set to 0 then each event group has
+ * 24 usable bits (bit 0 to bit 23).  The EventBits_t type is used to store
+ * event bits within an event group.
+ *
+ * @return If the event group was created then a handle to the event group is
+ * returned.  If there was insufficient FreeRTOS heap available to create the
+ * event group then NULL is returned.  See http://www.freertos.org/a00111.html
+ *
+ * Example usage:
+   <pre>
+	// Declare a variable to hold the created event group.
+	EventGroupHandle_t xCreatedEventGroup;
+
+	// Attempt to create the event group.
+	xCreatedEventGroup = xEventGroupCreate();
+
+	// Was the event group created successfully?
+	if( xCreatedEventGroup == NULL )
+	{
+		// The event group was not created because there was insufficient
+		// FreeRTOS heap available.
+	}
+	else
+	{
+		// The event group was created.
+	}
+   </pre>
+ * \defgroup xEventGroupCreate xEventGroupCreate
+ * \ingroup EventGroup
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	EventGroupHandle_t xEventGroupCreate( void ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * event_groups.h
+ *<pre>
+ EventGroupHandle_t xEventGroupCreateStatic( EventGroupHandle_t * pxEventGroupBuffer );
+ </pre>
+ *
+ * Create a new event group.
+ *
+ * Internally, within the FreeRTOS implementation, event groups use a [small]
+ * block of memory, in which the event group's structure is stored.  If an event
+ * groups is created using xEventGropuCreate() then the required memory is
+ * automatically dynamically allocated inside the xEventGroupCreate() function.
+ * (see http://www.freertos.org/a00111.html).  If an event group is created
+ * using xEventGropuCreateStatic() then the application writer must instead
+ * provide the memory that will get used by the event group.
+ * xEventGroupCreateStatic() therefore allows an event group to be created
+ * without using any dynamic memory allocation.
+ *
+ * Although event groups are not related to ticks, for internal implementation
+ * reasons the number of bits available for use in an event group is dependent
+ * on the configUSE_16_BIT_TICKS setting in FreeRTOSConfig.h.  If
+ * configUSE_16_BIT_TICKS is 1 then each event group contains 8 usable bits (bit
+ * 0 to bit 7).  If configUSE_16_BIT_TICKS is set to 0 then each event group has
+ * 24 usable bits (bit 0 to bit 23).  The EventBits_t type is used to store
+ * event bits within an event group.
+ *
+ * @param pxEventGroupBuffer pxEventGroupBuffer must point to a variable of type
+ * StaticEventGroup_t, which will be then be used to hold the event group's data
+ * structures, removing the need for the memory to be allocated dynamically.
+ *
+ * @return If the event group was created then a handle to the event group is
+ * returned.  If pxEventGroupBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+   <pre>
+	// StaticEventGroup_t is a publicly accessible structure that has the same
+	// size and alignment requirements as the real event group structure.  It is
+	// provided as a mechanism for applications to know the size of the event
+	// group (which is dependent on the architecture and configuration file
+	// settings) without breaking the strict data hiding policy by exposing the
+	// real event group internals.  This StaticEventGroup_t variable is passed
+	// into the xSemaphoreCreateEventGroupStatic() function and is used to store
+	// the event group's data structures
+	StaticEventGroup_t xEventGroupBuffer;
+
+	// Create the event group without dynamically allocating any memory.
+	xEventGroup = xEventGroupCreateStatic( &xEventGroupBuffer );
+   </pre>
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	EventGroupHandle_t xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * event_groups.h
+ *<pre>
+	EventBits_t xEventGroupWaitBits( 	EventGroupHandle_t xEventGroup,
+										const EventBits_t uxBitsToWaitFor,
+										const BaseType_t xClearOnExit,
+										const BaseType_t xWaitForAllBits,
+										const TickType_t xTicksToWait );
+ </pre>
+ *
+ * [Potentially] block to wait for one or more bits to be set within a
+ * previously created event group.
+ *
+ * This function cannot be called from an interrupt.
+ *
+ * @param xEventGroup The event group in which the bits are being tested.  The
+ * event group must have previously been created using a call to
+ * xEventGroupCreate().
+ *
+ * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
+ * inside the event group.  For example, to wait for bit 0 and/or bit 2 set
+ * uxBitsToWaitFor to 0x05.  To wait for bits 0 and/or bit 1 and/or bit 2 set
+ * uxBitsToWaitFor to 0x07.  Etc.
+ *
+ * @param xClearOnExit If xClearOnExit is set to pdTRUE then any bits within
+ * uxBitsToWaitFor that are set within the event group will be cleared before
+ * xEventGroupWaitBits() returns if the wait condition was met (if the function
+ * returns for a reason other than a timeout).  If xClearOnExit is set to
+ * pdFALSE then the bits set in the event group are not altered when the call to
+ * xEventGroupWaitBits() returns.
+ *
+ * @param xWaitForAllBits If xWaitForAllBits is set to pdTRUE then
+ * xEventGroupWaitBits() will return when either all the bits in uxBitsToWaitFor
+ * are set or the specified block time expires.  If xWaitForAllBits is set to
+ * pdFALSE then xEventGroupWaitBits() will return when any one of the bits set
+ * in uxBitsToWaitFor is set or the specified block time expires.  The block
+ * time is specified by the xTicksToWait parameter.
+ *
+ * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
+ * for one/all (depending on the xWaitForAllBits value) of the bits specified by
+ * uxBitsToWaitFor to become set.
+ *
+ * @return The value of the event group at the time either the bits being waited
+ * for became set, or the block time expired.  Test the return value to know
+ * which bits were set.  If xEventGroupWaitBits() returned because its timeout
+ * expired then not all the bits being waited for will be set.  If
+ * xEventGroupWaitBits() returned because the bits it was waiting for were set
+ * then the returned value is the event group value before any bits were
+ * automatically cleared in the case that xClearOnExit parameter was set to
+ * pdTRUE.
+ *
+ * Example usage:
+   <pre>
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+   const TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+		// Wait a maximum of 100ms for either bit 0 or bit 4 to be set within
+		// the event group.  Clear the bits before exiting.
+		uxBits = xEventGroupWaitBits(
+					xEventGroup,	// The event group being tested.
+					BIT_0 | BIT_4,	// The bits within the event group to wait for.
+					pdTRUE,			// BIT_0 and BIT_4 should be cleared before returning.
+					pdFALSE,		// Don't wait for both bits, either bit will do.
+					xTicksToWait );	// Wait a maximum of 100ms for either bit to be set.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// xEventGroupWaitBits() returned because both bits were set.
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// xEventGroupWaitBits() returned because just BIT_0 was set.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// xEventGroupWaitBits() returned because just BIT_4 was set.
+		}
+		else
+		{
+			// xEventGroupWaitBits() returned because xTicksToWait ticks passed
+			// without either BIT_0 or BIT_4 becoming set.
+		}
+   }
+   </pre>
+ * \defgroup xEventGroupWaitBits xEventGroupWaitBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *<pre>
+	EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
+ </pre>
+ *
+ * Clear bits within an event group.  This function cannot be called from an
+ * interrupt.
+ *
+ * @param xEventGroup The event group in which the bits are to be cleared.
+ *
+ * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear
+ * in the event group.  For example, to clear bit 3 only, set uxBitsToClear to
+ * 0x08.  To clear bit 3 and bit 0 set uxBitsToClear to 0x09.
+ *
+ * @return The value of the event group before the specified bits were cleared.
+ *
+ * Example usage:
+   <pre>
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+
+		// Clear bit 0 and bit 4 in xEventGroup.
+		uxBits = xEventGroupClearBits(
+								xEventGroup,	// The event group being updated.
+								BIT_0 | BIT_4 );// The bits being cleared.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// Both bit 0 and bit 4 were set before xEventGroupClearBits() was
+			// called.  Both will now be clear (not set).
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// Bit 0 was set before xEventGroupClearBits() was called.  It will
+			// now be clear.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// Bit 4 was set before xEventGroupClearBits() was called.  It will
+			// now be clear.
+		}
+		else
+		{
+			// Neither bit 0 nor bit 4 were set in the first place.
+		}
+   }
+   </pre>
+ * \defgroup xEventGroupClearBits xEventGroupClearBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *<pre>
+	BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+ </pre>
+ *
+ * A version of xEventGroupClearBits() that can be called from an interrupt.
+ *
+ * Setting bits in an event group is not a deterministic operation because there
+ * are an unknown number of tasks that may be waiting for the bit or bits being
+ * set.  FreeRTOS does not allow nondeterministic operations to be performed
+ * while interrupts are disabled, so protects event groups that are accessed
+ * from tasks by suspending the scheduler rather than disabling interrupts.  As
+ * a result event groups cannot be accessed directly from an interrupt service
+ * routine.  Therefore xEventGroupClearBitsFromISR() sends a message to the
+ * timer task to have the clear operation performed in the context of the timer
+ * task.
+ *
+ * @param xEventGroup The event group in which the bits are to be cleared.
+ *
+ * @param uxBitsToClear A bitwise value that indicates the bit or bits to clear.
+ * For example, to clear bit 3 only, set uxBitsToClear to 0x08.  To clear bit 3
+ * and bit 0 set uxBitsToClear to 0x09.
+ *
+ * @return If the request to execute the function was posted successfully then
+ * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned
+ * if the timer service queue was full.
+ *
+ * Example usage:
+   <pre>
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   // An event group which it is assumed has already been created by a call to
+   // xEventGroupCreate().
+   EventGroupHandle_t xEventGroup;
+
+   void anInterruptHandler( void )
+   {
+		// Clear bit 0 and bit 4 in xEventGroup.
+		xResult = xEventGroupClearBitsFromISR(
+							xEventGroup,	 // The event group being updated.
+							BIT_0 | BIT_4 ); // The bits being set.
+
+		if( xResult == pdPASS )
+		{
+			// The message was posted successfully.
+		}
+  }
+   </pre>
+ * \defgroup xEventGroupClearBitsFromISR xEventGroupClearBitsFromISR
+ * \ingroup EventGroup
+ */
+#if( configUSE_TRACE_FACILITY == 1 )
+	BaseType_t xEventGroupClearBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;
+#else
+	#define xEventGroupClearBitsFromISR( xEventGroup, uxBitsToClear ) xTimerPendFunctionCallFromISR( vEventGroupClearBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToClear, NULL )
+#endif
+
+/**
+ * event_groups.h
+ *<pre>
+	EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+ </pre>
+ *
+ * Set bits within an event group.
+ * This function cannot be called from an interrupt.  xEventGroupSetBitsFromISR()
+ * is a version that can be called from an interrupt.
+ *
+ * Setting bits in an event group will automatically unblock tasks that are
+ * blocked waiting for the bits.
+ *
+ * @param xEventGroup The event group in which the bits are to be set.
+ *
+ * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
+ * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3
+ * and bit 0 set uxBitsToSet to 0x09.
+ *
+ * @return The value of the event group at the time the call to
+ * xEventGroupSetBits() returns.  There are two reasons why the returned value
+ * might have the bits specified by the uxBitsToSet parameter cleared.  First,
+ * if setting a bit results in a task that was waiting for the bit leaving the
+ * blocked state then it is possible the bit will be cleared automatically
+ * (see the xClearBitOnExit parameter of xEventGroupWaitBits()).  Second, any
+ * unblocked (or otherwise Ready state) task that has a priority above that of
+ * the task that called xEventGroupSetBits() will execute and may change the
+ * event group value before the call to xEventGroupSetBits() returns.
+ *
+ * Example usage:
+   <pre>
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   void aFunction( EventGroupHandle_t xEventGroup )
+   {
+   EventBits_t uxBits;
+
+		// Set bit 0 and bit 4 in xEventGroup.
+		uxBits = xEventGroupSetBits(
+							xEventGroup,	// The event group being updated.
+							BIT_0 | BIT_4 );// The bits being set.
+
+		if( ( uxBits & ( BIT_0 | BIT_4 ) ) == ( BIT_0 | BIT_4 ) )
+		{
+			// Both bit 0 and bit 4 remained set when the function returned.
+		}
+		else if( ( uxBits & BIT_0 ) != 0 )
+		{
+			// Bit 0 remained set when the function returned, but bit 4 was
+			// cleared.  It might be that bit 4 was cleared automatically as a
+			// task that was waiting for bit 4 was removed from the Blocked
+			// state.
+		}
+		else if( ( uxBits & BIT_4 ) != 0 )
+		{
+			// Bit 4 remained set when the function returned, but bit 0 was
+			// cleared.  It might be that bit 0 was cleared automatically as a
+			// task that was waiting for bit 0 was removed from the Blocked
+			// state.
+		}
+		else
+		{
+			// Neither bit 0 nor bit 4 remained set.  It might be that a task
+			// was waiting for both of the bits to be set, and the bits were
+			// cleared as the task left the Blocked state.
+		}
+   }
+   </pre>
+ * \defgroup xEventGroupSetBits xEventGroupSetBits
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *<pre>
+	BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken );
+ </pre>
+ *
+ * A version of xEventGroupSetBits() that can be called from an interrupt.
+ *
+ * Setting bits in an event group is not a deterministic operation because there
+ * are an unknown number of tasks that may be waiting for the bit or bits being
+ * set.  FreeRTOS does not allow nondeterministic operations to be performed in
+ * interrupts or from critical sections.  Therefore xEventGroupSetBitsFromISR()
+ * sends a message to the timer task to have the set operation performed in the
+ * context of the timer task - where a scheduler lock is used in place of a
+ * critical section.
+ *
+ * @param xEventGroup The event group in which the bits are to be set.
+ *
+ * @param uxBitsToSet A bitwise value that indicates the bit or bits to set.
+ * For example, to set bit 3 only, set uxBitsToSet to 0x08.  To set bit 3
+ * and bit 0 set uxBitsToSet to 0x09.
+ *
+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
+ * will result in a message being sent to the timer daemon task.  If the
+ * priority of the timer daemon task is higher than the priority of the
+ * currently running task (the task the interrupt interrupted) then
+ * *pxHigherPriorityTaskWoken will be set to pdTRUE by
+ * xEventGroupSetBitsFromISR(), indicating that a context switch should be
+ * requested before the interrupt exits.  For that reason
+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
+ * example code below.
+ *
+ * @return If the request to execute the function was posted successfully then
+ * pdPASS is returned, otherwise pdFALSE is returned.  pdFALSE will be returned
+ * if the timer service queue was full.
+ *
+ * Example usage:
+   <pre>
+   #define BIT_0	( 1 << 0 )
+   #define BIT_4	( 1 << 4 )
+
+   // An event group which it is assumed has already been created by a call to
+   // xEventGroupCreate().
+   EventGroupHandle_t xEventGroup;
+
+   void anInterruptHandler( void )
+   {
+   BaseType_t xHigherPriorityTaskWoken, xResult;
+
+		// xHigherPriorityTaskWoken must be initialised to pdFALSE.
+		xHigherPriorityTaskWoken = pdFALSE;
+
+		// Set bit 0 and bit 4 in xEventGroup.
+		xResult = xEventGroupSetBitsFromISR(
+							xEventGroup,	// The event group being updated.
+							BIT_0 | BIT_4   // The bits being set.
+							&xHigherPriorityTaskWoken );
+
+		// Was the message posted successfully?
+		if( xResult == pdPASS )
+		{
+			// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+			// switch should be requested.  The macro used is port specific and
+			// will be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() -
+			// refer to the documentation page for the port being used.
+			portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+		}
+  }
+   </pre>
+ * \defgroup xEventGroupSetBitsFromISR xEventGroupSetBitsFromISR
+ * \ingroup EventGroup
+ */
+#if( configUSE_TRACE_FACILITY == 1 )
+	BaseType_t xEventGroupSetBitsFromISR( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#else
+	#define xEventGroupSetBitsFromISR( xEventGroup, uxBitsToSet, pxHigherPriorityTaskWoken ) xTimerPendFunctionCallFromISR( vEventGroupSetBitsCallback, ( void * ) xEventGroup, ( uint32_t ) uxBitsToSet, pxHigherPriorityTaskWoken )
+#endif
+
+/**
+ * event_groups.h
+ *<pre>
+	EventBits_t xEventGroupSync(	EventGroupHandle_t xEventGroup,
+									const EventBits_t uxBitsToSet,
+									const EventBits_t uxBitsToWaitFor,
+									TickType_t xTicksToWait );
+ </pre>
+ *
+ * Atomically set bits within an event group, then wait for a combination of
+ * bits to be set within the same event group.  This functionality is typically
+ * used to synchronise multiple tasks, where each task has to wait for the other
+ * tasks to reach a synchronisation point before proceeding.
+ *
+ * This function cannot be used from an interrupt.
+ *
+ * The function will return before its block time expires if the bits specified
+ * by the uxBitsToWait parameter are set, or become set within that time.  In
+ * this case all the bits specified by uxBitsToWait will be automatically
+ * cleared before the function returns.
+ *
+ * @param xEventGroup The event group in which the bits are being tested.  The
+ * event group must have previously been created using a call to
+ * xEventGroupCreate().
+ *
+ * @param uxBitsToSet The bits to set in the event group before determining
+ * if, and possibly waiting for, all the bits specified by the uxBitsToWait
+ * parameter are set.
+ *
+ * @param uxBitsToWaitFor A bitwise value that indicates the bit or bits to test
+ * inside the event group.  For example, to wait for bit 0 and bit 2 set
+ * uxBitsToWaitFor to 0x05.  To wait for bits 0 and bit 1 and bit 2 set
+ * uxBitsToWaitFor to 0x07.  Etc.
+ *
+ * @param xTicksToWait The maximum amount of time (specified in 'ticks') to wait
+ * for all of the bits specified by uxBitsToWaitFor to become set.
+ *
+ * @return The value of the event group at the time either the bits being waited
+ * for became set, or the block time expired.  Test the return value to know
+ * which bits were set.  If xEventGroupSync() returned because its timeout
+ * expired then not all the bits being waited for will be set.  If
+ * xEventGroupSync() returned because all the bits it was waiting for were
+ * set then the returned value is the event group value before any bits were
+ * automatically cleared.
+ *
+ * Example usage:
+ <pre>
+ // Bits used by the three tasks.
+ #define TASK_0_BIT		( 1 << 0 )
+ #define TASK_1_BIT		( 1 << 1 )
+ #define TASK_2_BIT		( 1 << 2 )
+
+ #define ALL_SYNC_BITS ( TASK_0_BIT | TASK_1_BIT | TASK_2_BIT )
+
+ // Use an event group to synchronise three tasks.  It is assumed this event
+ // group has already been created elsewhere.
+ EventGroupHandle_t xEventBits;
+
+ void vTask0( void *pvParameters )
+ {
+ EventBits_t uxReturn;
+ TickType_t xTicksToWait = 100 / portTICK_PERIOD_MS;
+
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 0 in the event flag to note this task has reached the
+		// sync point.  The other two tasks will set the other two bits defined
+		// by ALL_SYNC_BITS.  All three tasks have reached the synchronisation
+		// point when all the ALL_SYNC_BITS are set.  Wait a maximum of 100ms
+		// for this to happen.
+		uxReturn = xEventGroupSync( xEventBits, TASK_0_BIT, ALL_SYNC_BITS, xTicksToWait );
+
+		if( ( uxReturn & ALL_SYNC_BITS ) == ALL_SYNC_BITS )
+		{
+			// All three tasks reached the synchronisation point before the call
+			// to xEventGroupSync() timed out.
+		}
+	}
+ }
+
+ void vTask1( void *pvParameters )
+ {
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 1 in the event flag to note this task has reached the
+		// synchronisation point.  The other two tasks will set the other two
+		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+		// indefinitely for this to happen.
+		xEventGroupSync( xEventBits, TASK_1_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+		// xEventGroupSync() was called with an indefinite block time, so
+		// this task will only reach here if the syncrhonisation was made by all
+		// three tasks, so there is no need to test the return value.
+	 }
+ }
+
+ void vTask2( void *pvParameters )
+ {
+	 for( ;; )
+	 {
+		// Perform task functionality here.
+
+		// Set bit 2 in the event flag to note this task has reached the
+		// synchronisation point.  The other two tasks will set the other two
+		// bits defined by ALL_SYNC_BITS.  All three tasks have reached the
+		// synchronisation point when all the ALL_SYNC_BITS are set.  Wait
+		// indefinitely for this to happen.
+		xEventGroupSync( xEventBits, TASK_2_BIT, ALL_SYNC_BITS, portMAX_DELAY );
+
+		// xEventGroupSync() was called with an indefinite block time, so
+		// this task will only reach here if the syncrhonisation was made by all
+		// three tasks, so there is no need to test the return value.
+	}
+ }
+
+ </pre>
+ * \defgroup xEventGroupSync xEventGroupSync
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+
+/**
+ * event_groups.h
+ *<pre>
+	EventBits_t xEventGroupGetBits( EventGroupHandle_t xEventGroup );
+ </pre>
+ *
+ * Returns the current value of the bits in an event group.  This function
+ * cannot be used from an interrupt.
+ *
+ * @param xEventGroup The event group being queried.
+ *
+ * @return The event group bits at the time xEventGroupGetBits() was called.
+ *
+ * \defgroup xEventGroupGetBits xEventGroupGetBits
+ * \ingroup EventGroup
+ */
+#define xEventGroupGetBits( xEventGroup ) xEventGroupClearBits( xEventGroup, 0 )
+
+/**
+ * event_groups.h
+ *<pre>
+	EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup );
+ </pre>
+ *
+ * A version of xEventGroupGetBits() that can be called from an ISR.
+ *
+ * @param xEventGroup The event group being queried.
+ *
+ * @return The event group bits at the time xEventGroupGetBitsFromISR() was called.
+ *
+ * \defgroup xEventGroupGetBitsFromISR xEventGroupGetBitsFromISR
+ * \ingroup EventGroup
+ */
+EventBits_t xEventGroupGetBitsFromISR( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
+
+/**
+ * event_groups.h
+ *<pre>
+	void xEventGroupDelete( EventGroupHandle_t xEventGroup );
+ </pre>
+ *
+ * Delete an event group that was previously created by a call to
+ * xEventGroupCreate().  Tasks that are blocked on the event group will be
+ * unblocked and obtain 0 as the event group's value.
+ *
+ * @param xEventGroup The event group being deleted.
+ */
+void vEventGroupDelete( EventGroupHandle_t xEventGroup ) PRIVILEGED_FUNCTION;
+
+/* For internal use only. */
+void vEventGroupSetBitsCallback( void *pvEventGroup, const uint32_t ulBitsToSet ) PRIVILEGED_FUNCTION;
+void vEventGroupClearBitsCallback( void *pvEventGroup, const uint32_t ulBitsToClear ) PRIVILEGED_FUNCTION;
+
+
+#if (configUSE_TRACE_FACILITY == 1)
+	UBaseType_t uxEventGroupGetNumber( void* xEventGroup ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* EVENT_GROUPS_H */
+
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/heap_1.c b/STM32F1/libraries/FreeRTOS900/utility/heap_1.c
new file mode 100644
index 000000000..178ff7c32
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/heap_1.c
@@ -0,0 +1,174 @@
+/*
+    FreeRTOS V8.2.1 - Copyright (C) 2015 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>!AND MODIFIED BY!<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+
+/*
+ * The simplest possible implementation of pvPortMalloc().  Note that this
+ * implementation does NOT allow allocated memory to be freed again.
+ *
+ * See heap_2.c, heap_3.c and heap_4.c for alternative implementations, and the
+ * memory management pages of http://www.FreeRTOS.org for more information.
+ */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* A few bytes might be lost to byte aligning the heap start address. */
+#define configADJUSTED_HEAP_SIZE	( configTOTAL_HEAP_SIZE - portBYTE_ALIGNMENT )
+
+/* Allocate the memory for the heap. */
+static uint8_t ucHeap[ configTOTAL_HEAP_SIZE ];
+static size_t xNextFreeByte = ( size_t ) 0;
+
+/*-----------------------------------------------------------*/
+
+void *pvPortMalloc( size_t xWantedSize )
+{
+void *pvReturn = NULL;
+static uint8_t *pucAlignedHeap = NULL;
+
+	/* Ensure that blocks are always aligned to the required number of bytes. */
+	#if portBYTE_ALIGNMENT != 1
+		if( xWantedSize & portBYTE_ALIGNMENT_MASK )
+		{
+			/* Byte alignment required. */
+			xWantedSize += ( portBYTE_ALIGNMENT - ( xWantedSize & portBYTE_ALIGNMENT_MASK ) );
+		}
+	#endif
+
+	vTaskSuspendAll();
+	{
+		if( pucAlignedHeap == NULL )
+		{
+			/* Ensure the heap starts on a correctly aligned boundary. */
+			pucAlignedHeap = ( uint8_t * ) ( ( ( portPOINTER_SIZE_TYPE ) &ucHeap[ portBYTE_ALIGNMENT ] ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) );
+		}
+
+		/* Check there is enough room left for the allocation. */
+		if( ( ( xNextFreeByte + xWantedSize ) < configADJUSTED_HEAP_SIZE ) &&
+			( ( xNextFreeByte + xWantedSize ) > xNextFreeByte )	)/* Check for overflow. */
+		{
+			/* Return the next free byte then increment the index past this
+			block. */
+			pvReturn = pucAlignedHeap + xNextFreeByte;
+			xNextFreeByte += xWantedSize;
+		}
+
+		traceMALLOC( pvReturn, xWantedSize );
+	}
+	( void ) xTaskResumeAll();
+
+	#if( configUSE_MALLOC_FAILED_HOOK == 1 )
+	{
+		if( pvReturn == NULL )
+		{
+			extern void vApplicationMallocFailedHook( void );
+			vApplicationMallocFailedHook();
+		}
+	}
+	#endif
+
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vPortFree( void *pv )
+{
+	/* Memory cannot be freed using this scheme.  See heap_2.c, heap_3.c and
+	heap_4.c for alternative implementations, and the memory management pages of
+	http://www.FreeRTOS.org for more information. */
+	( void ) pv;
+
+	/* Force an assert as it is invalid to call this function. */
+	configASSERT( pv == NULL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortInitialiseBlocks( void )
+{
+	/* Only required when static memory is not cleared. */
+	xNextFreeByte = ( size_t ) 0;
+}
+/*-----------------------------------------------------------*/
+
+size_t xPortGetFreeHeapSize( void )
+{
+	return ( configADJUSTED_HEAP_SIZE - xNextFreeByte );
+}
+
+
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/list.c b/STM32F1/libraries/FreeRTOS900/utility/list.c
new file mode 100644
index 000000000..5e207c160
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/list.c
@@ -0,0 +1,240 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+
+#include <stdlib.h>
+#include "FreeRTOS.h"
+#include "list.h"
+
+/*-----------------------------------------------------------
+ * PUBLIC LIST API documented in list.h
+ *----------------------------------------------------------*/
+
+void vListInitialise( List_t * const pxList )
+{
+	/* The list structure contains a list item which is used to mark the
+	end of the list.  To initialise the list the list end is inserted
+	as the only list entry. */
+	pxList->pxIndex = ( ListItem_t * ) &( pxList->xListEnd );			/*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+
+	/* The list end value is the highest possible value in the list to
+	ensure it remains at the end of the list. */
+	pxList->xListEnd.xItemValue = portMAX_DELAY;
+
+	/* The list end next and previous pointers point to itself so we know
+	when the list is empty. */
+	pxList->xListEnd.pxNext = ( ListItem_t * ) &( pxList->xListEnd );	/*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+	pxList->xListEnd.pxPrevious = ( ListItem_t * ) &( pxList->xListEnd );/*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+
+	pxList->uxNumberOfItems = ( UBaseType_t ) 0U;
+
+	/* Write known values into the list if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList );
+	listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList );
+}
+/*-----------------------------------------------------------*/
+
+void vListInitialiseItem( ListItem_t * const pxItem )
+{
+	/* Make sure the list item is not recorded as being on a list. */
+	pxItem->pvContainer = NULL;
+
+	/* Write known values into the list item if
+	configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+	listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem );
+}
+/*-----------------------------------------------------------*/
+
+void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t * const pxIndex = pxList->pxIndex;
+
+	/* Only effective when configASSERT() is also defined, these tests may catch
+	the list data structures being overwritten in memory.  They will not catch
+	data errors caused by incorrect configuration or use of FreeRTOS. */
+	listTEST_LIST_INTEGRITY( pxList );
+	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+	/* Insert a new list item into pxList, but rather than sort the list,
+	makes the new list item the last item to be removed by a call to
+	listGET_OWNER_OF_NEXT_ENTRY(). */
+	pxNewListItem->pxNext = pxIndex;
+	pxNewListItem->pxPrevious = pxIndex->pxPrevious;
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	pxIndex->pxPrevious->pxNext = pxNewListItem;
+	pxIndex->pxPrevious = pxNewListItem;
+
+	/* Remember which list the item is in. */
+	pxNewListItem->pvContainer = ( void * ) pxList;
+
+	( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem )
+{
+ListItem_t *pxIterator;
+const TickType_t xValueOfInsertion = pxNewListItem->xItemValue;
+
+	/* Only effective when configASSERT() is also defined, these tests may catch
+	the list data structures being overwritten in memory.  They will not catch
+	data errors caused by incorrect configuration or use of FreeRTOS. */
+	listTEST_LIST_INTEGRITY( pxList );
+	listTEST_LIST_ITEM_INTEGRITY( pxNewListItem );
+
+	/* Insert the new list item into the list, sorted in xItemValue order.
+
+	If the list already contains a list item with the same item value then the
+	new list item should be placed after it.  This ensures that TCB's which are
+	stored in ready lists (all of which have the same xItemValue value) get a
+	share of the CPU.  However, if the xItemValue is the same as the back marker
+	the iteration loop below will not end.  Therefore the value is checked
+	first, and the algorithm slightly modified if necessary. */
+	if( xValueOfInsertion == portMAX_DELAY )
+	{
+		pxIterator = pxList->xListEnd.pxPrevious;
+	}
+	else
+	{
+		/* *** NOTE ***********************************************************
+		If you find your application is crashing here then likely causes are
+		listed below.  In addition see http://www.freertos.org/FAQHelp.html for
+		more tips, and ensure configASSERT() is defined!
+		http://www.freertos.org/a00110.html#configASSERT
+
+			1) Stack overflow -
+			   see http://www.freertos.org/Stacks-and-stack-overflow-checking.html
+			2) Incorrect interrupt priority assignment, especially on Cortex-M
+			   parts where numerically high priority values denote low actual
+			   interrupt priorities, which can seem counter intuitive.  See
+			   http://www.freertos.org/RTOS-Cortex-M3-M4.html and the definition
+			   of configMAX_SYSCALL_INTERRUPT_PRIORITY on
+			   http://www.freertos.org/a00110.html
+			3) Calling an API function from within a critical section or when
+			   the scheduler is suspended, or calling an API function that does
+			   not end in "FromISR" from an interrupt.
+			4) Using a queue or semaphore before it has been initialised or
+			   before the scheduler has been started (are interrupts firing
+			   before vTaskStartScheduler() has been called?).
+		**********************************************************************/
+
+		for( pxIterator = ( ListItem_t * ) &( pxList->xListEnd ); pxIterator->pxNext->xItemValue <= xValueOfInsertion; pxIterator = pxIterator->pxNext ) /*lint !e826 !e740 The mini list structure is used as the list end to save RAM.  This is checked and valid. */
+		{
+			/* There is nothing to do here, just iterating to the wanted
+			insertion position. */
+		}
+	}
+
+	pxNewListItem->pxNext = pxIterator->pxNext;
+	pxNewListItem->pxNext->pxPrevious = pxNewListItem;
+	pxNewListItem->pxPrevious = pxIterator;
+	pxIterator->pxNext = pxNewListItem;
+
+	/* Remember which list the item is in.  This allows fast removal of the
+	item later. */
+	pxNewListItem->pvContainer = ( void * ) pxList;
+
+	( pxList->uxNumberOfItems )++;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove )
+{
+/* The list item knows which list it is in.  Obtain the list from the list
+item. */
+List_t * const pxList = ( List_t * ) pxItemToRemove->pvContainer;
+
+	pxItemToRemove->pxNext->pxPrevious = pxItemToRemove->pxPrevious;
+	pxItemToRemove->pxPrevious->pxNext = pxItemToRemove->pxNext;
+
+	/* Only used during decision coverage testing. */
+	mtCOVERAGE_TEST_DELAY();
+
+	/* Make sure the index is left pointing to a valid item. */
+	if( pxList->pxIndex == pxItemToRemove )
+	{
+		pxList->pxIndex = pxItemToRemove->pxPrevious;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxItemToRemove->pvContainer = NULL;
+	( pxList->uxNumberOfItems )--;
+
+	return pxList->uxNumberOfItems;
+}
+/*-----------------------------------------------------------*/
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/list.h b/STM32F1/libraries/FreeRTOS900/utility/list.h
new file mode 100644
index 000000000..a080d27de
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/list.h
@@ -0,0 +1,453 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/*
+ * This is the list implementation used by the scheduler.  While it is tailored
+ * heavily for the schedulers needs, it is also available for use by
+ * application code.
+ *
+ * list_ts can only store pointers to list_item_ts.  Each ListItem_t contains a
+ * numeric value (xItemValue).  Most of the time the lists are sorted in
+ * descending item value order.
+ *
+ * Lists are created already containing one list item.  The value of this
+ * item is the maximum possible that can be stored, it is therefore always at
+ * the end of the list and acts as a marker.  The list member pxHead always
+ * points to this marker - even though it is at the tail of the list.  This
+ * is because the tail contains a wrap back pointer to the true head of
+ * the list.
+ *
+ * In addition to it's value, each list item contains a pointer to the next
+ * item in the list (pxNext), a pointer to the list it is in (pxContainer)
+ * and a pointer to back to the object that contains it.  These later two
+ * pointers are included for efficiency of list manipulation.  There is
+ * effectively a two way link between the object containing the list item and
+ * the list item itself.
+ *
+ *
+ * \page ListIntroduction List Implementation
+ * \ingroup FreeRTOSIntro
+ */
+
+#ifndef INC_FREERTOS_H
+	#error FreeRTOS.h must be included before list.h
+#endif
+
+#ifndef LIST_H
+#define LIST_H
+
+/*
+ * The list structure members are modified from within interrupts, and therefore
+ * by rights should be declared volatile.  However, they are only modified in a
+ * functionally atomic way (within critical sections of with the scheduler
+ * suspended) and are either passed by reference into a function or indexed via
+ * a volatile variable.  Therefore, in all use cases tested so far, the volatile
+ * qualifier can be omitted in order to provide a moderate performance
+ * improvement without adversely affecting functional behaviour.  The assembly
+ * instructions generated by the IAR, ARM and GCC compilers when the respective
+ * compiler's options were set for maximum optimisation has been inspected and
+ * deemed to be as intended.  That said, as compiler technology advances, and
+ * especially if aggressive cross module optimisation is used (a use case that
+ * has not been exercised to any great extend) then it is feasible that the
+ * volatile qualifier will be needed for correct optimisation.  It is expected
+ * that a compiler removing essential code because, without the volatile
+ * qualifier on the list structure members and with aggressive cross module
+ * optimisation, the compiler deemed the code unnecessary will result in
+ * complete and obvious failure of the scheduler.  If this is ever experienced
+ * then the volatile qualifier can be inserted in the relevant places within the
+ * list structures by simply defining configLIST_VOLATILE to volatile in
+ * FreeRTOSConfig.h (as per the example at the bottom of this comment block).
+ * If configLIST_VOLATILE is not defined then the preprocessor directives below
+ * will simply #define configLIST_VOLATILE away completely.
+ *
+ * To use volatile list structure members then add the following line to
+ * FreeRTOSConfig.h (without the quotes):
+ * "#define configLIST_VOLATILE volatile"
+ */
+#ifndef configLIST_VOLATILE
+	#define configLIST_VOLATILE
+#endif /* configSUPPORT_CROSS_MODULE_OPTIMISATION */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/* Macros that can be used to place known values within the list structures,
+then check that the known values do not get corrupted during the execution of
+the application.   These may catch the list data structures being overwritten in
+memory.  They will not catch data errors caused by incorrect configuration or
+use of FreeRTOS.*/
+#if( configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES == 0 )
+	/* Define the macros to do nothing. */
+	#define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE
+	#define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE
+	#define listFIRST_LIST_INTEGRITY_CHECK_VALUE
+	#define listSECOND_LIST_INTEGRITY_CHECK_VALUE
+	#define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
+	#define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )
+	#define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )
+	#define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )
+	#define listTEST_LIST_ITEM_INTEGRITY( pxItem )
+	#define listTEST_LIST_INTEGRITY( pxList )
+#else
+	/* Define macros that add new members into the list structures. */
+	#define listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE				TickType_t xListItemIntegrityValue1;
+	#define listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE				TickType_t xListItemIntegrityValue2;
+	#define listFIRST_LIST_INTEGRITY_CHECK_VALUE					TickType_t xListIntegrityValue1;
+	#define listSECOND_LIST_INTEGRITY_CHECK_VALUE					TickType_t xListIntegrityValue2;
+
+	/* Define macros that set the new structure members to known values. */
+	#define listSET_FIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )		( pxItem )->xListItemIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
+	#define listSET_SECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE( pxItem )	( pxItem )->xListItemIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
+	#define listSET_LIST_INTEGRITY_CHECK_1_VALUE( pxList )		( pxList )->xListIntegrityValue1 = pdINTEGRITY_CHECK_VALUE
+	#define listSET_LIST_INTEGRITY_CHECK_2_VALUE( pxList )		( pxList )->xListIntegrityValue2 = pdINTEGRITY_CHECK_VALUE
+
+	/* Define macros that will assert if one of the structure members does not
+	contain its expected value. */
+	#define listTEST_LIST_ITEM_INTEGRITY( pxItem )		configASSERT( ( ( pxItem )->xListItemIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxItem )->xListItemIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
+	#define listTEST_LIST_INTEGRITY( pxList )			configASSERT( ( ( pxList )->xListIntegrityValue1 == pdINTEGRITY_CHECK_VALUE ) && ( ( pxList )->xListIntegrityValue2 == pdINTEGRITY_CHECK_VALUE ) )
+#endif /* configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES */
+
+
+/*
+ * Definition of the only type of object that a list can contain.
+ */
+struct xLIST_ITEM
+{
+	listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE			/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	configLIST_VOLATILE TickType_t xItemValue;			/*< The value being listed.  In most cases this is used to sort the list in descending order. */
+	struct xLIST_ITEM * configLIST_VOLATILE pxNext;		/*< Pointer to the next ListItem_t in the list. */
+	struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;	/*< Pointer to the previous ListItem_t in the list. */
+	void * pvOwner;										/*< Pointer to the object (normally a TCB) that contains the list item.  There is therefore a two way link between the object containing the list item and the list item itself. */
+	void * configLIST_VOLATILE pvContainer;				/*< Pointer to the list in which this list item is placed (if any). */
+	listSECOND_LIST_ITEM_INTEGRITY_CHECK_VALUE			/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+};
+typedef struct xLIST_ITEM ListItem_t;					/* For some reason lint wants this as two separate definitions. */
+
+struct xMINI_LIST_ITEM
+{
+	listFIRST_LIST_ITEM_INTEGRITY_CHECK_VALUE			/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	configLIST_VOLATILE TickType_t xItemValue;
+	struct xLIST_ITEM * configLIST_VOLATILE pxNext;
+	struct xLIST_ITEM * configLIST_VOLATILE pxPrevious;
+};
+typedef struct xMINI_LIST_ITEM MiniListItem_t;
+
+/*
+ * Definition of the type of queue used by the scheduler.
+ */
+typedef struct xLIST
+{
+	listFIRST_LIST_INTEGRITY_CHECK_VALUE				/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+	configLIST_VOLATILE UBaseType_t uxNumberOfItems;
+	ListItem_t * configLIST_VOLATILE pxIndex;			/*< Used to walk through the list.  Points to the last item returned by a call to listGET_OWNER_OF_NEXT_ENTRY (). */
+	MiniListItem_t xListEnd;							/*< List item that contains the maximum possible item value meaning it is always at the end of the list and is therefore used as a marker. */
+	listSECOND_LIST_INTEGRITY_CHECK_VALUE				/*< Set to a known value if configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES is set to 1. */
+} List_t;
+
+/*
+ * Access macro to set the owner of a list item.  The owner of a list item
+ * is the object (usually a TCB) that contains the list item.
+ *
+ * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
+ * \ingroup LinkedList
+ */
+#define listSET_LIST_ITEM_OWNER( pxListItem, pxOwner )		( ( pxListItem )->pvOwner = ( void * ) ( pxOwner ) )
+
+/*
+ * Access macro to get the owner of a list item.  The owner of a list item
+ * is the object (usually a TCB) that contains the list item.
+ *
+ * \page listSET_LIST_ITEM_OWNER listSET_LIST_ITEM_OWNER
+ * \ingroup LinkedList
+ */
+#define listGET_LIST_ITEM_OWNER( pxListItem )	( ( pxListItem )->pvOwner )
+
+/*
+ * Access macro to set the value of the list item.  In most cases the value is
+ * used to sort the list in descending order.
+ *
+ * \page listSET_LIST_ITEM_VALUE listSET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listSET_LIST_ITEM_VALUE( pxListItem, xValue )	( ( pxListItem )->xItemValue = ( xValue ) )
+
+/*
+ * Access macro to retrieve the value of the list item.  The value can
+ * represent anything - for example the priority of a task, or the time at
+ * which a task should be unblocked.
+ *
+ * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listGET_LIST_ITEM_VALUE( pxListItem )	( ( pxListItem )->xItemValue )
+
+/*
+ * Access macro to retrieve the value of the list item at the head of a given
+ * list.
+ *
+ * \page listGET_LIST_ITEM_VALUE listGET_LIST_ITEM_VALUE
+ * \ingroup LinkedList
+ */
+#define listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxList )	( ( ( pxList )->xListEnd ).pxNext->xItemValue )
+
+/*
+ * Return the list item at the head of the list.
+ *
+ * \page listGET_HEAD_ENTRY listGET_HEAD_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_HEAD_ENTRY( pxList )	( ( ( pxList )->xListEnd ).pxNext )
+
+/*
+ * Return the list item at the head of the list.
+ *
+ * \page listGET_NEXT listGET_NEXT
+ * \ingroup LinkedList
+ */
+#define listGET_NEXT( pxListItem )	( ( pxListItem )->pxNext )
+
+/*
+ * Return the list item that marks the end of the list
+ *
+ * \page listGET_END_MARKER listGET_END_MARKER
+ * \ingroup LinkedList
+ */
+#define listGET_END_MARKER( pxList )	( ( ListItem_t const * ) ( &( ( pxList )->xListEnd ) ) )
+
+/*
+ * Access macro to determine if a list contains any items.  The macro will
+ * only have the value true if the list is empty.
+ *
+ * \page listLIST_IS_EMPTY listLIST_IS_EMPTY
+ * \ingroup LinkedList
+ */
+#define listLIST_IS_EMPTY( pxList )	( ( BaseType_t ) ( ( pxList )->uxNumberOfItems == ( UBaseType_t ) 0 ) )
+
+/*
+ * Access macro to return the number of items in the list.
+ */
+#define listCURRENT_LIST_LENGTH( pxList )	( ( pxList )->uxNumberOfItems )
+
+/*
+ * Access function to obtain the owner of the next entry in a list.
+ *
+ * The list member pxIndex is used to walk through a list.  Calling
+ * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list
+ * and returns that entry's pxOwner parameter.  Using multiple calls to this
+ * function it is therefore possible to move through every item contained in
+ * a list.
+ *
+ * The pxOwner parameter of a list item is a pointer to the object that owns
+ * the list item.  In the scheduler this is normally a task control block.
+ * The pxOwner parameter effectively creates a two way link between the list
+ * item and its owner.
+ *
+ * @param pxTCB pxTCB is set to the address of the owner of the next list item.
+ * @param pxList The list from which the next item owner is to be returned.
+ *
+ * \page listGET_OWNER_OF_NEXT_ENTRY listGET_OWNER_OF_NEXT_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_OWNER_OF_NEXT_ENTRY( pxTCB, pxList )										\
+{																							\
+List_t * const pxConstList = ( pxList );													\
+	/* Increment the index to the next item and return the item, ensuring */				\
+	/* we don't return the marker used at the end of the list.  */							\
+	( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;							\
+	if( ( void * ) ( pxConstList )->pxIndex == ( void * ) &( ( pxConstList )->xListEnd ) )	\
+	{																						\
+		( pxConstList )->pxIndex = ( pxConstList )->pxIndex->pxNext;						\
+	}																						\
+	( pxTCB ) = ( pxConstList )->pxIndex->pvOwner;											\
+}
+
+
+/*
+ * Access function to obtain the owner of the first entry in a list.  Lists
+ * are normally sorted in ascending item value order.
+ *
+ * This function returns the pxOwner member of the first item in the list.
+ * The pxOwner parameter of a list item is a pointer to the object that owns
+ * the list item.  In the scheduler this is normally a task control block.
+ * The pxOwner parameter effectively creates a two way link between the list
+ * item and its owner.
+ *
+ * @param pxList The list from which the owner of the head item is to be
+ * returned.
+ *
+ * \page listGET_OWNER_OF_HEAD_ENTRY listGET_OWNER_OF_HEAD_ENTRY
+ * \ingroup LinkedList
+ */
+#define listGET_OWNER_OF_HEAD_ENTRY( pxList )  ( (&( ( pxList )->xListEnd ))->pxNext->pvOwner )
+
+/*
+ * Check to see if a list item is within a list.  The list item maintains a
+ * "container" pointer that points to the list it is in.  All this macro does
+ * is check to see if the container and the list match.
+ *
+ * @param pxList The list we want to know if the list item is within.
+ * @param pxListItem The list item we want to know if is in the list.
+ * @return pdTRUE if the list item is in the list, otherwise pdFALSE.
+ */
+#define listIS_CONTAINED_WITHIN( pxList, pxListItem ) ( ( BaseType_t ) ( ( pxListItem )->pvContainer == ( void * ) ( pxList ) ) )
+
+/*
+ * Return the list a list item is contained within (referenced from).
+ *
+ * @param pxListItem The list item being queried.
+ * @return A pointer to the List_t object that references the pxListItem
+ */
+#define listLIST_ITEM_CONTAINER( pxListItem ) ( ( pxListItem )->pvContainer )
+
+/*
+ * This provides a crude means of knowing if a list has been initialised, as
+ * pxList->xListEnd.xItemValue is set to portMAX_DELAY by the vListInitialise()
+ * function.
+ */
+#define listLIST_IS_INITIALISED( pxList ) ( ( pxList )->xListEnd.xItemValue == portMAX_DELAY )
+
+/*
+ * Must be called before a list is used!  This initialises all the members
+ * of the list structure and inserts the xListEnd item into the list as a
+ * marker to the back of the list.
+ *
+ * @param pxList Pointer to the list being initialised.
+ *
+ * \page vListInitialise vListInitialise
+ * \ingroup LinkedList
+ */
+void vListInitialise( List_t * const pxList ) PRIVILEGED_FUNCTION;
+
+/*
+ * Must be called before a list item is used.  This sets the list container to
+ * null so the item does not think that it is already contained in a list.
+ *
+ * @param pxItem Pointer to the list item being initialised.
+ *
+ * \page vListInitialiseItem vListInitialiseItem
+ * \ingroup LinkedList
+ */
+void vListInitialiseItem( ListItem_t * const pxItem ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert a list item into a list.  The item will be inserted into the list in
+ * a position determined by its item value (descending item value order).
+ *
+ * @param pxList The list into which the item is to be inserted.
+ *
+ * @param pxNewListItem The item that is to be placed in the list.
+ *
+ * \page vListInsert vListInsert
+ * \ingroup LinkedList
+ */
+void vListInsert( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert a list item into a list.  The item will be inserted in a position
+ * such that it will be the last item within the list returned by multiple
+ * calls to listGET_OWNER_OF_NEXT_ENTRY.
+ *
+ * The list member pxIndex is used to walk through a list.  Calling
+ * listGET_OWNER_OF_NEXT_ENTRY increments pxIndex to the next item in the list.
+ * Placing an item in a list using vListInsertEnd effectively places the item
+ * in the list position pointed to by pxIndex.  This means that every other
+ * item within the list will be returned by listGET_OWNER_OF_NEXT_ENTRY before
+ * the pxIndex parameter again points to the item being inserted.
+ *
+ * @param pxList The list into which the item is to be inserted.
+ *
+ * @param pxNewListItem The list item to be inserted into the list.
+ *
+ * \page vListInsertEnd vListInsertEnd
+ * \ingroup LinkedList
+ */
+void vListInsertEnd( List_t * const pxList, ListItem_t * const pxNewListItem ) PRIVILEGED_FUNCTION;
+
+/*
+ * Remove an item from a list.  The list item has a pointer to the list that
+ * it is in, so only the list item need be passed into the function.
+ *
+ * @param uxListRemove The item to be removed.  The item will remove itself from
+ * the list pointed to by it's pxContainer parameter.
+ *
+ * @return The number of items that remain in the list after the list item has
+ * been removed.
+ *
+ * \page uxListRemove uxListRemove
+ * \ingroup LinkedList
+ */
+UBaseType_t uxListRemove( ListItem_t * const pxItemToRemove ) PRIVILEGED_FUNCTION;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/mpu_prototypes.h b/STM32F1/libraries/FreeRTOS900/utility/mpu_prototypes.h
new file mode 100644
index 000000000..8f7500b02
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/mpu_prototypes.h
@@ -0,0 +1,177 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/*
+ * When the MPU is used the standard (non MPU) API functions are mapped to
+ * equivalents that start "MPU_", the prototypes for which are defined in this
+ * header files.  This will cause the application code to call the MPU_ version
+ * which wraps the non-MPU version with privilege promoting then demoting code,
+ * so the kernel code always runs will full privileges.
+ */
+
+
+#ifndef MPU_PROTOTYPES_H
+#define MPU_PROTOTYPES_H
+
+/* MPU versions of tasks.h API function. */
+BaseType_t MPU_xTaskCreate( TaskFunction_t pxTaskCode, const char * const pcName, const uint16_t usStackDepth, void * const pvParameters, UBaseType_t uxPriority, TaskHandle_t * const pxCreatedTask );
+TaskHandle_t MPU_xTaskCreateStatic( TaskFunction_t pxTaskCode, const char * const pcName, const uint32_t ulStackDepth, void * const pvParameters, UBaseType_t uxPriority, StackType_t * const puxStackBuffer, StaticTask_t * const pxTaskBuffer );
+BaseType_t MPU_xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask );
+void MPU_vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );
+void MPU_vTaskDelete( TaskHandle_t xTaskToDelete );
+void MPU_vTaskDelay( const TickType_t xTicksToDelay );
+void MPU_vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement );
+BaseType_t MPU_xTaskAbortDelay( TaskHandle_t xTask );
+UBaseType_t MPU_uxTaskPriorityGet( TaskHandle_t xTask );
+eTaskState MPU_eTaskGetState( TaskHandle_t xTask );
+void MPU_vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );
+void MPU_vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );
+void MPU_vTaskSuspend( TaskHandle_t xTaskToSuspend );
+void MPU_vTaskResume( TaskHandle_t xTaskToResume );
+void MPU_vTaskStartScheduler( void );
+void MPU_vTaskSuspendAll( void );
+BaseType_t MPU_xTaskResumeAll( void );
+TickType_t MPU_xTaskGetTickCount( void );
+UBaseType_t MPU_uxTaskGetNumberOfTasks( void );
+char * MPU_pcTaskGetName( TaskHandle_t xTaskToQuery );
+TaskHandle_t MPU_xTaskGetHandle( const char *pcNameToQuery );
+UBaseType_t MPU_uxTaskGetStackHighWaterMark( TaskHandle_t xTask );
+void MPU_vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );
+TaskHookFunction_t MPU_xTaskGetApplicationTaskTag( TaskHandle_t xTask );
+void MPU_vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue );
+void * MPU_pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex );
+BaseType_t MPU_xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );
+TaskHandle_t MPU_xTaskGetIdleTaskHandle( void );
+UBaseType_t MPU_uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime );
+void MPU_vTaskList( char * pcWriteBuffer );
+void MPU_vTaskGetRunTimeStats( char *pcWriteBuffer );
+BaseType_t MPU_xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue );
+BaseType_t MPU_xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );
+uint32_t MPU_ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );
+BaseType_t MPU_xTaskNotifyStateClear( TaskHandle_t xTask );
+BaseType_t MPU_xTaskIncrementTick( void );
+TaskHandle_t MPU_xTaskGetCurrentTaskHandle( void );
+void MPU_vTaskSetTimeOutState( TimeOut_t * const pxTimeOut );
+BaseType_t MPU_xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait );
+void MPU_vTaskMissedYield( void );
+BaseType_t MPU_xTaskGetSchedulerState( void );
+
+/* MPU versions of queue.h API function. */
+BaseType_t MPU_xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition );
+BaseType_t MPU_xQueueGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, const BaseType_t xJustPeek );
+UBaseType_t MPU_uxQueueMessagesWaiting( const QueueHandle_t xQueue );
+UBaseType_t MPU_uxQueueSpacesAvailable( const QueueHandle_t xQueue );
+void MPU_vQueueDelete( QueueHandle_t xQueue );
+QueueHandle_t MPU_xQueueCreateMutex( const uint8_t ucQueueType );
+QueueHandle_t MPU_xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue );
+QueueHandle_t MPU_xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount );
+QueueHandle_t MPU_xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue );
+void* MPU_xQueueGetMutexHolder( QueueHandle_t xSemaphore );
+BaseType_t MPU_xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait );
+BaseType_t MPU_xQueueGiveMutexRecursive( QueueHandle_t pxMutex );
+void MPU_vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName );
+void MPU_vQueueUnregisterQueue( QueueHandle_t xQueue );
+const char * MPU_pcQueueGetName( QueueHandle_t xQueue );
+QueueHandle_t MPU_xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType );
+QueueHandle_t MPU_xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType );
+QueueSetHandle_t MPU_xQueueCreateSet( const UBaseType_t uxEventQueueLength );
+BaseType_t MPU_xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet );
+BaseType_t MPU_xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet );
+QueueSetMemberHandle_t MPU_xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait );
+BaseType_t MPU_xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue );
+void MPU_vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber );
+UBaseType_t MPU_uxQueueGetQueueNumber( QueueHandle_t xQueue );
+uint8_t MPU_ucQueueGetQueueType( QueueHandle_t xQueue );
+
+/* MPU versions of timers.h API function. */
+TimerHandle_t MPU_xTimerCreate(	const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction );
+TimerHandle_t MPU_xTimerCreateStatic(	const char * const pcTimerName, const TickType_t xTimerPeriodInTicks, const UBaseType_t uxAutoReload, void * const pvTimerID, TimerCallbackFunction_t pxCallbackFunction, StaticTimer_t *pxTimerBuffer );
+void * MPU_pvTimerGetTimerID( const TimerHandle_t xTimer );
+void MPU_vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );
+BaseType_t MPU_xTimerIsTimerActive( TimerHandle_t xTimer );
+TaskHandle_t MPU_xTimerGetTimerDaemonTaskHandle( void );
+BaseType_t MPU_xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait );
+const char * MPU_pcTimerGetName( TimerHandle_t xTimer );
+TickType_t MPU_xTimerGetPeriod( TimerHandle_t xTimer );
+TickType_t MPU_xTimerGetExpiryTime( TimerHandle_t xTimer );
+BaseType_t MPU_xTimerCreateTimerTask( void );
+BaseType_t MPU_xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait );
+
+/* MPU versions of event_group.h API function. */
+EventGroupHandle_t MPU_xEventGroupCreate( void );
+EventGroupHandle_t MPU_xEventGroupCreateStatic( StaticEventGroup_t *pxEventGroupBuffer );
+EventBits_t MPU_xEventGroupWaitBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToWaitFor, const BaseType_t xClearOnExit, const BaseType_t xWaitForAllBits, TickType_t xTicksToWait );
+EventBits_t MPU_xEventGroupClearBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToClear );
+EventBits_t MPU_xEventGroupSetBits( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet );
+EventBits_t MPU_xEventGroupSync( EventGroupHandle_t xEventGroup, const EventBits_t uxBitsToSet, const EventBits_t uxBitsToWaitFor, TickType_t xTicksToWait );
+void MPU_vEventGroupDelete( EventGroupHandle_t xEventGroup );
+UBaseType_t MPU_uxEventGroupGetNumber( void* xEventGroup );
+
+#endif /* MPU_PROTOTYPES_H */
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/mpu_wrappers.h b/STM32F1/libraries/FreeRTOS900/utility/mpu_wrappers.h
new file mode 100644
index 000000000..78f5a9aea
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/mpu_wrappers.h
@@ -0,0 +1,201 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#ifndef MPU_WRAPPERS_H
+#define MPU_WRAPPERS_H
+
+/* This file redefines API functions to be called through a wrapper macro, but
+only for ports that are using the MPU. */
+#ifdef portUSING_MPU_WRAPPERS
+
+	/* MPU_WRAPPERS_INCLUDED_FROM_API_FILE will be defined when this file is
+	included from queue.c or task.c to prevent it from having an effect within
+	those files. */
+	#ifndef MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+		/*
+		 * Map standard (non MPU) API functions to equivalents that start
+		 * "MPU_".  This will cause the application code to call the MPU_
+		 * version, which wraps the non-MPU version with privilege promoting
+		 * then demoting code, so the kernel code always runs will full
+		 * privileges.
+		 */
+
+		/* Map standard tasks.h API functions to the MPU equivalents. */
+		#define xTaskCreate								MPU_xTaskCreate
+		#define xTaskCreateStatic						MPU_xTaskCreateStatic
+		#define xTaskCreateRestricted					MPU_xTaskCreateRestricted
+		#define vTaskAllocateMPURegions					MPU_vTaskAllocateMPURegions
+		#define vTaskDelete								MPU_vTaskDelete
+		#define vTaskDelay								MPU_vTaskDelay
+		#define vTaskDelayUntil							MPU_vTaskDelayUntil
+		#define xTaskAbortDelay							MPU_xTaskAbortDelay
+		#define uxTaskPriorityGet						MPU_uxTaskPriorityGet
+		#define eTaskGetState							MPU_eTaskGetState
+		#define vTaskGetInfo							MPU_vTaskGetInfo
+		#define vTaskPrioritySet						MPU_vTaskPrioritySet
+		#define vTaskSuspend							MPU_vTaskSuspend
+		#define vTaskResume								MPU_vTaskResume
+		#define vTaskSuspendAll							MPU_vTaskSuspendAll
+		#define xTaskResumeAll							MPU_xTaskResumeAll
+		#define xTaskGetTickCount						MPU_xTaskGetTickCount
+		#define uxTaskGetNumberOfTasks					MPU_uxTaskGetNumberOfTasks
+		#define pcTaskGetName							MPU_pcTaskGetName
+		#define xTaskGetHandle							MPU_xTaskGetHandle
+		#define uxTaskGetStackHighWaterMark				MPU_uxTaskGetStackHighWaterMark
+		#define vTaskSetApplicationTaskTag				MPU_vTaskSetApplicationTaskTag
+		#define xTaskGetApplicationTaskTag				MPU_xTaskGetApplicationTaskTag
+		#define vTaskSetThreadLocalStoragePointer		MPU_vTaskSetThreadLocalStoragePointer
+		#define pvTaskGetThreadLocalStoragePointer		MPU_pvTaskGetThreadLocalStoragePointer
+		#define xTaskCallApplicationTaskHook			MPU_xTaskCallApplicationTaskHook
+		#define xTaskGetIdleTaskHandle					MPU_xTaskGetIdleTaskHandle
+		#define uxTaskGetSystemState					MPU_uxTaskGetSystemState
+		#define vTaskList								MPU_vTaskList
+		#define vTaskGetRunTimeStats					MPU_vTaskGetRunTimeStats
+		#define xTaskGenericNotify						MPU_xTaskGenericNotify
+		#define xTaskNotifyWait							MPU_xTaskNotifyWait
+		#define ulTaskNotifyTake						MPU_ulTaskNotifyTake
+		#define xTaskNotifyStateClear					MPU_xTaskNotifyStateClear
+
+		#define xTaskGetCurrentTaskHandle				MPU_xTaskGetCurrentTaskHandle
+		#define vTaskSetTimeOutState					MPU_vTaskSetTimeOutState
+		#define xTaskCheckForTimeOut					MPU_xTaskCheckForTimeOut
+		#define xTaskGetSchedulerState					MPU_xTaskGetSchedulerState
+
+		/* Map standard queue.h API functions to the MPU equivalents. */
+		#define xQueueGenericSend						MPU_xQueueGenericSend
+		#define xQueueGenericReceive					MPU_xQueueGenericReceive
+		#define uxQueueMessagesWaiting					MPU_uxQueueMessagesWaiting
+		#define uxQueueSpacesAvailable					MPU_uxQueueSpacesAvailable
+		#define vQueueDelete							MPU_vQueueDelete
+		#define xQueueCreateMutex						MPU_xQueueCreateMutex
+		#define xQueueCreateMutexStatic					MPU_xQueueCreateMutexStatic
+		#define xQueueCreateCountingSemaphore			MPU_xQueueCreateCountingSemaphore
+		#define xQueueCreateCountingSemaphoreStatic		MPU_xQueueCreateCountingSemaphoreStatic
+		#define xQueueGetMutexHolder					MPU_xQueueGetMutexHolder
+		#define xQueueTakeMutexRecursive				MPU_xQueueTakeMutexRecursive
+		#define xQueueGiveMutexRecursive				MPU_xQueueGiveMutexRecursive
+		#define xQueueGenericCreate						MPU_xQueueGenericCreate
+		#define xQueueGenericCreateStatic				MPU_xQueueGenericCreateStatic
+		#define xQueueCreateSet							MPU_xQueueCreateSet
+		#define xQueueAddToSet							MPU_xQueueAddToSet
+		#define xQueueRemoveFromSet						MPU_xQueueRemoveFromSet
+		#define xQueueSelectFromSet						MPU_xQueueSelectFromSet
+		#define xQueueGenericReset						MPU_xQueueGenericReset
+
+		#if( configQUEUE_REGISTRY_SIZE > 0 )
+			#define vQueueAddToRegistry						MPU_vQueueAddToRegistry
+			#define vQueueUnregisterQueue					MPU_vQueueUnregisterQueue
+			#define pcQueueGetName							MPU_pcQueueGetName
+		#endif
+
+		/* Map standard timer.h API functions to the MPU equivalents. */
+		#define xTimerCreate							MPU_xTimerCreate
+		#define xTimerCreateStatic						MPU_xTimerCreateStatic
+		#define pvTimerGetTimerID						MPU_pvTimerGetTimerID
+		#define vTimerSetTimerID						MPU_vTimerSetTimerID
+		#define xTimerIsTimerActive						MPU_xTimerIsTimerActive
+		#define xTimerGetTimerDaemonTaskHandle			MPU_xTimerGetTimerDaemonTaskHandle
+		#define xTimerPendFunctionCall					MPU_xTimerPendFunctionCall
+		#define pcTimerGetName							MPU_pcTimerGetName
+		#define xTimerGetPeriod							MPU_xTimerGetPeriod
+		#define xTimerGetExpiryTime						MPU_xTimerGetExpiryTime
+		#define xTimerGenericCommand					MPU_xTimerGenericCommand
+
+		/* Map standard event_group.h API functions to the MPU equivalents. */
+		#define xEventGroupCreate						MPU_xEventGroupCreate
+		#define xEventGroupCreateStatic					MPU_xEventGroupCreateStatic
+		#define xEventGroupWaitBits						MPU_xEventGroupWaitBits
+		#define xEventGroupClearBits					MPU_xEventGroupClearBits
+		#define xEventGroupSetBits						MPU_xEventGroupSetBits
+		#define xEventGroupSync							MPU_xEventGroupSync
+		#define vEventGroupDelete						MPU_vEventGroupDelete
+
+		/* Remove the privileged function macro. */
+		#define PRIVILEGED_FUNCTION
+
+	#else /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+		/* Ensure API functions go in the privileged execution section. */
+		#define PRIVILEGED_FUNCTION __attribute__((section("privileged_functions")))
+		#define PRIVILEGED_DATA __attribute__((section("privileged_data")))
+
+	#endif /* MPU_WRAPPERS_INCLUDED_FROM_API_FILE */
+
+#else /* portUSING_MPU_WRAPPERS */
+
+	#define PRIVILEGED_FUNCTION
+	#define PRIVILEGED_DATA
+	#define portUSING_MPU_WRAPPERS 0
+
+#endif /* portUSING_MPU_WRAPPERS */
+
+
+#endif /* MPU_WRAPPERS_H */
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/port.c b/STM32F1/libraries/FreeRTOS900/utility/port.c
new file mode 100644
index 000000000..6cfebe8d2
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/port.c
@@ -0,0 +1,717 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/*-----------------------------------------------------------
+ * Implementation of functions defined in portable.h for the ARM CM3 port.
+ *----------------------------------------------------------*/
+
+/* Scheduler includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+
+/* For backward compatibility, ensure configKERNEL_INTERRUPT_PRIORITY is
+defined.  The value should also ensure backward compatibility.
+FreeRTOS.org versions prior to V4.4.0 did not include this definition. */
+#ifndef configKERNEL_INTERRUPT_PRIORITY
+	#define configKERNEL_INTERRUPT_PRIORITY 255
+#endif
+
+#ifndef configSYSTICK_CLOCK_HZ
+	#define configSYSTICK_CLOCK_HZ configCPU_CLOCK_HZ
+	/* Ensure the SysTick is clocked at the same frequency as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 1UL << 2UL )
+#else
+	/* The way the SysTick is clocked is not modified in case it is not the same
+	as the core. */
+	#define portNVIC_SYSTICK_CLK_BIT	( 0 )
+#endif
+
+/* Constants required to manipulate the core.  Registers first... */
+#define portNVIC_SYSTICK_CTRL_REG			( * ( ( volatile uint32_t * ) 0xe000e010 ) )
+#define portNVIC_SYSTICK_LOAD_REG			( * ( ( volatile uint32_t * ) 0xe000e014 ) )
+#define portNVIC_SYSTICK_CURRENT_VALUE_REG	( * ( ( volatile uint32_t * ) 0xe000e018 ) )
+#define portNVIC_SYSPRI2_REG				( * ( ( volatile uint32_t * ) 0xe000ed20 ) )
+/* ...then bits in the registers. */
+#define portNVIC_SYSTICK_INT_BIT			( 1UL << 1UL )
+#define portNVIC_SYSTICK_ENABLE_BIT			( 1UL << 0UL )
+#define portNVIC_SYSTICK_COUNT_FLAG_BIT		( 1UL << 16UL )
+#define portNVIC_PENDSVCLEAR_BIT 			( 1UL << 27UL )
+#define portNVIC_PEND_SYSTICK_CLEAR_BIT		( 1UL << 25UL )
+
+#define portNVIC_PENDSV_PRI					( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 16UL )
+#define portNVIC_SYSTICK_PRI				( ( ( uint32_t ) configKERNEL_INTERRUPT_PRIORITY ) << 24UL )
+
+/* Constants required to check the validity of an interrupt priority. */
+#define portFIRST_USER_INTERRUPT_NUMBER		( 16 )
+#define portNVIC_IP_REGISTERS_OFFSET_16 	( 0xE000E3F0 )
+#define portAIRCR_REG						( * ( ( volatile uint32_t * ) 0xE000ED0C ) )
+#define portMAX_8_BIT_VALUE					( ( uint8_t ) 0xff )
+#define portTOP_BIT_OF_BYTE					( ( uint8_t ) 0x80 )
+#define portMAX_PRIGROUP_BITS				( ( uint8_t ) 7 )
+#define portPRIORITY_GROUP_MASK				( 0x07UL << 8UL )
+#define portPRIGROUP_SHIFT					( 8UL )
+
+/* Masks off all bits but the VECTACTIVE bits in the ICSR register. */
+#define portVECTACTIVE_MASK					( 0xFFUL )
+
+/* Constants required to set up the initial stack. */
+#define portINITIAL_XPSR					( 0x01000000UL )
+
+/* The systick is a 24-bit counter. */
+#define portMAX_24_BIT_NUMBER				( 0xffffffUL )
+
+/* A fiddle factor to estimate the number of SysTick counts that would have
+occurred while the SysTick counter is stopped during tickless idle
+calculations. */
+#define portMISSED_COUNTS_FACTOR			( 45UL )
+
+/* For strict compliance with the Cortex-M spec the task start address should
+have bit-0 clear, as it is loaded into the PC on exit from an ISR. */
+#define portSTART_ADDRESS_MASK				( ( StackType_t ) 0xfffffffeUL )
+
+/* Let the user override the pre-loading of the initial LR with the address of
+prvTaskExitError() in case it messes up unwinding of the stack in the
+debugger. */
+#ifdef configTASK_RETURN_ADDRESS
+	#define portTASK_RETURN_ADDRESS	configTASK_RETURN_ADDRESS
+#else
+	#define portTASK_RETURN_ADDRESS	prvTaskExitError
+#endif
+
+/* Each task maintains its own interrupt status in the critical nesting
+variable. */
+static UBaseType_t uxCriticalNesting = 0xaaaaaaaa;
+
+/*
+ * Setup the timer to generate the tick interrupts.  The implementation in this
+ * file is weak to allow application writers to change the timer used to
+ * generate the tick interrupt.
+ */
+void vPortSetupTimerInterrupt( void );
+
+/*
+ * Exception handlers.
+ */
+void xPortPendSVHandler( void ) __attribute__ (( naked ));
+void xPortSysTickHandler( void );
+void vPortSVCHandler( void ) __attribute__ (( naked ));
+
+/*
+ * Start first task is a separate function so it can be tested in isolation.
+ */
+static void prvPortStartFirstTask( void ) __attribute__ (( naked ));
+
+/*
+ * Used to catch tasks that attempt to return from their implementing function.
+ */
+static void prvTaskExitError( void );
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The number of SysTick increments that make up one tick period.
+ */
+#if configUSE_TICKLESS_IDLE == 1
+	static uint32_t ulTimerCountsForOneTick = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * The maximum number of tick periods that can be suppressed is limited by the
+ * 24 bit resolution of the SysTick timer.
+ */
+#if configUSE_TICKLESS_IDLE == 1
+	static uint32_t xMaximumPossibleSuppressedTicks = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Compensate for the CPU cycles that pass while the SysTick is stopped (low
+ * power functionality only.
+ */
+#if configUSE_TICKLESS_IDLE == 1
+	static uint32_t ulStoppedTimerCompensation = 0;
+#endif /* configUSE_TICKLESS_IDLE */
+
+/*
+ * Used by the portASSERT_IF_INTERRUPT_PRIORITY_INVALID() macro to ensure
+ * FreeRTOS API functions are not called from interrupts that have been assigned
+ * a priority above configMAX_SYSCALL_INTERRUPT_PRIORITY.
+ */
+#if ( configASSERT_DEFINED == 1 )
+	 static uint8_t ucMaxSysCallPriority = 0;
+	 static uint32_t ulMaxPRIGROUPValue = 0;
+	 static const volatile uint8_t * const pcInterruptPriorityRegisters = ( const volatile uint8_t * const ) portNVIC_IP_REGISTERS_OFFSET_16;
+#endif /* configASSERT_DEFINED */
+
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters )
+{
+	/* Simulate the stack frame as it would be created by a context switch
+	interrupt. */
+	pxTopOfStack--; /* Offset added to account for the way the MCU uses the stack on entry/exit of interrupts. */
+	*pxTopOfStack = portINITIAL_XPSR;	/* xPSR */
+	pxTopOfStack--;
+	*pxTopOfStack = ( ( StackType_t ) pxCode ) & portSTART_ADDRESS_MASK;	/* PC */
+	pxTopOfStack--;
+	*pxTopOfStack = ( StackType_t ) portTASK_RETURN_ADDRESS;	/* LR */
+	pxTopOfStack -= 5;	/* R12, R3, R2 and R1. */
+	*pxTopOfStack = ( StackType_t ) pvParameters;	/* R0 */
+	pxTopOfStack -= 8;	/* R11, R10, R9, R8, R7, R6, R5 and R4. */
+
+	return pxTopOfStack;
+}
+/*-----------------------------------------------------------*/
+
+static void prvTaskExitError( void )
+{
+	/* A function that implements a task must not exit or attempt to return to
+	its caller as there is nothing to return to.  If a task wants to exit it
+	should instead call vTaskDelete( NULL ).
+
+	Artificially force an assert() to be triggered if configASSERT() is
+	defined, then stop here so application writers can catch the error. */
+	configASSERT( uxCriticalNesting == ~0UL );
+	portDISABLE_INTERRUPTS();
+	for( ;; );
+}
+/*-----------------------------------------------------------*/
+
+// !!! Maple
+//void vPortSVCHandler( void )
+void __exc_svc( void )
+// !!! Maple
+{
+	__asm volatile (
+					"	ldr	r3, pxCurrentTCBConst2		\n" /* Restore the context. */
+					"	ldr r1, [r3]					\n" /* Use pxCurrentTCBConst to get the pxCurrentTCB address. */
+					"	ldr r0, [r1]					\n" /* The first item in pxCurrentTCB is the task top of stack. */
+					"	ldmia r0!, {r4-r11}				\n" /* Pop the registers that are not automatically saved on exception entry and the critical nesting count. */
+					"	msr psp, r0						\n" /* Restore the task stack pointer. */
+					"	isb								\n"
+					"	mov r0, #0 						\n"
+					"	msr	basepri, r0					\n"
+					"	orr r14, #0xd					\n"
+					"	bx r14							\n"
+					"									\n"
+					"	.align 4						\n"
+					"pxCurrentTCBConst2: .word pxCurrentTCB				\n"
+				);
+}
+/*-----------------------------------------------------------*/
+
+static void prvPortStartFirstTask( void )
+{
+	__asm volatile(
+					" ldr r0, =0xE000ED08 	\n" /* Use the NVIC offset register to locate the stack. */
+					" ldr r0, [r0] 			\n"
+					" ldr r0, [r0] 			\n"
+					" msr msp, r0			\n" /* Set the msp back to the start of the stack. */
+					" cpsie i				\n" /* Globally enable interrupts. */
+					" cpsie f				\n"
+					" dsb					\n"
+					" isb					\n"
+					" svc 0					\n" /* System call to start first task. */
+					" nop					\n"
+				);
+}
+/*-----------------------------------------------------------*/
+
+/*
+ * See header file for description.
+ */
+BaseType_t xPortStartScheduler( void )
+{
+	/* configMAX_SYSCALL_INTERRUPT_PRIORITY must not be set to 0.
+	See http://www.FreeRTOS.org/RTOS-Cortex-M3-M4.html */
+	configASSERT( configMAX_SYSCALL_INTERRUPT_PRIORITY );
+
+	#if( configASSERT_DEFINED == 1 )
+	{
+		volatile uint32_t ulOriginalPriority;
+		volatile uint8_t * const pucFirstUserPriorityRegister = ( volatile uint8_t * const ) ( portNVIC_IP_REGISTERS_OFFSET_16 + portFIRST_USER_INTERRUPT_NUMBER );
+		volatile uint8_t ucMaxPriorityValue;
+
+		/* Determine the maximum priority from which ISR safe FreeRTOS API
+		functions can be called.  ISR safe functions are those that end in
+		"FromISR".  FreeRTOS maintains separate thread and ISR API functions to
+		ensure interrupt entry is as fast and simple as possible.
+
+		Save the interrupt priority value that is about to be clobbered. */
+		ulOriginalPriority = *pucFirstUserPriorityRegister;
+
+		/* Determine the number of priority bits available.  First write to all
+		possible bits. */
+		*pucFirstUserPriorityRegister = portMAX_8_BIT_VALUE;
+
+		/* Read the value back to see how many bits stuck. */
+		ucMaxPriorityValue = *pucFirstUserPriorityRegister;
+
+		/* Use the same mask on the maximum system call priority. */
+		ucMaxSysCallPriority = configMAX_SYSCALL_INTERRUPT_PRIORITY & ucMaxPriorityValue;
+
+		/* Calculate the maximum acceptable priority group value for the number
+		of bits read back. */
+		ulMaxPRIGROUPValue = portMAX_PRIGROUP_BITS;
+		while( ( ucMaxPriorityValue & portTOP_BIT_OF_BYTE ) == portTOP_BIT_OF_BYTE )
+		{
+			ulMaxPRIGROUPValue--;
+			ucMaxPriorityValue <<= ( uint8_t ) 0x01;
+		}
+
+		/* Shift the priority group value back to its position within the AIRCR
+		register. */
+		ulMaxPRIGROUPValue <<= portPRIGROUP_SHIFT;
+		ulMaxPRIGROUPValue &= portPRIORITY_GROUP_MASK;
+
+		/* Restore the clobbered interrupt priority register to its original
+		value. */
+		*pucFirstUserPriorityRegister = ulOriginalPriority;
+	}
+	#endif /* conifgASSERT_DEFINED */
+
+	/* Make PendSV and SysTick the lowest priority interrupts. */
+	portNVIC_SYSPRI2_REG |= portNVIC_PENDSV_PRI;
+	portNVIC_SYSPRI2_REG |= portNVIC_SYSTICK_PRI;
+
+	/* Start the timer that generates the tick ISR.  Interrupts are disabled
+	here already. */
+	//vPortSetupTimerInterrupt();
+	systick_attach_callback(&xPortSysTickHandler);
+	// !!! Maple
+	
+	/* Initialise the critical nesting count ready for the first task. */
+	uxCriticalNesting = 0;
+
+	/* Start the first task. */
+	prvPortStartFirstTask();
+
+	/* Should never get here as the tasks will now be executing!  Call the task
+	exit error function to prevent compiler warnings about a static function
+	not being called in the case that the application writer overrides this
+	functionality by defining configTASK_RETURN_ADDRESS. */
+	prvTaskExitError();
+
+	/* Should not get here! */
+	return 0;
+}
+/*-----------------------------------------------------------*/
+
+void vPortEndScheduler( void )
+{
+	/* Not implemented in ports where there is nothing to return to.
+	Artificially force an assert. */
+	configASSERT( uxCriticalNesting == 1000UL );
+}
+/*-----------------------------------------------------------*/
+
+void vPortEnterCritical( void )
+{
+	portDISABLE_INTERRUPTS();
+	uxCriticalNesting++;
+
+	/* This is not the interrupt safe version of the enter critical function so
+	assert() if it is being called from an interrupt context.  Only API
+	functions that end in "FromISR" can be used in an interrupt.  Only assert if
+	the critical nesting count is 1 to protect against recursive calls if the
+	assert function also uses a critical section. */
+	if( uxCriticalNesting == 1 )
+	{
+		configASSERT( ( portNVIC_INT_CTRL_REG & portVECTACTIVE_MASK ) == 0 );
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vPortExitCritical( void )
+{
+	configASSERT( uxCriticalNesting );
+	uxCriticalNesting--;
+	if( uxCriticalNesting == 0 )
+	{
+		portENABLE_INTERRUPTS();
+	}
+}
+/*-----------------------------------------------------------*/
+
+	// !!! Maple
+	//void xPortPendSVHandler( void )
+	void __exc_pendsv( void )
+	{
+	/* This is a naked function. */
+
+	__asm volatile
+	(
+	"	mrs r0, psp							\n"
+	"	isb									\n"
+	"										\n"
+	"	ldr	r3, pxCurrentTCBConst			\n" /* Get the location of the current TCB. */
+	"	ldr	r2, [r3]						\n"
+	"										\n"
+	"	stmdb r0!, {r4-r11}					\n" /* Save the remaining registers. */
+	"	str r0, [r2]						\n" /* Save the new top of stack into the first member of the TCB. */
+	"										\n"
+	"	stmdb sp!, {r3, r14}				\n"
+	"	mov r0, %0							\n"
+	"	msr basepri, r0						\n"
+	"	bl vTaskSwitchContext				\n"
+	"	mov r0, #0							\n"
+	"	msr basepri, r0						\n"
+	"	ldmia sp!, {r3, r14}				\n"
+	"										\n"	/* Restore the context, including the critical nesting count. */
+	"	ldr r1, [r3]						\n"
+	"	ldr r0, [r1]						\n" /* The first item in pxCurrentTCB is the task top of stack. */
+	"	ldmia r0!, {r4-r11}					\n" /* Pop the registers. */
+	"	msr psp, r0							\n"
+	"	isb									\n"
+	"	bx r14								\n"
+	"										\n"
+	"	.align 4							\n"
+	"pxCurrentTCBConst: .word pxCurrentTCB	\n"
+	::"i"(configMAX_SYSCALL_INTERRUPT_PRIORITY)
+	);
+}
+/*-----------------------------------------------------------*/
+
+void xPortSysTickHandler( void )
+{
+	/* The SysTick runs at the lowest interrupt priority, so when this interrupt
+	executes all interrupts must be unmasked.  There is therefore no need to
+	save and then restore the interrupt mask value as its value is already
+	known. */
+	portDISABLE_INTERRUPTS();
+	{
+		/* Increment the RTOS tick. */
+		if( xTaskIncrementTick() != pdFALSE )
+		{
+			/* A context switch is required.  Context switching is performed in
+			the PendSV interrupt.  Pend the PendSV interrupt. */
+			portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;
+		}
+	}
+	portENABLE_INTERRUPTS();
+}
+/*-----------------------------------------------------------*/
+
+#if configUSE_TICKLESS_IDLE == 1
+
+	__attribute__((weak)) void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime )
+	{
+	uint32_t ulReloadValue, ulCompleteTickPeriods, ulCompletedSysTickDecrements, ulSysTickCTRL;
+	TickType_t xModifiableIdleTime;
+
+		/* Make sure the SysTick reload value does not overflow the counter. */
+		if( xExpectedIdleTime > xMaximumPossibleSuppressedTicks )
+		{
+			xExpectedIdleTime = xMaximumPossibleSuppressedTicks;
+		}
+
+		/* Stop the SysTick momentarily.  The time the SysTick is stopped for
+		is accounted for as best it can be, but using the tickless mode will
+		inevitably result in some tiny drift of the time maintained by the
+		kernel with respect to calendar time. */
+		portNVIC_SYSTICK_CTRL_REG &= ~portNVIC_SYSTICK_ENABLE_BIT;
+
+		/* Calculate the reload value required to wait xExpectedIdleTime
+		tick periods.  -1 is used because this code will execute part way
+		through one of the tick periods. */
+		ulReloadValue = portNVIC_SYSTICK_CURRENT_VALUE_REG + ( ulTimerCountsForOneTick * ( xExpectedIdleTime - 1UL ) );
+		if( ulReloadValue > ulStoppedTimerCompensation )
+		{
+			ulReloadValue -= ulStoppedTimerCompensation;
+		}
+
+		/* Enter a critical section but don't use the taskENTER_CRITICAL()
+		method as that will mask interrupts that should exit sleep mode. */
+		__asm volatile( "cpsid i" );
+		__asm volatile( "dsb" );
+		__asm volatile( "isb" );
+
+		/* If a context switch is pending or a task is waiting for the scheduler
+		to be unsuspended then abandon the low power entry. */
+		if( eTaskConfirmSleepModeStatus() == eAbortSleep )
+		{
+			/* Restart from whatever is left in the count register to complete
+			this tick period. */
+			portNVIC_SYSTICK_LOAD_REG = portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Reset the reload register to the value required for normal tick
+			periods. */
+			portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+
+			/* Re-enable interrupts - see comments above the cpsid instruction()
+			above. */
+			__asm volatile( "cpsie i" );
+		}
+		else
+		{
+			/* Set the new reload value. */
+			portNVIC_SYSTICK_LOAD_REG = ulReloadValue;
+
+			/* Clear the SysTick count flag and set the count value back to
+			zero. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+
+			/* Restart SysTick. */
+			portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+
+			/* Sleep until something happens.  configPRE_SLEEP_PROCESSING() can
+			set its parameter to 0 to indicate that its implementation contains
+			its own wait for interrupt or wait for event instruction, and so wfi
+			should not be executed again.  However, the original expected idle
+			time variable must remain unmodified, so a copy is taken. */
+			xModifiableIdleTime = xExpectedIdleTime;
+			configPRE_SLEEP_PROCESSING( xModifiableIdleTime );
+			if( xModifiableIdleTime > 0 )
+			{
+				__asm volatile( "dsb" );
+				__asm volatile( "wfi" );
+				__asm volatile( "isb" );
+			}
+			configPOST_SLEEP_PROCESSING( xExpectedIdleTime );
+
+			/* Stop SysTick.  Again, the time the SysTick is stopped for is
+			accounted for as best it can be, but using the tickless mode will
+			inevitably result in some tiny drift of the time maintained by the
+			kernel with respect to calendar time. */
+			ulSysTickCTRL = portNVIC_SYSTICK_CTRL_REG;
+			portNVIC_SYSTICK_CTRL_REG = ( ulSysTickCTRL & ~portNVIC_SYSTICK_ENABLE_BIT );
+
+			/* Re-enable interrupts - see comments above the cpsid instruction()
+			above. */
+			__asm volatile( "cpsie i" );
+
+			if( ( ulSysTickCTRL & portNVIC_SYSTICK_COUNT_FLAG_BIT ) != 0 )
+			{
+				uint32_t ulCalculatedLoadValue;
+
+				/* The tick interrupt has already executed, and the SysTick
+				count reloaded with ulReloadValue.  Reset the
+				portNVIC_SYSTICK_LOAD_REG with whatever remains of this tick
+				period. */
+				ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL ) - ( ulReloadValue - portNVIC_SYSTICK_CURRENT_VALUE_REG );
+
+				/* Don't allow a tiny value, or values that have somehow
+				underflowed because the post sleep hook did something
+				that took too long. */
+				if( ( ulCalculatedLoadValue < ulStoppedTimerCompensation ) || ( ulCalculatedLoadValue > ulTimerCountsForOneTick ) )
+				{
+					ulCalculatedLoadValue = ( ulTimerCountsForOneTick - 1UL );
+				}
+
+				portNVIC_SYSTICK_LOAD_REG = ulCalculatedLoadValue;
+
+				/* The tick interrupt handler will already have pended the tick
+				processing in the kernel.  As the pending tick will be
+				processed as soon as this function exits, the tick value
+				maintained by the tick is stepped forward by one less than the
+				time spent waiting. */
+				ulCompleteTickPeriods = xExpectedIdleTime - 1UL;
+			}
+			else
+			{
+				/* Something other than the tick interrupt ended the sleep.
+				Work out how long the sleep lasted rounded to complete tick
+				periods (not the ulReload value which accounted for part
+				ticks). */
+				ulCompletedSysTickDecrements = ( xExpectedIdleTime * ulTimerCountsForOneTick ) - portNVIC_SYSTICK_CURRENT_VALUE_REG;
+
+				/* How many complete tick periods passed while the processor
+				was waiting? */
+				ulCompleteTickPeriods = ulCompletedSysTickDecrements / ulTimerCountsForOneTick;
+
+				/* The reload value is set to whatever fraction of a single tick
+				period remains. */
+				portNVIC_SYSTICK_LOAD_REG = ( ( ulCompleteTickPeriods + 1UL ) * ulTimerCountsForOneTick ) - ulCompletedSysTickDecrements;
+			}
+
+			/* Restart SysTick so it runs from portNVIC_SYSTICK_LOAD_REG
+			again, then set portNVIC_SYSTICK_LOAD_REG back to its standard
+			value.  The critical section is used to ensure the tick interrupt
+			can only execute once in the case that the reload register is near
+			zero. */
+			portNVIC_SYSTICK_CURRENT_VALUE_REG = 0UL;
+			portENTER_CRITICAL();
+			{
+				portNVIC_SYSTICK_CTRL_REG |= portNVIC_SYSTICK_ENABLE_BIT;
+				vTaskStepTick( ulCompleteTickPeriods );
+				portNVIC_SYSTICK_LOAD_REG = ulTimerCountsForOneTick - 1UL;
+			}
+			portEXIT_CRITICAL();
+		}
+	}
+
+#endif /* #if configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+/*
+ * Setup the systick timer to generate the tick interrupts at the required
+ * frequency.
+ */
+__attribute__(( weak )) void vPortSetupTimerInterrupt( void )
+{
+	/* Calculate the constants required to configure the tick interrupt. */
+	#if configUSE_TICKLESS_IDLE == 1
+	{
+		ulTimerCountsForOneTick = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ );
+		xMaximumPossibleSuppressedTicks = portMAX_24_BIT_NUMBER / ulTimerCountsForOneTick;
+		ulStoppedTimerCompensation = portMISSED_COUNTS_FACTOR / ( configCPU_CLOCK_HZ / configSYSTICK_CLOCK_HZ );
+	}
+	#endif /* configUSE_TICKLESS_IDLE */
+
+	/* Configure SysTick to interrupt at the requested rate. */
+	portNVIC_SYSTICK_LOAD_REG = ( configSYSTICK_CLOCK_HZ / configTICK_RATE_HZ ) - 1UL;
+	portNVIC_SYSTICK_CTRL_REG = ( portNVIC_SYSTICK_CLK_BIT | portNVIC_SYSTICK_INT_BIT | portNVIC_SYSTICK_ENABLE_BIT );
+}
+/*-----------------------------------------------------------*/
+
+#if( configASSERT_DEFINED == 1 )
+
+	void vPortValidateInterruptPriority( void )
+	{
+	uint32_t ulCurrentInterrupt;
+	uint8_t ucCurrentPriority;
+
+		/* Obtain the number of the currently executing interrupt. */
+		__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
+
+		/* Is the interrupt number a user defined interrupt? */
+		if( ulCurrentInterrupt >= portFIRST_USER_INTERRUPT_NUMBER )
+		{
+			/* Look up the interrupt's priority. */
+			ucCurrentPriority = pcInterruptPriorityRegisters[ ulCurrentInterrupt ];
+
+			/* The following assertion will fail if a service routine (ISR) for
+			an interrupt that has been assigned a priority above
+			configMAX_SYSCALL_INTERRUPT_PRIORITY calls an ISR safe FreeRTOS API
+			function.  ISR safe FreeRTOS API functions must *only* be called
+			from interrupts that have been assigned a priority at or below
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Numerically low interrupt priority numbers represent logically high
+			interrupt priorities, therefore the priority of the interrupt must
+			be set to a value equal to or numerically *higher* than
+			configMAX_SYSCALL_INTERRUPT_PRIORITY.
+
+			Interrupts that	use the FreeRTOS API must not be left at their
+			default priority of	zero as that is the highest possible priority,
+			which is guaranteed to be above configMAX_SYSCALL_INTERRUPT_PRIORITY,
+			and	therefore also guaranteed to be invalid.
+
+			FreeRTOS maintains separate thread and ISR API functions to ensure
+			interrupt entry is as fast and simple as possible.
+
+			The following links provide detailed information:
+			http://www.freertos.org/RTOS-Cortex-M3-M4.html
+			http://www.freertos.org/FAQHelp.html */
+			configASSERT( ucCurrentPriority >= ucMaxSysCallPriority );
+		}
+
+		/* Priority grouping:  The interrupt controller (NVIC) allows the bits
+		that define each interrupt's priority to be split between bits that
+		define the interrupt's pre-emption priority bits and bits that define
+		the interrupt's sub-priority.  For simplicity all bits must be defined
+		to be pre-emption priority bits.  The following assertion will fail if
+		this is not the case (if some bits represent a sub-priority).
+
+		If the application only uses CMSIS libraries for interrupt
+		configuration then the correct setting can be achieved on all Cortex-M
+		devices by calling NVIC_SetPriorityGrouping( 0 ); before starting the
+		scheduler.  Note however that some vendor specific peripheral libraries
+		assume a non-zero priority group setting, in which cases using a value
+		of zero will result in unpredicable behaviour. */
+		configASSERT( ( portAIRCR_REG & portPRIORITY_GROUP_MASK ) <= ulMaxPRIGROUPValue );
+	}
+
+#endif /* configASSERT_DEFINED */
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/portable.h b/STM32F1/libraries/FreeRTOS900/utility/portable.h
new file mode 100644
index 000000000..b9f8be39d
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/portable.h
@@ -0,0 +1,207 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/*-----------------------------------------------------------
+ * Portable layer API.  Each function must be defined for each port.
+ *----------------------------------------------------------*/
+
+#ifndef PORTABLE_H
+#define PORTABLE_H
+
+/* Each FreeRTOS port has a unique portmacro.h header file.  Originally a
+pre-processor definition was used to ensure the pre-processor found the correct
+portmacro.h file for the port being used.  That scheme was deprecated in favour
+of setting the compiler's include path such that it found the correct
+portmacro.h file - removing the need for the constant and allowing the
+portmacro.h file to be located anywhere in relation to the port being used.
+Purely for reasons of backward compatibility the old method is still valid, but
+to make it clear that new projects should not use it, support for the port
+specific constants has been moved into the deprecated_definitions.h header
+file. */
+#include "deprecated_definitions.h"
+
+/* If portENTER_CRITICAL is not defined then including deprecated_definitions.h
+did not result in a portmacro.h header file being included - and it should be
+included here.  In this case the path to the correct portmacro.h header file
+must be set in the compiler's include path. */
+#ifndef portENTER_CRITICAL
+	#include "portmacro.h"
+#endif
+
+#if portBYTE_ALIGNMENT == 32
+	#define portBYTE_ALIGNMENT_MASK ( 0x001f )
+#endif
+
+#if portBYTE_ALIGNMENT == 16
+	#define portBYTE_ALIGNMENT_MASK ( 0x000f )
+#endif
+
+#if portBYTE_ALIGNMENT == 8
+	#define portBYTE_ALIGNMENT_MASK ( 0x0007 )
+#endif
+
+#if portBYTE_ALIGNMENT == 4
+	#define portBYTE_ALIGNMENT_MASK	( 0x0003 )
+#endif
+
+#if portBYTE_ALIGNMENT == 2
+	#define portBYTE_ALIGNMENT_MASK	( 0x0001 )
+#endif
+
+#if portBYTE_ALIGNMENT == 1
+	#define portBYTE_ALIGNMENT_MASK	( 0x0000 )
+#endif
+
+#ifndef portBYTE_ALIGNMENT_MASK
+	#error "Invalid portBYTE_ALIGNMENT definition"
+#endif
+
+#ifndef portNUM_CONFIGURABLE_REGIONS
+	#define portNUM_CONFIGURABLE_REGIONS 1
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include "mpu_wrappers.h"
+
+/*
+ * Setup the stack of a new task so it is ready to be placed under the
+ * scheduler control.  The registers have to be placed on the stack in
+ * the order that the port expects to find them.
+ *
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters, BaseType_t xRunPrivileged ) PRIVILEGED_FUNCTION;
+#else
+	StackType_t *pxPortInitialiseStack( StackType_t *pxTopOfStack, TaskFunction_t pxCode, void *pvParameters ) PRIVILEGED_FUNCTION;
+#endif
+
+/* Used by heap_5.c. */
+typedef struct HeapRegion
+{
+	uint8_t *pucStartAddress;
+	size_t xSizeInBytes;
+} HeapRegion_t;
+
+/*
+ * Used to define multiple heap regions for use by heap_5.c.  This function
+ * must be called before any calls to pvPortMalloc() - not creating a task,
+ * queue, semaphore, mutex, software timer, event group, etc. will result in
+ * pvPortMalloc being called.
+ *
+ * pxHeapRegions passes in an array of HeapRegion_t structures - each of which
+ * defines a region of memory that can be used as the heap.  The array is
+ * terminated by a HeapRegions_t structure that has a size of 0.  The region
+ * with the lowest start address must appear first in the array.
+ */
+void vPortDefineHeapRegions( const HeapRegion_t * const pxHeapRegions ) PRIVILEGED_FUNCTION;
+
+
+/*
+ * Map to the memory management routines required for the port.
+ */
+void *pvPortMalloc( size_t xSize ) PRIVILEGED_FUNCTION;
+void vPortFree( void *pv ) PRIVILEGED_FUNCTION;
+void vPortInitialiseBlocks( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+size_t xPortGetMinimumEverFreeHeapSize( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Setup the hardware ready for the scheduler to take control.  This generally
+ * sets up a tick interrupt and sets timers for the correct tick frequency.
+ */
+BaseType_t xPortStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Undo any hardware/ISR setup that was performed by xPortStartScheduler() so
+ * the hardware is left in its original condition after the scheduler stops
+ * executing.
+ */
+void vPortEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The structures and methods of manipulating the MPU are contained within the
+ * port layer.
+ *
+ * Fills the xMPUSettings structure with the memory region information
+ * contained in xRegions.
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	struct xMEMORY_REGION;
+	void vPortStoreTaskMPUSettings( xMPU_SETTINGS *xMPUSettings, const struct xMEMORY_REGION * const xRegions, StackType_t *pxBottomOfStack, uint32_t ulStackDepth ) PRIVILEGED_FUNCTION;
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTABLE_H */
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/portmacro.h b/STM32F1/libraries/FreeRTOS900/utility/portmacro.h
new file mode 100644
index 000000000..d44fc9222
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/portmacro.h
@@ -0,0 +1,284 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+
+#ifndef PORTMACRO_H
+#define PORTMACRO_H
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * Port specific definitions.
+ *
+ * The settings in this file configure FreeRTOS correctly for the
+ * given hardware and compiler.
+ *
+ * These settings should not be altered.
+ *-----------------------------------------------------------
+ */
+
+/* Type definitions. */
+#define portCHAR		char
+#define portFLOAT		float
+#define portDOUBLE		double
+#define portLONG		long
+#define portSHORT		short
+#define portSTACK_TYPE	uint32_t
+#define portBASE_TYPE	long
+
+typedef portSTACK_TYPE StackType_t;
+typedef long BaseType_t;
+typedef unsigned long UBaseType_t;
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	typedef uint16_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffff
+#else
+	typedef uint32_t TickType_t;
+	#define portMAX_DELAY ( TickType_t ) 0xffffffffUL
+
+	/* 32-bit tick type on a 32-bit architecture, so reads of the tick count do
+	not need to be guarded with a critical section. */
+	#define portTICK_TYPE_IS_ATOMIC 1
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specifics. */
+#define portSTACK_GROWTH			( -1 )
+#define portTICK_PERIOD_MS			( ( TickType_t ) 1000 / configTICK_RATE_HZ )
+#define portBYTE_ALIGNMENT			8
+/*-----------------------------------------------------------*/
+
+/* Scheduler utilities. */
+#define portYIELD() 															\
+{																				\
+	/* Set a PendSV to request a context switch. */								\
+	portNVIC_INT_CTRL_REG = portNVIC_PENDSVSET_BIT;								\
+																				\
+	/* Barriers are normally not required but do ensure the code is completely	\
+	within the specified behaviour for the architecture. */						\
+	__asm volatile( "dsb" );													\
+	__asm volatile( "isb" );													\
+}
+
+#define portNVIC_INT_CTRL_REG		( * ( ( volatile uint32_t * ) 0xe000ed04 ) )
+#define portNVIC_PENDSVSET_BIT		( 1UL << 28UL )
+#define portEND_SWITCHING_ISR( xSwitchRequired ) if( xSwitchRequired != pdFALSE ) portYIELD()
+#define portYIELD_FROM_ISR( x ) portEND_SWITCHING_ISR( x )
+/*-----------------------------------------------------------*/
+
+/* Critical section management. */
+extern void vPortEnterCritical( void );
+extern void vPortExitCritical( void );
+#define portSET_INTERRUPT_MASK_FROM_ISR()		ulPortRaiseBASEPRI()
+#define portCLEAR_INTERRUPT_MASK_FROM_ISR(x)	vPortSetBASEPRI(x)
+#define portDISABLE_INTERRUPTS()				vPortRaiseBASEPRI()
+#define portENABLE_INTERRUPTS()					vPortSetBASEPRI(0)
+#define portENTER_CRITICAL()					vPortEnterCritical()
+#define portEXIT_CRITICAL()						vPortExitCritical()
+
+/*-----------------------------------------------------------*/
+
+/* Task function macros as described on the FreeRTOS.org WEB site.  These are
+not necessary for to use this port.  They are defined so the common demo files
+(which build with all the ports) will build. */
+#define portTASK_FUNCTION_PROTO( vFunction, pvParameters ) void vFunction( void *pvParameters )
+#define portTASK_FUNCTION( vFunction, pvParameters ) void vFunction( void *pvParameters )
+/*-----------------------------------------------------------*/
+
+/* Tickless idle/low power functionality. */
+#ifndef portSUPPRESS_TICKS_AND_SLEEP
+	extern void vPortSuppressTicksAndSleep( TickType_t xExpectedIdleTime );
+	#define portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime ) vPortSuppressTicksAndSleep( xExpectedIdleTime )
+#endif
+/*-----------------------------------------------------------*/
+
+/* Architecture specific optimisations. */
+#ifndef configUSE_PORT_OPTIMISED_TASK_SELECTION
+	#define configUSE_PORT_OPTIMISED_TASK_SELECTION 1
+#endif
+
+#if configUSE_PORT_OPTIMISED_TASK_SELECTION == 1
+
+	/* Generic helper function. */
+	__attribute__( ( always_inline ) ) static inline uint8_t ucPortCountLeadingZeros( uint32_t ulBitmap )
+	{
+	uint8_t ucReturn;
+
+		__asm volatile ( "clz %0, %1" : "=r" ( ucReturn ) : "r" ( ulBitmap ) );
+		return ucReturn;
+	}
+
+	/* Check the configuration. */
+	#if( configMAX_PRIORITIES > 32 )
+		#error configUSE_PORT_OPTIMISED_TASK_SELECTION can only be set to 1 when configMAX_PRIORITIES is less than or equal to 32.  It is very rare that a system requires more than 10 to 15 difference priorities as tasks that share a priority will time slice.
+	#endif
+
+	/* Store/clear the ready priorities in a bit map. */
+	#define portRECORD_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) |= ( 1UL << ( uxPriority ) )
+	#define portRESET_READY_PRIORITY( uxPriority, uxReadyPriorities ) ( uxReadyPriorities ) &= ~( 1UL << ( uxPriority ) )
+
+	/*-----------------------------------------------------------*/
+
+	#define portGET_HIGHEST_PRIORITY( uxTopPriority, uxReadyPriorities ) uxTopPriority = ( 31UL - ( uint32_t ) ucPortCountLeadingZeros( ( uxReadyPriorities ) ) )
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+#ifdef configASSERT
+	void vPortValidateInterruptPriority( void );
+	#define portASSERT_IF_INTERRUPT_PRIORITY_INVALID() 	vPortValidateInterruptPriority()
+#endif
+
+/* portNOP() is not required by this port. */
+#define portNOP()
+
+#define portINLINE	__inline
+
+#ifndef portFORCE_INLINE
+	#define portFORCE_INLINE inline __attribute__(( always_inline))
+#endif
+
+portFORCE_INLINE static BaseType_t xPortIsInsideInterrupt( void )
+{
+uint32_t ulCurrentInterrupt;
+BaseType_t xReturn;
+
+	/* Obtain the number of the currently executing interrupt. */
+	__asm volatile( "mrs %0, ipsr" : "=r"( ulCurrentInterrupt ) );
+
+	if( ulCurrentInterrupt == 0 )
+	{
+		xReturn = pdFALSE;
+	}
+	else
+	{
+		xReturn = pdTRUE;
+	}
+
+	return xReturn;
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortRaiseBASEPRI( void )
+{
+uint32_t ulNewBASEPRI;
+
+	__asm volatile
+	(
+		"	mov %0, %1												\n"	\
+		"	msr basepri, %0											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		:"=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+	);
+}
+
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static uint32_t ulPortRaiseBASEPRI( void )
+{
+uint32_t ulOriginalBASEPRI, ulNewBASEPRI;
+
+	__asm volatile
+	(
+		"	mrs %0, basepri											\n" \
+		"	mov %1, %2												\n"	\
+		"	msr basepri, %1											\n" \
+		"	isb														\n" \
+		"	dsb														\n" \
+		:"=r" (ulOriginalBASEPRI), "=r" (ulNewBASEPRI) : "i" ( configMAX_SYSCALL_INTERRUPT_PRIORITY )
+	);
+
+	/* This return will not be reached but is necessary to prevent compiler
+	warnings. */
+	return ulOriginalBASEPRI;
+}
+/*-----------------------------------------------------------*/
+
+portFORCE_INLINE static void vPortSetBASEPRI( uint32_t ulNewMaskValue )
+{
+	__asm volatile
+	(
+		"	msr basepri, %0	" :: "r" ( ulNewMaskValue )
+	);
+}
+/*-----------------------------------------------------------*/
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* PORTMACRO_H */
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/projdefs.h b/STM32F1/libraries/FreeRTOS900/utility/projdefs.h
new file mode 100644
index 000000000..0b63fd8a9
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/projdefs.h
@@ -0,0 +1,161 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#ifndef PROJDEFS_H
+#define PROJDEFS_H
+
+/*
+ * Defines the prototype to which task functions must conform.  Defined in this
+ * file to ensure the type is known before portable.h is included.
+ */
+typedef void (*TaskFunction_t)( void * );
+
+/* Converts a time in milliseconds to a time in ticks.  This macro can be
+overridden by a macro of the same name defined in FreeRTOSConfig.h in case the
+definition here is not suitable for your application. */
+#ifndef pdMS_TO_TICKS
+	#define pdMS_TO_TICKS( xTimeInMs ) ( ( TickType_t ) ( ( ( TickType_t ) ( xTimeInMs ) * ( TickType_t ) configTICK_RATE_HZ ) / ( TickType_t ) 1000 ) )
+#endif
+
+#define pdFALSE			( ( BaseType_t ) 0 )
+#define pdTRUE			( ( BaseType_t ) 1 )
+
+#define pdPASS			( pdTRUE )
+#define pdFAIL			( pdFALSE )
+#define errQUEUE_EMPTY	( ( BaseType_t ) 0 )
+#define errQUEUE_FULL	( ( BaseType_t ) 0 )
+
+/* FreeRTOS error definitions. */
+#define errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY	( -1 )
+#define errQUEUE_BLOCKED						( -4 )
+#define errQUEUE_YIELD							( -5 )
+
+/* Macros used for basic data corruption checks. */
+#ifndef configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES
+	#define configUSE_LIST_DATA_INTEGRITY_CHECK_BYTES 0
+#endif
+
+#if( configUSE_16_BIT_TICKS == 1 )
+	#define pdINTEGRITY_CHECK_VALUE 0x5a5a
+#else
+	#define pdINTEGRITY_CHECK_VALUE 0x5a5a5a5aUL
+#endif
+
+/* The following errno values are used by FreeRTOS+ components, not FreeRTOS
+itself. */
+#define pdFREERTOS_ERRNO_NONE			0	/* No errors */
+#define	pdFREERTOS_ERRNO_ENOENT			2	/* No such file or directory */
+#define	pdFREERTOS_ERRNO_EINTR			4	/* Interrupted system call */
+#define	pdFREERTOS_ERRNO_EIO			5	/* I/O error */
+#define	pdFREERTOS_ERRNO_ENXIO			6	/* No such device or address */
+#define	pdFREERTOS_ERRNO_EBADF			9	/* Bad file number */
+#define	pdFREERTOS_ERRNO_EAGAIN			11	/* No more processes */
+#define	pdFREERTOS_ERRNO_EWOULDBLOCK	11	/* Operation would block */
+#define	pdFREERTOS_ERRNO_ENOMEM			12	/* Not enough memory */
+#define	pdFREERTOS_ERRNO_EACCES			13	/* Permission denied */
+#define	pdFREERTOS_ERRNO_EFAULT			14	/* Bad address */
+#define	pdFREERTOS_ERRNO_EBUSY			16	/* Mount device busy */
+#define	pdFREERTOS_ERRNO_EEXIST			17	/* File exists */
+#define	pdFREERTOS_ERRNO_EXDEV			18	/* Cross-device link */
+#define	pdFREERTOS_ERRNO_ENODEV			19	/* No such device */
+#define	pdFREERTOS_ERRNO_ENOTDIR		20	/* Not a directory */
+#define	pdFREERTOS_ERRNO_EISDIR			21	/* Is a directory */
+#define	pdFREERTOS_ERRNO_EINVAL			22	/* Invalid argument */
+#define	pdFREERTOS_ERRNO_ENOSPC			28	/* No space left on device */
+#define	pdFREERTOS_ERRNO_ESPIPE			29	/* Illegal seek */
+#define	pdFREERTOS_ERRNO_EROFS			30	/* Read only file system */
+#define	pdFREERTOS_ERRNO_EUNATCH		42	/* Protocol driver not attached */
+#define	pdFREERTOS_ERRNO_EBADE			50	/* Invalid exchange */
+#define	pdFREERTOS_ERRNO_EFTYPE			79	/* Inappropriate file type or format */
+#define	pdFREERTOS_ERRNO_ENMFILE		89	/* No more files */
+#define	pdFREERTOS_ERRNO_ENOTEMPTY		90	/* Directory not empty */
+#define	pdFREERTOS_ERRNO_ENAMETOOLONG 	91	/* File or path name too long */
+#define	pdFREERTOS_ERRNO_EOPNOTSUPP		95	/* Operation not supported on transport endpoint */
+#define	pdFREERTOS_ERRNO_ENOBUFS		105	/* No buffer space available */
+#define	pdFREERTOS_ERRNO_ENOPROTOOPT	109	/* Protocol not available */
+#define	pdFREERTOS_ERRNO_EADDRINUSE		112	/* Address already in use */
+#define	pdFREERTOS_ERRNO_ETIMEDOUT		116	/* Connection timed out */
+#define	pdFREERTOS_ERRNO_EINPROGRESS	119	/* Connection already in progress */
+#define	pdFREERTOS_ERRNO_EALREADY		120	/* Socket already connected */
+#define	pdFREERTOS_ERRNO_EADDRNOTAVAIL 	125	/* Address not available */
+#define	pdFREERTOS_ERRNO_EISCONN		127	/* Socket is already connected */
+#define	pdFREERTOS_ERRNO_ENOTCONN		128	/* Socket is not connected */
+#define	pdFREERTOS_ERRNO_ENOMEDIUM		135	/* No medium inserted */
+#define	pdFREERTOS_ERRNO_EILSEQ			138	/* An invalid UTF-16 sequence was encountered. */
+#define	pdFREERTOS_ERRNO_ECANCELED		140	/* Operation canceled. */
+
+/* The following endian values are used by FreeRTOS+ components, not FreeRTOS
+itself. */
+#define pdFREERTOS_LITTLE_ENDIAN	0
+#define pdFREERTOS_BIG_ENDIAN		1
+
+#endif /* PROJDEFS_H */
+
+
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/queue.c b/STM32F1/libraries/FreeRTOS900/utility/queue.c
new file mode 100644
index 000000000..ce623bec2
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/queue.c
@@ -0,0 +1,2566 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#include <stdlib.h>
+#include <string.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+
+#if ( configUSE_CO_ROUTINES == 1 )
+	#include "croutine.h"
+#endif
+
+/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
+MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
+header files above, but not in this file, in order to generate the correct
+privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+
+
+/* Constants used with the cRxLock and cTxLock structure members. */
+#define queueUNLOCKED					( ( int8_t ) -1 )
+#define queueLOCKED_UNMODIFIED			( ( int8_t ) 0 )
+
+/* When the Queue_t structure is used to represent a base queue its pcHead and
+pcTail members are used as pointers into the queue storage area.  When the
+Queue_t structure is used to represent a mutex pcHead and pcTail pointers are
+not necessary, and the pcHead pointer is set to NULL to indicate that the
+pcTail pointer actually points to the mutex holder (if any).  Map alternative
+names to the pcHead and pcTail structure members to ensure the readability of
+the code is maintained despite this dual use of two structure members.  An
+alternative implementation would be to use a union, but use of a union is
+against the coding standard (although an exception to the standard has been
+permitted where the dual use also significantly changes the type of the
+structure member). */
+#define pxMutexHolder					pcTail
+#define uxQueueType						pcHead
+#define queueQUEUE_IS_MUTEX				NULL
+
+/* Semaphores do not actually store or copy data, so have an item size of
+zero. */
+#define queueSEMAPHORE_QUEUE_ITEM_LENGTH ( ( UBaseType_t ) 0 )
+#define queueMUTEX_GIVE_BLOCK_TIME		 ( ( TickType_t ) 0U )
+
+#if( configUSE_PREEMPTION == 0 )
+	/* If the cooperative scheduler is being used then a yield should not be
+	performed just because a higher priority task has been woken. */
+	#define queueYIELD_IF_USING_PREEMPTION()
+#else
+	#define queueYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+#endif
+
+/*
+ * Definition of the queue used by the scheduler.
+ * Items are queued by copy, not reference.  See the following link for the
+ * rationale: http://www.freertos.org/Embedded-RTOS-Queues.html
+ */
+typedef struct QueueDefinition
+{
+	int8_t *pcHead;					/*< Points to the beginning of the queue storage area. */
+	int8_t *pcTail;					/*< Points to the byte at the end of the queue storage area.  Once more byte is allocated than necessary to store the queue items, this is used as a marker. */
+	int8_t *pcWriteTo;				/*< Points to the free next place in the storage area. */
+
+	union							/* Use of a union is an exception to the coding standard to ensure two mutually exclusive structure members don't appear simultaneously (wasting RAM). */
+	{
+		int8_t *pcReadFrom;			/*< Points to the last place that a queued item was read from when the structure is used as a queue. */
+		UBaseType_t uxRecursiveCallCount;/*< Maintains a count of the number of times a recursive mutex has been recursively 'taken' when the structure is used as a mutex. */
+	} u;
+
+	List_t xTasksWaitingToSend;		/*< List of tasks that are blocked waiting to post onto this queue.  Stored in priority order. */
+	List_t xTasksWaitingToReceive;	/*< List of tasks that are blocked waiting to read from this queue.  Stored in priority order. */
+
+	volatile UBaseType_t uxMessagesWaiting;/*< The number of items currently in the queue. */
+	UBaseType_t uxLength;			/*< The length of the queue defined as the number of items it will hold, not the number of bytes. */
+	UBaseType_t uxItemSize;			/*< The size of each items that the queue will hold. */
+
+	volatile int8_t cRxLock;		/*< Stores the number of items received from the queue (removed from the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
+	volatile int8_t cTxLock;		/*< Stores the number of items transmitted to the queue (added to the queue) while the queue was locked.  Set to queueUNLOCKED when the queue is not locked. */
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+		uint8_t ucStaticallyAllocated;	/*< Set to pdTRUE if the memory used by the queue was statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+
+	#if ( configUSE_QUEUE_SETS == 1 )
+		struct QueueDefinition *pxQueueSetContainer;
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t uxQueueNumber;
+		uint8_t ucQueueType;
+	#endif
+
+} xQUEUE;
+
+/* The old xQUEUE name is maintained above then typedefed to the new Queue_t
+name below to enable the use of older kernel aware debuggers. */
+typedef xQUEUE Queue_t;
+
+/*-----------------------------------------------------------*/
+
+/*
+ * The queue registry is just a means for kernel aware debuggers to locate
+ * queue structures.  It has no other purpose so is an optional component.
+ */
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	/* The type stored within the queue registry array.  This allows a name
+	to be assigned to each queue making kernel aware debugging a little
+	more user friendly. */
+	typedef struct QUEUE_REGISTRY_ITEM
+	{
+		const char *pcQueueName; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+		QueueHandle_t xHandle;
+	} xQueueRegistryItem;
+
+	/* The old xQueueRegistryItem name is maintained above then typedefed to the
+	new xQueueRegistryItem name below to enable the use of older kernel aware
+	debuggers. */
+	typedef xQueueRegistryItem QueueRegistryItem_t;
+
+	/* The queue registry is simply an array of QueueRegistryItem_t structures.
+	The pcQueueName member of a structure being NULL is indicative of the
+	array position being vacant. */
+	PRIVILEGED_DATA QueueRegistryItem_t xQueueRegistry[ configQUEUE_REGISTRY_SIZE ];
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+
+/*
+ * Unlocks a queue locked by a call to prvLockQueue.  Locking a queue does not
+ * prevent an ISR from adding or removing items to the queue, but does prevent
+ * an ISR from removing tasks from the queue event lists.  If an ISR finds a
+ * queue is locked it will instead increment the appropriate queue lock count
+ * to indicate that a task may require unblocking.  When the queue in unlocked
+ * these lock counts are inspected, and the appropriate action taken.
+ */
+static void prvUnlockQueue( Queue_t * const pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any data in a queue.
+ *
+ * @return pdTRUE if the queue contains no items, otherwise pdFALSE.
+ */
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Uses a critical section to determine if there is any space in a queue.
+ *
+ * @return pdTRUE if there is no space, otherwise pdFALSE;
+ */
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item into the queue, either at the front of the queue or the
+ * back of the queue.
+ */
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition ) PRIVILEGED_FUNCTION;
+
+/*
+ * Copies an item out of a queue.
+ */
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+#if ( configUSE_QUEUE_SETS == 1 )
+	/*
+	 * Checks to see if a queue is a member of a queue set, and if so, notifies
+	 * the queue set that the queue contains data.
+	 */
+	static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Called after a Queue_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * Mutexes are a special type of queue.  When a mutex is created, first the
+ * queue is created, then prvInitialiseMutex() is called to configure the queue
+ * as a mutex.
+ */
+#if( configUSE_MUTEXES == 1 )
+	static void prvInitialiseMutex( Queue_t *pxNewQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Macro to mark a queue as locked.  Locking a queue prevents an ISR from
+ * accessing the queue event lists.
+ */
+#define prvLockQueue( pxQueue )								\
+	taskENTER_CRITICAL();									\
+	{														\
+		if( ( pxQueue )->cRxLock == queueUNLOCKED )			\
+		{													\
+			( pxQueue )->cRxLock = queueLOCKED_UNMODIFIED;	\
+		}													\
+		if( ( pxQueue )->cTxLock == queueUNLOCKED )			\
+		{													\
+			( pxQueue )->cTxLock = queueLOCKED_UNMODIFIED;	\
+		}													\
+	}														\
+	taskEXIT_CRITICAL()
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue )
+{
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+	configASSERT( pxQueue );
+
+	taskENTER_CRITICAL();
+	{
+		pxQueue->pcTail = pxQueue->pcHead + ( pxQueue->uxLength * pxQueue->uxItemSize );
+		pxQueue->uxMessagesWaiting = ( UBaseType_t ) 0U;
+		pxQueue->pcWriteTo = pxQueue->pcHead;
+		pxQueue->u.pcReadFrom = pxQueue->pcHead + ( ( pxQueue->uxLength - ( UBaseType_t ) 1U ) * pxQueue->uxItemSize );
+		pxQueue->cRxLock = queueUNLOCKED;
+		pxQueue->cTxLock = queueUNLOCKED;
+
+		if( xNewQueue == pdFALSE )
+		{
+			/* If there are tasks blocked waiting to read from the queue, then
+			the tasks will remain blocked as after this function exits the queue
+			will still be empty.  If there are tasks blocked waiting to write to
+			the queue, then one should be unblocked as after this function exits
+			it will be possible to write to it. */
+			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+			{
+				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+				{
+					queueYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			/* Ensure the event queues start in the correct state. */
+			vListInitialise( &( pxQueue->xTasksWaitingToSend ) );
+			vListInitialise( &( pxQueue->xTasksWaitingToReceive ) );
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	/* A value is returned for calling semantic consistency with previous
+	versions. */
+	return pdPASS;
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType )
+	{
+	Queue_t *pxNewQueue;
+
+		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+
+		/* The StaticQueue_t structure and the queue storage area must be
+		supplied. */
+		configASSERT( pxStaticQueue != NULL );
+
+		/* A queue storage area should be provided if the item size is not 0, and
+		should not be provided if the item size is 0. */
+		configASSERT( !( ( pucQueueStorage != NULL ) && ( uxItemSize == 0 ) ) );
+		configASSERT( !( ( pucQueueStorage == NULL ) && ( uxItemSize != 0 ) ) );
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticQueue_t or StaticSemaphore_t equals the size of
+			the real queue and semaphore structures. */
+			volatile size_t xSize = sizeof( StaticQueue_t );
+			configASSERT( xSize == sizeof( Queue_t ) );
+		}
+		#endif /* configASSERT_DEFINED */
+
+		/* The address of a statically allocated queue was passed in, use it.
+		The address of a statically allocated storage area was also passed in
+		but is already set. */
+		pxNewQueue = ( Queue_t * ) pxStaticQueue; /*lint !e740 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+
+		if( pxNewQueue != NULL )
+		{
+			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+			{
+				/* Queues can be allocated wither statically or dynamically, so
+				note this queue was allocated statically in case the queue is
+				later deleted. */
+				pxNewQueue->ucStaticallyAllocated = pdTRUE;
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+		}
+
+		return pxNewQueue;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType )
+	{
+	Queue_t *pxNewQueue;
+	size_t xQueueSizeInBytes;
+	uint8_t *pucQueueStorage;
+
+		configASSERT( uxQueueLength > ( UBaseType_t ) 0 );
+
+		if( uxItemSize == ( UBaseType_t ) 0 )
+		{
+			/* There is not going to be a queue storage area. */
+			xQueueSizeInBytes = ( size_t ) 0;
+		}
+		else
+		{
+			/* Allocate enough space to hold the maximum number of items that
+			can be in the queue at any time. */
+			xQueueSizeInBytes = ( size_t ) ( uxQueueLength * uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+		}
+
+		pxNewQueue = ( Queue_t * ) pvPortMalloc( sizeof( Queue_t ) + xQueueSizeInBytes );
+
+		if( pxNewQueue != NULL )
+		{
+			/* Jump past the queue structure to find the location of the queue
+			storage area. */
+			pucQueueStorage = ( ( uint8_t * ) pxNewQueue ) + sizeof( Queue_t );
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* Queues can be created either statically or dynamically, so
+				note this task was created dynamically in case it is later
+				deleted. */
+				pxNewQueue->ucStaticallyAllocated = pdFALSE;
+			}
+			#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+			prvInitialiseNewQueue( uxQueueLength, uxItemSize, pucQueueStorage, ucQueueType, pxNewQueue );
+		}
+
+		return pxNewQueue;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewQueue( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, const uint8_t ucQueueType, Queue_t *pxNewQueue )
+{
+	/* Remove compiler warnings about unused parameters should
+	configUSE_TRACE_FACILITY not be set to 1. */
+	( void ) ucQueueType;
+
+	if( uxItemSize == ( UBaseType_t ) 0 )
+	{
+		/* No RAM was allocated for the queue storage area, but PC head cannot
+		be set to NULL because NULL is used as a key to say the queue is used as
+		a mutex.  Therefore just set pcHead to point to the queue as a benign
+		value that is known to be within the memory map. */
+		pxNewQueue->pcHead = ( int8_t * ) pxNewQueue;
+	}
+	else
+	{
+		/* Set the head to the start of the queue storage area. */
+		pxNewQueue->pcHead = ( int8_t * ) pucQueueStorage;
+	}
+
+	/* Initialise the queue members as described where the queue type is
+	defined. */
+	pxNewQueue->uxLength = uxQueueLength;
+	pxNewQueue->uxItemSize = uxItemSize;
+	( void ) xQueueGenericReset( pxNewQueue, pdTRUE );
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+	{
+		pxNewQueue->ucQueueType = ucQueueType;
+	}
+	#endif /* configUSE_TRACE_FACILITY */
+
+	#if( configUSE_QUEUE_SETS == 1 )
+	{
+		pxNewQueue->pxQueueSetContainer = NULL;
+	}
+	#endif /* configUSE_QUEUE_SETS */
+
+	traceQUEUE_CREATE( pxNewQueue );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_MUTEXES == 1 )
+
+	static void prvInitialiseMutex( Queue_t *pxNewQueue )
+	{
+		if( pxNewQueue != NULL )
+		{
+			/* The queue create function will set all the queue structure members
+			correctly for a generic queue, but this function is creating a
+			mutex.  Overwrite those members that need to be set differently -
+			in particular the information required for priority inheritance. */
+			pxNewQueue->pxMutexHolder = NULL;
+			pxNewQueue->uxQueueType = queueQUEUE_IS_MUTEX;
+
+			/* In case this is a recursive mutex. */
+			pxNewQueue->u.uxRecursiveCallCount = 0;
+
+			traceCREATE_MUTEX( pxNewQueue );
+
+			/* Start with the semaphore in the expected state. */
+			( void ) xQueueGenericSend( pxNewQueue, NULL, ( TickType_t ) 0U, queueSEND_TO_BACK );
+		}
+		else
+		{
+			traceCREATE_MUTEX_FAILED();
+		}
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType )
+	{
+	Queue_t *pxNewQueue;
+	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+		pxNewQueue = ( Queue_t * ) xQueueGenericCreate( uxMutexLength, uxMutexSize, ucQueueType );
+		prvInitialiseMutex( pxNewQueue );
+
+		return pxNewQueue;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_MUTEXES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue )
+	{
+	Queue_t *pxNewQueue;
+	const UBaseType_t uxMutexLength = ( UBaseType_t ) 1, uxMutexSize = ( UBaseType_t ) 0;
+
+		/* Prevent compiler warnings about unused parameters if
+		configUSE_TRACE_FACILITY does not equal 1. */
+		( void ) ucQueueType;
+
+		pxNewQueue = ( Queue_t * ) xQueueGenericCreateStatic( uxMutexLength, uxMutexSize, NULL, pxStaticQueue, ucQueueType );
+		prvInitialiseMutex( pxNewQueue );
+
+		return pxNewQueue;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_MUTEXES == 1 ) && ( INCLUDE_xSemaphoreGetMutexHolder == 1 ) )
+
+	void* xQueueGetMutexHolder( QueueHandle_t xSemaphore )
+	{
+	void *pxReturn;
+
+		/* This function is called by xSemaphoreGetMutexHolder(), and should not
+		be called directly.  Note:  This is a good way of determining if the
+		calling task is the mutex holder, but not a good way of determining the
+		identity of the mutex holder, as the holder may change between the
+		following critical section exiting and the function returning. */
+		taskENTER_CRITICAL();
+		{
+			if( ( ( Queue_t * ) xSemaphore )->uxQueueType == queueQUEUE_IS_MUTEX )
+			{
+				pxReturn = ( void * ) ( ( Queue_t * ) xSemaphore )->pxMutexHolder;
+			}
+			else
+			{
+				pxReturn = NULL;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return pxReturn;
+	} /*lint !e818 xSemaphore cannot be a pointer to const because it is a typedef. */
+
+#endif
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+	BaseType_t xQueueGiveMutexRecursive( QueueHandle_t xMutex )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+		configASSERT( pxMutex );
+
+		/* If this is the task that holds the mutex then pxMutexHolder will not
+		change outside of this task.  If this task does not hold the mutex then
+		pxMutexHolder can never coincidentally equal the tasks handle, and as
+		this is the only condition we are interested in it does not matter if
+		pxMutexHolder is accessed simultaneously by another task.  Therefore no
+		mutual exclusion is required to test the pxMutexHolder variable. */
+		if( pxMutex->pxMutexHolder == ( void * ) xTaskGetCurrentTaskHandle() ) /*lint !e961 Not a redundant cast as TaskHandle_t is a typedef. */
+		{
+			traceGIVE_MUTEX_RECURSIVE( pxMutex );
+
+			/* uxRecursiveCallCount cannot be zero if pxMutexHolder is equal to
+			the task handle, therefore no underflow check is required.  Also,
+			uxRecursiveCallCount is only modified by the mutex holder, and as
+			there can only be one, no mutual exclusion is required to modify the
+			uxRecursiveCallCount member. */
+			( pxMutex->u.uxRecursiveCallCount )--;
+
+			/* Has the recursive call count unwound to 0? */
+			if( pxMutex->u.uxRecursiveCallCount == ( UBaseType_t ) 0 )
+			{
+				/* Return the mutex.  This will automatically unblock any other
+				task that might be waiting to access the mutex. */
+				( void ) xQueueGenericSend( pxMutex, NULL, queueMUTEX_GIVE_BLOCK_TIME, queueSEND_TO_BACK );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			/* The mutex cannot be given because the calling task is not the
+			holder. */
+			xReturn = pdFAIL;
+
+			traceGIVE_MUTEX_RECURSIVE_FAILED( pxMutex );
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_RECURSIVE_MUTEXES == 1 )
+
+	BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxMutex = ( Queue_t * ) xMutex;
+
+		configASSERT( pxMutex );
+
+		/* Comments regarding mutual exclusion as per those within
+		xQueueGiveMutexRecursive(). */
+
+		traceTAKE_MUTEX_RECURSIVE( pxMutex );
+
+		if( pxMutex->pxMutexHolder == ( void * ) xTaskGetCurrentTaskHandle() ) /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */
+		{
+			( pxMutex->u.uxRecursiveCallCount )++;
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = xQueueGenericReceive( pxMutex, NULL, xTicksToWait, pdFALSE );
+
+			/* pdPASS will only be returned if the mutex was successfully
+			obtained.  The calling task may have entered the Blocked state
+			before reaching here. */
+			if( xReturn != pdFAIL )
+			{
+				( pxMutex->u.uxRecursiveCallCount )++;
+			}
+			else
+			{
+				traceTAKE_MUTEX_RECURSIVE_FAILED( pxMutex );
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_RECURSIVE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue )
+	{
+	QueueHandle_t xHandle;
+
+		configASSERT( uxMaxCount != 0 );
+		configASSERT( uxInitialCount <= uxMaxCount );
+
+		xHandle = xQueueGenericCreateStatic( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticQueue, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+		if( xHandle != NULL )
+		{
+			( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+			traceCREATE_COUNTING_SEMAPHORE();
+		}
+		else
+		{
+			traceCREATE_COUNTING_SEMAPHORE_FAILED();
+		}
+
+		return xHandle;
+	}
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount )
+	{
+	QueueHandle_t xHandle;
+
+		configASSERT( uxMaxCount != 0 );
+		configASSERT( uxInitialCount <= uxMaxCount );
+
+		xHandle = xQueueGenericCreate( uxMaxCount, queueSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_COUNTING_SEMAPHORE );
+
+		if( xHandle != NULL )
+		{
+			( ( Queue_t * ) xHandle )->uxMessagesWaiting = uxInitialCount;
+
+			traceCREATE_COUNTING_SEMAPHORE();
+		}
+		else
+		{
+			traceCREATE_COUNTING_SEMAPHORE_FAILED();
+		}
+
+		return xHandle;
+	}
+
+#endif /* ( ( configUSE_COUNTING_SEMAPHORES == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition )
+{
+BaseType_t xEntryTimeSet = pdFALSE, xYieldRequired;
+TimeOut_t xTimeOut;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+
+	/* This function relaxes the coding standard somewhat to allow return
+	statements within the function itself.  This is done in the interest
+	of execution time efficiency. */
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			/* Is there room on the queue now?  The running task must be the
+			highest priority task wanting to access the queue.  If the head item
+			in the queue is to be overwritten then it does not matter if the
+			queue is full. */
+			if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+			{
+				traceQUEUE_SEND( pxQueue );
+				xYieldRequired = prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE )
+						{
+							/* The queue is a member of a queue set, and posting
+							to the queue set caused a higher priority task to
+							unblock. A context switch is required. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						/* If there was a task waiting for data to arrive on the
+						queue then unblock it now. */
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The unblocked task has a priority higher than
+								our own so yield immediately.  Yes it is ok to
+								do this from within the critical section - the
+								kernel takes care of that. */
+								queueYIELD_IF_USING_PREEMPTION();
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else if( xYieldRequired != pdFALSE )
+						{
+							/* This path is a special case that will only get
+							executed if the task was holding multiple mutexes
+							and the mutexes were given back in an order that is
+							different to that in which they were taken. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					/* If there was a task waiting for data to arrive on the
+					queue then unblock it now. */
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The unblocked task has a priority higher than
+							our own so yield immediately.  Yes it is ok to do
+							this from within the critical section - the kernel
+							takes care of that. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else if( xYieldRequired != pdFALSE )
+					{
+						/* This path is a special case that will only get
+						executed if the task was holding multiple mutexes and
+						the mutexes were given back in an order that is
+						different to that in which they were taken. */
+						queueYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was full and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+
+					/* Return to the original privilege level before exiting
+					the function. */
+					traceQUEUE_SEND_FAILED( pxQueue );
+					return errQUEUE_FULL;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was full and a block time was specified so
+					configure the timeout structure. */
+					vTaskSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			if( prvIsQueueFull( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_SEND( pxQueue );
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToSend ), xTicksToWait );
+
+				/* Unlocking the queue means queue events can effect the
+				event list.  It is possible	that interrupts occurring now
+				remove this task from the event	list again - but as the
+				scheduler is suspended the task will go onto the pending
+				ready last instead of the actual ready list. */
+				prvUnlockQueue( pxQueue );
+
+				/* Resuming the scheduler will move tasks from the pending
+				ready list into the ready list - so it is feasible that this
+				task is already in a ready list before it yields - in which
+				case the yield will not cause a context switch unless there
+				is also a higher priority task in the pending ready list. */
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+			}
+			else
+			{
+				/* Try again. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			/* The timeout has expired. */
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			traceQUEUE_SEND_FAILED( pxQueue );
+			return errQUEUE_FULL;
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvItemToQueue == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( !( ( xCopyPosition == queueOVERWRITE ) && ( pxQueue->uxLength != 1 ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	/* Similar to xQueueGenericSend, except without blocking if there is no room
+	in the queue.  Also don't directly wake a task that was blocked on a queue
+	read, instead return a flag to say whether a context switch is required or
+	not (i.e. has a task with a higher priority than us been woken by this
+	post). */
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		if( ( pxQueue->uxMessagesWaiting < pxQueue->uxLength ) || ( xCopyPosition == queueOVERWRITE ) )
+		{
+			const int8_t cTxLock = pxQueue->cTxLock;
+
+			traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+			/* Semaphores use xQueueGiveFromISR(), so pxQueue will not be a
+			semaphore or mutex.  That means prvCopyDataToQueue() cannot result
+			in a task disinheriting a priority and prvCopyDataToQueue() can be
+			called here even though the disinherit function does not check if
+			the scheduler is suspended before accessing the ready lists. */
+			( void ) prvCopyDataToQueue( pxQueue, pvItemToQueue, xCopyPosition );
+
+			/* The event list is not altered if the queue is locked.  This will
+			be done when the queue is unlocked later. */
+			if( cTxLock == queueUNLOCKED )
+			{
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( prvNotifyQueueSetContainer( pxQueue, xCopyPosition ) != pdFALSE )
+						{
+							/* The queue is a member of a queue set, and posting
+							to the queue set caused a higher priority task to
+							unblock.  A context switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The task waiting has a higher priority so
+								record that a context switch is required. */
+								if( pxHigherPriorityTaskWoken != NULL )
+								{
+									*pxHigherPriorityTaskWoken = pdTRUE;
+								}
+								else
+								{
+									mtCOVERAGE_TEST_MARKER();
+								}
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was posted while it was locked. */
+				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+			xReturn = errQUEUE_FULL;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+	/* Similar to xQueueGenericSendFromISR() but used with semaphores where the
+	item size is 0.  Don't directly wake a task that was blocked on a queue
+	read, instead return a flag to say whether a context switch is required or
+	not (i.e. has a task with a higher priority than us been woken by this
+	post). */
+
+	configASSERT( pxQueue );
+
+	/* xQueueGenericSendFromISR() should be used instead of xQueueGiveFromISR()
+	if the item size is not 0. */
+	configASSERT( pxQueue->uxItemSize == 0 );
+
+	/* Normally a mutex would not be given from an interrupt, especially if
+	there is a mutex holder, as priority inheritance makes no sense for an
+	interrupts, only tasks. */
+	configASSERT( !( ( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX ) && ( pxQueue->pxMutexHolder != NULL ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+		/* When the queue is used to implement a semaphore no data is ever
+		moved through the queue but it is still valid to see if the queue 'has
+		space'. */
+		if( uxMessagesWaiting < pxQueue->uxLength )
+		{
+			const int8_t cTxLock = pxQueue->cTxLock;
+
+			traceQUEUE_SEND_FROM_ISR( pxQueue );
+
+			/* A task can only have an inherited priority if it is a mutex
+			holder - and if there is a mutex holder then the mutex cannot be
+			given from an ISR.  As this is the ISR version of the function it
+			can be assumed there is no mutex holder and no need to determine if
+			priority disinheritance is needed.  Simply increase the count of
+			messages (semaphores) available. */
+			pxQueue->uxMessagesWaiting = uxMessagesWaiting + 1;
+
+			/* The event list is not altered if the queue is locked.  This will
+			be done when the queue is unlocked later. */
+			if( cTxLock == queueUNLOCKED )
+			{
+				#if ( configUSE_QUEUE_SETS == 1 )
+				{
+					if( pxQueue->pxQueueSetContainer != NULL )
+					{
+						if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) != pdFALSE )
+						{
+							/* The semaphore is a member of a queue set, and
+							posting	to the queue set caused a higher priority
+							task to	unblock.  A context switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+						{
+							if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+							{
+								/* The task waiting has a higher priority so
+								record that a context switch is required. */
+								if( pxHigherPriorityTaskWoken != NULL )
+								{
+									*pxHigherPriorityTaskWoken = pdTRUE;
+								}
+								else
+								{
+									mtCOVERAGE_TEST_MARKER();
+								}
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+				}
+				#else /* configUSE_QUEUE_SETS */
+				{
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							if( pxHigherPriorityTaskWoken != NULL )
+							{
+								*pxHigherPriorityTaskWoken = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_QUEUE_SETS */
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was posted while it was locked. */
+				pxQueue->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			traceQUEUE_SEND_FROM_ISR_FAILED( pxQueue );
+			xReturn = errQUEUE_FULL;
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, const BaseType_t xJustPeeking )
+{
+BaseType_t xEntryTimeSet = pdFALSE;
+TimeOut_t xTimeOut;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+	{
+		configASSERT( !( ( xTaskGetSchedulerState() == taskSCHEDULER_SUSPENDED ) && ( xTicksToWait != 0 ) ) );
+	}
+	#endif
+
+	/* This function relaxes the coding standard somewhat to allow return
+	statements within the function itself.  This is done in the interest
+	of execution time efficiency. */
+
+	for( ;; )
+	{
+		taskENTER_CRITICAL();
+		{
+			const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+			/* Is there data in the queue now?  To be running the calling task
+			must be the highest priority task wanting to access the queue. */
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Remember the read position in case the queue is only being
+				peeked. */
+				pcOriginalReadPosition = pxQueue->u.pcReadFrom;
+
+				prvCopyDataFromQueue( pxQueue, pvBuffer );
+
+				if( xJustPeeking == pdFALSE )
+				{
+					traceQUEUE_RECEIVE( pxQueue );
+
+					/* Actually removing data, not just peeking. */
+					pxQueue->uxMessagesWaiting = uxMessagesWaiting - 1;
+
+					#if ( configUSE_MUTEXES == 1 )
+					{
+						if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+						{
+							/* Record the information required to implement
+							priority inheritance should it become necessary. */
+							pxQueue->pxMutexHolder = ( int8_t * ) pvTaskIncrementMutexHeldCount(); /*lint !e961 Cast is not redundant as TaskHandle_t is a typedef. */
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					#endif /* configUSE_MUTEXES */
+
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+						{
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					traceQUEUE_PEEK( pxQueue );
+
+					/* The data is not being removed, so reset the read
+					pointer. */
+					pxQueue->u.pcReadFrom = pcOriginalReadPosition;
+
+					/* The data is being left in the queue, so see if there are
+					any other tasks waiting for the data. */
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority than this task. */
+							queueYIELD_IF_USING_PREEMPTION();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				taskEXIT_CRITICAL();
+				return pdPASS;
+			}
+			else
+			{
+				if( xTicksToWait == ( TickType_t ) 0 )
+				{
+					/* The queue was empty and no block time is specified (or
+					the block time has expired) so leave now. */
+					taskEXIT_CRITICAL();
+					traceQUEUE_RECEIVE_FAILED( pxQueue );
+					return errQUEUE_EMPTY;
+				}
+				else if( xEntryTimeSet == pdFALSE )
+				{
+					/* The queue was empty and a block time was specified so
+					configure the timeout structure. */
+					vTaskSetTimeOutState( &xTimeOut );
+					xEntryTimeSet = pdTRUE;
+				}
+				else
+				{
+					/* Entry time was already set. */
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		/* Interrupts and other tasks can send to and receive from the queue
+		now the critical section has been exited. */
+
+		vTaskSuspendAll();
+		prvLockQueue( pxQueue );
+
+		/* Update the timeout state to see if it has expired yet. */
+		if( xTaskCheckForTimeOut( &xTimeOut, &xTicksToWait ) == pdFALSE )
+		{
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceBLOCKING_ON_QUEUE_RECEIVE( pxQueue );
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+					{
+						taskENTER_CRITICAL();
+						{
+							vTaskPriorityInherit( ( void * ) pxQueue->pxMutexHolder );
+						}
+						taskEXIT_CRITICAL();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif
+
+				vTaskPlaceOnEventList( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait );
+				prvUnlockQueue( pxQueue );
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* Try again. */
+				prvUnlockQueue( pxQueue );
+				( void ) xTaskResumeAll();
+			}
+		}
+		else
+		{
+			prvUnlockQueue( pxQueue );
+			( void ) xTaskResumeAll();
+
+			if( prvIsQueueEmpty( pxQueue ) != pdFALSE )
+			{
+				traceQUEUE_RECEIVE_FAILED( pxQueue );
+				return errQUEUE_EMPTY;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		const UBaseType_t uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+		/* Cannot block in an ISR, so check there is data available. */
+		if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			const int8_t cRxLock = pxQueue->cRxLock;
+
+			traceQUEUE_RECEIVE_FROM_ISR( pxQueue );
+
+			prvCopyDataFromQueue( pxQueue, pvBuffer );
+			pxQueue->uxMessagesWaiting = uxMessagesWaiting - 1;
+
+			/* If the queue is locked the event list will not be modified.
+			Instead update the lock count so the task that unlocks the queue
+			will know that an ISR has removed data while the queue was
+			locked. */
+			if( cRxLock == queueUNLOCKED )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority than us so
+						force a context switch. */
+						if( pxHigherPriorityTaskWoken != NULL )
+						{
+							*pxHigherPriorityTaskWoken = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* Increment the lock count so the task that unlocks the queue
+				knows that data was removed while it was locked. */
+				pxQueue->cRxLock = ( int8_t ) ( cRxLock + 1 );
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+			traceQUEUE_RECEIVE_FROM_ISR_FAILED( pxQueue );
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue,  void * const pvBuffer )
+{
+BaseType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+int8_t *pcOriginalReadPosition;
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+	configASSERT( pxQueue );
+	configASSERT( !( ( pvBuffer == NULL ) && ( pxQueue->uxItemSize != ( UBaseType_t ) 0U ) ) );
+	configASSERT( pxQueue->uxItemSize != 0 ); /* Can't peek a semaphore. */
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+	{
+		/* Cannot block in an ISR, so check there is data available. */
+		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			traceQUEUE_PEEK_FROM_ISR( pxQueue );
+
+			/* Remember the read position so it can be reset as nothing is
+			actually being removed from the queue. */
+			pcOriginalReadPosition = pxQueue->u.pcReadFrom;
+			prvCopyDataFromQueue( pxQueue, pvBuffer );
+			pxQueue->u.pcReadFrom = pcOriginalReadPosition;
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+			traceQUEUE_PEEK_FROM_ISR_FAILED( pxQueue );
+		}
+	}
+	portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+
+	configASSERT( xQueue );
+
+	taskENTER_CRITICAL();
+	{
+		uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+Queue_t *pxQueue;
+
+	pxQueue = ( Queue_t * ) xQueue;
+	configASSERT( pxQueue );
+
+	taskENTER_CRITICAL();
+	{
+		uxReturn = pxQueue->uxLength - pxQueue->uxMessagesWaiting;
+	}
+	taskEXIT_CRITICAL();
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue )
+{
+UBaseType_t uxReturn;
+
+	configASSERT( xQueue );
+
+	uxReturn = ( ( Queue_t * ) xQueue )->uxMessagesWaiting;
+
+	return uxReturn;
+} /*lint !e818 Pointer cannot be declared const as xQueue is a typedef not pointer. */
+/*-----------------------------------------------------------*/
+
+void vQueueDelete( QueueHandle_t xQueue )
+{
+Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+	configASSERT( pxQueue );
+	traceQUEUE_DELETE( pxQueue );
+
+	#if ( configQUEUE_REGISTRY_SIZE > 0 )
+	{
+		vQueueUnregisterQueue( pxQueue );
+	}
+	#endif
+
+	#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+	{
+		/* The queue can only have been allocated dynamically - free it
+		again. */
+		vPortFree( pxQueue );
+	}
+	#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+	{
+		/* The queue could have been allocated statically or dynamically, so
+		check before attempting to free the memory. */
+		if( pxQueue->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+		{
+			vPortFree( pxQueue );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#else
+	{
+		/* The queue must have been statically allocated, so is not going to be
+		deleted.  Avoid compiler warnings about the unused parameter. */
+		( void ) pxQueue;
+	}
+	#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue )
+	{
+		return ( ( Queue_t * ) xQueue )->uxQueueNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber )
+	{
+		( ( Queue_t * ) xQueue )->uxQueueNumber = uxQueueNumber;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	uint8_t ucQueueGetQueueType( QueueHandle_t xQueue )
+	{
+		return ( ( Queue_t * ) xQueue )->ucQueueType;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvCopyDataToQueue( Queue_t * const pxQueue, const void *pvItemToQueue, const BaseType_t xPosition )
+{
+BaseType_t xReturn = pdFALSE;
+UBaseType_t uxMessagesWaiting;
+
+	/* This function is called from a critical section. */
+
+	uxMessagesWaiting = pxQueue->uxMessagesWaiting;
+
+	if( pxQueue->uxItemSize == ( UBaseType_t ) 0 )
+	{
+		#if ( configUSE_MUTEXES == 1 )
+		{
+			if( pxQueue->uxQueueType == queueQUEUE_IS_MUTEX )
+			{
+				/* The mutex is no longer being held. */
+				xReturn = xTaskPriorityDisinherit( ( void * ) pxQueue->pxMutexHolder );
+				pxQueue->pxMutexHolder = NULL;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_MUTEXES */
+	}
+	else if( xPosition == queueSEND_TO_BACK )
+	{
+		( void ) memcpy( ( void * ) pxQueue->pcWriteTo, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports, plus previous logic ensures a null pointer can only be passed to memcpy() if the copy size is 0. */
+		pxQueue->pcWriteTo += pxQueue->uxItemSize;
+		if( pxQueue->pcWriteTo >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+		{
+			pxQueue->pcWriteTo = pxQueue->pcHead;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		( void ) memcpy( ( void * ) pxQueue->u.pcReadFrom, pvItemToQueue, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+		pxQueue->u.pcReadFrom -= pxQueue->uxItemSize;
+		if( pxQueue->u.pcReadFrom < pxQueue->pcHead ) /*lint !e946 MISRA exception justified as comparison of pointers is the cleanest solution. */
+		{
+			pxQueue->u.pcReadFrom = ( pxQueue->pcTail - pxQueue->uxItemSize );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( xPosition == queueOVERWRITE )
+		{
+			if( uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* An item is not being added but overwritten, so subtract
+				one from the recorded number of items in the queue so when
+				one is added again below the number of recorded items remains
+				correct. */
+				--uxMessagesWaiting;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	pxQueue->uxMessagesWaiting = uxMessagesWaiting + 1;
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCopyDataFromQueue( Queue_t * const pxQueue, void * const pvBuffer )
+{
+	if( pxQueue->uxItemSize != ( UBaseType_t ) 0 )
+	{
+		pxQueue->u.pcReadFrom += pxQueue->uxItemSize;
+		if( pxQueue->u.pcReadFrom >= pxQueue->pcTail ) /*lint !e946 MISRA exception justified as use of the relational operator is the cleanest solutions. */
+		{
+			pxQueue->u.pcReadFrom = pxQueue->pcHead;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+		( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( size_t ) pxQueue->uxItemSize ); /*lint !e961 !e418 MISRA exception as the casts are only redundant for some ports.  Also previous logic ensures a null pointer can only be passed to memcpy() when the count is 0. */
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvUnlockQueue( Queue_t * const pxQueue )
+{
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED. */
+
+	/* The lock counts contains the number of extra data items placed or
+	removed from the queue while the queue was locked.  When a queue is
+	locked items can be added or removed, but the event lists cannot be
+	updated. */
+	taskENTER_CRITICAL();
+	{
+		int8_t cTxLock = pxQueue->cTxLock;
+
+		/* See if data was added to the queue while it was locked. */
+		while( cTxLock > queueLOCKED_UNMODIFIED )
+		{
+			/* Data was posted while the queue was locked.  Are any tasks
+			blocked waiting for data to become available? */
+			#if ( configUSE_QUEUE_SETS == 1 )
+			{
+				if( pxQueue->pxQueueSetContainer != NULL )
+				{
+					if( prvNotifyQueueSetContainer( pxQueue, queueSEND_TO_BACK ) != pdFALSE )
+					{
+						/* The queue is a member of a queue set, and posting to
+						the queue set caused a higher priority task to unblock.
+						A context switch is required. */
+						vTaskMissedYield();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					/* Tasks that are removed from the event list will get
+					added to the pending ready list as the scheduler is still
+					suspended. */
+					if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+					{
+						if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+						{
+							/* The task waiting has a higher priority so record that a
+							context	switch is required. */
+							vTaskMissedYield();
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						break;
+					}
+				}
+			}
+			#else /* configUSE_QUEUE_SETS */
+			{
+				/* Tasks that are removed from the event list will get added to
+				the pending ready list as the scheduler is still suspended. */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority so record that
+						a context switch is required. */
+						vTaskMissedYield();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					break;
+				}
+			}
+			#endif /* configUSE_QUEUE_SETS */
+
+			--cTxLock;
+		}
+
+		pxQueue->cTxLock = queueUNLOCKED;
+	}
+	taskEXIT_CRITICAL();
+
+	/* Do the same for the Rx lock. */
+	taskENTER_CRITICAL();
+	{
+		int8_t cRxLock = pxQueue->cRxLock;
+
+		while( cRxLock > queueLOCKED_UNMODIFIED )
+		{
+			if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+			{
+				if( xTaskRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+				{
+					vTaskMissedYield();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				--cRxLock;
+			}
+			else
+			{
+				break;
+			}
+		}
+
+		pxQueue->cRxLock = queueUNLOCKED;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueEmpty( const Queue_t *pxQueue )
+{
+BaseType_t xReturn;
+
+	taskENTER_CRITICAL();
+	{
+		if( pxQueue->uxMessagesWaiting == ( UBaseType_t )  0 )
+		{
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue )
+{
+BaseType_t xReturn;
+
+	configASSERT( xQueue );
+	if( ( ( Queue_t * ) xQueue )->uxMessagesWaiting == ( UBaseType_t ) 0 )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvIsQueueFull( const Queue_t *pxQueue )
+{
+BaseType_t xReturn;
+
+	taskENTER_CRITICAL();
+	{
+		if( pxQueue->uxMessagesWaiting == pxQueue->uxLength )
+		{
+			xReturn = pdTRUE;
+		}
+		else
+		{
+			xReturn = pdFALSE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue )
+{
+BaseType_t xReturn;
+
+	configASSERT( xQueue );
+	if( ( ( Queue_t * ) xQueue )->uxMessagesWaiting == ( ( Queue_t * ) xQueue )->uxLength )
+	{
+		xReturn = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+		/* If the queue is already full we may have to block.  A critical section
+		is required to prevent an interrupt removing something from the queue
+		between the check to see if the queue is full and blocking on the queue. */
+		portDISABLE_INTERRUPTS();
+		{
+			if( prvIsQueueFull( pxQueue ) != pdFALSE )
+			{
+				/* The queue is full - do we want to block or just leave without
+				posting? */
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					/* As this is called from a coroutine we cannot block directly, but
+					return indicating that we need to block. */
+					vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToSend ) );
+					portENABLE_INTERRUPTS();
+					return errQUEUE_BLOCKED;
+				}
+				else
+				{
+					portENABLE_INTERRUPTS();
+					return errQUEUE_FULL;
+				}
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+			{
+				/* There is room in the queue, copy the data into the queue. */
+				prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+				xReturn = pdPASS;
+
+				/* Were any co-routines waiting for data to become available? */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					/* In this instance the co-routine could be placed directly
+					into the ready list as we are within a critical section.
+					Instead the same pending ready list mechanism is used as if
+					the event were caused from within an interrupt. */
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The co-routine waiting has a higher priority so record
+						that a yield might be appropriate. */
+						xReturn = errQUEUE_YIELD;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				xReturn = errQUEUE_FULL;
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+		/* If the queue is already empty we may have to block.  A critical section
+		is required to prevent an interrupt adding something to the queue
+		between the check to see if the queue is empty and blocking on the queue. */
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0 )
+			{
+				/* There are no messages in the queue, do we want to block or just
+				leave with nothing? */
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					/* As this is a co-routine we cannot block directly, but return
+					indicating that we need to block. */
+					vCoRoutineAddToDelayedList( xTicksToWait, &( pxQueue->xTasksWaitingToReceive ) );
+					portENABLE_INTERRUPTS();
+					return errQUEUE_BLOCKED;
+				}
+				else
+				{
+					portENABLE_INTERRUPTS();
+					return errQUEUE_FULL;
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		portDISABLE_INTERRUPTS();
+		{
+			if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+			{
+				/* Data is available from the queue. */
+				pxQueue->u.pcReadFrom += pxQueue->uxItemSize;
+				if( pxQueue->u.pcReadFrom >= pxQueue->pcTail )
+				{
+					pxQueue->u.pcReadFrom = pxQueue->pcHead;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+				--( pxQueue->uxMessagesWaiting );
+				( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+				xReturn = pdPASS;
+
+				/* Were any co-routines waiting for space to become available? */
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					/* In this instance the co-routine could be placed directly
+					into the ready list as we are within a critical section.
+					Instead the same pending ready list mechanism is used as if
+					the event were caused from within an interrupt. */
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						xReturn = errQUEUE_YIELD;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		portENABLE_INTERRUPTS();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken )
+	{
+	Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+		/* Cannot block within an ISR so if there is no space on the queue then
+		exit without doing anything. */
+		if( pxQueue->uxMessagesWaiting < pxQueue->uxLength )
+		{
+			prvCopyDataToQueue( pxQueue, pvItemToQueue, queueSEND_TO_BACK );
+
+			/* We only want to wake one co-routine per ISR, so check that a
+			co-routine has not already been woken. */
+			if( xCoRoutinePreviouslyWoken == pdFALSE )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						return pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xCoRoutinePreviouslyWoken;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_CO_ROUTINES == 1 )
+
+	BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxCoRoutineWoken )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+		/* We cannot block from an ISR, so check there is data available. If
+		not then just leave without doing anything. */
+		if( pxQueue->uxMessagesWaiting > ( UBaseType_t ) 0 )
+		{
+			/* Copy the data from the queue. */
+			pxQueue->u.pcReadFrom += pxQueue->uxItemSize;
+			if( pxQueue->u.pcReadFrom >= pxQueue->pcTail )
+			{
+				pxQueue->u.pcReadFrom = pxQueue->pcHead;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+			--( pxQueue->uxMessagesWaiting );
+			( void ) memcpy( ( void * ) pvBuffer, ( void * ) pxQueue->u.pcReadFrom, ( unsigned ) pxQueue->uxItemSize );
+
+			if( ( *pxCoRoutineWoken ) == pdFALSE )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueue->xTasksWaitingToSend ) ) == pdFALSE )
+				{
+					if( xCoRoutineRemoveFromEventList( &( pxQueue->xTasksWaitingToSend ) ) != pdFALSE )
+					{
+						*pxCoRoutineWoken = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_CO_ROUTINES */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcQueueName ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t ux;
+
+		/* See if there is an empty space in the registry.  A NULL name denotes
+		a free slot. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].pcQueueName == NULL )
+			{
+				/* Store the information on this queue. */
+				xQueueRegistry[ ux ].pcQueueName = pcQueueName;
+				xQueueRegistry[ ux ].xHandle = xQueue;
+
+				traceQUEUE_REGISTRY_ADD( xQueue, pcQueueName );
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	const char *pcQueueGetName( QueueHandle_t xQueue ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t ux;
+	const char *pcReturn = NULL; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+		/* Note there is nothing here to protect against another task adding or
+		removing entries from the registry while it is being searched. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].xHandle == xQueue )
+			{
+				pcReturn = xQueueRegistry[ ux ].pcQueueName;
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		return pcReturn;
+	}
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configQUEUE_REGISTRY_SIZE > 0 )
+
+	void vQueueUnregisterQueue( QueueHandle_t xQueue )
+	{
+	UBaseType_t ux;
+
+		/* See if the handle of the queue being unregistered in actually in the
+		registry. */
+		for( ux = ( UBaseType_t ) 0U; ux < ( UBaseType_t ) configQUEUE_REGISTRY_SIZE; ux++ )
+		{
+			if( xQueueRegistry[ ux ].xHandle == xQueue )
+			{
+				/* Set the name to NULL to show that this slot if free again. */
+				xQueueRegistry[ ux ].pcQueueName = NULL;
+
+				/* Set the handle to NULL to ensure the same queue handle cannot
+				appear in the registry twice if it is added, removed, then
+				added again. */
+				xQueueRegistry[ ux ].xHandle = ( QueueHandle_t ) 0;
+				break;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+	} /*lint !e818 xQueue could not be pointer to const because it is a typedef. */
+
+#endif /* configQUEUE_REGISTRY_SIZE */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TIMERS == 1 )
+
+	void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+	{
+	Queue_t * const pxQueue = ( Queue_t * ) xQueue;
+
+		/* This function should not be called by application code hence the
+		'Restricted' in its name.  It is not part of the public API.  It is
+		designed for use by kernel code, and has special calling requirements.
+		It can result in vListInsert() being called on a list that can only
+		possibly ever have one item in it, so the list will be fast, but even
+		so it should be called with the scheduler locked and not from a critical
+		section. */
+
+		/* Only do anything if there are no messages in the queue.  This function
+		will not actually cause the task to block, just place it on a blocked
+		list.  It will not block until the scheduler is unlocked - at which
+		time a yield will be performed.  If an item is added to the queue while
+		the queue is locked, and the calling task blocks on the queue, then the
+		calling task will be immediately unblocked when the queue is unlocked. */
+		prvLockQueue( pxQueue );
+		if( pxQueue->uxMessagesWaiting == ( UBaseType_t ) 0U )
+		{
+			/* There is nothing in the queue, block for the specified period. */
+			vTaskPlaceOnEventListRestricted( &( pxQueue->xTasksWaitingToReceive ), xTicksToWait, xWaitIndefinitely );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+		prvUnlockQueue( pxQueue );
+	}
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+#if( ( configUSE_QUEUE_SETS == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+
+	QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength )
+	{
+	QueueSetHandle_t pxQueue;
+
+		pxQueue = xQueueGenericCreate( uxEventQueueLength, sizeof( Queue_t * ), queueQUEUE_TYPE_SET );
+
+		return pxQueue;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+	{
+	BaseType_t xReturn;
+
+		taskENTER_CRITICAL();
+		{
+			if( ( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer != NULL )
+			{
+				/* Cannot add a queue/semaphore to more than one queue set. */
+				xReturn = pdFAIL;
+			}
+			else if( ( ( Queue_t * ) xQueueOrSemaphore )->uxMessagesWaiting != ( UBaseType_t ) 0 )
+			{
+				/* Cannot add a queue/semaphore to a queue set if there are already
+				items in the queue/semaphore. */
+				xReturn = pdFAIL;
+			}
+			else
+			{
+				( ( Queue_t * ) xQueueOrSemaphore )->pxQueueSetContainer = xQueueSet;
+				xReturn = pdPASS;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet )
+	{
+	BaseType_t xReturn;
+	Queue_t * const pxQueueOrSemaphore = ( Queue_t * ) xQueueOrSemaphore;
+
+		if( pxQueueOrSemaphore->pxQueueSetContainer != xQueueSet )
+		{
+			/* The queue was not a member of the set. */
+			xReturn = pdFAIL;
+		}
+		else if( pxQueueOrSemaphore->uxMessagesWaiting != ( UBaseType_t ) 0 )
+		{
+			/* It is dangerous to remove a queue from a set when the queue is
+			not empty because the queue set will still hold pending events for
+			the queue. */
+			xReturn = pdFAIL;
+		}
+		else
+		{
+			taskENTER_CRITICAL();
+			{
+				/* The queue is no longer contained in the set. */
+				pxQueueOrSemaphore->pxQueueSetContainer = NULL;
+			}
+			taskEXIT_CRITICAL();
+			xReturn = pdPASS;
+		}
+
+		return xReturn;
+	} /*lint !e818 xQueueSet could not be declared as pointing to const as it is a typedef. */
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, TickType_t const xTicksToWait )
+	{
+	QueueSetMemberHandle_t xReturn = NULL;
+
+		( void ) xQueueGenericReceive( ( QueueHandle_t ) xQueueSet, &xReturn, xTicksToWait, pdFALSE ); /*lint !e961 Casting from one typedef to another is not redundant. */
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet )
+	{
+	QueueSetMemberHandle_t xReturn = NULL;
+
+		( void ) xQueueReceiveFromISR( ( QueueHandle_t ) xQueueSet, &xReturn, NULL ); /*lint !e961 Casting from one typedef to another is not redundant. */
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_QUEUE_SETS == 1 )
+
+	static BaseType_t prvNotifyQueueSetContainer( const Queue_t * const pxQueue, const BaseType_t xCopyPosition )
+	{
+	Queue_t *pxQueueSetContainer = pxQueue->pxQueueSetContainer;
+	BaseType_t xReturn = pdFALSE;
+
+		/* This function must be called form a critical section. */
+
+		configASSERT( pxQueueSetContainer );
+		configASSERT( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength );
+
+		if( pxQueueSetContainer->uxMessagesWaiting < pxQueueSetContainer->uxLength )
+		{
+			const int8_t cTxLock = pxQueueSetContainer->cTxLock;
+
+			traceQUEUE_SEND( pxQueueSetContainer );
+
+			/* The data copied is the handle of the queue that contains data. */
+			xReturn = prvCopyDataToQueue( pxQueueSetContainer, &pxQueue, xCopyPosition );
+
+			if( cTxLock == queueUNLOCKED )
+			{
+				if( listLIST_IS_EMPTY( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) == pdFALSE )
+				{
+					if( xTaskRemoveFromEventList( &( pxQueueSetContainer->xTasksWaitingToReceive ) ) != pdFALSE )
+					{
+						/* The task waiting has a higher priority. */
+						xReturn = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				pxQueueSetContainer->cTxLock = ( int8_t ) ( cTxLock + 1 );
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_QUEUE_SETS */
+
+
+
+
+
+
+
+
+
+
+
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/queue.h b/STM32F1/libraries/FreeRTOS900/utility/queue.h
new file mode 100644
index 000000000..30be36013
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/queue.h
@@ -0,0 +1,1798 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+
+#ifndef QUEUE_H
+#define QUEUE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include queue.h"
+#endif
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+
+/**
+ * Type by which queues are referenced.  For example, a call to xQueueCreate()
+ * returns an QueueHandle_t variable that can then be used as a parameter to
+ * xQueueSend(), xQueueReceive(), etc.
+ */
+typedef void * QueueHandle_t;
+
+/**
+ * Type by which queue sets are referenced.  For example, a call to
+ * xQueueCreateSet() returns an xQueueSet variable that can then be used as a
+ * parameter to xQueueSelectFromSet(), xQueueAddToSet(), etc.
+ */
+typedef void * QueueSetHandle_t;
+
+/**
+ * Queue sets can contain both queues and semaphores, so the
+ * QueueSetMemberHandle_t is defined as a type to be used where a parameter or
+ * return value can be either an QueueHandle_t or an SemaphoreHandle_t.
+ */
+typedef void * QueueSetMemberHandle_t;
+
+/* For internal use only. */
+#define	queueSEND_TO_BACK		( ( BaseType_t ) 0 )
+#define	queueSEND_TO_FRONT		( ( BaseType_t ) 1 )
+#define queueOVERWRITE			( ( BaseType_t ) 2 )
+
+/* For internal use only.  These definitions *must* match those in queue.c. */
+#define queueQUEUE_TYPE_BASE				( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_SET					( ( uint8_t ) 0U )
+#define queueQUEUE_TYPE_MUTEX 				( ( uint8_t ) 1U )
+#define queueQUEUE_TYPE_COUNTING_SEMAPHORE	( ( uint8_t ) 2U )
+#define queueQUEUE_TYPE_BINARY_SEMAPHORE	( ( uint8_t ) 3U )
+#define queueQUEUE_TYPE_RECURSIVE_MUTEX		( ( uint8_t ) 4U )
+
+/**
+ * queue. h
+ * <pre>
+ QueueHandle_t xQueueCreate(
+							  UBaseType_t uxQueueLength,
+							  UBaseType_t uxItemSize
+						  );
+ * </pre>
+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory.  The first block is used to hold the queue's data structures.  The
+ * second block is used to hold items placed into the queue.  If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @return If the queue is successfully create then a handle to the newly
+ * created queue is returned.  If the queue cannot be created then 0 is
+ * returned.
+ *
+ * Example usage:
+   <pre>
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ };
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+	if( xQueue1 == 0 )
+	{
+		// Queue was not created and must not be used.
+	}
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue2 == 0 )
+	{
+		// Queue was not created and must not be used.
+	}
+
+	// ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueCreate xQueueCreate
+ * \ingroup QueueManagement
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xQueueCreate( uxQueueLength, uxItemSize ) xQueueGenericCreate( ( uxQueueLength ), ( uxItemSize ), ( queueQUEUE_TYPE_BASE ) )
+#endif
+
+/**
+ * queue. h
+ * <pre>
+ QueueHandle_t xQueueCreateStatic(
+							  UBaseType_t uxQueueLength,
+							  UBaseType_t uxItemSize,
+							  uint8_t *pucQueueStorageBuffer,
+							  StaticQueue_t *pxQueueBuffer
+						  );
+ * </pre>
+ *
+ * Creates a new queue instance, and returns a handle by which the new queue
+ * can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, queues use two blocks of
+ * memory.  The first block is used to hold the queue's data structures.  The
+ * second block is used to hold items placed into the queue.  If a queue is
+ * created using xQueueCreate() then both blocks of memory are automatically
+ * dynamically allocated inside the xQueueCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a queue is created using
+ * xQueueCreateStatic() then the application writer must provide the memory that
+ * will get used by the queue.  xQueueCreateStatic() therefore allows a queue to
+ * be created without using any dynamic memory allocation.
+ *
+ * http://www.FreeRTOS.org/Embedded-RTOS-Queues.html
+ *
+ * @param uxQueueLength The maximum number of items that the queue can contain.
+ *
+ * @param uxItemSize The number of bytes each item in the queue will require.
+ * Items are queued by copy, not by reference, so this is the number of bytes
+ * that will be copied for each posted item.  Each item on the queue must be
+ * the same size.
+ *
+ * @param pucQueueStorageBuffer If uxItemSize is not zero then
+ * pucQueueStorageBuffer must point to a uint8_t array that is at least large
+ * enough to hold the maximum number of items that can be in the queue at any
+ * one time - which is ( uxQueueLength * uxItemsSize ) bytes.  If uxItemSize is
+ * zero then pucQueueStorageBuffer can be NULL.
+ *
+ * @param pxQueueBuffer Must point to a variable of type StaticQueue_t, which
+ * will be used to hold the queue's data structure.
+ *
+ * @return If the queue is created then a handle to the created queue is
+ * returned.  If pxQueueBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+   <pre>
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ };
+
+ #define QUEUE_LENGTH 10
+ #define ITEM_SIZE sizeof( uint32_t )
+
+ // xQueueBuffer will hold the queue structure.
+ StaticQueue_t xQueueBuffer;
+
+ // ucQueueStorage will hold the items posted to the queue.  Must be at least
+ // [(queue length) * ( queue item size)] bytes long.
+ uint8_t ucQueueStorage[ QUEUE_LENGTH * ITEM_SIZE ];
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( QUEUE_LENGTH, // The number of items the queue can hold.
+							ITEM_SIZE	  // The size of each item in the queue
+							&( ucQueueStorage[ 0 ] ), // The buffer that will hold the items in the queue.
+							&xQueueBuffer ); // The buffer that will hold the queue structure.
+
+	// The queue is guaranteed to be created successfully as no dynamic memory
+	// allocation is used.  Therefore xQueue1 is now a handle to a valid queue.
+
+	// ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueCreateStatic xQueueCreateStatic
+ * \ingroup QueueManagement
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xQueueCreateStatic( uxQueueLength, uxItemSize, pucQueueStorage, pxQueueBuffer ) xQueueGenericCreateStatic( ( uxQueueLength ), ( uxItemSize ), ( pucQueueStorage ), ( pxQueueBuffer ), ( queueQUEUE_TYPE_BASE ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueSendToToFront(
+								   QueueHandle_t	xQueue,
+								   const void		*pvItemToQueue,
+								   TickType_t		xTicksToWait
+							   );
+ * </pre>
+ *
+ * This is a macro that calls xQueueGenericSend().
+ *
+ * Post an item to the front of a queue.  The item is queued by copy, not by
+ * reference.  This function must not be called from an interrupt service
+ * routine.  See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   <pre>
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSendToFront( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSendToFront( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFront( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_FRONT )
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueSendToBack(
+								   QueueHandle_t	xQueue,
+								   const void		*pvItemToQueue,
+								   TickType_t		xTicksToWait
+							   );
+ * </pre>
+ *
+ * This is a macro that calls xQueueGenericSend().
+ *
+ * Post an item to the back of a queue.  The item is queued by copy, not by
+ * reference.  This function must not be called from an interrupt service
+ * routine.  See xQueueSendFromISR () for an alternative which may be used
+ * in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the queue
+ * is full.  The  time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   <pre>
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSendToBack( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSendToBack( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBack( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueSend(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue,
+							  TickType_t xTicksToWait
+						 );
+ * </pre>
+ *
+ * This is a macro that calls xQueueGenericSend().  It is included for
+ * backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToFront() and xQueueSendToBack() macros.  It is
+ * equivalent to xQueueSendToBack().
+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   <pre>
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10 ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0 );
+	}
+
+	// ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+#define xQueueSend( xQueue, pvItemToQueue, xTicksToWait ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), ( xTicksToWait ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueOverwrite(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue
+						 );
+ * </pre>
+ *
+ * Only for use with queues that have a length of one - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue.  If the queue is already full then overwrite the
+ * value held in the queue.  The item is queued by copy, not by reference.
+ *
+ * This function must not be called from an interrupt service routine.
+ * See xQueueOverwriteFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle of the queue to which the data is being sent.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @return xQueueOverwrite() is a macro that calls xQueueGenericSend(), and
+ * therefore has the same return values as xQueueSendToFront().  However, pdPASS
+ * is the only value that can be returned because xQueueOverwrite() will write
+ * to the queue even when the queue is already full.
+ *
+ * Example usage:
+   <pre>
+
+ void vFunction( void *pvParameters )
+ {
+ QueueHandle_t xQueue;
+ uint32_t ulVarToSend, ulValReceived;
+
+	// Create a queue to hold one uint32_t value.  It is strongly
+	// recommended *not* to use xQueueOverwrite() on queues that can
+	// contain more than one value, and doing so will trigger an assertion
+	// if configASSERT() is defined.
+	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+
+	// Write the value 10 to the queue using xQueueOverwrite().
+	ulVarToSend = 10;
+	xQueueOverwrite( xQueue, &ulVarToSend );
+
+	// Peeking the queue should now return 10, but leave the value 10 in
+	// the queue.  A block time of zero is used as it is known that the
+	// queue holds a value.
+	ulValReceived = 0;
+	xQueuePeek( xQueue, &ulValReceived, 0 );
+
+	if( ulValReceived != 10 )
+	{
+		// Error unless the item was removed by a different task.
+	}
+
+	// The queue is still full.  Use xQueueOverwrite() to overwrite the
+	// value held in the queue with 100.
+	ulVarToSend = 100;
+	xQueueOverwrite( xQueue, &ulVarToSend );
+
+	// This time read from the queue, leaving the queue empty once more.
+	// A block time of 0 is used again.
+	xQueueReceive( xQueue, &ulValReceived, 0 );
+
+	// The value read should be the last value written, even though the
+	// queue was already full when the value was written.
+	if( ulValReceived != 100 )
+	{
+		// Error!
+	}
+
+	// ...
+}
+ </pre>
+ * \defgroup xQueueOverwrite xQueueOverwrite
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwrite( xQueue, pvItemToQueue ) xQueueGenericSend( ( xQueue ), ( pvItemToQueue ), 0, queueOVERWRITE )
+
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueGenericSend(
+									QueueHandle_t xQueue,
+									const void * pvItemToQueue,
+									TickType_t xTicksToWait
+									BaseType_t xCopyPosition
+								);
+ * </pre>
+ *
+ * It is preferred that the macros xQueueSend(), xQueueSendToFront() and
+ * xQueueSendToBack() are used in place of calling this function directly.
+ *
+ * Post an item on a queue.  The item is queued by copy, not by reference.
+ * This function must not be called from an interrupt service routine.
+ * See xQueueSendFromISR () for an alternative which may be used in an ISR.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for space to become available on the queue, should it already
+ * be full.  The call will return immediately if this is set to 0 and the
+ * queue is full.  The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the item was successfully posted, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+   <pre>
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ uint32_t ulVar = 10UL;
+
+ void vATask( void *pvParameters )
+ {
+ QueueHandle_t xQueue1, xQueue2;
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 uint32_t values.
+	xQueue1 = xQueueCreate( 10, sizeof( uint32_t ) );
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue2 = xQueueCreate( 10, sizeof( struct AMessage * ) );
+
+	// ...
+
+	if( xQueue1 != 0 )
+	{
+		// Send an uint32_t.  Wait for 10 ticks for space to become
+		// available if necessary.
+		if( xQueueGenericSend( xQueue1, ( void * ) &ulVar, ( TickType_t ) 10, queueSEND_TO_BACK ) != pdPASS )
+		{
+			// Failed to post the message, even after 10 ticks.
+		}
+	}
+
+	if( xQueue2 != 0 )
+	{
+		// Send a pointer to a struct AMessage object.  Don't block if the
+		// queue is already full.
+		pxMessage = & xMessage;
+		xQueueGenericSend( xQueue2, ( void * ) &pxMessage, ( TickType_t ) 0, queueSEND_TO_BACK );
+	}
+
+	// ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueSend xQueueSend
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSend( QueueHandle_t xQueue, const void * const pvItemToQueue, TickType_t xTicksToWait, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueuePeek(
+							 QueueHandle_t xQueue,
+							 void *pvBuffer,
+							 TickType_t xTicksToWait
+						 );</pre>
+ *
+ * This is a macro that calls the xQueueGenericReceive() function.
+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided.  The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * This macro must not be used in an interrupt service routine.  See
+ * xQueuePeekFromISR() for an alternative that can be called from an interrupt
+ * service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call.	 The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ * xQueuePeek() will return immediately if xTicksToWait is 0 and the queue
+ * is empty.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   <pre>
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to peek the data from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Peek a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueuePeek( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask, but the item still remains on the queue.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueReceive xQueueReceive
+ * \ingroup QueueManagement
+ */
+#define xQueuePeek( xQueue, pvBuffer, xTicksToWait ) xQueueGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdTRUE )
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueuePeekFromISR(
+									QueueHandle_t xQueue,
+									void *pvBuffer,
+								);</pre>
+ *
+ * A version of xQueuePeek() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Receive an item from a queue without removing the item from the queue.
+ * The item is received by copy so a buffer of adequate size must be
+ * provided.  The number of bytes copied into the buffer was defined when
+ * the queue was created.
+ *
+ * Successfully received items remain on the queue so will be returned again
+ * by the next call, or a call to xQueueReceive().
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * \defgroup xQueuePeekFromISR xQueuePeekFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueuePeekFromISR( QueueHandle_t xQueue, void * const pvBuffer ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueReceive(
+								 QueueHandle_t xQueue,
+								 void *pvBuffer,
+								 TickType_t xTicksToWait
+							);</pre>
+ *
+ * This is a macro that calls the xQueueGenericReceive() function.
+ *
+ * Receive an item from a queue.  The item is received by copy so a buffer of
+ * adequate size must be provided.  The number of bytes copied into the buffer
+ * was defined when the queue was created.
+ *
+ * Successfully received items are removed from the queue.
+ *
+ * This function must not be used in an interrupt service routine.  See
+ * xQueueReceiveFromISR for an alternative that can.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call.	 xQueueReceive() will return immediately if xTicksToWait
+ * is zero and the queue is empty.  The time is defined in tick periods so the
+ * constant portTICK_PERIOD_MS should be used to convert to real time if this is
+ * required.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   <pre>
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to receive from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Receive a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueueReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueReceive xQueueReceive
+ * \ingroup QueueManagement
+ */
+#define xQueueReceive( xQueue, pvBuffer, xTicksToWait ) xQueueGenericReceive( ( xQueue ), ( pvBuffer ), ( xTicksToWait ), pdFALSE )
+
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueGenericReceive(
+									   QueueHandle_t	xQueue,
+									   void	*pvBuffer,
+									   TickType_t	xTicksToWait
+									   BaseType_t	xJustPeek
+									);</pre>
+ *
+ * It is preferred that the macro xQueueReceive() be used rather than calling
+ * this function directly.
+ *
+ * Receive an item from a queue.  The item is received by copy so a buffer of
+ * adequate size must be provided.  The number of bytes copied into the buffer
+ * was defined when the queue was created.
+ *
+ * This function must not be used in an interrupt service routine.  See
+ * xQueueReceiveFromISR for an alternative that can.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param xTicksToWait The maximum amount of time the task should block
+ * waiting for an item to receive should the queue be empty at the time
+ * of the call.	 The time is defined in tick periods so the constant
+ * portTICK_PERIOD_MS should be used to convert to real time if this is required.
+ * xQueueGenericReceive() will return immediately if the queue is empty and
+ * xTicksToWait is 0.
+ *
+ * @param xJustPeek When set to true, the item received from the queue is not
+ * actually removed from the queue - meaning a subsequent call to
+ * xQueueReceive() will return the same item.  When set to false, the item
+ * being received from the queue is also removed from the queue.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   <pre>
+ struct AMessage
+ {
+	char ucMessageID;
+	char ucData[ 20 ];
+ } xMessage;
+
+ QueueHandle_t xQueue;
+
+ // Task to create a queue and post a value.
+ void vATask( void *pvParameters )
+ {
+ struct AMessage *pxMessage;
+
+	// Create a queue capable of containing 10 pointers to AMessage structures.
+	// These should be passed by pointer as they contain a lot of data.
+	xQueue = xQueueCreate( 10, sizeof( struct AMessage * ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Send a pointer to a struct AMessage object.  Don't block if the
+	// queue is already full.
+	pxMessage = & xMessage;
+	xQueueSend( xQueue, ( void * ) &pxMessage, ( TickType_t ) 0 );
+
+	// ... Rest of task code.
+ }
+
+ // Task to receive from the queue.
+ void vADifferentTask( void *pvParameters )
+ {
+ struct AMessage *pxRxedMessage;
+
+	if( xQueue != 0 )
+	{
+		// Receive a message on the created queue.  Block for 10 ticks if a
+		// message is not immediately available.
+		if( xQueueGenericReceive( xQueue, &( pxRxedMessage ), ( TickType_t ) 10 ) )
+		{
+			// pcRxedMessage now points to the struct AMessage variable posted
+			// by vATask.
+		}
+	}
+
+	// ... Rest of task code.
+ }
+ </pre>
+ * \defgroup xQueueReceive xQueueReceive
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericReceive( QueueHandle_t xQueue, void * const pvBuffer, TickType_t xTicksToWait, const BaseType_t xJustPeek ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue );</pre>
+ *
+ * Return the number of messages stored in a queue.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of messages available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueMessagesWaiting( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue );</pre>
+ *
+ * Return the number of free spaces available in a queue.  This is equal to the
+ * number of items that can be sent to the queue before the queue becomes full
+ * if no items are removed.
+ *
+ * @param xQueue A handle to the queue being queried.
+ *
+ * @return The number of spaces available in the queue.
+ *
+ * \defgroup uxQueueMessagesWaiting uxQueueMessagesWaiting
+ * \ingroup QueueManagement
+ */
+UBaseType_t uxQueueSpacesAvailable( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>void vQueueDelete( QueueHandle_t xQueue );</pre>
+ *
+ * Delete a queue - freeing all the memory allocated for storing of items
+ * placed on the queue.
+ *
+ * @param xQueue A handle to the queue to be deleted.
+ *
+ * \defgroup vQueueDelete vQueueDelete
+ * \ingroup QueueManagement
+ */
+void vQueueDelete( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueSendToFrontFromISR(
+										 QueueHandle_t xQueue,
+										 const void *pvItemToQueue,
+										 BaseType_t *pxHigherPriorityTaskWoken
+									  );
+ </pre>
+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the front of a queue.  It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToFrontFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendToFromFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   <pre>
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPrioritTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendToFrontFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		taskYIELD ();
+	}
+ }
+ </pre>
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToFrontFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_FRONT )
+
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueSendToBackFromISR(
+										 QueueHandle_t xQueue,
+										 const void *pvItemToQueue,
+										 BaseType_t *pxHigherPriorityTaskWoken
+									  );
+ </pre>
+ *
+ * This is a macro that calls xQueueGenericSendFromISR().
+ *
+ * Post an item to the back of a queue.  It is safe to use this macro from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendToBackFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendToBackFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   <pre>
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendToBackFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		taskYIELD ();
+	}
+ }
+ </pre>
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendToBackFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueOverwriteFromISR(
+							  QueueHandle_t xQueue,
+							  const void * pvItemToQueue,
+							  BaseType_t *pxHigherPriorityTaskWoken
+						 );
+ * </pre>
+ *
+ * A version of xQueueOverwrite() that can be used in an interrupt service
+ * routine (ISR).
+ *
+ * Only for use with queues that can hold a single item - so the queue is either
+ * empty or full.
+ *
+ * Post an item on a queue.  If the queue is already full then overwrite the
+ * value held in the queue.  The item is queued by copy, not by reference.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueOverwriteFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueOverwriteFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return xQueueOverwriteFromISR() is a macro that calls
+ * xQueueGenericSendFromISR(), and therefore has the same return values as
+ * xQueueSendToFrontFromISR().  However, pdPASS is the only value that can be
+ * returned because xQueueOverwriteFromISR() will write to the queue even when
+ * the queue is already full.
+ *
+ * Example usage:
+   <pre>
+
+ QueueHandle_t xQueue;
+
+ void vFunction( void *pvParameters )
+ {
+ 	// Create a queue to hold one uint32_t value.  It is strongly
+	// recommended *not* to use xQueueOverwriteFromISR() on queues that can
+	// contain more than one value, and doing so will trigger an assertion
+	// if configASSERT() is defined.
+	xQueue = xQueueCreate( 1, sizeof( uint32_t ) );
+}
+
+void vAnInterruptHandler( void )
+{
+// xHigherPriorityTaskWoken must be set to pdFALSE before it is used.
+BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+uint32_t ulVarToSend, ulValReceived;
+
+	// Write the value 10 to the queue using xQueueOverwriteFromISR().
+	ulVarToSend = 10;
+	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+	// The queue is full, but calling xQueueOverwriteFromISR() again will still
+	// pass because the value held in the queue will be overwritten with the
+	// new value.
+	ulVarToSend = 100;
+	xQueueOverwriteFromISR( xQueue, &ulVarToSend, &xHigherPriorityTaskWoken );
+
+	// Reading from the queue will now return 100.
+
+	// ...
+
+	if( xHigherPrioritytaskWoken == pdTRUE )
+	{
+		// Writing to the queue caused a task to unblock and the unblocked task
+		// has a priority higher than or equal to the priority of the currently
+		// executing task (the task this interrupt interrupted).  Perform a context
+		// switch so this interrupt returns directly to the unblocked task.
+		portYIELD_FROM_ISR(); // or portEND_SWITCHING_ISR() depending on the port.
+	}
+}
+ </pre>
+ * \defgroup xQueueOverwriteFromISR xQueueOverwriteFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueOverwriteFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueOVERWRITE )
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueSendFromISR(
+									 QueueHandle_t xQueue,
+									 const void *pvItemToQueue,
+									 BaseType_t *pxHigherPriorityTaskWoken
+								);
+ </pre>
+ *
+ * This is a macro that calls xQueueGenericSendFromISR().  It is included
+ * for backward compatibility with versions of FreeRTOS.org that did not
+ * include the xQueueSendToBackFromISR() and xQueueSendToFrontFromISR()
+ * macros.
+ *
+ * Post an item to the back of a queue.  It is safe to use this function from
+ * within an interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   <pre>
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWoken;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWoken = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post the byte.
+		xQueueSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWoken );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.
+	if( xHigherPriorityTaskWoken )
+	{
+		// Actual macro used here is port specific.
+		portYIELD_FROM_ISR ();
+	}
+ }
+ </pre>
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+#define xQueueSendFromISR( xQueue, pvItemToQueue, pxHigherPriorityTaskWoken ) xQueueGenericSendFromISR( ( xQueue ), ( pvItemToQueue ), ( pxHigherPriorityTaskWoken ), queueSEND_TO_BACK )
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueGenericSendFromISR(
+										   QueueHandle_t		xQueue,
+										   const	void	*pvItemToQueue,
+										   BaseType_t	*pxHigherPriorityTaskWoken,
+										   BaseType_t	xCopyPosition
+									   );
+ </pre>
+ *
+ * It is preferred that the macros xQueueSendFromISR(),
+ * xQueueSendToFrontFromISR() and xQueueSendToBackFromISR() be used in place
+ * of calling this function directly.  xQueueGiveFromISR() is an
+ * equivalent for use by semaphores that don't actually copy any data.
+ *
+ * Post an item on a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * Items are queued by copy not reference so it is preferable to only
+ * queue small items, especially when called from an ISR.  In most cases
+ * it would be preferable to store a pointer to the item being queued.
+ *
+ * @param xQueue The handle to the queue on which the item is to be posted.
+ *
+ * @param pvItemToQueue A pointer to the item that is to be placed on the
+ * queue.  The size of the items the queue will hold was defined when the
+ * queue was created, so this many bytes will be copied from pvItemToQueue
+ * into the queue storage area.
+ *
+ * @param pxHigherPriorityTaskWoken xQueueGenericSendFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending to the queue caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xQueueGenericSendFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @param xCopyPosition Can take the value queueSEND_TO_BACK to place the
+ * item at the back of the queue, or queueSEND_TO_FRONT to place the item
+ * at the front of the queue (for high priority messages).
+ *
+ * @return pdTRUE if the data was successfully sent to the queue, otherwise
+ * errQUEUE_FULL.
+ *
+ * Example usage for buffered IO (where the ISR can obtain more than one value
+ * per call):
+   <pre>
+ void vBufferISR( void )
+ {
+ char cIn;
+ BaseType_t xHigherPriorityTaskWokenByPost;
+
+	// We have not woken a task at the start of the ISR.
+	xHigherPriorityTaskWokenByPost = pdFALSE;
+
+	// Loop until the buffer is empty.
+	do
+	{
+		// Obtain a byte from the buffer.
+		cIn = portINPUT_BYTE( RX_REGISTER_ADDRESS );
+
+		// Post each byte.
+		xQueueGenericSendFromISR( xRxQueue, &cIn, &xHigherPriorityTaskWokenByPost, queueSEND_TO_BACK );
+
+	} while( portINPUT_BYTE( BUFFER_COUNT ) );
+
+	// Now the buffer is empty we can switch context if necessary.  Note that the
+	// name of the yield function required is port specific.
+	if( xHigherPriorityTaskWokenByPost )
+	{
+		taskYIELD_YIELD_FROM_ISR();
+	}
+ }
+ </pre>
+ *
+ * \defgroup xQueueSendFromISR xQueueSendFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueGenericSendFromISR( QueueHandle_t xQueue, const void * const pvItemToQueue, BaseType_t * const pxHigherPriorityTaskWoken, const BaseType_t xCopyPosition ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveFromISR( QueueHandle_t xQueue, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * queue. h
+ * <pre>
+ BaseType_t xQueueReceiveFromISR(
+									   QueueHandle_t	xQueue,
+									   void	*pvBuffer,
+									   BaseType_t *pxTaskWoken
+								   );
+ * </pre>
+ *
+ * Receive an item from a queue.  It is safe to use this function from within an
+ * interrupt service routine.
+ *
+ * @param xQueue The handle to the queue from which the item is to be
+ * received.
+ *
+ * @param pvBuffer Pointer to the buffer into which the received item will
+ * be copied.
+ *
+ * @param pxTaskWoken A task may be blocked waiting for space to become
+ * available on the queue.  If xQueueReceiveFromISR causes such a task to
+ * unblock *pxTaskWoken will get set to pdTRUE, otherwise *pxTaskWoken will
+ * remain unchanged.
+ *
+ * @return pdTRUE if an item was successfully received from the queue,
+ * otherwise pdFALSE.
+ *
+ * Example usage:
+   <pre>
+
+ QueueHandle_t xQueue;
+
+ // Function to create a queue and post some values.
+ void vAFunction( void *pvParameters )
+ {
+ char cValueToPost;
+ const TickType_t xTicksToWait = ( TickType_t )0xff;
+
+	// Create a queue capable of containing 10 characters.
+	xQueue = xQueueCreate( 10, sizeof( char ) );
+	if( xQueue == 0 )
+	{
+		// Failed to create the queue.
+	}
+
+	// ...
+
+	// Post some characters that will be used within an ISR.  If the queue
+	// is full then this task will block for xTicksToWait ticks.
+	cValueToPost = 'a';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+	cValueToPost = 'b';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+
+	// ... keep posting characters ... this task may block when the queue
+	// becomes full.
+
+	cValueToPost = 'c';
+	xQueueSend( xQueue, ( void * ) &cValueToPost, xTicksToWait );
+ }
+
+ // ISR that outputs all the characters received on the queue.
+ void vISR_Routine( void )
+ {
+ BaseType_t xTaskWokenByReceive = pdFALSE;
+ char cRxedChar;
+
+	while( xQueueReceiveFromISR( xQueue, ( void * ) &cRxedChar, &xTaskWokenByReceive) )
+	{
+		// A character was received.  Output the character now.
+		vOutputCharacter( cRxedChar );
+
+		// If removing the character from the queue woke the task that was
+		// posting onto the queue cTaskWokenByReceive will have been set to
+		// pdTRUE.  No matter how many times this loop iterates only one
+		// task will be woken.
+	}
+
+	if( cTaskWokenByPost != ( char ) pdFALSE;
+	{
+		taskYIELD ();
+	}
+ }
+ </pre>
+ * \defgroup xQueueReceiveFromISR xQueueReceiveFromISR
+ * \ingroup QueueManagement
+ */
+BaseType_t xQueueReceiveFromISR( QueueHandle_t xQueue, void * const pvBuffer, BaseType_t * const pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/*
+ * Utilities to query queues that are safe to use from an ISR.  These utilities
+ * should be used only from witin an ISR, or within a critical section.
+ */
+BaseType_t xQueueIsQueueEmptyFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueIsQueueFullFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueMessagesWaitingFromISR( const QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+/*
+ * The functions defined above are for passing data to and from tasks.  The
+ * functions below are the equivalents for passing data to and from
+ * co-routines.
+ *
+ * These functions are called from the co-routine macro implementation and
+ * should not be called directly from application code.  Instead use the macro
+ * wrappers defined within croutine.h.
+ */
+BaseType_t xQueueCRSendFromISR( QueueHandle_t xQueue, const void *pvItemToQueue, BaseType_t xCoRoutinePreviouslyWoken );
+BaseType_t xQueueCRReceiveFromISR( QueueHandle_t xQueue, void *pvBuffer, BaseType_t *pxTaskWoken );
+BaseType_t xQueueCRSend( QueueHandle_t xQueue, const void *pvItemToQueue, TickType_t xTicksToWait );
+BaseType_t xQueueCRReceive( QueueHandle_t xQueue, void *pvBuffer, TickType_t xTicksToWait );
+
+/*
+ * For internal use only.  Use xSemaphoreCreateMutex(),
+ * xSemaphoreCreateCounting() or xSemaphoreGetMutexHolder() instead of calling
+ * these functions directly.
+ */
+QueueHandle_t xQueueCreateMutex( const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateMutexStatic( const uint8_t ucQueueType, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphore( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount ) PRIVILEGED_FUNCTION;
+QueueHandle_t xQueueCreateCountingSemaphoreStatic( const UBaseType_t uxMaxCount, const UBaseType_t uxInitialCount, StaticQueue_t *pxStaticQueue ) PRIVILEGED_FUNCTION;
+void* xQueueGetMutexHolder( QueueHandle_t xSemaphore ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Use xSemaphoreTakeMutexRecursive() or
+ * xSemaphoreGiveMutexRecursive() instead of calling these functions directly.
+ */
+BaseType_t xQueueTakeMutexRecursive( QueueHandle_t xMutex, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGiveMutexRecursive( QueueHandle_t pxMutex ) PRIVILEGED_FUNCTION;
+
+/*
+ * Reset a queue back to its original empty state.  The return value is now
+ * obsolete and is always set to pdPASS.
+ */
+#define xQueueReset( xQueue ) xQueueGenericReset( xQueue, pdFALSE )
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger.  If you are not using a kernel
+ * aware debugger then this function can be ignored.
+ *
+ * configQUEUE_REGISTRY_SIZE defines the maximum number of handles the
+ * registry can hold.  configQUEUE_REGISTRY_SIZE must be greater than 0
+ * within FreeRTOSConfig.h for the registry to be available.  Its value
+ * does not effect the number of queues, semaphores and mutexes that can be
+ * created - just the number that the registry can hold.
+ *
+ * @param xQueue The handle of the queue being added to the registry.  This
+ * is the handle returned by a call to xQueueCreate().  Semaphore and mutex
+ * handles can also be passed in here.
+ *
+ * @param pcName The name to be associated with the handle.  This is the
+ * name that the kernel aware debugger will display.  The queue registry only
+ * stores a pointer to the string - so the string must be persistent (global or
+ * preferably in ROM/Flash), not on the stack.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	void vQueueAddToRegistry( QueueHandle_t xQueue, const char *pcName ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * The registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call vQueueAddToRegistry() add
+ * a queue, semaphore or mutex handle to the registry if you want the handle
+ * to be available to a kernel aware debugger, and vQueueUnregisterQueue() to
+ * remove the queue, semaphore or mutex from the register.  If you are not using
+ * a kernel aware debugger then this function can be ignored.
+ *
+ * @param xQueue The handle of the queue being removed from the registry.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	void vQueueUnregisterQueue( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * The queue registry is provided as a means for kernel aware debuggers to
+ * locate queues, semaphores and mutexes.  Call pcQueueGetName() to look
+ * up and return the name of a queue in the queue registry from the queue's
+ * handle.
+ *
+ * @param xQueue The handle of the queue the name of which will be returned.
+ * @return If the queue is in the registry then a pointer to the name of the
+ * queue is returned.  If the queue is not in the registry then NULL is
+ * returned.
+ */
+#if( configQUEUE_REGISTRY_SIZE > 0 )
+	const char *pcQueueGetName( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/*
+ * Generic version of the function used to creaet a queue using dynamic memory
+ * allocation.  This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	QueueHandle_t xQueueGenericCreate( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Generic version of the function used to creaet a queue using dynamic memory
+ * allocation.  This is called by other functions and macros that create other
+ * RTOS objects that use the queue structure as their base.
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	QueueHandle_t xQueueGenericCreateStatic( const UBaseType_t uxQueueLength, const UBaseType_t uxItemSize, uint8_t *pucQueueStorage, StaticQueue_t *pxStaticQueue, const uint8_t ucQueueType ) PRIVILEGED_FUNCTION;
+#endif
+
+/*
+ * Queue sets provide a mechanism to allow a task to block (pend) on a read
+ * operation from multiple queues or semaphores simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * A queue set must be explicitly created using a call to xQueueCreateSet()
+ * before it can be used.  Once created, standard FreeRTOS queues and semaphores
+ * can be added to the set using calls to xQueueAddToSet().
+ * xQueueSelectFromSet() is then used to determine which, if any, of the queues
+ * or semaphores contained in the set is in a state where a queue read or
+ * semaphore take operation would be successful.
+ *
+ * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  An additional 4 bytes of RAM is required for each space in a every
+ * queue added to a queue set.  Therefore counting semaphores that have a high
+ * maximum count value should not be added to a queue set.
+ *
+ * Note 4:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param uxEventQueueLength Queue sets store events that occur on
+ * the queues and semaphores contained in the set.  uxEventQueueLength specifies
+ * the maximum number of events that can be queued at once.  To be absolutely
+ * certain that events are not lost uxEventQueueLength should be set to the
+ * total sum of the length of the queues added to the set, where binary
+ * semaphores and mutexes have a length of 1, and counting semaphores have a
+ * length set by their maximum count value.  Examples:
+ *  + If a queue set is to hold a queue of length 5, another queue of length 12,
+ *    and a binary semaphore, then uxEventQueueLength should be set to
+ *    (5 + 12 + 1), or 18.
+ *  + If a queue set is to hold three binary semaphores then uxEventQueueLength
+ *    should be set to (1 + 1 + 1 ), or 3.
+ *  + If a queue set is to hold a counting semaphore that has a maximum count of
+ *    5, and a counting semaphore that has a maximum count of 3, then
+ *    uxEventQueueLength should be set to (5 + 3), or 8.
+ *
+ * @return If the queue set is created successfully then a handle to the created
+ * queue set is returned.  Otherwise NULL is returned.
+ */
+QueueSetHandle_t xQueueCreateSet( const UBaseType_t uxEventQueueLength ) PRIVILEGED_FUNCTION;
+
+/*
+ * Adds a queue or semaphore to a queue set that was previously created by a
+ * call to xQueueCreateSet().
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being added to
+ * the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set to which the queue or semaphore
+ * is being added.
+ *
+ * @return If the queue or semaphore was successfully added to the queue set
+ * then pdPASS is returned.  If the queue could not be successfully added to the
+ * queue set because it is already a member of a different queue set then pdFAIL
+ * is returned.
+ */
+BaseType_t xQueueAddToSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * Removes a queue or semaphore from a queue set.  A queue or semaphore can only
+ * be removed from a set if the queue or semaphore is empty.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * @param xQueueOrSemaphore The handle of the queue or semaphore being removed
+ * from the queue set (cast to an QueueSetMemberHandle_t type).
+ *
+ * @param xQueueSet The handle of the queue set in which the queue or semaphore
+ * is included.
+ *
+ * @return If the queue or semaphore was successfully removed from the queue set
+ * then pdPASS is returned.  If the queue was not in the queue set, or the
+ * queue (or semaphore) was not empty, then pdFAIL is returned.
+ */
+BaseType_t xQueueRemoveFromSet( QueueSetMemberHandle_t xQueueOrSemaphore, QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/*
+ * xQueueSelectFromSet() selects from the members of a queue set a queue or
+ * semaphore that either contains data (in the case of a queue) or is available
+ * to take (in the case of a semaphore).  xQueueSelectFromSet() effectively
+ * allows a task to block (pend) on a read operation on all the queues and
+ * semaphores in a queue set simultaneously.
+ *
+ * See FreeRTOS/Source/Demo/Common/Minimal/QueueSet.c for an example using this
+ * function.
+ *
+ * Note 1:  See the documentation on http://wwwFreeRTOS.org/RTOS-queue-sets.html
+ * for reasons why queue sets are very rarely needed in practice as there are
+ * simpler methods of blocking on multiple objects.
+ *
+ * Note 2:  Blocking on a queue set that contains a mutex will not cause the
+ * mutex holder to inherit the priority of the blocked task.
+ *
+ * Note 3:  A receive (in the case of a queue) or take (in the case of a
+ * semaphore) operation must not be performed on a member of a queue set unless
+ * a call to xQueueSelectFromSet() has first returned a handle to that set member.
+ *
+ * @param xQueueSet The queue set on which the task will (potentially) block.
+ *
+ * @param xTicksToWait The maximum time, in ticks, that the calling task will
+ * remain in the Blocked state (with other tasks executing) to wait for a member
+ * of the queue set to be ready for a successful queue read or semaphore take
+ * operation.
+ *
+ * @return xQueueSelectFromSet() will return the handle of a queue (cast to
+ * a QueueSetMemberHandle_t type) contained in the queue set that contains data,
+ * or the handle of a semaphore (cast to a QueueSetMemberHandle_t type) contained
+ * in the queue set that is available, or NULL if no such queue or semaphore
+ * exists before before the specified block time expires.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSet( QueueSetHandle_t xQueueSet, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * A version of xQueueSelectFromSet() that can be used from an ISR.
+ */
+QueueSetMemberHandle_t xQueueSelectFromSetFromISR( QueueSetHandle_t xQueueSet ) PRIVILEGED_FUNCTION;
+
+/* Not public API functions. */
+void vQueueWaitForMessageRestricted( QueueHandle_t xQueue, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+BaseType_t xQueueGenericReset( QueueHandle_t xQueue, BaseType_t xNewQueue ) PRIVILEGED_FUNCTION;
+void vQueueSetQueueNumber( QueueHandle_t xQueue, UBaseType_t uxQueueNumber ) PRIVILEGED_FUNCTION;
+UBaseType_t uxQueueGetQueueNumber( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+uint8_t ucQueueGetQueueType( QueueHandle_t xQueue ) PRIVILEGED_FUNCTION;
+
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* QUEUE_H */
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/readme.txt b/STM32F1/libraries/FreeRTOS900/utility/readme.txt
new file mode 100644
index 000000000..58480c56b
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/readme.txt
@@ -0,0 +1,17 @@
+Each real time kernel port consists of three files that contain the core kernel
+components and are common to every port, and one or more files that are 
+specific to a particular microcontroller and or compiler.
+
++ The FreeRTOS/Source directory contains the three files that are common to 
+every port - list.c, queue.c and tasks.c.  The kernel is contained within these 
+three files.  croutine.c implements the optional co-routine functionality - which
+is normally only used on very memory limited systems.
+
++ The FreeRTOS/Source/Portable directory contains the files that are specific to 
+a particular microcontroller and or compiler.
+
++ The FreeRTOS/Source/include directory contains the real time kernel header 
+files.
+
+See the readme file in the FreeRTOS/Source/Portable directory for more 
+information.
\ No newline at end of file
diff --git a/STM32F1/libraries/FreeRTOS900/utility/semphr.h b/STM32F1/libraries/FreeRTOS900/utility/semphr.h
new file mode 100644
index 000000000..a674b02a4
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/semphr.h
@@ -0,0 +1,1171 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+#ifndef SEMAPHORE_H
+#define SEMAPHORE_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h" must appear in source files before "include semphr.h"
+#endif
+
+#include "queue.h"
+
+typedef QueueHandle_t SemaphoreHandle_t;
+
+#define semBINARY_SEMAPHORE_QUEUE_LENGTH	( ( uint8_t ) 1U )
+#define semSEMAPHORE_QUEUE_ITEM_LENGTH		( ( uint8_t ) 0U )
+#define semGIVE_BLOCK_TIME					( ( TickType_t ) 0U )
+
+
+/**
+ * semphr. h
+ * <pre>vSemaphoreCreateBinary( SemaphoreHandle_t xSemaphore )</pre>
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * This old vSemaphoreCreateBinary() macro is now deprecated in favour of the
+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * <i>Macro</i> that implements a semaphore by using the existing queue mechanism.
+ * The queue length is 1 as this is a binary semaphore.  The data size is 0
+ * as we don't want to actually store any data - we just want to know if the
+ * queue is empty or full.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param xSemaphore Handle to the created semaphore.  Should be of type SemaphoreHandle_t.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to vSemaphoreCreateBinary ().
+    // This is a macro so pass the variable in directly.
+    vSemaphoreCreateBinary( xSemaphore );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ </pre>
+ * \defgroup vSemaphoreCreateBinary vSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define vSemaphoreCreateBinary( xSemaphore )																							\
+		{																																	\
+			( xSemaphore ) = xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE );	\
+			if( ( xSemaphore ) != NULL )																									\
+			{																																\
+				( void ) xSemaphoreGive( ( xSemaphore ) );																					\
+			}																																\
+		}
+#endif
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateBinary( void )</pre>
+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored.  If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * The old vSemaphoreCreateBinary() macro is now deprecated in favour of this
+ * xSemaphoreCreateBinary() function.  Note that binary semaphores created using
+ * the vSemaphoreCreateBinary() macro are created in a state such that the
+ * first call to 'take' the semaphore would pass, whereas binary semaphores
+ * created using xSemaphoreCreateBinary() are created in a state such that the
+ * the semaphore must first be 'given' before it can be 'taken'.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @return Handle to the created semaphore, or NULL if the memory required to
+ * hold the semaphore's data structures could not be allocated.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateBinary();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateBinary xSemaphoreCreateBinary
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateBinary() xQueueGenericCreate( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateBinaryStatic( StaticSemaphore_t *pxSemaphoreBuffer )</pre>
+ *
+ * Creates a new binary semaphore instance, and returns a handle by which the
+ * new semaphore can be referenced.
+ *
+ * NOTE: In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a binary semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, binary semaphores use a block
+ * of memory, in which the semaphore structure is stored.  If a binary semaphore
+ * is created using xSemaphoreCreateBinary() then the required memory is
+ * automatically dynamically allocated inside the xSemaphoreCreateBinary()
+ * function.  (see http://www.freertos.org/a00111.html).  If a binary semaphore
+ * is created using xSemaphoreCreateBinaryStatic() then the application writer
+ * must provide the memory.  xSemaphoreCreateBinaryStatic() therefore allows a
+ * binary semaphore to be created without using any dynamic memory allocation.
+ *
+ * This type of semaphore can be used for pure synchronisation between tasks or
+ * between an interrupt and a task.  The semaphore need not be given back once
+ * obtained, so one task/interrupt can continuously 'give' the semaphore while
+ * another continuously 'takes' the semaphore.  For this reason this type of
+ * semaphore does not use a priority inheritance mechanism.  For an alternative
+ * that does use priority inheritance see xSemaphoreCreateMutex().
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the semaphore is created then a handle to the created semaphore is
+ * returned.  If pxSemaphoreBuffer is NULL then NULL is returned.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore = NULL;
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateBinary().
+    // The semaphore's data structures will be placed in the xSemaphoreBuffer
+    // variable, the address of which is passed into the function.  The
+    // function's parameter is not NULL, so the function will not attempt any
+    // dynamic memory allocation, and therefore the function will not return
+    // return NULL.
+    xSemaphore = xSemaphoreCreateBinary( &xSemaphoreBuffer );
+
+    // Rest of task code goes here.
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateBinaryStatic xSemaphoreCreateBinaryStatic
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateBinaryStatic( pxStaticSemaphore ) xQueueGenericCreateStatic( ( UBaseType_t ) 1, semSEMAPHORE_QUEUE_ITEM_LENGTH, NULL, pxStaticSemaphore, queueQUEUE_TYPE_BINARY_SEMAPHORE )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * <pre>xSemaphoreTake(
+ *                   SemaphoreHandle_t xSemaphore,
+ *                   TickType_t xBlockTime
+ *               )</pre>
+ *
+ * <i>Macro</i> to obtain a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting().
+ *
+ * @param xSemaphore A handle to the semaphore being taken - obtained when
+ * the semaphore was created.
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time.  A block time of zero can be used to poll the semaphore.  A block
+ * time of portMAX_DELAY can be used to block indefinitely (provided
+ * INCLUDE_vTaskSuspend is set to 1 in FreeRTOSConfig.h).
+ *
+ * @return pdTRUE if the semaphore was obtained.  pdFALSE
+ * if xBlockTime expired without the semaphore becoming available.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // A task that creates a semaphore.
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    xSemaphore = xSemaphoreCreateBinary();
+ }
+
+ // A task that uses the semaphore.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xSemaphore != NULL )
+    {
+        // See if we can obtain the semaphore.  If the semaphore is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the semaphore and can now access the
+            // shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource.  Release the
+            // semaphore.
+            xSemaphoreGive( xSemaphore );
+        }
+        else
+        {
+            // We could not obtain the semaphore and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreTake xSemaphoreTake
+ * \ingroup Semaphores
+ */
+#define xSemaphoreTake( xSemaphore, xBlockTime )		xQueueGenericReceive( ( QueueHandle_t ) ( xSemaphore ), NULL, ( xBlockTime ), pdFALSE )
+
+/**
+ * semphr. h
+ * xSemaphoreTakeRecursive(
+ *                          SemaphoreHandle_t xMutex,
+ *                          TickType_t xBlockTime
+ *                        )
+ *
+ * <i>Macro</i> to recursively obtain, or 'take', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being obtained.  This is the
+ * handle returned by xSemaphoreCreateRecursiveMutex();
+ *
+ * @param xBlockTime The time in ticks to wait for the semaphore to become
+ * available.  The macro portTICK_PERIOD_MS can be used to convert this to a
+ * real time.  A block time of zero can be used to poll the semaphore.  If
+ * the task already owns the semaphore then xSemaphoreTakeRecursive() will
+ * return immediately no matter what the value of xBlockTime.
+ *
+ * @return pdTRUE if the semaphore was obtained.  pdFALSE if xBlockTime
+ * expired without the semaphore becoming available.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTakeRecursive( xSemaphore, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to
+			// xSemaphoreTakeRecursive() are made on the same mutex.  In real
+			// code these would not be just sequential calls as this would make
+			// no sense.  Instead the calls are likely to be buried inside
+			// a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be
+			// available to another task until it has also been given back
+			// three times.  Again it is unlikely that real code would have
+			// these calls sequentially, but instead buried in a more complex
+			// call structure.  This is just for illustrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+
+			// Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreTakeRecursive xSemaphoreTakeRecursive
+ * \ingroup Semaphores
+ */
+#if( configUSE_RECURSIVE_MUTEXES == 1 )
+	#define xSemaphoreTakeRecursive( xMutex, xBlockTime )	xQueueTakeMutexRecursive( ( xMutex ), ( xBlockTime ) )
+#endif
+
+/**
+ * semphr. h
+ * <pre>xSemaphoreGive( SemaphoreHandle_t xSemaphore )</pre>
+ *
+ * <i>Macro</i> to release a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary(), xSemaphoreCreateMutex() or
+ * xSemaphoreCreateCounting(). and obtained using sSemaphoreTake().
+ *
+ * This macro must not be used from an ISR.  See xSemaphoreGiveFromISR () for
+ * an alternative which can be used from an ISR.
+ *
+ * This macro must also not be used on semaphores created using
+ * xSemaphoreCreateRecursiveMutex().
+ *
+ * @param xSemaphore A handle to the semaphore being released.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @return pdTRUE if the semaphore was released.  pdFALSE if an error occurred.
+ * Semaphores are implemented using queues.  An error can occur if there is
+ * no space on the queue to post a message - indicating that the
+ * semaphore was not first obtained correctly.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ void vATask( void * pvParameters )
+ {
+    // Create the semaphore to guard a shared resource.
+    xSemaphore = vSemaphoreCreateBinary();
+
+    if( xSemaphore != NULL )
+    {
+        if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+        {
+            // We would expect this call to fail because we cannot give
+            // a semaphore without first "taking" it!
+        }
+
+        // Obtain the semaphore - don't block if the semaphore is not
+        // immediately available.
+        if( xSemaphoreTake( xSemaphore, ( TickType_t ) 0 ) )
+        {
+            // We now have the semaphore and can access the shared resource.
+
+            // ...
+
+            // We have finished accessing the shared resource so can free the
+            // semaphore.
+            if( xSemaphoreGive( xSemaphore ) != pdTRUE )
+            {
+                // We would not expect this call to fail because we must have
+                // obtained the semaphore to get here.
+            }
+        }
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreGive xSemaphoreGive
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGive( xSemaphore )		xQueueGenericSend( ( QueueHandle_t ) ( xSemaphore ), NULL, semGIVE_BLOCK_TIME, queueSEND_TO_BACK )
+
+/**
+ * semphr. h
+ * <pre>xSemaphoreGiveRecursive( SemaphoreHandle_t xMutex )</pre>
+ *
+ * <i>Macro</i> to recursively release, or 'give', a mutex type semaphore.
+ * The mutex must have previously been created using a call to
+ * xSemaphoreCreateRecursiveMutex();
+ *
+ * configUSE_RECURSIVE_MUTEXES must be set to 1 in FreeRTOSConfig.h for this
+ * macro to be available.
+ *
+ * This macro must not be used on mutexes created using xSemaphoreCreateMutex().
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * @param xMutex A handle to the mutex being released, or 'given'.  This is the
+ * handle returned by xSemaphoreCreateMutex();
+ *
+ * @return pdTRUE if the semaphore was given.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xMutex = NULL;
+
+ // A task that creates a mutex.
+ void vATask( void * pvParameters )
+ {
+    // Create the mutex to guard a shared resource.
+    xMutex = xSemaphoreCreateRecursiveMutex();
+ }
+
+ // A task that uses the mutex.
+ void vAnotherTask( void * pvParameters )
+ {
+    // ... Do other things.
+
+    if( xMutex != NULL )
+    {
+        // See if we can obtain the mutex.  If the mutex is not available
+        // wait 10 ticks to see if it becomes free.
+        if( xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 ) == pdTRUE )
+        {
+            // We were able to obtain the mutex and can now access the
+            // shared resource.
+
+            // ...
+            // For some reason due to the nature of the code further calls to
+			// xSemaphoreTakeRecursive() are made on the same mutex.  In real
+			// code these would not be just sequential calls as this would make
+			// no sense.  Instead the calls are likely to be buried inside
+			// a more complex call structure.
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+            xSemaphoreTakeRecursive( xMutex, ( TickType_t ) 10 );
+
+            // The mutex has now been 'taken' three times, so will not be
+			// available to another task until it has also been given back
+			// three times.  Again it is unlikely that real code would have
+			// these calls sequentially, it would be more likely that the calls
+			// to xSemaphoreGiveRecursive() would be called as a call stack
+			// unwound.  This is just for demonstrative purposes.
+            xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+			xSemaphoreGiveRecursive( xMutex );
+
+			// Now the mutex can be taken by other tasks.
+        }
+        else
+        {
+            // We could not obtain the mutex and can therefore not access
+            // the shared resource safely.
+        }
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreGiveRecursive xSemaphoreGiveRecursive
+ * \ingroup Semaphores
+ */
+#if( configUSE_RECURSIVE_MUTEXES == 1 )
+	#define xSemaphoreGiveRecursive( xMutex )	xQueueGiveMutexRecursive( ( xMutex ) )
+#endif
+
+/**
+ * semphr. h
+ * <pre>
+ xSemaphoreGiveFromISR(
+                          SemaphoreHandle_t xSemaphore,
+                          BaseType_t *pxHigherPriorityTaskWoken
+                      )</pre>
+ *
+ * <i>Macro</i> to  release a semaphore.  The semaphore must have previously been
+ * created with a call to xSemaphoreCreateBinary() or xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR.
+ *
+ * @param xSemaphore A handle to the semaphore being released.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if giving the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xSemaphoreGiveFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully given, otherwise errQUEUE_FULL.
+ *
+ * Example usage:
+ <pre>
+ \#define LONG_TIME 0xffff
+ \#define TICKS_TO_WAIT	10
+ SemaphoreHandle_t xSemaphore = NULL;
+
+ // Repetitive task.
+ void vATask( void * pvParameters )
+ {
+    for( ;; )
+    {
+        // We want this task to run every 10 ticks of a timer.  The semaphore
+        // was created before this task was started.
+
+        // Block waiting for the semaphore to become available.
+        if( xSemaphoreTake( xSemaphore, LONG_TIME ) == pdTRUE )
+        {
+            // It is time to execute.
+
+            // ...
+
+            // We have finished our task.  Return to the top of the loop where
+            // we will block on the semaphore until it is time to execute
+            // again.  Note when using the semaphore for synchronisation with an
+			// ISR in this manner there is no need to 'give' the semaphore back.
+        }
+    }
+ }
+
+ // Timer ISR
+ void vTimerISR( void * pvParameters )
+ {
+ static uint8_t ucLocalTickCount = 0;
+ static BaseType_t xHigherPriorityTaskWoken;
+
+    // A timer tick has occurred.
+
+    // ... Do other time functions.
+
+    // Is it time for vATask () to run?
+	xHigherPriorityTaskWoken = pdFALSE;
+    ucLocalTickCount++;
+    if( ucLocalTickCount >= TICKS_TO_WAIT )
+    {
+        // Unblock the task by releasing the semaphore.
+        xSemaphoreGiveFromISR( xSemaphore, &xHigherPriorityTaskWoken );
+
+        // Reset the count so we release the semaphore again in 10 ticks time.
+        ucLocalTickCount = 0;
+    }
+
+    if( xHigherPriorityTaskWoken != pdFALSE )
+    {
+        // We can force a context switch here.  Context switching from an
+        // ISR uses port specific syntax.  Check the demo task for your port
+        // to find the syntax required.
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreGiveFromISR xSemaphoreGiveFromISR
+ * \ingroup Semaphores
+ */
+#define xSemaphoreGiveFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueGiveFromISR( ( QueueHandle_t ) ( xSemaphore ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * <pre>
+ xSemaphoreTakeFromISR(
+                          SemaphoreHandle_t xSemaphore,
+                          BaseType_t *pxHigherPriorityTaskWoken
+                      )</pre>
+ *
+ * <i>Macro</i> to  take a semaphore from an ISR.  The semaphore must have
+ * previously been created with a call to xSemaphoreCreateBinary() or
+ * xSemaphoreCreateCounting().
+ *
+ * Mutex type semaphores (those created using a call to xSemaphoreCreateMutex())
+ * must not be used with this macro.
+ *
+ * This macro can be used from an ISR, however taking a semaphore from an ISR
+ * is not a common operation.  It is likely to only be useful when taking a
+ * counting semaphore when an interrupt is obtaining an object from a resource
+ * pool (when the semaphore count indicates the number of resources available).
+ *
+ * @param xSemaphore A handle to the semaphore being taken.  This is the
+ * handle returned when the semaphore was created.
+ *
+ * @param pxHigherPriorityTaskWoken xSemaphoreTakeFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if taking the semaphore caused a task
+ * to unblock, and the unblocked task has a priority higher than the currently
+ * running task.  If xSemaphoreTakeFromISR() sets this value to pdTRUE then
+ * a context switch should be requested before the interrupt is exited.
+ *
+ * @return pdTRUE if the semaphore was successfully taken, otherwise
+ * pdFALSE
+ */
+#define xSemaphoreTakeFromISR( xSemaphore, pxHigherPriorityTaskWoken )	xQueueReceiveFromISR( ( QueueHandle_t ) ( xSemaphore ), NULL, ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateMutex( void )</pre>
+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored.  If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * semaphore is returned.  If there was not enough heap to allocate the mutex
+ * data structures then NULL is returned.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateMutex xSemaphoreCreateMutex
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateMutex() xQueueCreateMutex( queueQUEUE_TYPE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateMutexStatic( StaticSemaphore_t *pxMutexBuffer )</pre>
+ *
+ * Creates a new mutex type semaphore instance, and returns a handle by which
+ * the new mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, mutex semaphores use a block
+ * of memory, in which the mutex structure is stored.  If a mutex is created
+ * using xSemaphoreCreateMutex() then the required memory is automatically
+ * dynamically allocated inside the xSemaphoreCreateMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a mutex is created using
+ * xSemaphoreCreateMutexStatic() then the application writer must provided the
+ * memory.  xSemaphoreCreateMutexStatic() therefore allows a mutex to be created
+ * without using any dynamic memory allocation.
+ *
+ * Mutexes created using this function can be accessed using the xSemaphoreTake()
+ * and xSemaphoreGive() macros.  The xSemaphoreTakeRecursive() and
+ * xSemaphoreGiveRecursive() macros must not be used.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will be used to hold the mutex's data structure, removing the need for
+ * the memory to be allocated dynamically.
+ *
+ * @return If the mutex was successfully created then a handle to the created
+ * mutex is returned.  If pxMutexBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xMutexBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // A mutex cannot be used before it has been created.  xMutexBuffer is
+    // into xSemaphoreCreateMutexStatic() so no dynamic memory allocation is
+    // attempted.
+    xSemaphore = xSemaphoreCreateMutexStatic( &xMutexBuffer );
+
+    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+    // so there is no need to check it.
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateMutexStatic xSemaphoreCreateMutexStatic
+ * \ingroup Semaphores
+ */
+ #if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateMutexStatic( pxMutexBuffer ) xQueueCreateMutexStatic( queueQUEUE_TYPE_MUTEX, ( pxMutexBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateRecursiveMutex( void )</pre>
+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * of memory, in which the mutex structure is stored.  If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @return xSemaphore Handle to the created mutex semaphore.  Should be of type
+ * SemaphoreHandle_t.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+    // Semaphore cannot be used before a call to xSemaphoreCreateMutex().
+    // This is a macro so pass the variable in directly.
+    xSemaphore = xSemaphoreCreateRecursiveMutex();
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateRecursiveMutex xSemaphoreCreateRecursiveMutex
+ * \ingroup Semaphores
+ */
+#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+	#define xSemaphoreCreateRecursiveMutex() xQueueCreateMutex( queueQUEUE_TYPE_RECURSIVE_MUTEX )
+#endif
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateRecursiveMutexStatic( StaticSemaphore_t *pxMutexBuffer )</pre>
+ *
+ * Creates a new recursive mutex type semaphore instance, and returns a handle
+ * by which the new recursive mutex can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, recursive mutexs use a block
+ * of memory, in which the mutex structure is stored.  If a recursive mutex is
+ * created using xSemaphoreCreateRecursiveMutex() then the required memory is
+ * automatically dynamically allocated inside the
+ * xSemaphoreCreateRecursiveMutex() function.  (see
+ * http://www.freertos.org/a00111.html).  If a recursive mutex is created using
+ * xSemaphoreCreateRecursiveMutexStatic() then the application writer must
+ * provide the memory that will get used by the mutex.
+ * xSemaphoreCreateRecursiveMutexStatic() therefore allows a recursive mutex to
+ * be created without using any dynamic memory allocation.
+ *
+ * Mutexes created using this macro can be accessed using the
+ * xSemaphoreTakeRecursive() and xSemaphoreGiveRecursive() macros.  The
+ * xSemaphoreTake() and xSemaphoreGive() macros must not be used.
+ *
+ * A mutex used recursively can be 'taken' repeatedly by the owner. The mutex
+ * doesn't become available again until the owner has called
+ * xSemaphoreGiveRecursive() for each successful 'take' request.  For example,
+ * if a task successfully 'takes' the same mutex 5 times then the mutex will
+ * not be available to any other task until it has also  'given' the mutex back
+ * exactly five times.
+ *
+ * This type of semaphore uses a priority inheritance mechanism so a task
+ * 'taking' a semaphore MUST ALWAYS 'give' the semaphore back once the
+ * semaphore it is no longer required.
+ *
+ * Mutex type semaphores cannot be used from within interrupt service routines.
+ *
+ * See xSemaphoreCreateBinary() for an alternative implementation that can be
+ * used for pure synchronisation (where one task or interrupt always 'gives' the
+ * semaphore and another always 'takes' the semaphore) and from within interrupt
+ * service routines.
+ *
+ * @param pxMutexBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the recursive mutex's data structure,
+ * removing the need for the memory to be allocated dynamically.
+ *
+ * @return If the recursive mutex was successfully created then a handle to the
+ * created recursive mutex is returned.  If pxMutexBuffer was NULL then NULL is
+ * returned.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xMutexBuffer;
+
+ void vATask( void * pvParameters )
+ {
+    // A recursive semaphore cannot be used before it is created.  Here a
+    // recursive mutex is created using xSemaphoreCreateRecursiveMutexStatic().
+    // The address of xMutexBuffer is passed into the function, and will hold
+    // the mutexes data structures - so no dynamic memory allocation will be
+    // attempted.
+    xSemaphore = xSemaphoreCreateRecursiveMutexStatic( &xMutexBuffer );
+
+    // As no dynamic memory allocation was performed, xSemaphore cannot be NULL,
+    // so there is no need to check it.
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateRecursiveMutexStatic xSemaphoreCreateRecursiveMutexStatic
+ * \ingroup Semaphores
+ */
+#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configUSE_RECURSIVE_MUTEXES == 1 ) )
+	#define xSemaphoreCreateRecursiveMutexStatic( pxStaticSemaphore ) xQueueCreateMutexStatic( queueQUEUE_TYPE_RECURSIVE_MUTEX, pxStaticSemaphore )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateCounting( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount )</pre>
+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored.  If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function.  (see
+ * http://www.freertos.org/a00111.html).  If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer can
+ * instead optionally provide the memory that will get used by the counting
+ * semaphore.  xSemaphoreCreateCountingStatic() therefore allows a counting
+ * semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ *    In this usage scenario an event handler will 'give' a semaphore each time
+ *    an event occurs (incrementing the semaphore count value), and a handler
+ *    task will 'take' a semaphore each time it processes an event
+ *    (decrementing the semaphore count value).  The count value is therefore
+ *    the difference between the number of events that have occurred and the
+ *    number that have been processed.  In this case it is desirable for the
+ *    initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ *    In this usage scenario the count value indicates the number of resources
+ *    available.  To obtain control of a resource a task must first obtain a
+ *    semaphore - decrementing the semaphore count value.  When the count value
+ *    reaches zero there are no free resources.  When a task finishes with the
+ *    resource it 'gives' the semaphore back - incrementing the semaphore count
+ *    value.  In this case it is desirable for the initial count value to be
+ *    equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached.  When the
+ *        semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ *        created.
+ *
+ * @return Handle to the created semaphore.  Null if the semaphore could not be
+ *         created.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+    // Semaphore cannot be used before a call to xSemaphoreCreateCounting().
+    // The max value to which the semaphore can count should be 10, and the
+    // initial value assigned to the count should be 0.
+    xSemaphore = xSemaphoreCreateCounting( 10, 0 );
+
+    if( xSemaphore != NULL )
+    {
+        // The semaphore was created successfully.
+        // The semaphore can now be used.
+    }
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateCounting xSemaphoreCreateCounting
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateCounting( uxMaxCount, uxInitialCount ) xQueueCreateCountingSemaphore( ( uxMaxCount ), ( uxInitialCount ) )
+#endif
+
+/**
+ * semphr. h
+ * <pre>SemaphoreHandle_t xSemaphoreCreateCountingStatic( UBaseType_t uxMaxCount, UBaseType_t uxInitialCount, StaticSemaphore_t *pxSemaphoreBuffer )</pre>
+ *
+ * Creates a new counting semaphore instance, and returns a handle by which the
+ * new counting semaphore can be referenced.
+ *
+ * In many usage scenarios it is faster and more memory efficient to use a
+ * direct to task notification in place of a counting semaphore!
+ * http://www.freertos.org/RTOS-task-notifications.html
+ *
+ * Internally, within the FreeRTOS implementation, counting semaphores use a
+ * block of memory, in which the counting semaphore structure is stored.  If a
+ * counting semaphore is created using xSemaphoreCreateCounting() then the
+ * required memory is automatically dynamically allocated inside the
+ * xSemaphoreCreateCounting() function.  (see
+ * http://www.freertos.org/a00111.html).  If a counting semaphore is created
+ * using xSemaphoreCreateCountingStatic() then the application writer must
+ * provide the memory.  xSemaphoreCreateCountingStatic() therefore allows a
+ * counting semaphore to be created without using any dynamic memory allocation.
+ *
+ * Counting semaphores are typically used for two things:
+ *
+ * 1) Counting events.
+ *
+ *    In this usage scenario an event handler will 'give' a semaphore each time
+ *    an event occurs (incrementing the semaphore count value), and a handler
+ *    task will 'take' a semaphore each time it processes an event
+ *    (decrementing the semaphore count value).  The count value is therefore
+ *    the difference between the number of events that have occurred and the
+ *    number that have been processed.  In this case it is desirable for the
+ *    initial count value to be zero.
+ *
+ * 2) Resource management.
+ *
+ *    In this usage scenario the count value indicates the number of resources
+ *    available.  To obtain control of a resource a task must first obtain a
+ *    semaphore - decrementing the semaphore count value.  When the count value
+ *    reaches zero there are no free resources.  When a task finishes with the
+ *    resource it 'gives' the semaphore back - incrementing the semaphore count
+ *    value.  In this case it is desirable for the initial count value to be
+ *    equal to the maximum count value, indicating that all resources are free.
+ *
+ * @param uxMaxCount The maximum count value that can be reached.  When the
+ *        semaphore reaches this value it can no longer be 'given'.
+ *
+ * @param uxInitialCount The count value assigned to the semaphore when it is
+ *        created.
+ *
+ * @param pxSemaphoreBuffer Must point to a variable of type StaticSemaphore_t,
+ * which will then be used to hold the semaphore's data structure, removing the
+ * need for the memory to be allocated dynamically.
+ *
+ * @return If the counting semaphore was successfully created then a handle to
+ * the created counting semaphore is returned.  If pxSemaphoreBuffer was NULL
+ * then NULL is returned.
+ *
+ * Example usage:
+ <pre>
+ SemaphoreHandle_t xSemaphore;
+ StaticSemaphore_t xSemaphoreBuffer;
+
+ void vATask( void * pvParameters )
+ {
+ SemaphoreHandle_t xSemaphore = NULL;
+
+    // Counting semaphore cannot be used before they have been created.  Create
+    // a counting semaphore using xSemaphoreCreateCountingStatic().  The max
+    // value to which the semaphore can count is 10, and the initial value
+    // assigned to the count will be 0.  The address of xSemaphoreBuffer is
+    // passed in and will be used to hold the semaphore structure, so no dynamic
+    // memory allocation will be used.
+    xSemaphore = xSemaphoreCreateCounting( 10, 0, &xSemaphoreBuffer );
+
+    // No memory allocation was attempted so xSemaphore cannot be NULL, so there
+    // is no need to check its value.
+ }
+ </pre>
+ * \defgroup xSemaphoreCreateCountingStatic xSemaphoreCreateCountingStatic
+ * \ingroup Semaphores
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	#define xSemaphoreCreateCountingStatic( uxMaxCount, uxInitialCount, pxSemaphoreBuffer ) xQueueCreateCountingSemaphoreStatic( ( uxMaxCount ), ( uxInitialCount ), ( pxSemaphoreBuffer ) )
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * semphr. h
+ * <pre>void vSemaphoreDelete( SemaphoreHandle_t xSemaphore );</pre>
+ *
+ * Delete a semaphore.  This function must be used with care.  For example,
+ * do not delete a mutex type semaphore if the mutex is held by a task.
+ *
+ * @param xSemaphore A handle to the semaphore to be deleted.
+ *
+ * \defgroup vSemaphoreDelete vSemaphoreDelete
+ * \ingroup Semaphores
+ */
+#define vSemaphoreDelete( xSemaphore ) vQueueDelete( ( QueueHandle_t ) ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * <pre>TaskHandle_t xSemaphoreGetMutexHolder( SemaphoreHandle_t xMutex );</pre>
+ *
+ * If xMutex is indeed a mutex type semaphore, return the current mutex holder.
+ * If xMutex is not a mutex type semaphore, or the mutex is available (not held
+ * by a task), return NULL.
+ *
+ * Note: This is a good way of determining if the calling task is the mutex
+ * holder, but not a good way of determining the identity of the mutex holder as
+ * the holder may change between the function exiting and the returned value
+ * being tested.
+ */
+#define xSemaphoreGetMutexHolder( xSemaphore ) xQueueGetMutexHolder( ( xSemaphore ) )
+
+/**
+ * semphr.h
+ * <pre>UBaseType_t uxSemaphoreGetCount( SemaphoreHandle_t xSemaphore );</pre>
+ *
+ * If the semaphore is a counting semaphore then uxSemaphoreGetCount() returns
+ * its current count value.  If the semaphore is a binary semaphore then
+ * uxSemaphoreGetCount() returns 1 if the semaphore is available, and 0 if the
+ * semaphore is not available.
+ *
+ */
+#define uxSemaphoreGetCount( xSemaphore ) uxQueueMessagesWaiting( ( QueueHandle_t ) ( xSemaphore ) )
+
+#endif /* SEMAPHORE_H */
+
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/stdint.readme b/STM32F1/libraries/FreeRTOS900/utility/stdint.readme
new file mode 100644
index 000000000..4414c29ed
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/stdint.readme
@@ -0,0 +1,27 @@
+
+#ifndef FREERTOS_STDINT
+#define FREERTOS_STDINT
+
+/*******************************************************************************
+ * THIS IS NOT A FULL stdint.h IMPLEMENTATION - It only contains the definitions
+ * necessary to build the FreeRTOS code.  It is provided to allow FreeRTOS to be
+ * built using compilers that do not provide their own stdint.h definition.
+ *
+ * To use this file:
+ *
+ *    1) Copy this file into the directory that contains your FreeRTOSConfig.h
+ *       header file, as that directory will already be in the compilers include
+ *       path.
+ *
+ *    2) Rename the copied file stdint.h.
+ *
+ */
+
+typedef signed char int8_t;
+typedef unsigned char uint8_t;
+typedef short int16_t;
+typedef unsigned short uint16_t;
+typedef long int32_t;
+typedef unsigned long uint32_t;
+
+#endif /* FREERTOS_STDINT */
diff --git a/STM32F1/libraries/FreeRTOS900/utility/task.h b/STM32F1/libraries/FreeRTOS900/utility/task.h
new file mode 100644
index 000000000..d0643c09e
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/task.h
@@ -0,0 +1,2267 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+
+#ifndef INC_TASK_H
+#define INC_TASK_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include task.h"
+#endif
+
+#include "list.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+#define tskKERNEL_VERSION_NUMBER "V9.0.0"
+#define tskKERNEL_VERSION_MAJOR 9
+#define tskKERNEL_VERSION_MINOR 0
+#define tskKERNEL_VERSION_BUILD 0
+
+/**
+ * task. h
+ *
+ * Type by which tasks are referenced.  For example, a call to xTaskCreate
+ * returns (via a pointer parameter) an TaskHandle_t variable that can then
+ * be used as a parameter to vTaskDelete to delete the task.
+ *
+ * \defgroup TaskHandle_t TaskHandle_t
+ * \ingroup Tasks
+ */
+typedef void * TaskHandle_t;
+
+/*
+ * Defines the prototype to which the application task hook function must
+ * conform.
+ */
+typedef BaseType_t (*TaskHookFunction_t)( void * );
+
+/* Task states returned by eTaskGetState. */
+typedef enum
+{
+	eRunning = 0,	/* A task is querying the state of itself, so must be running. */
+	eReady,			/* The task being queried is in a read or pending ready list. */
+	eBlocked,		/* The task being queried is in the Blocked state. */
+	eSuspended,		/* The task being queried is in the Suspended state, or is in the Blocked state with an infinite time out. */
+	eDeleted,		/* The task being queried has been deleted, but its TCB has not yet been freed. */
+	eInvalid			/* Used as an 'invalid state' value. */
+} eTaskState;
+
+/* Actions that can be performed when vTaskNotify() is called. */
+typedef enum
+{
+	eNoAction = 0,				/* Notify the task without updating its notify value. */
+	eSetBits,					/* Set bits in the task's notification value. */
+	eIncrement,					/* Increment the task's notification value. */
+	eSetValueWithOverwrite,		/* Set the task's notification value to a specific value even if the previous value has not yet been read by the task. */
+	eSetValueWithoutOverwrite	/* Set the task's notification value if the previous value has been read by the task. */
+} eNotifyAction;
+
+/*
+ * Used internally only.
+ */
+typedef struct xTIME_OUT
+{
+	BaseType_t xOverflowCount;
+	TickType_t xTimeOnEntering;
+} TimeOut_t;
+
+/*
+ * Defines the memory ranges allocated to the task when an MPU is used.
+ */
+typedef struct xMEMORY_REGION
+{
+	void *pvBaseAddress;
+	uint32_t ulLengthInBytes;
+	uint32_t ulParameters;
+} MemoryRegion_t;
+
+/*
+ * Parameters required to create an MPU protected task.
+ */
+typedef struct xTASK_PARAMETERS
+{
+	TaskFunction_t pvTaskCode;
+	const char * const pcName;	/*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	uint16_t usStackDepth;
+	void *pvParameters;
+	UBaseType_t uxPriority;
+	StackType_t *puxStackBuffer;
+	MemoryRegion_t xRegions[ portNUM_CONFIGURABLE_REGIONS ];
+} TaskParameters_t;
+
+/* Used with the uxTaskGetSystemState() function to return the state of each task
+in the system. */
+typedef struct xTASK_STATUS
+{
+	TaskHandle_t xHandle;			/* The handle of the task to which the rest of the information in the structure relates. */
+	const char *pcTaskName;			/* A pointer to the task's name.  This value will be invalid if the task was deleted since the structure was populated! */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	UBaseType_t xTaskNumber;		/* A number unique to the task. */
+	eTaskState eCurrentState;		/* The state in which the task existed when the structure was populated. */
+	UBaseType_t uxCurrentPriority;	/* The priority at which the task was running (may be inherited) when the structure was populated. */
+	UBaseType_t uxBasePriority;		/* The priority to which the task will return if the task's current priority has been inherited to avoid unbounded priority inversion when obtaining a mutex.  Only valid if configUSE_MUTEXES is defined as 1 in FreeRTOSConfig.h. */
+	uint32_t ulRunTimeCounter;		/* The total run time allocated to the task so far, as defined by the run time stats clock.  See http://www.freertos.org/rtos-run-time-stats.html.  Only valid when configGENERATE_RUN_TIME_STATS is defined as 1 in FreeRTOSConfig.h. */
+	StackType_t *pxStackBase;		/* Points to the lowest address of the task's stack area. */
+	uint16_t usStackHighWaterMark;	/* The minimum amount of stack space that has remained for the task since the task was created.  The closer this value is to zero the closer the task has come to overflowing its stack. */
+} TaskStatus_t;
+
+/* Possible return values for eTaskConfirmSleepModeStatus(). */
+typedef enum
+{
+	eAbortSleep = 0,		/* A task has been made ready or a context switch pended since portSUPPORESS_TICKS_AND_SLEEP() was called - abort entering a sleep mode. */
+	eStandardSleep,			/* Enter a sleep mode that will not last any longer than the expected idle time. */
+	eNoTasksWaitingTimeout	/* No tasks are waiting for a timeout so it is safe to enter a sleep mode that can only be exited by an external interrupt. */
+} eSleepModeStatus;
+
+/**
+ * Defines the priority used by the idle task.  This must not be modified.
+ *
+ * \ingroup TaskUtils
+ */
+#define tskIDLE_PRIORITY			( ( UBaseType_t ) 0U )
+
+/**
+ * task. h
+ *
+ * Macro for forcing a context switch.
+ *
+ * \defgroup taskYIELD taskYIELD
+ * \ingroup SchedulerControl
+ */
+#define taskYIELD()					portYIELD()
+
+/**
+ * task. h
+ *
+ * Macro to mark the start of a critical code region.  Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskENTER_CRITICAL taskENTER_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskENTER_CRITICAL()		portENTER_CRITICAL()
+#define taskENTER_CRITICAL_FROM_ISR() portSET_INTERRUPT_MASK_FROM_ISR()
+
+/**
+ * task. h
+ *
+ * Macro to mark the end of a critical code region.  Preemptive context
+ * switches cannot occur when in a critical region.
+ *
+ * NOTE: This may alter the stack (depending on the portable implementation)
+ * so must be used with care!
+ *
+ * \defgroup taskEXIT_CRITICAL taskEXIT_CRITICAL
+ * \ingroup SchedulerControl
+ */
+#define taskEXIT_CRITICAL()			portEXIT_CRITICAL()
+#define taskEXIT_CRITICAL_FROM_ISR( x ) portCLEAR_INTERRUPT_MASK_FROM_ISR( x )
+/**
+ * task. h
+ *
+ * Macro to disable all maskable interrupts.
+ *
+ * \defgroup taskDISABLE_INTERRUPTS taskDISABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskDISABLE_INTERRUPTS()	portDISABLE_INTERRUPTS()
+
+/**
+ * task. h
+ *
+ * Macro to enable microcontroller interrupts.
+ *
+ * \defgroup taskENABLE_INTERRUPTS taskENABLE_INTERRUPTS
+ * \ingroup SchedulerControl
+ */
+#define taskENABLE_INTERRUPTS()		portENABLE_INTERRUPTS()
+
+/* Definitions returned by xTaskGetSchedulerState().  taskSCHEDULER_SUSPENDED is
+0 to generate more optimal code when configASSERT() is defined as the constant
+is used in assert() statements. */
+#define taskSCHEDULER_SUSPENDED		( ( BaseType_t ) 0 )
+#define taskSCHEDULER_NOT_STARTED	( ( BaseType_t ) 1 )
+#define taskSCHEDULER_RUNNING		( ( BaseType_t ) 2 )
+
+
+/*-----------------------------------------------------------
+ * TASK CREATION API
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ *<pre>
+ BaseType_t xTaskCreate(
+							  TaskFunction_t pvTaskCode,
+							  const char * const pcName,
+							  uint16_t usStackDepth,
+							  void *pvParameters,
+							  UBaseType_t uxPriority,
+							  TaskHandle_t *pvCreatedTask
+						  );</pre>
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory.  xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * See xTaskCreateStatic() for a version that does not use any dynamic memory
+ * allocation.
+ *
+ * xTaskCreate() can only be used to create a task that has unrestricted
+ * access to the entire microcontroller memory map.  Systems that include MPU
+ * support can alternatively create an MPU constrained task using
+ * xTaskCreateRestricted().
+ *
+ * @param pvTaskCode Pointer to the task entry function.  Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task.  This is mainly used to
+ * facilitate debugging.  Max length defined by configMAX_TASK_NAME_LEN - default
+ * is 16.
+ *
+ * @param usStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes.  For example, if
+ * the stack is 16 bits wide and usStackDepth is defined as 100, 200 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task should run.  Systems that
+ * include MPU support can optionally create tasks in a privileged (system)
+ * mode by setting bit portPRIVILEGE_BIT of the priority parameter.  For
+ * example, to create a privileged task at priority 2 the uxPriority parameter
+ * should be set to ( 2 | portPRIVILEGE_BIT ).
+ *
+ * @param pvCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   <pre>
+ // Task to be created.
+ void vTaskCode( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+	 }
+ }
+
+ // Function that creates a task.
+ void vOtherFunction( void )
+ {
+ static uint8_t ucParameterToPass;
+ TaskHandle_t xHandle = NULL;
+
+	 // Create the task, storing the handle.  Note that the passed parameter ucParameterToPass
+	 // must exist for the lifetime of the task, so in this case is declared static.  If it was just an
+	 // an automatic stack variable it might no longer exist, or at least have been corrupted, by the time
+	 // the new task attempts to access it.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, &ucParameterToPass, tskIDLE_PRIORITY, &xHandle );
+     configASSERT( xHandle );
+
+	 // Use the handle to delete the task.
+     if( xHandle != NULL )
+     {
+	     vTaskDelete( xHandle );
+     }
+ }
+   </pre>
+ * \defgroup xTaskCreate xTaskCreate
+ * \ingroup Tasks
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
+							const char * const pcName,
+							const uint16_t usStackDepth,
+							void * const pvParameters,
+							UBaseType_t uxPriority,
+							TaskHandle_t * const pxCreatedTask ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/**
+ * task. h
+ *<pre>
+ TaskHandle_t xTaskCreateStatic( TaskFunction_t pvTaskCode,
+								 const char * const pcName,
+								 uint32_t ulStackDepth,
+								 void *pvParameters,
+								 UBaseType_t uxPriority,
+								 StackType_t *pxStackBuffer,
+								 StaticTask_t *pxTaskBuffer );</pre>
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ *
+ * Internally, within the FreeRTOS implementation, tasks use two blocks of
+ * memory.  The first block is used to hold the task's data structures.  The
+ * second block is used by the task as its stack.  If a task is created using
+ * xTaskCreate() then both blocks of memory are automatically dynamically
+ * allocated inside the xTaskCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a task is created using
+ * xTaskCreateStatic() then the application writer must provide the required
+ * memory.  xTaskCreateStatic() therefore allows a task to be created without
+ * using any dynamic memory allocation.
+ *
+ * @param pvTaskCode Pointer to the task entry function.  Tasks
+ * must be implemented to never return (i.e. continuous loop).
+ *
+ * @param pcName A descriptive name for the task.  This is mainly used to
+ * facilitate debugging.  The maximum length of the string is defined by
+ * configMAX_TASK_NAME_LEN in FreeRTOSConfig.h.
+ *
+ * @param ulStackDepth The size of the task stack specified as the number of
+ * variables the stack can hold - not the number of bytes.  For example, if
+ * the stack is 32-bits wide and ulStackDepth is defined as 100 then 400 bytes
+ * will be allocated for stack storage.
+ *
+ * @param pvParameters Pointer that will be used as the parameter for the task
+ * being created.
+ *
+ * @param uxPriority The priority at which the task will run.
+ *
+ * @param pxStackBuffer Must point to a StackType_t array that has at least
+ * ulStackDepth indexes - the array will then be used as the task's stack,
+ * removing the need for the stack to be allocated dynamically.
+ *
+ * @param pxTaskBuffer Must point to a variable of type StaticTask_t, which will
+ * then be used to hold the task's data structures, removing the need for the
+ * memory to be allocated dynamically.
+ *
+ * @return If neither pxStackBuffer or pxTaskBuffer are NULL, then the task will
+ * be created and pdPASS is returned.  If either pxStackBuffer or pxTaskBuffer
+ * are NULL then the task will not be created and
+ * errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY is returned.
+ *
+ * Example usage:
+   <pre>
+
+    // Dimensions the buffer that the task being created will use as its stack.
+    // NOTE:  This is the number of words the stack will hold, not the number of
+    // bytes.  For example, if each stack item is 32-bits, and this is set to 100,
+    // then 400 bytes (100 * 32-bits) will be allocated.
+    #define STACK_SIZE 200
+
+    // Structure that will hold the TCB of the task being created.
+    StaticTask_t xTaskBuffer;
+
+    // Buffer that the task being created will use as its stack.  Note this is
+    // an array of StackType_t variables.  The size of StackType_t is dependent on
+    // the RTOS port.
+    StackType_t xStack[ STACK_SIZE ];
+
+    // Function that implements the task being created.
+    void vTaskCode( void * pvParameters )
+    {
+        // The parameter value is expected to be 1 as 1 is passed in the
+        // pvParameters value in the call to xTaskCreateStatic().
+        configASSERT( ( uint32_t ) pvParameters == 1UL );
+
+        for( ;; )
+        {
+            // Task code goes here.
+        }
+    }
+
+    // Function that creates a task.
+    void vOtherFunction( void )
+    {
+        TaskHandle_t xHandle = NULL;
+
+        // Create the task without using any dynamic memory allocation.
+        xHandle = xTaskCreateStatic(
+                      vTaskCode,       // Function that implements the task.
+                      "NAME",          // Text name for the task.
+                      STACK_SIZE,      // Stack size in words, not bytes.
+                      ( void * ) 1,    // Parameter passed into the task.
+                      tskIDLE_PRIORITY,// Priority at which the task is created.
+                      xStack,          // Array to use as the task's stack.
+                      &xTaskBuffer );  // Variable to hold the task's data structure.
+
+        // puxStackBuffer and pxTaskBuffer were not NULL, so the task will have
+        // been created, and xHandle will be the task's handle.  Use the handle
+        // to suspend the task.
+        vTaskSuspend( xHandle );
+    }
+   </pre>
+ * \defgroup xTaskCreateStatic xTaskCreateStatic
+ * \ingroup Tasks
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
+									const char * const pcName,
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									StackType_t * const puxStackBuffer,
+									StaticTask_t * const pxTaskBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * task. h
+ *<pre>
+ BaseType_t xTaskCreateRestricted( TaskParameters_t *pxTaskDefinition, TaskHandle_t *pxCreatedTask );</pre>
+ *
+ * xTaskCreateRestricted() should only be used in systems that include an MPU
+ * implementation.
+ *
+ * Create a new task and add it to the list of tasks that are ready to run.
+ * The function parameters define the memory regions and associated access
+ * permissions allocated to the task.
+ *
+ * @param pxTaskDefinition Pointer to a structure that contains a member
+ * for each of the normal xTaskCreate() parameters (see the xTaskCreate() API
+ * documentation) plus an optional stack buffer and the memory region
+ * definitions.
+ *
+ * @param pxCreatedTask Used to pass back a handle by which the created task
+ * can be referenced.
+ *
+ * @return pdPASS if the task was successfully created and added to a ready
+ * list, otherwise an error code defined in the file projdefs.h
+ *
+ * Example usage:
+   <pre>
+// Create an TaskParameters_t structure that defines the task to be created.
+static const TaskParameters_t xCheckTaskParameters =
+{
+	vATask,		// pvTaskCode - the function that implements the task.
+	"ATask",	// pcName - just a text name for the task to assist debugging.
+	100,		// usStackDepth	- the stack size DEFINED IN WORDS.
+	NULL,		// pvParameters - passed into the task function as the function parameters.
+	( 1UL | portPRIVILEGE_BIT ),// uxPriority - task priority, set the portPRIVILEGE_BIT if the task should run in a privileged state.
+	cStackBuffer,// puxStackBuffer - the buffer to be used as the task stack.
+
+	// xRegions - Allocate up to three separate memory regions for access by
+	// the task, with appropriate access permissions.  Different processors have
+	// different memory alignment requirements - refer to the FreeRTOS documentation
+	// for full information.
+	{
+		// Base address					Length	Parameters
+        { cReadWriteArray,				32,		portMPU_REGION_READ_WRITE },
+        { cReadOnlyArray,				32,		portMPU_REGION_READ_ONLY },
+        { cPrivilegedOnlyAccessArray,	128,	portMPU_REGION_PRIVILEGED_READ_WRITE }
+	}
+};
+
+int main( void )
+{
+TaskHandle_t xHandle;
+
+	// Create a task from the const structure defined above.  The task handle
+	// is requested (the second parameter is not NULL) but in this case just for
+	// demonstration purposes as its not actually used.
+	xTaskCreateRestricted( &xRegTest1Parameters, &xHandle );
+
+	// Start the scheduler.
+	vTaskStartScheduler();
+
+	// Will only get here if there was insufficient memory to create the idle
+	// and/or timer task.
+	for( ;; );
+}
+   </pre>
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+#if( portUSING_MPU_WRAPPERS == 1 )
+	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask ) PRIVILEGED_FUNCTION;
+#endif
+
+/**
+ * task. h
+ *<pre>
+ void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions );</pre>
+ *
+ * Memory regions are assigned to a restricted task when the task is created by
+ * a call to xTaskCreateRestricted().  These regions can be redefined using
+ * vTaskAllocateMPURegions().
+ *
+ * @param xTask The handle of the task being updated.
+ *
+ * @param xRegions A pointer to an MemoryRegion_t structure that contains the
+ * new memory region definitions.
+ *
+ * Example usage:
+   <pre>
+// Define an array of MemoryRegion_t structures that configures an MPU region
+// allowing read/write access for 1024 bytes starting at the beginning of the
+// ucOneKByte array.  The other two of the maximum 3 definable regions are
+// unused so set to zero.
+static const MemoryRegion_t xAltRegions[ portNUM_CONFIGURABLE_REGIONS ] =
+{
+	// Base address		Length		Parameters
+	{ ucOneKByte,		1024,		portMPU_REGION_READ_WRITE },
+	{ 0,				0,			0 },
+	{ 0,				0,			0 }
+};
+
+void vATask( void *pvParameters )
+{
+	// This task was created such that it has access to certain regions of
+	// memory as defined by the MPU configuration.  At some point it is
+	// desired that these MPU regions are replaced with that defined in the
+	// xAltRegions const struct above.  Use a call to vTaskAllocateMPURegions()
+	// for this purpose.  NULL is used as the task handle to indicate that this
+	// function should modify the MPU regions of the calling task.
+	vTaskAllocateMPURegions( NULL, xAltRegions );
+
+	// Now the task can continue its function, but from this point on can only
+	// access its stack and the ucOneKByte array (unless any other statically
+	// defined or shared regions have been declared elsewhere).
+}
+   </pre>
+ * \defgroup xTaskCreateRestricted xTaskCreateRestricted
+ * \ingroup Tasks
+ */
+void vTaskAllocateMPURegions( TaskHandle_t xTask, const MemoryRegion_t * const pxRegions ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskDelete( TaskHandle_t xTask );</pre>
+ *
+ * INCLUDE_vTaskDelete must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Remove a task from the RTOS real time kernel's management.  The task being
+ * deleted will be removed from all ready, blocked, suspended and event lists.
+ *
+ * NOTE:  The idle task is responsible for freeing the kernel allocated
+ * memory from tasks that have been deleted.  It is therefore important that
+ * the idle task is not starved of microcontroller processing time if your
+ * application makes any calls to vTaskDelete ().  Memory allocated by the
+ * task code is not automatically freed, and should be freed before the task
+ * is deleted.
+ *
+ * See the demo application file death.c for sample code that utilises
+ * vTaskDelete ().
+ *
+ * @param xTask The handle of the task to be deleted.  Passing NULL will
+ * cause the calling task to be deleted.
+ *
+ * Example usage:
+   <pre>
+ void vOtherFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create the task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // Use the handle to delete the task.
+	 vTaskDelete( xHandle );
+ }
+   </pre>
+ * \defgroup vTaskDelete vTaskDelete
+ * \ingroup Tasks
+ */
+void vTaskDelete( TaskHandle_t xTaskToDelete ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * TASK CONTROL API
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * <pre>void vTaskDelay( const TickType_t xTicksToDelay );</pre>
+ *
+ * Delay a task for a given number of ticks.  The actual time that the
+ * task remains blocked depends on the tick rate.  The constant
+ * portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * INCLUDE_vTaskDelay must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ *
+ * vTaskDelay() specifies a time at which the task wishes to unblock relative to
+ * the time at which vTaskDelay() is called.  For example, specifying a block
+ * period of 100 ticks will cause the task to unblock 100 ticks after
+ * vTaskDelay() is called.  vTaskDelay() does not therefore provide a good method
+ * of controlling the frequency of a periodic task as the path taken through the
+ * code, as well as other task and interrupt activity, will effect the frequency
+ * at which vTaskDelay() gets called and therefore the time at which the task
+ * next executes.  See vTaskDelayUntil() for an alternative API function designed
+ * to facilitate fixed frequency execution.  It does this by specifying an
+ * absolute time (rather than a relative time) at which the calling task should
+ * unblock.
+ *
+ * @param xTicksToDelay The amount of time, in tick periods, that
+ * the calling task should block.
+ *
+ * Example usage:
+
+ void vTaskFunction( void * pvParameters )
+ {
+ // Block for 500ms.
+ const TickType_t xDelay = 500 / portTICK_PERIOD_MS;
+
+	 for( ;; )
+	 {
+		 // Simply toggle the LED every 500ms, blocking between each toggle.
+		 vToggleLED();
+		 vTaskDelay( xDelay );
+	 }
+ }
+
+ * \defgroup vTaskDelay vTaskDelay
+ * \ingroup TaskCtrl
+ */
+void vTaskDelay( const TickType_t xTicksToDelay ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskDelayUntil( TickType_t *pxPreviousWakeTime, const TickType_t xTimeIncrement );</pre>
+ *
+ * INCLUDE_vTaskDelayUntil must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Delay a task until a specified time.  This function can be used by periodic
+ * tasks to ensure a constant execution frequency.
+ *
+ * This function differs from vTaskDelay () in one important aspect:  vTaskDelay () will
+ * cause a task to block for the specified number of ticks from the time vTaskDelay () is
+ * called.  It is therefore difficult to use vTaskDelay () by itself to generate a fixed
+ * execution frequency as the time between a task starting to execute and that task
+ * calling vTaskDelay () may not be fixed [the task may take a different path though the
+ * code between calls, or may get interrupted or preempted a different number of times
+ * each time it executes].
+ *
+ * Whereas vTaskDelay () specifies a wake time relative to the time at which the function
+ * is called, vTaskDelayUntil () specifies the absolute (exact) time at which it wishes to
+ * unblock.
+ *
+ * The constant portTICK_PERIOD_MS can be used to calculate real time from the tick
+ * rate - with the resolution of one tick period.
+ *
+ * @param pxPreviousWakeTime Pointer to a variable that holds the time at which the
+ * task was last unblocked.  The variable must be initialised with the current time
+ * prior to its first use (see the example below).  Following this the variable is
+ * automatically updated within vTaskDelayUntil ().
+ *
+ * @param xTimeIncrement The cycle time period.  The task will be unblocked at
+ * time *pxPreviousWakeTime + xTimeIncrement.  Calling vTaskDelayUntil with the
+ * same xTimeIncrement parameter value will cause the task to execute with
+ * a fixed interface period.
+ *
+ * Example usage:
+   <pre>
+ // Perform an action every 10 ticks.
+ void vTaskFunction( void * pvParameters )
+ {
+ TickType_t xLastWakeTime;
+ const TickType_t xFrequency = 10;
+
+	 // Initialise the xLastWakeTime variable with the current time.
+	 xLastWakeTime = xTaskGetTickCount ();
+	 for( ;; )
+	 {
+		 // Wait for the next cycle.
+		 vTaskDelayUntil( &xLastWakeTime, xFrequency );
+
+		 // Perform action here.
+	 }
+ }
+   </pre>
+ * \defgroup vTaskDelayUntil vTaskDelayUntil
+ * \ingroup TaskCtrl
+ */
+void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>BaseType_t xTaskAbortDelay( TaskHandle_t xTask );</pre>
+ *
+ * INCLUDE_xTaskAbortDelay must be defined as 1 in FreeRTOSConfig.h for this
+ * function to be available.
+ *
+ * A task will enter the Blocked state when it is waiting for an event.  The
+ * event it is waiting for can be a temporal event (waiting for a time), such
+ * as when vTaskDelay() is called, or an event on an object, such as when
+ * xQueueReceive() or ulTaskNotifyTake() is called.  If the handle of a task
+ * that is in the Blocked state is used in a call to xTaskAbortDelay() then the
+ * task will leave the Blocked state, and return from whichever function call
+ * placed the task into the Blocked state.
+ *
+ * @param xTask The handle of the task to remove from the Blocked state.
+ *
+ * @return If the task referenced by xTask was not in the Blocked state then
+ * pdFAIL is returned.  Otherwise pdPASS is returned.
+ *
+ * \defgroup xTaskAbortDelay xTaskAbortDelay
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskAbortDelay( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask );</pre>
+ *
+ * INCLUDE_uxTaskPriorityGet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the priority of any task.
+ *
+ * @param xTask Handle of the task to be queried.  Passing a NULL
+ * handle results in the priority of the calling task being returned.
+ *
+ * @return The priority of xTask.
+ *
+ * Example usage:
+   <pre>
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to obtain the priority of the created task.
+	 // It was created with tskIDLE_PRIORITY, but may have changed
+	 // it itself.
+	 if( uxTaskPriorityGet( xHandle ) != tskIDLE_PRIORITY )
+	 {
+		 // The task has changed it's priority.
+	 }
+
+	 // ...
+
+	 // Is our priority higher than the created task?
+	 if( uxTaskPriorityGet( xHandle ) < uxTaskPriorityGet( NULL ) )
+	 {
+		 // Our priority (obtained using NULL handle) is higher.
+	 }
+ }
+   </pre>
+ * \defgroup uxTaskPriorityGet uxTaskPriorityGet
+ * \ingroup TaskCtrl
+ */
+UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask );</pre>
+ *
+ * A version of uxTaskPriorityGet() that can be used from an ISR.
+ */
+UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>eTaskState eTaskGetState( TaskHandle_t xTask );</pre>
+ *
+ * INCLUDE_eTaskGetState must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Obtain the state of any task.  States are encoded by the eTaskState
+ * enumerated type.
+ *
+ * @param xTask Handle of the task to be queried.
+ *
+ * @return The state of xTask at the time the function was called.  Note the
+ * state of the task might change between the function being called, and the
+ * functions return value being tested by the calling task.
+ */
+eTaskState eTaskGetState( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState );</pre>
+ *
+ * configUSE_TRACE_FACILITY must be defined as 1 for this function to be
+ * available.  See the configuration section for more information.
+ *
+ * Populates a TaskStatus_t structure with information about a task.
+ *
+ * @param xTask Handle of the task being queried.  If xTask is NULL then
+ * information will be returned about the calling task.
+ *
+ * @param pxTaskStatus A pointer to the TaskStatus_t structure that will be
+ * filled with information about the task referenced by the handle passed using
+ * the xTask parameter.
+ *
+ * @xGetFreeStackSpace The TaskStatus_t structure contains a member to report
+ * the stack high water mark of the task being queried.  Calculating the stack
+ * high water mark takes a relatively long time, and can make the system
+ * temporarily unresponsive - so the xGetFreeStackSpace parameter is provided to
+ * allow the high water mark checking to be skipped.  The high watermark value
+ * will only be written to the TaskStatus_t structure if xGetFreeStackSpace is
+ * not set to pdFALSE;
+ *
+ * @param eState The TaskStatus_t structure contains a member to report the
+ * state of the task being queried.  Obtaining the task state is not as fast as
+ * a simple assignment - so the eState parameter is provided to allow the state
+ * information to be omitted from the TaskStatus_t structure.  To obtain state
+ * information then set eState to eInvalid - otherwise the value passed in
+ * eState will be reported as the task state in the TaskStatus_t structure.
+ *
+ * Example usage:
+   <pre>
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+ TaskStatus_t xTaskDetails;
+
+    // Obtain the handle of a task from its name.
+    xHandle = xTaskGetHandle( "Task_Name" );
+
+    // Check the handle is not NULL.
+    configASSERT( xHandle );
+
+    // Use the handle to obtain further information about the task.
+    vTaskGetInfo( xHandle,
+                  &xTaskDetails,
+                  pdTRUE, // Include the high water mark in xTaskDetails.
+                  eInvalid ); // Include the task state in xTaskDetails.
+ }
+   </pre>
+ * \defgroup vTaskGetInfo vTaskGetInfo
+ * \ingroup TaskCtrl
+ */
+void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority );</pre>
+ *
+ * INCLUDE_vTaskPrioritySet must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Set the priority of any task.
+ *
+ * A context switch will occur before the function returns if the priority
+ * being set is higher than the currently executing task.
+ *
+ * @param xTask Handle to the task for which the priority is being set.
+ * Passing a NULL handle results in the priority of the calling task being set.
+ *
+ * @param uxNewPriority The priority to which the task will be set.
+ *
+ * Example usage:
+   <pre>
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to raise the priority of the created task.
+	 vTaskPrioritySet( xHandle, tskIDLE_PRIORITY + 1 );
+
+	 // ...
+
+	 // Use a NULL handle to raise our priority to the same value.
+	 vTaskPrioritySet( NULL, tskIDLE_PRIORITY + 1 );
+ }
+   </pre>
+ * \defgroup vTaskPrioritySet vTaskPrioritySet
+ * \ingroup TaskCtrl
+ */
+void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskSuspend( TaskHandle_t xTaskToSuspend );</pre>
+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Suspend any task.  When suspended a task will never get any microcontroller
+ * processing time, no matter what its priority.
+ *
+ * Calls to vTaskSuspend are not accumulative -
+ * i.e. calling vTaskSuspend () twice on the same task still only requires one
+ * call to vTaskResume () to ready the suspended task.
+ *
+ * @param xTaskToSuspend Handle to the task being suspended.  Passing a NULL
+ * handle will cause the calling task to be suspended.
+ *
+ * Example usage:
+   <pre>
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to suspend the created task.
+	 vTaskSuspend( xHandle );
+
+	 // ...
+
+	 // The created task will not run during this period, unless
+	 // another task calls vTaskResume( xHandle ).
+
+	 //...
+
+
+	 // Suspend ourselves.
+	 vTaskSuspend( NULL );
+
+	 // We cannot get here unless another task calls vTaskResume
+	 // with our handle as the parameter.
+ }
+   </pre>
+ * \defgroup vTaskSuspend vTaskSuspend
+ * \ingroup TaskCtrl
+ */
+void vTaskSuspend( TaskHandle_t xTaskToSuspend ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskResume( TaskHandle_t xTaskToResume );</pre>
+ *
+ * INCLUDE_vTaskSuspend must be defined as 1 for this function to be available.
+ * See the configuration section for more information.
+ *
+ * Resumes a suspended task.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * vTaskResume ().
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * Example usage:
+   <pre>
+ void vAFunction( void )
+ {
+ TaskHandle_t xHandle;
+
+	 // Create a task, storing the handle.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, &xHandle );
+
+	 // ...
+
+	 // Use the handle to suspend the created task.
+	 vTaskSuspend( xHandle );
+
+	 // ...
+
+	 // The created task will not run during this period, unless
+	 // another task calls vTaskResume( xHandle ).
+
+	 //...
+
+
+	 // Resume the suspended task ourselves.
+	 vTaskResume( xHandle );
+
+	 // The created task will once again get microcontroller processing
+	 // time in accordance with its priority within the system.
+ }
+   </pre>
+ * \defgroup vTaskResume vTaskResume
+ * \ingroup TaskCtrl
+ */
+void vTaskResume( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void xTaskResumeFromISR( TaskHandle_t xTaskToResume );</pre>
+ *
+ * INCLUDE_xTaskResumeFromISR must be defined as 1 for this function to be
+ * available.  See the configuration section for more information.
+ *
+ * An implementation of vTaskResume() that can be called from within an ISR.
+ *
+ * A task that has been suspended by one or more calls to vTaskSuspend ()
+ * will be made available for running again by a single call to
+ * xTaskResumeFromISR ().
+ *
+ * xTaskResumeFromISR() should not be used to synchronise a task with an
+ * interrupt if there is a chance that the interrupt could arrive prior to the
+ * task being suspended - as this can lead to interrupts being missed. Use of a
+ * semaphore as a synchronisation mechanism would avoid this eventuality.
+ *
+ * @param xTaskToResume Handle to the task being readied.
+ *
+ * @return pdTRUE if resuming the task should result in a context switch,
+ * otherwise pdFALSE. This is used by the ISR to determine if a context switch
+ * may be required following the ISR.
+ *
+ * \defgroup vTaskResumeFromISR vTaskResumeFromISR
+ * \ingroup TaskCtrl
+ */
+BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * SCHEDULER CONTROL
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * <pre>void vTaskStartScheduler( void );</pre>
+ *
+ * Starts the real time kernel tick processing.  After calling the kernel
+ * has control over which tasks are executed and when.
+ *
+ * See the demo application file main.c for an example of creating
+ * tasks and starting the kernel.
+ *
+ * Example usage:
+   <pre>
+ void vAFunction( void )
+ {
+	 // Create at least one task before starting the kernel.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+	 // Start the real time kernel with preemption.
+	 vTaskStartScheduler ();
+
+	 // Will not get here unless a task calls vTaskEndScheduler ()
+ }
+   </pre>
+ *
+ * \defgroup vTaskStartScheduler vTaskStartScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskStartScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskEndScheduler( void );</pre>
+ *
+ * NOTE:  At the time of writing only the x86 real mode port, which runs on a PC
+ * in place of DOS, implements this function.
+ *
+ * Stops the real time kernel tick.  All created tasks will be automatically
+ * deleted and multitasking (either preemptive or cooperative) will
+ * stop.  Execution then resumes from the point where vTaskStartScheduler ()
+ * was called, as if vTaskStartScheduler () had just returned.
+ *
+ * See the demo application file main. c in the demo/PC directory for an
+ * example that uses vTaskEndScheduler ().
+ *
+ * vTaskEndScheduler () requires an exit function to be defined within the
+ * portable layer (see vPortEndScheduler () in port. c for the PC port).  This
+ * performs hardware specific operations such as stopping the kernel tick.
+ *
+ * vTaskEndScheduler () will cause all of the resources allocated by the
+ * kernel to be freed - but will not free resources allocated by application
+ * tasks.
+ *
+ * Example usage:
+   <pre>
+ void vTaskCode( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // At some point we want to end the real time kernel processing
+		 // so call ...
+		 vTaskEndScheduler ();
+	 }
+ }
+
+ void vAFunction( void )
+ {
+	 // Create at least one task before starting the kernel.
+	 xTaskCreate( vTaskCode, "NAME", STACK_SIZE, NULL, tskIDLE_PRIORITY, NULL );
+
+	 // Start the real time kernel with preemption.
+	 vTaskStartScheduler ();
+
+	 // Will only get here when the vTaskCode () task has called
+	 // vTaskEndScheduler ().  When we get here we are back to single task
+	 // execution.
+ }
+   </pre>
+ *
+ * \defgroup vTaskEndScheduler vTaskEndScheduler
+ * \ingroup SchedulerControl
+ */
+void vTaskEndScheduler( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>void vTaskSuspendAll( void );</pre>
+ *
+ * Suspends the scheduler without disabling interrupts.  Context switches will
+ * not occur while the scheduler is suspended.
+ *
+ * After calling vTaskSuspendAll () the calling task will continue to execute
+ * without risk of being swapped out until a call to xTaskResumeAll () has been
+ * made.
+ *
+ * API functions that have the potential to cause a context switch (for example,
+ * vTaskDelayUntil(), xQueueSend(), etc.) must not be called while the scheduler
+ * is suspended.
+ *
+ * Example usage:
+   <pre>
+ void vTask1( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // ...
+
+		 // At some point the task wants to perform a long operation during
+		 // which it does not want to get swapped out.  It cannot use
+		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+		 // operation may cause interrupts to be missed - including the
+		 // ticks.
+
+		 // Prevent the real time kernel swapping out the task.
+		 vTaskSuspendAll ();
+
+		 // Perform the operation here.  There is no need to use critical
+		 // sections as we have all the microcontroller processing time.
+		 // During this time interrupts will still operate and the kernel
+		 // tick count will be maintained.
+
+		 // ...
+
+		 // The operation is complete.  Restart the kernel.
+		 xTaskResumeAll ();
+	 }
+ }
+   </pre>
+ * \defgroup vTaskSuspendAll vTaskSuspendAll
+ * \ingroup SchedulerControl
+ */
+void vTaskSuspendAll( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <pre>BaseType_t xTaskResumeAll( void );</pre>
+ *
+ * Resumes scheduler activity after it was suspended by a call to
+ * vTaskSuspendAll().
+ *
+ * xTaskResumeAll() only resumes the scheduler.  It does not unsuspend tasks
+ * that were previously suspended by a call to vTaskSuspend().
+ *
+ * @return If resuming the scheduler caused a context switch then pdTRUE is
+ *		  returned, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+   <pre>
+ void vTask1( void * pvParameters )
+ {
+	 for( ;; )
+	 {
+		 // Task code goes here.
+
+		 // ...
+
+		 // At some point the task wants to perform a long operation during
+		 // which it does not want to get swapped out.  It cannot use
+		 // taskENTER_CRITICAL ()/taskEXIT_CRITICAL () as the length of the
+		 // operation may cause interrupts to be missed - including the
+		 // ticks.
+
+		 // Prevent the real time kernel swapping out the task.
+		 vTaskSuspendAll ();
+
+		 // Perform the operation here.  There is no need to use critical
+		 // sections as we have all the microcontroller processing time.
+		 // During this time interrupts will still operate and the real
+		 // time kernel tick count will be maintained.
+
+		 // ...
+
+		 // The operation is complete.  Restart the kernel.  We want to force
+		 // a context switch - but there is no point if resuming the scheduler
+		 // caused a context switch already.
+		 if( !xTaskResumeAll () )
+		 {
+			  taskYIELD ();
+		 }
+	 }
+ }
+   </pre>
+ * \defgroup xTaskResumeAll xTaskResumeAll
+ * \ingroup SchedulerControl
+ */
+BaseType_t xTaskResumeAll( void ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------
+ * TASK UTILITIES
+ *----------------------------------------------------------*/
+
+/**
+ * task. h
+ * <PRE>TickType_t xTaskGetTickCount( void );</PRE>
+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * \defgroup xTaskGetTickCount xTaskGetTickCount
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCount( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>TickType_t xTaskGetTickCountFromISR( void );</PRE>
+ *
+ * @return The count of ticks since vTaskStartScheduler was called.
+ *
+ * This is a version of xTaskGetTickCount() that is safe to be called from an
+ * ISR - provided that TickType_t is the natural word size of the
+ * microcontroller being used or interrupt nesting is either not supported or
+ * not being used.
+ *
+ * \defgroup xTaskGetTickCountFromISR xTaskGetTickCountFromISR
+ * \ingroup TaskUtils
+ */
+TickType_t xTaskGetTickCountFromISR( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>uint16_t uxTaskGetNumberOfTasks( void );</PRE>
+ *
+ * @return The number of tasks that the real time kernel is currently managing.
+ * This includes all ready, blocked and suspended tasks.  A task that
+ * has been deleted but not yet freed by the idle task will also be
+ * included in the count.
+ *
+ * \defgroup uxTaskGetNumberOfTasks uxTaskGetNumberOfTasks
+ * \ingroup TaskUtils
+ */
+UBaseType_t uxTaskGetNumberOfTasks( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>char *pcTaskGetName( TaskHandle_t xTaskToQuery );</PRE>
+ *
+ * @return The text (human readable) name of the task referenced by the handle
+ * xTaskToQuery.  A task can query its own name by either passing in its own
+ * handle, or by setting xTaskToQuery to NULL.
+ *
+ * \defgroup pcTaskGetName pcTaskGetName
+ * \ingroup TaskUtils
+ */
+char *pcTaskGetName( TaskHandle_t xTaskToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * <PRE>TaskHandle_t xTaskGetHandle( const char *pcNameToQuery );</PRE>
+ *
+ * NOTE:  This function takes a relatively long time to complete and should be
+ * used sparingly.
+ *
+ * @return The handle of the task that has the human readable name pcNameToQuery.
+ * NULL is returned if no matching name is found.  INCLUDE_xTaskGetHandle
+ * must be set to 1 in FreeRTOSConfig.h for pcTaskGetHandle() to be available.
+ *
+ * \defgroup pcTaskGetHandle pcTaskGetHandle
+ * \ingroup TaskUtils
+ */
+TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task.h
+ * <PRE>UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask );</PRE>
+ *
+ * INCLUDE_uxTaskGetStackHighWaterMark must be set to 1 in FreeRTOSConfig.h for
+ * this function to be available.
+ *
+ * Returns the high water mark of the stack associated with xTask.  That is,
+ * the minimum free stack space there has been (in words, so on a 32 bit machine
+ * a value of 1 means 4 bytes) since the task started.  The smaller the returned
+ * number the closer the task has come to overflowing its stack.
+ *
+ * @param xTask Handle of the task associated with the stack to be checked.
+ * Set xTask to NULL to check the stack of the calling task.
+ *
+ * @return The smallest amount of free stack space there has been (in words, so
+ * actual spaces on the stack rather than bytes) since the task referenced by
+ * xTask was created.
+ */
+UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/* When using trace macros it is sometimes necessary to include task.h before
+FreeRTOS.h.  When this is done TaskHookFunction_t will not yet have been defined,
+so the following two prototypes will cause a compilation error.  This can be
+fixed by simply guarding against the inclusion of these two prototypes unless
+they are explicitly required by the configUSE_APPLICATION_TASK_TAG configuration
+constant. */
+#ifdef configUSE_APPLICATION_TASK_TAG
+	#if configUSE_APPLICATION_TASK_TAG == 1
+		/**
+		 * task.h
+		 * <pre>void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction );</pre>
+		 *
+		 * Sets pxHookFunction to be the task hook function used by the task xTask.
+		 * Passing xTask as NULL has the effect of setting the calling tasks hook
+		 * function.
+		 */
+		void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction ) PRIVILEGED_FUNCTION;
+
+		/**
+		 * task.h
+		 * <pre>void xTaskGetApplicationTaskTag( TaskHandle_t xTask );</pre>
+		 *
+		 * Returns the pxHookFunction value assigned to the task xTask.
+		 */
+		TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+	#endif /* configUSE_APPLICATION_TASK_TAG ==1 */
+#endif /* ifdef configUSE_APPLICATION_TASK_TAG */
+
+#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+
+	/* Each task contains an array of pointers that is dimensioned by the
+	configNUM_THREAD_LOCAL_STORAGE_POINTERS setting in FreeRTOSConfig.h.  The
+	kernel does not use the pointers itself, so the application writer can use
+	the pointers for any purpose they wish.  The following two functions are
+	used to set and query a pointer respectively. */
+	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue ) PRIVILEGED_FUNCTION;
+	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/**
+ * task.h
+ * <pre>BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter );</pre>
+ *
+ * Calls the hook function associated with xTask.  Passing xTask as NULL has
+ * the effect of calling the Running tasks (the calling task) hook function.
+ *
+ * pvParameter is passed to the hook function for the task to interpret as it
+ * wants.  The return value is the value returned by the task hook function
+ * registered by the user.
+ */
+BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter ) PRIVILEGED_FUNCTION;
+
+/**
+ * xTaskGetIdleTaskHandle() is only available if
+ * INCLUDE_xTaskGetIdleTaskHandle is set to 1 in FreeRTOSConfig.h.
+ *
+ * Simply returns the handle of the idle task.  It is not valid to call
+ * xTaskGetIdleTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTaskGetIdleTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * configUSE_TRACE_FACILITY must be defined as 1 in FreeRTOSConfig.h for
+ * uxTaskGetSystemState() to be available.
+ *
+ * uxTaskGetSystemState() populates an TaskStatus_t structure for each task in
+ * the system.  TaskStatus_t structures contain, among other things, members
+ * for the task handle, task name, task priority, task state, and total amount
+ * of run time consumed by the task.  See the TaskStatus_t structure
+ * definition in this file for the full member list.
+ *
+ * NOTE:  This function is intended for debugging use only as its use results in
+ * the scheduler remaining suspended for an extended period.
+ *
+ * @param pxTaskStatusArray A pointer to an array of TaskStatus_t structures.
+ * The array must contain at least one TaskStatus_t structure for each task
+ * that is under the control of the RTOS.  The number of tasks under the control
+ * of the RTOS can be determined using the uxTaskGetNumberOfTasks() API function.
+ *
+ * @param uxArraySize The size of the array pointed to by the pxTaskStatusArray
+ * parameter.  The size is specified as the number of indexes in the array, or
+ * the number of TaskStatus_t structures contained in the array, not by the
+ * number of bytes in the array.
+ *
+ * @param pulTotalRunTime If configGENERATE_RUN_TIME_STATS is set to 1 in
+ * FreeRTOSConfig.h then *pulTotalRunTime is set by uxTaskGetSystemState() to the
+ * total run time (as defined by the run time stats clock, see
+ * http://www.freertos.org/rtos-run-time-stats.html) since the target booted.
+ * pulTotalRunTime can be set to NULL to omit the total run time information.
+ *
+ * @return The number of TaskStatus_t structures that were populated by
+ * uxTaskGetSystemState().  This should equal the number returned by the
+ * uxTaskGetNumberOfTasks() API function, but will be zero if the value passed
+ * in the uxArraySize parameter was too small.
+ *
+ * Example usage:
+   <pre>
+    // This example demonstrates how a human readable table of run time stats
+	// information is generated from raw data provided by uxTaskGetSystemState().
+	// The human readable table is written to pcWriteBuffer
+	void vTaskGetRunTimeStats( char *pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	volatile UBaseType_t uxArraySize, x;
+	uint32_t ulTotalRunTime, ulStatsAsPercentage;
+
+		// Make sure the write buffer does not contain a string.
+		*pcWriteBuffer = 0x00;
+
+		// Take a snapshot of the number of tasks in case it changes while this
+		// function is executing.
+		uxArraySize = uxTaskGetNumberOfTasks();
+
+		// Allocate a TaskStatus_t structure for each task.  An array could be
+		// allocated statically at compile time.
+		pxTaskStatusArray = pvPortMalloc( uxArraySize * sizeof( TaskStatus_t ) );
+
+		if( pxTaskStatusArray != NULL )
+		{
+			// Generate raw status information about each task.
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalRunTime );
+
+			// For percentage calculations.
+			ulTotalRunTime /= 100UL;
+
+			// Avoid divide by zero errors.
+			if( ulTotalRunTime > 0 )
+			{
+				// For each populated position in the pxTaskStatusArray array,
+				// format the raw data as human readable ASCII data
+				for( x = 0; x < uxArraySize; x++ )
+				{
+					// What percentage of the total run time has the task used?
+					// This will always be rounded down to the nearest integer.
+					// ulTotalRunTimeDiv100 has already been divided by 100.
+					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalRunTime;
+
+					if( ulStatsAsPercentage > 0UL )
+					{
+						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+					}
+					else
+					{
+						// If the percentage is zero here then the task has
+						// consumed less than 1% of the total run time.
+						sprintf( pcWriteBuffer, "%s\t\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].pcTaskName, pxTaskStatusArray[ x ].ulRunTimeCounter );
+					}
+
+					pcWriteBuffer += strlen( ( char * ) pcWriteBuffer );
+				}
+			}
+
+			// The array is no longer needed, free the memory it consumes.
+			vPortFree( pxTaskStatusArray );
+		}
+	}
+	</pre>
+ */
+UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>void vTaskList( char *pcWriteBuffer );</PRE>
+ *
+ * configUSE_TRACE_FACILITY and configUSE_STATS_FORMATTING_FUNCTIONS must
+ * both be defined as 1 for this function to be available.  See the
+ * configuration section of the FreeRTOS.org website for more information.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Lists all the current tasks, along with their current state and stack
+ * usage high water mark.
+ *
+ * Tasks are reported as blocked ('B'), ready ('R'), deleted ('D') or
+ * suspended ('S').
+ *
+ * PLEASE NOTE:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays task
+ * names, states and stack usage.
+ *
+ * vTaskList() has a dependency on the sprintf() C library function that might
+ * bloat the code size, use a lot of stack, and provide different results on
+ * different platforms.  An alternative, tiny, third party, and limited
+ * functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState()
+ * directly to get access to raw stats data, rather than indirectly through a
+ * call to vTaskList().
+ *
+ * @param pcWriteBuffer A buffer into which the above mentioned details
+ * will be written, in ASCII form.  This buffer is assumed to be large
+ * enough to contain the generated report.  Approximately 40 bytes per
+ * task should be sufficient.
+ *
+ * \defgroup vTaskList vTaskList
+ * \ingroup TaskUtils
+ */
+void vTaskList( char * pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * <PRE>void vTaskGetRunTimeStats( char *pcWriteBuffer );</PRE>
+ *
+ * configGENERATE_RUN_TIME_STATS and configUSE_STATS_FORMATTING_FUNCTIONS
+ * must both be defined as 1 for this function to be available.  The application
+ * must also then provide definitions for
+ * portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() and portGET_RUN_TIME_COUNTER_VALUE()
+ * to configure a peripheral timer/counter and return the timers current count
+ * value respectively.  The counter should be at least 10 times the frequency of
+ * the tick count.
+ *
+ * NOTE 1: This function will disable interrupts for its duration.  It is
+ * not intended for normal application runtime use but as a debug aid.
+ *
+ * Setting configGENERATE_RUN_TIME_STATS to 1 will result in a total
+ * accumulated execution time being stored for each task.  The resolution
+ * of the accumulated time value depends on the frequency of the timer
+ * configured by the portCONFIGURE_TIMER_FOR_RUN_TIME_STATS() macro.
+ * Calling vTaskGetRunTimeStats() writes the total execution time of each
+ * task into a buffer, both as an absolute count value and as a percentage
+ * of the total system execution time.
+ *
+ * NOTE 2:
+ *
+ * This function is provided for convenience only, and is used by many of the
+ * demo applications.  Do not consider it to be part of the scheduler.
+ *
+ * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part of the
+ * uxTaskGetSystemState() output into a human readable table that displays the
+ * amount of time each task has spent in the Running state in both absolute and
+ * percentage terms.
+ *
+ * vTaskGetRunTimeStats() has a dependency on the sprintf() C library function
+ * that might bloat the code size, use a lot of stack, and provide different
+ * results on different platforms.  An alternative, tiny, third party, and
+ * limited functionality implementation of sprintf() is provided in many of the
+ * FreeRTOS/Demo sub-directories in a file called printf-stdarg.c (note
+ * printf-stdarg.c does not provide a full snprintf() implementation!).
+ *
+ * It is recommended that production systems call uxTaskGetSystemState() directly
+ * to get access to raw stats data, rather than indirectly through a call to
+ * vTaskGetRunTimeStats().
+ *
+ * @param pcWriteBuffer A buffer into which the execution times will be
+ * written, in ASCII form.  This buffer is assumed to be large enough to
+ * contain the generated report.  Approximately 40 bytes per task should
+ * be sufficient.
+ *
+ * \defgroup vTaskGetRunTimeStats vTaskGetRunTimeStats
+ * \ingroup TaskUtils
+ */
+void vTaskGetRunTimeStats( char *pcWriteBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * task. h
+ * <PRE>BaseType_t xTaskNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction );</PRE>
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param ulValue Data that can be sent with the notification.  How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all.  Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
+ * always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The task's notification value is incremented.  ulValue is not used and
+ * xTaskNotify() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The task's notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification (the
+ * task already had a notification pending).  xTaskNotify() always returns
+ * pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending then
+ * the task's notification value is set to ulValue and xTaskNotify() will
+ * return pdPASS.  If the task being notified already had a notification
+ * pending then no action is performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification without its notification value being
+ * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
+ * this case.
+ *
+ *  pulPreviousNotificationValue -
+ *  Can be used to pass out the subject task's notification value before any
+ *  bits are modified by the notify function.
+ *
+ * @return Dependent on the value of eAction.  See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotify xTaskNotify
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue ) PRIVILEGED_FUNCTION;
+#define xTaskNotify( xTaskToNotify, ulValue, eAction ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL )
+#define xTaskNotifyAndQuery( xTaskToNotify, ulValue, eAction, pulPreviousNotifyValue ) xTaskGenericNotify( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotifyValue ) )
+
+/**
+ * task. h
+ * <PRE>BaseType_t xTaskNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, BaseType_t *pxHigherPriorityTaskWoken );</PRE>
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * A version of xTaskNotify() that can be used from an interrupt service routine
+ * (ISR).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param ulValue Data that can be sent with the notification.  How the data is
+ * used depends on the value of the eAction parameter.
+ *
+ * @param eAction Specifies how the notification updates the task's notification
+ * value, if at all.  Valid values for eAction are as follows:
+ *
+ * eSetBits -
+ * The task's notification value is bitwise ORed with ulValue.  xTaskNofify()
+ * always returns pdPASS in this case.
+ *
+ * eIncrement -
+ * The task's notification value is incremented.  ulValue is not used and
+ * xTaskNotify() always returns pdPASS in this case.
+ *
+ * eSetValueWithOverwrite -
+ * The task's notification value is set to the value of ulValue, even if the
+ * task being notified had not yet processed the previous notification (the
+ * task already had a notification pending).  xTaskNotify() always returns
+ * pdPASS in this case.
+ *
+ * eSetValueWithoutOverwrite -
+ * If the task being notified did not already have a notification pending then
+ * the task's notification value is set to ulValue and xTaskNotify() will
+ * return pdPASS.  If the task being notified already had a notification
+ * pending then no action is performed and pdFAIL is returned.
+ *
+ * eNoAction -
+ * The task receives a notification without its notification value being
+ * updated.  ulValue is not used and xTaskNotify() always returns pdPASS in
+ * this case.
+ *
+ * @param pxHigherPriorityTaskWoken  xTaskNotifyFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * xTaskNotifyFromISR() sets this value to pdTRUE then a context switch should
+ * be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * @return Dependent on the value of eAction.  See the description of the
+ * eAction parameter.
+ *
+ * \defgroup xTaskNotify xTaskNotify
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+#define xTaskNotifyFromISR( xTaskToNotify, ulValue, eAction, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), NULL, ( pxHigherPriorityTaskWoken ) )
+#define xTaskNotifyAndQueryFromISR( xTaskToNotify, ulValue, eAction, pulPreviousNotificationValue, pxHigherPriorityTaskWoken ) xTaskGenericNotifyFromISR( ( xTaskToNotify ), ( ulValue ), ( eAction ), ( pulPreviousNotificationValue ), ( pxHigherPriorityTaskWoken ) )
+
+/**
+ * task. h
+ * <PRE>BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait );</pre>
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * A notification sent to a task will remain pending until it is cleared by the
+ * task calling xTaskNotifyWait() or ulTaskNotifyTake().  If the task was
+ * already in the Blocked state to wait for a notification when the notification
+ * arrives then the task will automatically be removed from the Blocked state
+ * (unblocked) and the notification cleared.
+ *
+ * A task can use xTaskNotifyWait() to [optionally] block to wait for a
+ * notification to be pending, or ulTaskNotifyTake() to [optionally] block
+ * to wait for its notification value to have a non-zero value.  The task does
+ * not consume any CPU time while it is in the Blocked state.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param ulBitsToClearOnEntry Bits that are set in ulBitsToClearOnEntry value
+ * will be cleared in the calling task's notification value before the task
+ * checks to see if any notifications are pending, and optionally blocks if no
+ * notifications are pending.  Setting ulBitsToClearOnEntry to ULONG_MAX (if
+ * limits.h is included) or 0xffffffffUL (if limits.h is not included) will have
+ * the effect of resetting the task's notification value to 0.  Setting
+ * ulBitsToClearOnEntry to 0 will leave the task's notification value unchanged.
+ *
+ * @param ulBitsToClearOnExit If a notification is pending or received before
+ * the calling task exits the xTaskNotifyWait() function then the task's
+ * notification value (see the xTaskNotify() API function) is passed out using
+ * the pulNotificationValue parameter.  Then any bits that are set in
+ * ulBitsToClearOnExit will be cleared in the task's notification value (note
+ * *pulNotificationValue is set before any bits are cleared).  Setting
+ * ulBitsToClearOnExit to ULONG_MAX (if limits.h is included) or 0xffffffffUL
+ * (if limits.h is not included) will have the effect of resetting the task's
+ * notification value to 0 before the function exits.  Setting
+ * ulBitsToClearOnExit to 0 will leave the task's notification value unchanged
+ * when the function exits (in which case the value passed out in
+ * pulNotificationValue will match the task's notification value).
+ *
+ * @param pulNotificationValue Used to pass the task's notification value out
+ * of the function.  Note the value passed out will not be effected by the
+ * clearing of any bits caused by ulBitsToClearOnExit being non-zero.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for a notification to be received, should a notification
+ * not already be pending when xTaskNotifyWait() was called.  The task
+ * will not consume any processing time while it is in the Blocked state.  This
+ * is specified in kernel ticks, the macro pdMS_TO_TICSK( value_in_ms ) can be
+ * used to convert a time specified in milliseconds to a time specified in
+ * ticks.
+ *
+ * @return If a notification was received (including notifications that were
+ * already pending when xTaskNotifyWait was called) then pdPASS is
+ * returned.  Otherwise pdFAIL is returned.
+ *
+ * \defgroup xTaskNotifyWait xTaskNotifyWait
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>BaseType_t xTaskNotifyGive( TaskHandle_t xTaskToNotify );</PRE>
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * xTaskNotifyGive() is a helper macro intended for use when task notifications
+ * are used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given using the xSemaphoreGive() API function,
+ * the equivalent action that instead uses a task notification is
+ * xTaskNotifyGive().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTake() API function rather than the
+ * xTaskNotifyWait() API function.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @return xTaskNotifyGive() is a macro that calls xTaskNotify() with the
+ * eAction parameter set to eIncrement - so pdPASS is always returned.
+ *
+ * \defgroup xTaskNotifyGive xTaskNotifyGive
+ * \ingroup TaskNotifications
+ */
+#define xTaskNotifyGive( xTaskToNotify ) xTaskGenericNotify( ( xTaskToNotify ), ( 0 ), eIncrement, NULL )
+
+/**
+ * task. h
+ * <PRE>void vTaskNotifyGiveFromISR( TaskHandle_t xTaskHandle, BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this macro
+ * to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * A version of xTaskNotifyGive() that can be called from an interrupt service
+ * routine (ISR).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * vTaskNotifyGiveFromISR() is intended for use when task notifications are
+ * used as light weight and faster binary or counting semaphore equivalents.
+ * Actual FreeRTOS semaphores are given from an ISR using the
+ * xSemaphoreGiveFromISR() API function, the equivalent action that instead uses
+ * a task notification is vTaskNotifyGiveFromISR().
+ *
+ * When task notifications are being used as a binary or counting semaphore
+ * equivalent then the task being notified should wait for the notification
+ * using the ulTaskNotificationTake() API function rather than the
+ * xTaskNotifyWait() API function.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for more details.
+ *
+ * @param xTaskToNotify The handle of the task being notified.  The handle to a
+ * task can be returned from the xTaskCreate() API function used to create the
+ * task, and the handle of the currently running task can be obtained by calling
+ * xTaskGetCurrentTaskHandle().
+ *
+ * @param pxHigherPriorityTaskWoken  vTaskNotifyGiveFromISR() will set
+ * *pxHigherPriorityTaskWoken to pdTRUE if sending the notification caused the
+ * task to which the notification was sent to leave the Blocked state, and the
+ * unblocked task has a priority higher than the currently running task.  If
+ * vTaskNotifyGiveFromISR() sets this value to pdTRUE then a context switch
+ * should be requested before the interrupt is exited.  How a context switch is
+ * requested from an ISR is dependent on the port - see the documentation page
+ * for the port in use.
+ *
+ * \defgroup xTaskNotifyWait xTaskNotifyWait
+ * \ingroup TaskNotifications
+ */
+void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait );</pre>
+ *
+ * configUSE_TASK_NOTIFICATIONS must be undefined or defined as 1 for this
+ * function to be available.
+ *
+ * When configUSE_TASK_NOTIFICATIONS is set to one each task has its own private
+ * "notification value", which is a 32-bit unsigned integer (uint32_t).
+ *
+ * Events can be sent to a task using an intermediary object.  Examples of such
+ * objects are queues, semaphores, mutexes and event groups.  Task notifications
+ * are a method of sending an event directly to a task without the need for such
+ * an intermediary object.
+ *
+ * A notification sent to a task can optionally perform an action, such as
+ * update, overwrite or increment the task's notification value.  In that way
+ * task notifications can be used to send data to a task, or be used as light
+ * weight and fast binary or counting semaphores.
+ *
+ * ulTaskNotifyTake() is intended for use when a task notification is used as a
+ * faster and lighter weight binary or counting semaphore alternative.  Actual
+ * FreeRTOS semaphores are taken using the xSemaphoreTake() API function, the
+ * equivalent action that instead uses a task notification is
+ * ulTaskNotifyTake().
+ *
+ * When a task is using its notification value as a binary or counting semaphore
+ * other tasks should send notifications to it using the xTaskNotifyGive()
+ * macro, or xTaskNotify() function with the eAction parameter set to
+ * eIncrement.
+ *
+ * ulTaskNotifyTake() can either clear the task's notification value to
+ * zero on exit, in which case the notification value acts like a binary
+ * semaphore, or decrement the task's notification value on exit, in which case
+ * the notification value acts like a counting semaphore.
+ *
+ * A task can use ulTaskNotifyTake() to [optionally] block to wait for a
+ * the task's notification value to be non-zero.  The task does not consume any
+ * CPU time while it is in the Blocked state.
+ *
+ * Where as xTaskNotifyWait() will return when a notification is pending,
+ * ulTaskNotifyTake() will return when the task's notification value is
+ * not zero.
+ *
+ * See http://www.FreeRTOS.org/RTOS-task-notifications.html for details.
+ *
+ * @param xClearCountOnExit if xClearCountOnExit is pdFALSE then the task's
+ * notification value is decremented when the function exits.  In this way the
+ * notification value acts like a counting semaphore.  If xClearCountOnExit is
+ * not pdFALSE then the task's notification value is cleared to zero when the
+ * function exits.  In this way the notification value acts like a binary
+ * semaphore.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait in
+ * the Blocked state for the task's notification value to be greater than zero,
+ * should the count not already be greater than zero when
+ * ulTaskNotifyTake() was called.  The task will not consume any processing
+ * time while it is in the Blocked state.  This is specified in kernel ticks,
+ * the macro pdMS_TO_TICSK( value_in_ms ) can be used to convert a time
+ * specified in milliseconds to a time specified in ticks.
+ *
+ * @return The task's notification count before it is either cleared to zero or
+ * decremented (see the xClearCountOnExit parameter).
+ *
+ * \defgroup ulTaskNotifyTake ulTaskNotifyTake
+ * \ingroup TaskNotifications
+ */
+uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * task. h
+ * <PRE>BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );</pre>
+ *
+ * If the notification state of the task referenced by the handle xTask is
+ * eNotified, then set the task's notification state to eNotWaitingNotification.
+ * The task's notification value is not altered.  Set xTask to NULL to clear the
+ * notification state of the calling task.
+ *
+ * @return pdTRUE if the task's notification state was set to
+ * eNotWaitingNotification, otherwise pdFALSE.
+ * \defgroup xTaskNotifyStateClear xTaskNotifyStateClear
+ * \ingroup TaskNotifications
+ */
+BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask );
+
+/*-----------------------------------------------------------
+ * SCHEDULER INTERNALS AVAILABLE FOR PORTING PURPOSES
+ *----------------------------------------------------------*/
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Called from the real time kernel tick (either preemptive or cooperative),
+ * this increments the tick count and checks if any tasks that are blocked
+ * for a finite period required removing from a blocked list and placing on
+ * a ready list.  If a non-zero value is returned then a context switch is
+ * required because either:
+ *   + A task was removed from a blocked list because its timeout had expired,
+ *     or
+ *   + Time slicing is in use and there is a task of equal priority to the
+ *     currently running task.
+ */
+BaseType_t xTaskIncrementTick( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes the calling task from the ready list and places it both
+ * on the list of tasks waiting for a particular event, and the
+ * list of delayed tasks.  The task will be removed from both lists
+ * and replaced on the ready list should either the event occur (and
+ * there be no higher priority tasks waiting on the same event) or
+ * the delay period expires.
+ *
+ * The 'unordered' version replaces the event list item value with the
+ * xItemValue value, and inserts the list item at the end of the list.
+ *
+ * The 'ordered' version uses the existing event list item value (which is the
+ * owning tasks priority) to insert the list item into the event list is task
+ * priority order.
+ *
+ * @param pxEventList The list containing tasks that are blocked waiting
+ * for the event to occur.
+ *
+ * @param xItemValue The item value to use for the event list item when the
+ * event list is not ordered by task priority.
+ *
+ * @param xTicksToWait The maximum amount of time that the task should wait
+ * for the event to occur.  This is specified in kernel ticks,the constant
+ * portTICK_PERIOD_MS can be used to convert kernel ticks into a real time
+ * period.
+ */
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * This function performs nearly the same function as vTaskPlaceOnEventList().
+ * The difference being that this function does not permit tasks to block
+ * indefinitely, whereas vTaskPlaceOnEventList() does.
+ *
+ */
+void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS AN
+ * INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * THIS FUNCTION MUST BE CALLED WITH INTERRUPTS DISABLED.
+ *
+ * Removes a task from both the specified event list and the list of blocked
+ * tasks, and places it on a ready queue.
+ *
+ * xTaskRemoveFromEventList()/xTaskRemoveFromUnorderedEventList() will be called
+ * if either an event occurs to unblock a task, or the block timeout period
+ * expires.
+ *
+ * xTaskRemoveFromEventList() is used when the event list is in task priority
+ * order.  It removes the list item from the head of the event list as that will
+ * have the highest priority owning task of all the tasks on the event list.
+ * xTaskRemoveFromUnorderedEventList() is used when the event list is not
+ * ordered and the event list items hold something other than the owning tasks
+ * priority.  In this case the event list item value is updated to the value
+ * passed in the xItemValue parameter.
+ *
+ * @return pdTRUE if the task being removed has a higher priority than the task
+ * making the call, otherwise pdFALSE.
+ */
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList ) PRIVILEGED_FUNCTION;
+BaseType_t xTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue ) PRIVILEGED_FUNCTION;
+
+/*
+ * THIS FUNCTION MUST NOT BE USED FROM APPLICATION CODE.  IT IS ONLY
+ * INTENDED FOR USE WHEN IMPLEMENTING A PORT OF THE SCHEDULER AND IS
+ * AN INTERFACE WHICH IS FOR THE EXCLUSIVE USE OF THE SCHEDULER.
+ *
+ * Sets the pointer to the current TCB to the TCB of the highest priority task
+ * that is ready to run.
+ */
+void vTaskSwitchContext( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * THESE FUNCTIONS MUST NOT BE USED FROM APPLICATION CODE.  THEY ARE USED BY
+ * THE EVENT BITS MODULE.
+ */
+TickType_t uxTaskResetEventItemValue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Return the handle of the calling task.
+ */
+TaskHandle_t xTaskGetCurrentTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Capture the current time status for future reference.
+ */
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut ) PRIVILEGED_FUNCTION;
+
+/*
+ * Compare the time status now with that previously captured to see if the
+ * timeout has expired.
+ */
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait ) PRIVILEGED_FUNCTION;
+
+/*
+ * Shortcut used by the queue implementation to prevent unnecessary call to
+ * taskYIELD();
+ */
+void vTaskMissedYield( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Returns the scheduler state as taskSCHEDULER_RUNNING,
+ * taskSCHEDULER_NOT_STARTED or taskSCHEDULER_SUSPENDED.
+ */
+BaseType_t xTaskGetSchedulerState( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Raises the priority of the mutex holder to that of the calling task should
+ * the mutex holder have a priority less than the calling task.
+ */
+void vTaskPriorityInherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the priority of a task back to its proper priority in the case that it
+ * inherited a higher priority while it was holding a semaphore.
+ */
+BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder ) PRIVILEGED_FUNCTION;
+
+/*
+ * Get the uxTCBNumber assigned to the task referenced by the xTask parameter.
+ */
+UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+
+/*
+ * Set the uxTaskNumber of the task referenced by the xTask parameter to
+ * uxHandle.
+ */
+void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only available when configUSE_TICKLESS_IDLE is set to 1.
+ * If tickless mode is being used, or a low power mode is implemented, then
+ * the tick interrupt will not execute during idle periods.  When this is the
+ * case, the tick count value maintained by the scheduler needs to be kept up
+ * to date with the actual execution time by being skipped forward by a time
+ * equal to the idle period.
+ */
+void vTaskStepTick( const TickType_t xTicksToJump ) PRIVILEGED_FUNCTION;
+
+/*
+ * Only avilable when configUSE_TICKLESS_IDLE is set to 1.
+ * Provided for use within portSUPPRESS_TICKS_AND_SLEEP() to allow the port
+ * specific sleep function to determine if it is ok to proceed with the sleep,
+ * and if it is ok to proceed, if it is ok to sleep indefinitely.
+ *
+ * This function is necessary because portSUPPRESS_TICKS_AND_SLEEP() is only
+ * called with the scheduler suspended, not from within a critical section.  It
+ * is therefore possible for an interrupt to request a context switch between
+ * portSUPPRESS_TICKS_AND_SLEEP() and the low power mode actually being
+ * entered.  eTaskConfirmSleepModeStatus() should be called from a short
+ * critical section between the timer being stopped and the sleep mode being
+ * entered to ensure it is ok to proceed into the sleep mode.
+ */
+eSleepModeStatus eTaskConfirmSleepModeStatus( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * For internal use only.  Increment the mutex held count when a mutex is
+ * taken and return the handle of the task that has taken the mutex.
+ */
+void *pvTaskIncrementMutexHeldCount( void ) PRIVILEGED_FUNCTION;
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* INC_TASK_H */
+
+
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/tasks.c b/STM32F1/libraries/FreeRTOS900/utility/tasks.c
new file mode 100644
index 000000000..6c261a651
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/tasks.c
@@ -0,0 +1,4807 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/* Standard includes. */
+#include <stdlib.h>
+#include <string.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+/* FreeRTOS includes. */
+#include "FreeRTOS.h"
+#include "task.h"
+#include "timers.h"
+#include "StackMacros.h"
+
+/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
+MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
+header files above, but not in this file, in order to generate the correct
+privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+
+/* Set configUSE_STATS_FORMATTING_FUNCTIONS to 2 to include the stats formatting
+functions but without including stdio.h here. */
+#if ( configUSE_STATS_FORMATTING_FUNCTIONS == 1 )
+	/* At the bottom of this file are two optional functions that can be used
+	to generate human readable text from the raw data generated by the
+	uxTaskGetSystemState() function.  Note the formatting functions are provided
+	for convenience only, and are NOT considered part of the kernel. */
+	#include <stdio.h>
+#endif /* configUSE_STATS_FORMATTING_FUNCTIONS == 1 ) */
+
+#if( configUSE_PREEMPTION == 0 )
+	/* If the cooperative scheduler is being used then a yield should not be
+	performed just because a higher priority task has been woken. */
+	#define taskYIELD_IF_USING_PREEMPTION()
+#else
+	#define taskYIELD_IF_USING_PREEMPTION() portYIELD_WITHIN_API()
+#endif
+
+/* Values that can be assigned to the ucNotifyState member of the TCB. */
+#define taskNOT_WAITING_NOTIFICATION	( ( uint8_t ) 0 )
+#define taskWAITING_NOTIFICATION		( ( uint8_t ) 1 )
+#define taskNOTIFICATION_RECEIVED		( ( uint8_t ) 2 )
+
+/*
+ * The value used to fill the stack of a task when the task is created.  This
+ * is used purely for checking the high water mark for tasks.
+ */
+#define tskSTACK_FILL_BYTE	( 0xa5U )
+
+/* Sometimes the FreeRTOSConfig.h settings only allow a task to be created using
+dynamically allocated RAM, in which case when any task is deleted it is known
+that both the task's stack and TCB need to be freed.  Sometimes the
+FreeRTOSConfig.h settings only allow a task to be created using statically
+allocated RAM, in which case when any task is deleted it is known that neither
+the task's stack or TCB should be freed.  Sometimes the FreeRTOSConfig.h
+settings allow a task to be created using either statically or dynamically
+allocated RAM, in which case a member of the TCB is used to record whether the
+stack and/or TCB were allocated statically or dynamically, so when a task is
+deleted the RAM that was allocated dynamically is freed again and no attempt is
+made to free the RAM that was allocated statically.
+tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE is only true if it is possible for a
+task to be created using either statically or dynamically allocated RAM.  Note
+that if portUSING_MPU_WRAPPERS is 1 then a protected task can be created with
+a statically allocated stack and a dynamically allocated TCB. */
+#define tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE ( ( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) ) || ( portUSING_MPU_WRAPPERS == 1 ) )
+#define tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB 		( ( uint8_t ) 0 )
+#define tskSTATICALLY_ALLOCATED_STACK_ONLY 			( ( uint8_t ) 1 )
+#define tskSTATICALLY_ALLOCATED_STACK_AND_TCB		( ( uint8_t ) 2 )
+
+/*
+ * Macros used by vListTask to indicate which state a task is in.
+ */
+#define tskBLOCKED_CHAR		( 'B' )
+#define tskREADY_CHAR		( 'R' )
+#define tskDELETED_CHAR		( 'D' )
+#define tskSUSPENDED_CHAR	( 'S' )
+
+/*
+ * Some kernel aware debuggers require the data the debugger needs access to be
+ * global, rather than file scope.
+ */
+#ifdef portREMOVE_STATIC_QUALIFIER
+	#define static
+#endif
+
+#if ( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+
+	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 0 then task selection is
+	performed in a generic way that is not optimised to any particular
+	microcontroller architecture. */
+
+	/* uxTopReadyPriority holds the priority of the highest priority ready
+	state task. */
+	#define taskRECORD_READY_PRIORITY( uxPriority )														\
+	{																									\
+		if( ( uxPriority ) > uxTopReadyPriority )														\
+		{																								\
+			uxTopReadyPriority = ( uxPriority );														\
+		}																								\
+	} /* taskRECORD_READY_PRIORITY */
+
+	/*-----------------------------------------------------------*/
+
+	#define taskSELECT_HIGHEST_PRIORITY_TASK()															\
+	{																									\
+	UBaseType_t uxTopPriority = uxTopReadyPriority;														\
+																										\
+		/* Find the highest priority queue that contains ready tasks. */								\
+		while( listLIST_IS_EMPTY( &( pxReadyTasksLists[ uxTopPriority ] ) ) )							\
+		{																								\
+			configASSERT( uxTopPriority );																\
+			--uxTopPriority;																			\
+		}																								\
+																										\
+		/* listGET_OWNER_OF_NEXT_ENTRY indexes through the list, so the tasks of						\
+		the	same priority get an equal share of the processor time. */									\
+		listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );			\
+		uxTopReadyPriority = uxTopPriority;																\
+	} /* taskSELECT_HIGHEST_PRIORITY_TASK */
+
+	/*-----------------------------------------------------------*/
+
+	/* Define away taskRESET_READY_PRIORITY() and portRESET_READY_PRIORITY() as
+	they are only required when a port optimised method of task selection is
+	being used. */
+	#define taskRESET_READY_PRIORITY( uxPriority )
+	#define portRESET_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+#else /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+	/* If configUSE_PORT_OPTIMISED_TASK_SELECTION is 1 then task selection is
+	performed in a way that is tailored to the particular microcontroller
+	architecture being used. */
+
+	/* A port optimised version is provided.  Call the port defined macros. */
+	#define taskRECORD_READY_PRIORITY( uxPriority )	portRECORD_READY_PRIORITY( uxPriority, uxTopReadyPriority )
+
+	/*-----------------------------------------------------------*/
+
+	#define taskSELECT_HIGHEST_PRIORITY_TASK()														\
+	{																								\
+	UBaseType_t uxTopPriority;																		\
+																									\
+		/* Find the highest priority list that contains ready tasks. */								\
+		portGET_HIGHEST_PRIORITY( uxTopPriority, uxTopReadyPriority );								\
+		configASSERT( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ uxTopPriority ] ) ) > 0 );		\
+		listGET_OWNER_OF_NEXT_ENTRY( pxCurrentTCB, &( pxReadyTasksLists[ uxTopPriority ] ) );		\
+	} /* taskSELECT_HIGHEST_PRIORITY_TASK() */
+
+	/*-----------------------------------------------------------*/
+
+	/* A port optimised version is provided, call it only if the TCB being reset
+	is being referenced from a ready list.  If it is referenced from a delayed
+	or suspended list then it won't be in a ready list. */
+	#define taskRESET_READY_PRIORITY( uxPriority )														\
+	{																									\
+		if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ ( uxPriority ) ] ) ) == ( UBaseType_t ) 0 )	\
+		{																								\
+			portRESET_READY_PRIORITY( ( uxPriority ), ( uxTopReadyPriority ) );							\
+		}																								\
+	}
+
+#endif /* configUSE_PORT_OPTIMISED_TASK_SELECTION */
+
+/*-----------------------------------------------------------*/
+
+/* pxDelayedTaskList and pxOverflowDelayedTaskList are switched when the tick
+count overflows. */
+#define taskSWITCH_DELAYED_LISTS()																	\
+{																									\
+	List_t *pxTemp;																					\
+																									\
+	/* The delayed tasks list should be empty when the lists are switched. */						\
+	configASSERT( ( listLIST_IS_EMPTY( pxDelayedTaskList ) ) );										\
+																									\
+	pxTemp = pxDelayedTaskList;																		\
+	pxDelayedTaskList = pxOverflowDelayedTaskList;													\
+	pxOverflowDelayedTaskList = pxTemp;																\
+	xNumOfOverflows++;																				\
+	prvResetNextTaskUnblockTime();																	\
+}
+
+/*-----------------------------------------------------------*/
+
+/*
+ * Place the task represented by pxTCB into the appropriate ready list for
+ * the task.  It is inserted at the end of the list.
+ */
+#define prvAddTaskToReadyList( pxTCB )																\
+	traceMOVED_TASK_TO_READY_STATE( pxTCB );														\
+	taskRECORD_READY_PRIORITY( ( pxTCB )->uxPriority );												\
+	vListInsertEnd( &( pxReadyTasksLists[ ( pxTCB )->uxPriority ] ), &( ( pxTCB )->xStateListItem ) ); \
+	tracePOST_MOVED_TASK_TO_READY_STATE( pxTCB )
+/*-----------------------------------------------------------*/
+
+/*
+ * Several functions take an TaskHandle_t parameter that can optionally be NULL,
+ * where NULL is used to indicate that the handle of the currently executing
+ * task should be used in place of the parameter.  This macro simply checks to
+ * see if the parameter is NULL and returns a pointer to the appropriate TCB.
+ */
+#define prvGetTCBFromHandle( pxHandle ) ( ( ( pxHandle ) == NULL ) ? ( TCB_t * ) pxCurrentTCB : ( TCB_t * ) ( pxHandle ) )
+
+/* The item value of the event list item is normally used to hold the priority
+of the task to which it belongs (coded to allow it to be held in reverse
+priority order).  However, it is occasionally borrowed for other purposes.  It
+is important its value is not updated due to a task priority change while it is
+being used for another purpose.  The following bit definition is used to inform
+the scheduler that the value should not be changed - in which case it is the
+responsibility of whichever module is using the value to ensure it gets set back
+to its original value when it is released. */
+#if( configUSE_16_BIT_TICKS == 1 )
+	#define taskEVENT_LIST_ITEM_VALUE_IN_USE	0x8000U
+#else
+	#define taskEVENT_LIST_ITEM_VALUE_IN_USE	0x80000000UL
+#endif
+
+/*
+ * Task control block.  A task control block (TCB) is allocated for each task,
+ * and stores task state information, including a pointer to the task's context
+ * (the task's run time environment, including register values)
+ */
+typedef struct tskTaskControlBlock
+{
+	volatile StackType_t	*pxTopOfStack;	/*< Points to the location of the last item placed on the tasks stack.  THIS MUST BE THE FIRST MEMBER OF THE TCB STRUCT. */
+
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+		xMPU_SETTINGS	xMPUSettings;		/*< The MPU settings are defined as part of the port layer.  THIS MUST BE THE SECOND MEMBER OF THE TCB STRUCT. */
+	#endif
+
+	ListItem_t			xStateListItem;	/*< The list that the state list item of a task is reference from denotes the state of that task (Ready, Blocked, Suspended ). */
+	ListItem_t			xEventListItem;		/*< Used to reference a task from an event list. */
+	UBaseType_t			uxPriority;			/*< The priority of the task.  0 is the lowest priority. */
+	StackType_t			*pxStack;			/*< Points to the start of the stack. */
+	char				pcTaskName[ configMAX_TASK_NAME_LEN ];/*< Descriptive name given to the task when created.  Facilitates debugging only. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+	#if ( portSTACK_GROWTH > 0 )
+		StackType_t		*pxEndOfStack;		/*< Points to the end of the stack on architectures where the stack grows up from low memory. */
+	#endif
+
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+		UBaseType_t		uxCriticalNesting;	/*< Holds the critical section nesting depth for ports that do not maintain their own count in the port layer. */
+	#endif
+
+	#if ( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t		uxTCBNumber;		/*< Stores a number that increments each time a TCB is created.  It allows debuggers to determine when a task has been deleted and then recreated. */
+		UBaseType_t		uxTaskNumber;		/*< Stores a number specifically for use by third party trace code. */
+	#endif
+
+	#if ( configUSE_MUTEXES == 1 )
+		UBaseType_t		uxBasePriority;		/*< The priority last assigned to the task - used by the priority inheritance mechanism. */
+		UBaseType_t		uxMutexesHeld;
+	#endif
+
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+		TaskHookFunction_t pxTaskTag;
+	#endif
+
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS > 0 )
+		void *pvThreadLocalStoragePointers[ configNUM_THREAD_LOCAL_STORAGE_POINTERS ];
+	#endif
+
+	#if( configGENERATE_RUN_TIME_STATS == 1 )
+		uint32_t		ulRunTimeCounter;	/*< Stores the amount of time the task has spent in the Running state. */
+	#endif
+
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		/* Allocate a Newlib reent structure that is specific to this task.
+		Note Newlib support has been included by popular demand, but is not
+		used by the FreeRTOS maintainers themselves.  FreeRTOS is not
+		responsible for resulting newlib operation.  User must be familiar with
+		newlib and must provide system-wide implementations of the necessary
+		stubs. Be warned that (at the time of writing) the current newlib design
+		implements a system-wide malloc() that must be provided with locks. */
+		struct	_reent xNewLib_reent;
+	#endif
+
+	#if( configUSE_TASK_NOTIFICATIONS == 1 )
+		volatile uint32_t ulNotifiedValue;
+		volatile uint8_t ucNotifyState;
+	#endif
+
+	/* See the comments above the definition of
+	tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE. */
+	#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+		uint8_t	ucStaticallyAllocated; 		/*< Set to pdTRUE if the task is a statically allocated to ensure no attempt is made to free the memory. */
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+		uint8_t ucDelayAborted;
+	#endif
+
+} tskTCB;
+
+/* The old tskTCB name is maintained above then typedefed to the new TCB_t name
+below to enable the use of older kernel aware debuggers. */
+typedef tskTCB TCB_t;
+
+/*lint -e956 A manual analysis and inspection has been used to determine which
+static variables must be declared volatile. */
+
+PRIVILEGED_DATA TCB_t * volatile pxCurrentTCB = NULL;
+
+/* Lists for ready and blocked tasks. --------------------*/
+PRIVILEGED_DATA static List_t pxReadyTasksLists[ configMAX_PRIORITIES ];/*< Prioritised ready tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList1;						/*< Delayed tasks. */
+PRIVILEGED_DATA static List_t xDelayedTaskList2;						/*< Delayed tasks (two lists are used - one for delays that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t * volatile pxDelayedTaskList;				/*< Points to the delayed task list currently being used. */
+PRIVILEGED_DATA static List_t * volatile pxOverflowDelayedTaskList;		/*< Points to the delayed task list currently being used to hold tasks that have overflowed the current tick count. */
+PRIVILEGED_DATA static List_t xPendingReadyList;						/*< Tasks that have been readied while the scheduler was suspended.  They will be moved to the ready list when the scheduler is resumed. */
+
+#if( INCLUDE_vTaskDelete == 1 )
+
+	PRIVILEGED_DATA static List_t xTasksWaitingTermination;				/*< Tasks that have been deleted - but their memory not yet freed. */
+	PRIVILEGED_DATA static volatile UBaseType_t uxDeletedTasksWaitingCleanUp = ( UBaseType_t ) 0U;
+
+#endif
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	PRIVILEGED_DATA static List_t xSuspendedTaskList;					/*< Tasks that are currently suspended. */
+
+#endif
+
+/* Other file private variables. --------------------------------*/
+PRIVILEGED_DATA static volatile UBaseType_t uxCurrentNumberOfTasks 	= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xTickCount 				= ( TickType_t ) 0U;
+PRIVILEGED_DATA static volatile UBaseType_t uxTopReadyPriority 		= tskIDLE_PRIORITY;
+PRIVILEGED_DATA static volatile BaseType_t xSchedulerRunning 		= pdFALSE;
+PRIVILEGED_DATA static volatile UBaseType_t uxPendedTicks 			= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile BaseType_t xYieldPending 			= pdFALSE;
+PRIVILEGED_DATA static volatile BaseType_t xNumOfOverflows 			= ( BaseType_t ) 0;
+PRIVILEGED_DATA static UBaseType_t uxTaskNumber 					= ( UBaseType_t ) 0U;
+PRIVILEGED_DATA static volatile TickType_t xNextTaskUnblockTime		= ( TickType_t ) 0U; /* Initialised to portMAX_DELAY before the scheduler starts. */
+PRIVILEGED_DATA static TaskHandle_t xIdleTaskHandle					= NULL;			/*< Holds the handle of the idle task.  The idle task is created automatically when the scheduler is started. */
+
+/* Context switches are held pending while the scheduler is suspended.  Also,
+interrupts must not manipulate the xStateListItem of a TCB, or any of the
+lists the xStateListItem can be referenced from, if the scheduler is suspended.
+If an interrupt needs to unblock a task while the scheduler is suspended then it
+moves the task's event list item into the xPendingReadyList, ready for the
+kernel to move the task from the pending ready list into the real ready list
+when the scheduler is unsuspended.  The pending ready list itself can only be
+accessed from a critical section. */
+PRIVILEGED_DATA static volatile UBaseType_t uxSchedulerSuspended	= ( UBaseType_t ) pdFALSE;
+
+#if ( configGENERATE_RUN_TIME_STATS == 1 )
+
+	PRIVILEGED_DATA static uint32_t ulTaskSwitchedInTime = 0UL;	/*< Holds the value of a timer/counter the last time a task was switched in. */
+	PRIVILEGED_DATA static uint32_t ulTotalRunTime = 0UL;		/*< Holds the total amount of execution time as defined by the run time counter clock. */
+
+#endif
+
+/*lint +e956 */
+
+/*-----------------------------------------------------------*/
+
+/* Callback function prototypes. --------------------------*/
+#if(  configCHECK_FOR_STACK_OVERFLOW > 0 )
+	extern void vApplicationStackOverflowHook( TaskHandle_t xTask, char *pcTaskName );
+#endif
+
+#if( configUSE_TICK_HOOK > 0 )
+	extern void vApplicationTickHook( void );
+#endif
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	extern void vApplicationGetIdleTaskMemory( StaticTask_t **ppxIdleTaskTCBBuffer, StackType_t **ppxIdleTaskStackBuffer, uint32_t *pulIdleTaskStackSize );
+#endif
+
+/* File private functions. --------------------------------*/
+
+/**
+ * Utility task that simply returns pdTRUE if the task referenced by xTask is
+ * currently in the Suspended state, or pdFALSE if the task referenced by xTask
+ * is in any other state.
+ */
+#if ( INCLUDE_vTaskSuspend == 1 )
+	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask ) PRIVILEGED_FUNCTION;
+#endif /* INCLUDE_vTaskSuspend */
+
+/*
+ * Utility to ready all the lists used by the scheduler.  This is called
+ * automatically upon the creation of the first task.
+ */
+static void prvInitialiseTaskLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The idle task, which as all tasks is implemented as a never ending loop.
+ * The idle task is automatically created and added to the ready lists upon
+ * creation of the first user task.
+ *
+ * The portTASK_FUNCTION_PROTO() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION_PROTO( prvIdleTask, pvParameters );
+
+/*
+ * Utility to free all memory allocated by the scheduler to hold a TCB,
+ * including the stack pointed to by the TCB.
+ *
+ * This does not free memory allocated by the task itself (i.e. memory
+ * allocated by calls to pvPortMalloc from within the tasks application code).
+ */
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	static void prvDeleteTCB( TCB_t *pxTCB ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Used only by the idle task.  This checks to see if anything has been placed
+ * in the list of tasks waiting to be deleted.  If so the task is cleaned up
+ * and its TCB deleted.
+ */
+static void prvCheckTasksWaitingTermination( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The currently executing task is entering the Blocked state.  Add the task to
+ * either the current or the overflow delayed task list.
+ */
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely ) PRIVILEGED_FUNCTION;
+
+/*
+ * Fills an TaskStatus_t structure with information on each task that is
+ * referenced from the pxList list (which may be a ready list, a delayed list,
+ * a suspended list, etc.).
+ *
+ * THIS FUNCTION IS INTENDED FOR DEBUGGING ONLY, AND SHOULD NOT BE CALLED FROM
+ * NORMAL APPLICATION CODE.
+ */
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Searches pxList for a task with name pcNameToQuery - returning a handle to
+ * the task if it is found, or NULL if the task is not found.
+ */
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * When a task is created, the stack of the task is filled with a known value.
+ * This function determines the 'high water mark' of the task stack by
+ * determining how much of the stack remains at the original preset value.
+ */
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
+
+	static uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Return the amount of time, in ticks, that will pass before the kernel will
+ * next move a task from the Blocked state to the Running state.
+ *
+ * This conditional compilation should use inequality to 0, not equality to 1.
+ * This is to ensure portSUPPRESS_TICKS_AND_SLEEP() can be called when user
+ * defined low power mode implementations require configUSE_TICKLESS_IDLE to be
+ * set to a value other than 1.
+ */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	static TickType_t prvGetExpectedIdleTime( void ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Set xNextTaskUnblockTime to the time at which the next Blocked state task
+ * will exit the Blocked state.
+ */
+static void prvResetNextTaskUnblockTime( void );
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+	/*
+	 * Helper function used to pad task names with spaces when printing out
+	 * human readable tables of task information.
+	 */
+	static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName ) PRIVILEGED_FUNCTION;
+
+#endif
+
+/*
+ * Called after a Task_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
+									const char * const pcName,
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									TaskHandle_t * const pxCreatedTask,
+									TCB_t *pxNewTCB,
+									const MemoryRegion_t * const xRegions ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/*
+ * Called after a new task has been created and initialised to place the task
+ * under the control of the scheduler.
+ */
+static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB ) PRIVILEGED_FUNCTION;
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	TaskHandle_t xTaskCreateStatic(	TaskFunction_t pxTaskCode,
+									const char * const pcName,
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									StackType_t * const puxStackBuffer,
+									StaticTask_t * const pxTaskBuffer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	TCB_t *pxNewTCB;
+	TaskHandle_t xReturn;
+
+		configASSERT( puxStackBuffer != NULL );
+		configASSERT( pxTaskBuffer != NULL );
+
+		if( ( pxTaskBuffer != NULL ) && ( puxStackBuffer != NULL ) )
+		{
+			/* The memory used for the task's TCB and stack are passed into this
+			function - use them. */
+			pxNewTCB = ( TCB_t * ) pxTaskBuffer; /*lint !e740 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+			pxNewTCB->pxStack = ( StackType_t * ) puxStackBuffer;
+
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created statically in case the task is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+
+			prvInitialiseNewTask( pxTaskCode, pcName, ulStackDepth, pvParameters, uxPriority, &xReturn, pxNewTCB, NULL );
+			prvAddNewTaskToReadyList( pxNewTCB );
+		}
+		else
+		{
+			xReturn = NULL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* SUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( portUSING_MPU_WRAPPERS == 1 )
+
+	BaseType_t xTaskCreateRestricted( const TaskParameters_t * const pxTaskDefinition, TaskHandle_t *pxCreatedTask )
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+
+		configASSERT( pxTaskDefinition->puxStackBuffer );
+
+		if( pxTaskDefinition->puxStackBuffer != NULL )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends
+			on the implementation of the port malloc function and whether or
+			not static allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+			if( pxNewTCB != NULL )
+			{
+				/* Store the stack location in the TCB. */
+				pxNewTCB->pxStack = pxTaskDefinition->puxStackBuffer;
+
+				/* Tasks can be created statically or dynamically, so note
+				this task had a statically allocated stack in case it is
+				later deleted.  The TCB was allocated dynamically. */
+				pxNewTCB->ucStaticallyAllocated = tskSTATICALLY_ALLOCATED_STACK_ONLY;
+
+				prvInitialiseNewTask(	pxTaskDefinition->pvTaskCode,
+										pxTaskDefinition->pcName,
+										( uint32_t ) pxTaskDefinition->usStackDepth,
+										pxTaskDefinition->pvParameters,
+										pxTaskDefinition->uxPriority,
+										pxCreatedTask, pxNewTCB,
+										pxTaskDefinition->xRegions );
+
+				prvAddNewTaskToReadyList( pxNewTCB );
+				xReturn = pdPASS;
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	BaseType_t xTaskCreate(	TaskFunction_t pxTaskCode,
+							const char * const pcName,
+							const uint16_t usStackDepth,
+							void * const pvParameters,
+							UBaseType_t uxPriority,
+							TaskHandle_t * const pxCreatedTask ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	TCB_t *pxNewTCB;
+	BaseType_t xReturn;
+
+		/* If the stack grows down then allocate the stack then the TCB so the stack
+		does not grow into the TCB.  Likewise if the stack grows up then allocate
+		the TCB then the stack. */
+		#if( portSTACK_GROWTH > 0 )
+		{
+			/* Allocate space for the TCB.  Where the memory comes from depends on
+			the implementation of the port malloc function and whether or not static
+			allocation is being used. */
+			pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) );
+
+			if( pxNewTCB != NULL )
+			{
+				/* Allocate space for the stack used by the task being created.
+				The base of the stack memory stored in the TCB so the task can
+				be deleted later if required. */
+				pxNewTCB->pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+				if( pxNewTCB->pxStack == NULL )
+				{
+					/* Could not allocate the stack.  Delete the allocated TCB. */
+					vPortFree( pxNewTCB );
+					pxNewTCB = NULL;
+				}
+			}
+		}
+		#else /* portSTACK_GROWTH */
+		{
+		StackType_t *pxStack;
+
+			/* Allocate space for the stack used by the task being created. */
+			pxStack = ( StackType_t * ) pvPortMalloc( ( ( ( size_t ) usStackDepth ) * sizeof( StackType_t ) ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+			if( pxStack != NULL )
+			{
+				/* Allocate space for the TCB. */
+				pxNewTCB = ( TCB_t * ) pvPortMalloc( sizeof( TCB_t ) ); /*lint !e961 MISRA exception as the casts are only redundant for some paths. */
+
+				if( pxNewTCB != NULL )
+				{
+					/* Store the stack location in the TCB. */
+					pxNewTCB->pxStack = pxStack;
+				}
+				else
+				{
+					/* The stack cannot be used as the TCB was not created.  Free
+					it again. */
+					vPortFree( pxStack );
+				}
+			}
+			else
+			{
+				pxNewTCB = NULL;
+			}
+		}
+		#endif /* portSTACK_GROWTH */
+
+		if( pxNewTCB != NULL )
+		{
+			#if( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE != 0 )
+			{
+				/* Tasks can be created statically or dynamically, so note this
+				task was created dynamically in case it is later deleted. */
+				pxNewTCB->ucStaticallyAllocated = tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB;
+			}
+			#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+			prvInitialiseNewTask( pxTaskCode, pcName, ( uint32_t ) usStackDepth, pvParameters, uxPriority, pxCreatedTask, pxNewTCB, NULL );
+			prvAddNewTaskToReadyList( pxNewTCB );
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewTask( 	TaskFunction_t pxTaskCode,
+									const char * const pcName,
+									const uint32_t ulStackDepth,
+									void * const pvParameters,
+									UBaseType_t uxPriority,
+									TaskHandle_t * const pxCreatedTask,
+									TCB_t *pxNewTCB,
+									const MemoryRegion_t * const xRegions ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+StackType_t *pxTopOfStack;
+UBaseType_t x;
+
+	#if( portUSING_MPU_WRAPPERS == 1 )
+		/* Should the task be created in privileged mode? */
+		BaseType_t xRunPrivileged;
+		if( ( uxPriority & portPRIVILEGE_BIT ) != 0U )
+		{
+			xRunPrivileged = pdTRUE;
+		}
+		else
+		{
+			xRunPrivileged = pdFALSE;
+		}
+		uxPriority &= ~portPRIVILEGE_BIT;
+	#endif /* portUSING_MPU_WRAPPERS == 1 */
+
+	/* Avoid dependency on memset() if it is not required. */
+	#if( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
+	{
+		/* Fill the stack with a known value to assist debugging. */
+		( void ) memset( pxNewTCB->pxStack, ( int ) tskSTACK_FILL_BYTE, ( size_t ) ulStackDepth * sizeof( StackType_t ) );
+	}
+	#endif /* ( ( configCHECK_FOR_STACK_OVERFLOW > 1 ) || ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) ) */
+
+	/* Calculate the top of stack address.  This depends on whether the stack
+	grows from high memory to low (as per the 80x86) or vice versa.
+	portSTACK_GROWTH is used to make the result positive or negative as required
+	by the port. */
+	#if( portSTACK_GROWTH < 0 )
+	{
+		pxTopOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
+		pxTopOfStack = ( StackType_t * ) ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack ) & ( ~( ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) ) ); /*lint !e923 MISRA exception.  Avoiding casts between pointers and integers is not practical.  Size differences accounted for using portPOINTER_SIZE_TYPE type. */
+
+		/* Check the alignment of the calculated top of stack is correct. */
+		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxTopOfStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+	}
+	#else /* portSTACK_GROWTH */
+	{
+		pxTopOfStack = pxNewTCB->pxStack;
+
+		/* Check the alignment of the stack buffer is correct. */
+		configASSERT( ( ( ( portPOINTER_SIZE_TYPE ) pxNewTCB->pxStack & ( portPOINTER_SIZE_TYPE ) portBYTE_ALIGNMENT_MASK ) == 0UL ) );
+
+		/* The other extreme of the stack space is required if stack checking is
+		performed. */
+		pxNewTCB->pxEndOfStack = pxNewTCB->pxStack + ( ulStackDepth - ( uint32_t ) 1 );
+	}
+	#endif /* portSTACK_GROWTH */
+
+	/* Store the task name in the TCB. */
+	for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+	{
+		pxNewTCB->pcTaskName[ x ] = pcName[ x ];
+
+		/* Don't copy all configMAX_TASK_NAME_LEN if the string is shorter than
+		configMAX_TASK_NAME_LEN characters just in case the memory after the
+		string is not accessible (extremely unlikely). */
+		if( pcName[ x ] == 0x00 )
+		{
+			break;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	/* Ensure the name string is terminated in the case that the string length
+	was greater or equal to configMAX_TASK_NAME_LEN. */
+	pxNewTCB->pcTaskName[ configMAX_TASK_NAME_LEN - 1 ] = '\0';
+
+	/* This is used as an array index so must ensure it's not too large.  First
+	remove the privilege bit if one is present. */
+	if( uxPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+	{
+		uxPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	pxNewTCB->uxPriority = uxPriority;
+	#if ( configUSE_MUTEXES == 1 )
+	{
+		pxNewTCB->uxBasePriority = uxPriority;
+		pxNewTCB->uxMutexesHeld = 0;
+	}
+	#endif /* configUSE_MUTEXES */
+
+	vListInitialiseItem( &( pxNewTCB->xStateListItem ) );
+	vListInitialiseItem( &( pxNewTCB->xEventListItem ) );
+
+	/* Set the pxNewTCB as a link back from the ListItem_t.  This is so we can get
+	back to	the containing TCB from a generic item in a list. */
+	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xStateListItem ), pxNewTCB );
+
+	/* Event lists are always in priority order. */
+	listSET_LIST_ITEM_VALUE( &( pxNewTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+	listSET_LIST_ITEM_OWNER( &( pxNewTCB->xEventListItem ), pxNewTCB );
+
+	#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+	{
+		pxNewTCB->uxCriticalNesting = ( UBaseType_t ) 0U;
+	}
+	#endif /* portCRITICAL_NESTING_IN_TCB */
+
+	#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+	{
+		pxNewTCB->pxTaskTag = NULL;
+	}
+	#endif /* configUSE_APPLICATION_TASK_TAG */
+
+	#if ( configGENERATE_RUN_TIME_STATS == 1 )
+	{
+		pxNewTCB->ulRunTimeCounter = 0UL;
+	}
+	#endif /* configGENERATE_RUN_TIME_STATS */
+
+	#if ( portUSING_MPU_WRAPPERS == 1 )
+	{
+		vPortStoreTaskMPUSettings( &( pxNewTCB->xMPUSettings ), xRegions, pxNewTCB->pxStack, ulStackDepth );
+	}
+	#else
+	{
+		/* Avoid compiler warning about unreferenced parameter. */
+		( void ) xRegions;
+	}
+	#endif
+
+	#if( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+	{
+		for( x = 0; x < ( UBaseType_t ) configNUM_THREAD_LOCAL_STORAGE_POINTERS; x++ )
+		{
+			pxNewTCB->pvThreadLocalStoragePointers[ x ] = NULL;
+		}
+	}
+	#endif
+
+	#if ( configUSE_TASK_NOTIFICATIONS == 1 )
+	{
+		pxNewTCB->ulNotifiedValue = 0;
+		pxNewTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+	}
+	#endif
+
+	#if ( configUSE_NEWLIB_REENTRANT == 1 )
+	{
+		/* Initialise this task's Newlib reent structure. */
+		_REENT_INIT_PTR( ( &( pxNewTCB->xNewLib_reent ) ) );
+	}
+	#endif
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+	{
+		pxNewTCB->ucDelayAborted = pdFALSE;
+	}
+	#endif
+
+	/* Initialize the TCB stack to look as if the task was already running,
+	but had been interrupted by the scheduler.  The return address is set
+	to the start of the task function. Once the stack has been initialised
+	the	top of stack variable is updated. */
+	#if( portUSING_MPU_WRAPPERS == 1 )
+	{
+		pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters, xRunPrivileged );
+	}
+	#else /* portUSING_MPU_WRAPPERS */
+	{
+		pxNewTCB->pxTopOfStack = pxPortInitialiseStack( pxTopOfStack, pxTaskCode, pvParameters );
+	}
+	#endif /* portUSING_MPU_WRAPPERS */
+
+	if( ( void * ) pxCreatedTask != NULL )
+	{
+		/* Pass the handle out in an anonymous way.  The handle can be used to
+		change the created task's priority, delete the created task, etc.*/
+		*pxCreatedTask = ( TaskHandle_t ) pxNewTCB;
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvAddNewTaskToReadyList( TCB_t *pxNewTCB )
+{
+	/* Ensure interrupts don't access the task lists while the lists are being
+	updated. */
+	taskENTER_CRITICAL();
+	{
+		uxCurrentNumberOfTasks++;
+		if( pxCurrentTCB == NULL )
+		{
+			/* There are no other tasks, or all the other tasks are in
+			the suspended state - make this the current task. */
+			pxCurrentTCB = pxNewTCB;
+
+			if( uxCurrentNumberOfTasks == ( UBaseType_t ) 1 )
+			{
+				/* This is the first task to be created so do the preliminary
+				initialisation required.  We will not recover if this call
+				fails, but we will report the failure. */
+				prvInitialiseTaskLists();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			/* If the scheduler is not already running, make this task the
+			current task if it is the highest priority task to be created
+			so far. */
+			if( xSchedulerRunning == pdFALSE )
+			{
+				if( pxCurrentTCB->uxPriority <= pxNewTCB->uxPriority )
+				{
+					pxCurrentTCB = pxNewTCB;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		uxTaskNumber++;
+
+		#if ( configUSE_TRACE_FACILITY == 1 )
+		{
+			/* Add a counter into the TCB for tracing only. */
+			pxNewTCB->uxTCBNumber = uxTaskNumber;
+		}
+		#endif /* configUSE_TRACE_FACILITY */
+		traceTASK_CREATE( pxNewTCB );
+
+		prvAddTaskToReadyList( pxNewTCB );
+
+		portSETUP_TCB( pxNewTCB );
+	}
+	taskEXIT_CRITICAL();
+
+	if( xSchedulerRunning != pdFALSE )
+	{
+		/* If the created task is of a higher priority than the current task
+		then it should run now. */
+		if( pxCurrentTCB->uxPriority < pxNewTCB->uxPriority )
+		{
+			taskYIELD_IF_USING_PREEMPTION();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	void vTaskDelete( TaskHandle_t xTaskToDelete )
+	{
+	TCB_t *pxTCB;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the calling task that is
+			being deleted. */
+			pxTCB = prvGetTCBFromHandle( xTaskToDelete );
+
+			/* Remove task from the ready list. */
+			if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+			{
+				taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Is the task waiting on an event also? */
+			if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+			{
+				( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Increment the uxTaskNumber also so kernel aware debuggers can
+			detect that the task lists need re-generating.  This is done before
+			portPRE_TASK_DELETE_HOOK() as in the Windows port that macro will
+			not return. */
+			uxTaskNumber++;
+
+			if( pxTCB == pxCurrentTCB )
+			{
+				/* A task is deleting itself.  This cannot complete within the
+				task itself, as a context switch to another task is required.
+				Place the task in the termination list.  The idle task will
+				check the termination list and free up any memory allocated by
+				the scheduler for the TCB and stack of the deleted task. */
+				vListInsertEnd( &xTasksWaitingTermination, &( pxTCB->xStateListItem ) );
+
+				/* Increment the ucTasksDeleted variable so the idle task knows
+				there is a task that has been deleted and that it should therefore
+				check the xTasksWaitingTermination list. */
+				++uxDeletedTasksWaitingCleanUp;
+
+				/* The pre-delete hook is primarily for the Windows simulator,
+				in which Windows specific clean up operations are performed,
+				after which it is not possible to yield away from this task -
+				hence xYieldPending is used to latch that a context switch is
+				required. */
+				portPRE_TASK_DELETE_HOOK( pxTCB, &xYieldPending );
+			}
+			else
+			{
+				--uxCurrentNumberOfTasks;
+				prvDeleteTCB( pxTCB );
+
+				/* Reset the next expected unblock time in case it referred to
+				the task that has just been deleted. */
+				prvResetNextTaskUnblockTime();
+			}
+
+			traceTASK_DELETE( pxTCB );
+		}
+		taskEXIT_CRITICAL();
+
+		/* Force a reschedule if it is the currently running task that has just
+		been deleted. */
+		if( xSchedulerRunning != pdFALSE )
+		{
+			if( pxTCB == pxCurrentTCB )
+			{
+				configASSERT( uxSchedulerSuspended == 0 );
+				portYIELD_WITHIN_API();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelayUntil == 1 )
+
+	void vTaskDelayUntil( TickType_t * const pxPreviousWakeTime, const TickType_t xTimeIncrement )
+	{
+	TickType_t xTimeToWake;
+	BaseType_t xAlreadyYielded, xShouldDelay = pdFALSE;
+
+		configASSERT( pxPreviousWakeTime );
+		configASSERT( ( xTimeIncrement > 0U ) );
+		configASSERT( uxSchedulerSuspended == 0 );
+
+		vTaskSuspendAll();
+		{
+			/* Minor optimisation.  The tick count cannot change in this
+			block. */
+			const TickType_t xConstTickCount = xTickCount;
+
+			/* Generate the tick time at which the task wants to wake. */
+			xTimeToWake = *pxPreviousWakeTime + xTimeIncrement;
+
+			if( xConstTickCount < *pxPreviousWakeTime )
+			{
+				/* The tick count has overflowed since this function was
+				lasted called.  In this case the only time we should ever
+				actually delay is if the wake time has also	overflowed,
+				and the wake time is greater than the tick time.  When this
+				is the case it is as if neither time had overflowed. */
+				if( ( xTimeToWake < *pxPreviousWakeTime ) && ( xTimeToWake > xConstTickCount ) )
+				{
+					xShouldDelay = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				/* The tick time has not overflowed.  In this case we will
+				delay if either the wake time has overflowed, and/or the
+				tick time is less than the wake time. */
+				if( ( xTimeToWake < *pxPreviousWakeTime ) || ( xTimeToWake > xConstTickCount ) )
+				{
+					xShouldDelay = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+
+			/* Update the wake time ready for the next call. */
+			*pxPreviousWakeTime = xTimeToWake;
+
+			if( xShouldDelay != pdFALSE )
+			{
+				traceTASK_DELAY_UNTIL( xTimeToWake );
+
+				/* prvAddCurrentTaskToDelayedList() needs the block time, not
+				the time to wake, so subtract the current tick count. */
+				prvAddCurrentTaskToDelayedList( xTimeToWake - xConstTickCount, pdFALSE );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		xAlreadyYielded = xTaskResumeAll();
+
+		/* Force a reschedule if xTaskResumeAll has not already done so, we may
+		have put ourselves to sleep. */
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelayUntil */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelay == 1 )
+
+	void vTaskDelay( const TickType_t xTicksToDelay )
+	{
+	BaseType_t xAlreadyYielded = pdFALSE;
+
+		/* A delay time of zero just forces a reschedule. */
+		if( xTicksToDelay > ( TickType_t ) 0U )
+		{
+			configASSERT( uxSchedulerSuspended == 0 );
+			vTaskSuspendAll();
+			{
+				traceTASK_DELAY();
+
+				/* A task that is removed from the event list while the
+				scheduler is suspended will not get placed in the ready
+				list or removed from the blocked list until the scheduler
+				is resumed.
+
+				This task cannot be in an event list as it is the currently
+				executing task. */
+				prvAddCurrentTaskToDelayedList( xTicksToDelay, pdFALSE );
+			}
+			xAlreadyYielded = xTaskResumeAll();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* Force a reschedule if xTaskResumeAll has not already done so, we may
+		have put ourselves to sleep. */
+		if( xAlreadyYielded == pdFALSE )
+		{
+			portYIELD_WITHIN_API();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskDelay */
+/*-----------------------------------------------------------*/
+
+#if( ( INCLUDE_eTaskGetState == 1 ) || ( configUSE_TRACE_FACILITY == 1 ) )
+
+	eTaskState eTaskGetState( TaskHandle_t xTask )
+	{
+	eTaskState eReturn;
+	List_t *pxStateList;
+	const TCB_t * const pxTCB = ( TCB_t * ) xTask;
+
+		configASSERT( pxTCB );
+
+		if( pxTCB == pxCurrentTCB )
+		{
+			/* The task calling this function is querying its own state. */
+			eReturn = eRunning;
+		}
+		else
+		{
+			taskENTER_CRITICAL();
+			{
+				pxStateList = ( List_t * ) listLIST_ITEM_CONTAINER( &( pxTCB->xStateListItem ) );
+			}
+			taskEXIT_CRITICAL();
+
+			if( ( pxStateList == pxDelayedTaskList ) || ( pxStateList == pxOverflowDelayedTaskList ) )
+			{
+				/* The task being queried is referenced from one of the Blocked
+				lists. */
+				eReturn = eBlocked;
+			}
+
+			#if ( INCLUDE_vTaskSuspend == 1 )
+				else if( pxStateList == &xSuspendedTaskList )
+				{
+					/* The task being queried is referenced from the suspended
+					list.  Is it genuinely suspended or is it block
+					indefinitely? */
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL )
+					{
+						eReturn = eSuspended;
+					}
+					else
+					{
+						eReturn = eBlocked;
+					}
+				}
+			#endif
+
+			#if ( INCLUDE_vTaskDelete == 1 )
+				else if( ( pxStateList == &xTasksWaitingTermination ) || ( pxStateList == NULL ) )
+				{
+					/* The task being queried is referenced from the deleted
+					tasks list, or it is not referenced from any lists at
+					all. */
+					eReturn = eDeleted;
+				}
+			#endif
+
+			else /*lint !e525 Negative indentation is intended to make use of pre-processor clearer. */
+			{
+				/* If the task is not in any other state, it must be in the
+				Ready (including pending ready) state. */
+				eReturn = eReady;
+			}
+		}
+
+		return eReturn;
+	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_eTaskGetState */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+	UBaseType_t uxTaskPriorityGet( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	UBaseType_t uxReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the priority of the that
+			called uxTaskPriorityGet() that is being queried. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+			uxReturn = pxTCB->uxPriority;
+		}
+		taskEXIT_CRITICAL();
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskPriorityGet == 1 )
+
+	UBaseType_t uxTaskPriorityGetFromISR( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	UBaseType_t uxReturn, uxSavedInterruptState;
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		uxSavedInterruptState = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			/* If null is passed in here then it is the priority of the calling
+			task that is being queried. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+			uxReturn = pxTCB->uxPriority;
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptState );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskPriorityGet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskPrioritySet == 1 )
+
+	void vTaskPrioritySet( TaskHandle_t xTask, UBaseType_t uxNewPriority )
+	{
+	TCB_t *pxTCB;
+	UBaseType_t uxCurrentBasePriority, uxPriorityUsedOnEntry;
+	BaseType_t xYieldRequired = pdFALSE;
+
+		configASSERT( ( uxNewPriority < configMAX_PRIORITIES ) );
+
+		/* Ensure the new priority is valid. */
+		if( uxNewPriority >= ( UBaseType_t ) configMAX_PRIORITIES )
+		{
+			uxNewPriority = ( UBaseType_t ) configMAX_PRIORITIES - ( UBaseType_t ) 1U;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the priority of the calling
+			task that is being changed. */
+			pxTCB = prvGetTCBFromHandle( xTask );
+
+			traceTASK_PRIORITY_SET( pxTCB, uxNewPriority );
+
+			#if ( configUSE_MUTEXES == 1 )
+			{
+				uxCurrentBasePriority = pxTCB->uxBasePriority;
+			}
+			#else
+			{
+				uxCurrentBasePriority = pxTCB->uxPriority;
+			}
+			#endif
+
+			if( uxCurrentBasePriority != uxNewPriority )
+			{
+				/* The priority change may have readied a task of higher
+				priority than the calling task. */
+				if( uxNewPriority > uxCurrentBasePriority )
+				{
+					if( pxTCB != pxCurrentTCB )
+					{
+						/* The priority of a task other than the currently
+						running task is being raised.  Is the priority being
+						raised above that of the running task? */
+						if( uxNewPriority >= pxCurrentTCB->uxPriority )
+						{
+							xYieldRequired = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						/* The priority of the running task is being raised,
+						but the running task must already be the highest
+						priority task able to run so no yield is required. */
+					}
+				}
+				else if( pxTCB == pxCurrentTCB )
+				{
+					/* Setting the priority of the running task down means
+					there may now be another task of higher priority that
+					is ready to execute. */
+					xYieldRequired = pdTRUE;
+				}
+				else
+				{
+					/* Setting the priority of any other task down does not
+					require a yield as the running task must be above the
+					new priority of the task being modified. */
+				}
+
+				/* Remember the ready list the task might be referenced from
+				before its uxPriority member is changed so the
+				taskRESET_READY_PRIORITY() macro can function correctly. */
+				uxPriorityUsedOnEntry = pxTCB->uxPriority;
+
+				#if ( configUSE_MUTEXES == 1 )
+				{
+					/* Only change the priority being used if the task is not
+					currently using an inherited priority. */
+					if( pxTCB->uxBasePriority == pxTCB->uxPriority )
+					{
+						pxTCB->uxPriority = uxNewPriority;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* The base priority gets set whatever. */
+					pxTCB->uxBasePriority = uxNewPriority;
+				}
+				#else
+				{
+					pxTCB->uxPriority = uxNewPriority;
+				}
+				#endif
+
+				/* Only reset the event list item value if the value is not
+				being used for anything else. */
+				if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+				{
+					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) uxNewPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* If the task is in the blocked or suspended list we need do
+				nothing more than change it's priority variable. However, if
+				the task is in a ready list it needs to be removed and placed
+				in the list appropriate to its new priority. */
+				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ uxPriorityUsedOnEntry ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+				{
+					/* The task is currently in its ready list - remove before adding
+					it to it's new ready list.  As we are in a critical section we
+					can do this even if the scheduler is suspended. */
+					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						/* It is known that the task is in its ready list so
+						there is no need to check again and the port level
+						reset macro can be called directly. */
+						portRESET_READY_PRIORITY( uxPriorityUsedOnEntry, uxTopReadyPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				if( xYieldRequired != pdFALSE )
+				{
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* Remove compiler warning about unused variables when the port
+				optimised task selection is not being used. */
+				( void ) uxPriorityUsedOnEntry;
+			}
+		}
+		taskEXIT_CRITICAL();
+	}
+
+#endif /* INCLUDE_vTaskPrioritySet */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	void vTaskSuspend( TaskHandle_t xTaskToSuspend )
+	{
+	TCB_t *pxTCB;
+
+		taskENTER_CRITICAL();
+		{
+			/* If null is passed in here then it is the running task that is
+			being suspended. */
+			pxTCB = prvGetTCBFromHandle( xTaskToSuspend );
+
+			traceTASK_SUSPEND( pxTCB );
+
+			/* Remove task from the ready/delayed list and place in the
+			suspended list. */
+			if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+			{
+				taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Is the task waiting on an event also? */
+			if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+			{
+				( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			vListInsertEnd( &xSuspendedTaskList, &( pxTCB->xStateListItem ) );
+		}
+		taskEXIT_CRITICAL();
+
+		if( xSchedulerRunning != pdFALSE )
+		{
+			/* Reset the next expected unblock time in case it referred to the
+			task that is now in the Suspended state. */
+			taskENTER_CRITICAL();
+			{
+				prvResetNextTaskUnblockTime();
+			}
+			taskEXIT_CRITICAL();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		if( pxTCB == pxCurrentTCB )
+		{
+			if( xSchedulerRunning != pdFALSE )
+			{
+				/* The current task has just been suspended. */
+				configASSERT( uxSchedulerSuspended == 0 );
+				portYIELD_WITHIN_API();
+			}
+			else
+			{
+				/* The scheduler is not running, but the task that was pointed
+				to by pxCurrentTCB has just been suspended and pxCurrentTCB
+				must be adjusted to point to a different task. */
+				if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == uxCurrentNumberOfTasks )
+				{
+					/* No other tasks are ready, so set pxCurrentTCB back to
+					NULL so when the next task is created pxCurrentTCB will
+					be set to point to it no matter what its relative priority
+					is. */
+					pxCurrentTCB = NULL;
+				}
+				else
+				{
+					vTaskSwitchContext();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	static BaseType_t prvTaskIsTaskSuspended( const TaskHandle_t xTask )
+	{
+	BaseType_t xReturn = pdFALSE;
+	const TCB_t * const pxTCB = ( TCB_t * ) xTask;
+
+		/* Accesses xPendingReadyList so must be called from a critical
+		section. */
+
+		/* It does not make sense to check if the calling task is suspended. */
+		configASSERT( xTask );
+
+		/* Is the task being resumed actually in the suspended list? */
+		if( listIS_CONTAINED_WITHIN( &xSuspendedTaskList, &( pxTCB->xStateListItem ) ) != pdFALSE )
+		{
+			/* Has the task already been resumed from within an ISR? */
+			if( listIS_CONTAINED_WITHIN( &xPendingReadyList, &( pxTCB->xEventListItem ) ) == pdFALSE )
+			{
+				/* Is it in the suspended list because it is in the	Suspended
+				state, or because is is blocked with no timeout? */
+				if( listIS_CONTAINED_WITHIN( NULL, &( pxTCB->xEventListItem ) ) != pdFALSE )
+				{
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	} /*lint !e818 xTask cannot be a pointer to const because it is a typedef. */
+
+#endif /* INCLUDE_vTaskSuspend */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskSuspend == 1 )
+
+	void vTaskResume( TaskHandle_t xTaskToResume )
+	{
+	TCB_t * const pxTCB = ( TCB_t * ) xTaskToResume;
+
+		/* It does not make sense to resume the calling task. */
+		configASSERT( xTaskToResume );
+
+		/* The parameter cannot be NULL as it is impossible to resume the
+		currently executing task. */
+		if( ( pxTCB != NULL ) && ( pxTCB != pxCurrentTCB ) )
+		{
+			taskENTER_CRITICAL();
+			{
+				if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+				{
+					traceTASK_RESUME( pxTCB );
+
+					/* As we are in a critical section we can access the ready
+					lists even if the scheduler is suspended. */
+					( void ) uxListRemove(  &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+
+					/* We may have just resumed a higher priority task. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						/* This yield may not cause the task just resumed to run,
+						but will leave the lists in the correct state for the
+						next yield. */
+						taskYIELD_IF_USING_PREEMPTION();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			taskEXIT_CRITICAL();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* INCLUDE_vTaskSuspend */
+
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) )
+
+	BaseType_t xTaskResumeFromISR( TaskHandle_t xTaskToResume )
+	{
+	BaseType_t xYieldRequired = pdFALSE;
+	TCB_t * const pxTCB = ( TCB_t * ) xTaskToResume;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToResume );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			if( prvTaskIsTaskSuspended( pxTCB ) != pdFALSE )
+			{
+				traceTASK_RESUME_FROM_ISR( pxTCB );
+
+				/* Check the ready lists can be accessed. */
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					/* Ready lists can be accessed so move the task from the
+					suspended list to the ready list directly. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						xYieldRequired = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed or ready lists cannot be accessed so the task
+					is held in the pending ready list until the scheduler is
+					unsuspended. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xYieldRequired;
+	}
+
+#endif /* ( ( INCLUDE_xTaskResumeFromISR == 1 ) && ( INCLUDE_vTaskSuspend == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+void vTaskStartScheduler( void )
+{
+BaseType_t xReturn;
+
+	/* Add the idle task at the lowest priority. */
+	#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	{
+		StaticTask_t *pxIdleTaskTCBBuffer = NULL;
+		StackType_t *pxIdleTaskStackBuffer = NULL;
+		uint32_t ulIdleTaskStackSize;
+
+		/* The Idle task is created using user provided RAM - obtain the
+		address of the RAM then create the idle task. */
+		vApplicationGetIdleTaskMemory( &pxIdleTaskTCBBuffer, &pxIdleTaskStackBuffer, &ulIdleTaskStackSize );
+		xIdleTaskHandle = xTaskCreateStatic(	prvIdleTask,
+												"IDLE",
+												ulIdleTaskStackSize,
+												( void * ) NULL,
+												( tskIDLE_PRIORITY | portPRIVILEGE_BIT ),
+												pxIdleTaskStackBuffer,
+												pxIdleTaskTCBBuffer ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+
+		if( xIdleTaskHandle != NULL )
+		{
+			xReturn = pdPASS;
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+	}
+	#else
+	{
+		/* The Idle task is being created using dynamically allocated RAM. */
+		xReturn = xTaskCreate(	prvIdleTask,
+								"IDLE", configMINIMAL_STACK_SIZE,
+								( void * ) NULL,
+								( tskIDLE_PRIORITY | portPRIVILEGE_BIT ),
+								&xIdleTaskHandle ); /*lint !e961 MISRA exception, justified as it is not a redundant explicit cast to all supported compilers. */
+	}
+	#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+	#if ( configUSE_TIMERS == 1 )
+	{
+		if( xReturn == pdPASS )
+		{
+			xReturn = xTimerCreateTimerTask();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif /* configUSE_TIMERS */
+
+	if( xReturn == pdPASS )
+	{
+		/* Interrupts are turned off here, to ensure a tick does not occur
+		before or during the call to xPortStartScheduler().  The stacks of
+		the created tasks contain a status word with interrupts switched on
+		so interrupts will automatically get re-enabled when the first task
+		starts to run. */
+		portDISABLE_INTERRUPTS();
+
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			/* Switch Newlib's _impure_ptr variable to point to the _reent
+			structure specific to the task that will run first. */
+			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+
+		xNextTaskUnblockTime = portMAX_DELAY;
+		xSchedulerRunning = pdTRUE;
+		xTickCount = ( TickType_t ) 0U;
+
+		/* If configGENERATE_RUN_TIME_STATS is defined then the following
+		macro must be defined to configure the timer/counter used to generate
+		the run time counter time base. */
+		portCONFIGURE_TIMER_FOR_RUN_TIME_STATS();
+
+		/* Setting up the timer tick is hardware specific and thus in the
+		portable interface. */
+		if( xPortStartScheduler() != pdFALSE )
+		{
+			/* Should not reach here as if the scheduler is running the
+			function will not return. */
+		}
+		else
+		{
+			/* Should only reach here if a task calls xTaskEndScheduler(). */
+		}
+	}
+	else
+	{
+		/* This line will only be reached if the kernel could not be started,
+		because there was not enough FreeRTOS heap to create the idle task
+		or the timer task. */
+		configASSERT( xReturn != errCOULD_NOT_ALLOCATE_REQUIRED_MEMORY );
+	}
+
+	/* Prevent compiler warnings if INCLUDE_xTaskGetIdleTaskHandle is set to 0,
+	meaning xIdleTaskHandle is not used anywhere else. */
+	( void ) xIdleTaskHandle;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskEndScheduler( void )
+{
+	/* Stop the scheduler interrupts and call the portable scheduler end
+	routine so the original ISRs can be restored if necessary.  The port
+	layer must ensure interrupts enable	bit is left in the correct state. */
+	portDISABLE_INTERRUPTS();
+	xSchedulerRunning = pdFALSE;
+	vPortEndScheduler();
+}
+/*----------------------------------------------------------*/
+
+void vTaskSuspendAll( void )
+{
+	/* A critical section is not required as the variable is of type
+	BaseType_t.  Please read Richard Barry's reply in the following link to a
+	post in the FreeRTOS support forum before reporting this as a bug! -
+	http://goo.gl/wu4acr */
+	++uxSchedulerSuspended;
+}
+/*----------------------------------------------------------*/
+
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	static TickType_t prvGetExpectedIdleTime( void )
+	{
+	TickType_t xReturn;
+	UBaseType_t uxHigherPriorityReadyTasks = pdFALSE;
+
+		/* uxHigherPriorityReadyTasks takes care of the case where
+		configUSE_PREEMPTION is 0, so there may be tasks above the idle priority
+		task that are in the Ready state, even though the idle task is
+		running. */
+		#if( configUSE_PORT_OPTIMISED_TASK_SELECTION == 0 )
+		{
+			if( uxTopReadyPriority > tskIDLE_PRIORITY )
+			{
+				uxHigherPriorityReadyTasks = pdTRUE;
+			}
+		}
+		#else
+		{
+			const UBaseType_t uxLeastSignificantBit = ( UBaseType_t ) 0x01;
+
+			/* When port optimised task selection is used the uxTopReadyPriority
+			variable is used as a bit map.  If bits other than the least
+			significant bit are set then there are tasks that have a priority
+			above the idle priority that are in the Ready state.  This takes
+			care of the case where the co-operative scheduler is in use. */
+			if( uxTopReadyPriority > uxLeastSignificantBit )
+			{
+				uxHigherPriorityReadyTasks = pdTRUE;
+			}
+		}
+		#endif
+
+		if( pxCurrentTCB->uxPriority > tskIDLE_PRIORITY )
+		{
+			xReturn = 0;
+		}
+		else if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > 1 )
+		{
+			/* There are other idle priority tasks in the ready state.  If
+			time slicing is used then the very next tick interrupt must be
+			processed. */
+			xReturn = 0;
+		}
+		else if( uxHigherPriorityReadyTasks != pdFALSE )
+		{
+			/* There are tasks in the Ready state that have a priority above the
+			idle priority.  This path can only be reached if
+			configUSE_PREEMPTION is 0. */
+			xReturn = 0;
+		}
+		else
+		{
+			xReturn = xNextTaskUnblockTime - xTickCount;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskResumeAll( void )
+{
+TCB_t *pxTCB = NULL;
+BaseType_t xAlreadyYielded = pdFALSE;
+
+	/* If uxSchedulerSuspended is zero then this function does not match a
+	previous call to vTaskSuspendAll(). */
+	configASSERT( uxSchedulerSuspended );
+
+	/* It is possible that an ISR caused a task to be removed from an event
+	list while the scheduler was suspended.  If this was the case then the
+	removed task will have been added to the xPendingReadyList.  Once the
+	scheduler has been resumed it is safe to move all the pending ready
+	tasks from this list into their appropriate ready list. */
+	taskENTER_CRITICAL();
+	{
+		--uxSchedulerSuspended;
+
+		if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+		{
+			if( uxCurrentNumberOfTasks > ( UBaseType_t ) 0U )
+			{
+				/* Move any readied tasks from the pending list into the
+				appropriate ready list. */
+				while( listLIST_IS_EMPTY( &xPendingReadyList ) == pdFALSE )
+				{
+					pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xPendingReadyList ) );
+					( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+
+					/* If the moved task has a priority higher than the current
+					task then a yield must be performed. */
+					if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+					{
+						xYieldPending = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( pxTCB != NULL )
+				{
+					/* A task was unblocked while the scheduler was suspended,
+					which may have prevented the next unblock time from being
+					re-calculated, in which case re-calculate it now.  Mainly
+					important for low power tickless implementations, where
+					this can prevent an unnecessary exit from low power
+					state. */
+					prvResetNextTaskUnblockTime();
+				}
+
+				/* If any ticks occurred while the scheduler was suspended then
+				they should be processed now.  This ensures the tick count does
+				not	slip, and that any delayed tasks are resumed at the correct
+				time. */
+				{
+					UBaseType_t uxPendedCounts = uxPendedTicks; /* Non-volatile copy. */
+
+					if( uxPendedCounts > ( UBaseType_t ) 0U )
+					{
+						do
+						{
+							if( xTaskIncrementTick() != pdFALSE )
+							{
+								xYieldPending = pdTRUE;
+							}
+							else
+							{
+								mtCOVERAGE_TEST_MARKER();
+							}
+							--uxPendedCounts;
+						} while( uxPendedCounts > ( UBaseType_t ) 0U );
+
+						uxPendedTicks = 0;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( xYieldPending != pdFALSE )
+				{
+					#if( configUSE_PREEMPTION != 0 )
+					{
+						xAlreadyYielded = pdTRUE;
+					}
+					#endif
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xAlreadyYielded;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCount( void )
+{
+TickType_t xTicks;
+
+	/* Critical section required if running on a 16 bit processor. */
+	portTICK_TYPE_ENTER_CRITICAL();
+	{
+		xTicks = xTickCount;
+	}
+	portTICK_TYPE_EXIT_CRITICAL();
+
+	return xTicks;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTaskGetTickCountFromISR( void )
+{
+TickType_t xReturn;
+UBaseType_t uxSavedInterruptStatus;
+
+	/* RTOS ports that support interrupt nesting have the concept of a maximum
+	system call (or maximum API call) interrupt priority.  Interrupts that are
+	above the maximum system call priority are kept permanently enabled, even
+	when the RTOS kernel is in a critical section, but cannot make any calls to
+	FreeRTOS API functions.  If configASSERT() is defined in FreeRTOSConfig.h
+	then portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+	failure if a FreeRTOS API function is called from an interrupt that has been
+	assigned a priority above the configured maximum system call priority.
+	Only FreeRTOS functions that end in FromISR can be called from interrupts
+	that have been assigned a priority at or (logically) below the maximum
+	system call	interrupt priority.  FreeRTOS maintains a separate interrupt
+	safe API to ensure interrupt entry is as fast and as simple as possible.
+	More information (albeit Cortex-M specific) is provided on the following
+	link: http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+	portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+	uxSavedInterruptStatus = portTICK_TYPE_SET_INTERRUPT_MASK_FROM_ISR();
+	{
+		xReturn = xTickCount;
+	}
+	portTICK_TYPE_CLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+UBaseType_t uxTaskGetNumberOfTasks( void )
+{
+	/* A critical section is not required because the variables are of type
+	BaseType_t. */
+	return uxCurrentNumberOfTasks;
+}
+/*-----------------------------------------------------------*/
+
+char *pcTaskGetName( TaskHandle_t xTaskToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+TCB_t *pxTCB;
+
+	/* If null is passed in here then the name of the calling task is being
+	queried. */
+	pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+	configASSERT( pxTCB );
+	return &( pxTCB->pcTaskName[ 0 ] );
+}
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	static TCB_t *prvSearchForNameWithinSingleList( List_t *pxList, const char pcNameToQuery[] )
+	{
+	TCB_t *pxNextTCB, *pxFirstTCB, *pxReturn = NULL;
+	UBaseType_t x;
+	char cNextChar;
+
+		/* This function is called with the scheduler suspended. */
+
+		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+		{
+			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );
+
+			do
+			{
+				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );
+
+				/* Check each character in the name looking for a match or
+				mismatch. */
+				for( x = ( UBaseType_t ) 0; x < ( UBaseType_t ) configMAX_TASK_NAME_LEN; x++ )
+				{
+					cNextChar = pxNextTCB->pcTaskName[ x ];
+
+					if( cNextChar != pcNameToQuery[ x ] )
+					{
+						/* Characters didn't match. */
+						break;
+					}
+					else if( cNextChar == 0x00 )
+					{
+						/* Both strings terminated, a match must have been
+						found. */
+						pxReturn = pxNextTCB;
+						break;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+
+				if( pxReturn != NULL )
+				{
+					/* The handle has been found. */
+					break;
+				}
+
+			} while( pxNextTCB != pxFirstTCB );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return pxReturn;
+	}
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetHandle == 1 )
+
+	TaskHandle_t xTaskGetHandle( const char *pcNameToQuery ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	UBaseType_t uxQueue = configMAX_PRIORITIES;
+	TCB_t* pxTCB;
+
+		/* Task names will be truncated to configMAX_TASK_NAME_LEN - 1 bytes. */
+		configASSERT( strlen( pcNameToQuery ) < configMAX_TASK_NAME_LEN );
+
+		vTaskSuspendAll();
+		{
+			/* Search the ready lists. */
+			do
+			{
+				uxQueue--;
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) &( pxReadyTasksLists[ uxQueue ] ), pcNameToQuery );
+
+				if( pxTCB != NULL )
+				{
+					/* Found the handle. */
+					break;
+				}
+
+			} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+			/* Search the delayed lists. */
+			if( pxTCB == NULL )
+			{
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxDelayedTaskList, pcNameToQuery );
+			}
+
+			if( pxTCB == NULL )
+			{
+				pxTCB = prvSearchForNameWithinSingleList( ( List_t * ) pxOverflowDelayedTaskList, pcNameToQuery );
+			}
+
+			#if ( INCLUDE_vTaskSuspend == 1 )
+			{
+				if( pxTCB == NULL )
+				{
+					/* Search the suspended list. */
+					pxTCB = prvSearchForNameWithinSingleList( &xSuspendedTaskList, pcNameToQuery );
+				}
+			}
+			#endif
+
+			#if( INCLUDE_vTaskDelete == 1 )
+			{
+				if( pxTCB == NULL )
+				{
+					/* Search the deleted list. */
+					pxTCB = prvSearchForNameWithinSingleList( &xTasksWaitingTermination, pcNameToQuery );
+				}
+			}
+			#endif
+		}
+		( void ) xTaskResumeAll();
+
+		return ( TaskHandle_t ) pxTCB;
+	}
+
+#endif /* INCLUDE_xTaskGetHandle */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTaskGetSystemState( TaskStatus_t * const pxTaskStatusArray, const UBaseType_t uxArraySize, uint32_t * const pulTotalRunTime )
+	{
+	UBaseType_t uxTask = 0, uxQueue = configMAX_PRIORITIES;
+
+		vTaskSuspendAll();
+		{
+			/* Is there a space in the array for each task in the system? */
+			if( uxArraySize >= uxCurrentNumberOfTasks )
+			{
+				/* Fill in an TaskStatus_t structure with information on each
+				task in the Ready state. */
+				do
+				{
+					uxQueue--;
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &( pxReadyTasksLists[ uxQueue ] ), eReady );
+
+				} while( uxQueue > ( UBaseType_t ) tskIDLE_PRIORITY ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+				/* Fill in an TaskStatus_t structure with information on each
+				task in the Blocked state. */
+				uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxDelayedTaskList, eBlocked );
+				uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), ( List_t * ) pxOverflowDelayedTaskList, eBlocked );
+
+				#if( INCLUDE_vTaskDelete == 1 )
+				{
+					/* Fill in an TaskStatus_t structure with information on
+					each task that has been deleted but not yet cleaned up. */
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xTasksWaitingTermination, eDeleted );
+				}
+				#endif
+
+				#if ( INCLUDE_vTaskSuspend == 1 )
+				{
+					/* Fill in an TaskStatus_t structure with information on
+					each task in the Suspended state. */
+					uxTask += prvListTasksWithinSingleList( &( pxTaskStatusArray[ uxTask ] ), &xSuspendedTaskList, eSuspended );
+				}
+				#endif
+
+				#if ( configGENERATE_RUN_TIME_STATS == 1)
+				{
+					if( pulTotalRunTime != NULL )
+					{
+						#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+							portALT_GET_RUN_TIME_COUNTER_VALUE( ( *pulTotalRunTime ) );
+						#else
+							*pulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+						#endif
+					}
+				}
+				#else
+				{
+					if( pulTotalRunTime != NULL )
+					{
+						*pulTotalRunTime = 0;
+					}
+				}
+				#endif
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		( void ) xTaskResumeAll();
+
+		return uxTask;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskGetIdleTaskHandle == 1 )
+
+	TaskHandle_t xTaskGetIdleTaskHandle( void )
+	{
+		/* If xTaskGetIdleTaskHandle() is called before the scheduler has been
+		started, then xIdleTaskHandle will be NULL. */
+		configASSERT( ( xIdleTaskHandle != NULL ) );
+		return xIdleTaskHandle;
+	}
+
+#endif /* INCLUDE_xTaskGetIdleTaskHandle */
+/*----------------------------------------------------------*/
+
+/* This conditional compilation should use inequality to 0, not equality to 1.
+This is to ensure vTaskStepTick() is available when user defined low power mode
+implementations require configUSE_TICKLESS_IDLE to be set to a value other than
+1. */
+#if ( configUSE_TICKLESS_IDLE != 0 )
+
+	void vTaskStepTick( const TickType_t xTicksToJump )
+	{
+		/* Correct the tick count value after a period during which the tick
+		was suppressed.  Note this does *not* call the tick hook function for
+		each stepped tick. */
+		configASSERT( ( xTickCount + xTicksToJump ) <= xNextTaskUnblockTime );
+		xTickCount += xTicksToJump;
+		traceINCREASE_TICK_COUNT( xTicksToJump );
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*----------------------------------------------------------*/
+
+#if ( INCLUDE_xTaskAbortDelay == 1 )
+
+	BaseType_t xTaskAbortDelay( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB = ( TCB_t * ) xTask;
+	BaseType_t xReturn = pdFALSE;
+
+		configASSERT( pxTCB );
+
+		vTaskSuspendAll();
+		{
+			/* A task can only be prematurely removed from the Blocked state if
+			it is actually in the Blocked state. */
+			if( eTaskGetState( xTask ) == eBlocked )
+			{
+				/* Remove the reference to the task from the blocked list.  An
+				interrupt won't touch the xStateListItem because the
+				scheduler is suspended. */
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+				/* Is the task waiting on an event also?  If so remove it from
+				the event list too.  Interrupts can touch the event list item,
+				even though the scheduler is suspended, so a critical section
+				is used. */
+				taskENTER_CRITICAL();
+				{
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+					{
+						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+						pxTCB->ucDelayAborted = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				taskEXIT_CRITICAL();
+
+				/* Place the unblocked task into the appropriate ready list. */
+				prvAddTaskToReadyList( pxTCB );
+
+				/* A task being unblocked cannot cause an immediate context
+				switch if preemption is turned off. */
+				#if (  configUSE_PREEMPTION == 1 )
+				{
+					/* Preemption is on, but a context switch should only be
+					performed if the unblocked task has a priority that is
+					equal to or higher than the currently executing task. */
+					if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+					{
+						/* Pend the yield to be performed when the scheduler
+						is unsuspended. */
+						xYieldPending = pdTRUE;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				#endif /* configUSE_PREEMPTION */
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		xTaskResumeAll();
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTaskAbortDelay */
+/*----------------------------------------------------------*/
+
+BaseType_t xTaskIncrementTick( void )
+{
+TCB_t * pxTCB;
+TickType_t xItemValue;
+BaseType_t xSwitchRequired = pdFALSE;
+
+	/* Called by the portable layer each time a tick interrupt occurs.
+	Increments the tick then checks to see if the new tick value will cause any
+	tasks to be unblocked. */
+	traceTASK_INCREMENT_TICK( xTickCount );
+	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+	{
+		/* Minor optimisation.  The tick count cannot change in this
+		block. */
+		const TickType_t xConstTickCount = xTickCount + 1;
+
+		/* Increment the RTOS tick, switching the delayed and overflowed
+		delayed lists if it wraps to 0. */
+		xTickCount = xConstTickCount;
+
+		if( xConstTickCount == ( TickType_t ) 0U )
+		{
+			taskSWITCH_DELAYED_LISTS();
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		/* See if this tick has made a timeout expire.  Tasks are stored in
+		the	queue in the order of their wake time - meaning once one task
+		has been found whose block time has not expired there is no need to
+		look any further down the list. */
+		if( xConstTickCount >= xNextTaskUnblockTime )
+		{
+			for( ;; )
+			{
+				if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+				{
+					/* The delayed list is empty.  Set xNextTaskUnblockTime
+					to the maximum possible value so it is extremely
+					unlikely that the
+					if( xTickCount >= xNextTaskUnblockTime ) test will pass
+					next time through. */
+					xNextTaskUnblockTime = portMAX_DELAY; /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					break;
+				}
+				else
+				{
+					/* The delayed list is not empty, get the value of the
+					item at the head of the delayed list.  This is the time
+					at which the task at the head of the delayed list must
+					be removed from the Blocked state. */
+					pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );
+					xItemValue = listGET_LIST_ITEM_VALUE( &( pxTCB->xStateListItem ) );
+
+					if( xConstTickCount < xItemValue )
+					{
+						/* It is not time to unblock this item yet, but the
+						item value is the time at which the task at the head
+						of the blocked list must be removed from the Blocked
+						state -	so record the item value in
+						xNextTaskUnblockTime. */
+						xNextTaskUnblockTime = xItemValue;
+						break;
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* It is time to remove the item from the Blocked state. */
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+
+					/* Is the task waiting on an event also?  If so remove
+					it from the event list. */
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+					{
+						( void ) uxListRemove( &( pxTCB->xEventListItem ) );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Place the unblocked task into the appropriate ready
+					list. */
+					prvAddTaskToReadyList( pxTCB );
+
+					/* A task being unblocked cannot cause an immediate
+					context switch if preemption is turned off. */
+					#if (  configUSE_PREEMPTION == 1 )
+					{
+						/* Preemption is on, but a context switch should
+						only be performed if the unblocked task has a
+						priority that is equal to or higher than the
+						currently executing task. */
+						if( pxTCB->uxPriority >= pxCurrentTCB->uxPriority )
+						{
+							xSwitchRequired = pdTRUE;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					#endif /* configUSE_PREEMPTION */
+				}
+			}
+		}
+
+		/* Tasks of equal priority to the currently running task will share
+		processing time (time slice) if preemption is on, and the application
+		writer has not explicitly turned time slicing off. */
+		#if ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) )
+		{
+			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ pxCurrentTCB->uxPriority ] ) ) > ( UBaseType_t ) 1 )
+			{
+				xSwitchRequired = pdTRUE;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configUSE_TIME_SLICING == 1 ) ) */
+
+		#if ( configUSE_TICK_HOOK == 1 )
+		{
+			/* Guard against the tick hook being called when the pended tick
+			count is being unwound (when the scheduler is being unlocked). */
+			if( uxPendedTicks == ( UBaseType_t ) 0U )
+			{
+				vApplicationTickHook();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_TICK_HOOK */
+	}
+	else
+	{
+		++uxPendedTicks;
+
+		/* The tick hook gets called at regular intervals, even if the
+		scheduler is locked. */
+		#if ( configUSE_TICK_HOOK == 1 )
+		{
+			vApplicationTickHook();
+		}
+		#endif
+	}
+
+	#if ( configUSE_PREEMPTION == 1 )
+	{
+		if( xYieldPending != pdFALSE )
+		{
+			xSwitchRequired = pdTRUE;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	#endif /* configUSE_PREEMPTION */
+
+	return xSwitchRequired;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	void vTaskSetApplicationTaskTag( TaskHandle_t xTask, TaskHookFunction_t pxHookFunction )
+	{
+	TCB_t *xTCB;
+
+		/* If xTask is NULL then it is the task hook of the calling task that is
+		getting set. */
+		if( xTask == NULL )
+		{
+			xTCB = ( TCB_t * ) pxCurrentTCB;
+		}
+		else
+		{
+			xTCB = ( TCB_t * ) xTask;
+		}
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		taskENTER_CRITICAL();
+			xTCB->pxTaskTag = pxHookFunction;
+		taskEXIT_CRITICAL();
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	TaskHookFunction_t xTaskGetApplicationTaskTag( TaskHandle_t xTask )
+	{
+	TCB_t *xTCB;
+	TaskHookFunction_t xReturn;
+
+		/* If xTask is NULL then we are setting our own task hook. */
+		if( xTask == NULL )
+		{
+			xTCB = ( TCB_t * ) pxCurrentTCB;
+		}
+		else
+		{
+			xTCB = ( TCB_t * ) xTask;
+		}
+
+		/* Save the hook function in the TCB.  A critical section is required as
+		the value can be accessed from an interrupt. */
+		taskENTER_CRITICAL();
+		{
+			xReturn = xTCB->pxTaskTag;
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_APPLICATION_TASK_TAG == 1 )
+
+	BaseType_t xTaskCallApplicationTaskHook( TaskHandle_t xTask, void *pvParameter )
+	{
+	TCB_t *xTCB;
+	BaseType_t xReturn;
+
+		/* If xTask is NULL then we are calling our own task hook. */
+		if( xTask == NULL )
+		{
+			xTCB = ( TCB_t * ) pxCurrentTCB;
+		}
+		else
+		{
+			xTCB = ( TCB_t * ) xTask;
+		}
+
+		if( xTCB->pxTaskTag != NULL )
+		{
+			xReturn = xTCB->pxTaskTag( pvParameter );
+		}
+		else
+		{
+			xReturn = pdFAIL;
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_APPLICATION_TASK_TAG */
+/*-----------------------------------------------------------*/
+
+void vTaskSwitchContext( void )
+{
+	if( uxSchedulerSuspended != ( UBaseType_t ) pdFALSE )
+	{
+		/* The scheduler is currently suspended - do not allow a context
+		switch. */
+		xYieldPending = pdTRUE;
+	}
+	else
+	{
+		xYieldPending = pdFALSE;
+		traceTASK_SWITCHED_OUT();
+
+		#if ( configGENERATE_RUN_TIME_STATS == 1 )
+		{
+				#ifdef portALT_GET_RUN_TIME_COUNTER_VALUE
+					portALT_GET_RUN_TIME_COUNTER_VALUE( ulTotalRunTime );
+				#else
+					ulTotalRunTime = portGET_RUN_TIME_COUNTER_VALUE();
+				#endif
+
+				/* Add the amount of time the task has been running to the
+				accumulated time so far.  The time the task started running was
+				stored in ulTaskSwitchedInTime.  Note that there is no overflow
+				protection here so count values are only valid until the timer
+				overflows.  The guard against negative values is to protect
+				against suspect run time stat counter implementations - which
+				are provided by the application, not the kernel. */
+				if( ulTotalRunTime > ulTaskSwitchedInTime )
+				{
+					pxCurrentTCB->ulRunTimeCounter += ( ulTotalRunTime - ulTaskSwitchedInTime );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+				ulTaskSwitchedInTime = ulTotalRunTime;
+		}
+		#endif /* configGENERATE_RUN_TIME_STATS */
+
+		/* Check for stack overflow, if configured. */
+		taskCHECK_FOR_STACK_OVERFLOW();
+
+		/* Select a new task to run using either the generic C or port
+		optimised asm code. */
+		taskSELECT_HIGHEST_PRIORITY_TASK();
+		traceTASK_SWITCHED_IN();
+
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			/* Switch Newlib's _impure_ptr variable to point to the _reent
+			structure specific to this task. */
+			_impure_ptr = &( pxCurrentTCB->xNewLib_reent );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+	}
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnEventList( List_t * const pxEventList, const TickType_t xTicksToWait )
+{
+	configASSERT( pxEventList );
+
+	/* THIS FUNCTION MUST BE CALLED WITH EITHER INTERRUPTS DISABLED OR THE
+	SCHEDULER SUSPENDED AND THE QUEUE BEING ACCESSED LOCKED. */
+
+	/* Place the event list item of the TCB in the appropriate event list.
+	This is placed in the list in priority order so the highest priority task
+	is the first to be woken by the event.  The queue that contains the event
+	list is locked, preventing simultaneous access from interrupts. */
+	vListInsert( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+void vTaskPlaceOnUnorderedEventList( List_t * pxEventList, const TickType_t xItemValue, const TickType_t xTicksToWait )
+{
+	configASSERT( pxEventList );
+
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
+	the event groups implementation. */
+	configASSERT( uxSchedulerSuspended != 0 );
+
+	/* Store the item value in the event list item.  It is safe to access the
+	event list item here as interrupts won't access the event list item of a
+	task that is not in the Blocked state. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+	/* Place the event list item of the TCB at the end of the appropriate event
+	list.  It is safe to access the event list here because it is part of an
+	event group implementation - and interrupts don't access event groups
+	directly (instead they access them indirectly by pending function calls to
+	the task level). */
+	vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+	prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TIMERS == 1 )
+
+	void vTaskPlaceOnEventListRestricted( List_t * const pxEventList, TickType_t xTicksToWait, const BaseType_t xWaitIndefinitely )
+	{
+		configASSERT( pxEventList );
+
+		/* This function should not be called by application code hence the
+		'Restricted' in its name.  It is not part of the public API.  It is
+		designed for use by kernel code, and has special calling requirements -
+		it should be called with the scheduler suspended. */
+
+
+		/* Place the event list item of the TCB in the appropriate event list.
+		In this case it is assume that this is the only task that is going to
+		be waiting on this event list, so the faster vListInsertEnd() function
+		can be used in place of vListInsert. */
+		vListInsertEnd( pxEventList, &( pxCurrentTCB->xEventListItem ) );
+
+		/* If the task should block indefinitely then set the block time to a
+		value that will be recognised as an indefinite delay inside the
+		prvAddCurrentTaskToDelayedList() function. */
+		if( xWaitIndefinitely != pdFALSE )
+		{
+			xTicksToWait = portMAX_DELAY;
+		}
+
+		traceTASK_DELAY_UNTIL( ( xTickCount + xTicksToWait ) );
+		prvAddCurrentTaskToDelayedList( xTicksToWait, xWaitIndefinitely );
+	}
+
+#endif /* configUSE_TIMERS */
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskRemoveFromEventList( const List_t * const pxEventList )
+{
+TCB_t *pxUnblockedTCB;
+BaseType_t xReturn;
+
+	/* THIS FUNCTION MUST BE CALLED FROM A CRITICAL SECTION.  It can also be
+	called from a critical section within an ISR. */
+
+	/* The event list is sorted in priority order, so the first in the list can
+	be removed as it is known to be the highest priority.  Remove the TCB from
+	the delayed list, and add it to the ready list.
+
+	If an event is for a queue that is locked then this function will never
+	get called - the lock count on the queue will get modified instead.  This
+	means exclusive access to the event list is guaranteed here.
+
+	This function assumes that a check has already been made to ensure that
+	pxEventList is not empty. */
+	pxUnblockedTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxEventList );
+	configASSERT( pxUnblockedTCB );
+	( void ) uxListRemove( &( pxUnblockedTCB->xEventListItem ) );
+
+	if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+	{
+		( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+		prvAddTaskToReadyList( pxUnblockedTCB );
+	}
+	else
+	{
+		/* The delayed and ready lists cannot be accessed, so hold this task
+		pending until the scheduler is resumed. */
+		vListInsertEnd( &( xPendingReadyList ), &( pxUnblockedTCB->xEventListItem ) );
+	}
+
+	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+	{
+		/* Return true if the task removed from the event list has a higher
+		priority than the calling task.  This allows the calling task to know if
+		it should force a context switch now. */
+		xReturn = pdTRUE;
+
+		/* Mark that a yield is pending in case the user is not using the
+		"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
+		xYieldPending = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	#if( configUSE_TICKLESS_IDLE != 0 )
+	{
+		/* If a task is blocked on a kernel object then xNextTaskUnblockTime
+		might be set to the blocked task's time out time.  If the task is
+		unblocked for a reason other than a timeout xNextTaskUnblockTime is
+		normally left unchanged, because it is automatically reset to a new
+		value when the tick count equals xNextTaskUnblockTime.  However if
+		tickless idling is used it might be more important to enter sleep mode
+		at the earliest possible time - so reset xNextTaskUnblockTime here to
+		ensure it is updated at the earliest possible time. */
+		prvResetNextTaskUnblockTime();
+	}
+	#endif
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskRemoveFromUnorderedEventList( ListItem_t * pxEventListItem, const TickType_t xItemValue )
+{
+TCB_t *pxUnblockedTCB;
+BaseType_t xReturn;
+
+	/* THIS FUNCTION MUST BE CALLED WITH THE SCHEDULER SUSPENDED.  It is used by
+	the event flags implementation. */
+	configASSERT( uxSchedulerSuspended != pdFALSE );
+
+	/* Store the new item value in the event list. */
+	listSET_LIST_ITEM_VALUE( pxEventListItem, xItemValue | taskEVENT_LIST_ITEM_VALUE_IN_USE );
+
+	/* Remove the event list form the event flag.  Interrupts do not access
+	event flags. */
+	pxUnblockedTCB = ( TCB_t * ) listGET_LIST_ITEM_OWNER( pxEventListItem );
+	configASSERT( pxUnblockedTCB );
+	( void ) uxListRemove( pxEventListItem );
+
+	/* Remove the task from the delayed list and add it to the ready list.  The
+	scheduler is suspended so interrupts will not be accessing the ready
+	lists. */
+	( void ) uxListRemove( &( pxUnblockedTCB->xStateListItem ) );
+	prvAddTaskToReadyList( pxUnblockedTCB );
+
+	if( pxUnblockedTCB->uxPriority > pxCurrentTCB->uxPriority )
+	{
+		/* Return true if the task removed from the event list has
+		a higher priority than the calling task.  This allows
+		the calling task to know if it should force a context
+		switch now. */
+		xReturn = pdTRUE;
+
+		/* Mark that a yield is pending in case the user is not using the
+		"xHigherPriorityTaskWoken" parameter to an ISR safe FreeRTOS function. */
+		xYieldPending = pdTRUE;
+	}
+	else
+	{
+		xReturn = pdFALSE;
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskSetTimeOutState( TimeOut_t * const pxTimeOut )
+{
+	configASSERT( pxTimeOut );
+	pxTimeOut->xOverflowCount = xNumOfOverflows;
+	pxTimeOut->xTimeOnEntering = xTickCount;
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTaskCheckForTimeOut( TimeOut_t * const pxTimeOut, TickType_t * const pxTicksToWait )
+{
+BaseType_t xReturn;
+
+	configASSERT( pxTimeOut );
+	configASSERT( pxTicksToWait );
+
+	taskENTER_CRITICAL();
+	{
+		/* Minor optimisation.  The tick count cannot change in this block. */
+		const TickType_t xConstTickCount = xTickCount;
+
+		#if( INCLUDE_xTaskAbortDelay == 1 )
+			if( pxCurrentTCB->ucDelayAborted != pdFALSE )
+			{
+				/* The delay was aborted, which is not the same as a time out,
+				but has the same result. */
+				pxCurrentTCB->ucDelayAborted = pdFALSE;
+				xReturn = pdTRUE;
+			}
+			else
+		#endif
+
+		#if ( INCLUDE_vTaskSuspend == 1 )
+			if( *pxTicksToWait == portMAX_DELAY )
+			{
+				/* If INCLUDE_vTaskSuspend is set to 1 and the block time
+				specified is the maximum block time then the task should block
+				indefinitely, and therefore never time out. */
+				xReturn = pdFALSE;
+			}
+			else
+		#endif
+
+		if( ( xNumOfOverflows != pxTimeOut->xOverflowCount ) && ( xConstTickCount >= pxTimeOut->xTimeOnEntering ) ) /*lint !e525 Indentation preferred as is to make code within pre-processor directives clearer. */
+		{
+			/* The tick count is greater than the time at which
+			vTaskSetTimeout() was called, but has also overflowed since
+			vTaskSetTimeOut() was called.  It must have wrapped all the way
+			around and gone past again. This passed since vTaskSetTimeout()
+			was called. */
+			xReturn = pdTRUE;
+		}
+		else if( ( ( TickType_t ) ( xConstTickCount - pxTimeOut->xTimeOnEntering ) ) < *pxTicksToWait ) /*lint !e961 Explicit casting is only redundant with some compilers, whereas others require it to prevent integer conversion errors. */
+		{
+			/* Not a genuine timeout. Adjust parameters for time remaining. */
+			*pxTicksToWait -= ( xConstTickCount - pxTimeOut->xTimeOnEntering );
+			vTaskSetTimeOutState( pxTimeOut );
+			xReturn = pdFALSE;
+		}
+		else
+		{
+			xReturn = pdTRUE;
+		}
+	}
+	taskEXIT_CRITICAL();
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTaskMissedYield( void )
+{
+	xYieldPending = pdTRUE;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	UBaseType_t uxTaskGetTaskNumber( TaskHandle_t xTask )
+	{
+	UBaseType_t uxReturn;
+	TCB_t *pxTCB;
+
+		if( xTask != NULL )
+		{
+			pxTCB = ( TCB_t * ) xTask;
+			uxReturn = pxTCB->uxTaskNumber;
+		}
+		else
+		{
+			uxReturn = 0U;
+		}
+
+		return uxReturn;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	void vTaskSetTaskNumber( TaskHandle_t xTask, const UBaseType_t uxHandle )
+	{
+	TCB_t *pxTCB;
+
+		if( xTask != NULL )
+		{
+			pxTCB = ( TCB_t * ) xTask;
+			pxTCB->uxTaskNumber = uxHandle;
+		}
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+
+/*
+ * -----------------------------------------------------------
+ * The Idle task.
+ * ----------------------------------------------------------
+ *
+ * The portTASK_FUNCTION() macro is used to allow port/compiler specific
+ * language extensions.  The equivalent prototype for this function is:
+ *
+ * void prvIdleTask( void *pvParameters );
+ *
+ */
+static portTASK_FUNCTION( prvIdleTask, pvParameters )
+{
+	/* Stop warnings. */
+	( void ) pvParameters;
+
+	/** THIS IS THE RTOS IDLE TASK - WHICH IS CREATED AUTOMATICALLY WHEN THE
+	SCHEDULER IS STARTED. **/
+
+	for( ;; )
+	{
+		/* See if any tasks have deleted themselves - if so then the idle task
+		is responsible for freeing the deleted task's TCB and stack. */
+		prvCheckTasksWaitingTermination();
+
+		#if ( configUSE_PREEMPTION == 0 )
+		{
+			/* If we are not using preemption we keep forcing a task switch to
+			see if any other task has become available.  If we are using
+			preemption we don't need to do this as any task becoming available
+			will automatically get the processor anyway. */
+			taskYIELD();
+		}
+		#endif /* configUSE_PREEMPTION */
+
+		#if ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) )
+		{
+			/* When using preemption tasks of equal priority will be
+			timesliced.  If a task that is sharing the idle priority is ready
+			to run then the idle task should yield before the end of the
+			timeslice.
+
+			A critical region is not required here as we are just reading from
+			the list, and an occasional incorrect value will not matter.  If
+			the ready list at the idle priority contains more than one task
+			then a task other than the idle task is ready to execute. */
+			if( listCURRENT_LIST_LENGTH( &( pxReadyTasksLists[ tskIDLE_PRIORITY ] ) ) > ( UBaseType_t ) 1 )
+			{
+				taskYIELD();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* ( ( configUSE_PREEMPTION == 1 ) && ( configIDLE_SHOULD_YIELD == 1 ) ) */
+
+		#if ( configUSE_IDLE_HOOK == 1 )
+		{
+			extern void vApplicationIdleHook( void );
+
+			/* Call the user defined function from within the idle task.  This
+			allows the application designer to add background functionality
+			without the overhead of a separate task.
+			NOTE: vApplicationIdleHook() MUST NOT, UNDER ANY CIRCUMSTANCES,
+			CALL A FUNCTION THAT MIGHT BLOCK. */
+			vApplicationIdleHook();
+		}
+		#endif /* configUSE_IDLE_HOOK */
+
+		/* This conditional compilation should use inequality to 0, not equality
+		to 1.  This is to ensure portSUPPRESS_TICKS_AND_SLEEP() is called when
+		user defined low power mode	implementations require
+		configUSE_TICKLESS_IDLE to be set to a value other than 1. */
+		#if ( configUSE_TICKLESS_IDLE != 0 )
+		{
+		TickType_t xExpectedIdleTime;
+
+			/* It is not desirable to suspend then resume the scheduler on
+			each iteration of the idle task.  Therefore, a preliminary
+			test of the expected idle time is performed without the
+			scheduler suspended.  The result here is not necessarily
+			valid. */
+			xExpectedIdleTime = prvGetExpectedIdleTime();
+
+			if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+			{
+				vTaskSuspendAll();
+				{
+					/* Now the scheduler is suspended, the expected idle
+					time can be sampled again, and this time its value can
+					be used. */
+					configASSERT( xNextTaskUnblockTime >= xTickCount );
+					xExpectedIdleTime = prvGetExpectedIdleTime();
+
+					if( xExpectedIdleTime >= configEXPECTED_IDLE_TIME_BEFORE_SLEEP )
+					{
+						traceLOW_POWER_IDLE_BEGIN();
+						portSUPPRESS_TICKS_AND_SLEEP( xExpectedIdleTime );
+						traceLOW_POWER_IDLE_END();
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+				}
+				( void ) xTaskResumeAll();
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configUSE_TICKLESS_IDLE */
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TICKLESS_IDLE != 0 )
+
+	eSleepModeStatus eTaskConfirmSleepModeStatus( void )
+	{
+	/* The idle task exists in addition to the application tasks. */
+	const UBaseType_t uxNonApplicationTasks = 1;
+	eSleepModeStatus eReturn = eStandardSleep;
+
+		if( listCURRENT_LIST_LENGTH( &xPendingReadyList ) != 0 )
+		{
+			/* A task was made ready while the scheduler was suspended. */
+			eReturn = eAbortSleep;
+		}
+		else if( xYieldPending != pdFALSE )
+		{
+			/* A yield was pended while the scheduler was suspended. */
+			eReturn = eAbortSleep;
+		}
+		else
+		{
+			/* If all the tasks are in the suspended list (which might mean they
+			have an infinite block time rather than actually being suspended)
+			then it is safe to turn all clocks off and just wait for external
+			interrupts. */
+			if( listCURRENT_LIST_LENGTH( &xSuspendedTaskList ) == ( uxCurrentNumberOfTasks - uxNonApplicationTasks ) )
+			{
+				eReturn = eNoTasksWaitingTimeout;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		return eReturn;
+	}
+
+#endif /* configUSE_TICKLESS_IDLE */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+	void vTaskSetThreadLocalStoragePointer( TaskHandle_t xTaskToSet, BaseType_t xIndex, void *pvValue )
+	{
+	TCB_t *pxTCB;
+
+		if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+		{
+			pxTCB = prvGetTCBFromHandle( xTaskToSet );
+			pxTCB->pvThreadLocalStoragePointers[ xIndex ] = pvValue;
+		}
+	}
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( configNUM_THREAD_LOCAL_STORAGE_POINTERS != 0 )
+
+	void *pvTaskGetThreadLocalStoragePointer( TaskHandle_t xTaskToQuery, BaseType_t xIndex )
+	{
+	void *pvReturn = NULL;
+	TCB_t *pxTCB;
+
+		if( xIndex < configNUM_THREAD_LOCAL_STORAGE_POINTERS )
+		{
+			pxTCB = prvGetTCBFromHandle( xTaskToQuery );
+			pvReturn = pxTCB->pvThreadLocalStoragePointers[ xIndex ];
+		}
+		else
+		{
+			pvReturn = NULL;
+		}
+
+		return pvReturn;
+	}
+
+#endif /* configNUM_THREAD_LOCAL_STORAGE_POINTERS */
+/*-----------------------------------------------------------*/
+
+#if ( portUSING_MPU_WRAPPERS == 1 )
+
+	void vTaskAllocateMPURegions( TaskHandle_t xTaskToModify, const MemoryRegion_t * const xRegions )
+	{
+	TCB_t *pxTCB;
+
+		/* If null is passed in here then we are modifying the MPU settings of
+		the calling task. */
+		pxTCB = prvGetTCBFromHandle( xTaskToModify );
+
+		vPortStoreTaskMPUSettings( &( pxTCB->xMPUSettings ), xRegions, NULL, 0 );
+	}
+
+#endif /* portUSING_MPU_WRAPPERS */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseTaskLists( void )
+{
+UBaseType_t uxPriority;
+
+	for( uxPriority = ( UBaseType_t ) 0U; uxPriority < ( UBaseType_t ) configMAX_PRIORITIES; uxPriority++ )
+	{
+		vListInitialise( &( pxReadyTasksLists[ uxPriority ] ) );
+	}
+
+	vListInitialise( &xDelayedTaskList1 );
+	vListInitialise( &xDelayedTaskList2 );
+	vListInitialise( &xPendingReadyList );
+
+	#if ( INCLUDE_vTaskDelete == 1 )
+	{
+		vListInitialise( &xTasksWaitingTermination );
+	}
+	#endif /* INCLUDE_vTaskDelete */
+
+	#if ( INCLUDE_vTaskSuspend == 1 )
+	{
+		vListInitialise( &xSuspendedTaskList );
+	}
+	#endif /* INCLUDE_vTaskSuspend */
+
+	/* Start with pxDelayedTaskList using list1 and the pxOverflowDelayedTaskList
+	using list2. */
+	pxDelayedTaskList = &xDelayedTaskList1;
+	pxOverflowDelayedTaskList = &xDelayedTaskList2;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckTasksWaitingTermination( void )
+{
+
+	/** THIS FUNCTION IS CALLED FROM THE RTOS IDLE TASK **/
+
+	#if ( INCLUDE_vTaskDelete == 1 )
+	{
+		BaseType_t xListIsEmpty;
+
+		/* ucTasksDeleted is used to prevent vTaskSuspendAll() being called
+		too often in the idle task. */
+		while( uxDeletedTasksWaitingCleanUp > ( UBaseType_t ) 0U )
+		{
+			vTaskSuspendAll();
+			{
+				xListIsEmpty = listLIST_IS_EMPTY( &xTasksWaitingTermination );
+			}
+			( void ) xTaskResumeAll();
+
+			if( xListIsEmpty == pdFALSE )
+			{
+				TCB_t *pxTCB;
+
+				taskENTER_CRITICAL();
+				{
+					pxTCB = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( ( &xTasksWaitingTermination ) );
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					--uxCurrentNumberOfTasks;
+					--uxDeletedTasksWaitingCleanUp;
+				}
+				taskEXIT_CRITICAL();
+
+				prvDeleteTCB( pxTCB );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+	}
+	#endif /* INCLUDE_vTaskDelete */
+}
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TRACE_FACILITY == 1 )
+
+	void vTaskGetInfo( TaskHandle_t xTask, TaskStatus_t *pxTaskStatus, BaseType_t xGetFreeStackSpace, eTaskState eState )
+	{
+	TCB_t *pxTCB;
+
+		/* xTask is NULL then get the state of the calling task. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		pxTaskStatus->xHandle = ( TaskHandle_t ) pxTCB;
+		pxTaskStatus->pcTaskName = ( const char * ) &( pxTCB->pcTaskName [ 0 ] );
+		pxTaskStatus->uxCurrentPriority = pxTCB->uxPriority;
+		pxTaskStatus->pxStackBase = pxTCB->pxStack;
+		pxTaskStatus->xTaskNumber = pxTCB->uxTCBNumber;
+
+		#if ( INCLUDE_vTaskSuspend == 1 )
+		{
+			/* If the task is in the suspended list then there is a chance it is
+			actually just blocked indefinitely - so really it should be reported as
+			being in the Blocked state. */
+			if( pxTaskStatus->eCurrentState == eSuspended )
+			{
+				vTaskSuspendAll();
+				{
+					if( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) != NULL )
+					{
+						pxTaskStatus->eCurrentState = eBlocked;
+					}
+				}
+				xTaskResumeAll();
+			}
+		}
+		#endif /* INCLUDE_vTaskSuspend */
+
+		#if ( configUSE_MUTEXES == 1 )
+		{
+			pxTaskStatus->uxBasePriority = pxTCB->uxBasePriority;
+		}
+		#else
+		{
+			pxTaskStatus->uxBasePriority = 0;
+		}
+		#endif
+
+		#if ( configGENERATE_RUN_TIME_STATS == 1 )
+		{
+			pxTaskStatus->ulRunTimeCounter = pxTCB->ulRunTimeCounter;
+		}
+		#else
+		{
+			pxTaskStatus->ulRunTimeCounter = 0;
+		}
+		#endif
+
+		/* Obtaining the task state is a little fiddly, so is only done if the value
+		of eState passed into this function is eInvalid - otherwise the state is
+		just set to whatever is passed in. */
+		if( eState != eInvalid )
+		{
+			pxTaskStatus->eCurrentState = eState;
+		}
+		else
+		{
+			pxTaskStatus->eCurrentState = eTaskGetState( xTask );
+		}
+
+		/* Obtaining the stack space takes some time, so the xGetFreeStackSpace
+		parameter is provided to allow it to be skipped. */
+		if( xGetFreeStackSpace != pdFALSE )
+		{
+			#if ( portSTACK_GROWTH > 0 )
+			{
+				pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxEndOfStack );
+			}
+			#else
+			{
+				pxTaskStatus->usStackHighWaterMark = prvTaskCheckFreeStackSpace( ( uint8_t * ) pxTCB->pxStack );
+			}
+			#endif
+		}
+		else
+		{
+			pxTaskStatus->usStackHighWaterMark = 0;
+		}
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_TRACE_FACILITY == 1 )
+
+	static UBaseType_t prvListTasksWithinSingleList( TaskStatus_t *pxTaskStatusArray, List_t *pxList, eTaskState eState )
+	{
+	volatile TCB_t *pxNextTCB, *pxFirstTCB;
+	UBaseType_t uxTask = 0;
+
+		if( listCURRENT_LIST_LENGTH( pxList ) > ( UBaseType_t ) 0 )
+		{
+			listGET_OWNER_OF_NEXT_ENTRY( pxFirstTCB, pxList );
+
+			/* Populate an TaskStatus_t structure within the
+			pxTaskStatusArray array for each task that is referenced from
+			pxList.  See the definition of TaskStatus_t in task.h for the
+			meaning of each TaskStatus_t structure member. */
+			do
+			{
+				listGET_OWNER_OF_NEXT_ENTRY( pxNextTCB, pxList );
+				vTaskGetInfo( ( TaskHandle_t ) pxNextTCB, &( pxTaskStatusArray[ uxTask ] ), pdTRUE, eState );
+				uxTask++;
+			} while( pxNextTCB != pxFirstTCB );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return uxTask;
+	}
+
+#endif /* configUSE_TRACE_FACILITY */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) )
+
+	static uint16_t prvTaskCheckFreeStackSpace( const uint8_t * pucStackByte )
+	{
+	uint32_t ulCount = 0U;
+
+		while( *pucStackByte == ( uint8_t ) tskSTACK_FILL_BYTE )
+		{
+			pucStackByte -= portSTACK_GROWTH;
+			ulCount++;
+		}
+
+		ulCount /= ( uint32_t ) sizeof( StackType_t ); /*lint !e961 Casting is not redundant on smaller architectures. */
+
+		return ( uint16_t ) ulCount;
+	}
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) || ( INCLUDE_uxTaskGetStackHighWaterMark == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_uxTaskGetStackHighWaterMark == 1 )
+
+	UBaseType_t uxTaskGetStackHighWaterMark( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	uint8_t *pucEndOfStack;
+	UBaseType_t uxReturn;
+
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		#if portSTACK_GROWTH < 0
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxStack;
+		}
+		#else
+		{
+			pucEndOfStack = ( uint8_t * ) pxTCB->pxEndOfStack;
+		}
+		#endif
+
+		uxReturn = ( UBaseType_t ) prvTaskCheckFreeStackSpace( pucEndOfStack );
+
+		return uxReturn;
+	}
+
+#endif /* INCLUDE_uxTaskGetStackHighWaterMark */
+/*-----------------------------------------------------------*/
+
+#if ( INCLUDE_vTaskDelete == 1 )
+
+	static void prvDeleteTCB( TCB_t *pxTCB )
+	{
+		/* This call is required specifically for the TriCore port.  It must be
+		above the vPortFree() calls.  The call is also used by ports/demos that
+		want to allocate and clean RAM statically. */
+		portCLEAN_UP_TCB( pxTCB );
+
+		/* Free up the memory allocated by the scheduler for the task.  It is up
+		to the task to free any memory allocated at the application level. */
+		#if ( configUSE_NEWLIB_REENTRANT == 1 )
+		{
+			_reclaim_reent( &( pxTCB->xNewLib_reent ) );
+		}
+		#endif /* configUSE_NEWLIB_REENTRANT */
+
+		#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) && ( portUSING_MPU_WRAPPERS == 0 ) )
+		{
+			/* The task can only have been allocated dynamically - free both
+			the stack and TCB. */
+			vPortFree( pxTCB->pxStack );
+			vPortFree( pxTCB );
+		}
+		#elif( tskSTATIC_AND_DYNAMIC_ALLOCATION_POSSIBLE == 1 )
+		{
+			/* The task could have been allocated statically or dynamically, so
+			check what was statically allocated before trying to free the
+			memory. */
+			if( pxTCB->ucStaticallyAllocated == tskDYNAMICALLY_ALLOCATED_STACK_AND_TCB )
+			{
+				/* Both the stack and TCB were allocated dynamically, so both
+				must be freed. */
+				vPortFree( pxTCB->pxStack );
+				vPortFree( pxTCB );
+			}
+			else if( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_ONLY )
+			{
+				/* Only the stack was statically allocated, so the TCB is the
+				only memory that must be freed. */
+				vPortFree( pxTCB );
+			}
+			else
+			{
+				/* Neither the stack nor the TCB were allocated dynamically, so
+				nothing needs to be freed. */
+				configASSERT( pxTCB->ucStaticallyAllocated == tskSTATICALLY_ALLOCATED_STACK_AND_TCB	)
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+	}
+
+#endif /* INCLUDE_vTaskDelete */
+/*-----------------------------------------------------------*/
+
+static void prvResetNextTaskUnblockTime( void )
+{
+TCB_t *pxTCB;
+
+	if( listLIST_IS_EMPTY( pxDelayedTaskList ) != pdFALSE )
+	{
+		/* The new current delayed list is empty.  Set xNextTaskUnblockTime to
+		the maximum possible value so it is	extremely unlikely that the
+		if( xTickCount >= xNextTaskUnblockTime ) test will pass until
+		there is an item in the delayed list. */
+		xNextTaskUnblockTime = portMAX_DELAY;
+	}
+	else
+	{
+		/* The new current delayed list is not empty, get the value of
+		the item at the head of the delayed list.  This is the time at
+		which the task at the head of the delayed list should be removed
+		from the Blocked state. */
+		( pxTCB ) = ( TCB_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxDelayedTaskList );
+		xNextTaskUnblockTime = listGET_LIST_ITEM_VALUE( &( ( pxTCB )->xStateListItem ) );
+	}
+}
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) )
+
+	TaskHandle_t xTaskGetCurrentTaskHandle( void )
+	{
+	TaskHandle_t xReturn;
+
+		/* A critical section is not required as this is not called from
+		an interrupt and the current TCB will always be the same for any
+		individual execution thread. */
+		xReturn = pxCurrentTCB;
+
+		return xReturn;
+	}
+
+#endif /* ( ( INCLUDE_xTaskGetCurrentTaskHandle == 1 ) || ( configUSE_MUTEXES == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) )
+
+	BaseType_t xTaskGetSchedulerState( void )
+	{
+	BaseType_t xReturn;
+
+		if( xSchedulerRunning == pdFALSE )
+		{
+			xReturn = taskSCHEDULER_NOT_STARTED;
+		}
+		else
+		{
+			if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+			{
+				xReturn = taskSCHEDULER_RUNNING;
+			}
+			else
+			{
+				xReturn = taskSCHEDULER_SUSPENDED;
+			}
+		}
+
+		return xReturn;
+	}
+
+#endif /* ( ( INCLUDE_xTaskGetSchedulerState == 1 ) || ( configUSE_TIMERS == 1 ) ) */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	void vTaskPriorityInherit( TaskHandle_t const pxMutexHolder )
+	{
+	TCB_t * const pxTCB = ( TCB_t * ) pxMutexHolder;
+
+		/* If the mutex was given back by an interrupt while the queue was
+		locked then the mutex holder might now be NULL. */
+		if( pxMutexHolder != NULL )
+		{
+			/* If the holder of the mutex has a priority below the priority of
+			the task attempting to obtain the mutex then it will temporarily
+			inherit the priority of the task attempting to obtain the mutex. */
+			if( pxTCB->uxPriority < pxCurrentTCB->uxPriority )
+			{
+				/* Adjust the mutex holder state to account for its new
+				priority.  Only reset the event list item value if the value is
+				not	being used for anything else. */
+				if( ( listGET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ) ) & taskEVENT_LIST_ITEM_VALUE_IN_USE ) == 0UL )
+				{
+					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+
+				/* If the task being modified is in the ready state it will need
+				to be moved into a new list. */
+				if( listIS_CONTAINED_WITHIN( &( pxReadyTasksLists[ pxTCB->uxPriority ] ), &( pxTCB->xStateListItem ) ) != pdFALSE )
+				{
+					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Inherit the priority before being moved into the new list. */
+					pxTCB->uxPriority = pxCurrentTCB->uxPriority;
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* Just inherit the priority. */
+					pxTCB->uxPriority = pxCurrentTCB->uxPriority;
+				}
+
+				traceTASK_PRIORITY_INHERIT( pxTCB, pxCurrentTCB->uxPriority );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	BaseType_t xTaskPriorityDisinherit( TaskHandle_t const pxMutexHolder )
+	{
+	TCB_t * const pxTCB = ( TCB_t * ) pxMutexHolder;
+	BaseType_t xReturn = pdFALSE;
+
+		if( pxMutexHolder != NULL )
+		{
+			/* A task can only have an inherited priority if it holds the mutex.
+			If the mutex is held by a task then it cannot be given from an
+			interrupt, and if a mutex is given by the holding task then it must
+			be the running state task. */
+			configASSERT( pxTCB == pxCurrentTCB );
+
+			configASSERT( pxTCB->uxMutexesHeld );
+			( pxTCB->uxMutexesHeld )--;
+
+			/* Has the holder of the mutex inherited the priority of another
+			task? */
+			if( pxTCB->uxPriority != pxTCB->uxBasePriority )
+			{
+				/* Only disinherit if no other mutexes are held. */
+				if( pxTCB->uxMutexesHeld == ( UBaseType_t ) 0 )
+				{
+					/* A task can only have an inherited priority if it holds
+					the mutex.  If the mutex is held by a task then it cannot be
+					given from an interrupt, and if a mutex is given by the
+					holding	task then it must be the running state task.  Remove
+					the	holding task from the ready	list. */
+					if( uxListRemove( &( pxTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+					{
+						taskRESET_READY_PRIORITY( pxTCB->uxPriority );
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+
+					/* Disinherit the priority before adding the task into the
+					new	ready list. */
+					traceTASK_PRIORITY_DISINHERIT( pxTCB, pxTCB->uxBasePriority );
+					pxTCB->uxPriority = pxTCB->uxBasePriority;
+
+					/* Reset the event list item value.  It cannot be in use for
+					any other purpose if this task is running, and it must be
+					running to give back the mutex. */
+					listSET_LIST_ITEM_VALUE( &( pxTCB->xEventListItem ), ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxTCB->uxPriority ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+					prvAddTaskToReadyList( pxTCB );
+
+					/* Return true to indicate that a context switch is required.
+					This is only actually required in the corner case whereby
+					multiple mutexes were held and the mutexes were given back
+					in an order different to that in which they were taken.
+					If a context switch did not occur when the first mutex was
+					returned, even if a task was waiting on it, then a context
+					switch should occur when the last mutex is returned whether
+					a task is waiting on it or not. */
+					xReturn = pdTRUE;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+
+		return xReturn;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+	void vTaskEnterCritical( void )
+	{
+		portDISABLE_INTERRUPTS();
+
+		if( xSchedulerRunning != pdFALSE )
+		{
+			( pxCurrentTCB->uxCriticalNesting )++;
+
+			/* This is not the interrupt safe version of the enter critical
+			function so	assert() if it is being called from an interrupt
+			context.  Only API functions that end in "FromISR" can be used in an
+			interrupt.  Only assert if the critical nesting count is 1 to
+			protect against recursive calls if the assert function also uses a
+			critical section. */
+			if( pxCurrentTCB->uxCriticalNesting == 1 )
+			{
+				portASSERT_IF_IN_ISR();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( portCRITICAL_NESTING_IN_TCB == 1 )
+
+	void vTaskExitCritical( void )
+	{
+		if( xSchedulerRunning != pdFALSE )
+		{
+			if( pxCurrentTCB->uxCriticalNesting > 0U )
+			{
+				( pxCurrentTCB->uxCriticalNesting )--;
+
+				if( pxCurrentTCB->uxCriticalNesting == 0U )
+				{
+					portENABLE_INTERRUPTS();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* portCRITICAL_NESTING_IN_TCB */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+	static char *prvWriteNameToBuffer( char *pcBuffer, const char *pcTaskName )
+	{
+	size_t x;
+
+		/* Start by copying the entire string. */
+		strcpy( pcBuffer, pcTaskName );
+
+		/* Pad the end of the string with spaces to ensure columns line up when
+		printed out. */
+		for( x = strlen( pcBuffer ); x < ( size_t ) ( configMAX_TASK_NAME_LEN - 1 ); x++ )
+		{
+			pcBuffer[ x ] = ' ';
+		}
+
+		/* Terminate. */
+		pcBuffer[ x ] = 0x00;
+
+		/* Return the new end of string. */
+		return &( pcBuffer[ x ] );
+	}
+
+#endif /* ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) */
+/*-----------------------------------------------------------*/
+
+#if ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+	void vTaskList( char * pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	volatile UBaseType_t uxArraySize, x;
+	char cStatus;
+
+		/*
+		 * PLEASE NOTE:
+		 *
+		 * This function is provided for convenience only, and is used by many
+		 * of the demo applications.  Do not consider it to be part of the
+		 * scheduler.
+		 *
+		 * vTaskList() calls uxTaskGetSystemState(), then formats part of the
+		 * uxTaskGetSystemState() output into a human readable table that
+		 * displays task names, states and stack usage.
+		 *
+		 * vTaskList() has a dependency on the sprintf() C library function that
+		 * might bloat the code size, use a lot of stack, and provide different
+		 * results on different platforms.  An alternative, tiny, third party,
+		 * and limited functionality implementation of sprintf() is provided in
+		 * many of the FreeRTOS/Demo sub-directories in a file called
+		 * printf-stdarg.c (note printf-stdarg.c does not provide a full
+		 * snprintf() implementation!).
+		 *
+		 * It is recommended that production systems call uxTaskGetSystemState()
+		 * directly to get access to raw stats data, rather than indirectly
+		 * through a call to vTaskList().
+		 */
+
+
+		/* Make sure the write buffer does not contain a string. */
+		*pcWriteBuffer = 0x00;
+
+		/* Take a snapshot of the number of tasks in case it changes while this
+		function is executing. */
+		uxArraySize = uxCurrentNumberOfTasks;
+
+		/* Allocate an array index for each task.  NOTE!  if
+		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+		equate to NULL. */
+		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );
+
+		if( pxTaskStatusArray != NULL )
+		{
+			/* Generate the (binary) data. */
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, NULL );
+
+			/* Create a human readable table from the binary data. */
+			for( x = 0; x < uxArraySize; x++ )
+			{
+				switch( pxTaskStatusArray[ x ].eCurrentState )
+				{
+					case eReady:		cStatus = tskREADY_CHAR;
+										break;
+
+					case eBlocked:		cStatus = tskBLOCKED_CHAR;
+										break;
+
+					case eSuspended:	cStatus = tskSUSPENDED_CHAR;
+										break;
+
+					case eDeleted:		cStatus = tskDELETED_CHAR;
+										break;
+
+					default:			/* Should not get here, but it is included
+										to prevent static checking errors. */
+										cStatus = 0x00;
+										break;
+				}
+
+				/* Write the task name to the string, padding with spaces so it
+				can be printed in tabular form more easily. */
+				pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+
+				/* Write the rest of the string. */
+				sprintf( pcWriteBuffer, "\t%c\t%u\t%u\t%u\r\n", cStatus, ( unsigned int ) pxTaskStatusArray[ x ].uxCurrentPriority, ( unsigned int ) pxTaskStatusArray[ x ].usStackHighWaterMark, ( unsigned int ) pxTaskStatusArray[ x ].xTaskNumber );
+				pcWriteBuffer += strlen( pcWriteBuffer );
+			}
+
+			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
+			is 0 then vPortFree() will be #defined to nothing. */
+			vPortFree( pxTaskStatusArray );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* ( ( configUSE_TRACE_FACILITY == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */
+/*----------------------------------------------------------*/
+
+#if ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) )
+
+	void vTaskGetRunTimeStats( char *pcWriteBuffer )
+	{
+	TaskStatus_t *pxTaskStatusArray;
+	volatile UBaseType_t uxArraySize, x;
+	uint32_t ulTotalTime, ulStatsAsPercentage;
+
+		#if( configUSE_TRACE_FACILITY != 1 )
+		{
+			#error configUSE_TRACE_FACILITY must also be set to 1 in FreeRTOSConfig.h to use vTaskGetRunTimeStats().
+		}
+		#endif
+
+		/*
+		 * PLEASE NOTE:
+		 *
+		 * This function is provided for convenience only, and is used by many
+		 * of the demo applications.  Do not consider it to be part of the
+		 * scheduler.
+		 *
+		 * vTaskGetRunTimeStats() calls uxTaskGetSystemState(), then formats part
+		 * of the uxTaskGetSystemState() output into a human readable table that
+		 * displays the amount of time each task has spent in the Running state
+		 * in both absolute and percentage terms.
+		 *
+		 * vTaskGetRunTimeStats() has a dependency on the sprintf() C library
+		 * function that might bloat the code size, use a lot of stack, and
+		 * provide different results on different platforms.  An alternative,
+		 * tiny, third party, and limited functionality implementation of
+		 * sprintf() is provided in many of the FreeRTOS/Demo sub-directories in
+		 * a file called printf-stdarg.c (note printf-stdarg.c does not provide
+		 * a full snprintf() implementation!).
+		 *
+		 * It is recommended that production systems call uxTaskGetSystemState()
+		 * directly to get access to raw stats data, rather than indirectly
+		 * through a call to vTaskGetRunTimeStats().
+		 */
+
+		/* Make sure the write buffer does not contain a string. */
+		*pcWriteBuffer = 0x00;
+
+		/* Take a snapshot of the number of tasks in case it changes while this
+		function is executing. */
+		uxArraySize = uxCurrentNumberOfTasks;
+
+		/* Allocate an array index for each task.  NOTE!  If
+		configSUPPORT_DYNAMIC_ALLOCATION is set to 0 then pvPortMalloc() will
+		equate to NULL. */
+		pxTaskStatusArray = pvPortMalloc( uxCurrentNumberOfTasks * sizeof( TaskStatus_t ) );
+
+		if( pxTaskStatusArray != NULL )
+		{
+			/* Generate the (binary) data. */
+			uxArraySize = uxTaskGetSystemState( pxTaskStatusArray, uxArraySize, &ulTotalTime );
+
+			/* For percentage calculations. */
+			ulTotalTime /= 100UL;
+
+			/* Avoid divide by zero errors. */
+			if( ulTotalTime > 0 )
+			{
+				/* Create a human readable table from the binary data. */
+				for( x = 0; x < uxArraySize; x++ )
+				{
+					/* What percentage of the total run time has the task used?
+					This will always be rounded down to the nearest integer.
+					ulTotalRunTimeDiv100 has already been divided by 100. */
+					ulStatsAsPercentage = pxTaskStatusArray[ x ].ulRunTimeCounter / ulTotalTime;
+
+					/* Write the task name to the string, padding with
+					spaces so it can be printed in tabular form more
+					easily. */
+					pcWriteBuffer = prvWriteNameToBuffer( pcWriteBuffer, pxTaskStatusArray[ x ].pcTaskName );
+
+					if( ulStatsAsPercentage > 0UL )
+					{
+						#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+						{
+							sprintf( pcWriteBuffer, "\t%lu\t\t%lu%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter, ulStatsAsPercentage );
+						}
+						#else
+						{
+							/* sizeof( int ) == sizeof( long ) so a smaller
+							printf() library can be used. */
+							sprintf( pcWriteBuffer, "\t%u\t\t%u%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter, ( unsigned int ) ulStatsAsPercentage );
+						}
+						#endif
+					}
+					else
+					{
+						/* If the percentage is zero here then the task has
+						consumed less than 1% of the total run time. */
+						#ifdef portLU_PRINTF_SPECIFIER_REQUIRED
+						{
+							sprintf( pcWriteBuffer, "\t%lu\t\t<1%%\r\n", pxTaskStatusArray[ x ].ulRunTimeCounter );
+						}
+						#else
+						{
+							/* sizeof( int ) == sizeof( long ) so a smaller
+							printf() library can be used. */
+							sprintf( pcWriteBuffer, "\t%u\t\t<1%%\r\n", ( unsigned int ) pxTaskStatusArray[ x ].ulRunTimeCounter );
+						}
+						#endif
+					}
+
+					pcWriteBuffer += strlen( pcWriteBuffer );
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			/* Free the array again.  NOTE!  If configSUPPORT_DYNAMIC_ALLOCATION
+			is 0 then vPortFree() will be #defined to nothing. */
+			vPortFree( pxTaskStatusArray );
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+#endif /* ( ( configGENERATE_RUN_TIME_STATS == 1 ) && ( configUSE_STATS_FORMATTING_FUNCTIONS > 0 ) ) */
+/*-----------------------------------------------------------*/
+
+TickType_t uxTaskResetEventItemValue( void )
+{
+TickType_t uxReturn;
+
+	uxReturn = listGET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ) );
+
+	/* Reset the event list item to its normal value - so it can be used with
+	queues and semaphores. */
+	listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xEventListItem ), ( ( TickType_t ) configMAX_PRIORITIES - ( TickType_t ) pxCurrentTCB->uxPriority ) ); /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+
+	return uxReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if ( configUSE_MUTEXES == 1 )
+
+	void *pvTaskIncrementMutexHeldCount( void )
+	{
+		/* If xSemaphoreCreateMutex() is called before any tasks have been created
+		then pxCurrentTCB will be NULL. */
+		if( pxCurrentTCB != NULL )
+		{
+			( pxCurrentTCB->uxMutexesHeld )++;
+		}
+
+		return pxCurrentTCB;
+	}
+
+#endif /* configUSE_MUTEXES */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	uint32_t ulTaskNotifyTake( BaseType_t xClearCountOnExit, TickType_t xTicksToWait )
+	{
+	uint32_t ulReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* Only block if the notification count is not already non-zero. */
+			if( pxCurrentTCB->ulNotifiedValue == 0UL )
+			{
+				/* Mark this task as waiting for a notification. */
+				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
+
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+					traceTASK_NOTIFY_TAKE_BLOCK();
+
+					/* All ports are written to allow a yield in a critical
+					section (some will yield immediately, others wait until the
+					critical section exits) - but it is not something that
+					application code should ever do. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		taskENTER_CRITICAL();
+		{
+			traceTASK_NOTIFY_TAKE();
+			ulReturn = pxCurrentTCB->ulNotifiedValue;
+
+			if( ulReturn != 0UL )
+			{
+				if( xClearCountOnExit != pdFALSE )
+				{
+					pxCurrentTCB->ulNotifiedValue = 0UL;
+				}
+				else
+				{
+					pxCurrentTCB->ulNotifiedValue = ulReturn - 1;
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+		}
+		taskEXIT_CRITICAL();
+
+		return ulReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskNotifyWait( uint32_t ulBitsToClearOnEntry, uint32_t ulBitsToClearOnExit, uint32_t *pulNotificationValue, TickType_t xTicksToWait )
+	{
+	BaseType_t xReturn;
+
+		taskENTER_CRITICAL();
+		{
+			/* Only block if a notification is not already pending. */
+			if( pxCurrentTCB->ucNotifyState != taskNOTIFICATION_RECEIVED )
+			{
+				/* Clear bits in the task's notification value as bits may get
+				set	by the notifying task or interrupt.  This can be used to
+				clear the value to zero. */
+				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnEntry;
+
+				/* Mark this task as waiting for a notification. */
+				pxCurrentTCB->ucNotifyState = taskWAITING_NOTIFICATION;
+
+				if( xTicksToWait > ( TickType_t ) 0 )
+				{
+					prvAddCurrentTaskToDelayedList( xTicksToWait, pdTRUE );
+					traceTASK_NOTIFY_WAIT_BLOCK();
+
+					/* All ports are written to allow a yield in a critical
+					section (some will yield immediately, others wait until the
+					critical section exits) - but it is not something that
+					application code should ever do. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		taskENTER_CRITICAL();
+		{
+			traceTASK_NOTIFY_WAIT();
+
+			if( pulNotificationValue != NULL )
+			{
+				/* Output the current notification value, which may or may not
+				have changed. */
+				*pulNotificationValue = pxCurrentTCB->ulNotifiedValue;
+			}
+
+			/* If ucNotifyValue is set then either the task never entered the
+			blocked state (because a notification was already pending) or the
+			task unblocked because of a notification.  Otherwise the task
+			unblocked because of a timeout. */
+			if( pxCurrentTCB->ucNotifyState == taskWAITING_NOTIFICATION )
+			{
+				/* A notification was not received. */
+				xReturn = pdFALSE;
+			}
+			else
+			{
+				/* A notification was already pending or a notification was
+				received while the task was waiting. */
+				pxCurrentTCB->ulNotifiedValue &= ~ulBitsToClearOnExit;
+				xReturn = pdTRUE;
+			}
+
+			pxCurrentTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskGenericNotify( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue )
+	{
+	TCB_t * pxTCB;
+	BaseType_t xReturn = pdPASS;
+	uint8_t ucOriginalNotifyState;
+
+		configASSERT( xTaskToNotify );
+		pxTCB = ( TCB_t * ) xTaskToNotify;
+
+		taskENTER_CRITICAL();
+		{
+			if( pulPreviousNotificationValue != NULL )
+			{
+				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
+			}
+
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			switch( eAction )
+			{
+				case eSetBits	:
+					pxTCB->ulNotifiedValue |= ulValue;
+					break;
+
+				case eIncrement	:
+					( pxTCB->ulNotifiedValue )++;
+					break;
+
+				case eSetValueWithOverwrite	:
+					pxTCB->ulNotifiedValue = ulValue;
+					break;
+
+				case eSetValueWithoutOverwrite :
+					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+					{
+						pxTCB->ulNotifiedValue = ulValue;
+					}
+					else
+					{
+						/* The value could not be written to the task. */
+						xReturn = pdFAIL;
+					}
+					break;
+
+				case eNoAction:
+					/* The task is being notified without its notify value being
+					updated. */
+					break;
+			}
+
+			traceTASK_NOTIFY();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+				prvAddTaskToReadyList( pxTCB );
+
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				#if( configUSE_TICKLESS_IDLE != 0 )
+				{
+					/* If a task is blocked waiting for a notification then
+					xNextTaskUnblockTime might be set to the blocked task's time
+					out time.  If the task is unblocked for a reason other than
+					a timeout xNextTaskUnblockTime is normally left unchanged,
+					because it will automatically get reset to a new value when
+					the tick count equals xNextTaskUnblockTime.  However if
+					tickless idling is used it might be more important to enter
+					sleep mode at the earliest possible time - so reset
+					xNextTaskUnblockTime here to ensure it is updated at the
+					earliest possible time. */
+					prvResetNextTaskUnblockTime();
+				}
+				#endif
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					taskYIELD_IF_USING_PREEMPTION();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskGenericNotifyFromISR( TaskHandle_t xTaskToNotify, uint32_t ulValue, eNotifyAction eAction, uint32_t *pulPreviousNotificationValue, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	TCB_t * pxTCB;
+	uint8_t ucOriginalNotifyState;
+	BaseType_t xReturn = pdPASS;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToNotify );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		pxTCB = ( TCB_t * ) xTaskToNotify;
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			if( pulPreviousNotificationValue != NULL )
+			{
+				*pulPreviousNotificationValue = pxTCB->ulNotifiedValue;
+			}
+
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			switch( eAction )
+			{
+				case eSetBits	:
+					pxTCB->ulNotifiedValue |= ulValue;
+					break;
+
+				case eIncrement	:
+					( pxTCB->ulNotifiedValue )++;
+					break;
+
+				case eSetValueWithOverwrite	:
+					pxTCB->ulNotifiedValue = ulValue;
+					break;
+
+				case eSetValueWithoutOverwrite :
+					if( ucOriginalNotifyState != taskNOTIFICATION_RECEIVED )
+					{
+						pxTCB->ulNotifiedValue = ulValue;
+					}
+					else
+					{
+						/* The value could not be written to the task. */
+						xReturn = pdFAIL;
+					}
+					break;
+
+				case eNoAction :
+					/* The task is being notified without its notify value being
+					updated. */
+					break;
+			}
+
+			traceTASK_NOTIFY_FROM_ISR();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed and ready lists cannot be accessed, so hold
+					this task pending until the scheduler is resumed. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					if( pxHigherPriorityTaskWoken != NULL )
+					{
+						*pxHigherPriorityTaskWoken = pdTRUE;
+					}
+					else
+					{
+						/* Mark that a yield is pending in case the user is not
+						using the "xHigherPriorityTaskWoken" parameter to an ISR
+						safe FreeRTOS function. */
+						xYieldPending = pdTRUE;
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	void vTaskNotifyGiveFromISR( TaskHandle_t xTaskToNotify, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	TCB_t * pxTCB;
+	uint8_t ucOriginalNotifyState;
+	UBaseType_t uxSavedInterruptStatus;
+
+		configASSERT( xTaskToNotify );
+
+		/* RTOS ports that support interrupt nesting have the concept of a
+		maximum	system call (or maximum API call) interrupt priority.
+		Interrupts that are	above the maximum system call priority are keep
+		permanently enabled, even when the RTOS kernel is in a critical section,
+		but cannot make any calls to FreeRTOS API functions.  If configASSERT()
+		is defined in FreeRTOSConfig.h then
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID() will result in an assertion
+		failure if a FreeRTOS API function is called from an interrupt that has
+		been assigned a priority above the configured maximum system call
+		priority.  Only FreeRTOS functions that end in FromISR can be called
+		from interrupts	that have been assigned a priority at or (logically)
+		below the maximum system call interrupt priority.  FreeRTOS maintains a
+		separate interrupt safe API to ensure interrupt entry is as fast and as
+		simple as possible.  More information (albeit Cortex-M specific) is
+		provided on the following link:
+		http://www.freertos.org/RTOS-Cortex-M3-M4.html */
+		portASSERT_IF_INTERRUPT_PRIORITY_INVALID();
+
+		pxTCB = ( TCB_t * ) xTaskToNotify;
+
+		uxSavedInterruptStatus = portSET_INTERRUPT_MASK_FROM_ISR();
+		{
+			ucOriginalNotifyState = pxTCB->ucNotifyState;
+			pxTCB->ucNotifyState = taskNOTIFICATION_RECEIVED;
+
+			/* 'Giving' is equivalent to incrementing a count in a counting
+			semaphore. */
+			( pxTCB->ulNotifiedValue )++;
+
+			traceTASK_NOTIFY_GIVE_FROM_ISR();
+
+			/* If the task is in the blocked state specifically to wait for a
+			notification then unblock it now. */
+			if( ucOriginalNotifyState == taskWAITING_NOTIFICATION )
+			{
+				/* The task should not have been on an event list. */
+				configASSERT( listLIST_ITEM_CONTAINER( &( pxTCB->xEventListItem ) ) == NULL );
+
+				if( uxSchedulerSuspended == ( UBaseType_t ) pdFALSE )
+				{
+					( void ) uxListRemove( &( pxTCB->xStateListItem ) );
+					prvAddTaskToReadyList( pxTCB );
+				}
+				else
+				{
+					/* The delayed and ready lists cannot be accessed, so hold
+					this task pending until the scheduler is resumed. */
+					vListInsertEnd( &( xPendingReadyList ), &( pxTCB->xEventListItem ) );
+				}
+
+				if( pxTCB->uxPriority > pxCurrentTCB->uxPriority )
+				{
+					/* The notified task has a priority above the currently
+					executing task so a yield is required. */
+					if( pxHigherPriorityTaskWoken != NULL )
+					{
+						*pxHigherPriorityTaskWoken = pdTRUE;
+					}
+					else
+					{
+						/* Mark that a yield is pending in case the user is not
+						using the "xHigherPriorityTaskWoken" parameter in an ISR
+						safe FreeRTOS function. */
+						xYieldPending = pdTRUE;
+					}
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		portCLEAR_INTERRUPT_MASK_FROM_ISR( uxSavedInterruptStatus );
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+
+/*-----------------------------------------------------------*/
+
+#if( configUSE_TASK_NOTIFICATIONS == 1 )
+
+	BaseType_t xTaskNotifyStateClear( TaskHandle_t xTask )
+	{
+	TCB_t *pxTCB;
+	BaseType_t xReturn;
+
+		/* If null is passed in here then it is the calling task that is having
+		its notification state cleared. */
+		pxTCB = prvGetTCBFromHandle( xTask );
+
+		taskENTER_CRITICAL();
+		{
+			if( pxTCB->ucNotifyState == taskNOTIFICATION_RECEIVED )
+			{
+				pxTCB->ucNotifyState = taskNOT_WAITING_NOTIFICATION;
+				xReturn = pdPASS;
+			}
+			else
+			{
+				xReturn = pdFAIL;
+			}
+		}
+		taskEXIT_CRITICAL();
+
+		return xReturn;
+	}
+
+#endif /* configUSE_TASK_NOTIFICATIONS */
+/*-----------------------------------------------------------*/
+
+
+static void prvAddCurrentTaskToDelayedList( TickType_t xTicksToWait, const BaseType_t xCanBlockIndefinitely )
+{
+TickType_t xTimeToWake;
+const TickType_t xConstTickCount = xTickCount;
+
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+	{
+		/* About to enter a delayed list, so ensure the ucDelayAborted flag is
+		reset to pdFALSE so it can be detected as having been set to pdTRUE
+		when the task leaves the Blocked state. */
+		pxCurrentTCB->ucDelayAborted = pdFALSE;
+	}
+	#endif
+
+	/* Remove the task from the ready list before adding it to the blocked list
+	as the same list item is used for both lists. */
+	if( uxListRemove( &( pxCurrentTCB->xStateListItem ) ) == ( UBaseType_t ) 0 )
+	{
+		/* The current task must be in a ready list, so there is no need to
+		check, and the port reset macro can be called directly. */
+		portRESET_READY_PRIORITY( pxCurrentTCB->uxPriority, uxTopReadyPriority );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	#if ( INCLUDE_vTaskSuspend == 1 )
+	{
+		if( ( xTicksToWait == portMAX_DELAY ) && ( xCanBlockIndefinitely != pdFALSE ) )
+		{
+			/* Add the task to the suspended task list instead of a delayed task
+			list to ensure it is not woken by a timing event.  It will block
+			indefinitely. */
+			vListInsertEnd( &xSuspendedTaskList, &( pxCurrentTCB->xStateListItem ) );
+		}
+		else
+		{
+			/* Calculate the time at which the task should be woken if the event
+			does not occur.  This may overflow but this doesn't matter, the
+			kernel will manage it correctly. */
+			xTimeToWake = xConstTickCount + xTicksToWait;
+
+			/* The list item will be inserted in wake time order. */
+			listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+			if( xTimeToWake < xConstTickCount )
+			{
+				/* Wake time has overflowed.  Place this item in the overflow
+				list. */
+				vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+			}
+			else
+			{
+				/* The wake time has not overflowed, so the current block list
+				is used. */
+				vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+				/* If the task entering the blocked state was placed at the
+				head of the list of blocked tasks then xNextTaskUnblockTime
+				needs to be updated too. */
+				if( xTimeToWake < xNextTaskUnblockTime )
+				{
+					xNextTaskUnblockTime = xTimeToWake;
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+	}
+	#else /* INCLUDE_vTaskSuspend */
+	{
+		/* Calculate the time at which the task should be woken if the event
+		does not occur.  This may overflow but this doesn't matter, the kernel
+		will manage it correctly. */
+		xTimeToWake = xConstTickCount + xTicksToWait;
+
+		/* The list item will be inserted in wake time order. */
+		listSET_LIST_ITEM_VALUE( &( pxCurrentTCB->xStateListItem ), xTimeToWake );
+
+		if( xTimeToWake < xConstTickCount )
+		{
+			/* Wake time has overflowed.  Place this item in the overflow list. */
+			vListInsert( pxOverflowDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+		}
+		else
+		{
+			/* The wake time has not overflowed, so the current block list is used. */
+			vListInsert( pxDelayedTaskList, &( pxCurrentTCB->xStateListItem ) );
+
+			/* If the task entering the blocked state was placed at the head of the
+			list of blocked tasks then xNextTaskUnblockTime needs to be updated
+			too. */
+			if( xTimeToWake < xNextTaskUnblockTime )
+			{
+				xNextTaskUnblockTime = xTimeToWake;
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+
+		/* Avoid compiler warning when INCLUDE_vTaskSuspend is not 1. */
+		( void ) xCanBlockIndefinitely;
+	}
+	#endif /* INCLUDE_vTaskSuspend */
+}
+
+
+#ifdef FREERTOS_MODULE_TEST
+	#include "tasks_test_access_functions.h"
+#endif
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/timers.c b/STM32F1/libraries/FreeRTOS900/utility/timers.c
new file mode 100644
index 000000000..d4a821a26
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/timers.c
@@ -0,0 +1,1092 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+/* Standard includes. */
+#include <stdlib.h>
+
+/* Defining MPU_WRAPPERS_INCLUDED_FROM_API_FILE prevents task.h from redefining
+all the API functions to use the MPU wrappers.  That should only be done when
+task.h is included from an application file. */
+#define MPU_WRAPPERS_INCLUDED_FROM_API_FILE
+
+#include "FreeRTOS.h"
+#include "task.h"
+#include "queue.h"
+#include "timers.h"
+
+#if ( INCLUDE_xTimerPendFunctionCall == 1 ) && ( configUSE_TIMERS == 0 )
+	#error configUSE_TIMERS must be set to 1 to make the xTimerPendFunctionCall() function available.
+#endif
+
+/* Lint e961 and e750 are suppressed as a MISRA exception justified because the
+MPU ports require MPU_WRAPPERS_INCLUDED_FROM_API_FILE to be defined for the
+header files above, but not in this file, in order to generate the correct
+privileged Vs unprivileged linkage and placement. */
+#undef MPU_WRAPPERS_INCLUDED_FROM_API_FILE /*lint !e961 !e750. */
+
+
+/* This entire source file will be skipped if the application is not configured
+to include software timer functionality.  This #if is closed at the very bottom
+of this file.  If you want to include software timer functionality then ensure
+configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#if ( configUSE_TIMERS == 1 )
+
+/* Misc definitions. */
+#define tmrNO_DELAY		( TickType_t ) 0U
+
+/* The definition of the timers themselves. */
+typedef struct tmrTimerControl
+{
+	const char				*pcTimerName;		/*<< Text name.  This is not used by the kernel, it is included simply to make debugging easier. */ /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	ListItem_t				xTimerListItem;		/*<< Standard linked list item as used by all kernel features for event management. */
+	TickType_t				xTimerPeriodInTicks;/*<< How quickly and often the timer expires. */
+	UBaseType_t				uxAutoReload;		/*<< Set to pdTRUE if the timer should be automatically restarted once expired.  Set to pdFALSE if the timer is, in effect, a one-shot timer. */
+	void 					*pvTimerID;			/*<< An ID to identify the timer.  This allows the timer to be identified when the same callback is used for multiple timers. */
+	TimerCallbackFunction_t	pxCallbackFunction;	/*<< The function that will be called when the timer expires. */
+	#if( configUSE_TRACE_FACILITY == 1 )
+		UBaseType_t			uxTimerNumber;		/*<< An ID assigned by trace tools such as FreeRTOS+Trace */
+	#endif
+
+	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
+		uint8_t 			ucStaticallyAllocated; /*<< Set to pdTRUE if the timer was created statically so no attempt is made to free the memory again if the timer is later deleted. */
+	#endif
+} xTIMER;
+
+/* The old xTIMER name is maintained above then typedefed to the new Timer_t
+name below to enable the use of older kernel aware debuggers. */
+typedef xTIMER Timer_t;
+
+/* The definition of messages that can be sent and received on the timer queue.
+Two types of message can be queued - messages that manipulate a software timer,
+and messages that request the execution of a non-timer related callback.  The
+two message types are defined in two separate structures, xTimerParametersType
+and xCallbackParametersType respectively. */
+typedef struct tmrTimerParameters
+{
+	TickType_t			xMessageValue;		/*<< An optional value used by a subset of commands, for example, when changing the period of a timer. */
+	Timer_t *			pxTimer;			/*<< The timer to which the command will be applied. */
+} TimerParameter_t;
+
+
+typedef struct tmrCallbackParameters
+{
+	PendedFunction_t	pxCallbackFunction;	/* << The callback function to execute. */
+	void *pvParameter1;						/* << The value that will be used as the callback functions first parameter. */
+	uint32_t ulParameter2;					/* << The value that will be used as the callback functions second parameter. */
+} CallbackParameters_t;
+
+/* The structure that contains the two message types, along with an identifier
+that is used to determine which message type is valid. */
+typedef struct tmrTimerQueueMessage
+{
+	BaseType_t			xMessageID;			/*<< The command being sent to the timer service task. */
+	union
+	{
+		TimerParameter_t xTimerParameters;
+
+		/* Don't include xCallbackParameters if it is not going to be used as
+		it makes the structure (and therefore the timer queue) larger. */
+		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+			CallbackParameters_t xCallbackParameters;
+		#endif /* INCLUDE_xTimerPendFunctionCall */
+	} u;
+} DaemonTaskMessage_t;
+
+/*lint -e956 A manual analysis and inspection has been used to determine which
+static variables must be declared volatile. */
+
+/* The list in which active timers are stored.  Timers are referenced in expire
+time order, with the nearest expiry time at the front of the list.  Only the
+timer service task is allowed to access these lists. */
+PRIVILEGED_DATA static List_t xActiveTimerList1;
+PRIVILEGED_DATA static List_t xActiveTimerList2;
+PRIVILEGED_DATA static List_t *pxCurrentTimerList;
+PRIVILEGED_DATA static List_t *pxOverflowTimerList;
+
+/* A queue that is used to send commands to the timer service task. */
+PRIVILEGED_DATA static QueueHandle_t xTimerQueue = NULL;
+PRIVILEGED_DATA static TaskHandle_t xTimerTaskHandle = NULL;
+
+/*lint +e956 */
+
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	/* If static allocation is supported then the application must provide the
+	following callback function - which enables the application to optionally
+	provide the memory that will be used by the timer task as the task's stack
+	and TCB. */
+	extern void vApplicationGetTimerTaskMemory( StaticTask_t **ppxTimerTaskTCBBuffer, StackType_t **ppxTimerTaskStackBuffer, uint32_t *pulTimerTaskStackSize );
+
+#endif
+
+/*
+ * Initialise the infrastructure used by the timer service task if it has not
+ * been initialised already.
+ */
+static void prvCheckForValidListAndQueue( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * The timer service task (daemon).  Timer functionality is controlled by this
+ * task.  Other tasks communicate with the timer service task using the
+ * xTimerQueue queue.
+ */
+static void prvTimerTask( void *pvParameters ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called by the timer service task to interpret and process a command it
+ * received on the timer queue.
+ */
+static void prvProcessReceivedCommands( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Insert the timer into either xActiveTimerList1, or xActiveTimerList2,
+ * depending on if the expire time causes a timer counter overflow.
+ */
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime ) PRIVILEGED_FUNCTION;
+
+/*
+ * An active timer has reached its expire time.  Reload the timer if it is an
+ * auto reload timer, then call its callback.
+ */
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow ) PRIVILEGED_FUNCTION;
+
+/*
+ * The tick count has overflowed.  Switch the timer lists after ensuring the
+ * current timer list does not still reference some timers.
+ */
+static void prvSwitchTimerLists( void ) PRIVILEGED_FUNCTION;
+
+/*
+ * Obtain the current tick count, setting *pxTimerListsWereSwitched to pdTRUE
+ * if a tick count overflow occurred since prvSampleTimeNow() was last called.
+ */
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched ) PRIVILEGED_FUNCTION;
+
+/*
+ * If the timer list contains any active timers then return the expire time of
+ * the timer that will expire first and set *pxListWasEmpty to false.  If the
+ * timer list does not contain any timers then return 0 and set *pxListWasEmpty
+ * to pdTRUE.
+ */
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * If a timer has expired, process it.  Otherwise, block the timer service task
+ * until either a timer does expire or a command is received.
+ */
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty ) PRIVILEGED_FUNCTION;
+
+/*
+ * Called after a Timer_t structure has been allocated either statically or
+ * dynamically to fill in the structure's members.
+ */
+static void prvInitialiseNewTimer(	const char * const pcTimerName,
+									const TickType_t xTimerPeriodInTicks,
+									const UBaseType_t uxAutoReload,
+									void * const pvTimerID,
+									TimerCallbackFunction_t pxCallbackFunction,
+									Timer_t *pxNewTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerCreateTimerTask( void )
+{
+BaseType_t xReturn = pdFAIL;
+
+	/* This function is called when the scheduler is started if
+	configUSE_TIMERS is set to 1.  Check that the infrastructure used by the
+	timer service task has been created/initialised.  If timers have already
+	been created then the initialisation will already have been performed. */
+	prvCheckForValidListAndQueue();
+
+	if( xTimerQueue != NULL )
+	{
+		#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+		{
+			StaticTask_t *pxTimerTaskTCBBuffer = NULL;
+			StackType_t *pxTimerTaskStackBuffer = NULL;
+			uint32_t ulTimerTaskStackSize;
+
+			vApplicationGetTimerTaskMemory( &pxTimerTaskTCBBuffer, &pxTimerTaskStackBuffer, &ulTimerTaskStackSize );
+			xTimerTaskHandle = xTaskCreateStatic(	prvTimerTask,
+													"Tmr Svc",
+													ulTimerTaskStackSize,
+													NULL,
+													( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+													pxTimerTaskStackBuffer,
+													pxTimerTaskTCBBuffer );
+
+			if( xTimerTaskHandle != NULL )
+			{
+				xReturn = pdPASS;
+			}
+		}
+		#else
+		{
+			xReturn = xTaskCreate(	prvTimerTask,
+									"Tmr Svc",
+									configTIMER_TASK_STACK_DEPTH,
+									NULL,
+									( ( UBaseType_t ) configTIMER_TASK_PRIORITY ) | portPRIVILEGE_BIT,
+									&xTimerTaskHandle );
+		}
+		#endif /* configSUPPORT_STATIC_ALLOCATION */
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	configASSERT( xReturn );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+
+	TimerHandle_t xTimerCreate(	const char * const pcTimerName,
+								const TickType_t xTimerPeriodInTicks,
+								const UBaseType_t uxAutoReload,
+								void * const pvTimerID,
+								TimerCallbackFunction_t pxCallbackFunction ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	Timer_t *pxNewTimer;
+
+		pxNewTimer = ( Timer_t * ) pvPortMalloc( sizeof( Timer_t ) );
+
+		if( pxNewTimer != NULL )
+		{
+			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* Timers can be created statically or dynamically, so note this
+				timer was created dynamically in case the timer is later
+				deleted. */
+				pxNewTimer->ucStaticallyAllocated = pdFALSE;
+			}
+			#endif /* configSUPPORT_STATIC_ALLOCATION */
+		}
+
+		return pxNewTimer;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+
+	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,
+										const TickType_t xTimerPeriodInTicks,
+										const UBaseType_t uxAutoReload,
+										void * const pvTimerID,
+										TimerCallbackFunction_t pxCallbackFunction,
+										StaticTimer_t *pxTimerBuffer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+	{
+	Timer_t *pxNewTimer;
+
+		#if( configASSERT_DEFINED == 1 )
+		{
+			/* Sanity check that the size of the structure used to declare a
+			variable of type StaticTimer_t equals the size of the real timer
+			structures. */
+			volatile size_t xSize = sizeof( StaticTimer_t );
+			configASSERT( xSize == sizeof( Timer_t ) );
+		}
+		#endif /* configASSERT_DEFINED */
+
+		/* A pointer to a StaticTimer_t structure MUST be provided, use it. */
+		configASSERT( pxTimerBuffer );
+		pxNewTimer = ( Timer_t * ) pxTimerBuffer; /*lint !e740 Unusual cast is ok as the structures are designed to have the same alignment, and the size is checked by an assert. */
+
+		if( pxNewTimer != NULL )
+		{
+			prvInitialiseNewTimer( pcTimerName, xTimerPeriodInTicks, uxAutoReload, pvTimerID, pxCallbackFunction, pxNewTimer );
+
+			#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+			{
+				/* Timers can be created statically or dynamically so note this
+				timer was created statically in case it is later deleted. */
+				pxNewTimer->ucStaticallyAllocated = pdTRUE;
+			}
+			#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+		}
+
+		return pxNewTimer;
+	}
+
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+/*-----------------------------------------------------------*/
+
+static void prvInitialiseNewTimer(	const char * const pcTimerName,
+									const TickType_t xTimerPeriodInTicks,
+									const UBaseType_t uxAutoReload,
+									void * const pvTimerID,
+									TimerCallbackFunction_t pxCallbackFunction,
+									Timer_t *pxNewTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+	/* 0 is not a valid value for xTimerPeriodInTicks. */
+	configASSERT( ( xTimerPeriodInTicks > 0 ) );
+
+	if( pxNewTimer != NULL )
+	{
+		/* Ensure the infrastructure used by the timer service task has been
+		created/initialised. */
+		prvCheckForValidListAndQueue();
+
+		/* Initialise the timer structure members using the function
+		parameters. */
+		pxNewTimer->pcTimerName = pcTimerName;
+		pxNewTimer->xTimerPeriodInTicks = xTimerPeriodInTicks;
+		pxNewTimer->uxAutoReload = uxAutoReload;
+		pxNewTimer->pvTimerID = pvTimerID;
+		pxNewTimer->pxCallbackFunction = pxCallbackFunction;
+		vListInitialiseItem( &( pxNewTimer->xTimerListItem ) );
+		traceTIMER_CREATE( pxNewTimer );
+	}
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait )
+{
+BaseType_t xReturn = pdFAIL;
+DaemonTaskMessage_t xMessage;
+
+	configASSERT( xTimer );
+
+	/* Send a message to the timer service task to perform a particular action
+	on a particular timer definition. */
+	if( xTimerQueue != NULL )
+	{
+		/* Send a command to the timer service task to start the xTimer timer. */
+		xMessage.xMessageID = xCommandID;
+		xMessage.u.xTimerParameters.xMessageValue = xOptionalValue;
+		xMessage.u.xTimerParameters.pxTimer = ( Timer_t * ) xTimer;
+
+		if( xCommandID < tmrFIRST_FROM_ISR_COMMAND )
+		{
+			if( xTaskGetSchedulerState() == taskSCHEDULER_RUNNING )
+			{
+				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+			}
+			else
+			{
+				xReturn = xQueueSendToBack( xTimerQueue, &xMessage, tmrNO_DELAY );
+			}
+		}
+		else
+		{
+			xReturn = xQueueSendToBackFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+		}
+
+		traceTIMER_COMMAND_SEND( xTimer, xCommandID, xOptionalValue, xReturn );
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void )
+{
+	/* If xTimerGetTimerDaemonTaskHandle() is called before the scheduler has been
+	started, then xTimerTaskHandle will be NULL. */
+	configASSERT( ( xTimerTaskHandle != NULL ) );
+	return xTimerTaskHandle;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTimerGetPeriod( TimerHandle_t xTimer )
+{
+Timer_t *pxTimer = ( Timer_t * ) xTimer;
+
+	configASSERT( xTimer );
+	return pxTimer->xTimerPeriodInTicks;
+}
+/*-----------------------------------------------------------*/
+
+TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer )
+{
+Timer_t * pxTimer = ( Timer_t * ) xTimer;
+TickType_t xReturn;
+
+	configASSERT( xTimer );
+	xReturn = listGET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ) );
+	return xReturn;
+}
+/*-----------------------------------------------------------*/
+
+const char * pcTimerGetName( TimerHandle_t xTimer ) /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+{
+Timer_t *pxTimer = ( Timer_t * ) xTimer;
+
+	configASSERT( xTimer );
+	return pxTimer->pcTimerName;
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessExpiredTimer( const TickType_t xNextExpireTime, const TickType_t xTimeNow )
+{
+BaseType_t xResult;
+Timer_t * const pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );
+
+	/* Remove the timer from the list of active timers.  A check has already
+	been performed to ensure the list is not empty. */
+	( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+	traceTIMER_EXPIRED( pxTimer );
+
+	/* If the timer is an auto reload timer then calculate the next
+	expiry time and re-insert the timer in the list of active timers. */
+	if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )
+	{
+		/* The timer is inserted into a list using a time relative to anything
+		other than the current time.  It will therefore be inserted into the
+		correct list relative to the time this task thinks it is now. */
+		if( prvInsertTimerInActiveList( pxTimer, ( xNextExpireTime + pxTimer->xTimerPeriodInTicks ), xTimeNow, xNextExpireTime ) != pdFALSE )
+		{
+			/* The timer expired before it was added to the active timer
+			list.  Reload it now.  */
+			xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+			configASSERT( xResult );
+			( void ) xResult;
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	else
+	{
+		mtCOVERAGE_TEST_MARKER();
+	}
+
+	/* Call the timer callback. */
+	pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+}
+/*-----------------------------------------------------------*/
+
+static void prvTimerTask( void *pvParameters )
+{
+TickType_t xNextExpireTime;
+BaseType_t xListWasEmpty;
+
+	/* Just to avoid compiler warnings. */
+	( void ) pvParameters;
+
+	#if( configUSE_DAEMON_TASK_STARTUP_HOOK == 1 )
+	{
+		extern void vApplicationDaemonTaskStartupHook( void );
+
+		/* Allow the application writer to execute some code in the context of
+		this task at the point the task starts executing.  This is useful if the
+		application includes initialisation code that would benefit from
+		executing after the scheduler has been started. */
+		vApplicationDaemonTaskStartupHook();
+	}
+	#endif /* configUSE_DAEMON_TASK_STARTUP_HOOK */
+
+	for( ;; )
+	{
+		/* Query the timers list to see if it contains any timers, and if so,
+		obtain the time at which the next timer will expire. */
+		xNextExpireTime = prvGetNextExpireTime( &xListWasEmpty );
+
+		/* If a timer has expired, process it.  Otherwise, block this task
+		until either a timer does expire, or a command is received. */
+		prvProcessTimerOrBlockTask( xNextExpireTime, xListWasEmpty );
+
+		/* Empty the command queue. */
+		prvProcessReceivedCommands();
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvProcessTimerOrBlockTask( const TickType_t xNextExpireTime, BaseType_t xListWasEmpty )
+{
+TickType_t xTimeNow;
+BaseType_t xTimerListsWereSwitched;
+
+	vTaskSuspendAll();
+	{
+		/* Obtain the time now to make an assessment as to whether the timer
+		has expired or not.  If obtaining the time causes the lists to switch
+		then don't process this timer as any timers that remained in the list
+		when the lists were switched will have been processed within the
+		prvSampleTimeNow() function. */
+		xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+		if( xTimerListsWereSwitched == pdFALSE )
+		{
+			/* The tick count has not overflowed, has the timer expired? */
+			if( ( xListWasEmpty == pdFALSE ) && ( xNextExpireTime <= xTimeNow ) )
+			{
+				( void ) xTaskResumeAll();
+				prvProcessExpiredTimer( xNextExpireTime, xTimeNow );
+			}
+			else
+			{
+				/* The tick count has not overflowed, and the next expire
+				time has not been reached yet.  This task should therefore
+				block to wait for the next expire time or a command to be
+				received - whichever comes first.  The following line cannot
+				be reached unless xNextExpireTime > xTimeNow, except in the
+				case when the current timer list is empty. */
+				if( xListWasEmpty != pdFALSE )
+				{
+					/* The current timer list is empty - is the overflow list
+					also empty? */
+					xListWasEmpty = listLIST_IS_EMPTY( pxOverflowTimerList );
+				}
+
+				vQueueWaitForMessageRestricted( xTimerQueue, ( xNextExpireTime - xTimeNow ), xListWasEmpty );
+
+				if( xTaskResumeAll() == pdFALSE )
+				{
+					/* Yield to wait for either a command to arrive, or the
+					block time to expire.  If a command arrived between the
+					critical section being exited and this yield then the yield
+					will not cause the task to block. */
+					portYIELD_WITHIN_API();
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+		}
+		else
+		{
+			( void ) xTaskResumeAll();
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvGetNextExpireTime( BaseType_t * const pxListWasEmpty )
+{
+TickType_t xNextExpireTime;
+
+	/* Timers are listed in expiry time order, with the head of the list
+	referencing the task that will expire first.  Obtain the time at which
+	the timer with the nearest expiry time will expire.  If there are no
+	active timers then just set the next expire time to 0.  That will cause
+	this task to unblock when the tick count overflows, at which point the
+	timer lists will be switched and the next expiry time can be
+	re-assessed.  */
+	*pxListWasEmpty = listLIST_IS_EMPTY( pxCurrentTimerList );
+	if( *pxListWasEmpty == pdFALSE )
+	{
+		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+	}
+	else
+	{
+		/* Ensure the task unblocks when the tick count rolls over. */
+		xNextExpireTime = ( TickType_t ) 0U;
+	}
+
+	return xNextExpireTime;
+}
+/*-----------------------------------------------------------*/
+
+static TickType_t prvSampleTimeNow( BaseType_t * const pxTimerListsWereSwitched )
+{
+TickType_t xTimeNow;
+PRIVILEGED_DATA static TickType_t xLastTime = ( TickType_t ) 0U; /*lint !e956 Variable is only accessible to one task. */
+
+	xTimeNow = xTaskGetTickCount();
+
+	if( xTimeNow < xLastTime )
+	{
+		prvSwitchTimerLists();
+		*pxTimerListsWereSwitched = pdTRUE;
+	}
+	else
+	{
+		*pxTimerListsWereSwitched = pdFALSE;
+	}
+
+	xLastTime = xTimeNow;
+
+	return xTimeNow;
+}
+/*-----------------------------------------------------------*/
+
+static BaseType_t prvInsertTimerInActiveList( Timer_t * const pxTimer, const TickType_t xNextExpiryTime, const TickType_t xTimeNow, const TickType_t xCommandTime )
+{
+BaseType_t xProcessTimerNow = pdFALSE;
+
+	listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xNextExpiryTime );
+	listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+
+	if( xNextExpiryTime <= xTimeNow )
+	{
+		/* Has the expiry time elapsed between the command to start/reset a
+		timer was issued, and the time the command was processed? */
+		if( ( ( TickType_t ) ( xTimeNow - xCommandTime ) ) >= pxTimer->xTimerPeriodInTicks ) /*lint !e961 MISRA exception as the casts are only redundant for some ports. */
+		{
+			/* The time between a command being issued and the command being
+			processed actually exceeds the timers period.  */
+			xProcessTimerNow = pdTRUE;
+		}
+		else
+		{
+			vListInsert( pxOverflowTimerList, &( pxTimer->xTimerListItem ) );
+		}
+	}
+	else
+	{
+		if( ( xTimeNow < xCommandTime ) && ( xNextExpiryTime >= xCommandTime ) )
+		{
+			/* If, since the command was issued, the tick count has overflowed
+			but the expiry time has not, then the timer must have already passed
+			its expiry time and should be processed immediately. */
+			xProcessTimerNow = pdTRUE;
+		}
+		else
+		{
+			vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+		}
+	}
+
+	return xProcessTimerNow;
+}
+/*-----------------------------------------------------------*/
+
+static void	prvProcessReceivedCommands( void )
+{
+DaemonTaskMessage_t xMessage;
+Timer_t *pxTimer;
+BaseType_t xTimerListsWereSwitched, xResult;
+TickType_t xTimeNow;
+
+	while( xQueueReceive( xTimerQueue, &xMessage, tmrNO_DELAY ) != pdFAIL ) /*lint !e603 xMessage does not have to be initialised as it is passed out, not in, and it is not used unless xQueueReceive() returns pdTRUE. */
+	{
+		#if ( INCLUDE_xTimerPendFunctionCall == 1 )
+		{
+			/* Negative commands are pended function calls rather than timer
+			commands. */
+			if( xMessage.xMessageID < ( BaseType_t ) 0 )
+			{
+				const CallbackParameters_t * const pxCallback = &( xMessage.u.xCallbackParameters );
+
+				/* The timer uses the xCallbackParameters member to request a
+				callback be executed.  Check the callback is not NULL. */
+				configASSERT( pxCallback );
+
+				/* Call the function. */
+				pxCallback->pxCallbackFunction( pxCallback->pvParameter1, pxCallback->ulParameter2 );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+		}
+		#endif /* INCLUDE_xTimerPendFunctionCall */
+
+		/* Commands that are positive are timer commands rather than pended
+		function calls. */
+		if( xMessage.xMessageID >= ( BaseType_t ) 0 )
+		{
+			/* The messages uses the xTimerParameters member to work on a
+			software timer. */
+			pxTimer = xMessage.u.xTimerParameters.pxTimer;
+
+			if( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) == pdFALSE )
+			{
+				/* The timer is in a list, remove it. */
+				( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+			}
+			else
+			{
+				mtCOVERAGE_TEST_MARKER();
+			}
+
+			traceTIMER_COMMAND_RECEIVED( pxTimer, xMessage.xMessageID, xMessage.u.xTimerParameters.xMessageValue );
+
+			/* In this case the xTimerListsWereSwitched parameter is not used, but
+			it must be present in the function call.  prvSampleTimeNow() must be
+			called after the message is received from xTimerQueue so there is no
+			possibility of a higher priority task adding a message to the message
+			queue with a time that is ahead of the timer daemon task (because it
+			pre-empted the timer daemon task after the xTimeNow value was set). */
+			xTimeNow = prvSampleTimeNow( &xTimerListsWereSwitched );
+
+			switch( xMessage.xMessageID )
+			{
+				case tmrCOMMAND_START :
+			    case tmrCOMMAND_START_FROM_ISR :
+			    case tmrCOMMAND_RESET :
+			    case tmrCOMMAND_RESET_FROM_ISR :
+				case tmrCOMMAND_START_DONT_TRACE :
+					/* Start or restart a timer. */
+					if( prvInsertTimerInActiveList( pxTimer,  xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, xTimeNow, xMessage.u.xTimerParameters.xMessageValue ) != pdFALSE )
+					{
+						/* The timer expired before it was added to the active
+						timer list.  Process it now. */
+						pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+						traceTIMER_EXPIRED( pxTimer );
+
+						if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )
+						{
+							xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xMessage.u.xTimerParameters.xMessageValue + pxTimer->xTimerPeriodInTicks, NULL, tmrNO_DELAY );
+							configASSERT( xResult );
+							( void ) xResult;
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					else
+					{
+						mtCOVERAGE_TEST_MARKER();
+					}
+					break;
+
+				case tmrCOMMAND_STOP :
+				case tmrCOMMAND_STOP_FROM_ISR :
+					/* The timer has already been removed from the active list.
+					There is nothing to do here. */
+					break;
+
+				case tmrCOMMAND_CHANGE_PERIOD :
+				case tmrCOMMAND_CHANGE_PERIOD_FROM_ISR :
+					pxTimer->xTimerPeriodInTicks = xMessage.u.xTimerParameters.xMessageValue;
+					configASSERT( ( pxTimer->xTimerPeriodInTicks > 0 ) );
+
+					/* The new period does not really have a reference, and can
+					be longer or shorter than the old one.  The command time is
+					therefore set to the current time, and as the period cannot
+					be zero the next expiry time can only be in the future,
+					meaning (unlike for the xTimerStart() case above) there is
+					no fail case that needs to be handled here. */
+					( void ) prvInsertTimerInActiveList( pxTimer, ( xTimeNow + pxTimer->xTimerPeriodInTicks ), xTimeNow, xTimeNow );
+					break;
+
+				case tmrCOMMAND_DELETE :
+					/* The timer has already been removed from the active list,
+					just free up the memory if the memory was dynamically
+					allocated. */
+					#if( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 0 ) )
+					{
+						/* The timer can only have been allocated dynamically -
+						free it again. */
+						vPortFree( pxTimer );
+					}
+					#elif( ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) && ( configSUPPORT_STATIC_ALLOCATION == 1 ) )
+					{
+						/* The timer could have been allocated statically or
+						dynamically, so check before attempting to free the
+						memory. */
+						if( pxTimer->ucStaticallyAllocated == ( uint8_t ) pdFALSE )
+						{
+							vPortFree( pxTimer );
+						}
+						else
+						{
+							mtCOVERAGE_TEST_MARKER();
+						}
+					}
+					#endif /* configSUPPORT_DYNAMIC_ALLOCATION */
+					break;
+
+				default	:
+					/* Don't expect to get here. */
+					break;
+			}
+		}
+	}
+}
+/*-----------------------------------------------------------*/
+
+static void prvSwitchTimerLists( void )
+{
+TickType_t xNextExpireTime, xReloadTime;
+List_t *pxTemp;
+Timer_t *pxTimer;
+BaseType_t xResult;
+
+	/* The tick count has overflowed.  The timer lists must be switched.
+	If there are any timers still referenced from the current timer list
+	then they must have expired and should be processed before the lists
+	are switched. */
+	while( listLIST_IS_EMPTY( pxCurrentTimerList ) == pdFALSE )
+	{
+		xNextExpireTime = listGET_ITEM_VALUE_OF_HEAD_ENTRY( pxCurrentTimerList );
+
+		/* Remove the timer from the list. */
+		pxTimer = ( Timer_t * ) listGET_OWNER_OF_HEAD_ENTRY( pxCurrentTimerList );
+		( void ) uxListRemove( &( pxTimer->xTimerListItem ) );
+		traceTIMER_EXPIRED( pxTimer );
+
+		/* Execute its callback, then send a command to restart the timer if
+		it is an auto-reload timer.  It cannot be restarted here as the lists
+		have not yet been switched. */
+		pxTimer->pxCallbackFunction( ( TimerHandle_t ) pxTimer );
+
+		if( pxTimer->uxAutoReload == ( UBaseType_t ) pdTRUE )
+		{
+			/* Calculate the reload value, and if the reload value results in
+			the timer going into the same timer list then it has already expired
+			and the timer should be re-inserted into the current list so it is
+			processed again within this loop.  Otherwise a command should be sent
+			to restart the timer to ensure it is only inserted into a list after
+			the lists have been swapped. */
+			xReloadTime = ( xNextExpireTime + pxTimer->xTimerPeriodInTicks );
+			if( xReloadTime > xNextExpireTime )
+			{
+				listSET_LIST_ITEM_VALUE( &( pxTimer->xTimerListItem ), xReloadTime );
+				listSET_LIST_ITEM_OWNER( &( pxTimer->xTimerListItem ), pxTimer );
+				vListInsert( pxCurrentTimerList, &( pxTimer->xTimerListItem ) );
+			}
+			else
+			{
+				xResult = xTimerGenericCommand( pxTimer, tmrCOMMAND_START_DONT_TRACE, xNextExpireTime, NULL, tmrNO_DELAY );
+				configASSERT( xResult );
+				( void ) xResult;
+			}
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+
+	pxTemp = pxCurrentTimerList;
+	pxCurrentTimerList = pxOverflowTimerList;
+	pxOverflowTimerList = pxTemp;
+}
+/*-----------------------------------------------------------*/
+
+static void prvCheckForValidListAndQueue( void )
+{
+	/* Check that the list from which active timers are referenced, and the
+	queue used to communicate with the timer service, have been
+	initialised. */
+	taskENTER_CRITICAL();
+	{
+		if( xTimerQueue == NULL )
+		{
+			vListInitialise( &xActiveTimerList1 );
+			vListInitialise( &xActiveTimerList2 );
+			pxCurrentTimerList = &xActiveTimerList1;
+			pxOverflowTimerList = &xActiveTimerList2;
+
+			#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+			{
+				/* The timer queue is allocated statically in case
+				configSUPPORT_DYNAMIC_ALLOCATION is 0. */
+				static StaticQueue_t xStaticTimerQueue;
+				static uint8_t ucStaticTimerQueueStorage[ configTIMER_QUEUE_LENGTH * sizeof( DaemonTaskMessage_t ) ];
+
+				xTimerQueue = xQueueCreateStatic( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ), &( ucStaticTimerQueueStorage[ 0 ] ), &xStaticTimerQueue );
+			}
+			#else
+			{
+				xTimerQueue = xQueueCreate( ( UBaseType_t ) configTIMER_QUEUE_LENGTH, sizeof( DaemonTaskMessage_t ) );
+			}
+			#endif
+
+			#if ( configQUEUE_REGISTRY_SIZE > 0 )
+			{
+				if( xTimerQueue != NULL )
+				{
+					vQueueAddToRegistry( xTimerQueue, "TmrQ" );
+				}
+				else
+				{
+					mtCOVERAGE_TEST_MARKER();
+				}
+			}
+			#endif /* configQUEUE_REGISTRY_SIZE */
+		}
+		else
+		{
+			mtCOVERAGE_TEST_MARKER();
+		}
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer )
+{
+BaseType_t xTimerIsInActiveList;
+Timer_t *pxTimer = ( Timer_t * ) xTimer;
+
+	configASSERT( xTimer );
+
+	/* Is the timer in the list of active timers? */
+	taskENTER_CRITICAL();
+	{
+		/* Checking to see if it is in the NULL list in effect checks to see if
+		it is referenced from either the current or the overflow timer lists in
+		one go, but the logic has to be reversed, hence the '!'. */
+		xTimerIsInActiveList = ( BaseType_t ) !( listIS_CONTAINED_WITHIN( NULL, &( pxTimer->xTimerListItem ) ) );
+	}
+	taskEXIT_CRITICAL();
+
+	return xTimerIsInActiveList;
+} /*lint !e818 Can't be pointer to const due to the typedef. */
+/*-----------------------------------------------------------*/
+
+void *pvTimerGetTimerID( const TimerHandle_t xTimer )
+{
+Timer_t * const pxTimer = ( Timer_t * ) xTimer;
+void *pvReturn;
+
+	configASSERT( xTimer );
+
+	taskENTER_CRITICAL();
+	{
+		pvReturn = pxTimer->pvTimerID;
+	}
+	taskEXIT_CRITICAL();
+
+	return pvReturn;
+}
+/*-----------------------------------------------------------*/
+
+void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID )
+{
+Timer_t * const pxTimer = ( Timer_t * ) xTimer;
+
+	configASSERT( xTimer );
+
+	taskENTER_CRITICAL();
+	{
+		pxTimer->pvTimerID = pvNewID;
+	}
+	taskEXIT_CRITICAL();
+}
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTimerPendFunctionCall == 1 )
+
+	BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken )
+	{
+	DaemonTaskMessage_t xMessage;
+	BaseType_t xReturn;
+
+		/* Complete the message with the function parameters and post it to the
+		daemon task. */
+		xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR;
+		xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+		xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+		xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+		xReturn = xQueueSendFromISR( xTimerQueue, &xMessage, pxHigherPriorityTaskWoken );
+
+		tracePEND_FUNC_CALL_FROM_ISR( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+#if( INCLUDE_xTimerPendFunctionCall == 1 )
+
+	BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait )
+	{
+	DaemonTaskMessage_t xMessage;
+	BaseType_t xReturn;
+
+		/* This function can only be called after a timer has been created or
+		after the scheduler has been started because, until then, the timer
+		queue does not exist. */
+		configASSERT( xTimerQueue );
+
+		/* Complete the message with the function parameters and post it to the
+		daemon task. */
+		xMessage.xMessageID = tmrCOMMAND_EXECUTE_CALLBACK;
+		xMessage.u.xCallbackParameters.pxCallbackFunction = xFunctionToPend;
+		xMessage.u.xCallbackParameters.pvParameter1 = pvParameter1;
+		xMessage.u.xCallbackParameters.ulParameter2 = ulParameter2;
+
+		xReturn = xQueueSendToBack( xTimerQueue, &xMessage, xTicksToWait );
+
+		tracePEND_FUNC_CALL( xFunctionToPend, pvParameter1, ulParameter2, xReturn );
+
+		return xReturn;
+	}
+
+#endif /* INCLUDE_xTimerPendFunctionCall */
+/*-----------------------------------------------------------*/
+
+/* This entire source file will be skipped if the application is not configured
+to include software timer functionality.  If you want to include software timer
+functionality then ensure configUSE_TIMERS is set to 1 in FreeRTOSConfig.h. */
+#endif /* configUSE_TIMERS == 1 */
+
+
+
diff --git a/STM32F1/libraries/FreeRTOS900/utility/timers.h b/STM32F1/libraries/FreeRTOS900/utility/timers.h
new file mode 100644
index 000000000..798c955bb
--- /dev/null
+++ b/STM32F1/libraries/FreeRTOS900/utility/timers.h
@@ -0,0 +1,1314 @@
+/*
+    FreeRTOS V9.0.0 - Copyright (C) 2016 Real Time Engineers Ltd.
+    All rights reserved
+
+    VISIT http://www.FreeRTOS.org TO ENSURE YOU ARE USING THE LATEST VERSION.
+
+    This file is part of the FreeRTOS distribution.
+
+    FreeRTOS is free software; you can redistribute it and/or modify it under
+    the terms of the GNU General Public License (version 2) as published by the
+    Free Software Foundation >>>> AND MODIFIED BY <<<< the FreeRTOS exception.
+
+    ***************************************************************************
+    >>!   NOTE: The modification to the GPL is included to allow you to     !<<
+    >>!   distribute a combined work that includes FreeRTOS without being   !<<
+    >>!   obliged to provide the source code for proprietary components     !<<
+    >>!   outside of the FreeRTOS kernel.                                   !<<
+    ***************************************************************************
+
+    FreeRTOS is distributed in the hope that it will be useful, but WITHOUT ANY
+    WARRANTY; without even the implied warranty of MERCHANTABILITY or FITNESS
+    FOR A PARTICULAR PURPOSE.  Full license text is available on the following
+    link: http://www.freertos.org/a00114.html
+
+    ***************************************************************************
+     *                                                                       *
+     *    FreeRTOS provides completely free yet professionally developed,    *
+     *    robust, strictly quality controlled, supported, and cross          *
+     *    platform software that is more than just the market leader, it     *
+     *    is the industry's de facto standard.                               *
+     *                                                                       *
+     *    Help yourself get started quickly while simultaneously helping     *
+     *    to support the FreeRTOS project by purchasing a FreeRTOS           *
+     *    tutorial book, reference manual, or both:                          *
+     *    http://www.FreeRTOS.org/Documentation                              *
+     *                                                                       *
+    ***************************************************************************
+
+    http://www.FreeRTOS.org/FAQHelp.html - Having a problem?  Start by reading
+    the FAQ page "My application does not run, what could be wrong?".  Have you
+    defined configASSERT()?
+
+    http://www.FreeRTOS.org/support - In return for receiving this top quality
+    embedded software for free we request you assist our global community by
+    participating in the support forum.
+
+    http://www.FreeRTOS.org/training - Investing in training allows your team to
+    be as productive as possible as early as possible.  Now you can receive
+    FreeRTOS training directly from Richard Barry, CEO of Real Time Engineers
+    Ltd, and the world's leading authority on the world's leading RTOS.
+
+    http://www.FreeRTOS.org/plus - A selection of FreeRTOS ecosystem products,
+    including FreeRTOS+Trace - an indispensable productivity tool, a DOS
+    compatible FAT file system, and our tiny thread aware UDP/IP stack.
+
+    http://www.FreeRTOS.org/labs - Where new FreeRTOS products go to incubate.
+    Come and try FreeRTOS+TCP, our new open source TCP/IP stack for FreeRTOS.
+
+    http://www.OpenRTOS.com - Real Time Engineers ltd. license FreeRTOS to High
+    Integrity Systems ltd. to sell under the OpenRTOS brand.  Low cost OpenRTOS
+    licenses offer ticketed support, indemnification and commercial middleware.
+
+    http://www.SafeRTOS.com - High Integrity Systems also provide a safety
+    engineered and independently SIL3 certified version for use in safety and
+    mission critical applications that require provable dependability.
+
+    1 tab == 4 spaces!
+*/
+
+
+#ifndef TIMERS_H
+#define TIMERS_H
+
+#ifndef INC_FREERTOS_H
+	#error "include FreeRTOS.h must appear in source files before include timers.h"
+#endif
+
+/*lint -e537 This headers are only multiply included if the application code
+happens to also be including task.h. */
+#include "task.h"
+/*lint +e537 */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*-----------------------------------------------------------
+ * MACROS AND DEFINITIONS
+ *----------------------------------------------------------*/
+
+/* IDs for commands that can be sent/received on the timer queue.  These are to
+be used solely through the macros that make up the public software timer API,
+as defined below.  The commands that are sent from interrupts must use the
+highest numbers as tmrFIRST_FROM_ISR_COMMAND is used to determine if the task
+or interrupt version of the queue send function should be used. */
+#define tmrCOMMAND_EXECUTE_CALLBACK_FROM_ISR 	( ( BaseType_t ) -2 )
+#define tmrCOMMAND_EXECUTE_CALLBACK				( ( BaseType_t ) -1 )
+#define tmrCOMMAND_START_DONT_TRACE				( ( BaseType_t ) 0 )
+#define tmrCOMMAND_START					    ( ( BaseType_t ) 1 )
+#define tmrCOMMAND_RESET						( ( BaseType_t ) 2 )
+#define tmrCOMMAND_STOP							( ( BaseType_t ) 3 )
+#define tmrCOMMAND_CHANGE_PERIOD				( ( BaseType_t ) 4 )
+#define tmrCOMMAND_DELETE						( ( BaseType_t ) 5 )
+
+#define tmrFIRST_FROM_ISR_COMMAND				( ( BaseType_t ) 6 )
+#define tmrCOMMAND_START_FROM_ISR				( ( BaseType_t ) 6 )
+#define tmrCOMMAND_RESET_FROM_ISR				( ( BaseType_t ) 7 )
+#define tmrCOMMAND_STOP_FROM_ISR				( ( BaseType_t ) 8 )
+#define tmrCOMMAND_CHANGE_PERIOD_FROM_ISR		( ( BaseType_t ) 9 )
+
+
+/**
+ * Type by which software timers are referenced.  For example, a call to
+ * xTimerCreate() returns an TimerHandle_t variable that can then be used to
+ * reference the subject timer in calls to other software timer API functions
+ * (for example, xTimerStart(), xTimerReset(), etc.).
+ */
+typedef void * TimerHandle_t;
+
+/*
+ * Defines the prototype to which timer callback functions must conform.
+ */
+typedef void (*TimerCallbackFunction_t)( TimerHandle_t xTimer );
+
+/*
+ * Defines the prototype to which functions used with the
+ * xTimerPendFunctionCallFromISR() function must conform.
+ */
+typedef void (*PendedFunction_t)( void *, uint32_t );
+
+/**
+ * TimerHandle_t xTimerCreate( 	const char * const pcTimerName,
+ * 								TickType_t xTimerPeriodInTicks,
+ * 								UBaseType_t uxAutoReload,
+ * 								void * pvTimerID,
+ * 								TimerCallbackFunction_t pxCallbackFunction );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored.  If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer.  xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is	"void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @return If the timer is successfully created then a handle to the newly
+ * created timer is returned.  If the timer cannot be created (because either
+ * there is insufficient FreeRTOS heap remaining to allocate the timer
+ * structures, or the timer period was set to 0) then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ * #define NUM_TIMERS 5
+ *
+ * // An array to hold handles to the created timers.
+ * TimerHandle_t xTimers[ NUM_TIMERS ];
+ *
+ * // An array to hold a count of the number of times each timer expires.
+ * int32_t lExpireCounters[ NUM_TIMERS ] = { 0 };
+ *
+ * // Define a callback function that will be used by multiple timer instances.
+ * // The callback function does nothing but count the number of times the
+ * // associated timer expires, and stop the timer once the timer has expired
+ * // 10 times.
+ * void vTimerCallback( TimerHandle_t pxTimer )
+ * {
+ * int32_t lArrayIndex;
+ * const int32_t xMaxExpiryCountBeforeStopping = 10;
+ *
+ * 	   // Optionally do something if the pxTimer parameter is NULL.
+ * 	   configASSERT( pxTimer );
+ *
+ *     // Which timer expired?
+ *     lArrayIndex = ( int32_t ) pvTimerGetTimerID( pxTimer );
+ *
+ *     // Increment the number of times that pxTimer has expired.
+ *     lExpireCounters[ lArrayIndex ] += 1;
+ *
+ *     // If the timer has expired 10 times then stop it from running.
+ *     if( lExpireCounters[ lArrayIndex ] == xMaxExpiryCountBeforeStopping )
+ *     {
+ *         // Do not use a block time if calling a timer API function from a
+ *         // timer callback function, as doing so could cause a deadlock!
+ *         xTimerStop( pxTimer, 0 );
+ *     }
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start some timers.  Starting the timers before the scheduler
+ *     // has been started means the timers will start running immediately that
+ *     // the scheduler starts.
+ *     for( x = 0; x < NUM_TIMERS; x++ )
+ *     {
+ *         xTimers[ x ] = xTimerCreate(    "Timer",       // Just a text name, not used by the kernel.
+ *                                         ( 100 * x ),   // The timer period in ticks.
+ *                                         pdTRUE,        // The timers will auto-reload themselves when they expire.
+ *                                         ( void * ) x,  // Assign each timer a unique id equal to its array index.
+ *                                         vTimerCallback // Each timer calls the same callback when it expires.
+ *                                     );
+ *
+ *         if( xTimers[ x ] == NULL )
+ *         {
+ *             // The timer was not created.
+ *         }
+ *         else
+ *         {
+ *             // Start the timer.  No block time is specified, and even if one was
+ *             // it would be ignored because the scheduler has not yet been
+ *             // started.
+ *             if( xTimerStart( xTimers[ x ], 0 ) != pdPASS )
+ *             {
+ *                 // The timer could not be set into the Active state.
+ *             }
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#if( configSUPPORT_DYNAMIC_ALLOCATION == 1 )
+	TimerHandle_t xTimerCreate(	const char * const pcTimerName,
+								const TickType_t xTimerPeriodInTicks,
+								const UBaseType_t uxAutoReload,
+								void * const pvTimerID,
+								TimerCallbackFunction_t pxCallbackFunction ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif
+
+/**
+ * TimerHandle_t xTimerCreateStatic(const char * const pcTimerName,
+ * 									TickType_t xTimerPeriodInTicks,
+ * 									UBaseType_t uxAutoReload,
+ * 									void * pvTimerID,
+ * 									TimerCallbackFunction_t pxCallbackFunction,
+ *									StaticTimer_t *pxTimerBuffer );
+ *
+ * Creates a new software timer instance, and returns a handle by which the
+ * created software timer can be referenced.
+ *
+ * Internally, within the FreeRTOS implementation, software timers use a block
+ * of memory, in which the timer data structure is stored.  If a software timer
+ * is created using xTimerCreate() then the required memory is automatically
+ * dynamically allocated inside the xTimerCreate() function.  (see
+ * http://www.freertos.org/a00111.html).  If a software timer is created using
+ * xTimerCreateStatic() then the application writer must provide the memory that
+ * will get used by the software timer.  xTimerCreateStatic() therefore allows a
+ * software timer to be created without using any dynamic memory allocation.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a
+ * timer into the active state.
+ *
+ * @param pcTimerName A text name that is assigned to the timer.  This is done
+ * purely to assist debugging.  The kernel itself only ever references a timer
+ * by its handle, and never by its name.
+ *
+ * @param xTimerPeriodInTicks The timer period.  The time is defined in tick
+ * periods so the constant portTICK_PERIOD_MS can be used to convert a time that
+ * has been specified in milliseconds.  For example, if the timer must expire
+ * after 100 ticks, then xTimerPeriodInTicks should be set to 100.
+ * Alternatively, if the timer must expire after 500ms, then xPeriod can be set
+ * to ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than or
+ * equal to 1000.
+ *
+ * @param uxAutoReload If uxAutoReload is set to pdTRUE then the timer will
+ * expire repeatedly with a frequency set by the xTimerPeriodInTicks parameter.
+ * If uxAutoReload is set to pdFALSE then the timer will be a one-shot timer and
+ * enter the dormant state after it expires.
+ *
+ * @param pvTimerID An identifier that is assigned to the timer being created.
+ * Typically this would be used in the timer callback function to identify which
+ * timer expired when the same callback function is assigned to more than one
+ * timer.
+ *
+ * @param pxCallbackFunction The function to call when the timer expires.
+ * Callback functions must have the prototype defined by TimerCallbackFunction_t,
+ * which is "void vCallbackFunction( TimerHandle_t xTimer );".
+ *
+ * @param pxTimerBuffer Must point to a variable of type StaticTimer_t, which
+ * will be then be used to hold the software timer's data structures, removing
+ * the need for the memory to be allocated dynamically.
+ *
+ * @return If the timer is created then a handle to the created timer is
+ * returned.  If pxTimerBuffer was NULL then NULL is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ * // The buffer used to hold the software timer's data structure.
+ * static StaticTimer_t xTimerBuffer;
+ *
+ * // A variable that will be incremented by the software timer's callback
+ * // function.
+ * UBaseType_t uxVariableToIncrement = 0;
+ *
+ * // A software timer callback function that increments a variable passed to
+ * // it when the software timer was created.  After the 5th increment the
+ * // callback function stops the software timer.
+ * static void prvTimerCallback( TimerHandle_t xExpiredTimer )
+ * {
+ * UBaseType_t *puxVariableToIncrement;
+ * BaseType_t xReturned;
+ *
+ *     // Obtain the address of the variable to increment from the timer ID.
+ *     puxVariableToIncrement = ( UBaseType_t * ) pvTimerGetTimerID( xExpiredTimer );
+ *
+ *     // Increment the variable to show the timer callback has executed.
+ *     ( *puxVariableToIncrement )++;
+ *
+ *     // If this callback has executed the required number of times, stop the
+ *     // timer.
+ *     if( *puxVariableToIncrement == 5 )
+ *     {
+ *         // This is called from a timer callback so must not block.
+ *         xTimerStop( xExpiredTimer, staticDONT_BLOCK );
+ *     }
+ * }
+ *
+ *
+ * void main( void )
+ * {
+ *     // Create the software time.  xTimerCreateStatic() has an extra parameter
+ *     // than the normal xTimerCreate() API function.  The parameter is a pointer
+ *     // to the StaticTimer_t structure that will hold the software timer
+ *     // structure.  If the parameter is passed as NULL then the structure will be
+ *     // allocated dynamically, just as if xTimerCreate() had been called.
+ *     xTimer = xTimerCreateStatic( "T1",             // Text name for the task.  Helps debugging only.  Not used by FreeRTOS.
+ *                                  xTimerPeriod,     // The period of the timer in ticks.
+ *                                  pdTRUE,           // This is an auto-reload timer.
+ *                                  ( void * ) &uxVariableToIncrement,    // A variable incremented by the software timer's callback function
+ *                                  prvTimerCallback, // The function to execute when the timer expires.
+ *                                  &xTimerBuffer );  // The buffer that will hold the software timer structure.
+ *
+ *     // The scheduler has not started yet so a block time is not used.
+ *     xReturned = xTimerStart( xTimer, 0 );
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timers running as they have already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#if( configSUPPORT_STATIC_ALLOCATION == 1 )
+	TimerHandle_t xTimerCreateStatic(	const char * const pcTimerName,
+										const TickType_t xTimerPeriodInTicks,
+										const UBaseType_t uxAutoReload,
+										void * const pvTimerID,
+										TimerCallbackFunction_t pxCallbackFunction,
+										StaticTimer_t *pxTimerBuffer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+#endif /* configSUPPORT_STATIC_ALLOCATION */
+
+/**
+ * void *pvTimerGetTimerID( TimerHandle_t xTimer );
+ *
+ * Returns the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer, and by calling the
+ * vTimerSetTimerID() API function.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return The ID assigned to the timer being queried.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void *pvTimerGetTimerID( const TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID );
+ *
+ * Sets the ID assigned to the timer.
+ *
+ * IDs are assigned to timers using the pvTimerID parameter of the call to
+ * xTimerCreated() that was used to create the timer.
+ *
+ * If the same callback function is assigned to multiple timers then the timer
+ * ID can be used as time specific (timer local) storage.
+ *
+ * @param xTimer The timer being updated.
+ *
+ * @param pvNewID The ID to assign to the timer.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ */
+void vTimerSetTimerID( TimerHandle_t xTimer, void *pvNewID ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer );
+ *
+ * Queries a timer to see if it is active or dormant.
+ *
+ * A timer will be dormant if:
+ *     1) It has been created but not started, or
+ *     2) It is an expired one-shot timer that has not been restarted.
+ *
+ * Timers are created in the dormant state.  The xTimerStart(), xTimerReset(),
+ * xTimerStartFromISR(), xTimerResetFromISR(), xTimerChangePeriod() and
+ * xTimerChangePeriodFromISR() API functions can all be used to transition a timer into the
+ * active state.
+ *
+ * @param xTimer The timer being queried.
+ *
+ * @return pdFALSE will be returned if the timer is dormant.  A value other than
+ * pdFALSE will be returned if the timer is active.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is active, do something.
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, do something else.
+ *     }
+ * }
+ * @endverbatim
+ */
+BaseType_t xTimerIsTimerActive( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+ * TaskHandle_t xTimerGetTimerDaemonTaskHandle( void );
+ *
+ * Simply returns the handle of the timer service/daemon task.  It it not valid
+ * to call xTimerGetTimerDaemonTaskHandle() before the scheduler has been started.
+ */
+TaskHandle_t xTimerGetTimerDaemonTaskHandle( void ) PRIVILEGED_FUNCTION;
+
+/**
+ * BaseType_t xTimerStart( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStart() starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerStart() has equivalent functionality
+ * to the xTimerReset() API function.
+ *
+ * Starting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerStart() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerStart() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerStart() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStart()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the start command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStart() was called.  xTicksToWait is ignored if xTimerStart() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStart( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStop( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerStop() stops a timer that was previously started using either of the
+ * The xTimerStart(), xTimerReset(), xTimerStartFromISR(), xTimerResetFromISR(),
+ * xTimerChangePeriod() or xTimerChangePeriodFromISR() API functions.
+ *
+ * Stopping a timer ensures the timer is not in the active state.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerStop()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the stop command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerStop() was called.  xTicksToWait is ignored if xTimerStop() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerCreate() API function example usage scenario.
+ *
+ */
+#define xTimerStop( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerChangePeriod( 	TimerHandle_t xTimer,
+ *										TickType_t xNewPeriod,
+ *										TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerChangePeriod() changes the period of a timer that was previously
+ * created using the xTimerCreate() API function.
+ *
+ * xTimerChangePeriod() can be called to change the period of an active or
+ * dormant state timer.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerChangePeriod() to be available.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the change period command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerChangePeriod() was called.  xTicksToWait is ignored if
+ * xTimerChangePeriod() is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the change period command could not be
+ * sent to the timer command queue even after xTicksToWait ticks had passed.
+ * pdPASS will be returned if the command was successfully sent to the timer
+ * command queue.  When the command is actually processed will depend on the
+ * priority of the timer service/daemon task relative to other tasks in the
+ * system.  The timer service/daemon task priority is set by the
+ * configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This function assumes xTimer has already been created.  If the timer
+ * // referenced by xTimer is already active when it is called, then the timer
+ * // is deleted.  If the timer referenced by xTimer is not active when it is
+ * // called, then the period of the timer is set to 500ms and the timer is
+ * // started.
+ * void vAFunction( TimerHandle_t xTimer )
+ * {
+ *     if( xTimerIsTimerActive( xTimer ) != pdFALSE ) // or more simply and equivalently "if( xTimerIsTimerActive( xTimer ) )"
+ *     {
+ *         // xTimer is already active - delete it.
+ *         xTimerDelete( xTimer );
+ *     }
+ *     else
+ *     {
+ *         // xTimer is not active, change its period to 500ms.  This will also
+ *         // cause the timer to start.  Block for a maximum of 100 ticks if the
+ *         // change period command cannot immediately be sent to the timer
+ *         // command queue.
+ *         if( xTimerChangePeriod( xTimer, 500 / portTICK_PERIOD_MS, 100 ) == pdPASS )
+ *         {
+ *             // The command was successfully sent.
+ *         }
+ *         else
+ *         {
+ *             // The command could not be sent, even after waiting for 100 ticks
+ *             // to pass.  Take appropriate action here.
+ *         }
+ *     }
+ * }
+ * @endverbatim
+ */
+ #define xTimerChangePeriod( xTimer, xNewPeriod, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD, ( xNewPeriod ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerDelete( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerDelete() deletes a timer that was previously created using the
+ * xTimerCreate() API function.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for
+ * xTimerDelete() to be available.
+ *
+ * @param xTimer The handle of the timer being deleted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the delete command to be
+ * successfully sent to the timer command queue, should the queue already be
+ * full when xTimerDelete() was called.  xTicksToWait is ignored if xTimerDelete()
+ * is called before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the delete command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ *
+ * See the xTimerChangePeriod() API function example usage scenario.
+ */
+#define xTimerDelete( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_DELETE, 0U, NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerReset( TimerHandle_t xTimer, TickType_t xTicksToWait );
+ *
+ * Timer functionality is provided by a timer service/daemon task.  Many of the
+ * public FreeRTOS timer API functions send commands to the timer service task
+ * through a queue called the timer command queue.  The timer command queue is
+ * private to the kernel itself and is not directly accessible to application
+ * code.  The length of the timer command queue is set by the
+ * configTIMER_QUEUE_LENGTH configuration constant.
+ *
+ * xTimerReset() re-starts a timer that was previously created using the
+ * xTimerCreate() API function.  If the timer had already been started and was
+ * already in the active state, then xTimerReset() will cause the timer to
+ * re-evaluate its expiry time so that it is relative to when xTimerReset() was
+ * called.  If the timer was in the dormant state then xTimerReset() has
+ * equivalent functionality to the xTimerStart() API function.
+ *
+ * Resetting a timer ensures the timer is in the active state.  If the timer
+ * is not stopped, deleted, or reset in the mean time, the callback function
+ * associated with the timer will get called 'n' ticks after xTimerReset() was
+ * called, where 'n' is the timers defined period.
+ *
+ * It is valid to call xTimerReset() before the scheduler has been started, but
+ * when this is done the timer will not actually start until the scheduler is
+ * started, and the timers expiry time will be relative to when the scheduler is
+ * started, not relative to when xTimerReset() was called.
+ *
+ * The configUSE_TIMERS configuration constant must be set to 1 for xTimerReset()
+ * to be available.
+ *
+ * @param xTimer The handle of the timer being reset/started/restarted.
+ *
+ * @param xTicksToWait Specifies the time, in ticks, that the calling task should
+ * be held in the Blocked state to wait for the reset command to be successfully
+ * sent to the timer command queue, should the queue already be full when
+ * xTimerReset() was called.  xTicksToWait is ignored if xTimerReset() is called
+ * before the scheduler is started.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue even after xTicksToWait ticks had passed.  pdPASS will
+ * be returned if the command was successfully sent to the timer command queue.
+ * When the command is actually processed will depend on the priority of the
+ * timer service/daemon task relative to other tasks in the system, although the
+ * timers expiry time is relative to when xTimerStart() is actually called.  The
+ * timer service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // When a key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer.
+ *
+ * TimerHandle_t xBacklightTimer = NULL;
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press event handler.
+ * void vKeyPressEventHandler( char cKey )
+ * {
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  Wait 10 ticks for the command to be successfully sent
+ *     // if it cannot be sent immediately.
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *     if( xTimerReset( xBacklightTimer, 100 ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ * }
+ *
+ * void main( void )
+ * {
+ * int32_t x;
+ *
+ *     // Create then start the one-shot timer that is responsible for turning
+ *     // the back-light off if no keys are pressed within a 5 second period.
+ *     xBacklightTimer = xTimerCreate( "BacklightTimer",           // Just a text name, not used by the kernel.
+ *                                     ( 5000 / portTICK_PERIOD_MS), // The timer period in ticks.
+ *                                     pdFALSE,                    // The timer is a one-shot timer.
+ *                                     0,                          // The id is not used by the callback so can take any value.
+ *                                     vBacklightTimerCallback     // The callback function that switches the LCD back-light off.
+ *                                   );
+ *
+ *     if( xBacklightTimer == NULL )
+ *     {
+ *         // The timer was not created.
+ *     }
+ *     else
+ *     {
+ *         // Start the timer.  No block time is specified, and even if one was
+ *         // it would be ignored because the scheduler has not yet been
+ *         // started.
+ *         if( xTimerStart( xBacklightTimer, 0 ) != pdPASS )
+ *         {
+ *             // The timer could not be set into the Active state.
+ *         }
+ *     }
+ *
+ *     // ...
+ *     // Create tasks here.
+ *     // ...
+ *
+ *     // Starting the scheduler will start the timer running as it has already
+ *     // been set into the active state.
+ *     vTaskStartScheduler();
+ *
+ *     // Should not reach here.
+ *     for( ;; );
+ * }
+ * @endverbatim
+ */
+#define xTimerReset( xTimer, xTicksToWait ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET, ( xTaskGetTickCount() ), NULL, ( xTicksToWait ) )
+
+/**
+ * BaseType_t xTimerStartFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStart() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being started/restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStartFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStartFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStartFromISR() function.  If
+ * xTimerStartFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the start command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerStartFromISR() is actually called.  The timer
+ * service/daemon task priority is set by the configTIMER_TASK_PRIORITY
+ * configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then restart the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerStartFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The start command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStartFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_START_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerStopFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerStop() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer being stopped.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerStopFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerStopFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerStopFromISR() function.  If
+ * xTimerStopFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the stop command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the timer should be simply stopped.
+ *
+ * // The interrupt service routine that stops the timer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - simply stop the timer.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerStopFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The stop command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerStopFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_STOP_FROM_ISR, 0, ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerChangePeriodFromISR( TimerHandle_t xTimer,
+ *										 TickType_t xNewPeriod,
+ *										 BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerChangePeriod() that can be called from an interrupt
+ * service routine.
+ *
+ * @param xTimer The handle of the timer that is having its period changed.
+ *
+ * @param xNewPeriod The new period for xTimer. Timer periods are specified in
+ * tick periods, so the constant portTICK_PERIOD_MS can be used to convert a time
+ * that has been specified in milliseconds.  For example, if the timer must
+ * expire after 100 ticks, then xNewPeriod should be set to 100.  Alternatively,
+ * if the timer must expire after 500ms, then xNewPeriod can be set to
+ * ( 500 / portTICK_PERIOD_MS ) provided configTICK_RATE_HZ is less than
+ * or equal to 1000.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerChangePeriodFromISR() writes a message to the
+ * timer command queue, so has the potential to transition the timer service/
+ * daemon task out of the Blocked state.  If calling xTimerChangePeriodFromISR()
+ * causes the timer service/daemon task to leave the Blocked state, and the
+ * timer service/daemon task has a priority equal to or greater than the
+ * currently executing task (the task that was interrupted), then
+ * *pxHigherPriorityTaskWoken will get set to pdTRUE internally within the
+ * xTimerChangePeriodFromISR() function.  If xTimerChangePeriodFromISR() sets
+ * this value to pdTRUE then a context switch should be performed before the
+ * interrupt exits.
+ *
+ * @return pdFAIL will be returned if the command to change the timers period
+ * could not be sent to the timer command queue.  pdPASS will be returned if the
+ * command was successfully sent to the timer command queue.  When the command
+ * is actually processed will depend on the priority of the timer service/daemon
+ * task relative to other tasks in the system.  The timer service/daemon task
+ * priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xTimer has already been created and started.  When
+ * // an interrupt occurs, the period of xTimer should be changed to 500ms.
+ *
+ * // The interrupt service routine that changes the period of xTimer.
+ * void vAnExampleInterruptServiceRoutine( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // The interrupt has occurred - change the period of xTimer to 500ms.
+ *     // xHigherPriorityTaskWoken was set to pdFALSE where it was defined
+ *     // (within this function).  As this is an interrupt service routine, only
+ *     // FreeRTOS API functions that end in "FromISR" can be used.
+ *     if( xTimerChangePeriodFromISR( xTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The command to change the timers period was not executed
+ *         // successfully.  Take appropriate action here.
+ *     }
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerChangePeriodFromISR( xTimer, xNewPeriod, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_CHANGE_PERIOD_FROM_ISR, ( xNewPeriod ), ( pxHigherPriorityTaskWoken ), 0U )
+
+/**
+ * BaseType_t xTimerResetFromISR( 	TimerHandle_t xTimer,
+ *									BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ * A version of xTimerReset() that can be called from an interrupt service
+ * routine.
+ *
+ * @param xTimer The handle of the timer that is to be started, reset, or
+ * restarted.
+ *
+ * @param pxHigherPriorityTaskWoken The timer service/daemon task spends most
+ * of its time in the Blocked state, waiting for messages to arrive on the timer
+ * command queue.  Calling xTimerResetFromISR() writes a message to the timer
+ * command queue, so has the potential to transition the timer service/daemon
+ * task out of the Blocked state.  If calling xTimerResetFromISR() causes the
+ * timer service/daemon task to leave the Blocked state, and the timer service/
+ * daemon task has a priority equal to or greater than the currently executing
+ * task (the task that was interrupted), then *pxHigherPriorityTaskWoken will
+ * get set to pdTRUE internally within the xTimerResetFromISR() function.  If
+ * xTimerResetFromISR() sets this value to pdTRUE then a context switch should
+ * be performed before the interrupt exits.
+ *
+ * @return pdFAIL will be returned if the reset command could not be sent to
+ * the timer command queue.  pdPASS will be returned if the command was
+ * successfully sent to the timer command queue.  When the command is actually
+ * processed will depend on the priority of the timer service/daemon task
+ * relative to other tasks in the system, although the timers expiry time is
+ * relative to when xTimerResetFromISR() is actually called.  The timer service/daemon
+ * task priority is set by the configTIMER_TASK_PRIORITY configuration constant.
+ *
+ * Example usage:
+ * @verbatim
+ * // This scenario assumes xBacklightTimer has already been created.  When a
+ * // key is pressed, an LCD back-light is switched on.  If 5 seconds pass
+ * // without a key being pressed, then the LCD back-light is switched off.  In
+ * // this case, the timer is a one-shot timer, and unlike the example given for
+ * // the xTimerReset() function, the key press event handler is an interrupt
+ * // service routine.
+ *
+ * // The callback function assigned to the one-shot timer.  In this case the
+ * // parameter is not used.
+ * void vBacklightTimerCallback( TimerHandle_t pxTimer )
+ * {
+ *     // The timer expired, therefore 5 seconds must have passed since a key
+ *     // was pressed.  Switch off the LCD back-light.
+ *     vSetBacklightState( BACKLIGHT_OFF );
+ * }
+ *
+ * // The key press interrupt service routine.
+ * void vKeyPressEventInterruptHandler( void )
+ * {
+ * BaseType_t xHigherPriorityTaskWoken = pdFALSE;
+ *
+ *     // Ensure the LCD back-light is on, then reset the timer that is
+ *     // responsible for turning the back-light off after 5 seconds of
+ *     // key inactivity.  This is an interrupt service routine so can only
+ *     // call FreeRTOS API functions that end in "FromISR".
+ *     vSetBacklightState( BACKLIGHT_ON );
+ *
+ *     // xTimerStartFromISR() or xTimerResetFromISR() could be called here
+ *     // as both cause the timer to re-calculate its expiry time.
+ *     // xHigherPriorityTaskWoken was initialised to pdFALSE when it was
+ *     // declared (in this function).
+ *     if( xTimerResetFromISR( xBacklightTimer, &xHigherPriorityTaskWoken ) != pdPASS )
+ *     {
+ *         // The reset command was not executed successfully.  Take appropriate
+ *         // action here.
+ *     }
+ *
+ *     // Perform the rest of the key processing here.
+ *
+ *     // If xHigherPriorityTaskWoken equals pdTRUE, then a context switch
+ *     // should be performed.  The syntax required to perform a context switch
+ *     // from inside an ISR varies from port to port, and from compiler to
+ *     // compiler.  Inspect the demos for the port you are using to find the
+ *     // actual syntax required.
+ *     if( xHigherPriorityTaskWoken != pdFALSE )
+ *     {
+ *         // Call the interrupt safe yield function here (actual function
+ *         // depends on the FreeRTOS port being used).
+ *     }
+ * }
+ * @endverbatim
+ */
+#define xTimerResetFromISR( xTimer, pxHigherPriorityTaskWoken ) xTimerGenericCommand( ( xTimer ), tmrCOMMAND_RESET_FROM_ISR, ( xTaskGetTickCountFromISR() ), ( pxHigherPriorityTaskWoken ), 0U )
+
+
+/**
+ * BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend,
+ *                                          void *pvParameter1,
+ *                                          uint32_t ulParameter2,
+ *                                          BaseType_t *pxHigherPriorityTaskWoken );
+ *
+ *
+ * Used from application interrupt service routines to defer the execution of a
+ * function to the RTOS daemon task (the timer service task, hence this function
+ * is implemented in timers.c and is prefixed with 'Timer').
+ *
+ * Ideally an interrupt service routine (ISR) is kept as short as possible, but
+ * sometimes an ISR either has a lot of processing to do, or needs to perform
+ * processing that is not deterministic.  In these cases
+ * xTimerPendFunctionCallFromISR() can be used to defer processing of a function
+ * to the RTOS daemon task.
+ *
+ * A mechanism is provided that allows the interrupt to return directly to the
+ * task that will subsequently execute the pended callback function.  This
+ * allows the callback function to execute contiguously in time with the
+ * interrupt - just as if the callback had executed in the interrupt itself.
+ *
+ * @param xFunctionToPend The function to execute from the timer service/
+ * daemon task.  The function must conform to the PendedFunction_t
+ * prototype.
+ *
+ * @param pvParameter1 The value of the callback function's first parameter.
+ * The parameter has a void * type to allow it to be used to pass any type.
+ * For example, unsigned longs can be cast to a void *, or the void * can be
+ * used to point to a structure.
+ *
+ * @param ulParameter2 The value of the callback function's second parameter.
+ *
+ * @param pxHigherPriorityTaskWoken As mentioned above, calling this function
+ * will result in a message being sent to the timer daemon task.  If the
+ * priority of the timer daemon task (which is set using
+ * configTIMER_TASK_PRIORITY in FreeRTOSConfig.h) is higher than the priority of
+ * the currently running task (the task the interrupt interrupted) then
+ * *pxHigherPriorityTaskWoken will be set to pdTRUE within
+ * xTimerPendFunctionCallFromISR(), indicating that a context switch should be
+ * requested before the interrupt exits.  For that reason
+ * *pxHigherPriorityTaskWoken must be initialised to pdFALSE.  See the
+ * example code below.
+ *
+ * @return pdPASS is returned if the message was successfully sent to the
+ * timer daemon task, otherwise pdFALSE is returned.
+ *
+ * Example usage:
+ * @verbatim
+ *
+ *	// The callback function that will execute in the context of the daemon task.
+ *  // Note callback functions must all use this same prototype.
+ *  void vProcessInterface( void *pvParameter1, uint32_t ulParameter2 )
+ *	{
+ *		BaseType_t xInterfaceToService;
+ *
+ *		// The interface that requires servicing is passed in the second
+ *      // parameter.  The first parameter is not used in this case.
+ *		xInterfaceToService = ( BaseType_t ) ulParameter2;
+ *
+ *		// ...Perform the processing here...
+ *	}
+ *
+ *	// An ISR that receives data packets from multiple interfaces
+ *  void vAnISR( void )
+ *	{
+ *		BaseType_t xInterfaceToService, xHigherPriorityTaskWoken;
+ *
+ *		// Query the hardware to determine which interface needs processing.
+ *		xInterfaceToService = prvCheckInterfaces();
+ *
+ *      // The actual processing is to be deferred to a task.  Request the
+ *      // vProcessInterface() callback function is executed, passing in the
+ *		// number of the interface that needs processing.  The interface to
+ *		// service is passed in the second parameter.  The first parameter is
+ *		// not used in this case.
+ *		xHigherPriorityTaskWoken = pdFALSE;
+ *		xTimerPendFunctionCallFromISR( vProcessInterface, NULL, ( uint32_t ) xInterfaceToService, &xHigherPriorityTaskWoken );
+ *
+ *		// If xHigherPriorityTaskWoken is now set to pdTRUE then a context
+ *		// switch should be requested.  The macro used is port specific and will
+ *		// be either portYIELD_FROM_ISR() or portEND_SWITCHING_ISR() - refer to
+ *		// the documentation page for the port being used.
+ *		portYIELD_FROM_ISR( xHigherPriorityTaskWoken );
+ *
+ *	}
+ * @endverbatim
+ */
+BaseType_t xTimerPendFunctionCallFromISR( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, BaseType_t *pxHigherPriorityTaskWoken ) PRIVILEGED_FUNCTION;
+
+ /**
+  * BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend,
+  *                                    void *pvParameter1,
+  *                                    uint32_t ulParameter2,
+  *                                    TickType_t xTicksToWait );
+  *
+  *
+  * Used to defer the execution of a function to the RTOS daemon task (the timer
+  * service task, hence this function is implemented in timers.c and is prefixed
+  * with 'Timer').
+  *
+  * @param xFunctionToPend The function to execute from the timer service/
+  * daemon task.  The function must conform to the PendedFunction_t
+  * prototype.
+  *
+  * @param pvParameter1 The value of the callback function's first parameter.
+  * The parameter has a void * type to allow it to be used to pass any type.
+  * For example, unsigned longs can be cast to a void *, or the void * can be
+  * used to point to a structure.
+  *
+  * @param ulParameter2 The value of the callback function's second parameter.
+  *
+  * @param xTicksToWait Calling this function will result in a message being
+  * sent to the timer daemon task on a queue.  xTicksToWait is the amount of
+  * time the calling task should remain in the Blocked state (so not using any
+  * processing time) for space to become available on the timer queue if the
+  * queue is found to be full.
+  *
+  * @return pdPASS is returned if the message was successfully sent to the
+  * timer daemon task, otherwise pdFALSE is returned.
+  *
+  */
+BaseType_t xTimerPendFunctionCall( PendedFunction_t xFunctionToPend, void *pvParameter1, uint32_t ulParameter2, TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+/**
+ * const char * const pcTimerGetName( TimerHandle_t xTimer );
+ *
+ * Returns the name that was assigned to a timer when the timer was created.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The name assigned to the timer specified by the xTimer parameter.
+ */
+const char * pcTimerGetName( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION; /*lint !e971 Unqualified char types are allowed for strings and single characters only. */
+
+/**
+ * TickType_t xTimerGetPeriod( TimerHandle_t xTimer );
+ *
+ * Returns the period of a timer.
+ *
+ * @param xTimer The handle of the timer being queried.
+ *
+ * @return The period of the timer in ticks.
+ */
+TickType_t xTimerGetPeriod( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/**
+* TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer );
+*
+* Returns the time in ticks at which the timer will expire.  If this is less
+* than the current tick count then the expiry time has overflowed from the
+* current time.
+*
+* @param xTimer The handle of the timer being queried.
+*
+* @return If the timer is running then the time in ticks at which the timer
+* will next expire is returned.  If the timer is not running then the return
+* value is undefined.
+*/
+TickType_t xTimerGetExpiryTime( TimerHandle_t xTimer ) PRIVILEGED_FUNCTION;
+
+/*
+ * Functions beyond this part are not part of the public API and are intended
+ * for use by the kernel only.
+ */
+BaseType_t xTimerCreateTimerTask( void ) PRIVILEGED_FUNCTION;
+BaseType_t xTimerGenericCommand( TimerHandle_t xTimer, const BaseType_t xCommandID, const TickType_t xOptionalValue, BaseType_t * const pxHigherPriorityTaskWoken, const TickType_t xTicksToWait ) PRIVILEGED_FUNCTION;
+
+#ifdef __cplusplus
+}
+#endif
+#endif /* TIMERS_H */
+
+
+

From e7abad654e8ca03a86502c3b5a27f5411660060e Mon Sep 17 00:00:00 2001
From: victorpv <victor_pv@hotmail.com>
Date: Sun, 26 Mar 2017 14:33:48 -0500
Subject: [PATCH 045/307] Timer DMA functions.

Adding 2 functions to enable and disable Timer peripheral DMA requests
on update event.
---
 STM32F1/system/libmaple/include/libmaple/timer.h | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/STM32F1/system/libmaple/include/libmaple/timer.h b/STM32F1/system/libmaple/include/libmaple/timer.h
index 59b340320..28b6c95ce 100644
--- a/STM32F1/system/libmaple/include/libmaple/timer.h
+++ b/STM32F1/system/libmaple/include/libmaple/timer.h
@@ -785,6 +785,22 @@ static inline void timer_dma_disable_trg_req(timer_dev *dev) {
     *bb_perip(&(dev->regs).gen->DIER, TIMER_DIER_TDE_BIT) = 0;
 }
 
+/**
+ * @brief Enable a timer's update DMA request
+ * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL
+ */
+static inline void timer_dma_enable_upd_req(timer_dev *dev) {
+    *bb_perip(&(dev->regs).gen->DIER, TIMER_DIER_UDE_BIT) = 1;
+}
+
+/**
+ * @brief Disable a timer's update DMA request
+ * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL
+ */
+static inline void timer_dma_disable_upd_req(timer_dev *dev) {
+    *bb_perip(&(dev->regs).gen->DIER, TIMER_DIER_UDE_BIT) = 0;
+}
+
 /**
  * @brief Enable a timer channel's DMA request.
  * @param dev Timer device, must have type TIMER_ADVANCED or TIMER_GENERAL

From 83e5f4832206f1924168c217df0c7bff1b06dad7 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Thu, 13 Apr 2017 22:34:37 +0200
Subject: [PATCH 046/307] remove "deprecated" flag from dma_setup_transfer

remove deprecated flag
---
 STM32F1/cores/maple/libmaple/dma_f1.c                | 1 -
 STM32F1/system/libmaple/stm32f1/include/series/dma.h | 1 -
 2 files changed, 2 deletions(-)

diff --git a/STM32F1/cores/maple/libmaple/dma_f1.c b/STM32F1/cores/maple/libmaple/dma_f1.c
index 6400d1533..c7c3c0072 100644
--- a/STM32F1/cores/maple/libmaple/dma_f1.c
+++ b/STM32F1/cores/maple/libmaple/dma_f1.c
@@ -341,7 +341,6 @@ void dma_set_per_addr(dma_dev *dev, dma_channel channel, __io void *addr) {
  * @see dma_attach_interrupt()
  * @see dma_enable()
  */
-__deprecated
 void dma_setup_transfer(dma_dev       *dev,
                         dma_channel    channel,
                         __io void     *peripheral_address,
diff --git a/STM32F1/system/libmaple/stm32f1/include/series/dma.h b/STM32F1/system/libmaple/stm32f1/include/series/dma.h
index bedb6028e..ff6185795 100644
--- a/STM32F1/system/libmaple/stm32f1/include/series/dma.h
+++ b/STM32F1/system/libmaple/stm32f1/include/series/dma.h
@@ -559,7 +559,6 @@ typedef enum dma_mode_flags {
  *
  * (It's not possible to fully configure a DMA stream on F2 with just
  * this information, so this interface is too tied to the F1.) */
-__deprecated
 void dma_setup_transfer(dma_dev       *dev,
                         dma_channel    channel,
                         __io void     *peripheral_address,

From 3d775ac3c5abe061945f0821489c20d7e4606f71 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Fri, 14 Apr 2017 00:04:32 +0200
Subject: [PATCH 047/307] added variant black_f4  + cleanup old F1 anf F2
 definitions

---
 STM32F4/boards.txt                            | 28 +++++++++
 STM32F4/cores/maple/boards.cpp                | 12 ++--
 STM32F4/cores/maple/boards.h                  |  2 +
 STM32F4/cores/maple/io.h                      |  9 ++-
 .../cores/maple/libmaple/HardwareSerial.cpp   |  2 +-
 STM32F4/cores/maple/libmaple/adc.c            | 12 ++--
 STM32F4/cores/maple/libmaple/adc.h            | 48 +++++---------
 STM32F4/cores/maple/libmaple/dma.h            |  7 +--
 STM32F4/cores/maple/libmaple/exti.h           |  4 --
 STM32F4/cores/maple/libmaple/gpio.h           |  7 +--
 STM32F4/cores/maple/libmaple/libmaple.h       | 11 +++-
 STM32F4/cores/maple/libmaple/libmaple_types.h | 12 ++--
 STM32F4/cores/maple/libmaple/rcc.h            |  7 +--
 STM32F4/cores/maple/libmaple/rules.mk         | 22 -------
 STM32F4/cores/maple/libmaple/stm32.h          | 63 +------------------
 STM32F4/cores/maple/libmaple/timer.h          | 19 ++----
 STM32F4/cores/maple/libmaple/usart.h          |  6 +-
 .../cores/maple/libmaple/usbF4/VCP/usb_conf.h |  4 ++
 .../maple/libmaple/usbF4/VCP/usbd_cdc_vcp.c   |  2 +-
 STM32F4/cores/maple/libmaple/usbF4/usb.c      |  2 +-
 STM32F4/cores/maple/wirish.h                  |  1 -
 STM32F4/cores/maple/wirish_analog.cpp         |  2 -
 STM32F4/cores/maple/wirish_digital.cpp        | 14 ++---
 STM32F4/cores/maple/wirish_types.h            | 15 +++++
 STM32F4/platform.txt                          |  8 +--
 25 files changed, 122 insertions(+), 197 deletions(-)

diff --git a/STM32F4/boards.txt b/STM32F4/boards.txt
index 7577d1949..3ff182c7b 100644
--- a/STM32F4/boards.txt
+++ b/STM32F4/boards.txt
@@ -29,6 +29,34 @@ discovery_f407.build.error_led_port=GPIOD
 discovery_f407.build.error_led_pin=14
 discovery_f407.build.board=STM32DiscoveryF407
 
+##############################################################
+black_f407vet6.name=STM32 Black F407VET6
+
+black_f407vet6.upload.tool=stlink_upload
+black_f407vet6.upload.protocol=stlink
+
+black_f407vet6.upload.file_type=bin
+black_f407vet6.upload.ram.maximum_size=65535
+black_f407vet6.upload.flash.maximum_size=514288
+black_f407vet6.upload.maximum_size=514288
+
+#black_f407vet6.upload.usbID=0483:3748
+#black_f407vet6.upload.altID=1
+#black_f407vet6.upload.auto_reset=true
+
+black_f407vet6.build.mcu=cortex-m4
+black_f407vet6.build.f_cpu=168000000L
+black_f407vet6.build.core=maple
+black_f407vet6.build.extra_flags=-mthumb -DSTM32_HIGH_DENSITY -DSTM32F4 -DBOARD_black_f4
+black_f407vet6.build.ldscript=ld/jtag.ld
+black_f407vet6.build.variant=black_f407vet6
+black_f407vet6.build.variant_system_lib=lib_f407.a
+black_f407vet6.build.vect=VECT_TAB_BASE
+black_f407vet6.build.density=STM32_HIGH_DENSITY
+black_f407vet6.build.error_led_port=GPIOA
+black_f407vet6.build.error_led_pin=7
+black_f407vet6.build.board=STM32BlackF407VET6
+
 ##############################################################
 stm32f4stamp.name=STM32F4Stamp F405
 
diff --git a/STM32F4/cores/maple/boards.cpp b/STM32F4/cores/maple/boards.cpp
index a85657163..f9bfd5a31 100644
--- a/STM32F4/cores/maple/boards.cpp
+++ b/STM32F4/cores/maple/boards.cpp
@@ -41,9 +41,7 @@
 #include "adc.h"
 #include "timer.h"
 #include "usb.h"
-#ifdef STM32F2
-//#include "usbF4.h"
-#endif
+
 
 static void setupFlash(void);
 static void setupClocks(void);
@@ -59,7 +57,7 @@ void init(void) {
 	systick_init(SYSTICK_RELOAD_VAL);
 	gpio_init_all();
 
-#ifdef STM32F2
+#ifdef STM32F4
 	rcc_clk_enable(RCC_SYSCFG);
 #else
     afio_init();
@@ -84,11 +82,13 @@ bool boardUsesPin(uint8 pin) {
 }
 
 static void setupFlash(void) {
+/*
 #ifndef STM32F2
 	// for F2 and F4 CPUs this is done in SetupClock...(), e.g. in SetupClock168MHz()
     flash_enable_prefetch();
     flash_set_latency(FLASH_WAIT_STATE_2);
 #endif
+*/
 }
 
 /*
@@ -121,8 +121,8 @@ static void setupNVIC() {
 static void adcDefaultConfig(const adc_dev* dev);
 
 static void setupADC() {
-#ifdef STM32F2
-	setupADC_F2();
+#ifdef STM32F4
+	setupADC_F4();
 #else
 	rcc_set_prescaler(RCC_PRESCALER_ADC, RCC_ADCPRE_PCLK_DIV_6);
 #endif
diff --git a/STM32F4/cores/maple/boards.h b/STM32F4/cores/maple/boards.h
index 00d07cddb..5e0aae3b8 100644
--- a/STM32F4/cores/maple/boards.h
+++ b/STM32F4/cores/maple/boards.h
@@ -140,6 +140,8 @@ bool boardUsesPin(uint8 pin);
 #include "aeroquad32mini.h"
 #elif defined(BOARD_discovery_f4)
 #include "discovery_f4.h"
+#elif defined(BOARD_black_f4)
+#include "black_f4.h"
 #elif defined(BOARD_freeflight)
 #include "freeflight.h"
 #else
diff --git a/STM32F4/cores/maple/io.h b/STM32F4/cores/maple/io.h
index df1ab969e..d4d1c25cd 100644
--- a/STM32F4/cores/maple/io.h
+++ b/STM32F4/cores/maple/io.h
@@ -33,6 +33,7 @@
 #ifndef _IO_H_
 #define _IO_H_
 
+#include <inttypes.h>
 #include "gpio.h"
 #include "adc.h"
 
@@ -179,9 +180,11 @@ static inline void toggleLED() {
  * accomplished portably over all LeafLabs boards by calling
  * pinMode(BOARD_BUTTON_PIN, INPUT).
  *
+ * @param button - one of available on-board buttons (up to 3 for black F4)
+ *
  * @see pinMode()
  */
-uint8 isButtonPressed();
+uint8 isButtonPressed(uint8_t button);
 
 /**
  * Wait until the button is pressed and released, timing out if no
@@ -195,12 +198,14 @@ uint8 isButtonPressed();
  * button is pressed.  If timeout_millis is left out (or 0), wait
  * forever.
  *
+ * @param button - one of available on-board buttons (up to 3 for black F4)
+ *
  * @return true, if the button was pressed; false, if the timeout was
  * reached.
  *
  * @see pinMode()
  */
-uint8 waitForButtonPress(uint32 timeout_millis=0);
+uint8 waitForButtonPress(uint8_t button, uint32 timeout_millis=0);
 
 /**
  * Shift out a byte of data, one bit at a time.
diff --git a/STM32F4/cores/maple/libmaple/HardwareSerial.cpp b/STM32F4/cores/maple/libmaple/HardwareSerial.cpp
index 59ce71d11..475116b17 100644
--- a/STM32F4/cores/maple/libmaple/HardwareSerial.cpp
+++ b/STM32F4/cores/maple/libmaple/HardwareSerial.cpp
@@ -92,7 +92,7 @@ void HardwareSerial::begin(uint32 baud) {
 
     const stm32_pin_info *txi = &PIN_MAP[tx_pin];
     const stm32_pin_info *rxi = &PIN_MAP[rx_pin];
-#ifdef STM32F2
+#ifdef STM32F4
 	// int af = 7<<8;
     if (usart_device == UART4 || usart_device == UART5) {
         gpio_set_af_mode(txi->gpio_device, txi->gpio_bit, 8);
diff --git a/STM32F4/cores/maple/libmaple/adc.c b/STM32F4/cores/maple/libmaple/adc.c
index aeeb43c0e..b803f29cb 100644
--- a/STM32F4/cores/maple/libmaple/adc.c
+++ b/STM32F4/cores/maple/libmaple/adc.c
@@ -74,7 +74,7 @@ const adc_dev *ADC3 = &adc3;
  */
 void adc_init(const adc_dev *dev) {
     rcc_clk_enable(dev->clk_id);
-#ifdef STM32F2
+#ifdef STM32F4
     if(dev->clk_id == RCC_ADC1) {
     	rcc_reset_dev(dev->clk_id);
     }
@@ -136,7 +136,9 @@ void adc_set_sample_rate(const adc_dev *dev, adc_smp_rate smp_rate) {
  * @brief Calibrate an ADC peripheral
  * @param dev adc device
  */
-void adc_calibrate(const adc_dev *dev) {
+void adc_calibrate(const adc_dev *dev)
+{
+/*
 #ifndef STM32F2
     __io uint32 *rstcal_bit = bb_perip(&(dev->regs->CR2), 3);
     __io uint32 *cal_bit = bb_perip(&(dev->regs->CR2), 2);
@@ -149,6 +151,7 @@ void adc_calibrate(const adc_dev *dev) {
     while (*cal_bit)
         ;
 #endif
+*/
 }
 
 /**
@@ -171,8 +174,8 @@ uint16 adc_read(const adc_dev *dev, uint8 channel) {
     return (uint16)(regs->DR & ADC_DR_DATA);
 }
 
-void setupADC_F2() {
-#ifdef STM32F2
+void setupADC_F4(void)
+{
 		  uint32 tmpreg1 = 0;
 
 		  tmpreg1 = ADC_COMMON->CCR;
@@ -196,5 +199,4 @@ void setupADC_F2() {
 
 		  /* Write to ADC CCR */
 		  ADC_COMMON->CCR = tmpreg1;
-#endif
 }
diff --git a/STM32F4/cores/maple/libmaple/adc.h b/STM32F4/cores/maple/libmaple/adc.h
index 3a40d4c58..7a395102d 100644
--- a/STM32F4/cores/maple/libmaple/adc.h
+++ b/STM32F4/cores/maple/libmaple/adc.h
@@ -42,17 +42,15 @@ extern "C"{
 #endif
 
 
-#ifdef STM32F2
-  typedef struct
-  {
-    __io uint32 CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-    __io uint32 CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-    __io uint32 CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-  } ADC_Common_TypeDef;
+typedef struct
+{
+	__io uint32 CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
+	__io uint32 CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
+	__io uint32 CDR;    /*!< ADC common regular data register for dual
+							 AND triple modes,                            Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
 #define ADC_COMMON  ((ADC_Common_TypeDef *) 0x40012300)
 
-#endif
 
 /** ADC register map type. */
 typedef struct adc_reg_map {
@@ -94,23 +92,12 @@ extern const adc_dev *ADC3;
  * Register map base pointers
  */
 
-#ifdef STM32F2
-	/** ADC1 register map base pointer. */
-	#define ADC1_BASE                       ((struct adc_reg_map*)0x40012000)
-	/** ADC2 register map base pointer. */
-	#define ADC2_BASE                       ((struct adc_reg_map*)0x40012100)
-  /** ADC3 register map base pointer. */
-  #define ADC3_BASE                       ((struct adc_reg_map*)0x40012200)
-#else
-	/** ADC1 register map base pointer. */
-	#define ADC1_BASE                       ((struct adc_reg_map*)0x40012400)
-	/** ADC2 register map base pointer. */
-	#define ADC2_BASE                       ((struct adc_reg_map*)0x40012800)
-	#ifdef STM32_HIGH_DENSITY
-  	/** ADC3 register map base pointer. */
-	  #define ADC3_BASE                       ((struct adc_reg_map*)0x40013C00)
-  #endif
-#endif
+/** ADC1 register map base pointer. */
+#define ADC1_BASE                       ((struct adc_reg_map*)0x40012000)
+/** ADC2 register map base pointer. */
+#define ADC2_BASE                       ((struct adc_reg_map*)0x40012100)
+/** ADC3 register map base pointer. */
+#define ADC3_BASE                       ((struct adc_reg_map*)0x40012200)
 
 /*
  * Register bit definitions
@@ -167,17 +154,10 @@ extern const adc_dev *ADC3;
 #define ADC_CR2_JEXTTRIG_BIT            15
 #define ADC_CR2_EXTTRIG_BIT             20
 #define ADC_CR2_TSEREFE_BIT             23
-#ifdef STM32F2
 #define ADC_CR2_JSWSTART_BIT            22
 #define ADC_CR2_SWSTART_BIT             30
 #define ADC_CR2_EXTSEL                  (0x0F000000)
 #define ADC_CR2_JEXTSEL                 (0x000F0000)
-#else
-#define ADC_CR2_JSWSTART_BIT            21
-#define ADC_CR2_SWSTART_BIT             22
-#define ADC_CR2_EXTSEL                  (0x000E0000)
-#define ADC_CR2_JEXTSEL                 (0x00007000)
-#endif
 
 
 
@@ -388,7 +368,7 @@ static inline void adc_disable_all(void) {
     adc_foreach(adc_disable);
 }
 
-void setupADC_F2();
+extern void setupADC_F4(void);
 
 #ifdef __cplusplus
 } // extern "C"
diff --git a/STM32F4/cores/maple/libmaple/dma.h b/STM32F4/cores/maple/libmaple/dma.h
index a965c036f..420adf8a4 100644
--- a/STM32F4/cores/maple/libmaple/dma.h
+++ b/STM32F4/cores/maple/libmaple/dma.h
@@ -30,9 +30,4 @@
  *  @brief Direct Memory Access peripheral support
  */
 
-#ifdef STM32F2
-#include "dmaF2.h"
-#include <libmaple/dma_common.h>
-#else
-#include "dmaF1.h"
-#endif
+#include "dmaF4.h"
diff --git a/STM32F4/cores/maple/libmaple/exti.h b/STM32F4/cores/maple/libmaple/exti.h
index bac8adcf4..063f2d7f1 100644
--- a/STM32F4/cores/maple/libmaple/exti.h
+++ b/STM32F4/cores/maple/libmaple/exti.h
@@ -52,11 +52,7 @@ typedef struct exti_reg_map {
 } exti_reg_map;
 
 /** EXTI register map base pointer */
-#ifdef STM32F2
 #define EXTI_BASE                       ((struct exti_reg_map*)0x40013C00)
-#else
-#define EXTI_BASE                       ((struct exti_reg_map*)0x40010400)
-#endif
 
 /** External interrupt trigger mode */
 typedef enum exti_trigger_mode {
diff --git a/STM32F4/cores/maple/libmaple/gpio.h b/STM32F4/cores/maple/libmaple/gpio.h
index 4d42386c1..f065c7190 100644
--- a/STM32F4/cores/maple/libmaple/gpio.h
+++ b/STM32F4/cores/maple/libmaple/gpio.h
@@ -31,8 +31,5 @@
  *         (AFIO) prototypes, defines, and inlined access functions.
  */
 
-#ifdef STM32F2
-#include "gpioF2.h"
-#else
-#include "gpioF1.h"
-#endif
+
+#include "gpioF4.h"
diff --git a/STM32F4/cores/maple/libmaple/libmaple.h b/STM32F4/cores/maple/libmaple/libmaple.h
index 10c6c0c00..20a57bc6f 100644
--- a/STM32F4/cores/maple/libmaple/libmaple.h
+++ b/STM32F4/cores/maple/libmaple/libmaple.h
@@ -42,19 +42,24 @@
  *
  * FIXME this has no business being here
  */
+/*
 #if defined(MCU_STM32F103VE) || defined(MCU_STM32F205VE) || defined(MCU_STM32F406VG)
-    /* e.g., Aeroquad32 */
-    #define USER_ADDR_ROM 0x08010000    /* ala42 */
+    // e.g., Aeroquad32
+    #define USER_ADDR_ROM 0x08010000    // ala42
     #define USER_ADDR_RAM 0x20000C00
     #define STACK_TOP     0x20000800
 #elif defined(BOARD_freeflight)
+*/
 #define USER_ADDR_ROM 0x08000000
-#define USER_ADDR_RAM 0x20000000
+#define USER_ADDR_RAM 0x20000C00
 #define STACK_TOP     0x20000800
+/*
 #else
 #define USER_ADDR_ROM 0x08005000
 #define USER_ADDR_RAM 0x20000C00
 #define STACK_TOP     0x20000800
 #endif
+*/
+
 #endif
 
diff --git a/STM32F4/cores/maple/libmaple/libmaple_types.h b/STM32F4/cores/maple/libmaple/libmaple_types.h
index 332ded176..e20e3274f 100644
--- a/STM32F4/cores/maple/libmaple/libmaple_types.h
+++ b/STM32F4/cores/maple/libmaple/libmaple_types.h
@@ -46,12 +46,14 @@ typedef long long int64;
 typedef void (*voidFuncPtr)(void);
 
 #define __io volatile
-#define __attr_flash __attribute__((section (".USER_FLASH")))
-
-#define __always_inline inline __attribute__((always_inline))
-
+#ifndef __attr_flash
+  #define __attr_flash __attribute__((section (".USER_FLASH")))
+#endif
+#ifndef __always_inline
+  #define __always_inline inline __attribute__((always_inline))
+#endif
 #ifndef NULL
-#define NULL 0
+  #define NULL 0
 #endif
 
 #endif
diff --git a/STM32F4/cores/maple/libmaple/rcc.h b/STM32F4/cores/maple/libmaple/rcc.h
index 6317cbdb8..75e2d3d7a 100644
--- a/STM32F4/cores/maple/libmaple/rcc.h
+++ b/STM32F4/cores/maple/libmaple/rcc.h
@@ -29,8 +29,5 @@
  * @brief reset and clock control definitions and prototypes
  */
 
-#ifdef STM32F2
-#include "rccF2.h"
-#else
-#include "rccF1.h"
-#endif
+
+#include "rccF4.h"
diff --git a/STM32F4/cores/maple/libmaple/rules.mk b/STM32F4/cores/maple/libmaple/rules.mk
index c4924dc86..eb8d96d26 100644
--- a/STM32F4/cores/maple/libmaple/rules.mk
+++ b/STM32F4/cores/maple/libmaple/rules.mk
@@ -3,17 +3,11 @@ sp              := $(sp).x
 dirstack_$(sp)  := $(d)
 d               := $(dir)
 BUILDDIRS       += $(BUILD_PATH)/$(d)
-ifneq ($(MCU_FAMILY), STM32F2)
-BUILDDIRS       += $(BUILD_PATH)/$(d)/usb
-BUILDDIRS       += $(BUILD_PATH)/$(d)/usb/usb_lib
-LIBMAPLE_INCLUDES := -I$(LIBMAPLE_PATH) -I$(LIBMAPLE_PATH)/usb -I$(LIBMAPLE_PATH)/usb/usb_lib
-else
 BUILDDIRS       += $(BUILD_PATH)/$(d)/usbF4/STM32_USB_Device_Library/Core/src
 BUILDDIRS       += $(BUILD_PATH)/$(d)/usbF4/STM32_USB_Device_Library/Class/cdc/src
 BUILDDIRS       += $(BUILD_PATH)/$(d)/usbF4/STM32_USB_OTG_Driver/src
 BUILDDIRS       += $(BUILD_PATH)/$(d)/usbF4/VCP
 LIBMAPLE_INCLUDES := -I$(LIBMAPLE_PATH) -I$(LIBMAPLE_PATH)/usbF4
-endif
 
 
 # Local flags
@@ -42,18 +36,6 @@ cSRCS_$(d) := adc.c                    \
               usart.c                  \
               util.c                   
 
-ifneq ($(MCU_FAMILY), STM32F2)
-	cSRCS_$(d) += \
-              usb/descriptors.c        \
-              usb/usb.c                \
-              usb/usb_callbacks.c      \
-              usb/usb_hardware.c       \
-              usb/usb_lib/usb_core.c   \
-              usb/usb_lib/usb_init.c   \
-              usb/usb_lib/usb_int.c    \
-              usb/usb_lib/usb_mem.c    \
-              usb/usb_lib/usb_regs.c
-else
 	V=1
 	cSRCS_$(d) += \
 		usbF4/STM32_USB_Device_Library/Core/src/usbd_core.c \
@@ -69,11 +51,7 @@ else
 		usbF4/VCP/usbd_usr.c \
 		usbF4/usb.c \
 		usbF4/VCP/misc.c 
-endif
 
-ifneq ($(MCU_FAMILY), STM32F2)
-	cSRCS_$(d) += bkp.c
-endif
 
 sSRCS_$(d) := exc.S
 
diff --git a/STM32F4/cores/maple/libmaple/stm32.h b/STM32F4/cores/maple/libmaple/stm32.h
index 0d4deaa41..3921788e7 100644
--- a/STM32F4/cores/maple/libmaple/stm32.h
+++ b/STM32F4/cores/maple/libmaple/stm32.h
@@ -138,69 +138,8 @@
 
 #endif
 
-#if defined(MCU_STM32F103RB)
-    /* e.g., LeafLabs Maple */
 
-    #define STM32_NR_GPIO_PORTS          4
-    #define STM32_DELAY_US_MULT         12
-    #define STM32_SRAM_END              ((void*)0x20005000)
-
-    #define NR_GPIO_PORTS               STM32_NR_GPIO_PORTS
-    #define DELAY_US_MULT               STM32_DELAY_US_MULT
-
-#elif defined(MCU_STM32F103ZE)
-    /* e.g., LeafLabs Maple Native */
-
-    #define STM32_NR_GPIO_PORTS          7
-    #define STM32_DELAY_US_MULT         12
-    #define STM32_SRAM_END              ((void*)0x20010000)
-
-    #define NR_GPIO_PORTS               STM32_NR_GPIO_PORTS
-    #define DELAY_US_MULT               STM32_DELAY_US_MULT
-
-#elif defined(MCU_STM32F103CB)
-    /* e.g., LeafLabs Maple Mini */
-
-    /* This STM32_NR_GPIO_PORTS value is not, strictly speaking, true.
-     * But only pins 0 and 1 exist, and they're used for OSC on the
-     * Mini, so we'll live with this for now. */
-    #define STM32_NR_GPIO_PORTS          3
-    #define STM32_DELAY_US_MULT         12
-    #define STM32_SRAM_END              ((void*)0x20005000)
-
-    #define NR_GPIO_PORTS               STM32_NR_GPIO_PORTS
-    #define DELAY_US_MULT               STM32_DELAY_US_MULT
-
-#elif defined(MCU_STM32F103RE)
-    /* e.g., LeafLabs Maple RET6 edition */
-
-    #define STM32_NR_GPIO_PORTS          4
-    #define STM32_DELAY_US_MULT         12
-    #define STM32_SRAM_END              ((void*)0x20010000)
-
-    #define NR_GPIO_PORTS               STM32_NR_GPIO_PORTS
-    #define DELAY_US_MULT               STM32_DELAY_US_MULT
-
-#elif defined(MCU_STM32F103VE)
-    /* e.g., LeafLabs Maple Native */
-
-    #define STM32_NR_GPIO_PORTS          5
-    #define STM32_DELAY_US_MULT         12
-    #define STM32_SRAM_END              ((void*)0x20010000)
-
-    #define NR_GPIO_PORTS               STM32_NR_GPIO_PORTS
-    #define DELAY_US_MULT               STM32_DELAY_US_MULT
-
-#elif defined(MCU_STM32F205VE)
-	#define STM32_TICKS_PER_US          120
-    #define STM32_NR_GPIO_PORTS          5
-    #define STM32_DELAY_US_MULT         (STM32_TICKS_PER_US/3)
-    #define STM32_SRAM_END              ((void*)0x20010000)
-
-    #define NR_GPIO_PORTS               STM32_NR_GPIO_PORTS
-    #define DELAY_US_MULT               STM32_DELAY_US_MULT
-
-#elif defined(MCU_STM32F406VG)
+#if defined( STM32F4 )
 	#define STM32_TICKS_PER_US          168
     #define STM32_NR_GPIO_PORTS          5
     #define STM32_DELAY_US_MULT         (STM32_TICKS_PER_US/3)
diff --git a/STM32F4/cores/maple/libmaple/timer.h b/STM32F4/cores/maple/libmaple/timer.h
index fce6345b2..79b7d2996 100644
--- a/STM32F4/cores/maple/libmaple/timer.h
+++ b/STM32F4/cores/maple/libmaple/timer.h
@@ -113,13 +113,8 @@ typedef struct timer_bas_reg_map {
 } timer_bas_reg_map;
 
 
-#ifdef STM32F2
-  /** Timer 1 register map base pointer */
-  #define TIMER1_BASE        ((struct timer_adv_reg_map*)0x40010000)
-#else
-  /** Timer 1 register map base pointer */
-  #define TIMER1_BASE        ((struct timer_adv_reg_map*)0x40012C00)
-#endif
+/** Timer 1 register map base pointer */
+#define TIMER1_BASE        ((struct timer_adv_reg_map*)0x40010000)
 /** Timer 2 register map base pointer */
 #define TIMER2_BASE        ((struct timer_gen_reg_map*)0x40000000)
 /** Timer 3 register map base pointer */
@@ -133,14 +128,8 @@ typedef struct timer_bas_reg_map {
 #define TIMER6_BASE        ((struct timer_bas_reg_map*)0x40001000)
 /** Timer 7 register map base pointer */
 #define TIMER7_BASE        ((struct timer_bas_reg_map*)0x40001400)
-
-#ifdef STM32F2
-  /** Timer 8 register map base pointer */
-  #define TIMER8_BASE        ((struct timer_adv_reg_map*)0x40010400)
-#else
-  /** Timer 8 register map base pointer */
-  #define TIMER8_BASE        ((struct timer_adv_reg_map*)0x40013400)
-#endif
+/** Timer 8 register map base pointer */
+#define TIMER8_BASE        ((struct timer_adv_reg_map*)0x40010400)
 #endif
 
 /*
diff --git a/STM32F4/cores/maple/libmaple/usart.h b/STM32F4/cores/maple/libmaple/usart.h
index 3f7c88590..282293a17 100644
--- a/STM32F4/cores/maple/libmaple/usart.h
+++ b/STM32F4/cores/maple/libmaple/usart.h
@@ -62,11 +62,7 @@ typedef struct usart_reg_map {
 } usart_reg_map;
 
 /** USART1 register map base pointer */
-#ifdef STM32F2
-  #define USART1_BASE                   ((struct usart_reg_map*)0x40011000)
-#else
-  #define USART1_BASE                   ((struct usart_reg_map*)0x40013800)
-#endif
+#define USART1_BASE                   ((struct usart_reg_map*)0x40011000)
 /** USART2 register map base pointer */
 #define USART2_BASE                     ((struct usart_reg_map*)0x40004400)
 /** USART3 register map base pointer */
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_conf.h b/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_conf.h
index 61b0ac50c..fd45f4db3 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_conf.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_conf.h
@@ -173,7 +173,9 @@ typedef unsigned char		u8;
 #elif defined (__ICCARM__)     /* IAR Compiler */
   #define __packed    __packed
 #elif defined   ( __GNUC__ )   /* GNU Compiler */
+ #ifndef __packed
   #define __packed    __attribute__ ((__packed__))
+ #endif
 #elif defined   (__TASKING__)  /* TASKING Compiler */
   #define __packed    __unaligned
 #endif /* __CC_ARM */
@@ -206,7 +208,9 @@ typedef unsigned char		u8;
 #elif defined (__ICCARM__)     /* IAR Compiler */
   #define __packed    __packed
 #elif defined   ( __GNUC__ )   /* GNU Compiler */
+ #ifndef __packed
   #define __packed    __attribute__ ((__packed__))
+ #endif
 #elif defined   (__TASKING__)  /* TASKING Compiler */
   #define __packed    __unaligned
 #endif /* __CC_ARM */
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.c b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.c
index b13260ee5..28a2d1ff2 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.c
@@ -255,7 +255,7 @@ typedef struct {
 
 void systemHardReset(void) {
     SCB_TypeDef* rSCB = (SCB_TypeDef *) SCB_BASE;
-    typedef void (*funcPtr)(void);
+    //typedef void (*funcPtr)(void); // not used
 
     /* Reset */
     rSCB->AIRCR = (u32)AIRCR_RESET_REQ;
diff --git a/STM32F4/cores/maple/libmaple/usbF4/usb.c b/STM32F4/cores/maple/libmaple/usbF4/usb.c
index 2c0672f6a..263e76f84 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/usb.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/usb.c
@@ -3,7 +3,7 @@
 #include "usbd_desc.h"
 #include "usb.h"
 #include <gpio.h>
-#include <rccF2.h>
+#include <rccF4.h>
 #include <usbd_cdc_vcp.h>
 
 USB_OTG_CORE_HANDLE  USB_OTG_dev;
diff --git a/STM32F4/cores/maple/wirish.h b/STM32F4/cores/maple/wirish.h
index 4aca74c0b..a9068e7a7 100644
--- a/STM32F4/cores/maple/wirish.h
+++ b/STM32F4/cores/maple/wirish.h
@@ -46,7 +46,6 @@
 #include "wirish_math.h"
 #include "wirish_time.h"
 #include <wirish_constants.h>
-#include "HardwareSPI.h"
 #include "HardwareSerial.h"
 #include "HardwareTimer.h"
 #include "usb_serial.h"
diff --git a/STM32F4/cores/maple/wirish_analog.cpp b/STM32F4/cores/maple/wirish_analog.cpp
index 63b5eb2d0..4e920e7c7 100644
--- a/STM32F4/cores/maple/wirish_analog.cpp
+++ b/STM32F4/cores/maple/wirish_analog.cpp
@@ -28,9 +28,7 @@
  *  @brief Arduino-compatible ADC implementation.
  */
 
-#include "libmaple.h"
 #include "wirish.h"
-#include "io.h"
 
 /* Assumes that the ADC has been initialized and that the pin is set
  * to INPUT_ANALOG */
diff --git a/STM32F4/cores/maple/wirish_digital.cpp b/STM32F4/cores/maple/wirish_digital.cpp
index a8b3ad811..da180dcb4 100644
--- a/STM32F4/cores/maple/wirish_digital.cpp
+++ b/STM32F4/cores/maple/wirish_digital.cpp
@@ -29,7 +29,7 @@
  */
 
 #include "wirish.h"
-#include "io.h"
+
 
 void pinMode(uint8 pin, WiringPinMode mode) {
     gpio_pin_mode outputMode;
@@ -111,21 +111,21 @@ void togglePin(uint8 pin) {
 
 #define BUTTON_DEBOUNCE_DELAY 1
 
-uint8 isButtonPressed() {
-    if (digitalRead(BOARD_BUTTON_PIN)) {
+uint8 isButtonPressed(uint8_t button) {
+    if (digitalRead(button)) {
         delay(BUTTON_DEBOUNCE_DELAY);
-        while (digitalRead(BOARD_BUTTON_PIN))
+        while (digitalRead(button))
             ;
         return true;
     }
     return false;
 }
 
-uint8 waitForButtonPress(uint32 timeout) {
+uint8 waitForButtonPress(uint8_t button, uint32 timeout) {
     uint32 start = millis();
     uint32 time;
     if (timeout == 0) {
-        while (!isButtonPressed())
+        while (!isButtonPressed(button))
             ;
         return true;
     }
@@ -136,6 +136,6 @@ uint8 waitForButtonPress(uint32 timeout) {
             time - start > timeout) {
             return false;
         }
-    } while (!isButtonPressed());
+    } while (!isButtonPressed(button));
     return true;
 }
diff --git a/STM32F4/cores/maple/wirish_types.h b/STM32F4/cores/maple/wirish_types.h
index a3c260a73..2d6d6a9a6 100644
--- a/STM32F4/cores/maple/wirish_types.h
+++ b/STM32F4/cores/maple/wirish_types.h
@@ -48,6 +48,20 @@
  * @brief Stores STM32-specific information related to a given Maple pin.
  * @see PIN_MAP
  */
+#ifdef BOARD_black_f4
+// restructure members to build consecutive pairs
+typedef struct stm32_pin_info {
+    gpio_dev *gpio_device;      /**< Maple pin's GPIO device */
+    uint8 gpio_bit;             /**< Pin's GPIO port bit. */
+    timer_dev *timer_device;    /**< Pin's timer device, if any. */
+    uint8 timer_channel;        /**< Timer channel, or 0 if none. */
+    const adc_dev *adc_device;  /**< ADC device, if any. */
+    uint8 adc_channel;          /**< Pin ADC channel, or ADCx if none. */
+    uint8 filler;
+} stm32_pin_info;
+
+#else
+
 typedef struct stm32_pin_info {
     gpio_dev *gpio_device;      /**< Maple pin's GPIO device */
     timer_dev *timer_device;    /**< Pin's timer device, if any. */
@@ -58,6 +72,7 @@ typedef struct stm32_pin_info {
     uint8 filler;
 } stm32_pin_info;
 
+#endif
 /**
  * Variable attribute, instructs the linker to place the marked
  * variable in Flash instead of RAM. */
diff --git a/STM32F4/platform.txt b/STM32F4/platform.txt
index 99ae55549..b32f283dc 100755
--- a/STM32F4/platform.txt
+++ b/STM32F4/platform.txt
@@ -12,13 +12,13 @@ version=0.1.0
 
 compiler.path={runtime.tools.arm-none-eabi-gcc.path}/bin/
 compiler.c.cmd=arm-none-eabi-gcc
-compiler.c.flags=-c -g -Os -w -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
+compiler.c.flags=-c -g -Os -Wall -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
 compiler.c.elf.cmd=arm-none-eabi-g++
 compiler.c.elf.flags=-Os -Wl,--gc-sections
 compiler.S.cmd=arm-none-eabi-gcc
 compiler.S.flags=-c -g -x assembler-with-cpp -MMD
 compiler.cpp.cmd=arm-none-eabi-g++
-compiler.cpp.flags=-c -g -Os -w -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
+compiler.cpp.flags=-c -g -Os -Wall -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
 compiler.ar.cmd=arm-none-eabi-ar
 compiler.ar.flags=rcs
 compiler.objcopy.cmd=arm-none-eabi-objcopy
@@ -44,12 +44,10 @@ compiler.ar.extra_flags=
 compiler.elf2hex.extra_flags=
 
 
-
 ##compiler.libs.c.flags="-I{build.system.path}/libmaple" "-I{build.system.path}/libmaple/include" "-I{build.system.path}/libmaple/stm32f1/include" "-I{build.system.path}/libmaple/stm32f1/include/series" "-I{build.system.path}/libmaple/usb/stm32f1" "-I{build.system.path}/libmaple/usb/usb_lib" 
 #compiler.libs.c.flags="-I{build.system.path}/libmaple" "-I{build.system.path}/libmaple/include" "-I{build.system.path}/libmaple/stm32f1/include"                                                           "-I{build.system.path}/libmaple/usb/stm32f1" "-I{build.system.path}/libmaple/usb/usb_lib" 
 
-
-compiler.libs.c.flags="-I{build.core.path}/libmaple" -I{build.core.path}/libmaple/usbF4 -I{build.core.path}/libmaple/usbF4/STM32_USB_Device_Library/Core/inc -I{build.core.path}/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/inc -I{build.core.path}/libmaple/usbF4/STM32_USB_OTG_Driver/inc -I{build.core.path}/libmaple/usbF4/VCP 
+compiler.libs.c.flags=-I{build.core.path} -I{build.core.path}/libmaple -I{build.core.path}/libmaple/usbF4 -I{build.core.path}/libmaple/usbF4/STM32_USB_Device_Library/Core/inc -I{build.core.path}/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/inc -I{build.core.path}/libmaple/usbF4/STM32_USB_OTG_Driver/inc -I{build.core.path}/libmaple/usbF4/VCP 
 
 
 

From 065f58684dfb4ee6728b7a40c58f06b6380911a7 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Fri, 14 Apr 2017 19:26:18 +0200
Subject: [PATCH 048/307] added black F4 variant files + activated USB
 interface

---
 STM32F4/cores/maple/libmaple/dmaF4.c          | 241 ++++++
 STM32F4/cores/maple/libmaple/dmaF4.h          | 270 +++++++
 STM32F4/cores/maple/libmaple/gpioF4.c         | 224 ++++++
 STM32F4/cores/maple/libmaple/gpioF4.h         | 550 ++++++++++++++
 STM32F4/cores/maple/libmaple/rccF4.c          | 707 ++++++++++++++++++
 STM32F4/cores/maple/libmaple/rccF4.h          | 642 ++++++++++++++++
 STM32F4/variants/black_f407vet6/black_f4.cpp  | 264 +++++++
 STM32F4/variants/black_f407vet6/black_f4.h    | 130 ++++
 STM32F4/variants/black_f407vet6/ld/common.inc | 219 ++++++
 .../variants/black_f407vet6/ld/extra_libs.inc |   7 +
 STM32F4/variants/black_f407vet6/ld/flash.ld   |  20 +
 STM32F4/variants/black_f407vet6/ld/jtag.ld    |  20 +
 STM32F4/variants/black_f407vet6/ld/names.inc  |  78 ++
 STM32F4/variants/black_f407vet6/ld/ram.ld     |  19 +
 .../black_f407vet6/ld/vector_symbols.inc      |  78 ++
 .../variants/black_f407vet6/pins_arduino.h    |   6 +
 STM32F4/variants/black_f407vet6/stm32_isrs.S  | 323 ++++++++
 .../black_f407vet6/stm32_vector_table.S       | 113 +++
 STM32F4/variants/black_f407vet6/variant.h     |  21 +
 .../variants/black_f407vet6/wirish/start.S    |  57 ++
 .../variants/black_f407vet6/wirish/start_c.c  |  95 +++
 21 files changed, 4084 insertions(+)
 create mode 100644 STM32F4/cores/maple/libmaple/dmaF4.c
 create mode 100644 STM32F4/cores/maple/libmaple/dmaF4.h
 create mode 100644 STM32F4/cores/maple/libmaple/gpioF4.c
 create mode 100644 STM32F4/cores/maple/libmaple/gpioF4.h
 create mode 100644 STM32F4/cores/maple/libmaple/rccF4.c
 create mode 100644 STM32F4/cores/maple/libmaple/rccF4.h
 create mode 100644 STM32F4/variants/black_f407vet6/black_f4.cpp
 create mode 100644 STM32F4/variants/black_f407vet6/black_f4.h
 create mode 100644 STM32F4/variants/black_f407vet6/ld/common.inc
 create mode 100644 STM32F4/variants/black_f407vet6/ld/extra_libs.inc
 create mode 100644 STM32F4/variants/black_f407vet6/ld/flash.ld
 create mode 100644 STM32F4/variants/black_f407vet6/ld/jtag.ld
 create mode 100644 STM32F4/variants/black_f407vet6/ld/names.inc
 create mode 100644 STM32F4/variants/black_f407vet6/ld/ram.ld
 create mode 100644 STM32F4/variants/black_f407vet6/ld/vector_symbols.inc
 create mode 100644 STM32F4/variants/black_f407vet6/pins_arduino.h
 create mode 100644 STM32F4/variants/black_f407vet6/stm32_isrs.S
 create mode 100644 STM32F4/variants/black_f407vet6/stm32_vector_table.S
 create mode 100644 STM32F4/variants/black_f407vet6/variant.h
 create mode 100644 STM32F4/variants/black_f407vet6/wirish/start.S
 create mode 100644 STM32F4/variants/black_f407vet6/wirish/start_c.c

diff --git a/STM32F4/cores/maple/libmaple/dmaF4.c b/STM32F4/cores/maple/libmaple/dmaF4.c
new file mode 100644
index 000000000..4b530aff8
--- /dev/null
+++ b/STM32F4/cores/maple/libmaple/dmaF4.c
@@ -0,0 +1,241 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Michael Hope.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+#ifdef STM32F4
+ 
+/**
+ * @file dmaF4.c
+ * @brief Direct Memory Access peripheral support
+ */
+
+#include "dma.h"
+#include "bitband.h"
+#include "util.h"
+
+/*
+ * Devices
+ */
+
+static dma_dev dma1 = {
+    .regs     = DMA1_BASE,
+    .clk_id   = RCC_DMA1,
+    .handlers = {{ .handler = NULL, .irq_line = 11 },
+                 { .handler = NULL, .irq_line = 12 },
+                 { .handler = NULL, .irq_line = 13 },
+                 { .handler = NULL, .irq_line = 14 },
+                 { .handler = NULL, .irq_line = 15 },
+                 { .handler = NULL, .irq_line = 16 },
+                 { .handler = NULL, .irq_line = 17 },
+                 { .handler = NULL, .irq_line = 47 }}
+};
+/** DMA1 device */
+dma_dev *DMA1 = &dma1;
+
+static dma_dev dma2 = {
+    .regs     = DMA2_BASE,
+    .clk_id   = RCC_DMA2,
+    .handlers = {{ .handler = NULL, .irq_line = 56 },
+                 { .handler = NULL, .irq_line = 57 },
+                 { .handler = NULL, .irq_line = 58 },
+                 { .handler = NULL, .irq_line = 59 },
+                 { .handler = NULL, .irq_line = 60 },
+                 { .handler = NULL, .irq_line = 68 },
+                 { .handler = NULL, .irq_line = 69 },
+                 { .handler = NULL, .irq_line = 70 }} /* !@#$ */
+};
+/** DMA2 device */
+dma_dev *DMA2 = &dma2;
+
+
+/*
+ * Convenience routines
+ */
+
+/**
+ * @brief Initialize a DMA device.
+ * @param dev Device to initialize.
+ */
+void dma_init(dma_dev *dev) {
+    rcc_clk_enable(dev->clk_id);
+}
+
+/**
+ * @brief Attach an interrupt to a DMA transfer.
+ *
+ * Interrupts are enabled using appropriate mode flags in
+ * dma_setup_transfer().
+ *
+ * @param dev DMA device
+ * @param stream Stream to attach handler to
+ * @param handler Interrupt handler to call when channel interrupt fires.
+ * @see dma_setup_transfer()
+ * @see dma_detach_interrupt()
+ */
+void dma_attach_interrupt(dma_dev *dev,
+                          dma_stream stream,
+                          void (*handler)(void)) {
+    dev->handlers[stream].handler = handler;
+    nvic_irq_enable(dev->handlers[stream].irq_line);
+}
+
+/**
+ * @brief Detach a DMA transfer interrupt handler.
+ *
+ * After calling this function, the given channel's interrupts will be
+ * disabled.
+ *
+ * @param dev DMA device
+ * @param stream Stream whose handler to detach
+ * @sideeffect Clears interrupt enable bits in the channel's CCR register.
+ * @see dma_attach_interrupt()
+ */
+void dma_detach_interrupt(dma_dev *dev, dma_stream stream) {
+    nvic_irq_disable(dev->handlers[stream].irq_line);
+    dev->handlers[stream].handler = NULL;
+}
+
+void dma_clear_isr_bits(dma_dev *dev, dma_stream stream) {
+    switch (stream) {
+    case 0:
+        dev->regs->LIFCR|=0x0000003d;
+        break;
+    case 1:
+        dev->regs->LIFCR|=0x00000f40;
+        break;
+    case 2:
+        dev->regs->LIFCR|=0x003d0000;
+        break;
+    case 3:
+        dev->regs->LIFCR|=0x0f400000;
+        break;
+    case 4:
+        dev->regs->HIFCR|=0x0000003d;
+        break;
+    case 5:
+        dev->regs->HIFCR|=0x00000f40;
+        break;
+    case 6:
+        dev->regs->HIFCR|=0x003d0000;
+        break;
+    case 7:
+        dev->regs->HIFCR|=0x0f400000;
+        break;
+    }
+}
+
+/*
+ * IRQ handlers
+ */
+
+static inline void dispatch_handler(dma_dev *dev, dma_stream stream) {
+    void (*handler)(void) = dev->handlers[stream].handler;
+    if (handler) {
+        handler();
+        dma_clear_isr_bits(dev, stream); /* in case handler doesn't */
+    }
+}
+
+//void __irq_dma1_stream0(void) {
+void __irq_dma1_channel1(void) {
+    dispatch_handler(DMA1, DMA_STREAM0);
+}
+
+//void __irq_dma1_stream1(void) {
+void __irq_dma1_channel2(void) {
+    dispatch_handler(DMA1, DMA_STREAM1);
+}
+
+//void __irq_dma1_stream2(void) {
+void __irq_dma1_channel3(void) {
+    dispatch_handler(DMA1, DMA_STREAM2);
+}
+
+//void __irq_dma1_stream3(void) {
+void __irq_dma1_channel4(void) {
+    dispatch_handler(DMA1, DMA_STREAM3);
+}
+
+//void __irq_dma1_stream4(void) {
+void __irq_dma1_channel5(void) {
+    dispatch_handler(DMA1, DMA_STREAM4);
+}
+
+//void __irq_dma1_stream5(void) {
+void __irq_dma1_channel6(void) {
+    dispatch_handler(DMA1, DMA_STREAM5);
+}
+
+//void __irq_dma1_stream6(void) {
+void __irq_dma1_channel7(void) {
+    dispatch_handler(DMA1, DMA_STREAM6);
+}
+
+//void __irq_dma1_stream7(void) {
+void __irq_adc3(void) {
+    dispatch_handler(DMA1, DMA_STREAM7);
+}
+
+//void __irq_dma2_stream0(void) {
+void __irq_dma2_channel1(void) {
+    dispatch_handler(DMA2, DMA_STREAM0);
+}
+
+//void __irq_dma2_stream1(void) {
+void __irq_dma2_channel2(void) {
+    dispatch_handler(DMA2, DMA_STREAM1);
+}
+
+//void __irq_dma2_stream2(void) {
+void __irq_dma2_channel3(void) {
+    dispatch_handler(DMA2, DMA_STREAM2);
+}
+
+//void __irq_dma2_stream3(void) {
+void __irq_dma2_channel4_5(void) {
+    dispatch_handler(DMA2, DMA_STREAM3);
+}
+
+//void __irq_dma2_stream4(void) {
+void __irq_DMA2_Stream4_IRQHandler(void) {
+    dispatch_handler(DMA2, DMA_STREAM4);
+}
+
+//void __irq_dma2_stream5(void) {
+void __irq_DMA2_Stream5_IRQHandler(void) {
+    dispatch_handler(DMA2, DMA_STREAM5);
+}
+
+//void __irq_dma2_stream6(void) {
+void __irq_DMA2_Stream6_IRQHandler(void) {
+    dispatch_handler(DMA2, DMA_STREAM6);
+}
+
+//void __irq_dma2_stream7(void) {
+void __irq_DMA2_Stream7_IRQHandler(void) {
+    dispatch_handler(DMA2, DMA_STREAM7);
+}
+
+#endif
diff --git a/STM32F4/cores/maple/libmaple/dmaF4.h b/STM32F4/cores/maple/libmaple/dmaF4.h
new file mode 100644
index 000000000..6f7086f36
--- /dev/null
+++ b/STM32F4/cores/maple/libmaple/dmaF4.h
@@ -0,0 +1,270 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Michael Hope.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file dma.h
+ *
+ * @author Marti Bolivar <mbolivar@leaflabs.com>;
+ *         Original implementation by Michael Hope
+ *
+ * @brief Direct Memory Access peripheral support
+ */
+
+/*
+ * See /notes/dma.txt for more information.
+ */
+
+#ifndef _DMA_H_
+#define _DMA_H_
+
+#include "libmaple_types.h"
+#include "rcc.h"
+#include "nvic.h"
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*
+ * Register maps
+ */
+
+/**
+ * @brief DMA stream type.
+ *
+ */
+typedef struct dma_stream_t {
+    __io uint32 CR;           /**< Stream configuration register */
+    __io uint32 NDTR;         /**< Stream number of data register */
+    __io uint32 PAR;          /**< Stream peripheral address register */
+    __io uint32 M0AR;         /**< Stream memory address register 0 */
+    __io uint32 M1AR;         /**< Stream memory address register 1 */
+    __io uint32 FCR;           /**< Stream FIFO configuration register */
+} dma_stream_t;
+/**
+ * @brief DMA register map type.
+ *
+ */
+typedef struct dma_reg_map {
+    __io uint32 LISR;           /**< Low interrupt status register */
+    __io uint32 HISR;           /**< High interrupt status register */
+    __io uint32 LIFCR;          /**< Low interrupt flag clear register */
+    __io uint32 HIFCR;          /**< High interrupt flag clear register */
+    dma_stream_t  STREAM[8];
+} dma_reg_map;
+
+/** DMA controller register map base pointers */
+#define DMA1_BASE                       ((struct dma_reg_map*)0x40026000)
+#define DMA2_BASE                       ((struct dma_reg_map*)0x40026400)
+
+/*
+ * Register bit definitions
+ */
+
+/* Channel configuration register */
+
+#define DMA_CR_CH0                      (0x0 << 25)
+#define DMA_CR_CH1                      (0x1 << 25)
+#define DMA_CR_CH2                      (0x2 << 25)
+#define DMA_CR_CH3                      (0x3 << 25)
+#define DMA_CR_CH4                      (0x4 << 25)
+#define DMA_CR_CH5                      (0x5 << 25)
+#define DMA_CR_CH6                      (0x6 << 25)
+#define DMA_CR_CH7                      (0x7 << 25)
+#define DMA_CR_MBURST0                  (0x0 << 23)
+#define DMA_CR_MBURST4                  (0x1 << 23)
+#define DMA_CR_MBURST8                  (0x2 << 23)
+#define DMA_CR_MBURST16                 (0x3 << 23)
+#define DMA_CR_PBURST0                  (0x0 << 21)
+#define DMA_CR_PBURST4                  (0x1 << 21)
+#define DMA_CR_PBURST8                  (0x2 << 21)
+#define DMA_CR_PBURST16                 (0x3 << 21)
+#define DMA_CR_CT0                      (0x0 << 19)
+#define DMA_CR_CT1                      (0x1 << 19)
+#define DMA_CR_DBM                      (0x1 << 18)
+
+#define DMA_CR_PL_LOW                   (0x0 << 16)
+#define DMA_CR_PL_MEDIUM                (0x1 << 16)
+#define DMA_CR_PL_HIGH                  (0x2 << 16)
+#define DMA_CR_PL_VERY_HIGH             (0x3 << 16)
+#define DMA_CR_PL_MASK                  (0x3 << 16)
+
+#define DMA_CR_PINCOS                   (0x1 << 15)
+
+#define DMA_CR_MSIZE_8BITS              (0x0 << 13)
+#define DMA_CR_MSIZE_16BITS             (0x1 << 13)
+#define DMA_CR_MSIZE_32BITS             (0x2 << 13)
+
+#define DMA_CR_PSIZE_8BITS              (0x0 << 11)
+#define DMA_CR_PSIZE_16BITS             (0x1 << 11)
+#define DMA_CR_PSIZE_32BITS             (0x2 << 11)
+
+#define DMA_CR_MINC                     (0x1 << 10)
+#define DMA_CR_PINC                     (0x1 << 9)
+#define DMA_CR_CIRC                     (0x1 << 8)
+#define DMA_CR_DIR_P2M                  (0x0 << 6)
+#define DMA_CR_DIR_M2P                  (0x1 << 6)
+#define DMA_CR_DIR_M2M                  (0x2 << 6)
+
+#define DMA_CR_PFCTRL                   (0x1 << 5)
+#define DMA_CR_TCIE                     (0x1 << 4)
+#define DMA_CR_HTIE                     (0x1 << 3)
+#define DMA_CR_TEIE                     (0x1 << 2)
+#define DMA_CR_DMEIE                    (0x1 << 1)
+#define DMA_CR_EN                       (0x1)
+
+/*
+ * Devices
+ */
+
+/** Encapsulates state related to a DMA channel interrupt. */
+typedef struct dma_handler_config {
+    void (*handler)(void);      /**< User-specified channel interrupt
+                                     handler */
+    nvic_irq_num irq_line;      /**< Channel's NVIC interrupt number */
+} dma_handler_config;
+
+/** DMA device type */
+typedef struct dma_dev {
+    dma_reg_map *regs;             /**< Register map */
+    rcc_clk_id clk_id;             /**< Clock ID */
+    dma_handler_config handlers[]; /**<
+                                    * @brief IRQ handlers and NVIC numbers.
+                                    *
+                                    * @see dma_attach_interrupt()
+                                    * @see dma_detach_interrupt()
+                                    */
+} dma_dev;
+
+extern dma_dev *DMA1;
+extern dma_dev *DMA2;
+
+/*
+ * Convenience functions
+ */
+
+void dma_init(dma_dev *dev);
+
+/** Flags for DMA transfer configuration. */
+typedef enum dma_mode_flags {
+    DMA_MEM_2_MEM  = 1 << 14, /**< Memory to memory mode */
+    DMA_MINC_MODE  = 1 << 7,  /**< Auto-increment memory address */
+    DMA_PINC_MODE  = 1 << 6,  /**< Auto-increment peripheral address */
+    DMA_CIRC_MODE  = 1 << 5,  /**< Circular mode */
+    DMA_FROM_MEM   = 1 << 4,  /**< Read from memory to peripheral */
+    DMA_TRNS_ERR   = 1 << 3,  /**< Interrupt on transfer error */
+    DMA_HALF_TRNS  = 1 << 2,  /**< Interrupt on half-transfer */
+    DMA_TRNS_CMPLT = 1 << 1   /**< Interrupt on transfer completion */
+} dma_mode_flags;
+
+/** Source and destination transfer sizes. */
+typedef enum dma_xfer_size {
+    DMA_SIZE_8BITS  = 0,        /**< 8-bit transfers */
+    DMA_SIZE_16BITS = 1,        /**< 16-bit transfers */
+    DMA_SIZE_32BITS = 2         /**< 32-bit transfers */
+} dma_xfer_size;
+
+/** DMA channel */
+typedef enum dma_stream {
+    DMA_STREAM0 = 0,                /**< Stream 0 */
+    DMA_STREAM1 = 1,                /**< Stream 1 */
+    DMA_STREAM2 = 2,                /**< Stream 2 */
+    DMA_STREAM3 = 3,                /**< Stream 3 */
+    DMA_STREAM4 = 4,                /**< Stream 4 */
+    DMA_STREAM5 = 5,                /**< Stream 5 */
+    DMA_STREAM6 = 6,                /**< Stream 6 */
+    DMA_STREAM7 = 7,                /**< Stream 7 */
+} dma_stream;
+    
+static inline void dma_setup_transfer(dma_dev       *dev,
+                                      dma_stream    stream,
+                                      __io void     *peripheral_address,
+                                      __io void     *memory_address0,
+                                      __io void     *memory_address1,
+                                      uint32         flags,
+                                      uint32         fifo_flags) {
+    dev->regs->STREAM[stream].CR &= ~DMA_CR_EN; // disable
+    dev->regs->STREAM[stream].PAR = (uint32)peripheral_address;
+    dev->regs->STREAM[stream].M0AR = (uint32)memory_address0;
+    dev->regs->STREAM[stream].M1AR = (uint32)memory_address1;
+    dev->regs->STREAM[stream].FCR = fifo_flags & 0x87; // mask out reserved bits
+    dev->regs->STREAM[stream].CR = flags & 0x0feffffe; // mask out reserved and enable
+}
+    
+static inline void dma_set_num_transfers(dma_dev *dev,
+                                         dma_stream stream,
+                                         uint16 num_transfers) {
+    dev->regs->STREAM[stream].NDTR = num_transfers;
+}
+
+void dma_attach_interrupt(dma_dev *dev,
+                          dma_stream stream,
+                          void (*handler)(void));
+
+void dma_detach_interrupt(dma_dev *dev, dma_stream stream);
+
+static inline void dma_enable(dma_dev *dev, dma_stream stream) {
+    dev->regs->STREAM[stream].CR |= DMA_CR_EN;
+}    
+
+static inline void dma_disable(dma_dev *dev, dma_stream stream) {
+    dev->regs->STREAM[stream].CR &= ~DMA_CR_EN;
+}    
+
+/**
+ * @brief Check if a DMA stream is enabled
+ * @param dev DMA device
+ * @param stream Stream whose enabled bit to check.
+ */
+static inline uint8 dma_is_stream_enabled(dma_dev *dev, dma_stream stream) {
+    return (uint8)(dev->regs->STREAM[stream].CR & DMA_CR_EN);
+}
+
+/**
+ * @brief Get the ISR status bits for a DMA stream.
+ *
+ * The bits are returned right-aligned, in the following order:
+ * transfer error flag, half-transfer flag, transfer complete flag,
+ * global interrupt flag.
+ *
+ * @param dev DMA device
+ * @param stream Stream whose ISR bits to return.
+ */
+uint8 dma_get_isr_bits(dma_dev *dev, dma_stream stream);
+
+/**
+ * @brief Clear the ISR status bits for a given DMA stream.
+ *
+ * @param dev DMA device
+ * @param stream Stream whose ISR bits to clear.
+ */
+void dma_clear_isr_bits(dma_dev *dev, dma_stream stream);
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif
diff --git a/STM32F4/cores/maple/libmaple/gpioF4.c b/STM32F4/cores/maple/libmaple/gpioF4.c
new file mode 100644
index 000000000..ba166f538
--- /dev/null
+++ b/STM32F4/cores/maple/libmaple/gpioF4.c
@@ -0,0 +1,224 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Perry Hung.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+ #ifdef STM32F4
+ 
+/**
+ * @file gpio.c
+ * @brief GPIO initialization routine
+ */
+
+#include "gpio.h"
+#include "rcc.h"
+
+/*
+ * GPIO devices
+ */
+
+gpio_dev gpioa = {
+    .regs      = GPIOA_BASE,
+    .clk_id    = RCC_GPIOA,
+    .exti_port = AFIO_EXTI_PA,
+};
+/** GPIO port A device. */
+gpio_dev* const GPIOA = &gpioa;
+
+gpio_dev gpiob = {
+    .regs      = GPIOB_BASE,
+    .clk_id    = RCC_GPIOB,
+    .exti_port = AFIO_EXTI_PB,
+};
+/** GPIO port B device. */
+gpio_dev* const GPIOB = &gpiob;
+
+gpio_dev gpioc = {
+    .regs      = GPIOC_BASE,
+    .clk_id    = RCC_GPIOC,
+    .exti_port = AFIO_EXTI_PC,
+};
+/** GPIO port C device. */
+gpio_dev* const GPIOC = &gpioc;
+
+gpio_dev gpiod = {
+    .regs      = GPIOD_BASE,
+    .clk_id    = RCC_GPIOD,
+    .exti_port = AFIO_EXTI_PD,
+};
+/** GPIO port D device. */
+gpio_dev* const GPIOD = &gpiod;
+
+#ifdef STM32_HIGH_DENSITY
+gpio_dev gpioe = {
+    .regs      = GPIOE_BASE,
+    .clk_id    = RCC_GPIOE,
+    .exti_port = AFIO_EXTI_PE,
+};
+/** GPIO port E device. */
+gpio_dev* const GPIOE = &gpioe;
+
+gpio_dev gpiof = {
+    .regs      = GPIOF_BASE,
+    .clk_id    = RCC_GPIOF,
+    .exti_port = AFIO_EXTI_PF,
+};
+/** GPIO port F device. */
+gpio_dev* const GPIOF = &gpiof;
+
+gpio_dev gpiog = {
+    .regs      = GPIOG_BASE,
+    .clk_id    = RCC_GPIOG,
+    .exti_port = AFIO_EXTI_PG,
+};
+/** GPIO port G device. */
+gpio_dev* const GPIOG = &gpiog;
+#endif
+
+/*
+ * GPIO convenience routines
+ */
+
+/**
+ * Initialize a GPIO device.
+ *
+ * Enables the clock for and resets the given device.
+ *
+ * @param dev GPIO device to initialize.
+ */
+void gpio_init(gpio_dev *dev) {
+    rcc_clk_enable(dev->clk_id);
+    rcc_reset_dev(dev->clk_id);
+}
+
+/**
+ * Initialize and reset all available GPIO devices.
+ */
+void gpio_init_all(void) {
+    gpio_init(GPIOA);
+    gpio_init(GPIOB);
+    gpio_init(GPIOC);
+    gpio_init(GPIOD);
+
+#ifdef STM32_HIGH_DENSITY
+    gpio_init(GPIOE);
+    gpio_init(GPIOF);
+    gpio_init(GPIOG);
+#endif
+
+#ifdef ARDUINO_STM32F4_NETDUINO2PLUS
+    // PA8 Output the Master Clock MCO1
+    gpio_set_af_mode(GPIOA, 8, 0);
+    gpio_set_mode(GPIOA, 8, GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
+    // PB4 as alternate MISO Input
+    gpio_set_af_mode(GPIOB, 4, 5);
+    // PA5 as alternate SCK Output
+    gpio_set_af_mode(GPIOA, 5, 5);
+    // PA7 as alternate MOSI Output
+    gpio_set_af_mode(GPIOA, 7, 5);
+#endif
+}
+
+/**
+ * Set the mode of a GPIO pin.
+ *
+ * @param dev GPIO device.
+ * @param pin Pin on the device whose mode to set, 0--15.
+ * @param mode General purpose or alternate function mode to set the pin to.
+ * @see gpio_pin_mode
+ */
+void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode) {
+    gpio_reg_map *regs = dev->regs;
+
+	//regs->AFR[pin/8] = (regs->AFR[pin/8] & ~(15 << (4*(pin&7)))) | (((mode >> 8) & 15) << (4*(pin&7)));
+	//gpio_set_af_mode(dev, pin, mode>>8);
+
+    regs->MODER      = (regs->MODER      & ~( 3 << (2*pin)))     | (((mode >> 0) & 3)  << (2*pin));
+    regs->PUPDR      = (regs->PUPDR      & ~( 3 << (2*pin)))     | (((mode >> 2) & 3)  << (2*pin));
+    regs->OSPEEDR    = (regs->OSPEEDR    & ~( 3 << (2*pin)))     | (((mode >> 4) & 3)  << (2*pin));
+    regs->OTYPER     = (regs->OTYPER     & ~( 1 << (1*pin)))     | (((mode >> 6) & 1)  << (1*pin));
+}
+
+/**
+ * Set the alternate function mode of a GPIO pin.
+ *
+ * @param dev GPIO device.
+ * @param pin Pin on the device whose mode to set, 0--15.
+ * @param mode alternate function mode to set the pin to.
+ * @see gpio_pin_mode
+ */
+void gpio_set_af_mode(gpio_dev *dev, uint8 pin, int mode) {
+    gpio_reg_map *regs = dev->regs;
+
+	regs->AFR[pin/8] = (regs->AFR[pin/8] & ~(15 << (4*(pin&7)))) | (((mode >> 0) & 15) << (4*(pin&7)));
+}
+
+/*
+ * AFIO
+ */
+
+/**
+ * @brief Initialize the AFIO clock, and reset the AFIO registers.
+ */
+void afio_init(void) {
+    //rcc_clk_enable(RCC_AFIO);
+    //rcc_reset_dev(RCC_AFIO);
+}
+
+#define AFIO_EXTI_SEL_MASK 0xF
+
+/**
+ * @brief Select a source input for an external interrupt.
+ *
+ * @param exti      External interrupt.
+ * @param gpio_port Port which contains pin to use as source input.
+ * @see afio_exti_num
+ * @see afio_exti_port
+ */
+void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port) {
+    __io uint32 *exti_cr = &SYSCFG_BASE->EXTICR1 + exti / 4;
+    uint32 shift = 4 * (exti % 4);
+    uint32 cr = *exti_cr;
+
+    cr &= ~(AFIO_EXTI_SEL_MASK << shift);
+    cr |= gpio_port << shift;
+    *exti_cr = cr;
+}
+
+/**
+ * @brief Perform an alternate function remap.
+ * @param remapping Remapping to perform.
+ */
+#if 0
+void afio_remap(afio_remap_peripheral remapping) {
+    if (remapping & AFIO_REMAP_USE_MAPR2) {
+        remapping &= ~AFIO_REMAP_USE_MAPR2;
+        AFIO_BASE->MAPR2 |= remapping;
+    } else {
+        AFIO_BASE->MAPR |= remapping;
+    }
+}
+#endif
+
+#endif
diff --git a/STM32F4/cores/maple/libmaple/gpioF4.h b/STM32F4/cores/maple/libmaple/gpioF4.h
new file mode 100644
index 000000000..91bd67be3
--- /dev/null
+++ b/STM32F4/cores/maple/libmaple/gpioF4.h
@@ -0,0 +1,550 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Perry Hung.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+*****************************************************************************/
+
+/**
+ *  @file gpio.h
+ *
+ *  @brief General purpose I/O (GPIO) and Alternate Function I/O
+ *         (AFIO) prototypes, defines, and inlined access functions.
+ */
+
+#ifndef _GPIO_H_
+#define _GPIO_H_
+
+#include "libmaple.h"
+#include "rcc.h"
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/*
+ * GPIO register maps and devices
+ */
+
+/** GPIO register map type */
+typedef struct gpio_reg_map {
+    __io uint32 MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
+    __io uint32 OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
+    __io uint32 OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
+    __io uint32 PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+    __io uint32 IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
+    __io uint32 ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
+    __io uint16 BSRRL;    /*!< GPIO port bit set/reset low register,  Address offset: 0x18      */
+    __io uint16 BSRRH;    /*!< GPIO port bit set/reset high register, Address offset: 0x1A      */
+    __io uint32 LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+    __io uint32 AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x24-0x28 */
+} gpio_reg_map;
+
+
+
+/**
+ * @brief External interrupt line port selector.
+ *
+ * Used to determine which GPIO port to map an external interrupt line
+ * onto. */
+/* (See AFIO sections, below) */
+typedef enum afio_exti_port {
+    AFIO_EXTI_PA,               /**< Use port A (PAx) pin. */
+    AFIO_EXTI_PB,               /**< Use port B (PBx) pin. */
+    AFIO_EXTI_PC,               /**< Use port C (PCx) pin. */
+    AFIO_EXTI_PD,               /**< Use port D (PDx) pin. */
+#ifdef STM32_HIGH_DENSITY
+    AFIO_EXTI_PE,               /**< Use port E (PEx) pin. */
+    AFIO_EXTI_PF,               /**< Use port F (PFx) pin. */
+    AFIO_EXTI_PG,               /**< Use port G (PGx) pin. */
+#endif
+} afio_exti_port;
+
+/** GPIO device type */
+typedef struct gpio_dev {
+    gpio_reg_map *regs;       /**< Register map */
+    rcc_clk_id clk_id;        /**< RCC clock information */
+    afio_exti_port exti_port; /**< AFIO external interrupt port value */
+} gpio_dev;
+
+extern gpio_dev gpioa;
+extern gpio_dev* const GPIOA;
+extern gpio_dev gpiob;
+extern gpio_dev* const GPIOB;
+extern gpio_dev gpioc;
+extern gpio_dev* const GPIOC;
+extern gpio_dev gpiod;
+extern gpio_dev* const GPIOD;
+#ifdef STM32_HIGH_DENSITY
+extern gpio_dev gpioe;
+extern gpio_dev* const GPIOE;
+extern gpio_dev gpiof;
+extern gpio_dev* const GPIOF;
+extern gpio_dev gpiog;
+extern gpio_dev* const GPIOG;
+#endif
+
+/** GPIO port register map base pointer */
+#define GPIOA_BASE                      ((struct gpio_reg_map*)0x40020000)
+#define GPIOB_BASE                      ((struct gpio_reg_map*)0x40020400)
+#define GPIOC_BASE                      ((struct gpio_reg_map*)0x40020800)
+#define GPIOD_BASE                      ((struct gpio_reg_map*)0x40020C00)
+#ifdef STM32_HIGH_DENSITY
+#define GPIOE_BASE                      ((struct gpio_reg_map*)0x40021000)
+#define GPIOF_BASE                      ((struct gpio_reg_map*)0x40021400)
+#define GPIOG_BASE                      ((struct gpio_reg_map*)0x40021800)
+#endif
+
+/*
+ * GPIO register bit definitions
+ */
+
+#define GPIO_MODE_INPUT                 0
+#define GPIO_MODE_OUTPUT                1
+#define GPIO_MODE_AF                    2
+#define GPIO_MODE_ANALOG                3
+
+#define GPIO_PUPD_INPUT_FLOATING        (0 << 2)
+#define GPIO_PUPD_INPUT_PU              (1 << 2)
+#define GPIO_PUPD_INPUT_PD              (2 << 2)
+
+#define GPIO_OSPEED_2MHZ                (0 << 4)
+#define GPIO_OSPEED_25MHZ               (1 << 4)
+#define GPIO_OSPEED_50MHZ               (2 << 4)
+#define GPIO_OSPEED_100MHZ              (3 << 4)
+
+#define GPIO_OTYPE_PP                   (0 << 6)
+#define GPIO_OTYPE_OD                   (1 << 6)
+
+/*
+MODER
+00: Input (reset state)
+01: General purpose output mode
+10: Alternate function mode
+11: Analog mode
+
+OTYPER
+0: Output push-pull (reset state)
+1: Output open-drain
+
+OSPEEDR
+00: 2 MHz Low speed
+01: 25 MHz Medium speed
+10: 50 MHz Fast speed
+11: 100 MHz High speed on 30 pF (80 MHz Output max speed on 15 pF)
+
+PUPDR
+00: No pull-up, pull-down
+01: Pull-up
+10: Pull-down
+
+AFRL 4 bit AF00-AF15
+AFRH 4 bit AF00-AF15
+*/
+
+/**
+ * @brief GPIO Pin modes.
+ *
+ * These only allow for 50MHZ max output speeds; if you want slower,
+ * use direct register access.
+ */
+typedef enum gpio_pin_mode {
+    GPIO_OUTPUT_PP = (GPIO_MODE_OUTPUT | GPIO_OTYPE_PP |
+                      GPIO_OSPEED_50MHZ), /**< Output push-pull. */
+    GPIO_OUTPUT_OD = (GPIO_MODE_OUTPUT | GPIO_OTYPE_OD |
+                      GPIO_OSPEED_50MHZ), /**< Output open-drain. */
+    GPIO_AF_OUTPUT_PP = (GPIO_MODE_AF | GPIO_OTYPE_PP |
+                         GPIO_OSPEED_50MHZ), /**< Alternate function
+                                                        output push-pull. */
+    GPIO_AF_OUTPUT_OD = (GPIO_MODE_AF | GPIO_OTYPE_OD |
+                         GPIO_OSPEED_50MHZ), /**< Alternate function
+                                                        output open drain. */
+    GPIO_INPUT_ANALOG = (GPIO_MODE_ANALOG), /**< Analog input. */
+    GPIO_INPUT_FLOATING = (GPIO_MODE_INPUT |
+                           GPIO_PUPD_INPUT_FLOATING), /**< Input floating. */
+    GPIO_INPUT_PD = (GPIO_MODE_INPUT |
+                     GPIO_PUPD_INPUT_PD), /**< Input pull-down. */
+    GPIO_INPUT_PU = (GPIO_MODE_INPUT |
+                     GPIO_PUPD_INPUT_PU), /**< Input pull-up. */
+    GPIO_AF_INPUT_PD = (GPIO_MODE_AF |
+                     GPIO_PUPD_INPUT_PD), /**< Input pull-down. */
+	GPIO_BIGNUMBER = 0xfff
+} gpio_pin_mode;
+
+/*
+ * GPIO Convenience routines
+ */
+
+void gpio_init(gpio_dev *dev);
+void gpio_init_all(void);
+void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode);
+void gpio_set_af_mode(gpio_dev *dev, uint8 pin, int mode);
+
+/**
+ * @brief Get a GPIO port's corresponding afio_exti_port.
+ * @param dev GPIO device whose afio_exti_port to return.
+ */
+static inline afio_exti_port gpio_exti_port(gpio_dev *dev) {
+    return dev->exti_port;
+}
+
+/**
+ * Set or reset a GPIO pin.
+ *
+ * Pin must have previously been configured to output mode.
+ *
+ * @param dev GPIO device whose pin to set.
+ * @param pin Pin on to set or reset
+ * @param val If true, set the pin.  If false, reset the pin.
+ */
+static inline void gpio_write_bit(gpio_dev *dev, uint8 pin, uint8 val) {
+    if (val) {
+        dev->regs->BSRRL = BIT(pin);
+    } else {
+        dev->regs->BSRRH = BIT(pin);
+    }
+}
+
+/**
+ * Determine whether or not a GPIO pin is set.
+ *
+ * Pin must have previously been configured to input mode.
+ *
+ * @param dev GPIO device whose pin to test.
+ * @param pin Pin on dev to test.
+ * @return True if the pin is set, false otherwise.
+ */
+static inline uint32 gpio_read_bit(gpio_dev *dev, uint8 pin) {
+    return dev->regs->IDR & BIT(pin);
+}
+
+/**
+ * Toggle a pin configured as output push-pull.
+ * @param dev GPIO device.
+ * @param pin Pin on dev to toggle.
+ */
+static inline void gpio_toggle_bit(gpio_dev *dev, uint8 pin) {
+    dev->regs->ODR = dev->regs->ODR ^ BIT(pin);
+}
+
+/*
+ * AFIO register map
+ */
+
+/** AFIO register map */
+typedef struct syscfg_reg_map {
+    __io uint32 MEMRM;    /**< memory remap register  */
+    __io uint32 PMC;      /**< peripheral mode configuration register */
+    __io uint32 EXTICR1;  /**< External interrupt configuration register 1. */
+    __io uint32 EXTICR2;  /**< External interrupt configuration register 2. */
+    __io uint32 EXTICR3;  /**< External interrupt configuration register 3. */
+    __io uint32 EXTICR4;  /**< External interrupt configuration register 4. */
+    __io uint32 CMPCR;    /**< Compensation cell control register */
+} syscfg_reg_map;
+
+/** AFIO register map base pointer. */
+#define SYSCFG_BASE                       ((struct syscfg_reg_map *)0x40013800)
+
+/*
+ * AFIO register bit definitions
+ */
+
+/* Event control register */
+
+#define AFIO_EVCR_EVOE                  (0x1 << 7)
+#define AFIO_EVCR_PORT_PA               (0x0 << 4)
+#define AFIO_EVCR_PORT_PB               (0x1 << 4)
+#define AFIO_EVCR_PORT_PC               (0x2 << 4)
+#define AFIO_EVCR_PORT_PD               (0x3 << 4)
+#define AFIO_EVCR_PORT_PE               (0x4 << 4)
+#define AFIO_EVCR_PIN_0                 0x0
+#define AFIO_EVCR_PIN_1                 0x1
+#define AFIO_EVCR_PIN_2                 0x2
+#define AFIO_EVCR_PIN_3                 0x3
+#define AFIO_EVCR_PIN_4                 0x4
+#define AFIO_EVCR_PIN_5                 0x5
+#define AFIO_EVCR_PIN_6                 0x6
+#define AFIO_EVCR_PIN_7                 0x7
+#define AFIO_EVCR_PIN_8                 0x8
+#define AFIO_EVCR_PIN_9                 0x9
+#define AFIO_EVCR_PIN_10                0xA
+#define AFIO_EVCR_PIN_11                0xB
+#define AFIO_EVCR_PIN_12                0xC
+#define AFIO_EVCR_PIN_13                0xD
+#define AFIO_EVCR_PIN_14                0xE
+#define AFIO_EVCR_PIN_15                0xF
+
+/* AF remap and debug I/O configuration register */
+
+#define AFIO_MAPR_SWJ_CFG                      (0x7 << 24)
+#define AFIO_MAPR_SWJ_CFG_FULL_SWJ             (0x0 << 24)
+#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST    (0x1 << 24)
+#define AFIO_MAPR_SWJ_CFG_NO_JTAG_SW           (0x2 << 24)
+#define AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW        (0x4 << 24)
+#define AFIO_MAPR_ADC2_ETRGREG_REMAP           BIT(20)
+#define AFIO_MAPR_ADC2_ETRGINJ_REMAP           BIT(19)
+#define AFIO_MAPR_ADC1_ETRGREG_REMAP           BIT(18)
+#define AFIO_MAPR_ADC1_ETRGINJ_REMAP           BIT(17)
+#define AFIO_MAPR_TIM5CH4_IREMAP               BIT(16)
+#define AFIO_MAPR_PD01_REMAP                   BIT(15)
+#define AFIO_MAPR_CAN_REMAP                    (0x3 << 13)
+#define AFIO_MAPR_CAN_REMAP_NONE               (0x0 << 13)
+#define AFIO_MAPR_CAN_REMAP_PB8_PB9            (0x2 << 13)
+#define AFIO_MAPR_CAN_REMAP_PD0_PD1            (0x3 << 13)
+#define AFIO_MAPR_TIM4_REMAP                   BIT(12)
+#define AFIO_MAPR_TIM3_REMAP                   (0x3 << 10)
+#define AFIO_MAPR_TIM3_REMAP_NONE              (0x0 << 10)
+#define AFIO_MAPR_TIM3_REMAP_PARTIAL           (0x2 << 10)
+#define AFIO_MAPR_TIM3_REMAP_FULL              (0x3 << 10)
+#define AFIO_MAPR_TIM2_REMAP                   (0x3 << 8)
+#define AFIO_MAPR_TIM2_REMAP_NONE              (0x0 << 8)
+#define AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3  (0x1 << 8)
+#define AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11 (0x2 << 8)
+#define AFIO_MAPR_TIM2_REMAP_FULL              (0x3 << 8)
+#define AFIO_MAPR_TIM1_REMAP                   (0x3 << 6)
+#define AFIO_MAPR_TIM1_REMAP_NONE              (0x0 << 6)
+#define AFIO_MAPR_TIM1_REMAP_PARTIAL           (0x1 << 6)
+#define AFIO_MAPR_TIM1_REMAP_FULL              (0x3 << 6)
+#define AFIO_MAPR_USART3_REMAP                 (0x3 << 4)
+#define AFIO_MAPR_USART3_REMAP_NONE            (0x0 << 4)
+#define AFIO_MAPR_USART3_REMAP_PARTIAL         (0x1 << 4)
+#define AFIO_MAPR_USART3_REMAP_FULL            (0x3 << 4)
+#define AFIO_MAPR_USART2_REMAP                 BIT(3)
+#define AFIO_MAPR_USART1_REMAP                 BIT(2)
+#define AFIO_MAPR_I2C1_REMAP                   BIT(1)
+#define AFIO_MAPR_SPI1_REMAP                   BIT(0)
+
+/* External interrupt configuration register 1 */
+
+#define AFIO_EXTICR1_EXTI3              (0xF << 12)
+#define AFIO_EXTICR1_EXTI3_PA           (0x0 << 12)
+#define AFIO_EXTICR1_EXTI3_PB           (0x1 << 12)
+#define AFIO_EXTICR1_EXTI3_PC           (0x2 << 12)
+#define AFIO_EXTICR1_EXTI3_PD           (0x3 << 12)
+#define AFIO_EXTICR1_EXTI3_PE           (0x4 << 12)
+#define AFIO_EXTICR1_EXTI3_PF           (0x5 << 12)
+#define AFIO_EXTICR1_EXTI3_PG           (0x6 << 12)
+#define AFIO_EXTICR1_EXTI2              (0xF << 8)
+#define AFIO_EXTICR1_EXTI2_PA           (0x0 << 8)
+#define AFIO_EXTICR1_EXTI2_PB           (0x1 << 8)
+#define AFIO_EXTICR1_EXTI2_PC           (0x2 << 8)
+#define AFIO_EXTICR1_EXTI2_PD           (0x3 << 8)
+#define AFIO_EXTICR1_EXTI2_PE           (0x4 << 8)
+#define AFIO_EXTICR1_EXTI2_PF           (0x5 << 8)
+#define AFIO_EXTICR1_EXTI2_PG           (0x6 << 8)
+#define AFIO_EXTICR1_EXTI1              (0xF << 4)
+#define AFIO_EXTICR1_EXTI1_PA           (0x0 << 4)
+#define AFIO_EXTICR1_EXTI1_PB           (0x1 << 4)
+#define AFIO_EXTICR1_EXTI1_PC           (0x2 << 4)
+#define AFIO_EXTICR1_EXTI1_PD           (0x3 << 4)
+#define AFIO_EXTICR1_EXTI1_PE           (0x4 << 4)
+#define AFIO_EXTICR1_EXTI1_PF           (0x5 << 4)
+#define AFIO_EXTICR1_EXTI1_PG           (0x6 << 4)
+#define AFIO_EXTICR1_EXTI0              0xF
+#define AFIO_EXTICR1_EXTI0_PA           0x0
+#define AFIO_EXTICR1_EXTI0_PB           0x1
+#define AFIO_EXTICR1_EXTI0_PC           0x2
+#define AFIO_EXTICR1_EXTI0_PD           0x3
+#define AFIO_EXTICR1_EXTI0_PE           0x4
+#define AFIO_EXTICR1_EXTI0_PF           0x5
+#define AFIO_EXTICR1_EXTI0_PG           0x6
+
+/* External interrupt configuration register 2 */
+
+#define AFIO_EXTICR2_EXTI7              (0xF << 12)
+#define AFIO_EXTICR2_EXTI7_PA           (0x0 << 12)
+#define AFIO_EXTICR2_EXTI7_PB           (0x1 << 12)
+#define AFIO_EXTICR2_EXTI7_PC           (0x2 << 12)
+#define AFIO_EXTICR2_EXTI7_PD           (0x3 << 12)
+#define AFIO_EXTICR2_EXTI7_PE           (0x4 << 12)
+#define AFIO_EXTICR2_EXTI7_PF           (0x5 << 12)
+#define AFIO_EXTICR2_EXTI7_PG           (0x6 << 12)
+#define AFIO_EXTICR2_EXTI6              (0xF << 8)
+#define AFIO_EXTICR2_EXTI6_PA           (0x0 << 8)
+#define AFIO_EXTICR2_EXTI6_PB           (0x1 << 8)
+#define AFIO_EXTICR2_EXTI6_PC           (0x2 << 8)
+#define AFIO_EXTICR2_EXTI6_PD           (0x3 << 8)
+#define AFIO_EXTICR2_EXTI6_PE           (0x4 << 8)
+#define AFIO_EXTICR2_EXTI6_PF           (0x5 << 8)
+#define AFIO_EXTICR2_EXTI6_PG           (0x6 << 8)
+#define AFIO_EXTICR2_EXTI5              (0xF << 4)
+#define AFIO_EXTICR2_EXTI5_PA           (0x0 << 4)
+#define AFIO_EXTICR2_EXTI5_PB           (0x1 << 4)
+#define AFIO_EXTICR2_EXTI5_PC           (0x2 << 4)
+#define AFIO_EXTICR2_EXTI5_PD           (0x3 << 4)
+#define AFIO_EXTICR2_EXTI5_PE           (0x4 << 4)
+#define AFIO_EXTICR2_EXTI5_PF           (0x5 << 4)
+#define AFIO_EXTICR2_EXTI5_PG           (0x6 << 4)
+#define AFIO_EXTICR2_EXTI4              0xF
+#define AFIO_EXTICR2_EXTI4_PA           0x0
+#define AFIO_EXTICR2_EXTI4_PB           0x1
+#define AFIO_EXTICR2_EXTI4_PC           0x2
+#define AFIO_EXTICR2_EXTI4_PD           0x3
+#define AFIO_EXTICR2_EXTI4_PE           0x4
+#define AFIO_EXTICR2_EXTI4_PF           0x5
+#define AFIO_EXTICR2_EXTI4_PG           0x6
+
+/* AF remap and debug I/O configuration register 2 */
+
+#define AFIO_MAPR2_FSMC_NADV            BIT(10)
+#define AFIO_MAPR2_TIM14_REMAP          BIT(9)
+#define AFIO_MAPR2_TIM13_REMAP          BIT(8)
+#define AFIO_MAPR2_TIM11_REMAP          BIT(7)
+#define AFIO_MAPR2_TIM10_REMAP          BIT(6)
+#define AFIO_MAPR2_TIM9_REMAP           BIT(5)
+
+/*
+ * AFIO convenience routines
+ */
+
+void afio_init(void);
+
+/**
+ * External interrupt line numbers.
+ */
+typedef enum afio_exti_num {
+    AFIO_EXTI_0,                /**< External interrupt line 0. */
+    AFIO_EXTI_1,                /**< External interrupt line 1. */
+    AFIO_EXTI_2,                /**< External interrupt line 2. */
+    AFIO_EXTI_3,                /**< External interrupt line 3. */
+    AFIO_EXTI_4,                /**< External interrupt line 4. */
+    AFIO_EXTI_5,                /**< External interrupt line 5. */
+    AFIO_EXTI_6,                /**< External interrupt line 6. */
+    AFIO_EXTI_7,                /**< External interrupt line 7. */
+    AFIO_EXTI_8,                /**< External interrupt line 8. */
+    AFIO_EXTI_9,                /**< External interrupt line 9. */
+    AFIO_EXTI_10,               /**< External interrupt line 10. */
+    AFIO_EXTI_11,               /**< External interrupt line 11. */
+    AFIO_EXTI_12,               /**< External interrupt line 12. */
+    AFIO_EXTI_13,               /**< External interrupt line 13. */
+    AFIO_EXTI_14,               /**< External interrupt line 14. */
+    AFIO_EXTI_15,               /**< External interrupt line 15. */
+} afio_exti_num;
+
+void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port);
+
+/* HACK: Use upper bit to denote MAPR2, Bit 31 is reserved and
+ * not used in either MAPR or MAPR2 */
+#define AFIO_REMAP_USE_MAPR2            (1 << 31)
+
+/**
+ * @brief Available peripheral remaps.
+ * @see afio_remap()
+ */
+typedef enum afio_remap_peripheral {
+    AFIO_REMAP_ADC2_ETRGREG  = AFIO_MAPR_ADC2_ETRGREG_REMAP, /**<
+        ADC 2 external trigger regular conversion remapping */
+    AFIO_REMAP_ADC2_ETRGINJ  = AFIO_MAPR_ADC2_ETRGINJ_REMAP, /**<
+        ADC 2 external trigger injected conversion remapping */
+    AFIO_REMAP_ADC1_ETRGREG  = AFIO_MAPR_ADC1_ETRGREG_REMAP, /**<
+        ADC 1 external trigger regular conversion remapping */
+    AFIO_REMAP_ADC1_ETRGINJ  = AFIO_MAPR_ADC1_ETRGINJ_REMAP, /**<
+        ADC 1 external trigger injected conversion remapping */
+    AFIO_REMAP_TIM5CH4_I     = AFIO_MAPR_TIM5CH4_IREMAP, /**<
+        Timer 5 channel 4 internal remapping */
+    AFIO_REMAP_PD01          = AFIO_MAPR_PD01_REMAP, /**<
+        Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
+    AFIO_REMAP_CAN_1         = AFIO_MAPR_CAN_REMAP_PB8_PB9, /**<
+        CAN alternate function remapping 1 (RX on PB8, TX on PB9) */
+    AFIO_REMAP_CAN_2         = AFIO_MAPR_CAN_REMAP_PD0_PD1, /**<
+        CAN alternate function remapping 2 (RX on PD0, TX on PD1) */
+    AFIO_REMAP_TIM4          = AFIO_MAPR_TIM4_REMAP, /**<
+        Timer 4 remapping */
+    AFIO_REMAP_TIM3_PARTIAL  = AFIO_MAPR_TIM3_REMAP_PARTIAL, /**<
+        Timer 3 partial remapping */
+    AFIO_REMAP_TIM3_FULL      = AFIO_MAPR_TIM3_REMAP_FULL, /**<
+        Timer 3 full remapping */
+    AFIO_REMAP_TIM2_PARTIAL_1 = AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3, /**<
+        Timer 2 partial remapping 1 (CH1 and ETR on PA15, CH2 on PB3, CH3
+        on PA2, CH4 on PA3) */
+    AFIO_REMAP_TIM2_PARTIAL_2 = AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11, /**<
+        Timer 2 partial remapping 2 (CH1 and ETR on PA0, CH2 on PA1, CH3
+        on PB10, CH4 on PB11) */
+    AFIO_REMAP_TIM2_FULL      = AFIO_MAPR_TIM2_REMAP_FULL, /**<
+        Timer 2 full remapping */
+    AFIO_REMAP_USART2        = AFIO_MAPR_USART2_REMAP, /**<
+        USART 2 remapping */
+    AFIO_REMAP_USART1        = AFIO_MAPR_USART1_REMAP, /**<
+        USART 1 remapping */
+    AFIO_REMAP_I2C1          = AFIO_MAPR_I2C1_REMAP, /**<
+        I2C 1 remapping */
+    AFIO_REMAP_SPI1          = AFIO_MAPR_SPI1_REMAP, /**<
+        SPI 1 remapping */
+    AFIO_REMAP_FSMC_NADV     = (AFIO_MAPR2_FSMC_NADV |
+                                AFIO_REMAP_USE_MAPR2), /**<
+        NADV signal not connected */
+    AFIO_REMAP_TIM14         = (AFIO_MAPR2_TIM14_REMAP |
+                                AFIO_REMAP_USE_MAPR2), /**<
+        Timer 14 remapping */
+    AFIO_REMAP_TIM13         = (AFIO_MAPR2_TIM13_REMAP |
+                                AFIO_REMAP_USE_MAPR2), /**<
+        Timer 13 remapping */
+    AFIO_REMAP_TIM11         = (AFIO_MAPR2_TIM11_REMAP |
+                                AFIO_REMAP_USE_MAPR2), /**<
+        Timer 11 remapping */
+    AFIO_REMAP_TIM10         = (AFIO_MAPR2_TIM10_REMAP |
+                                AFIO_REMAP_USE_MAPR2), /**<
+        Timer 10 remapping */
+    AFIO_REMAP_TIM9          = (AFIO_MAPR2_TIM9_REMAP |
+                                AFIO_REMAP_USE_MAPR2) /**<
+        Timer 9 */
+} afio_remap_peripheral;
+
+void afio_remap(afio_remap_peripheral p);
+
+/**
+ * @brief Debug port configuration
+ *
+ * Used to configure the behavior of JTAG and Serial Wire (SW) debug
+ * ports and their associated GPIO pins.
+ *
+ * @see afio_cfg_debug_ports()
+ */
+typedef enum afio_debug_cfg {
+    AFIO_DEBUG_FULL_SWJ = AFIO_MAPR_SWJ_CFG_FULL_SWJ, /**<
+                                   Full Serial Wire and JTAG debug */
+    AFIO_DEBUG_FULL_SWJ_NO_NJRST = AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST, /**<
+                                   Full Serial Wire and JTAG, but no NJTRST. */
+    AFIO_DEBUG_SW_ONLY = AFIO_MAPR_SWJ_CFG_NO_JTAG_SW, /**<
+                                   Serial Wire debug only (JTAG-DP disabled,
+                                   SW-DP enabled) */
+    AFIO_DEBUG_NONE = AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW /**<
+                                   No debug; all JTAG and SW pins are free
+                                   for use as GPIOs. */
+} afio_debug_cfg;
+
+/**
+ * @brief Enable or disable the JTAG and SW debug ports.
+ * @param config Desired debug port configuration
+ * @see afio_debug_cfg
+ */
+static inline void afio_cfg_debug_ports(afio_debug_cfg config) {
+    //__io uint32 *mapr = &AFIO_BASE->MAPR;
+    //*mapr = (*mapr & ~AFIO_MAPR_SWJ_CFG) | config;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/STM32F4/cores/maple/libmaple/rccF4.c b/STM32F4/cores/maple/libmaple/rccF4.c
new file mode 100644
index 000000000..dd2ea2648
--- /dev/null
+++ b/STM32F4/cores/maple/libmaple/rccF4.c
@@ -0,0 +1,707 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Perry Hung.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+#ifdef STM32F4
+ 
+/**
+ * @file rcc.c
+ * @brief Implements pretty much only the basic clock setup on the
+ *        stm32, clock enable/disable and peripheral reset commands.
+ */
+
+#include "libmaple.h"
+#include "flash.h"
+#include "gpio.h"
+#include "rcc.h"
+#include "bitband.h"
+
+#define APB1                            RCC_APB1
+#define APB2                            RCC_APB2
+#define AHB1                            RCC_AHB1
+#define AHB2                            RCC_AHB2
+#define AHB3                            RCC_AHB3
+
+struct rcc_dev_info {
+    const rcc_clk_domain clk_domain;
+    const uint8 line_num;
+};
+
+static uint32 rcc_dev_clk_speed_table[AHB3];
+
+/* Device descriptor table, maps rcc_clk_id onto bus and enable/reset
+ * register bit numbers. */
+static const struct rcc_dev_info rcc_dev_table[] = {
+    [RCC_GPIOA]   = { .clk_domain = AHB1, .line_num =  0 }, //*
+    [RCC_GPIOB]   = { .clk_domain = AHB1, .line_num =  1 }, //*
+    [RCC_GPIOC]   = { .clk_domain = AHB1, .line_num =  2 }, //*
+    [RCC_GPIOD]   = { .clk_domain = AHB1, .line_num =  3 }, //*
+
+//    [RCC_AFIO]    = { .clk_domain = APB2, .line_num =  0 },
+    [RCC_ADC1]    = { .clk_domain = APB2, .line_num =  8 }, //*
+    [RCC_ADC2]    = { .clk_domain = APB2, .line_num =  9 }, //*
+    [RCC_ADC3]    = { .clk_domain = APB2, .line_num = 10 }, //*
+    [RCC_USART1]  = { .clk_domain = APB2, .line_num =  4 }, //*
+    [RCC_USART2]  = { .clk_domain = APB1, .line_num = 17 }, //unchanged
+    [RCC_USART3]  = { .clk_domain = APB1, .line_num = 18 }, //unchanged
+    [RCC_TIMER1]  = { .clk_domain = APB2, .line_num =  0 }, //*
+    [RCC_TIMER2]  = { .clk_domain = APB1, .line_num =  0 }, //unchanged
+    [RCC_TIMER3]  = { .clk_domain = APB1, .line_num =  1 }, //unchanged
+    [RCC_TIMER4]  = { .clk_domain = APB1, .line_num =  2 }, //unchanged
+    [RCC_SPI1]    = { .clk_domain = APB2, .line_num = 12 }, //unchanged
+    [RCC_SPI2]    = { .clk_domain = APB1, .line_num = 14 }, //unchanged
+    [RCC_DMA1]    = { .clk_domain = AHB1, .line_num = 21 }, //*
+    [RCC_PWR]     = { .clk_domain = APB1, .line_num = 28},  //unchanged
+    [RCC_BKP]     = { .clk_domain = AHB1, .line_num = 18},  //*
+    [RCC_I2C1]    = { .clk_domain = APB1, .line_num = 21 }, //unchanged
+    [RCC_I2C2]    = { .clk_domain = APB1, .line_num = 22 }, //unchanged
+    [RCC_CRC]     = { .clk_domain = AHB1, .line_num = 12},  //*
+//    [RCC_FLITF]   = { .clk_domain = AHB,  .line_num =  4},
+//    [RCC_SRAM]    = { .clk_domain = AHB,  .line_num =  2},
+
+    [RCC_GPIOE]   = { .clk_domain = AHB1, .line_num =  4 }, //*
+    [RCC_GPIOF]   = { .clk_domain = AHB1, .line_num =  5 }, //*
+    [RCC_GPIOG]   = { .clk_domain = AHB1, .line_num =  6 }, //*
+    [RCC_UART4]   = { .clk_domain = APB1, .line_num = 19 }, //unchanged
+    [RCC_UART5]   = { .clk_domain = APB1, .line_num = 20 }, //unchanged
+    [RCC_TIMER5]  = { .clk_domain = APB1, .line_num =  3 }, //unchanged
+    [RCC_TIMER6]  = { .clk_domain = APB1, .line_num =  4 }, //unchanged
+    [RCC_TIMER7]  = { .clk_domain = APB1, .line_num =  5 }, //unchanged
+    [RCC_TIMER8]  = { .clk_domain = APB2, .line_num =  1 }, //*
+    [RCC_FSMC]    = { .clk_domain = AHB3, .line_num =  0 }, //*
+    [RCC_DAC]     = { .clk_domain = APB1, .line_num = 29 }, //unchanged
+    [RCC_DMA2]    = { .clk_domain = AHB1, .line_num = 22 }, //*
+    [RCC_SDIO]    = { .clk_domain = APB2, .line_num = 11 }, //*
+    [RCC_SPI3]    = { .clk_domain = APB1, .line_num = 15 }, //unchanged
+    [RCC_TIMER9]  = { .clk_domain = APB2, .line_num = 16 }, //*
+    [RCC_TIMER10] = { .clk_domain = APB2, .line_num = 17 }, //*
+    [RCC_TIMER11] = { .clk_domain = APB2, .line_num = 18 }, //*
+    [RCC_TIMER12] = { .clk_domain = APB1, .line_num =  6 }, //unchanged
+    [RCC_TIMER13] = { .clk_domain = APB1, .line_num =  7 }, //unchanged
+    [RCC_TIMER14] = { .clk_domain = APB1, .line_num =  8 }, //unchanged
+    [RCC_USBFS]   = { .clk_domain = AHB2, .line_num =  7 }, //*
+    [RCC_SYSCFG]  = { .clk_domain = APB2, .line_num =  14 }, //*
+    [RCC_SPI4]    = { .clk_domain = APB1, .line_num = 15 },
+};
+
+/**
+ * @brief Initialize the clock control system. Initializes the system
+ *        clock source to use the PLL driven by an external oscillator
+ * @param sysclk_src system clock source, must be PLL
+ * @param pll_src pll clock source, must be HSE
+ * @param pll_mul pll multiplier
+ */
+
+#define HSE_STARTUP_TIMEOUT  ((uint16)0x0500)   /*!< Time out for HSE start up */
+#define  RCC_CFGR_HPRE_DIV1                  ((uint32)0x00000000)        /*!< SYSCLK not divided */
+#define  RCC_CFGR_PPRE1_DIV2                 ((uint32)0x00001000)        /*!< HCLK divided by 2 */
+#define  RCC_CFGR_PPRE1_DIV4                 ((uint32)0x00001400)        /*!< HCLK divided by 4 */
+#define  RCC_CFGR_PPRE2_DIV1                 ((uint32)0x00000000)        /*!< HCLK not divided */
+#define  RCC_CFGR_PPRE2_DIV2                 ((uint32)0x00008000)        /*!< HCLK divided by 2 */
+
+#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32)0x00400000)
+
+/*******************  Bits definition for FLASH_ACR register  *****************/
+//#define FLASH_ACR_LATENCY                    ((uint32_t)0x00000007)
+#define FLASH_ACR_LATENCY_0WS                ((uint32)0x00000000)
+#define FLASH_ACR_LATENCY_1WS                ((uint32)0x00000001)
+#define FLASH_ACR_LATENCY_2WS                ((uint32)0x00000002)
+#define FLASH_ACR_LATENCY_3WS                ((uint32)0x00000003)
+#define FLASH_ACR_LATENCY_4WS                ((uint32)0x00000004)
+#define FLASH_ACR_LATENCY_5WS                ((uint32)0x00000005)
+#define FLASH_ACR_LATENCY_6WS                ((uint32)0x00000006)
+#define FLASH_ACR_LATENCY_7WS                ((uint32)0x00000007)
+
+#define FLASH_ACR_PRFTEN                     ((uint32)0x00000100)
+#define FLASH_ACR_ICEN                       ((uint32)0x00000200)
+#define FLASH_ACR_DCEN                       ((uint32)0x00000400)
+#define FLASH_ACR_ICRST                      ((uint32)0x00000800)
+#define FLASH_ACR_DCRST                      ((uint32)0x00001000)
+#define FLASH_ACR_BYTE0_ADDRESS              ((uint32)0x40023C00)
+#define FLASH_ACR_BYTE2_ADDRESS              ((uint32)0x40023C03)
+
+typedef struct
+{
+  __io uint32 CR;   /*!< PWR power control register,        Address offset: 0x00 */
+  __io uint32 CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+#define PWR_BASE                             (0x40007000)
+#define PWR                                  ((PWR_TypeDef *) PWR_BASE)
+#define PWR_CR_VOS                           ((uint16)0x4000)     /*!< Regulator voltage scaling output selection */
+
+typedef struct
+{
+  __io uint32 ACR;      /*!< FLASH access control register, Address offset: 0x00 */
+  __io uint32 KEYR;     /*!< FLASH key register,            Address offset: 0x04 */
+  __io uint32 OPTKEYR;  /*!< FLASH option key register,     Address offset: 0x08 */
+  __io uint32 SR;       /*!< FLASH status register,         Address offset: 0x0C */
+  __io uint32 CR;       /*!< FLASH control register,        Address offset: 0x10 */
+  __io uint32 OPTCR;    /*!< FLASH option control register, Address offset: 0x14 */
+} FLASH_TypeDef;
+
+#define FLASH_R_BASE          (0x40023C00)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define RESET 0
+
+typedef uint32 uint32_t;
+
+void InitMCO1()
+{
+    rcc_reg_map *RCC = RCC_BASE;
+    // Turn MCO1 Master Clock Output mode
+    RCC->CFGR &= RCC_CFGR_MCO1_RESET_MASK;
+    RCC->CFGR |= RCC_CFGR_MCO1Source_HSE | RCC_CFGR_MCO1Div_1;
+    // PA8 Output the Master Clock MCO1
+    gpio_set_af_mode(GPIOA, 8, 0);
+    gpio_set_mode(GPIOA, 8, GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
+}
+
+
+void SetupClock72MHz()
+{
+	uint32_t SystemCoreClock = 72000000;
+
+	/******************************************************************************/
+	/*            PLL (clocked by HSE) used as System clock source                */
+	/******************************************************************************/
+	/************************* PLL Parameters *************************************/
+	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
+	int PLL_M = 4;
+	int PLL_N = 216;
+
+	/* SYSCLK = PLL_VCO / PLL_P */
+	int PLL_P = 6;
+
+	/* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
+	int PLL_Q = 9;
+
+
+	uint32 StartUpCounter = 0, HSEStatus = 0;
+	rcc_reg_map *RCC = RCC_BASE;
+
+	/* Enable HSE */
+	RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+	/* Wait till HSE is ready and if Time out is reached exit */
+	do
+	{
+		HSEStatus = RCC->CR & RCC_CR_HSERDY;
+		StartUpCounter++;
+	} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+	if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+	{
+		HSEStatus = (uint32_t)0x01;
+	}
+	else
+	{
+		HSEStatus = (uint32_t)0x00;
+	}
+
+	if (HSEStatus == (uint32_t)0x01)
+	{
+		/* Select regulator voltage output Scale 2 mode, System frequency up to 144 MHz */
+		RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+		PWR->CR &= (uint32_t)~(PWR_CR_VOS);
+
+		/* HCLK = SYSCLK / 1*/
+		RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
+
+		/* PCLK2 = HCLK / 1*/
+		RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
+
+		/* PCLK1 = HCLK / 2*/
+		RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
+
+		// save bus clock values
+		rcc_dev_clk_speed_table[RCC_AHB1] = (SystemCoreClock/1);
+		rcc_dev_clk_speed_table[RCC_APB2] = (SystemCoreClock/1);
+		rcc_dev_clk_speed_table[RCC_APB1] = (SystemCoreClock/2);
+
+		/* Configure the main PLL */
+		RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
+			(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
+
+		/* Enable the main PLL */
+		RCC->CR |= RCC_CR_PLLON;
+
+		/* Wait till the main PLL is ready */
+		while((RCC->CR & RCC_CR_PLLRDY) == 0)
+		{
+		}
+
+		/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
+		FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
+
+		/* Select the main PLL as system clock source */
+		RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+		RCC->CFGR |= RCC_CFGR_SW_PLL;
+
+		/* Wait till the main PLL is used as system clock source */
+		while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+		{
+		}
+	}
+	else
+	{ /* If HSE fails to start-up, the application will have wrong clock
+	  configuration. User can add here some code to deal with this error */
+	}
+}
+
+
+void SetupClock120MHz()
+{
+	uint32_t SystemCoreClock = 120000000;
+
+	/******************************************************************************/
+	/*            PLL (clocked by HSE) used as System clock source                */
+	/******************************************************************************/
+	/************************* PLL Parameters *************************************/
+	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
+	int PLL_M = 8;
+	int PLL_N = 240;
+
+	/* SYSCLK = PLL_VCO / PLL_P */
+	int PLL_P = 2;
+
+	/* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
+	int PLL_Q = 5;
+
+
+	uint32 StartUpCounter = 0, HSEStatus = 0;
+	rcc_reg_map *RCC = RCC_BASE;
+
+	/* Enable HSE */
+	RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+	/* Wait till HSE is ready and if Time out is reached exit */
+	do
+	{
+		HSEStatus = RCC->CR & RCC_CR_HSERDY;
+		StartUpCounter++;
+	} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+	if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+	{
+		HSEStatus = (uint32_t)0x01;
+	}
+	else
+	{
+		HSEStatus = (uint32_t)0x00;
+	}
+
+	if (HSEStatus == (uint32_t)0x01)
+	{
+		/* Select regulator voltage output Scale 2 mode, System frequency up to 144 MHz */
+		RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+		PWR->CR &= (uint32_t)~(PWR_CR_VOS);
+
+		/* HCLK = SYSCLK / 1*/
+		RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
+
+		/* PCLK2 = HCLK / 2*/
+		RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
+
+		/* PCLK1 = HCLK / 4*/
+		RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
+
+		// save bus clock values
+		rcc_dev_clk_speed_table[RCC_AHB1] = (SystemCoreClock/1);
+		rcc_dev_clk_speed_table[RCC_APB2] = (SystemCoreClock/2);
+		rcc_dev_clk_speed_table[RCC_APB1] = (SystemCoreClock/4);
+
+		/* Configure the main PLL */
+		RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
+			(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
+
+		/* Enable the main PLL */
+		RCC->CR |= RCC_CR_PLLON;
+
+		/* Wait till the main PLL is ready */
+		while((RCC->CR & RCC_CR_PLLRDY) == 0)
+		{
+		}
+
+		/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
+		FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_3WS;
+
+		/* Select the main PLL as system clock source */
+		RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+		RCC->CFGR |= RCC_CFGR_SW_PLL;
+
+		/* Wait till the main PLL is used as system clock source */
+		while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+		{
+		}
+	}
+	else
+	{ /* If HSE fails to start-up, the application will have wrong clock
+	  configuration. User can add here some code to deal with this error */
+	}
+}
+
+
+void SetupClock168MHz()
+{
+	uint32_t SystemCoreClock = 168000000;
+
+	/******************************************************************************/
+	/*            PLL (clocked by HSE) used as System clock source                */
+	/******************************************************************************/
+	/************************* PLL Parameters *************************************/
+	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
+#ifdef ARDUINO_STM32F4_NETDUINO2PLUS
+	int PLL_M = 25; // The NETDUINO has a 25MHz external oscillator
+#else
+	int PLL_M = 8;
+#endif
+	int PLL_N = 336;
+
+	/* SYSCLK = PLL_VCO / PLL_P */
+	int PLL_P = 2;
+
+	/* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
+	int PLL_Q = 7;
+
+
+	uint32 StartUpCounter = 0, HSEStatus = 0;
+	rcc_reg_map *RCC = RCC_BASE;
+
+#ifdef ARDUINO_STM32F4_NETDUINO2PLUS
+        InitMCO1();
+#endif
+        
+	/* Enable HSE */
+	RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+
+	/* Wait till HSE is ready and if Time out is reached exit */
+	do
+	{
+		HSEStatus = RCC->CR & RCC_CR_HSERDY;
+		StartUpCounter++;
+	} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+	if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+	{
+		HSEStatus = (uint32_t)0x01;
+	}
+	else
+	{
+		HSEStatus = (uint32_t)0x00;
+	}
+
+	if (HSEStatus == (uint32_t)0x01)
+	{
+		/* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
+		RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+		PWR->CR |= PWR_CR_VOS;
+
+		/* HCLK = SYSCLK / 1*/
+		RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
+
+		/* PCLK2 = HCLK / 2*/
+		RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
+
+		/* PCLK1 = HCLK / 4*/
+		RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
+
+		// save bus clock values
+		rcc_dev_clk_speed_table[RCC_AHB1] = (SystemCoreClock/1);
+		rcc_dev_clk_speed_table[RCC_APB2] = (SystemCoreClock/2);
+		rcc_dev_clk_speed_table[RCC_APB1] = (SystemCoreClock/4);
+
+		/* Configure the main PLL */
+		RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
+			(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
+
+		/* Enable the main PLL */
+		RCC->CR |= RCC_CR_PLLON;
+
+		/* Wait till the main PLL is ready */
+		while((RCC->CR & RCC_CR_PLLRDY) == 0)
+		{
+		}
+
+		/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
+		FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
+
+		/* Select the main PLL as system clock source */
+		RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+		RCC->CFGR |= RCC_CFGR_SW_PLL;
+
+		/* Wait till the main PLL is used as system clock source */
+		while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+		{
+		}
+	}
+	else
+	{ /* If HSE fails to start-up, the application will have wrong clock
+	  configuration. User can add here some code to deal with this error */
+	}
+}
+
+
+void rcc_clk_init(rcc_sysclk_src sysclk_src,
+                  rcc_pllsrc pll_src,
+                  rcc_pll_multiplier pll_mul) {
+
+  //SetupClock72MHz();
+#if STM32_TICKS_PER_US == 168
+	  SetupClock168MHz();
+#endif
+#if STM32_TICKS_PER_US == 120
+	  SetupClock120MHz();
+#endif
+#if STM32_TICKS_PER_US == 72
+	  SetupClock72MHz();
+#endif
+}
+
+
+
+
+#define PLL_M      8
+#define PLL_N      240
+/* SYSCLK = PLL_VCO / PLL_P */
+#define PLL_P      2
+
+/* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
+#define PLL_Q      5
+
+
+void rcc_clk_init2(rcc_sysclk_src sysclk_src,
+                  rcc_pllsrc pll_src,
+                  rcc_pll_multiplier pll_mul) {
+
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+  uint32 StartUpCounter = 0, HSEStatus = 0;
+  rcc_reg_map *pRCC = RCC_BASE;
+
+  /* Enable HSE */
+  pRCC->CR |= RCC_CR_HSEON;
+
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = pRCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((pRCC->CR & RCC_CR_HSERDY) != 0)
+  {
+    HSEStatus = 0x01;
+  }
+  else
+  {
+    HSEStatus = 0x00;
+  }
+
+  if (HSEStatus == 0x01)
+  {
+    /* HCLK = SYSCLK / 1*/
+    pRCC->CFGR |= RCC_CFGR_HPRE_DIV1;
+
+    /* PCLK2 = HCLK / 2*/
+    pRCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
+
+    /* PCLK1 = HCLK / 4*/
+    pRCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
+
+    /* Configure the main PLL */
+    pRCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
+                   (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
+
+    /* Enable the main PLL */
+    pRCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till the main PLL is ready */
+    while((pRCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+
+    /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
+    ((FLASH_TypeDef*)FLASH)->ACR = FLASH_ACR_PRFTEN |FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_3WS;
+
+    /* Select the main PLL as system clock source */
+    pRCC->CFGR &= ~RCC_CFGR_SW;
+    pRCC->CFGR |= RCC_CFGR_SW_PLL;
+
+    /* Wait till the main PLL is used as system clock source */
+    while ((pRCC->CFGR & RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+
+#if 0
+    uint32 cfgr = 0;
+    uint32 cr;
+
+    /* Assume that we're going to clock the chip off the PLL, fed by
+     * the HSE */
+    ASSERT(sysclk_src == RCC_CLKSRC_PLL &&
+           pll_src    == RCC_PLLSRC_HSE);
+
+    RCC_BASE->CFGR = pll_src | pll_mul;
+
+    /* Turn on the HSE */
+    cr = RCC_BASE->CR;
+    cr |= RCC_CR_HSEON;
+    RCC_BASE->CR = cr;
+    while (!(RCC_BASE->CR & RCC_CR_HSERDY))
+        ;
+
+    /* Now the PLL */
+    cr |= RCC_CR_PLLON;
+    RCC_BASE->CR = cr;
+    while (!(RCC_BASE->CR & RCC_CR_PLLRDY))
+        ;
+
+    /* Finally, let's switch over to the PLL */
+    cfgr &= ~RCC_CFGR_SW;
+    cfgr |= RCC_CFGR_SW_PLL;
+    RCC_BASE->CFGR = cfgr;
+    while ((RCC_BASE->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL)
+        ;
+#endif
+}
+
+/**
+ * @brief Turn on the clock line on a peripheral
+ * @param id Clock ID of the peripheral to turn on.
+ */
+void rcc_clk_enable(rcc_clk_id id) {
+    static const __io uint32* enable_regs[] = {
+        [APB1] = &RCC_BASE->APB1ENR,
+        [APB2] = &RCC_BASE->APB2ENR,
+        [AHB1] = &RCC_BASE->AHB1ENR,
+        [AHB2] = &RCC_BASE->AHB2ENR,
+        [AHB3] = &RCC_BASE->AHB3ENR,
+    };
+
+    rcc_clk_domain clk_domain = rcc_dev_clk(id);
+    __io uint32* enr = (__io uint32*)enable_regs[clk_domain];
+    uint8 lnum = rcc_dev_table[id].line_num;
+
+    bb_peri_set_bit(enr, lnum, 1);
+}
+
+/**
+ * @brief Turn on the clock line on a peripheral
+ * @param id Clock ID of the peripheral to turn on.
+ */
+void rcc_clk_disable(rcc_clk_id id) {
+    static const __io uint32* enable_regs[] = {
+        [APB1] = &RCC_BASE->APB1ENR,
+        [APB2] = &RCC_BASE->APB2ENR,
+        [AHB1] = &RCC_BASE->AHB1ENR,
+        [AHB2] = &RCC_BASE->AHB2ENR,
+        [AHB3] = &RCC_BASE->AHB3ENR,
+    };
+
+    rcc_clk_domain clk_domain = rcc_dev_clk(id);
+    __io uint32* enr = (__io uint32*)enable_regs[clk_domain];
+    uint8 lnum = rcc_dev_table[id].line_num;
+
+    bb_peri_set_bit(enr, lnum, 0);
+}
+
+/**
+ * @brief Reset a peripheral.
+ * @param id Clock ID of the peripheral to reset.
+ */
+void rcc_reset_dev(rcc_clk_id id) {
+    static const __io uint32* reset_regs[] = {
+        [APB1] = &RCC_BASE->APB1RSTR,
+        [APB2] = &RCC_BASE->APB2RSTR,
+        [AHB1] = &RCC_BASE->AHB1RSTR,
+        [AHB2] = &RCC_BASE->AHB2RSTR,
+        [AHB3] = &RCC_BASE->AHB3RSTR,
+    };
+
+    rcc_clk_domain clk_domain = rcc_dev_clk(id);
+    __io void* addr = (__io void*)reset_regs[clk_domain];
+    uint8 lnum = rcc_dev_table[id].line_num;
+
+    bb_peri_set_bit(addr, lnum, 1);
+    bb_peri_set_bit(addr, lnum, 0);
+}
+
+/**
+ * @brief Get a peripheral's clock domain
+ * @param id Clock ID of the peripheral whose clock domain to return
+ * @return Clock source for the given clock ID
+ */
+rcc_clk_domain rcc_dev_clk(rcc_clk_id id) {
+    return rcc_dev_table[id].clk_domain;
+}
+
+/**
+ * @brief Get a peripheral's clock domain speed
+ * @param id Clock ID of the peripheral whose clock domain speed to return
+ * @return Clock speed for the given clock ID
+ */
+uint32 rcc_dev_clk_speed(rcc_clk_id id) {
+    return rcc_dev_clk_speed_table[rcc_dev_clk(id)];
+}
+
+/**
+ * @brief Get a peripheral's timer clock domain speed
+ * @param id Clock ID of the peripheral whose clock domain speed to return
+ * @return Clock speed for the given clock ID
+ */
+uint32 rcc_dev_timer_clk_speed(rcc_clk_id id) {
+    return 2*rcc_dev_clk_speed(id);
+}
+
+/**
+ * @brief Set the divider on a peripheral prescaler
+ * @param prescaler prescaler to set
+ * @param divider prescaler divider
+ */
+void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider) {
+#if 0
+    static const uint32 masks[] = {
+        [RCC_PRESCALER_AHB] = RCC_CFGR_HPRE,
+        [RCC_PRESCALER_APB1] = RCC_CFGR_PPRE1,
+        [RCC_PRESCALER_APB2] = RCC_CFGR_PPRE2,
+        [RCC_PRESCALER_USB] = RCC_CFGR_USBPRE,
+        [RCC_PRESCALER_ADC] = RCC_CFGR_ADCPRE,
+    };
+
+    uint32 cfgr = RCC_BASE->CFGR;
+    cfgr &= ~masks[prescaler];
+    cfgr |= divider;
+    RCC_BASE->CFGR = cfgr;
+#endif
+}
+
+#endif
diff --git a/STM32F4/cores/maple/libmaple/rccF4.h b/STM32F4/cores/maple/libmaple/rccF4.h
new file mode 100644
index 000000000..99c5ff25d
--- /dev/null
+++ b/STM32F4/cores/maple/libmaple/rccF4.h
@@ -0,0 +1,642 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Perry Hung.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file rcc.h
+ * @brief reset and clock control definitions and prototypes
+ */
+
+#include "libmaple_types.h"
+#include "bitband.h"
+
+#ifndef _RCC_H_
+#define _RCC_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+/** RCC register map type */
+typedef struct
+{
+  __io uint32 CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
+  __io uint32 PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
+  __io uint32 CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
+  __io uint32 CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
+  __io uint32 AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
+  __io uint32 AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
+  __io uint32 AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
+  uint32      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
+  __io uint32 APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
+  __io uint32 APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
+  uint32      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
+  __io uint32 AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
+  __io uint32 AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
+  __io uint32 AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
+  uint32      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
+  __io uint32 APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
+  __io uint32 APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
+  uint32      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
+  __io uint32 AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+  __io uint32 AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+  __io uint32 AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+  uint32      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
+  __io uint32 APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+  __io uint32 APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+  uint32      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
+  __io uint32 BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
+  __io uint32 CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
+  uint32      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
+  __io uint32 SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
+  __io uint32 PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
+} rcc_reg_map;
+
+/** RCC register map base pointer */
+//#define RCC_BASE                        ((struct rcc_reg_map*)0x40021000)
+#define RCC_BASE              ((rcc_reg_map*)0x40023800)
+
+/*
+ * Register bit definitions
+ */
+
+/* Clock control register */
+
+#define RCC_CR_PLLRDY_BIT               25
+#define RCC_CR_PLLON_BIT                24
+#define RCC_CR_CSSON_BIT                19
+#define RCC_CR_HSEBYP_BIT               18
+#define RCC_CR_HSERDY_BIT               17
+#define RCC_CR_HSEON_BIT                16
+#define RCC_CR_HSIRDY_BIT               1
+#define RCC_CR_HSION_BIT                0
+
+#define RCC_CR_PLLRDY                   BIT(RCC_CR_PLLRDY_BIT)
+#define RCC_CR_PLLON                    BIT(RCC_CR_PLLON_BIT)
+#define RCC_CR_CSSON                    BIT(RCC_CR_CSSON_BIT)
+#define RCC_CR_HSEBYP                   BIT(RCC_CR_HSEBYP_BIT)
+#define RCC_CR_HSERDY                   BIT(RCC_CR_HSERDY_BIT)
+#define RCC_CR_HSEON                    BIT(RCC_CR_HSEON_BIT)
+#define RCC_CR_HSICAL                   (0xFF << 8)
+#define RCC_CR_HSITRIM                  (0x1F << 3)
+#define RCC_CR_HSIRDY                   BIT(RCC_CR_HSIRDY_BIT)
+#define RCC_CR_HSION                    BIT(RCC_CR_HSION_BIT)
+
+/* Clock configuration register */
+
+#define RCC_CFGR_USBPRE_BIT             22
+#define RCC_CFGR_PLLXTPRE_BIT           17
+#define RCC_CFGR_PLLSRC_BIT             16
+
+#define RCC_CFGR_MCO                    (0x3 << 24)
+#define RCC_CFGR_USBPRE                 BIT(RCC_CFGR_USBPRE_BIT)
+#define RCC_CFGR_PLLMUL                 (0xF << 18)
+#define RCC_CFGR_PLLXTPRE               BIT(RCC_CFGR_PLLXTPRE_BIT)
+#define RCC_CFGR_PLLSRC                 BIT(RCC_CFGR_PLLSRC_BIT)
+#define RCC_CFGR_ADCPRE                 (0x3 << 14)
+#define RCC_CFGR_PPRE2                  (0x7 << 11)
+#define RCC_CFGR_PPRE1                  (0x7 << 8)
+#define RCC_CFGR_HPRE                   (0xF << 4)
+#define RCC_CFGR_SWS                    (0x3 << 2)
+#define RCC_CFGR_SWS_PLL                (0x2 << 2)
+#define RCC_CFGR_SWS_HSE                (0x1 << 2)
+#define RCC_CFGR_SW                     0x3
+#define RCC_CFGR_SW_PLL                 0x2
+#define RCC_CFGR_SW_HSE                 0x1
+
+#define  RCC_CFGR_MCO1Source_HSI             ((uint32_t)0x00000000)
+#define  RCC_CFGR_MCO1Source_LSE             ((uint32_t)0x00200000)
+#define  RCC_CFGR_MCO1Source_HSE             ((uint32_t)0x00400000)
+#define  RCC_CFGR_MCO1Source_PLLCLK          ((uint32_t)0x00600000)
+#define  RCC_CFGR_MCO1Div_1                  ((uint32_t)0x00000000)
+#define  RCC_CFGR_MCO1Div_2                  ((uint32_t)0x04000000)
+#define  RCC_CFGR_MCO1Div_3                  ((uint32_t)0x05000000)
+#define  RCC_CFGR_MCO1Div_4                  ((uint32_t)0x06000000)
+#define  RCC_CFGR_MCO1Div_5                  ((uint32_t)0x07000000)
+#define  RCC_CFGR_MCO1_RESET_MASK            ((uint32_t)0xF89FFFFF)
+
+/* Clock interrupt register */
+
+#define RCC_CIR_CSSC_BIT                23
+#define RCC_CIR_PLLRDYC_BIT             20
+#define RCC_CIR_HSERDYC_BIT             19
+#define RCC_CIR_HSIRDYC_BIT             18
+#define RCC_CIR_LSERDYC_BIT             17
+#define RCC_CIR_LSIRDYC_BIT             16
+#define RCC_CIR_PLLRDYIE_BIT            12
+#define RCC_CIR_HSERDYIE_BIT            11
+#define RCC_CIR_HSIRDYIE_BIT            10
+#define RCC_CIR_LSERDYIE_BIT            9
+#define RCC_CIR_LSIRDYIE_BIT            8
+#define RCC_CIR_CSSF_BIT                7
+#define RCC_CIR_PLLRDYF_BIT             4
+#define RCC_CIR_HSERDYF_BIT             3
+#define RCC_CIR_HSIRDYF_BIT             2
+#define RCC_CIR_LSERDYF_BIT             1
+#define RCC_CIR_LSIRDYF_BIT             0
+
+#define RCC_CIR_CSSC                    BIT(RCC_CIR_CSSC_BIT)
+#define RCC_CIR_PLLRDYC                 BIT(RCC_CIR_PLLRDYC_BIT)
+#define RCC_CIR_HSERDYC                 BIT(RCC_CIR_HSERDYC_BIT)
+#define RCC_CIR_HSIRDYC                 BIT(RCC_CIR_HSIRDYC_BIT)
+#define RCC_CIR_LSERDYC                 BIT(RCC_CIR_LSERDYC_BIT)
+#define RCC_CIR_LSIRDYC                 BIT(RCC_CIR_LSIRDYC_BIT)
+#define RCC_CIR_PLLRDYIE                BIT(RCC_CIR_PLLRDYIE_BIT)
+#define RCC_CIR_HSERDYIE                BIT(RCC_CIR_HSERDYIE_BIT)
+#define RCC_CIR_HSIRDYIE                BIT(RCC_CIR_HSIRDYIE_BIT)
+#define RCC_CIR_LSERDYIE                BIT(RCC_CIR_LSERDYIE_BIT)
+#define RCC_CIR_LSIRDYIE                BIT(RCC_CIR_LSIRDYIE_BIT)
+#define RCC_CIR_CSSF                    BIT(RCC_CIR_CSSF_BIT)
+#define RCC_CIR_PLLRDYF                 BIT(RCC_CIR_PLLRDYF_BIT)
+#define RCC_CIR_HSERDYF                 BIT(RCC_CIR_HSERDYF_BIT)
+#define RCC_CIR_HSIRDYF                 BIT(RCC_CIR_HSIRDYF_BIT)
+#define RCC_CIR_LSERDYF                 BIT(RCC_CIR_LSERDYF_BIT)
+#define RCC_CIR_LSIRDYF                 BIT(RCC_CIR_LSIRDYF_BIT)
+
+/* APB2 peripheral reset register */
+
+#define RCC_APB2RSTR_TIM11RST_BIT       21
+#define RCC_APB2RSTR_TIM10RST_BIT       20
+#define RCC_APB2RSTR_TIM9RST_BIT        19
+#define RCC_APB2RSTR_ADC3RST_BIT        15
+#define RCC_APB2RSTR_USART1RST_BIT      14
+#define RCC_APB2RSTR_TIM8RST_BIT        13
+#define RCC_APB2RSTR_SPI1RST_BIT        12
+#define RCC_APB2RSTR_TIM1RST_BIT        11
+#define RCC_APB2RSTR_ADC2RST_BIT        10
+#define RCC_APB2RSTR_ADC1RST_BIT        9
+#define RCC_APB2RSTR_IOPGRST_BIT        8
+#define RCC_APB2RSTR_IOPFRST_BIT        7
+#define RCC_APB2RSTR_IOPERST_BIT        6
+#define RCC_APB2RSTR_IOPDRST_BIT        5
+#define RCC_APB2RSTR_IOPCRST_BIT        4
+#define RCC_APB2RSTR_IOPBRST_BIT        3
+#define RCC_APB2RSTR_IOPARST_BIT        2
+#define RCC_APB2RSTR_AFIORST_BIT        0
+
+#define RCC_APB2RSTR_TIM11RST           BIT(RCC_APB2RSTR_TIM11RST_BIT)
+#define RCC_APB2RSTR_TIM10RST           BIT(RCC_APB2RSTR_TIM10RST_BIT)
+#define RCC_APB2RSTR_TIM9RST            BIT(RCC_APB2RSTR_TIM9RST_BIT)
+#define RCC_APB2RSTR_ADC3RST            BIT(RCC_APB2RSTR_ADC3RST_BIT)
+#define RCC_APB2RSTR_USART1RST          BIT(RCC_APB2RSTR_USART1RST_BIT)
+#define RCC_APB2RSTR_TIM8RST            BIT(RCC_APB2RSTR_TIM8RST_BIT)
+#define RCC_APB2RSTR_SPI1RST            BIT(RCC_APB2RSTR_SPI1RST_BIT)
+#define RCC_APB2RSTR_TIM1RST            BIT(RCC_APB2RSTR_TIM1RST_BIT)
+#define RCC_APB2RSTR_ADC2RST            BIT(RCC_APB2RSTR_ADC2RST_BIT)
+#define RCC_APB2RSTR_ADC1RST            BIT(RCC_APB2RSTR_ADC1RST_BIT)
+#define RCC_APB2RSTR_IOPGRST            BIT(RCC_APB2RSTR_IOPGRST_BIT)
+#define RCC_APB2RSTR_IOPFRST            BIT(RCC_APB2RSTR_IOPFRST_BIT)
+#define RCC_APB2RSTR_IOPERST            BIT(RCC_APB2RSTR_IOPERST_BIT)
+#define RCC_APB2RSTR_IOPDRST            BIT(RCC_APB2RSTR_IOPDRST_BIT)
+#define RCC_APB2RSTR_IOPCRST            BIT(RCC_APB2RSTR_IOPCRST_BIT)
+#define RCC_APB2RSTR_IOPBRST            BIT(RCC_APB2RSTR_IOPBRST_BIT)
+#define RCC_APB2RSTR_IOPARST            BIT(RCC_APB2RSTR_IOPARST_BIT)
+#define RCC_APB2RSTR_AFIORST            BIT(RCC_APB2RSTR_AFIORST_BIT)
+
+/* APB1 peripheral reset register */
+
+#define RCC_APB1RSTR_DACRST_BIT         29
+#define RCC_APB1RSTR_PWRRST_BIT         28
+#define RCC_APB1RSTR_BKPRST_BIT         27
+#define RCC_APB1RSTR_CANRST_BIT         25
+#define RCC_APB1RSTR_USBRST_BIT         23
+#define RCC_APB1RSTR_I2C2RST_BIT        22
+#define RCC_APB1RSTR_I2C1RST_BIT        21
+#define RCC_APB1RSTR_UART5RST_BIT       20
+#define RCC_APB1RSTR_UART4RST_BIT       19
+#define RCC_APB1RSTR_USART3RST_BIT      18
+#define RCC_APB1RSTR_USART2RST_BIT      17
+#define RCC_APB1RSTR_SPI3RST_BIT        15
+#define RCC_APB1RSTR_SPI2RST_BIT        14
+#define RCC_APB1RSTR_WWDRST_BIT         11
+#define RCC_APB1RSTR_TIM14RST_BIT       8
+#define RCC_APB1RSTR_TIM13RST_BIT       7
+#define RCC_APB1RSTR_TIM12RST_BIT       6
+#define RCC_APB1RSTR_TIM7RST_BIT        5
+#define RCC_APB1RSTR_TIM6RST_BIT        4
+#define RCC_APB1RSTR_TIM5RST_BIT        3
+#define RCC_APB1RSTR_TIM4RST_BIT        2
+#define RCC_APB1RSTR_TIM3RST_BIT        1
+#define RCC_APB1RSTR_TIM2RST_BIT        0
+
+#define RCC_APB1RSTR_DACRST             BIT(RCC_APB1RSTR_DACRST_BIT)
+#define RCC_APB1RSTR_PWRRST             BIT(RCC_APB1RSTR_PWRRST_BIT)
+#define RCC_APB1RSTR_BKPRST             BIT(RCC_APB1RSTR_BKPRST_BIT)
+#define RCC_APB1RSTR_CANRST             BIT(RCC_APB1RSTR_CANRST_BIT)
+#define RCC_APB1RSTR_USBRST             BIT(RCC_APB1RSTR_USBRST_BIT)
+#define RCC_APB1RSTR_I2C2RST            BIT(RCC_APB1RSTR_I2C2RST_BIT)
+#define RCC_APB1RSTR_I2C1RST            BIT(RCC_APB1RSTR_I2C1RST_BIT)
+#define RCC_APB1RSTR_UART5RST           BIT(RCC_APB1RSTR_UART5RST_BIT)
+#define RCC_APB1RSTR_UART4RST           BIT(RCC_APB1RSTR_UART4RST_BIT)
+#define RCC_APB1RSTR_USART3RST          BIT(RCC_APB1RSTR_USART3RST_BIT)
+#define RCC_APB1RSTR_USART2RST          BIT(RCC_APB1RSTR_USART2RST_BIT)
+#define RCC_APB1RSTR_SPI3RST            BIT(RCC_APB1RSTR_SPI3RST_BIT)
+#define RCC_APB1RSTR_SPI2RST            BIT(RCC_APB1RSTR_SPI2RST_BIT)
+#define RCC_APB1RSTR_WWDRST             BIT(RCC_APB1RSTR_WWDRST_BIT)
+#define RCC_APB1RSTR_TIM14RST           BIT(RCC_APB1RSTR_TIM14RST_BIT)
+#define RCC_APB1RSTR_TIM13RST           BIT(RCC_APB1RSTR_TIM13RST_BIT)
+#define RCC_APB1RSTR_TIM12RST           BIT(RCC_APB1RSTR_TIM12RST_BIT)
+#define RCC_APB1RSTR_TIM7RST            BIT(RCC_APB1RSTR_TIM7RST_BIT)
+#define RCC_APB1RSTR_TIM6RST            BIT(RCC_APB1RSTR_TIM6RST_BIT)
+#define RCC_APB1RSTR_TIM5RST            BIT(RCC_APB1RSTR_TIM5RST_BIT)
+#define RCC_APB1RSTR_TIM4RST            BIT(RCC_APB1RSTR_TIM4RST_BIT)
+#define RCC_APB1RSTR_TIM3RST            BIT(RCC_APB1RSTR_TIM3RST_BIT)
+#define RCC_APB1RSTR_TIM2RST            BIT(RCC_APB1RSTR_TIM2RST_BIT)
+
+/* AHB peripheral clock enable register */
+
+#define RCC_AHBENR_SDIOEN_BIT           10
+#define RCC_AHBENR_FSMCEN_BIT           8
+#define RCC_AHBENR_CRCEN_BIT            7
+#define RCC_AHBENR_FLITFEN_BIT          4
+#define RCC_AHBENR_SRAMEN_BIT           2
+#define RCC_AHBENR_DMA2EN_BIT           1
+#define RCC_AHBENR_DMA1EN_BIT           0
+
+#define RCC_AHBENR_SDIOEN               BIT(RCC_AHBENR_SDIOEN_BIT)
+#define RCC_AHBENR_FSMCEN               BIT(RCC_AHBENR_FSMCEN_BIT)
+#define RCC_AHBENR_CRCEN                BIT(RCC_AHBENR_CRCEN_BIT)
+#define RCC_AHBENR_FLITFEN              BIT(RCC_AHBENR_FLITFEN_BIT)
+#define RCC_AHBENR_SRAMEN               BIT(RCC_AHBENR_SRAMEN_BIT)
+#define RCC_AHBENR_DMA2EN               BIT(RCC_AHBENR_DMA2EN_BIT)
+#define RCC_AHBENR_DMA1EN               BIT(RCC_AHBENR_DMA1EN_BIT)
+
+/* APB2 peripheral clock enable register */
+
+#define RCC_APB2ENR_TIM11EN_BIT         21
+#define RCC_APB2ENR_TIM10EN_BIT         20
+#define RCC_APB2ENR_TIM9EN_BIT          19
+#define RCC_APB2ENR_ADC3EN_BIT          15
+#define RCC_APB2ENR_USART1EN_BIT        14
+#define RCC_APB2ENR_TIM8EN_BIT          13
+#define RCC_APB2ENR_SPI1EN_BIT          12
+#define RCC_APB2ENR_TIM1EN_BIT          11
+#define RCC_APB2ENR_ADC2EN_BIT          10
+#define RCC_APB2ENR_ADC1EN_BIT          9
+#define RCC_APB2ENR_IOPGEN_BIT          8
+#define RCC_APB2ENR_IOPFEN_BIT          7
+#define RCC_APB2ENR_IOPEEN_BIT          6
+#define RCC_APB2ENR_IOPDEN_BIT          5
+#define RCC_APB2ENR_IOPCEN_BIT          4
+#define RCC_APB2ENR_IOPBEN_BIT          3
+#define RCC_APB2ENR_IOPAEN_BIT          2
+#define RCC_APB2ENR_AFIOEN_BIT          0
+
+#define RCC_APB2ENR_TIM11EN             BIT(RCC_APB2ENR_TIM11EN_BIT)
+#define RCC_APB2ENR_TIM10EN             BIT(RCC_APB2ENR_TIM10EN_BIT)
+#define RCC_APB2ENR_TIM9EN              BIT(RCC_APB2ENR_TIM9EN_BIT)
+#define RCC_APB2ENR_ADC3EN              BIT(RCC_APB2ENR_ADC3EN_BIT)
+#define RCC_APB2ENR_USART1EN            BIT(RCC_APB2ENR_USART1EN_BIT)
+#define RCC_APB2ENR_TIM8EN              BIT(RCC_APB2ENR_TIM8EN_BIT)
+#define RCC_APB2ENR_SPI1EN              BIT(RCC_APB2ENR_SPI1EN_BIT)
+#define RCC_APB2ENR_TIM1EN              BIT(RCC_APB2ENR_TIM1EN_BIT)
+#define RCC_APB2ENR_ADC2EN              BIT(RCC_APB2ENR_ADC2EN_BIT)
+#define RCC_APB2ENR_ADC1EN              BIT(RCC_APB2ENR_ADC1EN_BIT)
+#define RCC_APB2ENR_IOPGEN              BIT(RCC_APB2ENR_IOPGEN_BIT)
+#define RCC_APB2ENR_IOPFEN              BIT(RCC_APB2ENR_IOPFEN_BIT)
+#define RCC_APB2ENR_IOPEEN              BIT(RCC_APB2ENR_IOPEEN_BIT)
+#define RCC_APB2ENR_IOPDEN              BIT(RCC_APB2ENR_IOPDEN_BIT)
+#define RCC_APB2ENR_IOPCEN              BIT(RCC_APB2ENR_IOPCEN_BIT)
+#define RCC_APB2ENR_IOPBEN              BIT(RCC_APB2ENR_IOPBEN_BIT)
+#define RCC_APB2ENR_IOPAEN              BIT(RCC_APB2ENR_IOPAEN_BIT)
+#define RCC_APB2ENR_AFIOEN              BIT(RCC_APB2ENR_AFIOEN_BIT)
+
+/* APB1 peripheral clock enable register */
+
+#define RCC_APB1ENR_DACEN_BIT           29
+#define RCC_APB1ENR_PWREN_BIT           28
+#define RCC_APB1ENR_BKPEN_BIT           27
+#define RCC_APB1ENR_CANEN_BIT           25
+#define RCC_APB1ENR_USBEN_BIT           23
+#define RCC_APB1ENR_I2C2EN_BIT          22
+#define RCC_APB1ENR_I2C1EN_BIT          21
+#define RCC_APB1ENR_UART5EN_BIT         20
+#define RCC_APB1ENR_UART4EN_BIT         19
+#define RCC_APB1ENR_USART3EN_BIT        18
+#define RCC_APB1ENR_USART2EN_BIT        17
+#define RCC_APB1ENR_SPI3EN_BIT          15
+#define RCC_APB1ENR_SPI2EN_BIT          14
+#define RCC_APB1ENR_WWDEN_BIT           11
+#define RCC_APB1ENR_TIM14EN_BIT         8
+#define RCC_APB1ENR_TIM13EN_BIT         7
+#define RCC_APB1ENR_TIM12EN_BIT         6
+#define RCC_APB1ENR_TIM7EN_BIT          5
+#define RCC_APB1ENR_TIM6EN_BIT          4
+#define RCC_APB1ENR_TIM5EN_BIT          3
+#define RCC_APB1ENR_TIM4EN_BIT          2
+#define RCC_APB1ENR_TIM3EN_BIT          1
+#define RCC_APB1ENR_TIM2EN_BIT          0
+
+#define RCC_APB1ENR_DACEN               BIT(RCC_APB1ENR_DACEN_BIT)
+#define RCC_APB1ENR_PWREN               BIT(RCC_APB1ENR_PWREN_BIT)
+#define RCC_APB1ENR_BKPEN               BIT(RCC_APB1ENR_BKPEN_BIT)
+#define RCC_APB1ENR_CANEN               BIT(RCC_APB1ENR_CANEN_BIT)
+#define RCC_APB1ENR_USBEN               BIT(RCC_APB1ENR_USBEN_BIT)
+#define RCC_APB1ENR_I2C2EN              BIT(RCC_APB1ENR_I2C2EN_BIT)
+#define RCC_APB1ENR_I2C1EN              BIT(RCC_APB1ENR_I2C1EN_BIT)
+#define RCC_APB1ENR_UART5EN             BIT(RCC_APB1ENR_UART5EN_BIT)
+#define RCC_APB1ENR_UART4EN             BIT(RCC_APB1ENR_UART4EN_BIT)
+#define RCC_APB1ENR_USART3EN            BIT(RCC_APB1ENR_USART3EN_BIT)
+#define RCC_APB1ENR_USART2EN            BIT(RCC_APB1ENR_USART2EN_BIT)
+#define RCC_APB1ENR_SPI3EN              BIT(RCC_APB1ENR_SPI3EN_BIT)
+#define RCC_APB1ENR_SPI2EN              BIT(RCC_APB1ENR_SPI2EN_BIT)
+#define RCC_APB1ENR_WWDEN               BIT(RCC_APB1ENR_WWDEN_BIT)
+#define RCC_APB1ENR_TIM14EN             BIT(RCC_APB1ENR_TIM14EN_BIT)
+#define RCC_APB1ENR_TIM13EN             BIT(RCC_APB1ENR_TIM13EN_BIT)
+#define RCC_APB1ENR_TIM12EN             BIT(RCC_APB1ENR_TIM12EN_BIT)
+#define RCC_APB1ENR_TIM7EN              BIT(RCC_APB1ENR_TIM7EN_BIT)
+#define RCC_APB1ENR_TIM6EN              BIT(RCC_APB1ENR_TIM6EN_BIT)
+#define RCC_APB1ENR_TIM5EN              BIT(RCC_APB1ENR_TIM5EN_BIT)
+#define RCC_APB1ENR_TIM4EN              BIT(RCC_APB1ENR_TIM4EN_BIT)
+#define RCC_APB1ENR_TIM3EN              BIT(RCC_APB1ENR_TIM3EN_BIT)
+#define RCC_APB1ENR_TIM2EN              BIT(RCC_APB1ENR_TIM2EN_BIT)
+
+/* Backup domain control register */
+
+#define RCC_BDCR_BDRST_BIT              16
+#define RCC_BDCR_RTCEN_BIT              15
+#define RCC_BDCR_LSEBYP_BIT             2
+#define RCC_BDCR_LSERDY_BIT             1
+#define RCC_BDCR_LSEON_BIT              0
+
+#define RCC_BDCR_BDRST                  BIT(RCC_BDCR_BDRST_BIT)
+#define RCC_BDCR_RTCEN                  BIT(RCC_BDCR_RTC_BIT)
+#define RCC_BDCR_RTCSEL                 (0x3 << 8)
+#define RCC_BDCR_RTCSEL_NONE            (0x0 << 8)
+#define RCC_BDCR_RTCSEL_LSE             (0x1 << 8)
+#define RCC_BDCR_RTCSEL_LSI             (0x2 << 8)
+#define RCC_BDCR_RTCSEL_HSE             (0x3 << 8)
+#define RCC_BDCR_LSEBYP                 BIT(RCC_BDCR_LSEBYP_BIT)
+#define RCC_BDCR_LSERDY                 BIT(RCC_BDCR_LSERDY_BIT)
+#define RCC_BDCR_LSEON                  BIT(RCC_BDCR_LSEON_BIT)
+
+/* Control/status register */
+
+#define RCC_CSR_LPWRRSTF_BIT            31
+#define RCC_CSR_WWDGRSTF_BIT            30
+#define RCC_CSR_IWDGRSTF_BIT            29
+#define RCC_CSR_SFTRSTF_BIT             28
+#define RCC_CSR_PORRSTF_BIT             27
+#define RCC_CSR_PINRSTF_BIT             26
+#define RCC_CSR_RMVF_BIT                24
+#define RCC_CSR_LSIRDY_BIT              1
+#define RCC_CSR_LSION_BIT               0
+
+#define RCC_CSR_LPWRRSTF                BIT(RCC_CSR_LPWRRSTF_BIT)
+#define RCC_CSR_WWDGRSTF                BIT(RCC_CSR_WWDGRSTF_BIT)
+#define RCC_CSR_IWDGRSTF                BIT(RCC_CSR_IWDGRSTF_BIT)
+#define RCC_CSR_SFTRSTF                 BIT(RCC_CSR_SFTRSTF_BIT)
+#define RCC_CSR_PORRSTF                 BIT(RCC_CSR_PORRSTF_BIT)
+#define RCC_CSR_PINRSTF                 BIT(RCC_CSR_PINRSTF_BIT)
+#define RCC_CSR_RMVF                    BIT(RCC_CSR_RMVF_BIT)
+#define RCC_CSR_LSIRDY                  BIT(RCC_CSR_LSIRDY_BIT)
+#define RCC_CSR_LSION                   BIT(RCC_CSR_LSION_BIT)
+
+/*
+ * Convenience routines
+ */
+
+/**
+ * SYSCLK sources
+ * @see rcc_clk_init()
+ */
+typedef enum rcc_sysclk_src {
+    RCC_CLKSRC_HSI = 0x0,
+    RCC_CLKSRC_HSE = 0x1,
+    RCC_CLKSRC_PLL = 0x2,
+} rcc_sysclk_src;
+
+/**
+ * PLL entry clock source
+ * @see rcc_clk_init()
+ */
+typedef enum rcc_pllsrc {
+    RCC_PLLSRC_HSE = (0x1 << 16),
+    RCC_PLLSRC_HSI_DIV_2 = (0x0 << 16)
+} rcc_pllsrc;
+
+/**
+ * PLL multipliers
+ * @see rcc_clk_init()
+ */
+typedef enum rcc_pll_multiplier {
+    RCC_PLLMUL_2 = (0x0 << 18),
+    RCC_PLLMUL_3 = (0x1 << 18),
+    RCC_PLLMUL_4 = (0x2 << 18),
+    RCC_PLLMUL_5 = (0x3 << 18),
+    RCC_PLLMUL_6 = (0x4 << 18),
+    RCC_PLLMUL_7 = (0x5 << 18),
+    RCC_PLLMUL_8 = (0x6 << 18),
+    RCC_PLLMUL_9 = (0x7 << 18),
+    RCC_PLLMUL_10 = (0x8 << 18),
+    RCC_PLLMUL_11 = (0x9 << 18),
+    RCC_PLLMUL_12 = (0xA << 18),
+    RCC_PLLMUL_13 = (0xB << 18),
+    RCC_PLLMUL_14 = (0xC << 18),
+    RCC_PLLMUL_15 = (0xD << 18),
+    RCC_PLLMUL_16 = (0xE << 18),
+} rcc_pll_multiplier;
+
+/**
+ * @brief Identifies bus and clock line for a peripheral.
+ *
+ * Also generally useful as a unique identifier for that peripheral
+ * (or its corresponding device struct).
+ */
+typedef enum rcc_clk_id {
+    RCC_GPIOA,
+    RCC_GPIOB,
+    RCC_GPIOC,
+    RCC_GPIOD,
+//    RCC_AFIO,
+    RCC_ADC1,
+    RCC_ADC2,
+    RCC_ADC3,
+    RCC_USART1,
+    RCC_USART2,
+    RCC_USART3,
+    RCC_TIMER1,
+    RCC_TIMER2,
+    RCC_TIMER3,
+    RCC_TIMER4,
+    RCC_SPI1,
+    RCC_SPI2,
+    RCC_DMA1,
+    RCC_PWR,
+    RCC_BKP,
+    RCC_I2C1,
+    RCC_I2C2,
+    RCC_CRC,
+//    RCC_FLITF,
+//    RCC_SRAM,
+    RCC_GPIOE,
+    RCC_GPIOF,
+    RCC_GPIOG,
+    RCC_UART4,
+    RCC_UART5,
+    RCC_TIMER5,
+    RCC_TIMER6,
+    RCC_TIMER7,
+    RCC_TIMER8,
+    RCC_FSMC,
+    RCC_DAC,
+    RCC_DMA2,
+    RCC_SDIO,
+    RCC_SPI3,
+    RCC_TIMER9,
+    RCC_TIMER10,
+    RCC_TIMER11,
+    RCC_TIMER12,
+    RCC_TIMER13,
+    RCC_TIMER14,
+    RCC_USBFS,
+    RCC_SYSCFG,
+	RCC_SPI4
+} rcc_clk_id;
+
+void rcc_clk_init(rcc_sysclk_src sysclk_src,
+                  rcc_pllsrc pll_src,
+                  rcc_pll_multiplier pll_mul);
+void rcc_clk_disable(rcc_clk_id device);
+void rcc_clk_enable(rcc_clk_id device);
+void rcc_reset_dev(rcc_clk_id device);
+
+void SetupClock72MHz();
+void SetupClock120MHz();
+void SetupClock168MHz();
+
+typedef enum rcc_clk_domain {
+    RCC_APB1,
+    RCC_APB2,
+    RCC_AHB1,
+    RCC_AHB2,
+    RCC_AHB3
+} rcc_clk_domain;
+
+rcc_clk_domain rcc_dev_clk(rcc_clk_id device);
+
+uint32 rcc_dev_clk_speed(rcc_clk_id id);
+uint32 rcc_dev_timer_clk_speed(rcc_clk_id id);
+
+/**
+ * Prescaler identifiers
+ * @see rcc_set_prescaler()
+ */
+typedef enum rcc_prescaler {
+    RCC_PRESCALER_AHB,
+    RCC_PRESCALER_APB1,
+    RCC_PRESCALER_APB2,
+    RCC_PRESCALER_USB,
+    RCC_PRESCALER_ADC
+} rcc_prescaler;
+
+/**
+ * ADC prescaler dividers
+ * @see rcc_set_prescaler()
+ */
+typedef enum rcc_adc_divider {
+    RCC_ADCPRE_PCLK_DIV_2 = 0x0 << 14,
+    RCC_ADCPRE_PCLK_DIV_4 = 0x1 << 14,
+    RCC_ADCPRE_PCLK_DIV_6 = 0x2 << 14,
+    RCC_ADCPRE_PCLK_DIV_8 = 0x3 << 14,
+} rcc_adc_divider;
+
+/**
+ * APB1 prescaler dividers
+ * @see rcc_set_prescaler()
+ */
+typedef enum rcc_apb1_divider {
+    RCC_APB1_HCLK_DIV_1 = 0x0 << 8,
+    RCC_APB1_HCLK_DIV_2 = 0x4 << 8,
+    RCC_APB1_HCLK_DIV_4 = 0x5 << 8,
+    RCC_APB1_HCLK_DIV_8 = 0x6 << 8,
+    RCC_APB1_HCLK_DIV_16 = 0x7 << 8,
+} rcc_apb1_divider;
+
+/**
+ * APB2 prescaler dividers
+ * @see rcc_set_prescaler()
+ */
+typedef enum rcc_apb2_divider {
+    RCC_APB2_HCLK_DIV_1 = 0x0 << 11,
+    RCC_APB2_HCLK_DIV_2 = 0x4 << 11,
+    RCC_APB2_HCLK_DIV_4 = 0x5 << 11,
+    RCC_APB2_HCLK_DIV_8 = 0x6 << 11,
+    RCC_APB2_HCLK_DIV_16 = 0x7 << 11,
+} rcc_apb2_divider;
+
+/**
+ * AHB prescaler dividers
+ * @see rcc_set_prescaler()
+ */
+typedef enum rcc_ahb_divider {
+    RCC_AHB_SYSCLK_DIV_1 = 0x0 << 4,
+    RCC_AHB_SYSCLK_DIV_2 = 0x8 << 4,
+    RCC_AHB_SYSCLK_DIV_4 = 0x9 << 4,
+    RCC_AHB_SYSCLK_DIV_8 = 0xA << 4,
+    RCC_AHB_SYSCLK_DIV_16 = 0xB << 4,
+    RCC_AHB_SYSCLK_DIV_32 = 0xC << 4,
+    RCC_AHB_SYSCLK_DIV_64 = 0xD << 4,
+    RCC_AHB_SYSCLK_DIV_128 = 0xD << 4,
+    RCC_AHB_SYSCLK_DIV_256 = 0xE << 4,
+    RCC_AHB_SYSCLK_DIV_512 = 0xF << 4,
+} rcc_ahb_divider;
+
+void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider);
+
+
+/**
+ * @brief Start the low speed internal oscillatior
+ */
+static inline void rcc_start_lsi(void) {
+	*bb_perip(&RCC_BASE->CSR, RCC_CSR_LSION_BIT) = 1;
+	while (*bb_perip(&RCC_BASE->CSR, RCC_CSR_LSIRDY_BIT) == 0);
+}
+
+/* FIXME [0.0.13] Just have data point to an rcc_pll_multiplier! */
+/**
+ * @brief Start the low speed external oscillatior
+ */
+static inline void rcc_start_lse(void) {
+	bb_peri_set_bit(&RCC_BASE->BDCR, RCC_BDCR_LSEBYP_BIT, 0);
+	bb_peri_set_bit(&RCC_BASE->BDCR, RCC_BDCR_LSEON_BIT, 1);
+	while (bb_peri_get_bit(&RCC_BASE->BDCR, RCC_BDCR_LSERDY_BIT ) == 0);
+}
+
+/*
+ * Deprecated bits.
+ */
+static inline void rcc_start_hse(void) {				// Added to support RTClock
+//	*bb_perip(&RCC_BASE->CR, RCC_CR_HSEON_BIT) = 1;
+	while (bb_peri_get_bit(&RCC_BASE->CR, RCC_CR_HSERDY_BIT) == 0);
+}
+
+
+
+#ifdef __cplusplus
+} // extern "C"
+#endif
+
+#endif
diff --git a/STM32F4/variants/black_f407vet6/black_f4.cpp b/STM32F4/variants/black_f407vet6/black_f4.cpp
new file mode 100644
index 000000000..78d37aafc
--- /dev/null
+++ b/STM32F4/variants/black_f407vet6/black_f4.cpp
@@ -0,0 +1,264 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file   black_f4.cpp
+ * @author ala42
+ * @brief  black_f4 board file.
+ */
+
+#ifdef BOARD_black_f4
+
+#include "black_f4.h"
+
+//#include "fsmc.h"
+#include "gpio.h"
+#include "rcc.h"
+#include "timer.h"
+
+#include "wirish_types.h"
+
+// Pins reserved for the on-board hardware
+#define USB_DM_PIN		BOARD_USB_DM_PIN // PA11
+#define USB_DP_PIN		BOARD_USB_DP_PIN // PA12
+
+#define FLASH_CS_PIN	PB0
+#define FLASH_CLK_PIN	BOARD_SPI3_SCK_PIN	// PB3
+#define FLASH_DO_PIN	BOARD_SPI3_MISO_PIN	// PB4
+#define FLASH_DI_PIN	BOARD_SPI3_MOSI_PIN	// PB5
+
+#define NRF24_CLK_PIN	BOARD_SPI3_SCK_PIN	// PB3
+#define NRF24_DO_PIN	BOARD_SPI3_MISO_PIN	// PB4
+#define NRF24_DI_PIN	BOARD_SPI3_MOSI_PIN	// PB5
+#define NRF24_CE_PIN	PB6
+#define NRF24_CS_PIN	PB7
+#define NRF24_IRQ_PIN	PB8
+
+// SD card, SDIO mode
+#define SD_DAT0         BOARD_SDIO_D0	// PC8
+#define SD_DAT1         BOARD_SDIO_D1	// PC9
+#define SD_DAT2         BOARD_SDIO_D2	// PC10
+#define SD_DAT3         BOARD_SDIO_D3	// PC11
+#define SD_CLK          BOARD_SDIO_CK	// PC12
+#define SD_CMD          BOARD_SDIO_CMD	// PD2
+// SD card, SPI mode, only usable with software SPI
+#define SD_DI           BOARD_SDIO_CMD	// PD2
+#define SD_DO           BOARD_SDIO_D0	// PC8
+#define SD_CS           BOARD_SDIO_D3	// PC11
+#define SD_SCLK         BOARD_SDIO_CK	// PC12
+
+//static void initSRAMChip(void);
+/*****************************************************************************/
+//  Alternate functions, see DocID022152 Rev 8, Table 9. 
+/*****************************************************************************/
+void boardInit(void) {
+/*	// remap TIMER8 to PC6-9
+	gpio_set_af_mode(GPIOC, 6, 3);
+	gpio_set_af_mode(GPIOC, 7, 3);
+	gpio_set_af_mode(GPIOC, 8, 3);
+	gpio_set_af_mode(GPIOC, 9, 3);
+
+	// remap TIMER1 to PE9,11,13,14
+	gpio_set_af_mode(GPIOE,  9, 1);
+	gpio_set_af_mode(GPIOE, 11, 1);
+	gpio_set_af_mode(GPIOE, 13, 1);
+	gpio_set_af_mode(GPIOE, 14, 1);
+
+	// remap TIMER3 to PB4,5,0,1
+	gpio_set_af_mode(GPIOB,  4, 2);
+	gpio_set_af_mode(GPIOB,  5, 2);
+	gpio_set_af_mode(GPIOB,  0, 2);
+	gpio_set_af_mode(GPIOB,  1, 2);
+
+	//gpio_set_af_mode(GPIOA, 2, 7);
+	//gpio_set_af_mode(GPIOA, 3, 7);
+*/
+	return;
+}
+
+/*
+typedef struct stm32_pin_info {
+    gpio_dev *gpio_device;      // Maple pin's GPIO device
+    uint8 gpio_bit;             // Pin's GPIO port bit.
+    timer_dev *timer_device;    // Pin's timer device, if any.
+    uint8 timer_channel;        // Timer channel, or 0 if none.
+    const adc_dev *adc_device;  // ADC device, if any.
+    uint8 adc_channel;          // Pin ADC channel, or ADCx if none.
+} stm32_pin_info;
+*/
+
+extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = { // LQFP100 package pin
+    {GPIOA,  0, TIMER5, 1, ADC1,    0}, // D00/PA0  | 23 | USART2_CTS | UART4_TX       | ETH_MII_CRS      | TIM2_CH1_ETR   | TIM5_CH1       | TIM8_ETR                      | ADC123_IN0/WKUP
+    {GPIOA,  1, TIMER5, 2, ADC1,    1}, // D01/PA1  | 24 | USART2_RTS | UART4_RX       | ETH_RMII_REF_CLK | ETH_MII_RX_CLK | TIM5_CH2       | TIM2_CH2                      | ADC123_IN1
+    {GPIOA,  2, TIMER5, 3, ADC1,    2}, // D02/PA2  | 25 | USART2_TX  | TIM5_CH3       | TIM9_CH1         | TIM2_CH3       | ETH_MDIO                                       | ADC123_IN2
+    {GPIOA,  3, TIMER5, 4, ADC1,    3}, // D03/PA3  | 26 | USART2_RX  | TIM5_CH4       | TIM9_CH2         | TIM2_CH4       | OTG_HS_ULPI_D0 | ETH_MII_COL                   | ADC123_IN3
+    {GPIOA,  4,   NULL, 0, ADC1,    4}, // D04/PA4  | 29 | SPI1_NSS   | SPI3_NSS       | USART2_CK        | DCMI_HSYNC     | OTG_HS_SOF     | I2S3_WS                       | ADC12_IN4 / DAC_OUT1
+    {GPIOA,  5,   NULL, 0, ADC1,    5}, // D05/PA5  | 30 | SPI1_SCK   | OTG_HS_ULPI_CK | TIM2_CH1_ETR     | TIM8_CH1N                                                       | ADC12_IN5 / DAC_OUT2
+    {GPIOA,  6,   NULL, 1, ADC1,    6}, // D06/PA6  | 31 | SPI1_MISO  | TIM8_BKIN      | TIM13_CH1        | DCMI_PIXCLK    | TIM3_CH1       | TIM1_BKIN                     | ADC12_IN6
+    {GPIOA,  7,   NULL, 0, ADC1,    7}, // D07/PA7  | 32 | SPI1_MOSI  | TIM8_CH1N      | TIM14_CH1        | TIM3_CH2       | ETH_MII_RX_DV  | TIM1_CH1N   / ETH_RMII_CRS_DV | ADC12_IN7
+    {GPIOA,  8,   NULL, 0, NULL, ADCx}, // D08/PA8  | 67 | MCO1       | USART1_CK      | TIM1_CH1         | I2C3_SCL       | OTG_FS_SOF
+    {GPIOA,  9,   NULL, 0, NULL, ADCx}, // D09/PA9  | 68 | USART1_TX  | TIM1_CH2       | I2C3_SMBA        | DCMI_D0
+    {GPIOA, 10,   NULL, 0, NULL, ADCx}, // D10/PA10 | 69 | USART1_RX  | TIM1_CH3       | OTG_FS_ID        | DCMI_D1
+    {GPIOA, 11,   NULL, 0, NULL, ADCx}, // D11/PA11 | 70 | USART1_CTS | CAN1_RX        | TIM1_CH4         | OTG_FS_DM
+    {GPIOA, 12,   NULL, 0, NULL, ADCx}, // D12/PA12 | 71 | USART1_RTS | CAN1_TX        | TIM1_ETR         | OTG_FS_DP
+    {GPIOA, 13,   NULL, 0, NULL, ADCx}, // D13/PA13 | 72 | JTMS-SWDIO
+    {GPIOA, 14,   NULL, 0, NULL, ADCx}, // D14/PA14 | 76 | JTCK-SWCLK
+    {GPIOA, 15, TIMER2, 1, NULL, ADCx}, // D15/PA15 | 77 | JTDI       | SPI3_NSS       | I2S3_WS          | TIM2_CH1_ETR   | SPI1_NSS
+
+    {GPIOB,  0, TIMER3, 3, ADC1,    8}, // D16/PB0  | 35 | TIM3_CH3   | TIM8_CH2N | OTG_HS_ULPI_D1 | ETH_MII_RXD2   | TIM1_CH2N      | ADC12_IN8
+    {GPIOB,  1, TIMER3, 4, ADC1,    9}, // D17/PB1  | 36 | TIM3_CH4   | TIM8_CH3N | OTG_HS_ULPI_D2 | ETH_MII_RXD3   | TIM1_CH3N      | ADC12_IN9
+    {GPIOB,  2,   NULL, 0, NULL, ADCx}, // D18/PB2  | 37 | BOOT1    
+    {GPIOB,  3, TIMER2, 2, NULL, ADCx}, // D19/PB3  | 89 | JTDO       | TRACESWO  | SPI3_SCK       | I2S3_CK        | TIM2_CH2       | SPI1_SCK
+    {GPIOB,  4, TIMER3, 1, NULL, ADCx}, // D20/PB4  | 90 | NJTRST     | SPI3_MISO | TIM3_CH1       | SPI1_MISO      | I2S3ext_SD
+    {GPIOB,  5, TIMER3, 2, NULL, ADCx}, // D21/PB5  | 91 | I2C1_SMBA  | CAN2_RX   | OTG_HS_ULPI_D7 | ETH_PPS_OUT    | TIM3_CH2       | SPI1_MOSI      | SPI3_MOSI      | DCMI_D10      | I2S3_SD
+    {GPIOB,  6,   NULL, 0, NULL, ADCx}, // D22/PB6  | 92 | I2C1_SCL   | TIM4_CH1  | CAN2_TX        | DCMI_D5        | USART1_TX
+    {GPIOB,  7,   NULL, 0, NULL, ADCx}, // D23/PB7  | 93 | I2C1_SDA   | FSMC_NL   | DCMI_VSYNC     | USART1_RX      | TIM4_CH2
+    {GPIOB,  8,   NULL, 0, NULL, ADCx}, // D24/PB8  | 95 | TIM4_CH3   | SDIO_D4   | TIM10_CH1      | DCMI_D6        | ETH_MII_TXD3   | I2C1_SCL       | CAN1_RX
+    {GPIOB,  9,   NULL, 0, NULL, ADCx}, // D25/PB9  | 96 | SPI2_NSS   | I2S2_WS   | TIM4_CH4       | TIM11_CH1      | SDIO_D5        | DCMI_D7        | I2C1_SDA       | CAN1_TX
+    {GPIOB, 10,   NULL, 0, NULL, ADCx}, // D26/PB10 | 47 | SPI2_SCK   | I2S2_CK   | I2C2_SCL       | USART3_TX      | OTG_HS_ULPI_D3 | ETH_MII_RX_ER  | TIM2_CH3
+    {GPIOB, 11,   NULL, 0, NULL, ADCx}, // D27/PB11 | 48 | I2C2_SDA   | USART3_RX | OTG_HS_ULPI_D4 | ETH_RMII_TX_EN | ETH_MII_TX_EN  | TIM2_CH4
+    {GPIOB, 12,   NULL, 0, NULL, ADCx}, // D28/PB12 | 51 | SPI2_NSS   | I2S2_WS   | I2C2_SMBA      | USART3_CK      | TIM1_BKIN      | CAN2_RX        | OTG_HS_ULPI_D5 | ETH_RMII_TXD0 | ETH_MII_TXD0 | OTG_HS_ID
+    {GPIOB, 13,   NULL, 0, NULL, ADCx}, // D29/PB13 | 52 | SPI2_SCK   | I2S2_CK   | USART3_CTS     | TIM1_CH1N      | CAN2_TX        | OTG_HS_ULPI_D6 | ETH_RMII_TXD1  | ETH_MII_TXD1
+    {GPIOB, 14,   NULL, 0, NULL, ADCx}, // D30/PB14 | 53 | SPI2_MISO  | TIM1_CH2N | TIM12_CH1      | OTG_HS_DM      | USART3_RTS     | TIM8_CH2N      | I2S2ext_SD
+    {GPIOB, 15,   NULL, 0, NULL, ADCx}, // D31/PB15 | 54 | SPI2_MOSI  | I2S2_SD   | TIM1_CH3N      | TIM8_CH3N      | TIM12_CH2      | OTG_HS_DP
+
+    {GPIOC,  0,   NULL, 0, ADC1,   10}, // D32/PC0  | 15 | OTG_HS_ULPI_STP                                                  | ADC123_IN10
+    {GPIOC,  1,   NULL, 0, ADC1,   11}, // D33/PC1  | 16 | ETH_MDC                                                          | ADC123_IN11
+    {GPIOC,  2,   NULL, 0, ADC1,   12}, // D34/PC2  | 17 | SPI2_MISO  | OTG_HS_ULPI_DIR  | ETH_MII_TXD2    | I2S2ext_SD     | ADC123_IN12
+    {GPIOC,  3,   NULL, 0, ADC1,   13}, // D35/PC3  | 18 | SPI2_MOSI  | I2S2_SD          | OTG_HS_ULPI_NXT | ETH_MII_TX_CLK | ADC123_IN13
+    {GPIOC,  4,   NULL, 0, ADC1,   14}, // D36/PC4  | 33 | ETH_RMII_RX_D0                | ETH_MII_RX_D0                    | ADC12_IN14
+    {GPIOC,  5,   NULL, 0, ADC1,   15}, // D37/PC5  | 34 | ETH_RMII_RX_D1                | ETH_MII_RX_D1                    | ADC12_IN15
+    {GPIOC,  6, TIMER8, 1, NULL, ADCx}, // D38/PC6  | 63 | I2S2_MCK   | TIM8_CH1/SDIO_D6 | USART6_TX       | DCMI_D0/TIM3_CH1 
+    {GPIOC,  7, TIMER8, 2, NULL, ADCx}, // D39/PC7  | 64 | I2S3_MCK   | TIM8_CH2/SDIO_D7 | USART6_RX       | DCMI_D1/TIM3_CH2
+    {GPIOC,  8, TIMER8, 3, NULL, ADCx}, // D40/PC8  | 65 | TIM8_CH3   | SDIO_D0          | TIM3_CH3        | USART6_CK      | DCMI_D2
+    {GPIOC,  9, TIMER8, 4, NULL, ADCx}, // D41/PC9  | 66 | I2S_CKIN   | MCO2             | TIM8_CH4        | SDIO_D1        | I2C3_SDA  | DCMI_D3    | TIM3_CH4
+    {GPIOC, 10,   NULL, 0, NULL, ADCx}, // D42/PC10 | 78 | SPI3_SCK   | I2S3_CK          | UART4_TX        | SDIO_D2        | DCMI_D8   | USART3_TX
+    {GPIOC, 11,   NULL, 0, NULL, ADCx}, // D43/PC11 | 79 | UART4_RX   | SPI3_MISO        | SDIO_D3         | DCMI_D4        | USART3_RX | I2S3ext_SD
+    {GPIOC, 12,   NULL, 0, NULL, ADCx}, // D44/PC12 | 80 | UART5_TX   | SDIO_CK          | DCMI_D9         | SPI3_MOSI      | I2S3_SD   | USART3_CK
+    {GPIOC, 13,   NULL, 0, NULL, ADCx}, // D45/PC13 |  7 | RTC_OUT, RTC_TAMP1, RTC_TS
+    {GPIOC, 14,   NULL, 0, NULL, ADCx}, // D46/PC14 |  8 | OSC32_IN
+    {GPIOC, 15,   NULL, 0, NULL, ADCx}, // D47/PC15 |  9 | OSC32_OUT
+                       
+    {GPIOD,  0,   NULL, 0, NULL, ADCx}, // D48/PD0  | 81 | FSMC_D2    | CAN1_RX
+    {GPIOD,  1,   NULL, 0, NULL, ADCx}, // D49/PD1  | 82 | FSMC_D3    | CAN1_TX
+    {GPIOD,  2,   NULL, 0, NULL, ADCx}, // D50/PD2  | 83 | TIM3_ETR   | UART5_RX   | SDIO_CMD | DCMI_D11
+    {GPIOD,  3,   NULL, 0, NULL, ADCx}, // D51/PD3  | 84 | FSMC_CLK   | USART2_CTS
+    {GPIOD,  4,   NULL, 0, NULL, ADCx}, // D52/PD4  | 85 | FSMC_NOE   | USART2_RTS
+    {GPIOD,  5,   NULL, 0, NULL, ADCx}, // D53/PD5  | 86 | FSMC_NWE   | USART2_TX
+    {GPIOD,  6,   NULL, 0, NULL, ADCx}, // D54/PD6  | 87 | FSMC_NWAIT | USART2_RX
+    {GPIOD,  7,   NULL, 0, NULL, ADCx}, // D55/PD7  | 88 | USART2_CK  | FSMC_NE1   | FSMC_NCE2
+    {GPIOD,  8,   NULL, 0, NULL, ADCx}, // D56/PD8  | 55 | FSMC_D13   | USART3_TX
+    {GPIOD,  9,   NULL, 0, NULL, ADCx}, // D57/PD9  | 56 | FSMC_D14   | USART3_RX
+    {GPIOD, 10,   NULL, 0, NULL, ADCx}, // D58/PD10 | 57 | FSMC_D15   | USART3_CK
+    {GPIOD, 11,   NULL, 0, NULL, ADCx}, // D59/PD11 | 58 | FSMC_CLE   | FSMC_A16   | USART3_CTS
+    {GPIOD, 12, TIMER4, 1, NULL, ADCx}, // D60/PD12 | 59 | FSMC_ALE   | FSMC_A17   | TIM4_CH1   | USART3_RTS // remap in
+    {GPIOD, 13, TIMER4, 2, NULL, ADCx}, // D61/PD13 | 60 | FSMC_A18                | TIM4_CH2                // remap in
+    {GPIOD, 14, TIMER4, 3, NULL, ADCx}, // D62/PD14 | 61 | FSMC_D0                 | TIM4_CH3                // remap in
+    {GPIOD, 15, TIMER4, 4, NULL, ADCx}, // D63/PD15 | 62 | FSMC_D1                 | TIM4_CH4                // remap in
+
+    {GPIOE,  0,   NULL, 0, NULL, ADCx}, // D64/PE0  | 97 | TIM4_ETR  | FSMC_NBL0 | DCMI_D2
+    {GPIOE,  1,   NULL, 0, NULL, ADCx}, // D65/PE1  | 98 | FSMC_NBL1 | DCMI_D3
+    {GPIOE,  2,   NULL, 0, NULL, ADCx}, // D66/PE2  |  1 | TRACECLK  | FSMC_A23  | ETH_MII_TXD3
+    {GPIOE,  3,   NULL, 0, NULL, ADCx}, // D67/PE3  |  2 | TRACED0   | FSMC_A19
+    {GPIOE,  4,   NULL, 0, NULL, ADCx}, // D68/PE4  |  3 | TRACED1   | FSMC_A20  | DCMI_D4
+    {GPIOE,  5,   NULL, 0, NULL, ADCx}, // D69/PE5  |  4 | TRACED2   | FSMC_A21  | TIM9_CH1     / DCMI_D6
+    {GPIOE,  6,   NULL, 0, NULL, ADCx}, // D70/PE6  |  5 | TRACED3   | FSMC_A22  | TIM9_CH2     / DCMI_D7
+    {GPIOE,  7,   NULL, 0, NULL, ADCx}, // D71/PE7  | 38 | FSMC_D4   | TIM1_ETR
+    {GPIOE,  8,   NULL, 0, NULL, ADCx}, // D72/PE8  | 39 | FSMC_D5   | TIM1_CH1N
+    {GPIOE,  9, TIMER1, 1, NULL, ADCx}, // D73/PE9  | 40 | FSMC_D6   | TIM1_CH1   // remap in
+    {GPIOE, 10,   NULL, 0, NULL, ADCx}, // D74/PE10 | 41 | FSMC_D7   | TIM1_CH2N
+    {GPIOE, 11, TIMER1, 2, NULL, ADCx}, // D75/PE11 | 42 | FSMC_D8   | TIM1_CH2   // remap in
+    {GPIOE, 12,   NULL, 0, NULL, ADCx}, // D76/PE12 | 43 | FSMC_D9   | TIM1_CH3N
+    {GPIOE, 13, TIMER1, 3, NULL, ADCx}, // D77/PE13 | 44 | FSMC_D10  | TIM1_CH3   // remap in
+    {GPIOE, 14, TIMER1, 4, NULL, ADCx}, // D78/PE14 | 45 | FSMC_D11  | TIM1_CH4   // remap in
+    {GPIOE, 15,   NULL, 0, NULL, ADCx}, // D79/PE15 | 46 | FSMC_D12  | TIM1_BKIN
+#if 0
+    {GPIOF,  0,   NULL, 0, NULL, ADCx}, // D80/PF0
+    {GPIOF,  1,   NULL, 0, NULL, ADCx}, // D81/PF1
+    {GPIOF,  2,   NULL, 0, NULL, ADCx}, // D82/PF2
+    {GPIOF,  3,   NULL, 0, NULL, ADCx}, // D83/PF3
+    {GPIOF,  4,   NULL, 0, NULL, ADCx}, // D84/PF4
+    {GPIOF,  5,   NULL, 0, NULL, ADCx}, // D85/PF5
+    {GPIOF,  6,   NULL, 0, NULL, ADCx}, // D86/PF6
+    {GPIOF,  7,   NULL, 0, NULL, ADCx}, // D87/PF7
+    {GPIOF,  8,   NULL, 0, NULL, ADCx}, // D88/PF8
+    {GPIOF,  9,   NULL, 0, NULL, ADCx}, // D89/PF9
+    {GPIOF, 10,   NULL, 0, NULL, ADCx}, // D90/PF10
+    {GPIOF, 11,   NULL, 0, NULL, ADCx}, // D91/PF11
+    {GPIOF, 12,   NULL, 0, NULL, ADCx}, // D92/PF12
+    {GPIOF, 13,   NULL, 0, NULL, ADCx}, // D93/PF13
+    {GPIOF, 14,   NULL, 0, NULL, ADCx}, // D94/PF14
+    {GPIOF, 15,   NULL, 0, NULL, ADCx}, // D95/PF15
+
+    {GPIOG,  0,   NULL, 0, NULL, ADCx}, // D96/PG0
+    {GPIOG,  1,   NULL, 0, NULL, ADCx}, // D97/PG1
+    {GPIOG,  2,   NULL, 0, NULL, ADCx}, // D98/PG2
+    {GPIOG,  3,   NULL, 0, NULL, ADCx}, // D99/PG3
+    {GPIOG,  4,   NULL, 0, NULL, ADCx}, // D100/PG4
+    {GPIOG,  5,   NULL, 0, NULL, ADCx}, // D101/PG5
+    {GPIOG,  6,   NULL, 0, NULL, ADCx}, // D102/PG6
+    {GPIOG,  7,   NULL, 0, NULL, ADCx}, // D103/PG7 
+    {GPIOG,  8,   NULL, 0, NULL, ADCx}, // D104/PG8
+    {GPIOG,  9,   NULL, 0, NULL, ADCx}, // D105/PG9
+    {GPIOG, 10,   NULL, 0, NULL, ADCx}, // D106/PG10
+    {GPIOG, 11,   NULL, 0, NULL, ADCx}, // D107/PG11
+    {GPIOG, 12,   NULL, 0, NULL, ADCx}, // D108/PG12
+    {GPIOG, 13,   NULL, 0, NULL, ADCx}, // D109/PG13
+    {GPIOG, 14,   NULL, 0, NULL, ADCx}, // D110/PG14
+    {GPIOG, 15,   NULL, 0, NULL, ADCx}  // D111/PG15
+#endif
+};
+/* to be defined
+extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
+    0, 1, 2, 3, 15, 16, 17, 19, 20, 21, 38, 39, 49, 41, 60, 61, 62, 63, 73, 75, 77, 78
+};
+*/
+extern const uint8 boardADCPins[BOARD_NR_ADC_PINS] __FLASH__ = {
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PB0, PB1, PC0, PC1, PC2, PC3, PC4, PC5
+};
+
+extern const uint8 boardUsedPins[BOARD_NR_USED_PINS] __FLASH__ = {
+    BOARD_LED_PIN, BOARD_LED2_PIN, BOARD_BUTTON1_PIN, BOARD_BUTTON2_PIN, BOARD_BUTTON2_PIN,
+	BOARD_JTMS_SWDIO_PIN, BOARD_JTCK_SWCLK_PIN,
+	FLASH_CS_PIN, FLASH_CLK_PIN, FLASH_DO_PIN, FLASH_DI_PIN,
+	NRF24_CE_PIN, NRF24_CS_PIN, NRF24_IRQ_PIN,
+	BOARD_SDIO_D0, BOARD_SDIO_D1, BOARD_SDIO_D2, BOARD_SDIO_D3, BOARD_SDIO_CK, BOARD_SDIO_CMD,
+	USB_DM_PIN, USB_DP_PIN
+};
+/*
+static void initSRAMChip(void) {
+    fsmc_nor_psram_reg_map *regs = FSMC_NOR_PSRAM1_BASE;
+
+    fsmc_sram_init_gpios();
+    rcc_clk_enable(RCC_FSMC);
+
+    regs->BCR = (FSMC_BCR_WREN | FSMC_BCR_MWID_16BITS | FSMC_BCR_MTYP_SRAM |
+                 FSMC_BCR_MBKEN);
+    fsmc_nor_psram_set_addset(regs, 0);
+    fsmc_nor_psram_set_datast(regs, 3);
+}
+*/
+#endif
diff --git a/STM32F4/variants/black_f407vet6/black_f4.h b/STM32F4/variants/black_f407vet6/black_f4.h
new file mode 100644
index 000000000..6f5d3dac7
--- /dev/null
+++ b/STM32F4/variants/black_f407vet6/black_f4.h
@@ -0,0 +1,130 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file   black_f4.h
+ * @author Marti Bolivar <mbolivar@leaflabs.com>
+ * @brief  Private include file for Maple Native in boards.h
+ *
+ * See maple.h for more information on these definitions.
+ */
+
+#ifndef _BOARD_BLACK_F4_H_
+#define _BOARD_BLACK_F4_H_
+
+#define Port2Pin(port, bit) ((port-'A')*16+bit)
+
+#define CYCLES_PER_MICROSECOND  168
+
+
+#undef  STM32_PCLK1
+#undef  STM32_PCLK2
+#define STM32_PCLK1   (CYCLES_PER_MICROSECOND*1000000/4)
+#define STM32_PCLK2   (CYCLES_PER_MICROSECOND*1000000/2)
+
+#define SYSTICK_RELOAD_VAL      (CYCLES_PER_MICROSECOND*1000-1)
+
+#define BOARD_USB_DM_PIN		PA11
+#define BOARD_USB_DP_PIN		PA12
+
+#define BOARD_LED_PIN           PA6 //Port2Pin('A', 6)
+#define BOARD_LED2_PIN          PA7 //Port2Pin('A', 7)
+#define BOARD_BUTTON1_PIN       PA0 //Port2Pin('A', 0)
+#define BOARD_BUTTON2_PIN       PE4 //Port2Pin('E', 4)
+#define BOARD_BUTTON3_PIN       PE3 //Port2Pin('E', 3)
+
+#define BOARD_NR_USARTS         5
+#define BOARD_USART1_TX_PIN     PA9  //Port2Pin('A', 9)
+#define BOARD_USART1_RX_PIN     PA10 //Port2Pin('A',10)
+#define BOARD_USART2_TX_PIN     PA2  //Port2Pin('A', 2)
+#define BOARD_USART2_RX_PIN     PA3  //Port2Pin('A', 3)
+#define BOARD_USART3_TX_PIN     PB10 //Port2Pin('B',10)
+#define BOARD_USART3_RX_PIN     PB11 //Port2Pin('B',11)
+#define BOARD_UART4_TX_PIN      PA0  //Port2Pin('A', 0)
+#define BOARD_UART4_RX_PIN      PA1  //Port2Pin('A', 1)
+#define BOARD_UART5_TX_PIN      PC12 //Port2Pin('C',12)
+#define BOARD_UART5_RX_PIN      PD2  //Port2Pin('D', 2)
+
+#define BOARD_NR_SPI            3
+#define BOARD_SPI1_NSS_PIN      PA4  //Port2Pin('A', 4)
+#define BOARD_SPI1_SCK_PIN      PA5  //Port2Pin('A', 5)
+#define BOARD_SPI1_MISO_PIN     PA6  //Port2Pin('A', 6)
+#define BOARD_SPI1_MOSI_PIN     PA7  //Port2Pin('A', 7)
+#define BOARD_SPI1A_NSS_PIN     PA15 //Port2Pin('A',15)
+#define BOARD_SPI1A_SCK_PIN     PB3  //Port2Pin('B', 3)
+#define BOARD_SPI1A_MISO_PIN    PB4  //Port2Pin('B', 4)
+#define BOARD_SPI1A_MOSI_PIN    PB5  //Port2Pin('B', 5)
+
+#define BOARD_SPI2_NSS_PIN      PB12 //Port2Pin('B',12)
+#define BOARD_SPI2_SCK_PIN      PB13 //Port2Pin('B',13)
+#define BOARD_SPI2_MISO_PIN     PB14 //Port2Pin('B',14)
+#define BOARD_SPI2_MOSI_PIN     PB15 //Port2Pin('B',15)
+#define BOARD_SPI2A_NSS_PIN     PB9  //Port2Pin('B', 9)
+#define BOARD_SPI2A_SCK_PIN     PB10 //Port2Pin('B',10)
+#define BOARD_SPI2A_MISO_PIN    PC2  //Port2Pin('C', 2)
+#define BOARD_SPI2A_MOSI_PIN    pc3  //Port2Pin('C', 3)
+
+#define BOARD_SPI3_NSS_PIN      PA15 //Port2Pin('A',15)
+#define BOARD_SPI3_SCK_PIN      PB3  //Port2Pin('B', 3)
+#define BOARD_SPI3_MISO_PIN     PB4  //Port2Pin('B', 4)
+#define BOARD_SPI3_MOSI_PIN     PB5  //Port2Pin('B', 5)
+/* overlap with the SDIO interface for SD card
+#define BOARD_SPI3A_NSS_PIN     Port2Pin('A', 4)
+#define BOARD_SPI3A_SCK_PIN     Port2Pin('C',10)
+#define BOARD_SPI3A_MISO_PIN    Port2Pin('C',11)
+#define BOARD_SPI3A_MOSI_PIN    Port2Pin('C',12)
+*/
+#define BOARD_SDIO_D0           PC8  //Port2Pin('C', 8)
+#define BOARD_SDIO_D1           PC9  //Port2Pin('C', 9)
+#define BOARD_SDIO_D2           PC10 //Port2Pin('C',10)
+#define BOARD_SDIO_D3           PC11 //Port2Pin('C',11)
+#define BOARD_SDIO_CK           PC12 //Port2Pin('C',12)
+#define BOARD_SDIO_CMD          PD2  //Port2Pin('D', 2)
+
+#define BOARD_NR_GPIO_PINS      80
+#define BOARD_NR_PWM_PINS       22
+#define BOARD_NR_ADC_PINS       16
+#define BOARD_NR_USED_PINS      22
+#define BOARD_JTMS_SWDIO_PIN    PA13 //Port2Pin('A',13)
+#define BOARD_JTCK_SWCLK_PIN    PA14 //Port2Pin('A',14)
+#define BOARD_JTDI_PIN          PA15 //Port2Pin('A',15)
+#define BOARD_JTDO_PIN          PB3  //Port2Pin('B', 3)
+#define BOARD_NJTRST_PIN        PB4  //Port2Pin('B', 4)
+
+
+enum {
+PA0,PA1,PA2,PA3,PA4,PA5,PA6,PA7,PA8,PA9,PA10,PA11,PA12,PA13,PA14,PA15,
+PB0,PB1,PB2,PB3,PB4,PB5,PB6,PB7,PB8,PB9,PB10,PB11,PB12,PB13,PB14,PB15,
+PC0,PC1,PC2,PC3,PC4,PC5,PC6,PC7,PC8,PC9,PC10,PC11,PC12,PC13,PC14,PC15,
+PD0,PD1,PD2,PD3,PD4,PD5,PD6,PD7,PD8,PD9,PD10,PD11,PD12,PD13,PD14,PD15,
+PE0,PE1,PE2,PE3,PE4,PE5,PE6,PE7,PE8,PE9,PE10,PE11,PE12,PE13,PE14,PE15,
+#if 0
+PF0,PF1,PF2,PF3,PF4,PF5,PF6,PF7,PF8,PF9,PF10,PF11,PF12,PF13,PF14,PF15,
+PG0,PG1,PG2,PG3,PG4,PG5,PG6,PG7,PG8,PG9,PG10,PG11,PG12,PG13,PG14,PG15
+#endif
+};
+
+#endif
diff --git a/STM32F4/variants/black_f407vet6/ld/common.inc b/STM32F4/variants/black_f407vet6/ld/common.inc
new file mode 100644
index 000000000..f5a0f5b6e
--- /dev/null
+++ b/STM32F4/variants/black_f407vet6/ld/common.inc
@@ -0,0 +1,219 @@
+/*
+ * Linker script for libmaple.
+ *
+ * Original author "lanchon" from ST forums, with modifications by LeafLabs.
+ */
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+
+/*
+ * Configure other libraries we want in the link.
+ *
+ * libgcc, libc, and libm are common across supported toolchains.
+ * However, some toolchains require additional archives which aren't
+ * present everywhere (e.g. ARM's gcc-arm-embedded releases).
+ *
+ * To hack around this, we let the build system specify additional
+ * archives by putting the right extra_libs.inc (in a directory under
+ * toolchains/) in our search path.
+ */
+GROUP(libgcc.a libc.a libm.a)
+INCLUDE extra_libs.inc
+
+/*
+ * These force the linker to search for vector table symbols.
+ *
+ * These symbols vary by STM32 family (and also within families).
+ * It's up to the build system to configure the link's search path
+ * properly for the target MCU.
+ */
+INCLUDE vector_symbols.inc
+
+/* STM32 vector table. */
+EXTERN(__stm32_vector_table)
+
+/* C runtime initialization function. */
+EXTERN(start_c)
+
+/* main entry point */
+EXTERN(main)
+
+/* Initial stack pointer value. */
+EXTERN(__msp_init)
+PROVIDE(__msp_init = ORIGIN(ram) + LENGTH(ram));
+
+/* Reset vector and chip reset entry point */
+EXTERN(__start__)
+ENTRY(__start__)
+PROVIDE(__exc_reset = __start__);
+
+/* Heap boundaries, for libmaple */
+EXTERN(_lm_heap_start);
+EXTERN(_lm_heap_end);
+
+SECTIONS
+{
+    .text :
+      {
+        __text_start__ = .;
+        /*
+         * STM32 vector table.  Leave this here.  Yes, really.
+         */
+        *(.stm32.interrupt_vector)
+
+        /*
+         * Program code and vague linking
+         */
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.plt)
+        *(.gnu.warning)
+        *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+        *(.gcc_except_table)
+        *(.eh_frame_hdr)
+        *(.eh_frame)
+
+        . = ALIGN(4);
+        KEEP(*(.init))
+
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+      } > REGION_TEXT
+
+    /*
+     * End of text
+     */
+    .text.align :
+      {
+        . = ALIGN(8);
+        __text_end__ = .;
+      } > REGION_TEXT
+
+    /*
+     * .ARM.exidx exception unwinding; mandated by ARM's C++ ABI
+     */
+    __exidx_start = .;
+    .ARM.exidx :
+      {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+      } > REGION_RODATA
+    __exidx_end = .;
+
+    /*
+     * .data
+     */
+    .data :
+      {
+        . = ALIGN(8);
+        __data_start__ = .;
+
+        *(.got.plt) *(.got)
+        *(.data .data.* .gnu.linkonce.d.*)
+
+        . = ALIGN(8);
+        __data_end__ = .;
+      } > REGION_DATA AT> REGION_RODATA
+
+    /*
+     * Read-only data
+     */
+    .rodata :
+      {
+        *(.rodata .rodata.* .gnu.linkonce.r.*)
+        /* .USER_FLASH: We allow users to allocate into Flash here */
+        *(.USER_FLASH)
+        /* ROM image configuration; for C startup */
+        . = ALIGN(4);
+        _lm_rom_img_cfgp = .;
+        LONG(LOADADDR(.data));
+        /*
+         * Heap: Linker scripts may choose a custom heap by overriding
+         * _lm_heap_start and _lm_heap_end. Otherwise, the heap is in
+         * internal SRAM, beginning after .bss, and growing towards
+         * the stack.
+         *
+         * I'm shoving these here naively; there's probably a cleaner way
+         * to go about this. [mbolivar]
+         */
+        _lm_heap_start = DEFINED(_lm_heap_start) ? _lm_heap_start : _end;
+        _lm_heap_end   = DEFINED(_lm_heap_end) ? _lm_heap_end : __msp_init;
+      } > REGION_RODATA
+
+    /*
+     * .bss
+     */
+    .bss :
+      {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss .bss.* .gnu.linkonce.b.*)
+        *(COMMON)
+        . = ALIGN (8);
+        __bss_end__ = .;
+        _end = __bss_end__;
+      } > REGION_BSS
+
+    /*
+     * Debugging sections
+     */
+    .stab 0 (NOLOAD) : { *(.stab) }
+    .stabstr 0 (NOLOAD) : { *(.stabstr) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+
+    .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+    .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+    /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/STM32F4/variants/black_f407vet6/ld/extra_libs.inc b/STM32F4/variants/black_f407vet6/ld/extra_libs.inc
new file mode 100644
index 000000000..dd2c84fa4
--- /dev/null
+++ b/STM32F4/variants/black_f407vet6/ld/extra_libs.inc
@@ -0,0 +1,7 @@
+/*
+ * Extra archives needed by ARM's GCC ARM Embedded arm-none-eabi-
+ * releases (https://launchpad.net/gcc-arm-embedded/).
+ */
+
+/* This is for the provided newlib. */
+GROUP(libnosys.a)
diff --git a/STM32F4/variants/black_f407vet6/ld/flash.ld b/STM32F4/variants/black_f407vet6/ld/flash.ld
new file mode 100644
index 000000000..c753a786c
--- /dev/null
+++ b/STM32F4/variants/black_f407vet6/ld/flash.ld
@@ -0,0 +1,20 @@
+/*
+ * Discovery F4 (STM32F407VGT6, high density) linker script for
+ * Flash builds.
+ */
+
+MEMORY
+{
+  ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 125K
+  rom (rx)  : ORIGIN = 0x08010000, LENGTH = 960K  /* ala42 */
+}
+
+/* GROUP(libcs4_stm32_high_density.a) */
+
+REGION_ALIAS("REGION_TEXT", rom);
+REGION_ALIAS("REGION_DATA", ram);
+REGION_ALIAS("REGION_BSS", ram);
+REGION_ALIAS("REGION_RODATA", rom);
+
+_FLASH_BUILD = 1;
+INCLUDE common.inc
diff --git a/STM32F4/variants/black_f407vet6/ld/jtag.ld b/STM32F4/variants/black_f407vet6/ld/jtag.ld
new file mode 100644
index 000000000..fe70f68dc
--- /dev/null
+++ b/STM32F4/variants/black_f407vet6/ld/jtag.ld
@@ -0,0 +1,20 @@
+/*
+ * STM32F4xx high density linker script for
+ * JTAG (bare metal, no bootloader) builds.
+ */
+
+MEMORY
+{
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+  rom (rx)  : ORIGIN = 0x08000000, LENGTH = 512K
+}
+
+/* GROUP(libcs3_stm32_high_density.a) */
+
+REGION_ALIAS("REGION_TEXT", rom);
+REGION_ALIAS("REGION_DATA", ram);
+REGION_ALIAS("REGION_BSS", ram);
+REGION_ALIAS("REGION_RODATA", rom);
+
+_FLASH_BUILD = 1;
+INCLUDE common.inc
diff --git a/STM32F4/variants/black_f407vet6/ld/names.inc b/STM32F4/variants/black_f407vet6/ld/names.inc
new file mode 100644
index 000000000..6d7ff6e94
--- /dev/null
+++ b/STM32F4/variants/black_f407vet6/ld/names.inc
@@ -0,0 +1,78 @@
+EXTERN(__cs3_stack)
+EXTERN(__cs3_reset)
+EXTERN(__exc_nmi)
+EXTERN(__exc_hardfault)
+EXTERN(__exc_memmanage)
+EXTERN(__exc_busfault)
+EXTERN(__exc_usagefault)
+EXTERN(__stm32reservedexception7)
+EXTERN(__stm32reservedexception8)
+EXTERN(__stm32reservedexception9)
+EXTERN(__stm32reservedexception10)
+EXTERN(__exc_svc)
+EXTERN(__exc_debug_monitor)
+EXTERN(__stm32reservedexception13)
+EXTERN(__exc_pendsv)
+EXTERN(__exc_systick)
+
+EXTERN(__irq_wwdg)
+EXTERN(__irq_pvd)
+EXTERN(__irq_tamper)
+EXTERN(__irq_rtc)
+EXTERN(__irq_flash)
+EXTERN(__irq_rcc)
+EXTERN(__irq_exti0)
+EXTERN(__irq_exti1)
+EXTERN(__irq_exti2)
+EXTERN(__irq_exti3)
+EXTERN(__irq_exti4)
+EXTERN(__irq_dma1_channel1)
+EXTERN(__irq_dma1_channel2)
+EXTERN(__irq_dma1_channel3)
+EXTERN(__irq_dma1_channel4)
+EXTERN(__irq_dma1_channel5)
+EXTERN(__irq_dma1_channel6)
+EXTERN(__irq_dma1_channel7)
+EXTERN(__irq_adc)
+EXTERN(__irq_usb_hp_can_tx)
+EXTERN(__irq_usb_lp_can_rx0)
+EXTERN(__irq_can_rx1)
+EXTERN(__irq_can_sce)
+EXTERN(__irq_exti9_5)
+EXTERN(__irq_tim1_brk)
+EXTERN(__irq_tim1_up)
+EXTERN(__irq_tim1_trg_com)
+EXTERN(__irq_tim1_cc)
+EXTERN(__irq_tim2)
+EXTERN(__irq_tim3)
+EXTERN(__irq_tim4)
+EXTERN(__irq_i2c1_ev)
+EXTERN(__irq_i2c1_er)
+EXTERN(__irq_i2c2_ev)
+EXTERN(__irq_i2c2_er)
+EXTERN(__irq_spi1)
+EXTERN(__irq_spi2)
+EXTERN(__irq_usart1)
+EXTERN(__irq_usart2)
+EXTERN(__irq_usart3)
+EXTERN(__irq_exti15_10)
+EXTERN(__irq_rtcalarm)
+EXTERN(__irq_usbwakeup)
+
+EXTERN(__irq_tim8_brk)
+EXTERN(__irq_tim8_up)
+EXTERN(__irq_tim8_trg_com)
+EXTERN(__irq_tim8_cc)
+EXTERN(__irq_adc3)
+EXTERN(__irq_fsmc)
+EXTERN(__irq_sdio)
+EXTERN(__irq_tim5)
+EXTERN(__irq_spi3)
+EXTERN(__irq_uart4)
+EXTERN(__irq_uart5)
+EXTERN(__irq_tim6)
+EXTERN(__irq_tim7)
+EXTERN(__irq_dma2_channel1)
+EXTERN(__irq_dma2_channel2)
+EXTERN(__irq_dma2_channel3)
+EXTERN(__irq_dma2_channel4_5)
diff --git a/STM32F4/variants/black_f407vet6/ld/ram.ld b/STM32F4/variants/black_f407vet6/ld/ram.ld
new file mode 100644
index 000000000..b57060c92
--- /dev/null
+++ b/STM32F4/variants/black_f407vet6/ld/ram.ld
@@ -0,0 +1,19 @@
+/*
+ * aeroquad32 (STM32F103VET6, high density) linker script for
+ * RAM builds.
+ */
+
+MEMORY
+{
+  ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 61K
+  rom (rx)  : ORIGIN = 0x08010000, LENGTH = 0K  /* ala42 */
+}
+
+GROUP(libcs3_stm32_high_density.a)
+
+REGION_ALIAS("REGION_TEXT", ram);
+REGION_ALIAS("REGION_DATA", ram);
+REGION_ALIAS("REGION_BSS", ram);
+REGION_ALIAS("REGION_RODATA", ram);
+
+INCLUDE common.inc
diff --git a/STM32F4/variants/black_f407vet6/ld/vector_symbols.inc b/STM32F4/variants/black_f407vet6/ld/vector_symbols.inc
new file mode 100644
index 000000000..f8519bba4
--- /dev/null
+++ b/STM32F4/variants/black_f407vet6/ld/vector_symbols.inc
@@ -0,0 +1,78 @@
+EXTERN(__msp_init)
+EXTERN(__exc_reset)
+EXTERN(__exc_nmi)
+EXTERN(__exc_hardfault)
+EXTERN(__exc_memmanage)
+EXTERN(__exc_busfault)
+EXTERN(__exc_usagefault)
+EXTERN(__stm32reservedexception7)
+EXTERN(__stm32reservedexception8)
+EXTERN(__stm32reservedexception9)
+EXTERN(__stm32reservedexception10)
+EXTERN(__exc_svc)
+EXTERN(__exc_debug_monitor)
+EXTERN(__stm32reservedexception13)
+EXTERN(__exc_pendsv)
+EXTERN(__exc_systick)
+
+EXTERN(__irq_wwdg)
+EXTERN(__irq_pvd)
+EXTERN(__irq_tamper)
+EXTERN(__irq_rtc)
+EXTERN(__irq_flash)
+EXTERN(__irq_rcc)
+EXTERN(__irq_exti0)
+EXTERN(__irq_exti1)
+EXTERN(__irq_exti2)
+EXTERN(__irq_exti3)
+EXTERN(__irq_exti4)
+EXTERN(__irq_dma1_channel1)
+EXTERN(__irq_dma1_channel2)
+EXTERN(__irq_dma1_channel3)
+EXTERN(__irq_dma1_channel4)
+EXTERN(__irq_dma1_channel5)
+EXTERN(__irq_dma1_channel6)
+EXTERN(__irq_dma1_channel7)
+EXTERN(__irq_adc)
+EXTERN(__irq_usb_hp_can_tx)
+EXTERN(__irq_usb_lp_can_rx0)
+EXTERN(__irq_can_rx1)
+EXTERN(__irq_can_sce)
+EXTERN(__irq_exti9_5)
+EXTERN(__irq_tim1_brk)
+EXTERN(__irq_tim1_up)
+EXTERN(__irq_tim1_trg_com)
+EXTERN(__irq_tim1_cc)
+EXTERN(__irq_tim2)
+EXTERN(__irq_tim3)
+EXTERN(__irq_tim4)
+EXTERN(__irq_i2c1_ev)
+EXTERN(__irq_i2c1_er)
+EXTERN(__irq_i2c2_ev)
+EXTERN(__irq_i2c2_er)
+EXTERN(__irq_spi1)
+EXTERN(__irq_spi2)
+EXTERN(__irq_usart1)
+EXTERN(__irq_usart2)
+EXTERN(__irq_usart3)
+EXTERN(__irq_exti15_10)
+EXTERN(__irq_rtcalarm)
+EXTERN(__irq_usbwakeup)
+
+EXTERN(__irq_tim8_brk)
+EXTERN(__irq_tim8_up)
+EXTERN(__irq_tim8_trg_com)
+EXTERN(__irq_tim8_cc)
+EXTERN(__irq_adc3)
+EXTERN(__irq_fsmc)
+EXTERN(__irq_sdio)
+EXTERN(__irq_tim5)
+EXTERN(__irq_spi3)
+EXTERN(__irq_uart4)
+EXTERN(__irq_uart5)
+EXTERN(__irq_tim6)
+EXTERN(__irq_tim7)
+EXTERN(__irq_dma2_channel1)
+EXTERN(__irq_dma2_channel2)
+EXTERN(__irq_dma2_channel3)
+EXTERN(__irq_dma2_channel4_5)
diff --git a/STM32F4/variants/black_f407vet6/pins_arduino.h b/STM32F4/variants/black_f407vet6/pins_arduino.h
new file mode 100644
index 000000000..3052f2eb2
--- /dev/null
+++ b/STM32F4/variants/black_f407vet6/pins_arduino.h
@@ -0,0 +1,6 @@
+
+
+
+
+// API compatibility
+#include "variant.h"
\ No newline at end of file
diff --git a/STM32F4/variants/black_f407vet6/stm32_isrs.S b/STM32F4/variants/black_f407vet6/stm32_isrs.S
new file mode 100644
index 000000000..34e515c08
--- /dev/null
+++ b/STM32F4/variants/black_f407vet6/stm32_isrs.S
@@ -0,0 +1,323 @@
+/* STM32 ISR weak declarations */
+
+	.thumb
+
+/* Default handler for all non-overridden interrupts and exceptions */
+	.globl	__default_handler
+	.type	__default_handler, %function
+
+__default_handler:
+	b .
+
+	.weak	__exc_nmi
+	.globl	__exc_nmi
+	.set	__exc_nmi, __default_handler
+	.weak	__exc_hardfault
+	.globl	__exc_hardfault
+	.set	__exc_hardfault, __default_handler
+	.weak	__exc_memmanage
+	.globl	__exc_memmanage
+	.set	__exc_memmanage, __default_handler
+	.weak	__exc_busfault
+	.globl	__exc_busfault
+	.set	__exc_busfault, __default_handler
+	.weak	__exc_usagefault
+	.globl	__exc_usagefault
+	.set	__exc_usagefault, __default_handler
+	.weak	__stm32reservedexception7
+	.globl	__stm32reservedexception7
+	.set	__stm32reservedexception7, __default_handler
+	.weak	__stm32reservedexception8
+	.globl	__stm32reservedexception8
+	.set	__stm32reservedexception8, __default_handler
+	.weak	__stm32reservedexception9
+	.globl	__stm32reservedexception9
+	.set	__stm32reservedexception9, __default_handler
+	.weak	__stm32reservedexception10
+	.globl	__stm32reservedexception10
+	.set	__stm32reservedexception10, __default_handler
+	.weak	__exc_svc
+	.globl	__exc_svc
+	.set	__exc_svc, __default_handler
+	.weak	__exc_debug_monitor
+	.globl	__exc_debug_monitor
+	.set	__exc_debug_monitor, __default_handler
+	.weak	__stm32reservedexception13
+	.globl	__stm32reservedexception13
+	.set	__stm32reservedexception13, __default_handler
+	.weak	__exc_pendsv
+	.globl	__exc_pendsv
+	.set	__exc_pendsv, __default_handler
+	.weak	__exc_systick
+	.globl	__exc_systick
+	.set	__exc_systick, __default_handler
+	.weak	__irq_wwdg
+	.globl	__irq_wwdg
+	.set	__irq_wwdg, __default_handler
+	.weak	__irq_pvd
+	.globl	__irq_pvd
+	.set	__irq_pvd, __default_handler
+	.weak	__irq_tamper
+	.globl	__irq_tamper
+	.set	__irq_tamper, __default_handler
+	.weak	__irq_rtc
+	.globl	__irq_rtc
+	.set	__irq_rtc, __default_handler
+	.weak	__irq_flash
+	.globl	__irq_flash
+	.set	__irq_flash, __default_handler
+	.weak	__irq_rcc
+	.globl	__irq_rcc
+	.set	__irq_rcc, __default_handler
+	.weak	__irq_exti0
+	.globl	__irq_exti0
+	.set	__irq_exti0, __default_handler
+	.weak	__irq_exti1
+	.globl	__irq_exti1
+	.set	__irq_exti1, __default_handler
+	.weak	__irq_exti2
+	.globl	__irq_exti2
+	.set	__irq_exti2, __default_handler
+	.weak	__irq_exti3
+	.globl	__irq_exti3
+	.set	__irq_exti3, __default_handler
+	.weak	__irq_exti4
+	.globl	__irq_exti4
+	.set	__irq_exti4, __default_handler
+	.weak	__irq_dma1_channel1
+	.globl	__irq_dma1_channel1
+	.set	__irq_dma1_channel1, __default_handler
+	.weak	__irq_dma1_channel2
+	.globl	__irq_dma1_channel2
+	.set	__irq_dma1_channel2, __default_handler
+	.weak	__irq_dma1_channel3
+	.globl	__irq_dma1_channel3
+	.set	__irq_dma1_channel3, __default_handler
+	.weak	__irq_dma1_channel4
+	.globl	__irq_dma1_channel4
+	.set	__irq_dma1_channel4, __default_handler
+	.weak	__irq_dma1_channel5
+	.globl	__irq_dma1_channel5
+	.set	__irq_dma1_channel5, __default_handler
+	.weak	__irq_dma1_channel6
+	.globl	__irq_dma1_channel6
+	.set	__irq_dma1_channel6, __default_handler
+	.weak	__irq_dma1_channel7
+	.globl	__irq_dma1_channel7
+	.set	__irq_dma1_channel7, __default_handler
+	.weak	__irq_adc
+	.globl	__irq_adc
+	.set	__irq_adc, __default_handler
+	.weak	__irq_usb_hp_can_tx
+	.globl	__irq_usb_hp_can_tx
+	.set	__irq_usb_hp_can_tx, __default_handler
+	.weak	__irq_usb_lp_can_rx0
+	.globl	__irq_usb_lp_can_rx0
+	.set	__irq_usb_lp_can_rx0, __default_handler
+	.weak	__irq_can_rx1
+	.globl	__irq_can_rx1
+	.set	__irq_can_rx1, __default_handler
+	.weak	__irq_can_sce
+	.globl	__irq_can_sce
+	.set	__irq_can_sce, __default_handler
+	.weak	__irq_exti9_5
+	.globl	__irq_exti9_5
+	.set	__irq_exti9_5, __default_handler
+	.weak	__irq_tim1_brk
+	.globl	__irq_tim1_brk
+	.set	__irq_tim1_brk, __default_handler
+	.weak	__irq_tim1_up
+	.globl	__irq_tim1_up
+	.set	__irq_tim1_up, __default_handler
+	.weak	__irq_tim1_trg_com
+	.globl	__irq_tim1_trg_com
+	.set	__irq_tim1_trg_com, __default_handler
+	.weak	__irq_tim1_cc
+	.globl	__irq_tim1_cc
+	.set	__irq_tim1_cc, __default_handler
+	.weak	__irq_tim2
+	.globl	__irq_tim2
+	.set	__irq_tim2, __default_handler
+	.weak	__irq_tim3
+	.globl	__irq_tim3
+	.set	__irq_tim3, __default_handler
+	.weak	__irq_tim4
+	.globl	__irq_tim4
+	.set	__irq_tim4, __default_handler
+	.weak	__irq_i2c1_ev
+	.globl	__irq_i2c1_ev
+	.set	__irq_i2c1_ev, __default_handler
+	.weak	__irq_i2c1_er
+	.globl	__irq_i2c1_er
+	.set	__irq_i2c1_er, __default_handler
+	.weak	__irq_i2c2_ev
+	.globl	__irq_i2c2_ev
+	.set	__irq_i2c2_ev, __default_handler
+	.weak	__irq_i2c2_er
+	.globl	__irq_i2c2_er
+	.set	__irq_i2c2_er, __default_handler
+	.weak	__irq_spi1
+	.globl	__irq_spi1
+	.set	__irq_spi1, __default_handler
+	.weak	__irq_spi2
+	.globl	__irq_spi2
+	.set	__irq_spi2, __default_handler
+	.weak	__irq_usart1
+	.globl	__irq_usart1
+	.set	__irq_usart1, __default_handler
+	.weak	__irq_usart2
+	.globl	__irq_usart2
+	.set	__irq_usart2, __default_handler
+	.weak	__irq_usart3
+	.globl	__irq_usart3
+	.set	__irq_usart3, __default_handler
+	.weak	__irq_exti15_10
+	.globl	__irq_exti15_10
+	.set	__irq_exti15_10, __default_handler
+	.weak	__irq_rtcalarm
+	.globl	__irq_rtcalarm
+	.set	__irq_rtcalarm, __default_handler
+	.weak	__irq_usbwakeup
+	.globl	__irq_usbwakeup
+	.set	__irq_usbwakeup, __default_handler
+#if defined (STM32_HIGH_DENSITY)
+	.weak	__irq_tim8_brk
+	.globl	__irq_tim8_brk
+	.set	__irq_tim8_brk, __default_handler
+	.weak	__irq_tim8_up
+	.globl	__irq_tim8_up
+	.set	__irq_tim8_up, __default_handler
+	.weak	__irq_tim8_trg_com
+	.globl	__irq_tim8_trg_com
+	.set	__irq_tim8_trg_com, __default_handler
+	.weak	__irq_tim8_cc
+	.globl	__irq_tim8_cc
+	.set	__irq_tim8_cc, __default_handler
+	.weak	__irq_adc3
+	.globl	__irq_adc3
+	.set	__irq_adc3, __default_handler
+	.weak	__irq_fsmc
+	.globl	__irq_fsmc
+	.set	__irq_fsmc, __default_handler
+	.weak	__irq_sdio
+	.globl	__irq_sdio
+	.set	__irq_sdio, __default_handler
+	.weak	__irq_tim5
+	.globl	__irq_tim5
+	.set	__irq_tim5, __default_handler
+	.weak	__irq_spi3
+	.globl	__irq_spi3
+	.set	__irq_spi3, __default_handler
+	.weak	__irq_uart4
+	.globl	__irq_uart4
+	.set	__irq_uart4, __default_handler
+	.weak	__irq_uart5
+	.globl	__irq_uart5
+	.set	__irq_uart5, __default_handler
+	.weak	__irq_tim6
+	.globl	__irq_tim6
+	.set	__irq_tim6, __default_handler
+	.weak	__irq_tim7
+	.globl	__irq_tim7
+	.set	__irq_tim7, __default_handler
+	.weak	__irq_dma2_channel1
+	.globl	__irq_dma2_channel1
+	.set	__irq_dma2_channel1, __default_handler
+	.weak	__irq_dma2_channel2
+	.globl	__irq_dma2_channel2
+	.set	__irq_dma2_channel2, __default_handler
+	.weak	__irq_dma2_channel3
+	.globl	__irq_dma2_channel3
+	.set	__irq_dma2_channel3, __default_handler
+	.weak	__irq_dma2_channel4_5
+	.globl	__irq_dma2_channel4_5
+	.set	__irq_dma2_channel4_5, __default_handler
+#endif /* STM32_HIGH_DENSITY */
+
+	.weak	__irq_DMA2_Stream4_IRQHandler              
+	.globl	__irq_DMA2_Stream4_IRQHandler              
+	.set	__irq_DMA2_Stream4_IRQHandler, __default_handler
+
+  .weak	__irq_ETH_IRQHandler                       
+  .globl	__irq_ETH_IRQHandler                       
+  .set	__irq_ETH_IRQHandler, __default_handler
+
+  .weak	__irq_ETH_WKUP_IRQHandler                         
+  .globl	__irq_ETH_WKUP_IRQHandler                         
+  .set	__irq_ETH_WKUP_IRQHandler, __default_handler  
+
+  .weak	__irq_CAN2_TX_IRQHandler                          
+  .globl	__irq_CAN2_TX_IRQHandler                          
+  .set	__irq_CAN2_TX_IRQHandler, __default_handler    
+
+  .weak	__irq_CAN2_RX0_IRQHandler                         
+  .globl	__irq_CAN2_RX0_IRQHandler                         
+  .set	__irq_CAN2_RX0_IRQHandler, __default_handler      
+
+  .weak	__irq_CAN2_RX1_IRQHandler                         
+  .globl	__irq_CAN2_RX1_IRQHandler                         
+  .set	__irq_CAN2_RX1_IRQHandler, __default_handler        
+
+  .weak	__irq_CAN2_SCE_IRQHandler                         
+  .globl	__irq_CAN2_SCE_IRQHandler                         
+  .set	__irq_CAN2_SCE_IRQHandler, __default_handler          
+
+  .weak	__irq_OTG_FS_IRQHandler                    
+  .globl	__irq_OTG_FS_IRQHandler                    
+  .set	__irq_OTG_FS_IRQHandler, __default_handler            
+
+  .weak	__irq_DMA2_Stream5_IRQHandler              
+  .globl	__irq_DMA2_Stream5_IRQHandler              
+  .set	__irq_DMA2_Stream5_IRQHandler, __default_handler              
+
+  .weak	__irq_DMA2_Stream6_IRQHandler              
+  .globl	__irq_DMA2_Stream6_IRQHandler              
+  .set	__irq_DMA2_Stream6_IRQHandler, __default_handler                
+
+  .weak	__irq_DMA2_Stream7_IRQHandler              
+  .globl	__irq_DMA2_Stream7_IRQHandler              
+  .set	__irq_DMA2_Stream7_IRQHandler, __default_handler                  
+
+  .weak	__irq_USART6_IRQHandler                     
+  .globl	__irq_USART6_IRQHandler                     
+  .set	__irq_USART6_IRQHandler, __default_handler                    
+
+  .weak	__irq_I2C3_EV_IRQHandler                          
+  .globl	__irq_I2C3_EV_IRQHandler                          
+  .set	__irq_I2C3_EV_IRQHandler, __default_handler                      
+
+  .weak	__irq_I2C3_ER_IRQHandler                          
+  .globl	__irq_I2C3_ER_IRQHandler                          
+  .set	__irq_I2C3_ER_IRQHandler, __default_handler                        
+
+  .weak	__irq_OTG_HS_EP1_OUT_IRQHandler              
+  .globl	__irq_OTG_HS_EP1_OUT_IRQHandler              
+  .set	__irq_OTG_HS_EP1_OUT_IRQHandler, __default_handler                          
+
+  .weak	__irq_OTG_HS_EP1_IN_IRQHandler              
+  .globl	__irq_OTG_HS_EP1_IN_IRQHandler              
+  .set	__irq_OTG_HS_EP1_IN_IRQHandler, __default_handler                            
+
+  .weak	__irq_OTG_HS_WKUP_IRQHandler                       
+  .globl	__irq_OTG_HS_WKUP_IRQHandler                       
+  .set	__irq_OTG_HS_WKUP_IRQHandler, __default_handler                              
+
+  .weak	__irq_OTG_HS_IRQHandler                    
+  .globl	__irq_OTG_HS_IRQHandler                    
+  .set	__irq_OTG_HS_IRQHandler, __default_handler                                
+
+  .weak	__irq_DCMI_IRQHandler                      
+  .globl	__irq_DCMI_IRQHandler                      
+  .set	__irq_DCMI_IRQHandler, __default_handler                                  
+
+  .weak	__irq_CRYP_IRQHandler                      
+  .globl	__irq_CRYP_IRQHandler                      
+  .set	__irq_CRYP_IRQHandler, __default_handler                                    
+
+  .weak	__irq_HASH_RNG_IRQHandler    
+  .globl	__irq_HASH_RNG_IRQHandler    
+  .set	__irq_HASH_RNG_IRQHandler, __default_handler                                      
+
+  .weak	__irq_FPU_IRQHandler         
+  .globl	__irq_FPU_IRQHandler         
+  .set	__irq_FPU_IRQHandler, __default_handler                                        
diff --git a/STM32F4/variants/black_f407vet6/stm32_vector_table.S b/STM32F4/variants/black_f407vet6/stm32_vector_table.S
new file mode 100644
index 000000000..9f08d6669
--- /dev/null
+++ b/STM32F4/variants/black_f407vet6/stm32_vector_table.S
@@ -0,0 +1,113 @@
+/* STM32 vector table */
+
+	.section	".stm32.interrupt_vector"
+
+	.globl	__stm32_vector_table
+	.type	__stm32_vector_table, %object
+
+__stm32_vector_table:
+/* CM3 core interrupts */
+	.long	__msp_init
+	.long	__exc_reset
+	.long	__exc_nmi
+	.long	__exc_hardfault
+	.long	__exc_memmanage
+	.long	__exc_busfault
+	.long	__exc_usagefault
+	.long	__stm32reservedexception7
+	.long	__stm32reservedexception8
+	.long	__stm32reservedexception9
+	.long	__stm32reservedexception10
+	.long	__exc_svc
+	.long	__exc_debug_monitor
+	.long	__stm32reservedexception13
+	.long	__exc_pendsv
+	.long	__exc_systick
+/* Peripheral interrupts */
+	.long	__irq_wwdg
+	.long	__irq_pvd
+	.long	__irq_tamper
+	.long	__irq_rtc
+	.long	__irq_flash
+	.long	__irq_rcc
+	.long	__irq_exti0
+	.long	__irq_exti1
+	.long	__irq_exti2
+	.long	__irq_exti3
+	.long	__irq_exti4
+	.long	__irq_dma1_channel1
+	.long	__irq_dma1_channel2
+	.long	__irq_dma1_channel3
+	.long	__irq_dma1_channel4
+	.long	__irq_dma1_channel5
+	.long	__irq_dma1_channel6
+	.long	__irq_dma1_channel7
+	.long	__irq_adc
+	.long	__irq_usb_hp_can_tx
+	.long	__irq_usb_lp_can_rx0
+	.long	__irq_can_rx1
+	.long	__irq_can_sce
+	.long	__irq_exti9_5
+	.long	__irq_tim1_brk
+	.long	__irq_tim1_up
+	.long	__irq_tim1_trg_com
+	.long	__irq_tim1_cc
+	.long	__irq_tim2
+	.long	__irq_tim3
+	.long	__irq_tim4
+	.long	__irq_i2c1_ev
+	.long	__irq_i2c1_er
+	.long	__irq_i2c2_ev
+	.long	__irq_i2c2_er
+	.long	__irq_spi1
+	.long	__irq_spi2
+	.long	__irq_usart1
+	.long	__irq_usart2
+	.long	__irq_usart3
+	.long	__irq_exti15_10
+	.long	__irq_rtcalarm
+	.long	__irq_usbwakeup
+#if defined (STM32_HIGH_DENSITY)
+	.long	__irq_tim8_brk
+	.long	__irq_tim8_up
+	.long	__irq_tim8_trg_com
+	.long	__irq_tim8_cc
+	.long	__irq_adc3
+	.long	__irq_fsmc
+	.long	__irq_sdio
+	.long	__irq_tim5
+	.long	__irq_spi3
+	.long	__irq_uart4
+	.long	__irq_uart5
+	.long	__irq_tim6
+	.long	__irq_tim7
+	.long	__irq_dma2_channel1
+	.long	__irq_dma2_channel2
+	.long	__irq_dma2_channel3
+	.long	__irq_dma2_channel4_5
+#endif /* STM32_HIGH_DENSITY */
+
+  .long	__irq_DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */                   
+  .long	__irq_ETH_IRQHandler                    /* Ethernet                     */                   
+  .long	__irq_ETH_WKUP_IRQHandler               /* Ethernet Wakeup through EXTI line */                     
+  .long	__irq_CAN2_TX_IRQHandler                /* CAN2 TX                      */                          
+  .long	__irq_CAN2_RX0_IRQHandler               /* CAN2 RX0                     */                          
+  .long	__irq_CAN2_RX1_IRQHandler               /* CAN2 RX1                     */                          
+  .long	__irq_CAN2_SCE_IRQHandler               /* CAN2 SCE                     */                          
+  .long	__irq_OTG_FS_IRQHandler                 /* USB OTG FS                   */                   
+  .long	__irq_DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */                   
+  .long	__irq_DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */                   
+  .long	__irq_DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */                   
+  .long	__irq_USART6_IRQHandler                 /* USART6                       */                    
+  .long	__irq_I2C3_EV_IRQHandler                /* I2C3 event                   */                          
+  .long	__irq_I2C3_ER_IRQHandler                /* I2C3 error                   */                          
+  .long	__irq_OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */                   
+  .long	__irq_OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */                   
+  .long	__irq_OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */                         
+  .long	__irq_OTG_HS_IRQHandler                 /* USB OTG HS                   */                   
+  .long	__irq_DCMI_IRQHandler                   /* DCMI                         */                   
+  .long	__irq_CRYP_IRQHandler                   /* CRYP crypto                  */                   
+  .long	__irq_HASH_RNG_IRQHandler               /* Hash and Rng                 */
+  .long	__irq_FPU_IRQHandler                    /* FPU                          */
+
+	.size	__stm32_vector_table, . - __stm32_vector_table
diff --git a/STM32F4/variants/black_f407vet6/variant.h b/STM32F4/variants/black_f407vet6/variant.h
new file mode 100644
index 000000000..cd0a96de4
--- /dev/null
+++ b/STM32F4/variants/black_f407vet6/variant.h
@@ -0,0 +1,21 @@
+#ifndef _VARIANT_ARDUINO_STM32_
+#define _VARIANT_ARDUINO_STM32_
+
+
+#define digitalPinToPort(P)        ( PIN_MAP[P].gpio_device )
+#define digitalPinToBitMask(P)     ( BIT(PIN_MAP[P].gpio_bit) )
+#define portOutputRegister(port)   ( &(port->regs->ODR) )
+#define portInputRegister(port)    ( &(port->regs->IDR) )
+
+#define portSetRegister(pin)		( &(PIN_MAP[pin].gpio_device->regs->BSRR) )
+#define portClearRegister(pin)		( &(PIN_MAP[pin].gpio_device->regs->BRR) )
+
+#define portConfigRegister(pin)		( &(PIN_MAP[pin].gpio_device->regs->CRL) )
+
+static const uint8_t SS   = BOARD_SPI1_NSS_PIN;
+static const uint8_t SS1  = BOARD_SPI2_NSS_PIN;
+static const uint8_t MOSI = BOARD_SPI1_MOSI_PIN;
+static const uint8_t MISO = BOARD_SPI1_MISO_PIN;
+static const uint8_t SCK  = BOARD_SPI1_SCK_PIN;
+
+#endif /* _VARIANT_ARDUINO_STM32_ */
\ No newline at end of file
diff --git a/STM32F4/variants/black_f407vet6/wirish/start.S b/STM32F4/variants/black_f407vet6/wirish/start.S
new file mode 100644
index 000000000..8b181aa99
--- /dev/null
+++ b/STM32F4/variants/black_f407vet6/wirish/start.S
@@ -0,0 +1,57 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/*
+ * This file is a modified version of a file obtained from
+ * CodeSourcery Inc. (now part of Mentor Graphics Corp.), in which the
+ * following text appeared:
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+        .text
+        .code 16
+        .thumb_func
+
+        .globl __start__
+        .type __start__, %function
+__start__:
+        .fnstart
+        ldr r1,=__msp_init
+        mov sp,r1
+        ldr r1,=start_c
+        bx r1
+        .pool
+        .cantunwind
+        .fnend
diff --git a/STM32F4/variants/black_f407vet6/wirish/start_c.c b/STM32F4/variants/black_f407vet6/wirish/start_c.c
new file mode 100644
index 000000000..655fefb88
--- /dev/null
+++ b/STM32F4/variants/black_f407vet6/wirish/start_c.c
@@ -0,0 +1,95 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/*
+ * This file is a modified version of a file obtained from
+ * CodeSourcery Inc. (now part of Mentor Graphics Corp.), in which the
+ * following text appeared:
+ *
+ * Copyright (c) 2006, 2007 CodeSourcery Inc
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+#include <stddef.h>
+
+extern void __libc_init_array(void);
+
+extern int main(int, char**, char**);
+
+extern void exit(int) __attribute__((noreturn, weak));
+
+/* The linker must ensure that these are at least 4-byte aligned. */
+extern char __data_start__, __data_end__;
+extern char __bss_start__, __bss_end__;
+
+struct rom_img_cfg {
+    int *img_start;
+};
+
+extern char _lm_rom_img_cfgp;
+
+void __attribute__((noreturn)) start_c(void) {
+    struct rom_img_cfg *img_cfg = (struct rom_img_cfg*)&_lm_rom_img_cfgp;
+    int *src = img_cfg->img_start;
+    int *dst = (int*)&__data_start__;
+    int exit_code;
+
+    /* Initialize .data, if necessary. */
+    if (src != dst) {
+        int *end = (int*)&__data_end__;
+        while (dst < end) {
+            *dst++ = *src++;
+        }
+    }
+
+    /* Zero .bss. */
+    dst = (int*)&__bss_start__;
+    while (dst < (int*)&__bss_end__) {
+        *dst++ = 0;
+    }
+
+    /* Run initializers. */
+    __libc_init_array();
+
+    /* Jump to main. */
+    exit_code = main(0, 0, 0);
+    if (exit) {
+        exit(exit_code);
+    }
+
+    /* If exit is NULL, make sure we don't return. */
+    for (;;)
+        continue;
+}

From 5c9dc5ebfcfbaed297c66fae38b3b41f6fe9fc9d Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Sat, 15 Apr 2017 12:35:06 +0200
Subject: [PATCH 049/307] renamed target from "black" to generic f407v +
 removed unused files

---
 STM32F4/boards.txt                            |  52 +-
 STM32F4/cores/maple/boards.cpp                |   2 +-
 STM32F4/cores/maple/boards.h                  |   4 +-
 STM32F4/cores/maple/io.h                      |   4 +-
 STM32F4/cores/maple/libmaple/HardwareSPI.cpp  | 424 -----------
 STM32F4/cores/maple/libmaple/HardwareSPI.h    | 279 -------
 STM32F4/cores/maple/libmaple/dmaF1.c          | 383 ----------
 STM32F4/cores/maple/libmaple/dmaF1.h          | 453 -----------
 STM32F4/cores/maple/libmaple/dmaF2.c          | 241 ------
 STM32F4/cores/maple/libmaple/dmaF2.h          | 270 -------
 STM32F4/cores/maple/libmaple/gpio.c           |  36 -
 STM32F4/cores/maple/libmaple/gpioF1.c         | 200 -----
 STM32F4/cores/maple/libmaple/gpioF1.h         | 530 -------------
 STM32F4/cores/maple/libmaple/gpioF2.c         | 224 ------
 STM32F4/cores/maple/libmaple/gpioF2.h         | 550 --------------
 STM32F4/cores/maple/libmaple/rcc.c            |  37 -
 STM32F4/cores/maple/libmaple/rccF1.c          | 233 ------
 STM32F4/cores/maple/libmaple/rccF1.h          | 572 --------------
 STM32F4/cores/maple/libmaple/rccF2.c          | 707 ------------------
 STM32F4/cores/maple/libmaple/rccF2.h          | 642 ----------------
 STM32F4/cores/maple/libmaple/usbF4/usb.c      |   4 +-
 STM32F4/cores/maple/wirish_types.h            |   2 +-
 .../black_f4.h.old}                           |   2 +-
 .../generic_f407v.cpp}                        |   8 +-
 .../variants/generic_f407v/generic_f407v.h    | 130 ++++
 .../ld/common.inc                             |   0
 .../ld/extra_libs.inc                         |   0
 .../ld/flash.ld                               |   0
 .../ld/jtag.ld                                |   0
 .../ld/names.inc                              |   0
 .../ld/ram.ld                                 |   0
 .../ld/vector_symbols.inc                     |   0
 .../pins_arduino.h                            |   0
 .../stm32_isrs.S                              |   0
 .../stm32_vector_table.S                      |   0
 .../variant.h                                 |   0
 .../wirish/start.S                            |   0
 .../wirish/start_c.c                          |   0
 38 files changed, 169 insertions(+), 5820 deletions(-)
 delete mode 100644 STM32F4/cores/maple/libmaple/HardwareSPI.cpp
 delete mode 100644 STM32F4/cores/maple/libmaple/HardwareSPI.h
 delete mode 100644 STM32F4/cores/maple/libmaple/dmaF1.c
 delete mode 100644 STM32F4/cores/maple/libmaple/dmaF1.h
 delete mode 100644 STM32F4/cores/maple/libmaple/dmaF2.c
 delete mode 100644 STM32F4/cores/maple/libmaple/dmaF2.h
 delete mode 100644 STM32F4/cores/maple/libmaple/gpio.c
 delete mode 100644 STM32F4/cores/maple/libmaple/gpioF1.c
 delete mode 100644 STM32F4/cores/maple/libmaple/gpioF1.h
 delete mode 100644 STM32F4/cores/maple/libmaple/gpioF2.c
 delete mode 100644 STM32F4/cores/maple/libmaple/gpioF2.h
 delete mode 100644 STM32F4/cores/maple/libmaple/rcc.c
 delete mode 100644 STM32F4/cores/maple/libmaple/rccF1.c
 delete mode 100644 STM32F4/cores/maple/libmaple/rccF1.h
 delete mode 100644 STM32F4/cores/maple/libmaple/rccF2.c
 delete mode 100644 STM32F4/cores/maple/libmaple/rccF2.h
 rename STM32F4/variants/{black_f407vet6/black_f4.h => generic_f407v/black_f4.h.old} (99%)
 rename STM32F4/variants/{black_f407vet6/black_f4.cpp => generic_f407v/generic_f407v.cpp} (99%)
 create mode 100644 STM32F4/variants/generic_f407v/generic_f407v.h
 rename STM32F4/variants/{black_f407vet6 => generic_f407v}/ld/common.inc (100%)
 rename STM32F4/variants/{black_f407vet6 => generic_f407v}/ld/extra_libs.inc (100%)
 rename STM32F4/variants/{black_f407vet6 => generic_f407v}/ld/flash.ld (100%)
 rename STM32F4/variants/{black_f407vet6 => generic_f407v}/ld/jtag.ld (100%)
 rename STM32F4/variants/{black_f407vet6 => generic_f407v}/ld/names.inc (100%)
 rename STM32F4/variants/{black_f407vet6 => generic_f407v}/ld/ram.ld (100%)
 rename STM32F4/variants/{black_f407vet6 => generic_f407v}/ld/vector_symbols.inc (100%)
 rename STM32F4/variants/{black_f407vet6 => generic_f407v}/pins_arduino.h (100%)
 rename STM32F4/variants/{black_f407vet6 => generic_f407v}/stm32_isrs.S (100%)
 rename STM32F4/variants/{black_f407vet6 => generic_f407v}/stm32_vector_table.S (100%)
 rename STM32F4/variants/{black_f407vet6 => generic_f407v}/variant.h (100%)
 rename STM32F4/variants/{black_f407vet6 => generic_f407v}/wirish/start.S (100%)
 rename STM32F4/variants/{black_f407vet6 => generic_f407v}/wirish/start_c.c (100%)

diff --git a/STM32F4/boards.txt b/STM32F4/boards.txt
index 3ff182c7b..df9f2b41a 100644
--- a/STM32F4/boards.txt
+++ b/STM32F4/boards.txt
@@ -30,32 +30,32 @@ discovery_f407.build.error_led_pin=14
 discovery_f407.build.board=STM32DiscoveryF407
 
 ##############################################################
-black_f407vet6.name=STM32 Black F407VET6
-
-black_f407vet6.upload.tool=stlink_upload
-black_f407vet6.upload.protocol=stlink
-
-black_f407vet6.upload.file_type=bin
-black_f407vet6.upload.ram.maximum_size=65535
-black_f407vet6.upload.flash.maximum_size=514288
-black_f407vet6.upload.maximum_size=514288
-
-#black_f407vet6.upload.usbID=0483:3748
-#black_f407vet6.upload.altID=1
-#black_f407vet6.upload.auto_reset=true
-
-black_f407vet6.build.mcu=cortex-m4
-black_f407vet6.build.f_cpu=168000000L
-black_f407vet6.build.core=maple
-black_f407vet6.build.extra_flags=-mthumb -DSTM32_HIGH_DENSITY -DSTM32F4 -DBOARD_black_f4
-black_f407vet6.build.ldscript=ld/jtag.ld
-black_f407vet6.build.variant=black_f407vet6
-black_f407vet6.build.variant_system_lib=lib_f407.a
-black_f407vet6.build.vect=VECT_TAB_BASE
-black_f407vet6.build.density=STM32_HIGH_DENSITY
-black_f407vet6.build.error_led_port=GPIOA
-black_f407vet6.build.error_led_pin=7
-black_f407vet6.build.board=STM32BlackF407VET6
+generic_f407v.name=Generic STM32F407V series
+
+generic_f407v.upload.tool=stlink_upload
+generic_f407v.upload.protocol=stlink
+
+generic_f407v.upload.file_type=bin
+generic_f407v.upload.ram.maximum_size=131072
+generic_f407v.upload.flash.maximum_size=514288
+generic_f407v.upload.maximum_size=514288
+
+#generic_f407v.upload.usbID=0483:3748
+#generic_f407v.upload.altID=1
+#generic_f407v.upload.auto_reset=true
+
+generic_f407v.build.mcu=cortex-m4
+generic_f407v.build.f_cpu=168000000L
+generic_f407v.build.core=maple
+generic_f407v.build.extra_flags=-mthumb -DSTM32_HIGH_DENSITY -DSTM32F4 -DBOARD_generic_f407v
+generic_f407v.build.ldscript=ld/jtag.ld
+generic_f407v.build.variant=generic_f407v
+generic_f407v.build.variant_system_lib=lib_f407.a
+generic_f407v.build.vect=VECT_TAB_BASE
+generic_f407v.build.density=STM32_HIGH_DENSITY
+generic_f407v.build.error_led_port=GPIOA
+generic_f407v.build.error_led_pin=7
+generic_f407v.build.board=STM32GenericF407VET6
 
 ##############################################################
 stm32f4stamp.name=STM32F4Stamp F405
diff --git a/STM32F4/cores/maple/boards.cpp b/STM32F4/cores/maple/boards.cpp
index f9bfd5a31..c8ba97894 100644
--- a/STM32F4/cores/maple/boards.cpp
+++ b/STM32F4/cores/maple/boards.cpp
@@ -67,7 +67,7 @@ void init(void) {
     setupADC();
     setupTimers();
 
-    //setupUSB();
+    setupUSB();
 }
 
 /* You could farm this out to the files in boards/ if e.g. it takes
diff --git a/STM32F4/cores/maple/boards.h b/STM32F4/cores/maple/boards.h
index 5e0aae3b8..e123341ed 100644
--- a/STM32F4/cores/maple/boards.h
+++ b/STM32F4/cores/maple/boards.h
@@ -140,8 +140,8 @@ bool boardUsesPin(uint8 pin);
 #include "aeroquad32mini.h"
 #elif defined(BOARD_discovery_f4)
 #include "discovery_f4.h"
-#elif defined(BOARD_black_f4)
-#include "black_f4.h"
+#elif defined(BOARD_generic_f407v)
+#include "generic_f407v.h"
 #elif defined(BOARD_freeflight)
 #include "freeflight.h"
 #else
diff --git a/STM32F4/cores/maple/io.h b/STM32F4/cores/maple/io.h
index d4d1c25cd..1208be63f 100644
--- a/STM32F4/cores/maple/io.h
+++ b/STM32F4/cores/maple/io.h
@@ -180,7 +180,7 @@ static inline void toggleLED() {
  * accomplished portably over all LeafLabs boards by calling
  * pinMode(BOARD_BUTTON_PIN, INPUT).
  *
- * @param button - one of available on-board buttons (up to 3 for black F4)
+ * @param button - one of available on-board buttons (up to 3 for generic F4)
  *
  * @see pinMode()
  */
@@ -198,7 +198,7 @@ uint8 isButtonPressed(uint8_t button);
  * button is pressed.  If timeout_millis is left out (or 0), wait
  * forever.
  *
- * @param button - one of available on-board buttons (up to 3 for black F4)
+ * @param button - one of available on-board buttons (up to 3 for generic F4)
  *
  * @return true, if the button was pressed; false, if the timeout was
  * reached.
diff --git a/STM32F4/cores/maple/libmaple/HardwareSPI.cpp b/STM32F4/cores/maple/libmaple/HardwareSPI.cpp
deleted file mode 100644
index a5b4711be..000000000
--- a/STM32F4/cores/maple/libmaple/HardwareSPI.cpp
+++ /dev/null
@@ -1,424 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @author Marti Bolivar <mbolivar@leaflabs.com>
- * @brief Wirish SPI implementation.
- */
-
-#include "HardwareSPI.h"
-
-#include "timer.h"
-#include "util.h"
-#include "rcc.h"
-
-#include "wirish.h"
-#include "boards.h"
-
-struct spi_pins {
-    uint8 nss;
-    uint8 sck;
-    uint8 miso;
-    uint8 mosi;
-};
-
-static const spi_pins* dev_to_spi_pins(spi_dev *dev);
-
-static void enable_device(spi_dev *dev,
-                          bool as_master,
-                          SPIFrequency frequency,
-                          spi_cfg_flag endianness,
-                          spi_mode mode);
-
-static const spi_pins board_spi_pins[] __FLASH__ = {
-    {BOARD_SPI1_NSS_PIN,
-     BOARD_SPI1_SCK_PIN,
-     BOARD_SPI1_MISO_PIN,
-     BOARD_SPI1_MOSI_PIN},
-#ifdef BOARD_SPI2_NSS_PIN
-	{BOARD_SPI2_NSS_PIN,
-     BOARD_SPI2_SCK_PIN,
-     BOARD_SPI2_MISO_PIN,
-     BOARD_SPI2_MOSI_PIN},
-#endif
-#ifdef STM32_HIGH_DENSITY
-    {BOARD_SPI3B_NSS_PIN,
-     BOARD_SPI3B_SCK_PIN,
-     BOARD_SPI3B_MISO_PIN,
-     BOARD_SPI3B_MOSI_PIN},
-#endif
-#ifdef STM32F4
-    {BOARD_SPI3B_NSS_PIN,
-     BOARD_SPI3B_SCK_PIN,
-     BOARD_SPI3B_MISO_PIN,
-     BOARD_SPI3B_MOSI_PIN},
-#endif
-};
-
-
-/*
- * Constructor
- */
-
-HardwareSPI::HardwareSPI(uint32 spi_num) {
-    switch (spi_num) {
-    case 1:
-        this->spi_d = SPI1;
-        break;
-    case 2:
-        this->spi_d = SPI2;
-        break;
-#ifdef STM32_HIGH_DENSITY
-    case 3:
-        this->spi_d = SPI3;
-        break;
-#endif
-#ifdef STM32F4
-//    case 4:
-//        this->spi_d = SPI4;
-//        break;
-#endif
-    default:
-        ASSERT(0);
-    }
-}
-
-/*
- * Set up/tear down
- */
-
-void HardwareSPI::begin(SPIFrequency frequency, uint32 bitOrder, uint32 mode) {
-    if (mode >= 4) {
-        ASSERT(0);
-        return;
-    }
-    spi_cfg_flag end = bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB;
-    spi_mode m = (spi_mode)mode;
-    enable_device(this->spi_d, true, frequency, end, m);
-}
-
-void HardwareSPI::begin(void) {
-    this->begin(SPI_1_125MHZ, MSBFIRST, 0);
-}
-
-void HardwareSPI::beginSlave(uint32 bitOrder, uint32 mode) {
-    if (mode >= 4) {
-        ASSERT(0);
-        return;
-    }
-    spi_cfg_flag end = bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB;
-    spi_mode m = (spi_mode)mode;
-    enable_device(this->spi_d, false, (SPIFrequency)0, end, m);
-}
-
-void HardwareSPI::beginSlave(void) {
-    this->beginSlave(MSBFIRST, 0);
-}
-
-
-/*
-void HardwareSPI::beginTransaction(uint8_t pin, SPISettings settings)
-{
-//    this->begin(settings.clock, settings.bitOrder, settings.dataMode);
-    this->begin(SPI_1_125MHZ, settings.bitOrder, settings.dataMode);
-}
-*/
-
-void HardwareSPI::end(void) {
-    if (!spi_is_enabled(this->spi_d)) {
-        return;
-    }
-
-    // Follows RM0008's sequence for disabling a SPI in master/slave
-    // full duplex mode.
-    while (spi_is_rx_nonempty(this->spi_d)) {
-        // FIXME [0.1.0] remove this once you have an interrupt based driver
-        volatile uint16 rx __attribute__((unused)) = spi_rx_reg(this->spi_d);
-    }
-    while (!spi_is_tx_empty(this->spi_d))
-        ;
-    while (spi_is_busy(this->spi_d))
-        ;
-    spi_peripheral_disable(this->spi_d);
-}
-
-/*
- * I/O
- */
-
-uint8 HardwareSPI::read(void) {
-    uint8 buf[1];
-    this->read(buf, 1);
-    return buf[0];
-}
-
-void HardwareSPI::read(uint8 *buf, uint32 len) {
-    uint32 rxed = 0;
-    while (rxed < len) {
-        while (!spi_is_rx_nonempty(this->spi_d))
-            ;
-        buf[rxed++] = (uint8)spi_rx_reg(this->spi_d);
-    }
-}
-
-#if 0
-void HardwareSPI::readMaster(uint8 *buf, uint32 len) {
-    uint32 rxed = 0;
-    while (rxed < len) {
-		spi_tx_reg(this->spi_d, 0xff);
-        while (!spi_is_rx_nonempty(this->spi_d))
-            ;
-        buf[rxed++] = (uint8)spi_rx_reg(this->spi_d);
-		buf[rxed++] = this->spi_d->regs->DR;
-    }
-}
-#endif
-void HardwareSPI::readMaster(uint8 *buf, uint32 len) {
-	spi_reg_map *r = this->spi_d->regs;
-    uint32 rxed = 0;
-    while (rxed < len) {
-		r->DR = 0xff;
-        while (!(r->SR & SPI_SR_RXNE))
-            ;
-		buf[rxed++] = r->DR;
-    }
-}
-
-
-void HardwareSPI::waitReady() {
-	while (!spi_is_rx_nonempty(this->spi_d))
-		;
-}
-
-void HardwareSPI::write(uint8 byte) {
-    this->write(&byte, 1);
-}
-
-void HardwareSPI::write(const uint8 *data, uint32 length) {
-    uint32 txed = 0;
-    while (txed < length) {
-        txed += spi_tx(this->spi_d, data + txed, length - txed);
-    }
-}
-
-uint8 HardwareSPI::transfer(uint8 byte) {
-    this->write(byte);
-    return this->read();
-}
-
-/*
- * Pin accessors
- */
-
-uint8 HardwareSPI::misoPin(void) {
-    return dev_to_spi_pins(this->spi_d)->miso;
-}
-
-uint8 HardwareSPI::mosiPin(void) {
-    return dev_to_spi_pins(this->spi_d)->mosi;
-}
-
-uint8 HardwareSPI::sckPin(void) {
-    return dev_to_spi_pins(this->spi_d)->sck;
-}
-
-uint8 HardwareSPI::nssPin(void) {
-    return dev_to_spi_pins(this->spi_d)->nss;
-}
-
-/*
- * Deprecated functions
- */
-
-uint8 HardwareSPI::send(uint8 data) {
-    uint8 buf[] = {data};
-    return this->send(buf, 1);
-}
-
-#if 1	
-uint8 HardwareSPI::send(const uint8 *buf, uint32 len) {
-    uint32 txed = 0;
-    uint8 ret = 0;
-    while (txed < len) {
-        this->write(buf[txed++]);
-        ret = this->read();
-    }
-    return ret;
-}
-#else
-// this does not work for an unknown reason
-uint8 HardwareSPI::send(const uint8 *buf, uint32 len) {
-	volatile uint32 *dr = &(this->spi_d->regs->DR);
-	volatile uint32 *sr = &(this->spi_d->regs->SR);
-    uint32 txed = 0;
-	uint32 rx=0;
-    while (txed < len) {
-        //while (!(*sr & SPI_SR_TXE))
-        //    ;
-		//*dr = buf[txed++];
-		this->write(buf[txed++]);
-
-        while (!(*sr & SPI_SR_RXNE))
-			;
-		rx = *dr;
-		//rx = this->read();
-    }
-
-	return rx;
-}
-#endif
-
-uint8 HardwareSPI::recv(void) {
-    return this->read();
-}
-
-/*
- * Auxiliary functions
- */
-
-static void configure_gpios(spi_dev *dev, bool as_master);
-static spi_baud_rate determine_baud_rate(spi_dev *dev, SPIFrequency freq);
-
-static const spi_pins* dev_to_spi_pins(spi_dev *dev) {
-    switch (dev->clk_id) {
-    case RCC_SPI1: return board_spi_pins;
-    case RCC_SPI2: return board_spi_pins + 1;
-#ifdef STM32_HIGH_DENSITY
-    case RCC_SPI3: return board_spi_pins + 2;
-#endif
-#ifdef STM32F4
-    case RCC_SPI4: return board_spi_pins + 3;
-#endif
-    default:       return NULL;
-    }
-}
-
-/* Enables the device in master or slave full duplex mode.  If you
- * change this code, you must ensure that appropriate changes are made
- * to HardwareSPI::end(). */
-static void enable_device(spi_dev *dev,
-                          bool as_master,
-                          SPIFrequency freq,
-                          spi_cfg_flag endianness,
-                          spi_mode mode) {
-    spi_baud_rate baud = determine_baud_rate(dev, freq);
-    uint32 cfg_flags = (endianness | SPI_DFF_8_BIT | SPI_SW_SLAVE |
-                        (as_master ? SPI_SOFT_SS : 0));
-
-    spi_init(dev);
-    configure_gpios(dev, as_master);
-    if (as_master) {
-        spi_master_enable(dev, baud, mode, cfg_flags);
-    } else {
-        spi_slave_enable(dev, mode, cfg_flags);
-    }
-}
-
-static void disable_pwm(const stm32_pin_info *i) {
-    if (i->timer_device) {
-        timer_set_mode(i->timer_device, i->timer_channel, TIMER_DISABLED);
-    }
-}
-
-static void configure_gpios(spi_dev *dev, bool as_master) {
-    const spi_pins *pins = dev_to_spi_pins(dev);
-
-    if (!pins) {
-        return;
-    }
-
-	const stm32_pin_info *nssi = (pins->nss >= 0) ? &PIN_MAP[pins->nss] : NULL;
-    const stm32_pin_info *scki = &PIN_MAP[pins->sck];
-    const stm32_pin_info *misoi = &PIN_MAP[pins->miso];
-    const stm32_pin_info *mosii = &PIN_MAP[pins->mosi];
-
-	if(nssi) {
-		disable_pwm(nssi);
-	}
-    disable_pwm(scki);
-    disable_pwm(misoi);
-    disable_pwm(mosii);
-
-#ifdef STM32F4
-	if(dev->clk_id <= RCC_SPI2) {
-		if(nssi) {
-			if(!as_master) {
-				gpio_set_af_mode(nssi->gpio_device,  scki->gpio_bit, 5);
-			}
-		}
-		gpio_set_af_mode(scki->gpio_device,  scki->gpio_bit, 5);
-		gpio_set_af_mode(misoi->gpio_device, misoi->gpio_bit, 5);
-		gpio_set_af_mode(mosii->gpio_device, mosii->gpio_bit, 5);
-	} else {
-		if(nssi) {
-			if(!as_master) {
-				gpio_set_af_mode(nssi->gpio_device,  scki->gpio_bit, 6);
-			}
-		}
-		gpio_set_af_mode(scki->gpio_device,  scki->gpio_bit, 6);
-		gpio_set_af_mode(misoi->gpio_device, misoi->gpio_bit, 6);
-		gpio_set_af_mode(mosii->gpio_device, mosii->gpio_bit, 6);
-	}
-#endif
-
-		if(nssi) {
-                    spi_config_gpios(dev, as_master, nssi->gpio_device, nssi->gpio_bit,
-                                                     scki->gpio_device, scki->gpio_bit, 
-                                                     misoi->gpio_device, misoi->gpio_bit,
-                                                     mosii->gpio_device, mosii->gpio_bit);
-		} else {
-                    spi_config_gpios(dev, as_master, NULL, -1,
-                                                     scki->gpio_device, scki->gpio_bit, 
-                                                     misoi->gpio_device, misoi->gpio_bit,
-                                                     mosii->gpio_device, mosii->gpio_bit);
-		}
-}
-
-static const spi_baud_rate baud_rates[MAX_SPI_FREQS] __FLASH__ = {
-    SPI_BAUD_PCLK_DIV_2,
-    SPI_BAUD_PCLK_DIV_4,
-    SPI_BAUD_PCLK_DIV_8,
-    SPI_BAUD_PCLK_DIV_16,
-    SPI_BAUD_PCLK_DIV_32,
-    SPI_BAUD_PCLK_DIV_64,
-    SPI_BAUD_PCLK_DIV_128,
-    SPI_BAUD_PCLK_DIV_256,
-};
-
-/*
- * Note: This assumes you're on a LeafLabs-style board
- * (CYCLES_PER_MICROSECOND == 72, APB2 at 72MHz, APB1 at 36MHz).
- */
-static spi_baud_rate determine_baud_rate(spi_dev *dev, SPIFrequency freq) {
-    if (rcc_dev_clk(dev->clk_id) == RCC_APB2 && freq == SPI_140_625KHZ) {
-        /* APB2 peripherals are too fast for 140.625 KHz */
-        ASSERT(0);
-        return (spi_baud_rate)~0;
-    }
-    return (rcc_dev_clk(dev->clk_id) == RCC_APB2 ?
-            baud_rates[freq + 1] :
-            baud_rates[freq]);
-}
diff --git a/STM32F4/cores/maple/libmaple/HardwareSPI.h b/STM32F4/cores/maple/libmaple/HardwareSPI.h
deleted file mode 100644
index 327f29da1..000000000
--- a/STM32F4/cores/maple/libmaple/HardwareSPI.h
+++ /dev/null
@@ -1,279 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file HardwareSPI.h
- * @brief High-level SPI interface
- *
- * This is a "bare essentials" polling driver for now.
- */
-
-/* TODO [0.1.0] Remove deprecated methods. */
-
-#include "libmaple_types.h"
-#include "spi.h"
-
-#include "boards.h"
-#include "wirish.h"
-
-#ifndef _HARDWARESPI_H_
-#define _HARDWARESPI_H_
-
-/**
- * @brief Defines the possible SPI communication speeds.
- */
-typedef enum SPIFrequency {
-    SPI_18MHZ       = 0, /**< 18 MHz */
-    SPI_9MHZ        = 1, /**< 9 MHz */
-    SPI_4_5MHZ      = 2, /**< 4.5 MHz */
-    SPI_2_25MHZ     = 3, /**< 2.25 MHz */
-    SPI_1_125MHZ    = 4, /**< 1.125 MHz */
-    SPI_562_500KHZ  = 5, /**< 562.500 KHz */
-    SPI_281_250KHZ  = 6, /**< 281.250 KHz */
-    SPI_140_625KHZ  = 7, /**< 140.625 KHz */
-} SPIFrequency;
-
-#define MAX_SPI_FREQS 8
-
-#if CYCLES_PER_MICROSECOND != 72
-/* TODO [0.2.0?] something smarter than this */
-//#warning "Unexpected clock speed; SPI frequency calculation will be incorrect"
-#endif
-
-
-//#define BOARD_SPI_DEFAULT_SS PC13
-#define BOARD_SPI_DEFAULT_SS PB0
-#define SPI_MODE0 SPI_MODE_0
-#define SPI_MODE1 SPI_MODE_1
-#define SPI_MODE2 SPI_MODE_2
-#define SPI_MODE3 SPI_MODE_3
-
-/*
-class SPISettings {
-public:
-	SPISettings(uint32 clock, BitOrder bitOrder, uint8 dataMode) {
-		if (__builtin_constant_p(clock)) {
-			init_AlwaysInline(clock, bitOrder, dataMode);
-		} else {
-			init_MightInline(clock, bitOrder, dataMode);
-		}
-	}
-	SPISettings() { init_AlwaysInline(4000000, MSBFIRST, SPI_MODE0); }
-private:
-	void init_MightInline(uint32 clock, BitOrder bitOrder, uint8 dataMode) {
-		init_AlwaysInline(clock, bitOrder, dataMode);
-	}
-	void init_AlwaysInline(uint32 clock, BitOrder bitOrder, uint8 dataMode) __attribute__((__always_inline__)) {
-		this->clock = clock;
-		this->bitOrder = bitOrder;
-		this->dataMode = dataMode;
-	}
-	uint32 clock;
-	BitOrder bitOrder;
-	uint8 dataMode;
-	friend class HardwareSPI;
-};
-*/
-
-
-/**
- * @brief Wirish SPI interface.
- *
- * This implementation uses software slave management, so the caller
- * is responsible for controlling the slave select line.
- */
-class HardwareSPI {
-public:
-    /**
-     * @param spiPortNumber Number of the SPI port to manage.
-     */
-    HardwareSPI(uint32 spiPortNumber);
-
-    /*
-     * Set up/tear down
-     */
-
-    /**
-     * @brief Turn on a SPI port and set its GPIO pin modes for use as master.
-     *
-     * SPI port is enabled in full duplex mode, with software slave management.
-     *
-     * @param frequency Communication frequency
-     * @param bitOrder Either LSBFIRST (little-endian) or MSBFIRST (big-endian)
-     * @param mode SPI mode to use, one of SPI_MODE_0, SPI_MODE_1,
-     *             SPI_MODE_2, and SPI_MODE_3.
-     */
-    void begin(SPIFrequency frequency, uint32 bitOrder, uint32 mode);
-
-    /**
-     * @brief Equivalent to begin(SPI_1_125MHZ, MSBFIRST, 0).
-     */
-    void begin(void);
-
-    /**
-     * @brief Turn on a SPI port and set its GPIO pin modes for use as a slave.
-     *
-     * SPI port is enabled in full duplex mode, with software slave management.
-     *
-     * @param bitOrder Either LSBFIRST (little-endian) or MSBFIRST(big-endian)
-     * @param mode SPI mode to use
-     */
-    void beginSlave(uint32 bitOrder, uint32 mode);
-
-    /**
-     * @brief Equivalent to beginSlave(MSBFIRST, 0).
-     */
-    void beginSlave(void);
-
-    /**
-     * @brief Disables the SPI port, but leaves its GPIO pin modes unchanged.
-     */
-    void end(void);
-
-    /*
-     * I/O
-     */
-
-    /**
-     * @brief Return the next unread byte.
-     *
-     * If there is no unread byte waiting, this function will block
-     * until one is received.
-     */
-    uint8 read(void);
-
-    /**
-     * @brief Read length bytes, storing them into buffer.
-     * @param buffer Buffer to store received bytes into.
-     * @param length Number of bytes to store in buffer.  This
-     *               function will block until the desired number of
-     *               bytes have been read.
-     */
-    void read(uint8 *buffer, uint32 length);
-
-	/**
-     * @brief Read length bytes, storing them into buffer.
-     * @param buffer Buffer to store received bytes into.
-     * @param length Number of bytes to store in buffer.  This
-     *               function will block until the desired number of
-     *               bytes have been read.
-     */
-    void readMaster(uint8 *buffer, uint32 length);
-
-
-	void waitReady();
-    /**
-     * @brief Transmit a byte.
-     * @param data Byte to transmit.
-     */
-    void write(uint8 data);
-
-    /**
-     * @brief Transmit multiple bytes.
-     * @param buffer Bytes to transmit.
-     * @param length Number of bytes in buffer to transmit.
-     */
-    void write(const uint8 *buffer, uint32 length);
-
-    /**
-     * @brief Transmit a byte, then return the next unread byte.
-     *
-     * This function transmits before receiving.
-     *
-     * @param data Byte to transmit.
-     * @return Next unread byte.
-     */
-    uint8 transfer(uint8 data);
-
-    /*
-     * Pin accessors
-     */
-
-    /**
-     * @brief Return the number of the MISO (master in, slave out) pin
-     */
-    uint8 misoPin(void);
-
-    /**
-     * @brief Return the number of the MOSI (master out, slave in) pin
-     */
-    uint8 mosiPin(void);
-
-    /**
-     * @brief Return the number of the SCK (serial clock) pin
-     */
-    uint8 sckPin(void);
-
-    /**
-     * @brief Return the number of the NSS (slave select) pin
-     */
-    uint8 nssPin(void);
-
-    /* -- The following methods are deprecated --------------------------- */
-
-    /**
-     * @brief Deprecated.
-     *
-     * Use HardwareSPI::transfer() instead.
-     *
-     * @see HardwareSPI::transfer()
-     */
-    uint8 send(uint8 data);
-
-    /**
-     * @brief Deprecated.
-     *
-     * Use HardwareSPI::write() in combination with
-     * HardwareSPI::read() (or HardwareSPI::transfer()) instead.
-     *
-     * @see HardwareSPI::write()
-     * @see HardwareSPI::read()
-     * @see HardwareSPI::transfer()
-     */
-    uint8 send(const uint8 *data, uint32 length);
-
-    /**
-     * @brief Deprecated.
-     *
-     * Use HardwareSPI::read() instead.
-     *
-     * @see HardwareSPI::read()
-     */
-    uint8 recv(void);
-    
-//    void beginTransaction(SPISettings settings) { beginTransaction(BOARD_SPI_DEFAULT_SS, settings); }
-//    void beginTransaction(uint8 pin, SPISettings settings);
-    void endTransaction(void) { }
-                            
-private:
-    spi_dev *spi_d;
-};
-
-
-extern HardwareSPI SPI;
-
-#endif
-
diff --git a/STM32F4/cores/maple/libmaple/dmaF1.c b/STM32F4/cores/maple/libmaple/dmaF1.c
deleted file mode 100644
index f8ddb2d22..000000000
--- a/STM32F4/cores/maple/libmaple/dmaF1.c
+++ /dev/null
@@ -1,383 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Michael Hope.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-#ifdef STM32F1
-
-/**
- * @file dma.c
- * @author Marti Bolivar <mbolivar@leaflabs.com>;
- *         Original implementation by Michael Hope
- * @brief Direct Memory Access peripheral support
- */
-
-#include "dma.h"
-#include "bitband.h"
-#include "util.h"
-
-/*
- * Devices
- */
-
-static dma_dev dma1 = {
-    .regs     = DMA1_BASE,
-    .clk_id   = RCC_DMA1,
-    .handlers = {{ .handler = NULL, .irq_line = NVIC_DMA_CH1 },
-                 { .handler = NULL, .irq_line = NVIC_DMA_CH2 },
-                 { .handler = NULL, .irq_line = NVIC_DMA_CH3 },
-                 { .handler = NULL, .irq_line = NVIC_DMA_CH4 },
-                 { .handler = NULL, .irq_line = NVIC_DMA_CH5 },
-                 { .handler = NULL, .irq_line = NVIC_DMA_CH6 },
-                 { .handler = NULL, .irq_line = NVIC_DMA_CH7 }}
-};
-/** DMA1 device */
-dma_dev *DMA1 = &dma1;
-
-#ifdef STM32_HIGH_DENSITY
-static dma_dev dma2 = {
-    .regs     = DMA2_BASE,
-    .clk_id   = RCC_DMA2,
-    .handlers = {{ .handler = NULL, .irq_line = NVIC_DMA2_CH1   },
-                 { .handler = NULL, .irq_line = NVIC_DMA2_CH2   },
-                 { .handler = NULL, .irq_line = NVIC_DMA2_CH3   },
-                 { .handler = NULL, .irq_line = NVIC_DMA2_CH_4_5 },
-                 { .handler = NULL, .irq_line = NVIC_DMA2_CH_4_5 }} /* !@#$ */
-};
-/** DMA2 device */
-dma_dev *DMA2 = &dma2;
-#endif
-
-/*
- * Convenience routines
- */
-
-/**
- * @brief Initialize a DMA device.
- * @param dev Device to initialize.
- */
-void dma_init(dma_dev *dev) {
-    rcc_clk_enable(dev->clk_id);
-}
-
-/**
- * @brief Set up a DMA transfer.
- *
- * The channel will be disabled before being reconfigured.  The
- * transfer will have low priority by default.  You may choose another
- * priority before the transfer begins using dma_set_priority(), as
- * well as performing any other configuration you desire.  When the
- * channel is configured to your liking, enable it using dma_enable().
- *
- * @param dev DMA device.
- * @param channel DMA channel.
- * @param peripheral_address Base address of peripheral data register
- *                           involved in the transfer.
- * @param peripheral_size Peripheral data transfer size.
- * @param memory_address Base memory address involved in the transfer.
- * @param memory_size Memory data transfer size.
- * @param mode Logical OR of dma_mode_flags
- * @sideeffect Disables the given DMA channel.
- * @see dma_xfer_size
- * @see dma_mode_flags
- * @see dma_set_num_transfers()
- * @see dma_set_priority()
- * @see dma_attach_interrupt()
- * @see dma_enable()
- */
-void dma_setup_transfer(dma_dev       *dev,
-                        dma_channel    channel,
-                        __io void     *peripheral_address,
-                        dma_xfer_size  peripheral_size,
-                        __io void     *memory_address,
-                        dma_xfer_size  memory_size,
-                        uint32         mode) {
-    dma_channel_reg_map *channel_regs = dma_channel_regs(dev, channel);
-
-    dma_disable(dev, channel);  /* can't write to CMAR/CPAR otherwise */
-    channel_regs->CCR = (memory_size << 10) | (peripheral_size << 8) | mode;
-    channel_regs->CMAR = (uint32)memory_address;
-    channel_regs->CPAR = (uint32)peripheral_address;
-}
-
-/**
- * @brief Set the number of data to be transferred on a DMA channel.
- *
- * You may not call this function while the channel is enabled.
- *
- * @param dev DMA device
- * @param channel Channel through which the transfer occurs.
- * @param num_transfers
- */
-void dma_set_num_transfers(dma_dev *dev,
-                           dma_channel channel,
-                           uint16 num_transfers) {
-    dma_channel_reg_map *channel_regs;
-
-    ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
-
-    channel_regs = dma_channel_regs(dev, channel);
-    channel_regs->CNDTR = num_transfers;
-}
-
-/**
- * @brief Set the priority of a DMA transfer.
- *
- * You may not call this function while the channel is enabled.
- *
- * @param dev DMA device
- * @param channel DMA channel
- * @param priority priority to set.
- */
-void dma_set_priority(dma_dev *dev,
-                      dma_channel channel,
-                      dma_priority priority) {
-    dma_channel_reg_map *channel_regs;
-    uint32 ccr;
-
-    ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
-
-    channel_regs = dma_channel_regs(dev, channel);
-    ccr = channel_regs->CCR;
-    ccr &= ~DMA_CCR_PL;
-    ccr |= priority;
-    channel_regs->CCR = ccr;
-}
-
-/**
- * @brief Attach an interrupt to a DMA transfer.
- *
- * Interrupts are enabled using appropriate mode flags in
- * dma_setup_transfer().
- *
- * @param dev DMA device
- * @param channel Channel to attach handler to
- * @param handler Interrupt handler to call when channel interrupt fires.
- * @see dma_setup_transfer()
- * @see dma_get_irq_cause()
- * @see dma_detach_interrupt()
- */
-void dma_attach_interrupt(dma_dev *dev,
-                          dma_channel channel,
-                          void (*handler)(void)) {
-    dev->handlers[channel - 1].handler = handler;
-    nvic_irq_enable(dev->handlers[channel - 1].irq_line);
-}
-
-/**
- * @brief Detach a DMA transfer interrupt handler.
- *
- * After calling this function, the given channel's interrupts will be
- * disabled.
- *
- * @param dev DMA device
- * @param channel Channel whose handler to detach
- * @sideeffect Clears interrupt enable bits in the channel's CCR register.
- * @see dma_attach_interrupt()
- */
-void dma_detach_interrupt(dma_dev *dev, dma_channel channel) {
-    /* Don't use nvic_irq_disable()! Think about DMA2 channels 4 and 5. */
-    dma_channel_regs(dev, channel)->CCR &= ~0xF;
-    dev->handlers[channel - 1].handler = NULL;
-}
-
-/**
- * @brief Discover the reason why a DMA interrupt was called.
- *
- * You may only call this function within an attached interrupt
- * handler for the given channel.
- *
- * This function resets the internal DMA register state which encodes
- * the cause of the interrupt; consequently, it can only be called
- * once per interrupt handler invocation.
- *
- * @param dev DMA device
- * @param channel Channel whose interrupt is being handled.
- * @return Reason why the interrupt fired.
- * @sideeffect Clears channel status flags in dev->regs->ISR.
- * @see dma_attach_interrupt()
- * @see dma_irq_cause
- */
-dma_irq_cause dma_get_irq_cause(dma_dev *dev, dma_channel channel) {
-    uint8 status_bits = dma_get_isr_bits(dev, channel);
-
-    /* If the channel global interrupt flag is cleared, then
-     * something's very wrong. */
-    ASSERT(status_bits & BIT(0));
-
-    dma_clear_isr_bits(dev, channel);
-
-    /* ISR flags get set even if the corresponding interrupt enable
-     * bits in the channel's configuration register are cleared, so we
-     * can't use a switch here.
-     *
-     * Don't change the order of these if statements. */
-    if (status_bits & BIT(3)) {
-        return DMA_TRANSFER_ERROR;
-    } else if (status_bits & BIT(1)) {
-        return DMA_TRANSFER_COMPLETE;
-    } else if (status_bits & BIT(2)) {
-        return DMA_TRANSFER_HALF_COMPLETE;
-    } else if (status_bits & BIT(0)) {
-        /* Shouldn't happen (unless someone messed up an IFCR write). */
-        throb();
-    }
-#if DEBUG_LEVEL < DEBUG_ALL
-    else {
-        /* We shouldn't have been called, but the debug level is too
-         * low for the above ASSERT() to have had any effect.  In
-         * order to fail fast, mimic the DMA controller's behavior
-         * when an error occurs. */
-        dma_disable(dev, channel);
-    }
-#endif
-    return DMA_TRANSFER_ERROR;
-}
-
-/**
- * @brief Enable a DMA channel.
- * @param dev DMA device
- * @param channel Channel to enable
- */
-void dma_enable(dma_dev *dev, dma_channel channel) {
-    dma_channel_reg_map *chan_regs = dma_channel_regs(dev, channel);
-    bb_peri_set_bit(&chan_regs->CCR, DMA_CCR_EN_BIT, 1);
-}
-
-/**
- * @brief Disable a DMA channel.
- * @param dev DMA device
- * @param channel Channel to disable
- */
-void dma_disable(dma_dev *dev, dma_channel channel) {
-    dma_channel_reg_map *chan_regs = dma_channel_regs(dev, channel);
-    bb_peri_set_bit(&chan_regs->CCR, DMA_CCR_EN_BIT, 0);
-}
-
-/**
- * @brief Set the base memory address where data will be read from or
- *        written to.
- *
- * You must not call this function while the channel is enabled.
- *
- * If the DMA memory size is 16 bits, the address is automatically
- * aligned to a half-word.  If the DMA memory size is 32 bits, the
- * address is aligned to a word.
- *
- * @param dev DMA Device
- * @param channel Channel whose base memory address to set.
- * @param addr Memory base address to use.
- */
-void dma_set_mem_addr(dma_dev *dev, dma_channel channel, __io void *addr) {
-    dma_channel_reg_map *chan_regs;
-
-    ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
-
-    chan_regs = dma_channel_regs(dev, channel);
-    chan_regs->CMAR = (uint32)addr;
-}
-
-/**
- * @brief Set the base peripheral address where data will be read from
- *        or written to.
- *
- * You must not call this function while the channel is enabled.
- *
- * If the DMA peripheral size is 16 bits, the address is automatically
- * aligned to a half-word.  If the DMA peripheral size is 32 bits, the
- * address is aligned to a word.
- *
- * @param dev DMA Device
- * @param channel Channel whose peripheral data register base address to set.
- * @param addr Peripheral memory base address to use.
- */
-void dma_set_per_addr(dma_dev *dev, dma_channel channel, __io void *addr) {
-    dma_channel_reg_map *chan_regs;
-
-    ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
-
-    chan_regs = dma_channel_regs(dev, channel);
-    chan_regs->CPAR = (uint32)addr;
-}
-
-/*
- * IRQ handlers
- */
-
-static inline void dispatch_handler(dma_dev *dev, dma_channel channel) {
-    void (*handler)(void) = dev->handlers[channel - 1].handler;
-    if (handler) {
-        handler();
-        dma_clear_isr_bits(dev, channel); /* in case handler doesn't */
-    }
-}
-
-void __irq_dma1_channel1(void) {
-    dispatch_handler(DMA1, DMA_CH1);
-}
-
-void __irq_dma1_channel2(void) {
-    dispatch_handler(DMA1, DMA_CH2);
-}
-
-void __irq_dma1_channel3(void) {
-    dispatch_handler(DMA1, DMA_CH3);
-}
-
-void __irq_dma1_channel4(void) {
-    dispatch_handler(DMA1, DMA_CH4);
-}
-
-void __irq_dma1_channel5(void) {
-    dispatch_handler(DMA1, DMA_CH5);
-}
-
-void __irq_dma1_channel6(void) {
-    dispatch_handler(DMA1, DMA_CH6);
-}
-
-void __irq_dma1_channel7(void) {
-    dispatch_handler(DMA1, DMA_CH7);
-}
-
-#ifdef STM32_HIGH_DENSITY
-void __irq_dma2_channel1(void) {
-    dispatch_handler(DMA2, DMA_CH1);
-}
-
-void __irq_dma2_channel2(void) {
-    dispatch_handler(DMA2, DMA_CH2);
-}
-
-void __irq_dma2_channel3(void) {
-    dispatch_handler(DMA2, DMA_CH3);
-}
-
-void __irq_dma2_channel4_5(void) {
-    dispatch_handler(DMA2, DMA_CH4);
-    dispatch_handler(DMA2, DMA_CH5);
-}
-#endif
-
-#endif
\ No newline at end of file
diff --git a/STM32F4/cores/maple/libmaple/dmaF1.h b/STM32F4/cores/maple/libmaple/dmaF1.h
deleted file mode 100644
index 6e8087f49..000000000
--- a/STM32F4/cores/maple/libmaple/dmaF1.h
+++ /dev/null
@@ -1,453 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Michael Hope.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file dma.h
- *
- * @author Marti Bolivar <mbolivar@leaflabs.com>;
- *         Original implementation by Michael Hope
- *
- * @brief Direct Memory Access peripheral support
- */
-
-/*
- * See /notes/dma.txt for more information.
- */
-
-#ifndef _DMA_H_
-#define _DMA_H_
-
-#include "libmaple_types.h"
-#include "rcc.h"
-#include "nvic.h"
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-/*
- * Register maps
- */
-
-/**
- * @brief DMA register map type.
- *
- * Note that DMA controller 2 (register map base pointer DMA2_BASE)
- * only supports channels 1--5.
- */
-typedef struct dma_reg_map {
-    __io uint32 ISR;            /**< Interrupt status register */
-    __io uint32 IFCR;           /**< Interrupt flag clear register */
-    __io uint32 CCR1;           /**< Channel 1 configuration register */
-    __io uint32 CNDTR1;         /**< Channel 1 number of data register */
-    __io uint32 CPAR1;          /**< Channel 1 peripheral address register */
-    __io uint32 CMAR1;          /**< Channel 1 memory address register */
-    const uint32 RESERVED1;     /**< Reserved. */
-    __io uint32 CCR2;           /**< Channel 2 configuration register */
-    __io uint32 CNDTR2;         /**< Channel 2 number of data register */
-    __io uint32 CPAR2;          /**< Channel 2 peripheral address register */
-    __io uint32 CMAR2;          /**< Channel 2 memory address register */
-    const uint32 RESERVED2;     /**< Reserved. */
-    __io uint32 CCR3;           /**< Channel 3 configuration register */
-    __io uint32 CNDTR3;         /**< Channel 3 number of data register */
-    __io uint32 CPAR3;          /**< Channel 3 peripheral address register */
-    __io uint32 CMAR3;          /**< Channel 3 memory address register */
-    const uint32 RESERVED3;     /**< Reserved. */
-    __io uint32 CCR4;           /**< Channel 4 configuration register */
-    __io uint32 CNDTR4;         /**< Channel 4 number of data register */
-    __io uint32 CPAR4;          /**< Channel 4 peripheral address register */
-    __io uint32 CMAR4;          /**< Channel 4 memory address register */
-    const uint32 RESERVED4;     /**< Reserved. */
-    __io uint32 CCR5;           /**< Channel 5 configuration register */
-    __io uint32 CNDTR5;         /**< Channel 5 number of data register */
-    __io uint32 CPAR5;          /**< Channel 5 peripheral address register */
-    __io uint32 CMAR5;          /**< Channel 5 memory address register */
-    const uint32 RESERVED5;     /**< Reserved. */
-    __io uint32 CCR6;           /**< Channel 6 configuration register */
-    __io uint32 CNDTR6;         /**< Channel 6 number of data register */
-    __io uint32 CPAR6;          /**< Channel 6 peripheral address register */
-    __io uint32 CMAR6;          /**< Channel 6 memory address register */
-    const uint32 RESERVED6;     /**< Reserved. */
-    __io uint32 CCR7;           /**< Channel 7 configuration register */
-    __io uint32 CNDTR7;         /**< Channel 7 number of data register */
-    __io uint32 CPAR7;          /**< Channel 7 peripheral address register */
-    __io uint32 CMAR7;          /**< Channel 7 memory address register */
-    const uint32 RESERVED7;     /**< Reserved. */
-} dma_reg_map;
-
-/** DMA controller 1 register map base pointer */
-#define DMA1_BASE                       ((struct dma_reg_map*)0x40020000)
-
-#ifdef STM32_HIGH_DENSITY
-/** DMA controller 2 register map base pointer */
-#define DMA2_BASE                       ((struct dma_reg_map*)0x40020400)
-#endif
-
-/*
- * Register bit definitions
- */
-
-/* Interrupt status register */
-
-#define DMA_ISR_TEIF7_BIT               27
-#define DMA_ISR_HTIF7_BIT               26
-#define DMA_ISR_TCIF7_BIT               25
-#define DMA_ISR_GIF7_BIT                24
-#define DMA_ISR_TEIF6_BIT               23
-#define DMA_ISR_HTIF6_BIT               22
-#define DMA_ISR_TCIF6_BIT               21
-#define DMA_ISR_GIF6_BIT                20
-#define DMA_ISR_TEIF5_BIT               19
-#define DMA_ISR_HTIF5_BIT               18
-#define DMA_ISR_TCIF5_BIT               17
-#define DMA_ISR_GIF5_BIT                16
-#define DMA_ISR_TEIF4_BIT               15
-#define DMA_ISR_HTIF4_BIT               14
-#define DMA_ISR_TCIF4_BIT               13
-#define DMA_ISR_GIF4_BIT                12
-#define DMA_ISR_TEIF3_BIT               11
-#define DMA_ISR_HTIF3_BIT               10
-#define DMA_ISR_TCIF3_BIT               9
-#define DMA_ISR_GIF3_BIT                8
-#define DMA_ISR_TEIF2_BIT               7
-#define DMA_ISR_HTIF2_BIT               6
-#define DMA_ISR_TCIF2_BIT               5
-#define DMA_ISR_GIF2_BIT                4
-#define DMA_ISR_TEIF1_BIT               3
-#define DMA_ISR_HTIF1_BIT               2
-#define DMA_ISR_TCIF1_BIT               1
-#define DMA_ISR_GIF1_BIT                0
-
-#define DMA_ISR_TEIF7                   BIT(DMA_ISR_TEIF7_BIT)
-#define DMA_ISR_HTIF7                   BIT(DMA_ISR_HTIF7_BIT)
-#define DMA_ISR_TCIF7                   BIT(DMA_ISR_TCIF7_BIT)
-#define DMA_ISR_GIF7                    BIT(DMA_ISR_GIF7_BIT)
-#define DMA_ISR_TEIF6                   BIT(DMA_ISR_TEIF6_BIT)
-#define DMA_ISR_HTIF6                   BIT(DMA_ISR_HTIF6_BIT)
-#define DMA_ISR_TCIF6                   BIT(DMA_ISR_TCIF6_BIT)
-#define DMA_ISR_GIF6                    BIT(DMA_ISR_GIF6_BIT)
-#define DMA_ISR_TEIF5                   BIT(DMA_ISR_TEIF5_BIT)
-#define DMA_ISR_HTIF5                   BIT(DMA_ISR_HTIF5_BIT)
-#define DMA_ISR_TCIF5                   BIT(DMA_ISR_TCIF5_BIT)
-#define DMA_ISR_GIF5                    BIT(DMA_ISR_GIF5_BIT)
-#define DMA_ISR_TEIF4                   BIT(DMA_ISR_TEIF4_BIT)
-#define DMA_ISR_HTIF4                   BIT(DMA_ISR_HTIF4_BIT)
-#define DMA_ISR_TCIF4                   BIT(DMA_ISR_TCIF4_BIT)
-#define DMA_ISR_GIF4                    BIT(DMA_ISR_GIF4_BIT)
-#define DMA_ISR_TEIF3                   BIT(DMA_ISR_TEIF3_BIT)
-#define DMA_ISR_HTIF3                   BIT(DMA_ISR_HTIF3_BIT)
-#define DMA_ISR_TCIF3                   BIT(DMA_ISR_TCIF3_BIT)
-#define DMA_ISR_GIF3                    BIT(DMA_ISR_GIF3_BIT)
-#define DMA_ISR_TEIF2                   BIT(DMA_ISR_TEIF2_BIT)
-#define DMA_ISR_HTIF2                   BIT(DMA_ISR_HTIF2_BIT)
-#define DMA_ISR_TCIF2                   BIT(DMA_ISR_TCIF2_BIT)
-#define DMA_ISR_GIF2                    BIT(DMA_ISR_GIF2_BIT)
-#define DMA_ISR_TEIF1                   BIT(DMA_ISR_TEIF1_BIT)
-#define DMA_ISR_HTIF1                   BIT(DMA_ISR_HTIF1_BIT)
-#define DMA_ISR_TCIF1                   BIT(DMA_ISR_TCIF1_BIT)
-#define DMA_ISR_GIF1                    BIT(DMA_ISR_GIF1_BIT)
-
-/* Interrupt flag clear register */
-
-#define DMA_IFCR_CTEIF7_BIT             27
-#define DMA_IFCR_CHTIF7_BIT             26
-#define DMA_IFCR_CTCIF7_BIT             25
-#define DMA_IFCR_CGIF7_BIT              24
-#define DMA_IFCR_CTEIF6_BIT             23
-#define DMA_IFCR_CHTIF6_BIT             22
-#define DMA_IFCR_CTCIF6_BIT             21
-#define DMA_IFCR_CGIF6_BIT              20
-#define DMA_IFCR_CTEIF5_BIT             19
-#define DMA_IFCR_CHTIF5_BIT             18
-#define DMA_IFCR_CTCIF5_BIT             17
-#define DMA_IFCR_CGIF5_BIT              16
-#define DMA_IFCR_CTEIF4_BIT             15
-#define DMA_IFCR_CHTIF4_BIT             14
-#define DMA_IFCR_CTCIF4_BIT             13
-#define DMA_IFCR_CGIF4_BIT              12
-#define DMA_IFCR_CTEIF3_BIT             11
-#define DMA_IFCR_CHTIF3_BIT             10
-#define DMA_IFCR_CTCIF3_BIT             9
-#define DMA_IFCR_CGIF3_BIT              8
-#define DMA_IFCR_CTEIF2_BIT             7
-#define DMA_IFCR_CHTIF2_BIT             6
-#define DMA_IFCR_CTCIF2_BIT             5
-#define DMA_IFCR_CGIF2_BIT              4
-#define DMA_IFCR_CTEIF1_BIT             3
-#define DMA_IFCR_CHTIF1_BIT             2
-#define DMA_IFCR_CTCIF1_BIT             1
-#define DMA_IFCR_CGIF1_BIT              0
-
-#define DMA_IFCR_CTEIF7                 BIT(DMA_IFCR_CTEIF7_BIT)
-#define DMA_IFCR_CHTIF7                 BIT(DMA_IFCR_CHTIF7_BIT)
-#define DMA_IFCR_CTCIF7                 BIT(DMA_IFCR_CTCIF7_BIT)
-#define DMA_IFCR_CGIF7                  BIT(DMA_IFCR_CGIF7_BIT)
-#define DMA_IFCR_CTEIF6                 BIT(DMA_IFCR_CTEIF6_BIT)
-#define DMA_IFCR_CHTIF6                 BIT(DMA_IFCR_CHTIF6_BIT)
-#define DMA_IFCR_CTCIF6                 BIT(DMA_IFCR_CTCIF6_BIT)
-#define DMA_IFCR_CGIF6                  BIT(DMA_IFCR_CGIF6_BIT)
-#define DMA_IFCR_CTEIF5                 BIT(DMA_IFCR_CTEIF5_BIT)
-#define DMA_IFCR_CHTIF5                 BIT(DMA_IFCR_CHTIF5_BIT)
-#define DMA_IFCR_CTCIF5                 BIT(DMA_IFCR_CTCIF5_BIT)
-#define DMA_IFCR_CGIF5                  BIT(DMA_IFCR_CGIF5_BIT)
-#define DMA_IFCR_CTEIF4                 BIT(DMA_IFCR_CTEIF4_BIT)
-#define DMA_IFCR_CHTIF4                 BIT(DMA_IFCR_CHTIF4_BIT)
-#define DMA_IFCR_CTCIF4                 BIT(DMA_IFCR_CTCIF4_BIT)
-#define DMA_IFCR_CGIF4                  BIT(DMA_IFCR_CGIF4_BIT)
-#define DMA_IFCR_CTEIF3                 BIT(DMA_IFCR_CTEIF3_BIT)
-#define DMA_IFCR_CHTIF3                 BIT(DMA_IFCR_CHTIF3_BIT)
-#define DMA_IFCR_CTCIF3                 BIT(DMA_IFCR_CTCIF3_BIT)
-#define DMA_IFCR_CGIF3                  BIT(DMA_IFCR_CGIF3_BIT)
-#define DMA_IFCR_CTEIF2                 BIT(DMA_IFCR_CTEIF2_BIT)
-#define DMA_IFCR_CHTIF2                 BIT(DMA_IFCR_CHTIF2_BIT)
-#define DMA_IFCR_CTCIF2                 BIT(DMA_IFCR_CTCIF2_BIT)
-#define DMA_IFCR_CGIF2                  BIT(DMA_IFCR_CGIF2_BIT)
-#define DMA_IFCR_CTEIF1                 BIT(DMA_IFCR_CTEIF1_BIT)
-#define DMA_IFCR_CHTIF1                 BIT(DMA_IFCR_CHTIF1_BIT)
-#define DMA_IFCR_CTCIF1                 BIT(DMA_IFCR_CTCIF1_BIT)
-#define DMA_IFCR_CGIF1                  BIT(DMA_IFCR_CGIF1_BIT)
-
-/* Channel configuration register */
-
-#define DMA_CCR_MEM2MEM_BIT             14
-#define DMA_CCR_MINC_BIT                7
-#define DMA_CCR_PINC_BIT                6
-#define DMA_CCR_CIRC_BIT                5
-#define DMA_CCR_DIR_BIT                 4
-#define DMA_CCR_TEIE_BIT                3
-#define DMA_CCR_HTIE_BIT                2
-#define DMA_CCR_TCIE_BIT                1
-#define DMA_CCR_EN_BIT                  0
-
-#define DMA_CCR_MEM2MEM                 BIT(DMA_CCR_MEM2MEM_BIT)
-#define DMA_CCR_PL                      (0x3 << 12)
-#define DMA_CCR_PL_LOW                  (0x0 << 12)
-#define DMA_CCR_PL_MEDIUM               (0x1 << 12)
-#define DMA_CCR_PL_HIGH                 (0x2 << 12)
-#define DMA_CCR_PL_VERY_HIGH            (0x3 << 12)
-#define DMA_CCR_MSIZE                   (0x3 << 10)
-#define DMA_CCR_MSIZE_8BITS             (0x0 << 10)
-#define DMA_CCR_MSIZE_16BITS            (0x1 << 10)
-#define DMA_CCR_MSIZE_32BITS            (0x2 << 10)
-#define DMA_CCR_PSIZE                   (0x3 << 8)
-#define DMA_CCR_PSIZE_8BITS             (0x0 << 8)
-#define DMA_CCR_PSIZE_16BITS            (0x1 << 8)
-#define DMA_CCR_PSIZE_32BITS            (0x2 << 8)
-#define DMA_CCR_MINC                    BIT(DMA_CCR_MINC_BIT)
-#define DMA_CCR_PINC                    BIT(DMA_CCR_PINC_BIT)
-#define DMA_CCR_CIRC                    BIT(DMA_CCR_CIRC_BIT)
-#define DMA_CCR_DIR                     BIT(DMA_CCR_DIR_BIT)
-#define DMA_CCR_TEIE                    BIT(DMA_CCR_TEIE_BIT)
-#define DMA_CCR_HTIE                    BIT(DMA_CCR_HTIE_BIT)
-#define DMA_CCR_TCIE                    BIT(DMA_CCR_TCIE_BIT)
-#define DMA_CCR_EN                      BIT(DMA_CCR_EN_BIT)
-
-/*
- * Devices
- */
-
-/** Encapsulates state related to a DMA channel interrupt. */
-typedef struct dma_handler_config {
-    void (*handler)(void);      /**< User-specified channel interrupt
-                                     handler */
-    nvic_irq_num irq_line;      /**< Channel's NVIC interrupt number */
-} dma_handler_config;
-
-/** DMA device type */
-typedef struct dma_dev {
-    dma_reg_map *regs;             /**< Register map */
-    rcc_clk_id clk_id;             /**< Clock ID */
-    dma_handler_config handlers[]; /**<
-                                    * @brief IRQ handlers and NVIC numbers.
-                                    *
-                                    * @see dma_attach_interrupt()
-                                    * @see dma_detach_interrupt()
-                                    */
-} dma_dev;
-
-extern dma_dev *DMA1;
-#ifdef STM32_HIGH_DENSITY
-extern dma_dev *DMA2;
-#endif
-
-/*
- * Convenience functions
- */
-
-void dma_init(dma_dev *dev);
-
-/** Flags for DMA transfer configuration. */
-typedef enum dma_mode_flags {
-    DMA_MEM_2_MEM  = 1 << 14, /**< Memory to memory mode */
-    DMA_MINC_MODE  = 1 << 7,  /**< Auto-increment memory address */
-    DMA_PINC_MODE  = 1 << 6,  /**< Auto-increment peripheral address */
-    DMA_CIRC_MODE  = 1 << 5,  /**< Circular mode */
-    DMA_FROM_MEM   = 1 << 4,  /**< Read from memory to peripheral */
-    DMA_TRNS_ERR   = 1 << 3,  /**< Interrupt on transfer error */
-    DMA_HALF_TRNS  = 1 << 2,  /**< Interrupt on half-transfer */
-    DMA_TRNS_CMPLT = 1 << 1   /**< Interrupt on transfer completion */
-} dma_mode_flags;
-
-/** Source and destination transfer sizes. */
-typedef enum dma_xfer_size {
-    DMA_SIZE_8BITS  = 0,        /**< 8-bit transfers */
-    DMA_SIZE_16BITS = 1,        /**< 16-bit transfers */
-    DMA_SIZE_32BITS = 2         /**< 32-bit transfers */
-} dma_xfer_size;
-
-/** DMA channel */
-typedef enum dma_channel {
-    DMA_CH1 = 1,                /**< Channel 1 */
-    DMA_CH2 = 2,                /**< Channel 2 */
-    DMA_CH3 = 3,                /**< Channel 3 */
-    DMA_CH4 = 4,                /**< Channel 4 */
-    DMA_CH5 = 5,                /**< Channel 5 */
-    DMA_CH6 = 6,                /**< Channel 6 */
-    DMA_CH7 = 7,                /**< Channel 7 */
-} dma_channel;
-
-void dma_setup_transfer(dma_dev       *dev,
-                        dma_channel    channel,
-                        __io void     *peripheral_address,
-                        dma_xfer_size  peripheral_size,
-                        __io void     *memory_address,
-                        dma_xfer_size  memory_size,
-                        uint32         mode);
-
-void dma_set_num_transfers(dma_dev *dev,
-                           dma_channel channel,
-                           uint16 num_transfers);
-
-/** DMA transfer priority. */
-typedef enum dma_priority {
-    DMA_PRIORITY_LOW       = DMA_CCR_PL_LOW,      /**< Low priority */
-    DMA_PRIORITY_MEDIUM    = DMA_CCR_PL_MEDIUM,   /**< Medium priority */
-    DMA_PRIORITY_HIGH      = DMA_CCR_PL_HIGH,     /**< High priority */
-    DMA_PRIORITY_VERY_HIGH = DMA_CCR_PL_VERY_HIGH /**< Very high priority */
-} dma_priority;
-
-void dma_set_priority(dma_dev *dev,
-                      dma_channel channel,
-                      dma_priority priority);
-
-void dma_attach_interrupt(dma_dev *dev,
-                          dma_channel channel,
-                          void (*handler)(void));
-void dma_detach_interrupt(dma_dev *dev, dma_channel channel);
-
-/**
- * Encodes the reason why a DMA interrupt was called.
- * @see dma_get_irq_cause()
- */
-typedef enum dma_irq_cause {
-    DMA_TRANSFER_COMPLETE,      /**< Transfer is complete. */
-    DMA_TRANSFER_HALF_COMPLETE, /**< Transfer is half complete. */
-    DMA_TRANSFER_ERROR,         /**< Error occurred during transfer. */
-} dma_irq_cause;
-
-dma_irq_cause dma_get_irq_cause(dma_dev *dev, dma_channel channel);
-
-void dma_enable(dma_dev *dev, dma_channel channel);
-void dma_disable(dma_dev *dev, dma_channel channel);
-
-void dma_set_mem_addr(dma_dev *dev, dma_channel channel, __io void *address);
-void dma_set_per_addr(dma_dev *dev, dma_channel channel, __io void *address);
-
-/**
- * @brief DMA channel register map type.
- *
- * Provides access to an individual channel's registers.
- */
-typedef struct dma_channel_reg_map {
-    __io uint32 CCR;           /**< Channel configuration register */
-    __io uint32 CNDTR;         /**< Channel number of data register */
-    __io uint32 CPAR;          /**< Channel peripheral address register */
-    __io uint32 CMAR;          /**< Channel memory address register */
-} dma_channel_reg_map;
-
-#define DMA_CHANNEL_NREGS 5
-
-/**
- * @brief Obtain a pointer to an individual DMA channel's registers.
- *
- * For example, dma_channel_regs(DMA1, DMA_CH1)->CCR is DMA1_BASE->CCR1.
- *
- * @param dev DMA device
- * @param channel DMA channel whose channel register map to obtain.
- */
-static inline dma_channel_reg_map* dma_channel_regs(dma_dev *dev,
-                                                    dma_channel channel) {
-    __io uint32 *ccr1 = &dev->regs->CCR1;
-    return (dma_channel_reg_map*)(ccr1 + DMA_CHANNEL_NREGS * (channel - 1));
-}
-
-/**
- * @brief Check if a DMA channel is enabled
- * @param dev DMA device
- * @param channel Channel whose enabled bit to check.
- */
-static inline uint8 dma_is_channel_enabled(dma_dev *dev, dma_channel channel) {
-    return (uint8)(dma_channel_regs(dev, channel)->CCR & DMA_CCR_EN);
-}
-
-/**
- * @brief Get the ISR status bits for a DMA channel.
- *
- * The bits are returned right-aligned, in the following order:
- * transfer error flag, half-transfer flag, transfer complete flag,
- * global interrupt flag.
- *
- * If you're attempting to figure out why a DMA interrupt fired; you
- * may find dma_get_irq_cause() more convenient.
- *
- * @param dev DMA device
- * @param channel Channel whose ISR bits to return.
- * @see dma_get_irq_cause().
- */
-static inline uint8 dma_get_isr_bits(dma_dev *dev, dma_channel channel) {
-    uint8 shift = (channel - 1) * 4;
-    return (dev->regs->ISR >> shift) & 0xF;
-}
-
-/**
- * @brief Clear the ISR status bits for a given DMA channel.
- *
- * If you're attempting to clean up after yourself in a DMA interrupt,
- * you may find dma_get_irq_cause() more convenient.
- *
- * @param dev DMA device
- * @param channel Channel whose ISR bits to clear.
- * @see dma_get_irq_cause()
- */
-static inline void dma_clear_isr_bits(dma_dev *dev, dma_channel channel) {
-    dev->regs->IFCR = BIT(4 * (channel - 1));
-}
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
-#endif
diff --git a/STM32F4/cores/maple/libmaple/dmaF2.c b/STM32F4/cores/maple/libmaple/dmaF2.c
deleted file mode 100644
index 0911e584a..000000000
--- a/STM32F4/cores/maple/libmaple/dmaF2.c
+++ /dev/null
@@ -1,241 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Michael Hope.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
- #ifdef STM32F2
- 
-/**
- * @file dmaF2.c
- * @brief Direct Memory Access peripheral support
- */
-
-#include "dma.h"
-#include "bitband.h"
-#include "util.h"
-
-/*
- * Devices
- */
-
-static dma_dev dma1 = {
-    .regs     = DMA1_BASE,
-    .clk_id   = RCC_DMA1,
-    .handlers = {{ .handler = NULL, .irq_line = 11 },
-                 { .handler = NULL, .irq_line = 12 },
-                 { .handler = NULL, .irq_line = 13 },
-                 { .handler = NULL, .irq_line = 14 },
-                 { .handler = NULL, .irq_line = 15 },
-                 { .handler = NULL, .irq_line = 16 },
-                 { .handler = NULL, .irq_line = 17 },
-                 { .handler = NULL, .irq_line = 47 }}
-};
-/** DMA1 device */
-dma_dev *DMA1 = &dma1;
-
-static dma_dev dma2 = {
-    .regs     = DMA2_BASE,
-    .clk_id   = RCC_DMA2,
-    .handlers = {{ .handler = NULL, .irq_line = 56 },
-                 { .handler = NULL, .irq_line = 57 },
-                 { .handler = NULL, .irq_line = 58 },
-                 { .handler = NULL, .irq_line = 59 },
-                 { .handler = NULL, .irq_line = 60 },
-                 { .handler = NULL, .irq_line = 68 },
-                 { .handler = NULL, .irq_line = 69 },
-                 { .handler = NULL, .irq_line = 70 }} /* !@#$ */
-};
-/** DMA2 device */
-dma_dev *DMA2 = &dma2;
-
-
-/*
- * Convenience routines
- */
-
-/**
- * @brief Initialize a DMA device.
- * @param dev Device to initialize.
- */
-void dma_init(dma_dev *dev) {
-    rcc_clk_enable(dev->clk_id);
-}
-
-/**
- * @brief Attach an interrupt to a DMA transfer.
- *
- * Interrupts are enabled using appropriate mode flags in
- * dma_setup_transfer().
- *
- * @param dev DMA device
- * @param stream Stream to attach handler to
- * @param handler Interrupt handler to call when channel interrupt fires.
- * @see dma_setup_transfer()
- * @see dma_detach_interrupt()
- */
-void dma_attach_interrupt(dma_dev *dev,
-                          dma_stream stream,
-                          void (*handler)(void)) {
-    dev->handlers[stream].handler = handler;
-    nvic_irq_enable(dev->handlers[stream].irq_line);
-}
-
-/**
- * @brief Detach a DMA transfer interrupt handler.
- *
- * After calling this function, the given channel's interrupts will be
- * disabled.
- *
- * @param dev DMA device
- * @param stream Stream whose handler to detach
- * @sideeffect Clears interrupt enable bits in the channel's CCR register.
- * @see dma_attach_interrupt()
- */
-void dma_detach_interrupt(dma_dev *dev, dma_stream stream) {
-    nvic_irq_disable(dev->handlers[stream].irq_line);
-    dev->handlers[stream].handler = NULL;
-}
-
-void dma_clear_isr_bits(dma_dev *dev, dma_stream stream) {
-    switch (stream) {
-    case 0:
-        dev->regs->LIFCR|=0x0000003d;
-        break;
-    case 1:
-        dev->regs->LIFCR|=0x00000f40;
-        break;
-    case 2:
-        dev->regs->LIFCR|=0x003d0000;
-        break;
-    case 3:
-        dev->regs->LIFCR|=0x0f400000;
-        break;
-    case 4:
-        dev->regs->HIFCR|=0x0000003d;
-        break;
-    case 5:
-        dev->regs->HIFCR|=0x00000f40;
-        break;
-    case 6:
-        dev->regs->HIFCR|=0x003d0000;
-        break;
-    case 7:
-        dev->regs->HIFCR|=0x0f400000;
-        break;
-    }
-}
-
-/*
- * IRQ handlers
- */
-
-static inline void dispatch_handler(dma_dev *dev, dma_stream stream) {
-    void (*handler)(void) = dev->handlers[stream].handler;
-    if (handler) {
-        handler();
-        dma_clear_isr_bits(dev, stream); /* in case handler doesn't */
-    }
-}
-
-//void __irq_dma1_stream0(void) {
-void __irq_dma1_channel1(void) {
-    dispatch_handler(DMA1, DMA_STREAM0);
-}
-
-//void __irq_dma1_stream1(void) {
-void __irq_dma1_channel2(void) {
-    dispatch_handler(DMA1, DMA_STREAM1);
-}
-
-//void __irq_dma1_stream2(void) {
-void __irq_dma1_channel3(void) {
-    dispatch_handler(DMA1, DMA_STREAM2);
-}
-
-//void __irq_dma1_stream3(void) {
-void __irq_dma1_channel4(void) {
-    dispatch_handler(DMA1, DMA_STREAM3);
-}
-
-//void __irq_dma1_stream4(void) {
-void __irq_dma1_channel5(void) {
-    dispatch_handler(DMA1, DMA_STREAM4);
-}
-
-//void __irq_dma1_stream5(void) {
-void __irq_dma1_channel6(void) {
-    dispatch_handler(DMA1, DMA_STREAM5);
-}
-
-//void __irq_dma1_stream6(void) {
-void __irq_dma1_channel7(void) {
-    dispatch_handler(DMA1, DMA_STREAM6);
-}
-
-//void __irq_dma1_stream7(void) {
-void __irq_adc3(void) {
-    dispatch_handler(DMA1, DMA_STREAM7);
-}
-
-//void __irq_dma2_stream0(void) {
-void __irq_dma2_channel1(void) {
-    dispatch_handler(DMA2, DMA_STREAM0);
-}
-
-//void __irq_dma2_stream1(void) {
-void __irq_dma2_channel2(void) {
-    dispatch_handler(DMA2, DMA_STREAM1);
-}
-
-//void __irq_dma2_stream2(void) {
-void __irq_dma2_channel3(void) {
-    dispatch_handler(DMA2, DMA_STREAM2);
-}
-
-//void __irq_dma2_stream3(void) {
-void __irq_dma2_channel4_5(void) {
-    dispatch_handler(DMA2, DMA_STREAM3);
-}
-
-//void __irq_dma2_stream4(void) {
-void __irq_DMA2_Stream4_IRQHandler(void) {
-    dispatch_handler(DMA2, DMA_STREAM4);
-}
-
-//void __irq_dma2_stream5(void) {
-void __irq_DMA2_Stream5_IRQHandler(void) {
-    dispatch_handler(DMA2, DMA_STREAM5);
-}
-
-//void __irq_dma2_stream6(void) {
-void __irq_DMA2_Stream6_IRQHandler(void) {
-    dispatch_handler(DMA2, DMA_STREAM6);
-}
-
-//void __irq_dma2_stream7(void) {
-void __irq_DMA2_Stream7_IRQHandler(void) {
-    dispatch_handler(DMA2, DMA_STREAM7);
-}
-
-#endif
diff --git a/STM32F4/cores/maple/libmaple/dmaF2.h b/STM32F4/cores/maple/libmaple/dmaF2.h
deleted file mode 100644
index 6f7086f36..000000000
--- a/STM32F4/cores/maple/libmaple/dmaF2.h
+++ /dev/null
@@ -1,270 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Michael Hope.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file dma.h
- *
- * @author Marti Bolivar <mbolivar@leaflabs.com>;
- *         Original implementation by Michael Hope
- *
- * @brief Direct Memory Access peripheral support
- */
-
-/*
- * See /notes/dma.txt for more information.
- */
-
-#ifndef _DMA_H_
-#define _DMA_H_
-
-#include "libmaple_types.h"
-#include "rcc.h"
-#include "nvic.h"
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-/*
- * Register maps
- */
-
-/**
- * @brief DMA stream type.
- *
- */
-typedef struct dma_stream_t {
-    __io uint32 CR;           /**< Stream configuration register */
-    __io uint32 NDTR;         /**< Stream number of data register */
-    __io uint32 PAR;          /**< Stream peripheral address register */
-    __io uint32 M0AR;         /**< Stream memory address register 0 */
-    __io uint32 M1AR;         /**< Stream memory address register 1 */
-    __io uint32 FCR;           /**< Stream FIFO configuration register */
-} dma_stream_t;
-/**
- * @brief DMA register map type.
- *
- */
-typedef struct dma_reg_map {
-    __io uint32 LISR;           /**< Low interrupt status register */
-    __io uint32 HISR;           /**< High interrupt status register */
-    __io uint32 LIFCR;          /**< Low interrupt flag clear register */
-    __io uint32 HIFCR;          /**< High interrupt flag clear register */
-    dma_stream_t  STREAM[8];
-} dma_reg_map;
-
-/** DMA controller register map base pointers */
-#define DMA1_BASE                       ((struct dma_reg_map*)0x40026000)
-#define DMA2_BASE                       ((struct dma_reg_map*)0x40026400)
-
-/*
- * Register bit definitions
- */
-
-/* Channel configuration register */
-
-#define DMA_CR_CH0                      (0x0 << 25)
-#define DMA_CR_CH1                      (0x1 << 25)
-#define DMA_CR_CH2                      (0x2 << 25)
-#define DMA_CR_CH3                      (0x3 << 25)
-#define DMA_CR_CH4                      (0x4 << 25)
-#define DMA_CR_CH5                      (0x5 << 25)
-#define DMA_CR_CH6                      (0x6 << 25)
-#define DMA_CR_CH7                      (0x7 << 25)
-#define DMA_CR_MBURST0                  (0x0 << 23)
-#define DMA_CR_MBURST4                  (0x1 << 23)
-#define DMA_CR_MBURST8                  (0x2 << 23)
-#define DMA_CR_MBURST16                 (0x3 << 23)
-#define DMA_CR_PBURST0                  (0x0 << 21)
-#define DMA_CR_PBURST4                  (0x1 << 21)
-#define DMA_CR_PBURST8                  (0x2 << 21)
-#define DMA_CR_PBURST16                 (0x3 << 21)
-#define DMA_CR_CT0                      (0x0 << 19)
-#define DMA_CR_CT1                      (0x1 << 19)
-#define DMA_CR_DBM                      (0x1 << 18)
-
-#define DMA_CR_PL_LOW                   (0x0 << 16)
-#define DMA_CR_PL_MEDIUM                (0x1 << 16)
-#define DMA_CR_PL_HIGH                  (0x2 << 16)
-#define DMA_CR_PL_VERY_HIGH             (0x3 << 16)
-#define DMA_CR_PL_MASK                  (0x3 << 16)
-
-#define DMA_CR_PINCOS                   (0x1 << 15)
-
-#define DMA_CR_MSIZE_8BITS              (0x0 << 13)
-#define DMA_CR_MSIZE_16BITS             (0x1 << 13)
-#define DMA_CR_MSIZE_32BITS             (0x2 << 13)
-
-#define DMA_CR_PSIZE_8BITS              (0x0 << 11)
-#define DMA_CR_PSIZE_16BITS             (0x1 << 11)
-#define DMA_CR_PSIZE_32BITS             (0x2 << 11)
-
-#define DMA_CR_MINC                     (0x1 << 10)
-#define DMA_CR_PINC                     (0x1 << 9)
-#define DMA_CR_CIRC                     (0x1 << 8)
-#define DMA_CR_DIR_P2M                  (0x0 << 6)
-#define DMA_CR_DIR_M2P                  (0x1 << 6)
-#define DMA_CR_DIR_M2M                  (0x2 << 6)
-
-#define DMA_CR_PFCTRL                   (0x1 << 5)
-#define DMA_CR_TCIE                     (0x1 << 4)
-#define DMA_CR_HTIE                     (0x1 << 3)
-#define DMA_CR_TEIE                     (0x1 << 2)
-#define DMA_CR_DMEIE                    (0x1 << 1)
-#define DMA_CR_EN                       (0x1)
-
-/*
- * Devices
- */
-
-/** Encapsulates state related to a DMA channel interrupt. */
-typedef struct dma_handler_config {
-    void (*handler)(void);      /**< User-specified channel interrupt
-                                     handler */
-    nvic_irq_num irq_line;      /**< Channel's NVIC interrupt number */
-} dma_handler_config;
-
-/** DMA device type */
-typedef struct dma_dev {
-    dma_reg_map *regs;             /**< Register map */
-    rcc_clk_id clk_id;             /**< Clock ID */
-    dma_handler_config handlers[]; /**<
-                                    * @brief IRQ handlers and NVIC numbers.
-                                    *
-                                    * @see dma_attach_interrupt()
-                                    * @see dma_detach_interrupt()
-                                    */
-} dma_dev;
-
-extern dma_dev *DMA1;
-extern dma_dev *DMA2;
-
-/*
- * Convenience functions
- */
-
-void dma_init(dma_dev *dev);
-
-/** Flags for DMA transfer configuration. */
-typedef enum dma_mode_flags {
-    DMA_MEM_2_MEM  = 1 << 14, /**< Memory to memory mode */
-    DMA_MINC_MODE  = 1 << 7,  /**< Auto-increment memory address */
-    DMA_PINC_MODE  = 1 << 6,  /**< Auto-increment peripheral address */
-    DMA_CIRC_MODE  = 1 << 5,  /**< Circular mode */
-    DMA_FROM_MEM   = 1 << 4,  /**< Read from memory to peripheral */
-    DMA_TRNS_ERR   = 1 << 3,  /**< Interrupt on transfer error */
-    DMA_HALF_TRNS  = 1 << 2,  /**< Interrupt on half-transfer */
-    DMA_TRNS_CMPLT = 1 << 1   /**< Interrupt on transfer completion */
-} dma_mode_flags;
-
-/** Source and destination transfer sizes. */
-typedef enum dma_xfer_size {
-    DMA_SIZE_8BITS  = 0,        /**< 8-bit transfers */
-    DMA_SIZE_16BITS = 1,        /**< 16-bit transfers */
-    DMA_SIZE_32BITS = 2         /**< 32-bit transfers */
-} dma_xfer_size;
-
-/** DMA channel */
-typedef enum dma_stream {
-    DMA_STREAM0 = 0,                /**< Stream 0 */
-    DMA_STREAM1 = 1,                /**< Stream 1 */
-    DMA_STREAM2 = 2,                /**< Stream 2 */
-    DMA_STREAM3 = 3,                /**< Stream 3 */
-    DMA_STREAM4 = 4,                /**< Stream 4 */
-    DMA_STREAM5 = 5,                /**< Stream 5 */
-    DMA_STREAM6 = 6,                /**< Stream 6 */
-    DMA_STREAM7 = 7,                /**< Stream 7 */
-} dma_stream;
-    
-static inline void dma_setup_transfer(dma_dev       *dev,
-                                      dma_stream    stream,
-                                      __io void     *peripheral_address,
-                                      __io void     *memory_address0,
-                                      __io void     *memory_address1,
-                                      uint32         flags,
-                                      uint32         fifo_flags) {
-    dev->regs->STREAM[stream].CR &= ~DMA_CR_EN; // disable
-    dev->regs->STREAM[stream].PAR = (uint32)peripheral_address;
-    dev->regs->STREAM[stream].M0AR = (uint32)memory_address0;
-    dev->regs->STREAM[stream].M1AR = (uint32)memory_address1;
-    dev->regs->STREAM[stream].FCR = fifo_flags & 0x87; // mask out reserved bits
-    dev->regs->STREAM[stream].CR = flags & 0x0feffffe; // mask out reserved and enable
-}
-    
-static inline void dma_set_num_transfers(dma_dev *dev,
-                                         dma_stream stream,
-                                         uint16 num_transfers) {
-    dev->regs->STREAM[stream].NDTR = num_transfers;
-}
-
-void dma_attach_interrupt(dma_dev *dev,
-                          dma_stream stream,
-                          void (*handler)(void));
-
-void dma_detach_interrupt(dma_dev *dev, dma_stream stream);
-
-static inline void dma_enable(dma_dev *dev, dma_stream stream) {
-    dev->regs->STREAM[stream].CR |= DMA_CR_EN;
-}    
-
-static inline void dma_disable(dma_dev *dev, dma_stream stream) {
-    dev->regs->STREAM[stream].CR &= ~DMA_CR_EN;
-}    
-
-/**
- * @brief Check if a DMA stream is enabled
- * @param dev DMA device
- * @param stream Stream whose enabled bit to check.
- */
-static inline uint8 dma_is_stream_enabled(dma_dev *dev, dma_stream stream) {
-    return (uint8)(dev->regs->STREAM[stream].CR & DMA_CR_EN);
-}
-
-/**
- * @brief Get the ISR status bits for a DMA stream.
- *
- * The bits are returned right-aligned, in the following order:
- * transfer error flag, half-transfer flag, transfer complete flag,
- * global interrupt flag.
- *
- * @param dev DMA device
- * @param stream Stream whose ISR bits to return.
- */
-uint8 dma_get_isr_bits(dma_dev *dev, dma_stream stream);
-
-/**
- * @brief Clear the ISR status bits for a given DMA stream.
- *
- * @param dev DMA device
- * @param stream Stream whose ISR bits to clear.
- */
-void dma_clear_isr_bits(dma_dev *dev, dma_stream stream);
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
-#endif
diff --git a/STM32F4/cores/maple/libmaple/gpio.c b/STM32F4/cores/maple/libmaple/gpio.c
deleted file mode 100644
index 3792220e3..000000000
--- a/STM32F4/cores/maple/libmaple/gpio.c
+++ /dev/null
@@ -1,36 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file gpio.c
- * @brief GPIO initialization routine
- */
-
-// #ifdef STM32F2
-// #include "gpioF2.c"
-// #else
-// #include "gpioF1.c"
-// #endif
diff --git a/STM32F4/cores/maple/libmaple/gpioF1.c b/STM32F4/cores/maple/libmaple/gpioF1.c
deleted file mode 100644
index 846b7542a..000000000
--- a/STM32F4/cores/maple/libmaple/gpioF1.c
+++ /dev/null
@@ -1,200 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-#ifdef STM32F1
-
-/**
- * @file gpio.c
- * @brief GPIO initialization routine
- */
-
-#include "gpio.h"
-#include "rcc.h"
-
-/*
- * GPIO devices
- */
-
-gpio_dev gpioa = {
-    .regs      = GPIOA_BASE,
-    .clk_id    = RCC_GPIOA,
-    .exti_port = AFIO_EXTI_PA,
-};
-/** GPIO port A device. */
-gpio_dev* const GPIOA = &gpioa;
-
-gpio_dev gpiob = {
-    .regs      = GPIOB_BASE,
-    .clk_id    = RCC_GPIOB,
-    .exti_port = AFIO_EXTI_PB,
-};
-/** GPIO port B device. */
-gpio_dev* const GPIOB = &gpiob;
-
-gpio_dev gpioc = {
-    .regs      = GPIOC_BASE,
-    .clk_id    = RCC_GPIOC,
-    .exti_port = AFIO_EXTI_PC,
-};
-/** GPIO port C device. */
-gpio_dev* const GPIOC = &gpioc;
-
-gpio_dev gpiod = {
-    .regs      = GPIOD_BASE,
-    .clk_id    = RCC_GPIOD,
-    .exti_port = AFIO_EXTI_PD,
-};
-/** GPIO port D device. */
-gpio_dev* const GPIOD = &gpiod;
-
-#ifdef STM32_HIGH_DENSITY
-gpio_dev gpioe = {
-    .regs      = GPIOE_BASE,
-    .clk_id    = RCC_GPIOE,
-    .exti_port = AFIO_EXTI_PE,
-};
-/** GPIO port E device. */
-gpio_dev* const GPIOE = &gpioe;
-
-gpio_dev gpiof = {
-    .regs      = GPIOF_BASE,
-    .clk_id    = RCC_GPIOF,
-    .exti_port = AFIO_EXTI_PF,
-};
-/** GPIO port F device. */
-gpio_dev* const GPIOF = &gpiof;
-
-gpio_dev gpiog = {
-    .regs      = GPIOG_BASE,
-    .clk_id    = RCC_GPIOG,
-    .exti_port = AFIO_EXTI_PG,
-};
-/** GPIO port G device. */
-gpio_dev* const GPIOG = &gpiog;
-#endif
-
-/*
- * GPIO convenience routines
- */
-
-/**
- * Initialize a GPIO device.
- *
- * Enables the clock for and resets the given device.
- *
- * @param dev GPIO device to initialize.
- */
-void gpio_init(gpio_dev *dev) {
-    rcc_clk_enable(dev->clk_id);
-    rcc_reset_dev(dev->clk_id);
-}
-
-/**
- * Initialize and reset all available GPIO devices.
- */
-void gpio_init_all(void) {
-    gpio_init(GPIOA);
-    gpio_init(GPIOB);
-    gpio_init(GPIOC);
-    gpio_init(GPIOD);
-#ifdef STM32_HIGH_DENSITY
-    gpio_init(GPIOE);
-    gpio_init(GPIOF);
-    gpio_init(GPIOG);
-#endif
-}
-
-/**
- * Set the mode of a GPIO pin.
- *
- * @param dev GPIO device.
- * @param pin Pin on the device whose mode to set, 0--15.
- * @param mode General purpose or alternate function mode to set the pin to.
- * @see gpio_pin_mode
- */
-void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode) {
-    gpio_reg_map *regs = dev->regs;
-    __io uint32 *cr = &regs->CRL + (pin >> 3);
-    uint32 shift = (pin & 0x7) * 4;
-    uint32 tmp = *cr;
-
-    tmp &= ~(0xF << shift);
-    tmp |= (mode == GPIO_INPUT_PU ? GPIO_INPUT_PD : mode) << shift;
-    *cr = tmp;
-
-    if (mode == GPIO_INPUT_PD) {
-        regs->ODR &= ~BIT(pin);
-    } else if (mode == GPIO_INPUT_PU) {
-        regs->ODR |= BIT(pin);
-    }
-}
-
-/*
- * AFIO
- */
-
-/**
- * @brief Initialize the AFIO clock, and reset the AFIO registers.
- */
-void afio_init(void) {
-    rcc_clk_enable(RCC_AFIO);
-    rcc_reset_dev(RCC_AFIO);
-}
-
-#define AFIO_EXTI_SEL_MASK 0xF
-
-/**
- * @brief Select a source input for an external interrupt.
- *
- * @param exti      External interrupt.
- * @param gpio_port Port which contains pin to use as source input.
- * @see afio_exti_num
- * @see afio_exti_port
- */
-void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port) {
-    __io uint32 *exti_cr = &AFIO_BASE->EXTICR1 + exti / 4;
-    uint32 shift = 4 * (exti % 4);
-    uint32 cr = *exti_cr;
-
-    cr &= ~(AFIO_EXTI_SEL_MASK << shift);
-    cr |= gpio_port << shift;
-    *exti_cr = cr;
-}
-
-/**
- * @brief Perform an alternate function remap.
- * @param remapping Remapping to perform.
- */
-void afio_remap(afio_remap_peripheral remapping) {
-    if (remapping & AFIO_REMAP_USE_MAPR2) {
-        remapping &= ~AFIO_REMAP_USE_MAPR2;
-        AFIO_BASE->MAPR2 |= remapping;
-    } else {
-        AFIO_BASE->MAPR |= remapping;
-    }
-}
-
-#endif
diff --git a/STM32F4/cores/maple/libmaple/gpioF1.h b/STM32F4/cores/maple/libmaple/gpioF1.h
deleted file mode 100644
index c69efb417..000000000
--- a/STM32F4/cores/maple/libmaple/gpioF1.h
+++ /dev/null
@@ -1,530 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
-*****************************************************************************/
-
-/**
- *  @file gpio.h
- *
- *  @brief General purpose I/O (GPIO) and Alternate Function I/O
- *         (AFIO) prototypes, defines, and inlined access functions.
- */
-
-#ifndef _GPIO_H_
-#define _GPIO_H_
-
-#include "libmaple.h"
-#include "rcc.h"
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-/*
- * GPIO register maps and devices
- */
-
-/** GPIO register map type */
-typedef struct gpio_reg_map {
-    __io uint32 CRL;      /**< Port configuration register low */
-    __io uint32 CRH;      /**< Port configuration register high */
-    __io uint32 IDR;      /**< Port input data register */
-    __io uint32 ODR;      /**< Port output data register */
-    __io uint32 BSRR;     /**< Port bit set/reset register */
-    __io uint32 BRR;      /**< Port bit reset register */
-    __io uint32 LCKR;     /**< Port configuration lock register */
-} gpio_reg_map;
-
-/**
- * @brief External interrupt line port selector.
- *
- * Used to determine which GPIO port to map an external interrupt line
- * onto. */
-/* (See AFIO sections, below) */
-typedef enum afio_exti_port {
-    AFIO_EXTI_PA,               /**< Use port A (PAx) pin. */
-    AFIO_EXTI_PB,               /**< Use port B (PBx) pin. */
-    AFIO_EXTI_PC,               /**< Use port C (PCx) pin. */
-    AFIO_EXTI_PD,               /**< Use port D (PDx) pin. */
-#ifdef STM32_HIGH_DENSITY
-    AFIO_EXTI_PE,               /**< Use port E (PEx) pin. */
-    AFIO_EXTI_PF,               /**< Use port F (PFx) pin. */
-    AFIO_EXTI_PG,               /**< Use port G (PGx) pin. */
-#endif
-} afio_exti_port;
-
-/** GPIO device type */
-typedef struct gpio_dev {
-    gpio_reg_map *regs;       /**< Register map */
-    rcc_clk_id clk_id;        /**< RCC clock information */
-    afio_exti_port exti_port; /**< AFIO external interrupt port value */
-} gpio_dev;
-
-extern gpio_dev gpioa;
-extern gpio_dev* const GPIOA;
-extern gpio_dev gpiob;
-extern gpio_dev* const GPIOB;
-extern gpio_dev gpioc;
-extern gpio_dev* const GPIOC;
-extern gpio_dev gpiod;
-extern gpio_dev* const GPIOD;
-#ifdef STM32_HIGH_DENSITY
-extern gpio_dev gpioe;
-extern gpio_dev* const GPIOE;
-extern gpio_dev gpiof;
-extern gpio_dev* const GPIOF;
-extern gpio_dev gpiog;
-extern gpio_dev* const GPIOG;
-#endif
-
-/** GPIO port A register map base pointer */
-#define GPIOA_BASE                      ((struct gpio_reg_map*)0x40010800)
-/** GPIO port B register map base pointer */
-#define GPIOB_BASE                      ((struct gpio_reg_map*)0x40010C00)
-/** GPIO port C register map base pointer */
-#define GPIOC_BASE                      ((struct gpio_reg_map*)0x40011000)
-/** GPIO port D register map base pointer */
-#define GPIOD_BASE                      ((struct gpio_reg_map*)0x40011400)
-#ifdef STM32_HIGH_DENSITY
-/** GPIO port E register map base pointer */
-#define GPIOE_BASE                      ((struct gpio_reg_map*)0x40011800)
-/** GPIO port F register map base pointer */
-#define GPIOF_BASE                      ((struct gpio_reg_map*)0x40011C00)
-/** GPIO port G register map base pointer */
-#define GPIOG_BASE                      ((struct gpio_reg_map*)0x40012000)
-#endif
-
-/*
- * GPIO register bit definitions
- */
-
-/* Control registers, low and high */
-
-#define GPIO_CR_CNF                     (0x3 << 2)
-#define GPIO_CR_CNF_INPUT_ANALOG        (0x0 << 2)
-#define GPIO_CR_CNF_INPUT_FLOATING      (0x1 << 2)
-#define GPIO_CR_CNF_INPUT_PU_PD         (0x2 << 2)
-#define GPIO_CR_CNF_OUTPUT_PP           (0x0 << 2)
-#define GPIO_CR_CNF_OUTPUT_OD           (0x1 << 2)
-#define GPIO_CR_CNF_AF_OUTPUT_PP        (0x2 << 2)
-#define GPIO_CR_CNF_AF_OUTPUT_OD        (0x3 << 2)
-#define GPIO_CR_MODE                    0x3
-#define GPIO_CR_MODE_INPUT              0x0
-#define GPIO_CR_MODE_OUTPUT_10MHZ       0x1
-#define GPIO_CR_MODE_OUTPUT_2MHZ        0x2
-#define GPIO_CR_MODE_OUTPUT_50MHZ       0x3
-
-/**
- * @brief GPIO Pin modes.
- *
- * These only allow for 50MHZ max output speeds; if you want slower,
- * use direct register access.
- */
-typedef enum gpio_pin_mode {
-    GPIO_OUTPUT_PP = (GPIO_CR_CNF_OUTPUT_PP |
-                      GPIO_CR_MODE_OUTPUT_50MHZ), /**< Output push-pull. */
-    GPIO_OUTPUT_OD = (GPIO_CR_CNF_OUTPUT_OD |
-                      GPIO_CR_MODE_OUTPUT_50MHZ), /**< Output open-drain. */
-    GPIO_AF_OUTPUT_PP = (GPIO_CR_CNF_AF_OUTPUT_PP |
-                         GPIO_CR_MODE_OUTPUT_50MHZ), /**< Alternate function
-                                                        output push-pull. */
-    GPIO_AF_OUTPUT_OD = (GPIO_CR_CNF_AF_OUTPUT_OD |
-                         GPIO_CR_MODE_OUTPUT_50MHZ), /**< Alternate function
-                                                        output open drain. */
-    GPIO_INPUT_ANALOG = (GPIO_CR_CNF_INPUT_ANALOG |
-                         GPIO_CR_MODE_INPUT), /**< Analog input. */
-    GPIO_INPUT_FLOATING = (GPIO_CR_CNF_INPUT_FLOATING |
-                           GPIO_CR_MODE_INPUT), /**< Input floating. */
-    GPIO_INPUT_PD = (GPIO_CR_CNF_INPUT_PU_PD |
-                     GPIO_CR_MODE_INPUT), /**< Input pull-down. */
-    GPIO_AF_INPUT_PD = (GPIO_INPUT_PD), /**< Input pull-down. */
-    GPIO_INPUT_PU /**< Input pull-up. */
-
-
-    /* GPIO_INPUT_PU treated as a special case, for ODR twiddling */
-} gpio_pin_mode;
-
-/*
- * GPIO Convenience routines
- */
-
-void gpio_init(gpio_dev *dev);
-void gpio_init_all(void);
-void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode);
-
-/**
- * @brief Get a GPIO port's corresponding afio_exti_port.
- * @param dev GPIO device whose afio_exti_port to return.
- */
-static inline afio_exti_port gpio_exti_port(gpio_dev *dev) {
-    return dev->exti_port;
-}
-
-/**
- * Set or reset a GPIO pin.
- *
- * Pin must have previously been configured to output mode.
- *
- * @param dev GPIO device whose pin to set.
- * @param pin Pin on to set or reset
- * @param val If true, set the pin.  If false, reset the pin.
- */
-static inline void gpio_write_bit(gpio_dev *dev, uint8 pin, uint8 val) {
-    if (val) {
-        dev->regs->BSRR = BIT(pin);
-    } else {
-        dev->regs->BRR = BIT(pin);
-    }
-}
-
-/**
- * Determine whether or not a GPIO pin is set.
- *
- * Pin must have previously been configured to input mode.
- *
- * @param dev GPIO device whose pin to test.
- * @param pin Pin on dev to test.
- * @return True if the pin is set, false otherwise.
- */
-static inline uint32 gpio_read_bit(gpio_dev *dev, uint8 pin) {
-    return dev->regs->IDR & BIT(pin);
-}
-
-/**
- * Toggle a pin configured as output push-pull.
- * @param dev GPIO device.
- * @param pin Pin on dev to toggle.
- */
-static inline void gpio_toggle_bit(gpio_dev *dev, uint8 pin) {
-    dev->regs->ODR = dev->regs->ODR ^ BIT(pin);
-}
-
-/*
- * AFIO register map
- */
-
-/** AFIO register map */
-typedef struct afio_reg_map {
-    __io uint32 EVCR;        /**< Event control register.  */
-    __io uint32 MAPR;        /**< AF remap and debug I/O configuration
-                                register. */
-    __io uint32 EXTICR1;     /**< External interrupt configuration
-                                register 1. */
-    __io uint32 EXTICR2;     /**< External interrupt configuration
-                                register 2. */
-    __io uint32 EXTICR3;     /**< External interrupt configuration
-                                register 3. */
-    __io uint32 EXTICR4;     /**< External interrupt configuration
-                                register 4. */
-    __io uint32 MAPR2;       /**< AF remap and debug I/O configuration
-                                register 2. */
-} afio_reg_map;
-
-/** AFIO register map base pointer. */
-#define AFIO_BASE                       ((struct afio_reg_map *)0x40010000)
-
-/*
- * AFIO register bit definitions
- */
-
-/* Event control register */
-
-#define AFIO_EVCR_EVOE                  (0x1 << 7)
-#define AFIO_EVCR_PORT_PA               (0x0 << 4)
-#define AFIO_EVCR_PORT_PB               (0x1 << 4)
-#define AFIO_EVCR_PORT_PC               (0x2 << 4)
-#define AFIO_EVCR_PORT_PD               (0x3 << 4)
-#define AFIO_EVCR_PORT_PE               (0x4 << 4)
-#define AFIO_EVCR_PIN_0                 0x0
-#define AFIO_EVCR_PIN_1                 0x1
-#define AFIO_EVCR_PIN_2                 0x2
-#define AFIO_EVCR_PIN_3                 0x3
-#define AFIO_EVCR_PIN_4                 0x4
-#define AFIO_EVCR_PIN_5                 0x5
-#define AFIO_EVCR_PIN_6                 0x6
-#define AFIO_EVCR_PIN_7                 0x7
-#define AFIO_EVCR_PIN_8                 0x8
-#define AFIO_EVCR_PIN_9                 0x9
-#define AFIO_EVCR_PIN_10                0xA
-#define AFIO_EVCR_PIN_11                0xB
-#define AFIO_EVCR_PIN_12                0xC
-#define AFIO_EVCR_PIN_13                0xD
-#define AFIO_EVCR_PIN_14                0xE
-#define AFIO_EVCR_PIN_15                0xF
-
-/* AF remap and debug I/O configuration register */
-
-#define AFIO_MAPR_SWJ_CFG                      (0x7 << 24)
-#define AFIO_MAPR_SWJ_CFG_FULL_SWJ             (0x0 << 24)
-#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST    (0x1 << 24)
-#define AFIO_MAPR_SWJ_CFG_NO_JTAG_SW           (0x2 << 24)
-#define AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW        (0x4 << 24)
-#define AFIO_MAPR_ADC2_ETRGREG_REMAP           BIT(20)
-#define AFIO_MAPR_ADC2_ETRGINJ_REMAP           BIT(19)
-#define AFIO_MAPR_ADC1_ETRGREG_REMAP           BIT(18)
-#define AFIO_MAPR_ADC1_ETRGINJ_REMAP           BIT(17)
-#define AFIO_MAPR_TIM5CH4_IREMAP               BIT(16)
-#define AFIO_MAPR_PD01_REMAP                   BIT(15)
-#define AFIO_MAPR_CAN_REMAP                    (0x3 << 13)
-#define AFIO_MAPR_CAN_REMAP_NONE               (0x0 << 13)
-#define AFIO_MAPR_CAN_REMAP_PB8_PB9            (0x2 << 13)
-#define AFIO_MAPR_CAN_REMAP_PD0_PD1            (0x3 << 13)
-#define AFIO_MAPR_TIM4_REMAP                   BIT(12)
-#define AFIO_MAPR_TIM3_REMAP                   (0x3 << 10)
-#define AFIO_MAPR_TIM3_REMAP_NONE              (0x0 << 10)
-#define AFIO_MAPR_TIM3_REMAP_PARTIAL           (0x2 << 10)
-#define AFIO_MAPR_TIM3_REMAP_FULL              (0x3 << 10)
-#define AFIO_MAPR_TIM2_REMAP                   (0x3 << 8)
-#define AFIO_MAPR_TIM2_REMAP_NONE              (0x0 << 8)
-#define AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3  (0x1 << 8)
-#define AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11 (0x2 << 8)
-#define AFIO_MAPR_TIM2_REMAP_FULL              (0x3 << 8)
-#define AFIO_MAPR_TIM1_REMAP                   (0x3 << 6)
-#define AFIO_MAPR_TIM1_REMAP_NONE              (0x0 << 6)
-#define AFIO_MAPR_TIM1_REMAP_PARTIAL           (0x1 << 6)
-#define AFIO_MAPR_TIM1_REMAP_FULL              (0x3 << 6)
-#define AFIO_MAPR_USART3_REMAP                 (0x3 << 4)
-#define AFIO_MAPR_USART3_REMAP_NONE            (0x0 << 4)
-#define AFIO_MAPR_USART3_REMAP_PARTIAL         (0x1 << 4)
-#define AFIO_MAPR_USART3_REMAP_FULL            (0x3 << 4)
-#define AFIO_MAPR_USART2_REMAP                 BIT(3)
-#define AFIO_MAPR_USART1_REMAP                 BIT(2)
-#define AFIO_MAPR_I2C1_REMAP                   BIT(1)
-#define AFIO_MAPR_SPI1_REMAP                   BIT(0)
-
-/* External interrupt configuration register 1 */
-
-#define AFIO_EXTICR1_EXTI3              (0xF << 12)
-#define AFIO_EXTICR1_EXTI3_PA           (0x0 << 12)
-#define AFIO_EXTICR1_EXTI3_PB           (0x1 << 12)
-#define AFIO_EXTICR1_EXTI3_PC           (0x2 << 12)
-#define AFIO_EXTICR1_EXTI3_PD           (0x3 << 12)
-#define AFIO_EXTICR1_EXTI3_PE           (0x4 << 12)
-#define AFIO_EXTICR1_EXTI3_PF           (0x5 << 12)
-#define AFIO_EXTICR1_EXTI3_PG           (0x6 << 12)
-#define AFIO_EXTICR1_EXTI2              (0xF << 8)
-#define AFIO_EXTICR1_EXTI2_PA           (0x0 << 8)
-#define AFIO_EXTICR1_EXTI2_PB           (0x1 << 8)
-#define AFIO_EXTICR1_EXTI2_PC           (0x2 << 8)
-#define AFIO_EXTICR1_EXTI2_PD           (0x3 << 8)
-#define AFIO_EXTICR1_EXTI2_PE           (0x4 << 8)
-#define AFIO_EXTICR1_EXTI2_PF           (0x5 << 8)
-#define AFIO_EXTICR1_EXTI2_PG           (0x6 << 8)
-#define AFIO_EXTICR1_EXTI1              (0xF << 4)
-#define AFIO_EXTICR1_EXTI1_PA           (0x0 << 4)
-#define AFIO_EXTICR1_EXTI1_PB           (0x1 << 4)
-#define AFIO_EXTICR1_EXTI1_PC           (0x2 << 4)
-#define AFIO_EXTICR1_EXTI1_PD           (0x3 << 4)
-#define AFIO_EXTICR1_EXTI1_PE           (0x4 << 4)
-#define AFIO_EXTICR1_EXTI1_PF           (0x5 << 4)
-#define AFIO_EXTICR1_EXTI1_PG           (0x6 << 4)
-#define AFIO_EXTICR1_EXTI0              0xF
-#define AFIO_EXTICR1_EXTI0_PA           0x0
-#define AFIO_EXTICR1_EXTI0_PB           0x1
-#define AFIO_EXTICR1_EXTI0_PC           0x2
-#define AFIO_EXTICR1_EXTI0_PD           0x3
-#define AFIO_EXTICR1_EXTI0_PE           0x4
-#define AFIO_EXTICR1_EXTI0_PF           0x5
-#define AFIO_EXTICR1_EXTI0_PG           0x6
-
-/* External interrupt configuration register 2 */
-
-#define AFIO_EXTICR2_EXTI7              (0xF << 12)
-#define AFIO_EXTICR2_EXTI7_PA           (0x0 << 12)
-#define AFIO_EXTICR2_EXTI7_PB           (0x1 << 12)
-#define AFIO_EXTICR2_EXTI7_PC           (0x2 << 12)
-#define AFIO_EXTICR2_EXTI7_PD           (0x3 << 12)
-#define AFIO_EXTICR2_EXTI7_PE           (0x4 << 12)
-#define AFIO_EXTICR2_EXTI7_PF           (0x5 << 12)
-#define AFIO_EXTICR2_EXTI7_PG           (0x6 << 12)
-#define AFIO_EXTICR2_EXTI6              (0xF << 8)
-#define AFIO_EXTICR2_EXTI6_PA           (0x0 << 8)
-#define AFIO_EXTICR2_EXTI6_PB           (0x1 << 8)
-#define AFIO_EXTICR2_EXTI6_PC           (0x2 << 8)
-#define AFIO_EXTICR2_EXTI6_PD           (0x3 << 8)
-#define AFIO_EXTICR2_EXTI6_PE           (0x4 << 8)
-#define AFIO_EXTICR2_EXTI6_PF           (0x5 << 8)
-#define AFIO_EXTICR2_EXTI6_PG           (0x6 << 8)
-#define AFIO_EXTICR2_EXTI5              (0xF << 4)
-#define AFIO_EXTICR2_EXTI5_PA           (0x0 << 4)
-#define AFIO_EXTICR2_EXTI5_PB           (0x1 << 4)
-#define AFIO_EXTICR2_EXTI5_PC           (0x2 << 4)
-#define AFIO_EXTICR2_EXTI5_PD           (0x3 << 4)
-#define AFIO_EXTICR2_EXTI5_PE           (0x4 << 4)
-#define AFIO_EXTICR2_EXTI5_PF           (0x5 << 4)
-#define AFIO_EXTICR2_EXTI5_PG           (0x6 << 4)
-#define AFIO_EXTICR2_EXTI4              0xF
-#define AFIO_EXTICR2_EXTI4_PA           0x0
-#define AFIO_EXTICR2_EXTI4_PB           0x1
-#define AFIO_EXTICR2_EXTI4_PC           0x2
-#define AFIO_EXTICR2_EXTI4_PD           0x3
-#define AFIO_EXTICR2_EXTI4_PE           0x4
-#define AFIO_EXTICR2_EXTI4_PF           0x5
-#define AFIO_EXTICR2_EXTI4_PG           0x6
-
-/* AF remap and debug I/O configuration register 2 */
-
-#define AFIO_MAPR2_FSMC_NADV            BIT(10)
-#define AFIO_MAPR2_TIM14_REMAP          BIT(9)
-#define AFIO_MAPR2_TIM13_REMAP          BIT(8)
-#define AFIO_MAPR2_TIM11_REMAP          BIT(7)
-#define AFIO_MAPR2_TIM10_REMAP          BIT(6)
-#define AFIO_MAPR2_TIM9_REMAP           BIT(5)
-
-/*
- * AFIO convenience routines
- */
-
-void afio_init(void);
-
-/**
- * External interrupt line numbers.
- */
-typedef enum afio_exti_num {
-    AFIO_EXTI_0,                /**< External interrupt line 0. */
-    AFIO_EXTI_1,                /**< External interrupt line 1. */
-    AFIO_EXTI_2,                /**< External interrupt line 2. */
-    AFIO_EXTI_3,                /**< External interrupt line 3. */
-    AFIO_EXTI_4,                /**< External interrupt line 4. */
-    AFIO_EXTI_5,                /**< External interrupt line 5. */
-    AFIO_EXTI_6,                /**< External interrupt line 6. */
-    AFIO_EXTI_7,                /**< External interrupt line 7. */
-    AFIO_EXTI_8,                /**< External interrupt line 8. */
-    AFIO_EXTI_9,                /**< External interrupt line 9. */
-    AFIO_EXTI_10,               /**< External interrupt line 10. */
-    AFIO_EXTI_11,               /**< External interrupt line 11. */
-    AFIO_EXTI_12,               /**< External interrupt line 12. */
-    AFIO_EXTI_13,               /**< External interrupt line 13. */
-    AFIO_EXTI_14,               /**< External interrupt line 14. */
-    AFIO_EXTI_15,               /**< External interrupt line 15. */
-} afio_exti_num;
-
-void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port);
-
-/* HACK: Use upper bit to denote MAPR2, Bit 31 is reserved and
- * not used in either MAPR or MAPR2 */
-#define AFIO_REMAP_USE_MAPR2            (1 << 31)
-
-/**
- * @brief Available peripheral remaps.
- * @see afio_remap()
- */
-typedef enum afio_remap_peripheral {
-    AFIO_REMAP_ADC2_ETRGREG  = AFIO_MAPR_ADC2_ETRGREG_REMAP, /**<
-        ADC 2 external trigger regular conversion remapping */
-    AFIO_REMAP_ADC2_ETRGINJ  = AFIO_MAPR_ADC2_ETRGINJ_REMAP, /**<
-        ADC 2 external trigger injected conversion remapping */
-    AFIO_REMAP_ADC1_ETRGREG  = AFIO_MAPR_ADC1_ETRGREG_REMAP, /**<
-        ADC 1 external trigger regular conversion remapping */
-    AFIO_REMAP_ADC1_ETRGINJ  = AFIO_MAPR_ADC1_ETRGINJ_REMAP, /**<
-        ADC 1 external trigger injected conversion remapping */
-    AFIO_REMAP_TIM5CH4_I     = AFIO_MAPR_TIM5CH4_IREMAP, /**<
-        Timer 5 channel 4 internal remapping */
-    AFIO_REMAP_PD01          = AFIO_MAPR_PD01_REMAP, /**<
-        Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
-    AFIO_REMAP_CAN_1         = AFIO_MAPR_CAN_REMAP_PB8_PB9, /**<
-        CAN alternate function remapping 1 (RX on PB8, TX on PB9) */
-    AFIO_REMAP_CAN_2         = AFIO_MAPR_CAN_REMAP_PD0_PD1, /**<
-        CAN alternate function remapping 2 (RX on PD0, TX on PD1) */
-    AFIO_REMAP_TIM4          = AFIO_MAPR_TIM4_REMAP, /**<
-        Timer 4 remapping */
-    AFIO_REMAP_TIM3_PARTIAL  = AFIO_MAPR_TIM3_REMAP_PARTIAL, /**<
-        Timer 3 partial remapping */
-    AFIO_REMAP_TIM3_FULL      = AFIO_MAPR_TIM3_REMAP_FULL, /**<
-        Timer 3 full remapping */
-    AFIO_REMAP_TIM2_PARTIAL_1 = AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3, /**<
-        Timer 2 partial remapping 1 (CH1 and ETR on PA15, CH2 on PB3, CH3
-        on PA2, CH4 on PA3) */
-    AFIO_REMAP_TIM2_PARTIAL_2 = AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11, /**<
-        Timer 2 partial remapping 2 (CH1 and ETR on PA0, CH2 on PA1, CH3
-        on PB10, CH4 on PB11) */
-    AFIO_REMAP_TIM2_FULL      = AFIO_MAPR_TIM2_REMAP_FULL, /**<
-        Timer 2 full remapping */
-    AFIO_REMAP_USART2        = AFIO_MAPR_USART2_REMAP, /**<
-        USART 2 remapping */
-    AFIO_REMAP_USART1        = AFIO_MAPR_USART1_REMAP, /**<
-        USART 1 remapping */
-    AFIO_REMAP_I2C1          = AFIO_MAPR_I2C1_REMAP, /**<
-        I2C 1 remapping */
-    AFIO_REMAP_SPI1          = AFIO_MAPR_SPI1_REMAP, /**<
-        SPI 1 remapping */
-    AFIO_REMAP_FSMC_NADV     = (AFIO_MAPR2_FSMC_NADV |
-                                AFIO_REMAP_USE_MAPR2), /**<
-        NADV signal not connected */
-    AFIO_REMAP_TIM14         = (AFIO_MAPR2_TIM14_REMAP |
-                                AFIO_REMAP_USE_MAPR2), /**<
-        Timer 14 remapping */
-    AFIO_REMAP_TIM13         = (AFIO_MAPR2_TIM13_REMAP |
-                                AFIO_REMAP_USE_MAPR2), /**<
-        Timer 13 remapping */
-    AFIO_REMAP_TIM11         = (AFIO_MAPR2_TIM11_REMAP |
-                                AFIO_REMAP_USE_MAPR2), /**<
-        Timer 11 remapping */
-    AFIO_REMAP_TIM10         = (AFIO_MAPR2_TIM10_REMAP |
-                                AFIO_REMAP_USE_MAPR2), /**<
-        Timer 10 remapping */
-    AFIO_REMAP_TIM9          = (AFIO_MAPR2_TIM9_REMAP |
-                                AFIO_REMAP_USE_MAPR2) /**<
-        Timer 9 */
-} afio_remap_peripheral;
-
-void afio_remap(afio_remap_peripheral p);
-
-/**
- * @brief Debug port configuration
- *
- * Used to configure the behavior of JTAG and Serial Wire (SW) debug
- * ports and their associated GPIO pins.
- *
- * @see afio_cfg_debug_ports()
- */
-typedef enum afio_debug_cfg {
-    AFIO_DEBUG_FULL_SWJ = AFIO_MAPR_SWJ_CFG_FULL_SWJ, /**<
-                                   Full Serial Wire and JTAG debug */
-    AFIO_DEBUG_FULL_SWJ_NO_NJRST = AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST, /**<
-                                   Full Serial Wire and JTAG, but no NJTRST. */
-    AFIO_DEBUG_SW_ONLY = AFIO_MAPR_SWJ_CFG_NO_JTAG_SW, /**<
-                                   Serial Wire debug only (JTAG-DP disabled,
-                                   SW-DP enabled) */
-    AFIO_DEBUG_NONE = AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW /**<
-                                   No debug; all JTAG and SW pins are free
-                                   for use as GPIOs. */
-} afio_debug_cfg;
-
-/**
- * @brief Enable or disable the JTAG and SW debug ports.
- * @param config Desired debug port configuration
- * @see afio_debug_cfg
- */
-static inline void afio_cfg_debug_ports(afio_debug_cfg config) {
-    __io uint32 *mapr = &AFIO_BASE->MAPR;
-    *mapr = (*mapr & ~AFIO_MAPR_SWJ_CFG) | config;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
diff --git a/STM32F4/cores/maple/libmaple/gpioF2.c b/STM32F4/cores/maple/libmaple/gpioF2.c
deleted file mode 100644
index b04c7e9d6..000000000
--- a/STM32F4/cores/maple/libmaple/gpioF2.c
+++ /dev/null
@@ -1,224 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
- #ifdef STM32F2
- 
-/**
- * @file gpio.c
- * @brief GPIO initialization routine
- */
-
-#include "gpio.h"
-#include "rcc.h"
-
-/*
- * GPIO devices
- */
-
-gpio_dev gpioa = {
-    .regs      = GPIOA_BASE,
-    .clk_id    = RCC_GPIOA,
-    .exti_port = AFIO_EXTI_PA,
-};
-/** GPIO port A device. */
-gpio_dev* const GPIOA = &gpioa;
-
-gpio_dev gpiob = {
-    .regs      = GPIOB_BASE,
-    .clk_id    = RCC_GPIOB,
-    .exti_port = AFIO_EXTI_PB,
-};
-/** GPIO port B device. */
-gpio_dev* const GPIOB = &gpiob;
-
-gpio_dev gpioc = {
-    .regs      = GPIOC_BASE,
-    .clk_id    = RCC_GPIOC,
-    .exti_port = AFIO_EXTI_PC,
-};
-/** GPIO port C device. */
-gpio_dev* const GPIOC = &gpioc;
-
-gpio_dev gpiod = {
-    .regs      = GPIOD_BASE,
-    .clk_id    = RCC_GPIOD,
-    .exti_port = AFIO_EXTI_PD,
-};
-/** GPIO port D device. */
-gpio_dev* const GPIOD = &gpiod;
-
-#ifdef STM32_HIGH_DENSITY
-gpio_dev gpioe = {
-    .regs      = GPIOE_BASE,
-    .clk_id    = RCC_GPIOE,
-    .exti_port = AFIO_EXTI_PE,
-};
-/** GPIO port E device. */
-gpio_dev* const GPIOE = &gpioe;
-
-gpio_dev gpiof = {
-    .regs      = GPIOF_BASE,
-    .clk_id    = RCC_GPIOF,
-    .exti_port = AFIO_EXTI_PF,
-};
-/** GPIO port F device. */
-gpio_dev* const GPIOF = &gpiof;
-
-gpio_dev gpiog = {
-    .regs      = GPIOG_BASE,
-    .clk_id    = RCC_GPIOG,
-    .exti_port = AFIO_EXTI_PG,
-};
-/** GPIO port G device. */
-gpio_dev* const GPIOG = &gpiog;
-#endif
-
-/*
- * GPIO convenience routines
- */
-
-/**
- * Initialize a GPIO device.
- *
- * Enables the clock for and resets the given device.
- *
- * @param dev GPIO device to initialize.
- */
-void gpio_init(gpio_dev *dev) {
-    rcc_clk_enable(dev->clk_id);
-    rcc_reset_dev(dev->clk_id);
-}
-
-/**
- * Initialize and reset all available GPIO devices.
- */
-void gpio_init_all(void) {
-    gpio_init(GPIOA);
-    gpio_init(GPIOB);
-    gpio_init(GPIOC);
-    gpio_init(GPIOD);
-
-#ifdef STM32_HIGH_DENSITY
-    gpio_init(GPIOE);
-    gpio_init(GPIOF);
-    gpio_init(GPIOG);
-#endif
-
-#ifdef ARDUINO_STM32F4_NETDUINO2PLUS
-    // PA8 Output the Master Clock MCO1
-    gpio_set_af_mode(GPIOA, 8, 0);
-    gpio_set_mode(GPIOA, 8, GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
-    // PB4 as alternate MISO Input
-    gpio_set_af_mode(GPIOB, 4, 5);
-    // PA5 as alternate SCK Output
-    gpio_set_af_mode(GPIOA, 5, 5);
-    // PA7 as alternate MOSI Output
-    gpio_set_af_mode(GPIOA, 7, 5);
-#endif
-}
-
-/**
- * Set the mode of a GPIO pin.
- *
- * @param dev GPIO device.
- * @param pin Pin on the device whose mode to set, 0--15.
- * @param mode General purpose or alternate function mode to set the pin to.
- * @see gpio_pin_mode
- */
-void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode) {
-    gpio_reg_map *regs = dev->regs;
-
-	//regs->AFR[pin/8] = (regs->AFR[pin/8] & ~(15 << (4*(pin&7)))) | (((mode >> 8) & 15) << (4*(pin&7)));
-	//gpio_set_af_mode(dev, pin, mode>>8);
-
-    regs->MODER      = (regs->MODER      & ~( 3 << (2*pin)))     | (((mode >> 0) & 3)  << (2*pin));
-    regs->PUPDR      = (regs->PUPDR      & ~( 3 << (2*pin)))     | (((mode >> 2) & 3)  << (2*pin));
-    regs->OSPEEDR    = (regs->OSPEEDR    & ~( 3 << (2*pin)))     | (((mode >> 4) & 3)  << (2*pin));
-    regs->OTYPER     = (regs->OTYPER     & ~( 1 << (1*pin)))     | (((mode >> 6) & 1)  << (1*pin));
-}
-
-/**
- * Set the alternate function mode of a GPIO pin.
- *
- * @param dev GPIO device.
- * @param pin Pin on the device whose mode to set, 0--15.
- * @param mode alternate function mode to set the pin to.
- * @see gpio_pin_mode
- */
-void gpio_set_af_mode(gpio_dev *dev, uint8 pin, int mode) {
-    gpio_reg_map *regs = dev->regs;
-
-	regs->AFR[pin/8] = (regs->AFR[pin/8] & ~(15 << (4*(pin&7)))) | (((mode >> 0) & 15) << (4*(pin&7)));
-}
-
-/*
- * AFIO
- */
-
-/**
- * @brief Initialize the AFIO clock, and reset the AFIO registers.
- */
-void afio_init(void) {
-    //rcc_clk_enable(RCC_AFIO);
-    //rcc_reset_dev(RCC_AFIO);
-}
-
-#define AFIO_EXTI_SEL_MASK 0xF
-
-/**
- * @brief Select a source input for an external interrupt.
- *
- * @param exti      External interrupt.
- * @param gpio_port Port which contains pin to use as source input.
- * @see afio_exti_num
- * @see afio_exti_port
- */
-void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port) {
-    __io uint32 *exti_cr = &SYSCFG_BASE->EXTICR1 + exti / 4;
-    uint32 shift = 4 * (exti % 4);
-    uint32 cr = *exti_cr;
-
-    cr &= ~(AFIO_EXTI_SEL_MASK << shift);
-    cr |= gpio_port << shift;
-    *exti_cr = cr;
-}
-
-/**
- * @brief Perform an alternate function remap.
- * @param remapping Remapping to perform.
- */
-#if 0
-void afio_remap(afio_remap_peripheral remapping) {
-    if (remapping & AFIO_REMAP_USE_MAPR2) {
-        remapping &= ~AFIO_REMAP_USE_MAPR2;
-        AFIO_BASE->MAPR2 |= remapping;
-    } else {
-        AFIO_BASE->MAPR |= remapping;
-    }
-}
-#endif
-
-#endif
diff --git a/STM32F4/cores/maple/libmaple/gpioF2.h b/STM32F4/cores/maple/libmaple/gpioF2.h
deleted file mode 100644
index 91bd67be3..000000000
--- a/STM32F4/cores/maple/libmaple/gpioF2.h
+++ /dev/null
@@ -1,550 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
-*****************************************************************************/
-
-/**
- *  @file gpio.h
- *
- *  @brief General purpose I/O (GPIO) and Alternate Function I/O
- *         (AFIO) prototypes, defines, and inlined access functions.
- */
-
-#ifndef _GPIO_H_
-#define _GPIO_H_
-
-#include "libmaple.h"
-#include "rcc.h"
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-/*
- * GPIO register maps and devices
- */
-
-/** GPIO register map type */
-typedef struct gpio_reg_map {
-    __io uint32 MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
-    __io uint32 OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
-    __io uint32 OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
-    __io uint32 PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
-    __io uint32 IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
-    __io uint32 ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
-    __io uint16 BSRRL;    /*!< GPIO port bit set/reset low register,  Address offset: 0x18      */
-    __io uint16 BSRRH;    /*!< GPIO port bit set/reset high register, Address offset: 0x1A      */
-    __io uint32 LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
-    __io uint32 AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x24-0x28 */
-} gpio_reg_map;
-
-
-
-/**
- * @brief External interrupt line port selector.
- *
- * Used to determine which GPIO port to map an external interrupt line
- * onto. */
-/* (See AFIO sections, below) */
-typedef enum afio_exti_port {
-    AFIO_EXTI_PA,               /**< Use port A (PAx) pin. */
-    AFIO_EXTI_PB,               /**< Use port B (PBx) pin. */
-    AFIO_EXTI_PC,               /**< Use port C (PCx) pin. */
-    AFIO_EXTI_PD,               /**< Use port D (PDx) pin. */
-#ifdef STM32_HIGH_DENSITY
-    AFIO_EXTI_PE,               /**< Use port E (PEx) pin. */
-    AFIO_EXTI_PF,               /**< Use port F (PFx) pin. */
-    AFIO_EXTI_PG,               /**< Use port G (PGx) pin. */
-#endif
-} afio_exti_port;
-
-/** GPIO device type */
-typedef struct gpio_dev {
-    gpio_reg_map *regs;       /**< Register map */
-    rcc_clk_id clk_id;        /**< RCC clock information */
-    afio_exti_port exti_port; /**< AFIO external interrupt port value */
-} gpio_dev;
-
-extern gpio_dev gpioa;
-extern gpio_dev* const GPIOA;
-extern gpio_dev gpiob;
-extern gpio_dev* const GPIOB;
-extern gpio_dev gpioc;
-extern gpio_dev* const GPIOC;
-extern gpio_dev gpiod;
-extern gpio_dev* const GPIOD;
-#ifdef STM32_HIGH_DENSITY
-extern gpio_dev gpioe;
-extern gpio_dev* const GPIOE;
-extern gpio_dev gpiof;
-extern gpio_dev* const GPIOF;
-extern gpio_dev gpiog;
-extern gpio_dev* const GPIOG;
-#endif
-
-/** GPIO port register map base pointer */
-#define GPIOA_BASE                      ((struct gpio_reg_map*)0x40020000)
-#define GPIOB_BASE                      ((struct gpio_reg_map*)0x40020400)
-#define GPIOC_BASE                      ((struct gpio_reg_map*)0x40020800)
-#define GPIOD_BASE                      ((struct gpio_reg_map*)0x40020C00)
-#ifdef STM32_HIGH_DENSITY
-#define GPIOE_BASE                      ((struct gpio_reg_map*)0x40021000)
-#define GPIOF_BASE                      ((struct gpio_reg_map*)0x40021400)
-#define GPIOG_BASE                      ((struct gpio_reg_map*)0x40021800)
-#endif
-
-/*
- * GPIO register bit definitions
- */
-
-#define GPIO_MODE_INPUT                 0
-#define GPIO_MODE_OUTPUT                1
-#define GPIO_MODE_AF                    2
-#define GPIO_MODE_ANALOG                3
-
-#define GPIO_PUPD_INPUT_FLOATING        (0 << 2)
-#define GPIO_PUPD_INPUT_PU              (1 << 2)
-#define GPIO_PUPD_INPUT_PD              (2 << 2)
-
-#define GPIO_OSPEED_2MHZ                (0 << 4)
-#define GPIO_OSPEED_25MHZ               (1 << 4)
-#define GPIO_OSPEED_50MHZ               (2 << 4)
-#define GPIO_OSPEED_100MHZ              (3 << 4)
-
-#define GPIO_OTYPE_PP                   (0 << 6)
-#define GPIO_OTYPE_OD                   (1 << 6)
-
-/*
-MODER
-00: Input (reset state)
-01: General purpose output mode
-10: Alternate function mode
-11: Analog mode
-
-OTYPER
-0: Output push-pull (reset state)
-1: Output open-drain
-
-OSPEEDR
-00: 2 MHz Low speed
-01: 25 MHz Medium speed
-10: 50 MHz Fast speed
-11: 100 MHz High speed on 30 pF (80 MHz Output max speed on 15 pF)
-
-PUPDR
-00: No pull-up, pull-down
-01: Pull-up
-10: Pull-down
-
-AFRL 4 bit AF00-AF15
-AFRH 4 bit AF00-AF15
-*/
-
-/**
- * @brief GPIO Pin modes.
- *
- * These only allow for 50MHZ max output speeds; if you want slower,
- * use direct register access.
- */
-typedef enum gpio_pin_mode {
-    GPIO_OUTPUT_PP = (GPIO_MODE_OUTPUT | GPIO_OTYPE_PP |
-                      GPIO_OSPEED_50MHZ), /**< Output push-pull. */
-    GPIO_OUTPUT_OD = (GPIO_MODE_OUTPUT | GPIO_OTYPE_OD |
-                      GPIO_OSPEED_50MHZ), /**< Output open-drain. */
-    GPIO_AF_OUTPUT_PP = (GPIO_MODE_AF | GPIO_OTYPE_PP |
-                         GPIO_OSPEED_50MHZ), /**< Alternate function
-                                                        output push-pull. */
-    GPIO_AF_OUTPUT_OD = (GPIO_MODE_AF | GPIO_OTYPE_OD |
-                         GPIO_OSPEED_50MHZ), /**< Alternate function
-                                                        output open drain. */
-    GPIO_INPUT_ANALOG = (GPIO_MODE_ANALOG), /**< Analog input. */
-    GPIO_INPUT_FLOATING = (GPIO_MODE_INPUT |
-                           GPIO_PUPD_INPUT_FLOATING), /**< Input floating. */
-    GPIO_INPUT_PD = (GPIO_MODE_INPUT |
-                     GPIO_PUPD_INPUT_PD), /**< Input pull-down. */
-    GPIO_INPUT_PU = (GPIO_MODE_INPUT |
-                     GPIO_PUPD_INPUT_PU), /**< Input pull-up. */
-    GPIO_AF_INPUT_PD = (GPIO_MODE_AF |
-                     GPIO_PUPD_INPUT_PD), /**< Input pull-down. */
-	GPIO_BIGNUMBER = 0xfff
-} gpio_pin_mode;
-
-/*
- * GPIO Convenience routines
- */
-
-void gpio_init(gpio_dev *dev);
-void gpio_init_all(void);
-void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode);
-void gpio_set_af_mode(gpio_dev *dev, uint8 pin, int mode);
-
-/**
- * @brief Get a GPIO port's corresponding afio_exti_port.
- * @param dev GPIO device whose afio_exti_port to return.
- */
-static inline afio_exti_port gpio_exti_port(gpio_dev *dev) {
-    return dev->exti_port;
-}
-
-/**
- * Set or reset a GPIO pin.
- *
- * Pin must have previously been configured to output mode.
- *
- * @param dev GPIO device whose pin to set.
- * @param pin Pin on to set or reset
- * @param val If true, set the pin.  If false, reset the pin.
- */
-static inline void gpio_write_bit(gpio_dev *dev, uint8 pin, uint8 val) {
-    if (val) {
-        dev->regs->BSRRL = BIT(pin);
-    } else {
-        dev->regs->BSRRH = BIT(pin);
-    }
-}
-
-/**
- * Determine whether or not a GPIO pin is set.
- *
- * Pin must have previously been configured to input mode.
- *
- * @param dev GPIO device whose pin to test.
- * @param pin Pin on dev to test.
- * @return True if the pin is set, false otherwise.
- */
-static inline uint32 gpio_read_bit(gpio_dev *dev, uint8 pin) {
-    return dev->regs->IDR & BIT(pin);
-}
-
-/**
- * Toggle a pin configured as output push-pull.
- * @param dev GPIO device.
- * @param pin Pin on dev to toggle.
- */
-static inline void gpio_toggle_bit(gpio_dev *dev, uint8 pin) {
-    dev->regs->ODR = dev->regs->ODR ^ BIT(pin);
-}
-
-/*
- * AFIO register map
- */
-
-/** AFIO register map */
-typedef struct syscfg_reg_map {
-    __io uint32 MEMRM;    /**< memory remap register  */
-    __io uint32 PMC;      /**< peripheral mode configuration register */
-    __io uint32 EXTICR1;  /**< External interrupt configuration register 1. */
-    __io uint32 EXTICR2;  /**< External interrupt configuration register 2. */
-    __io uint32 EXTICR3;  /**< External interrupt configuration register 3. */
-    __io uint32 EXTICR4;  /**< External interrupt configuration register 4. */
-    __io uint32 CMPCR;    /**< Compensation cell control register */
-} syscfg_reg_map;
-
-/** AFIO register map base pointer. */
-#define SYSCFG_BASE                       ((struct syscfg_reg_map *)0x40013800)
-
-/*
- * AFIO register bit definitions
- */
-
-/* Event control register */
-
-#define AFIO_EVCR_EVOE                  (0x1 << 7)
-#define AFIO_EVCR_PORT_PA               (0x0 << 4)
-#define AFIO_EVCR_PORT_PB               (0x1 << 4)
-#define AFIO_EVCR_PORT_PC               (0x2 << 4)
-#define AFIO_EVCR_PORT_PD               (0x3 << 4)
-#define AFIO_EVCR_PORT_PE               (0x4 << 4)
-#define AFIO_EVCR_PIN_0                 0x0
-#define AFIO_EVCR_PIN_1                 0x1
-#define AFIO_EVCR_PIN_2                 0x2
-#define AFIO_EVCR_PIN_3                 0x3
-#define AFIO_EVCR_PIN_4                 0x4
-#define AFIO_EVCR_PIN_5                 0x5
-#define AFIO_EVCR_PIN_6                 0x6
-#define AFIO_EVCR_PIN_7                 0x7
-#define AFIO_EVCR_PIN_8                 0x8
-#define AFIO_EVCR_PIN_9                 0x9
-#define AFIO_EVCR_PIN_10                0xA
-#define AFIO_EVCR_PIN_11                0xB
-#define AFIO_EVCR_PIN_12                0xC
-#define AFIO_EVCR_PIN_13                0xD
-#define AFIO_EVCR_PIN_14                0xE
-#define AFIO_EVCR_PIN_15                0xF
-
-/* AF remap and debug I/O configuration register */
-
-#define AFIO_MAPR_SWJ_CFG                      (0x7 << 24)
-#define AFIO_MAPR_SWJ_CFG_FULL_SWJ             (0x0 << 24)
-#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST    (0x1 << 24)
-#define AFIO_MAPR_SWJ_CFG_NO_JTAG_SW           (0x2 << 24)
-#define AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW        (0x4 << 24)
-#define AFIO_MAPR_ADC2_ETRGREG_REMAP           BIT(20)
-#define AFIO_MAPR_ADC2_ETRGINJ_REMAP           BIT(19)
-#define AFIO_MAPR_ADC1_ETRGREG_REMAP           BIT(18)
-#define AFIO_MAPR_ADC1_ETRGINJ_REMAP           BIT(17)
-#define AFIO_MAPR_TIM5CH4_IREMAP               BIT(16)
-#define AFIO_MAPR_PD01_REMAP                   BIT(15)
-#define AFIO_MAPR_CAN_REMAP                    (0x3 << 13)
-#define AFIO_MAPR_CAN_REMAP_NONE               (0x0 << 13)
-#define AFIO_MAPR_CAN_REMAP_PB8_PB9            (0x2 << 13)
-#define AFIO_MAPR_CAN_REMAP_PD0_PD1            (0x3 << 13)
-#define AFIO_MAPR_TIM4_REMAP                   BIT(12)
-#define AFIO_MAPR_TIM3_REMAP                   (0x3 << 10)
-#define AFIO_MAPR_TIM3_REMAP_NONE              (0x0 << 10)
-#define AFIO_MAPR_TIM3_REMAP_PARTIAL           (0x2 << 10)
-#define AFIO_MAPR_TIM3_REMAP_FULL              (0x3 << 10)
-#define AFIO_MAPR_TIM2_REMAP                   (0x3 << 8)
-#define AFIO_MAPR_TIM2_REMAP_NONE              (0x0 << 8)
-#define AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3  (0x1 << 8)
-#define AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11 (0x2 << 8)
-#define AFIO_MAPR_TIM2_REMAP_FULL              (0x3 << 8)
-#define AFIO_MAPR_TIM1_REMAP                   (0x3 << 6)
-#define AFIO_MAPR_TIM1_REMAP_NONE              (0x0 << 6)
-#define AFIO_MAPR_TIM1_REMAP_PARTIAL           (0x1 << 6)
-#define AFIO_MAPR_TIM1_REMAP_FULL              (0x3 << 6)
-#define AFIO_MAPR_USART3_REMAP                 (0x3 << 4)
-#define AFIO_MAPR_USART3_REMAP_NONE            (0x0 << 4)
-#define AFIO_MAPR_USART3_REMAP_PARTIAL         (0x1 << 4)
-#define AFIO_MAPR_USART3_REMAP_FULL            (0x3 << 4)
-#define AFIO_MAPR_USART2_REMAP                 BIT(3)
-#define AFIO_MAPR_USART1_REMAP                 BIT(2)
-#define AFIO_MAPR_I2C1_REMAP                   BIT(1)
-#define AFIO_MAPR_SPI1_REMAP                   BIT(0)
-
-/* External interrupt configuration register 1 */
-
-#define AFIO_EXTICR1_EXTI3              (0xF << 12)
-#define AFIO_EXTICR1_EXTI3_PA           (0x0 << 12)
-#define AFIO_EXTICR1_EXTI3_PB           (0x1 << 12)
-#define AFIO_EXTICR1_EXTI3_PC           (0x2 << 12)
-#define AFIO_EXTICR1_EXTI3_PD           (0x3 << 12)
-#define AFIO_EXTICR1_EXTI3_PE           (0x4 << 12)
-#define AFIO_EXTICR1_EXTI3_PF           (0x5 << 12)
-#define AFIO_EXTICR1_EXTI3_PG           (0x6 << 12)
-#define AFIO_EXTICR1_EXTI2              (0xF << 8)
-#define AFIO_EXTICR1_EXTI2_PA           (0x0 << 8)
-#define AFIO_EXTICR1_EXTI2_PB           (0x1 << 8)
-#define AFIO_EXTICR1_EXTI2_PC           (0x2 << 8)
-#define AFIO_EXTICR1_EXTI2_PD           (0x3 << 8)
-#define AFIO_EXTICR1_EXTI2_PE           (0x4 << 8)
-#define AFIO_EXTICR1_EXTI2_PF           (0x5 << 8)
-#define AFIO_EXTICR1_EXTI2_PG           (0x6 << 8)
-#define AFIO_EXTICR1_EXTI1              (0xF << 4)
-#define AFIO_EXTICR1_EXTI1_PA           (0x0 << 4)
-#define AFIO_EXTICR1_EXTI1_PB           (0x1 << 4)
-#define AFIO_EXTICR1_EXTI1_PC           (0x2 << 4)
-#define AFIO_EXTICR1_EXTI1_PD           (0x3 << 4)
-#define AFIO_EXTICR1_EXTI1_PE           (0x4 << 4)
-#define AFIO_EXTICR1_EXTI1_PF           (0x5 << 4)
-#define AFIO_EXTICR1_EXTI1_PG           (0x6 << 4)
-#define AFIO_EXTICR1_EXTI0              0xF
-#define AFIO_EXTICR1_EXTI0_PA           0x0
-#define AFIO_EXTICR1_EXTI0_PB           0x1
-#define AFIO_EXTICR1_EXTI0_PC           0x2
-#define AFIO_EXTICR1_EXTI0_PD           0x3
-#define AFIO_EXTICR1_EXTI0_PE           0x4
-#define AFIO_EXTICR1_EXTI0_PF           0x5
-#define AFIO_EXTICR1_EXTI0_PG           0x6
-
-/* External interrupt configuration register 2 */
-
-#define AFIO_EXTICR2_EXTI7              (0xF << 12)
-#define AFIO_EXTICR2_EXTI7_PA           (0x0 << 12)
-#define AFIO_EXTICR2_EXTI7_PB           (0x1 << 12)
-#define AFIO_EXTICR2_EXTI7_PC           (0x2 << 12)
-#define AFIO_EXTICR2_EXTI7_PD           (0x3 << 12)
-#define AFIO_EXTICR2_EXTI7_PE           (0x4 << 12)
-#define AFIO_EXTICR2_EXTI7_PF           (0x5 << 12)
-#define AFIO_EXTICR2_EXTI7_PG           (0x6 << 12)
-#define AFIO_EXTICR2_EXTI6              (0xF << 8)
-#define AFIO_EXTICR2_EXTI6_PA           (0x0 << 8)
-#define AFIO_EXTICR2_EXTI6_PB           (0x1 << 8)
-#define AFIO_EXTICR2_EXTI6_PC           (0x2 << 8)
-#define AFIO_EXTICR2_EXTI6_PD           (0x3 << 8)
-#define AFIO_EXTICR2_EXTI6_PE           (0x4 << 8)
-#define AFIO_EXTICR2_EXTI6_PF           (0x5 << 8)
-#define AFIO_EXTICR2_EXTI6_PG           (0x6 << 8)
-#define AFIO_EXTICR2_EXTI5              (0xF << 4)
-#define AFIO_EXTICR2_EXTI5_PA           (0x0 << 4)
-#define AFIO_EXTICR2_EXTI5_PB           (0x1 << 4)
-#define AFIO_EXTICR2_EXTI5_PC           (0x2 << 4)
-#define AFIO_EXTICR2_EXTI5_PD           (0x3 << 4)
-#define AFIO_EXTICR2_EXTI5_PE           (0x4 << 4)
-#define AFIO_EXTICR2_EXTI5_PF           (0x5 << 4)
-#define AFIO_EXTICR2_EXTI5_PG           (0x6 << 4)
-#define AFIO_EXTICR2_EXTI4              0xF
-#define AFIO_EXTICR2_EXTI4_PA           0x0
-#define AFIO_EXTICR2_EXTI4_PB           0x1
-#define AFIO_EXTICR2_EXTI4_PC           0x2
-#define AFIO_EXTICR2_EXTI4_PD           0x3
-#define AFIO_EXTICR2_EXTI4_PE           0x4
-#define AFIO_EXTICR2_EXTI4_PF           0x5
-#define AFIO_EXTICR2_EXTI4_PG           0x6
-
-/* AF remap and debug I/O configuration register 2 */
-
-#define AFIO_MAPR2_FSMC_NADV            BIT(10)
-#define AFIO_MAPR2_TIM14_REMAP          BIT(9)
-#define AFIO_MAPR2_TIM13_REMAP          BIT(8)
-#define AFIO_MAPR2_TIM11_REMAP          BIT(7)
-#define AFIO_MAPR2_TIM10_REMAP          BIT(6)
-#define AFIO_MAPR2_TIM9_REMAP           BIT(5)
-
-/*
- * AFIO convenience routines
- */
-
-void afio_init(void);
-
-/**
- * External interrupt line numbers.
- */
-typedef enum afio_exti_num {
-    AFIO_EXTI_0,                /**< External interrupt line 0. */
-    AFIO_EXTI_1,                /**< External interrupt line 1. */
-    AFIO_EXTI_2,                /**< External interrupt line 2. */
-    AFIO_EXTI_3,                /**< External interrupt line 3. */
-    AFIO_EXTI_4,                /**< External interrupt line 4. */
-    AFIO_EXTI_5,                /**< External interrupt line 5. */
-    AFIO_EXTI_6,                /**< External interrupt line 6. */
-    AFIO_EXTI_7,                /**< External interrupt line 7. */
-    AFIO_EXTI_8,                /**< External interrupt line 8. */
-    AFIO_EXTI_9,                /**< External interrupt line 9. */
-    AFIO_EXTI_10,               /**< External interrupt line 10. */
-    AFIO_EXTI_11,               /**< External interrupt line 11. */
-    AFIO_EXTI_12,               /**< External interrupt line 12. */
-    AFIO_EXTI_13,               /**< External interrupt line 13. */
-    AFIO_EXTI_14,               /**< External interrupt line 14. */
-    AFIO_EXTI_15,               /**< External interrupt line 15. */
-} afio_exti_num;
-
-void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port);
-
-/* HACK: Use upper bit to denote MAPR2, Bit 31 is reserved and
- * not used in either MAPR or MAPR2 */
-#define AFIO_REMAP_USE_MAPR2            (1 << 31)
-
-/**
- * @brief Available peripheral remaps.
- * @see afio_remap()
- */
-typedef enum afio_remap_peripheral {
-    AFIO_REMAP_ADC2_ETRGREG  = AFIO_MAPR_ADC2_ETRGREG_REMAP, /**<
-        ADC 2 external trigger regular conversion remapping */
-    AFIO_REMAP_ADC2_ETRGINJ  = AFIO_MAPR_ADC2_ETRGINJ_REMAP, /**<
-        ADC 2 external trigger injected conversion remapping */
-    AFIO_REMAP_ADC1_ETRGREG  = AFIO_MAPR_ADC1_ETRGREG_REMAP, /**<
-        ADC 1 external trigger regular conversion remapping */
-    AFIO_REMAP_ADC1_ETRGINJ  = AFIO_MAPR_ADC1_ETRGINJ_REMAP, /**<
-        ADC 1 external trigger injected conversion remapping */
-    AFIO_REMAP_TIM5CH4_I     = AFIO_MAPR_TIM5CH4_IREMAP, /**<
-        Timer 5 channel 4 internal remapping */
-    AFIO_REMAP_PD01          = AFIO_MAPR_PD01_REMAP, /**<
-        Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
-    AFIO_REMAP_CAN_1         = AFIO_MAPR_CAN_REMAP_PB8_PB9, /**<
-        CAN alternate function remapping 1 (RX on PB8, TX on PB9) */
-    AFIO_REMAP_CAN_2         = AFIO_MAPR_CAN_REMAP_PD0_PD1, /**<
-        CAN alternate function remapping 2 (RX on PD0, TX on PD1) */
-    AFIO_REMAP_TIM4          = AFIO_MAPR_TIM4_REMAP, /**<
-        Timer 4 remapping */
-    AFIO_REMAP_TIM3_PARTIAL  = AFIO_MAPR_TIM3_REMAP_PARTIAL, /**<
-        Timer 3 partial remapping */
-    AFIO_REMAP_TIM3_FULL      = AFIO_MAPR_TIM3_REMAP_FULL, /**<
-        Timer 3 full remapping */
-    AFIO_REMAP_TIM2_PARTIAL_1 = AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3, /**<
-        Timer 2 partial remapping 1 (CH1 and ETR on PA15, CH2 on PB3, CH3
-        on PA2, CH4 on PA3) */
-    AFIO_REMAP_TIM2_PARTIAL_2 = AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11, /**<
-        Timer 2 partial remapping 2 (CH1 and ETR on PA0, CH2 on PA1, CH3
-        on PB10, CH4 on PB11) */
-    AFIO_REMAP_TIM2_FULL      = AFIO_MAPR_TIM2_REMAP_FULL, /**<
-        Timer 2 full remapping */
-    AFIO_REMAP_USART2        = AFIO_MAPR_USART2_REMAP, /**<
-        USART 2 remapping */
-    AFIO_REMAP_USART1        = AFIO_MAPR_USART1_REMAP, /**<
-        USART 1 remapping */
-    AFIO_REMAP_I2C1          = AFIO_MAPR_I2C1_REMAP, /**<
-        I2C 1 remapping */
-    AFIO_REMAP_SPI1          = AFIO_MAPR_SPI1_REMAP, /**<
-        SPI 1 remapping */
-    AFIO_REMAP_FSMC_NADV     = (AFIO_MAPR2_FSMC_NADV |
-                                AFIO_REMAP_USE_MAPR2), /**<
-        NADV signal not connected */
-    AFIO_REMAP_TIM14         = (AFIO_MAPR2_TIM14_REMAP |
-                                AFIO_REMAP_USE_MAPR2), /**<
-        Timer 14 remapping */
-    AFIO_REMAP_TIM13         = (AFIO_MAPR2_TIM13_REMAP |
-                                AFIO_REMAP_USE_MAPR2), /**<
-        Timer 13 remapping */
-    AFIO_REMAP_TIM11         = (AFIO_MAPR2_TIM11_REMAP |
-                                AFIO_REMAP_USE_MAPR2), /**<
-        Timer 11 remapping */
-    AFIO_REMAP_TIM10         = (AFIO_MAPR2_TIM10_REMAP |
-                                AFIO_REMAP_USE_MAPR2), /**<
-        Timer 10 remapping */
-    AFIO_REMAP_TIM9          = (AFIO_MAPR2_TIM9_REMAP |
-                                AFIO_REMAP_USE_MAPR2) /**<
-        Timer 9 */
-} afio_remap_peripheral;
-
-void afio_remap(afio_remap_peripheral p);
-
-/**
- * @brief Debug port configuration
- *
- * Used to configure the behavior of JTAG and Serial Wire (SW) debug
- * ports and their associated GPIO pins.
- *
- * @see afio_cfg_debug_ports()
- */
-typedef enum afio_debug_cfg {
-    AFIO_DEBUG_FULL_SWJ = AFIO_MAPR_SWJ_CFG_FULL_SWJ, /**<
-                                   Full Serial Wire and JTAG debug */
-    AFIO_DEBUG_FULL_SWJ_NO_NJRST = AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST, /**<
-                                   Full Serial Wire and JTAG, but no NJTRST. */
-    AFIO_DEBUG_SW_ONLY = AFIO_MAPR_SWJ_CFG_NO_JTAG_SW, /**<
-                                   Serial Wire debug only (JTAG-DP disabled,
-                                   SW-DP enabled) */
-    AFIO_DEBUG_NONE = AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW /**<
-                                   No debug; all JTAG and SW pins are free
-                                   for use as GPIOs. */
-} afio_debug_cfg;
-
-/**
- * @brief Enable or disable the JTAG and SW debug ports.
- * @param config Desired debug port configuration
- * @see afio_debug_cfg
- */
-static inline void afio_cfg_debug_ports(afio_debug_cfg config) {
-    //__io uint32 *mapr = &AFIO_BASE->MAPR;
-    //*mapr = (*mapr & ~AFIO_MAPR_SWJ_CFG) | config;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
diff --git a/STM32F4/cores/maple/libmaple/rcc.c b/STM32F4/cores/maple/libmaple/rcc.c
deleted file mode 100644
index b3cb9c5d1..000000000
--- a/STM32F4/cores/maple/libmaple/rcc.c
+++ /dev/null
@@ -1,37 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file rcc.c
- * @brief Implements pretty much only the basic clock setup on the
- *        stm32, clock enable/disable and peripheral reset commands.
- */
-
-// #ifdef STM32F2
-// #include "rccF2.c"
-// #else
-// #include "rccF1.c"
-// #endif
diff --git a/STM32F4/cores/maple/libmaple/rccF1.c b/STM32F4/cores/maple/libmaple/rccF1.c
deleted file mode 100644
index 9eb56b872..000000000
--- a/STM32F4/cores/maple/libmaple/rccF1.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
- #ifdef STM32F1
- 
-/**
- * @file rcc.c
- * @brief Implements pretty much only the basic clock setup on the
- *        stm32, clock enable/disable and peripheral reset commands.
- */
-
-#include "libmaple.h"
-#include "flash.h"
-#include "rcc.h"
-#include "bitband.h"
-
-#define APB1                            RCC_APB1
-#define APB2                            RCC_APB2
-#define AHB                             RCC_AHB
-
-struct rcc_dev_info {
-    const rcc_clk_domain clk_domain;
-    const uint8 line_num;
-};
-
-/* Device descriptor table, maps rcc_clk_id onto bus and enable/reset
- * register bit numbers. */
-static const struct rcc_dev_info rcc_dev_table[] = {
-    [RCC_GPIOA]  = { .clk_domain = APB2, .line_num = 2 },
-    [RCC_GPIOB]  = { .clk_domain = APB2, .line_num = 3 },
-    [RCC_GPIOC]  = { .clk_domain = APB2, .line_num = 4 },
-    [RCC_GPIOD]  = { .clk_domain = APB2, .line_num = 5 },
-    [RCC_AFIO]   = { .clk_domain = APB2, .line_num = 0 },
-    [RCC_ADC1]   = { .clk_domain = APB2, .line_num = 9 },
-    [RCC_ADC2]   = { .clk_domain = APB2, .line_num = 10 },
-    [RCC_ADC3]   = { .clk_domain = APB2, .line_num = 15 },
-    [RCC_USART1] = { .clk_domain = APB2, .line_num = 14 },
-    [RCC_USART2] = { .clk_domain = APB1, .line_num = 17 },
-    [RCC_USART3] = { .clk_domain = APB1, .line_num = 18 },
-    [RCC_TIMER1] = { .clk_domain = APB2, .line_num = 11 },
-    [RCC_TIMER2] = { .clk_domain = APB1, .line_num = 0 },
-    [RCC_TIMER3] = { .clk_domain = APB1, .line_num = 1 },
-    [RCC_TIMER4] = { .clk_domain = APB1, .line_num = 2 },
-    [RCC_SPI1]   = { .clk_domain = APB2, .line_num = 12 },
-    [RCC_SPI2]   = { .clk_domain = APB1, .line_num = 14 },
-    [RCC_DMA1]   = { .clk_domain = AHB,  .line_num = 0 },
-    [RCC_PWR]    = { .clk_domain = APB1, .line_num = 28},
-    [RCC_BKP]    = { .clk_domain = APB1, .line_num = 27},
-    [RCC_I2C1]   = { .clk_domain = APB1, .line_num = 21 },
-    [RCC_I2C2]   = { .clk_domain = APB1, .line_num = 22 },
-    [RCC_CRC]    = { .clk_domain = AHB,  .line_num = 6},
-    [RCC_FLITF]  = { .clk_domain = AHB,  .line_num = 4},
-    [RCC_SRAM]   = { .clk_domain = AHB,  .line_num = 2},
-#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
-    [RCC_GPIOE]  = { .clk_domain = APB2, .line_num = 6 },
-    [RCC_GPIOF]  = { .clk_domain = APB2, .line_num = 7 },
-    [RCC_GPIOG]  = { .clk_domain = APB2, .line_num = 8 },
-    [RCC_UART4]  = { .clk_domain = APB1, .line_num = 19 },
-    [RCC_UART5]  = { .clk_domain = APB1, .line_num = 20 },
-    [RCC_TIMER5] = { .clk_domain = APB1, .line_num = 3 },
-    [RCC_TIMER6] = { .clk_domain = APB1, .line_num = 4 },
-    [RCC_TIMER7] = { .clk_domain = APB1, .line_num = 5 },
-    [RCC_TIMER8] = { .clk_domain = APB2, .line_num = 13 },
-    [RCC_FSMC]   = { .clk_domain = AHB,  .line_num = 8 },
-    [RCC_DAC]    = { .clk_domain = APB1, .line_num = 29 },
-    [RCC_DMA2]   = { .clk_domain = AHB,  .line_num = 1 },
-    [RCC_SDIO]   = { .clk_domain = AHB,  .line_num = 10 },
-    [RCC_SPI3]   = { .clk_domain = APB1, .line_num = 15 },
-#endif
-#ifdef STM32_XL_DENSITY
-    [RCC_TIMER9]  = { .clk_domain = APB2, .line_num = 19 },
-    [RCC_TIMER10] = { .clk_domain = APB2, .line_num = 20 },
-    [RCC_TIMER11] = { .clk_domain = APB2, .line_num = 21 },
-    [RCC_TIMER12] = { .clk_domain = APB1, .line_num = 6 },
-    [RCC_TIMER13] = { .clk_domain = APB1, .line_num = 7 },
-    [RCC_TIMER14] = { .clk_domain = APB1, .line_num = 8 },
-#endif
-};
-
-/**
- * @brief Initialize the clock control system. Initializes the system
- *        clock source to use the PLL driven by an external oscillator
- * @param sysclk_src system clock source, must be PLL
- * @param pll_src pll clock source, must be HSE
- * @param pll_mul pll multiplier
- */
-void rcc_clk_init(rcc_sysclk_src sysclk_src,
-                  rcc_pllsrc pll_src,
-                  rcc_pll_multiplier pll_mul) {
-    uint32 cfgr = 0;
-    uint32 cr;
-
-    /* Assume that we're going to clock the chip off the PLL, fed by
-     * the HSE */
-    ASSERT(sysclk_src == RCC_CLKSRC_PLL &&
-           pll_src    == RCC_PLLSRC_HSE);
-
-    RCC_BASE->CFGR = pll_src | pll_mul;
-
-    /* Turn on the HSE */
-    cr = RCC_BASE->CR;
-    cr |= RCC_CR_HSEON;
-    RCC_BASE->CR = cr;
-    while (!(RCC_BASE->CR & RCC_CR_HSERDY))
-        ;
-
-    /* Now the PLL */
-    cr |= RCC_CR_PLLON;
-    RCC_BASE->CR = cr;
-    while (!(RCC_BASE->CR & RCC_CR_PLLRDY))
-        ;
-
-    /* Finally, let's switch over to the PLL */
-    cfgr &= ~RCC_CFGR_SW;
-    cfgr |= RCC_CFGR_SW_PLL;
-    RCC_BASE->CFGR = cfgr;
-    while ((RCC_BASE->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL)
-        ;
-}
-
-/**
- * @brief Turn on the clock line on a peripheral
- * @param id Clock ID of the peripheral to turn on.
- */
-void rcc_clk_enable(rcc_clk_id id) {
-    static const __io uint32* enable_regs[] = {
-        [APB1] = &RCC_BASE->APB1ENR,
-        [APB2] = &RCC_BASE->APB2ENR,
-        [AHB] = &RCC_BASE->AHBENR,
-    };
-
-    rcc_clk_domain clk_domain = rcc_dev_clk(id);
-    __io uint32* enr = (__io uint32*)enable_regs[clk_domain];
-    uint8 lnum = rcc_dev_table[id].line_num;
-
-    bb_peri_set_bit(enr, lnum, 1);
-}
-
-/**
- * @brief Reset a peripheral.
- * @param id Clock ID of the peripheral to reset.
- */
-void rcc_reset_dev(rcc_clk_id id) {
-    static const __io uint32* reset_regs[] = {
-        [APB1] = &RCC_BASE->APB1RSTR,
-        [APB2] = &RCC_BASE->APB2RSTR,
-    };
-
-    rcc_clk_domain clk_domain = rcc_dev_clk(id);
-    __io void* addr = (__io void*)reset_regs[clk_domain];
-    uint8 lnum = rcc_dev_table[id].line_num;
-
-    bb_peri_set_bit(addr, lnum, 1);
-    bb_peri_set_bit(addr, lnum, 0);
-}
-
-/**
- * @brief Get a peripheral's clock domain
- * @param id Clock ID of the peripheral whose clock domain to return
- * @return Clock source for the given clock ID
- */
-rcc_clk_domain rcc_dev_clk(rcc_clk_id id) {
-    return rcc_dev_table[id].clk_domain;
-}
-
-/**
- * @brief Get a peripheral's clock domain speed
- * @param id Clock ID of the peripheral whose clock domain speed to return
- * @return Clock speed for the given clock ID
- */
-uint32 rcc_dev_clk_speed(rcc_clk_id id) {
-    static const uint32 rcc_dev_clk_speed_table[] = {
-        [RCC_AHB]  = 72000000,
-        [RCC_APB1] = 36000000,
-        [RCC_APB2] = 72000000
-	  };
-    return rcc_dev_clk_speed_table[rcc_dev_clk(id)];
-}
-
-/**
- * @brief Get a peripheral's timer clock domain speed
- * @param id Clock ID of the peripheral whose clock domain speed to return
- * @return Clock speed for the given clock ID
- */
-uint32 rcc_dev_timer_clk_speed(rcc_clk_id id) {
-    return rcc_dev_clk_speed(RCC_APB2); // 72 MHz for all counter
-}
-
-/**
- * @brief Set the divider on a peripheral prescaler
- * @param prescaler prescaler to set
- * @param divider prescaler divider
- */
-void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider) {
-    static const uint32 masks[] = {
-        [RCC_PRESCALER_AHB] = RCC_CFGR_HPRE,
-        [RCC_PRESCALER_APB1] = RCC_CFGR_PPRE1,
-        [RCC_PRESCALER_APB2] = RCC_CFGR_PPRE2,
-        [RCC_PRESCALER_USB] = RCC_CFGR_USBPRE,
-        [RCC_PRESCALER_ADC] = RCC_CFGR_ADCPRE,
-    };
-
-    uint32 cfgr = RCC_BASE->CFGR;
-    cfgr &= ~masks[prescaler];
-    cfgr |= divider;
-    RCC_BASE->CFGR = cfgr;
-}
-
-
-#endif
diff --git a/STM32F4/cores/maple/libmaple/rccF1.h b/STM32F4/cores/maple/libmaple/rccF1.h
deleted file mode 100644
index dd79704d8..000000000
--- a/STM32F4/cores/maple/libmaple/rccF1.h
+++ /dev/null
@@ -1,572 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file rcc.h
- * @brief reset and clock control definitions and prototypes
- */
-
-#include "libmaple_types.h"
-
-#ifndef _RCC_H_
-#define _RCC_H_
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-/** RCC register map type */
-typedef struct rcc_reg_map {
-    __io uint32 CR;             /**< Clock control register */
-    __io uint32 CFGR;           /**< Clock configuration register */
-    __io uint32 CIR;            /**< Clock interrupt register */
-    __io uint32 APB2RSTR;       /**< APB2 peripheral reset register */
-    __io uint32 APB1RSTR;       /**< APB1 peripheral reset register */
-    __io uint32 AHBENR;         /**< AHB peripheral clock enable register */
-    __io uint32 APB2ENR;        /**< APB2 peripheral clock enable register */
-    __io uint32 APB1ENR;        /**< APB1 peripheral clock enable register */
-    __io uint32 BDCR;           /**< Backup domain control register */
-    __io uint32 CSR;            /**< Control/status register */
-} rcc_reg_map;
-
-/** RCC register map base pointer */
-#define RCC_BASE                        ((struct rcc_reg_map*)0x40021000)
-
-/*
- * Register bit definitions
- */
-
-/* Clock control register */
-
-#define RCC_CR_PLLRDY_BIT               25
-#define RCC_CR_PLLON_BIT                24
-#define RCC_CR_CSSON_BIT                19
-#define RCC_CR_HSEBYP_BIT               18
-#define RCC_CR_HSERDY_BIT               17
-#define RCC_CR_HSEON_BIT                16
-#define RCC_CR_HSIRDY_BIT               1
-#define RCC_CR_HSION_BIT                0
-
-#define RCC_CR_PLLRDY                   BIT(RCC_CR_PLLRDY_BIT)
-#define RCC_CR_PLLON                    BIT(RCC_CR_PLLON_BIT)
-#define RCC_CR_CSSON                    BIT(RCC_CR_CSSON_BIT)
-#define RCC_CR_HSEBYP                   BIT(RCC_CR_HSEBYP_BIT)
-#define RCC_CR_HSERDY                   BIT(RCC_CR_HSERDY_BIT)
-#define RCC_CR_HSEON                    BIT(RCC_CR_HSEON_BIT)
-#define RCC_CR_HSICAL                   (0xFF << 8)
-#define RCC_CR_HSITRIM                  (0x1F << 3)
-#define RCC_CR_HSIRDY                   BIT(RCC_CR_HSIRDY_BIT)
-#define RCC_CR_HSION                    BIT(RCC_CR_HSION_BIT)
-
-/* Clock configuration register */
-
-#define RCC_CFGR_USBPRE_BIT             22
-#define RCC_CFGR_PLLXTPRE_BIT           17
-#define RCC_CFGR_PLLSRC_BIT             16
-
-#define RCC_CFGR_MCO                    (0x3 << 24)
-#define RCC_CFGR_USBPRE                 BIT(RCC_CFGR_USBPRE_BIT)
-#define RCC_CFGR_PLLMUL                 (0xF << 18)
-#define RCC_CFGR_PLLXTPRE               BIT(RCC_CFGR_PLLXTPRE_BIT)
-#define RCC_CFGR_PLLSRC                 BIT(RCC_CFGR_PLLSRC_BIT)
-#define RCC_CFGR_ADCPRE                 (0x3 << 14)
-#define RCC_CFGR_PPRE2                  (0x7 << 11)
-#define RCC_CFGR_PPRE1                  (0x7 << 8)
-#define RCC_CFGR_HPRE                   (0xF << 4)
-#define RCC_CFGR_SWS                    (0x3 << 2)
-#define RCC_CFGR_SWS_PLL                (0x2 << 2)
-#define RCC_CFGR_SWS_HSE                (0x1 << 2)
-#define RCC_CFGR_SW                     0x3
-#define RCC_CFGR_SW_PLL                 0x2
-#define RCC_CFGR_SW_HSE                 0x1
-
-/* Clock interrupt register */
-
-#define RCC_CIR_CSSC_BIT                23
-#define RCC_CIR_PLLRDYC_BIT             20
-#define RCC_CIR_HSERDYC_BIT             19
-#define RCC_CIR_HSIRDYC_BIT             18
-#define RCC_CIR_LSERDYC_BIT             17
-#define RCC_CIR_LSIRDYC_BIT             16
-#define RCC_CIR_PLLRDYIE_BIT            12
-#define RCC_CIR_HSERDYIE_BIT            11
-#define RCC_CIR_HSIRDYIE_BIT            10
-#define RCC_CIR_LSERDYIE_BIT            9
-#define RCC_CIR_LSIRDYIE_BIT            8
-#define RCC_CIR_CSSF_BIT                7
-#define RCC_CIR_PLLRDYF_BIT             4
-#define RCC_CIR_HSERDYF_BIT             3
-#define RCC_CIR_HSIRDYF_BIT             2
-#define RCC_CIR_LSERDYF_BIT             1
-#define RCC_CIR_LSIRDYF_BIT             0
-
-#define RCC_CIR_CSSC                    BIT(RCC_CIR_CSSC_BIT)
-#define RCC_CIR_PLLRDYC                 BIT(RCC_CIR_PLLRDYC_BIT)
-#define RCC_CIR_HSERDYC                 BIT(RCC_CIR_HSERDYC_BIT)
-#define RCC_CIR_HSIRDYC                 BIT(RCC_CIR_HSIRDYC_BIT)
-#define RCC_CIR_LSERDYC                 BIT(RCC_CIR_LSERDYC_BIT)
-#define RCC_CIR_LSIRDYC                 BIT(RCC_CIR_LSIRDYC_BIT)
-#define RCC_CIR_PLLRDYIE                BIT(RCC_CIR_PLLRDYIE_BIT)
-#define RCC_CIR_HSERDYIE                BIT(RCC_CIR_HSERDYIE_BIT)
-#define RCC_CIR_HSIRDYIE                BIT(RCC_CIR_HSIRDYIE_BIT)
-#define RCC_CIR_LSERDYIE                BIT(RCC_CIR_LSERDYIE_BIT)
-#define RCC_CIR_LSIRDYIE                BIT(RCC_CIR_LSIRDYIE_BIT)
-#define RCC_CIR_CSSF                    BIT(RCC_CIR_CSSF_BIT)
-#define RCC_CIR_PLLRDYF                 BIT(RCC_CIR_PLLRDYF_BIT)
-#define RCC_CIR_HSERDYF                 BIT(RCC_CIR_HSERDYF_BIT)
-#define RCC_CIR_HSIRDYF                 BIT(RCC_CIR_HSIRDYF_BIT)
-#define RCC_CIR_LSERDYF                 BIT(RCC_CIR_LSERDYF_BIT)
-#define RCC_CIR_LSIRDYF                 BIT(RCC_CIR_LSIRDYF_BIT)
-
-/* APB2 peripheral reset register */
-
-#define RCC_APB2RSTR_TIM11RST_BIT       21
-#define RCC_APB2RSTR_TIM10RST_BIT       20
-#define RCC_APB2RSTR_TIM9RST_BIT        19
-#define RCC_APB2RSTR_ADC3RST_BIT        15
-#define RCC_APB2RSTR_USART1RST_BIT      14
-#define RCC_APB2RSTR_TIM8RST_BIT        13
-#define RCC_APB2RSTR_SPI1RST_BIT        12
-#define RCC_APB2RSTR_TIM1RST_BIT        11
-#define RCC_APB2RSTR_ADC2RST_BIT        10
-#define RCC_APB2RSTR_ADC1RST_BIT        9
-#define RCC_APB2RSTR_IOPGRST_BIT        8
-#define RCC_APB2RSTR_IOPFRST_BIT        7
-#define RCC_APB2RSTR_IOPERST_BIT        6
-#define RCC_APB2RSTR_IOPDRST_BIT        5
-#define RCC_APB2RSTR_IOPCRST_BIT        4
-#define RCC_APB2RSTR_IOPBRST_BIT        3
-#define RCC_APB2RSTR_IOPARST_BIT        2
-#define RCC_APB2RSTR_AFIORST_BIT        0
-
-#define RCC_APB2RSTR_TIM11RST           BIT(RCC_APB2RSTR_TIM11RST_BIT)
-#define RCC_APB2RSTR_TIM10RST           BIT(RCC_APB2RSTR_TIM10RST_BIT)
-#define RCC_APB2RSTR_TIM9RST            BIT(RCC_APB2RSTR_TIM9RST_BIT)
-#define RCC_APB2RSTR_ADC3RST            BIT(RCC_APB2RSTR_ADC3RST_BIT)
-#define RCC_APB2RSTR_USART1RST          BIT(RCC_APB2RSTR_USART1RST_BIT)
-#define RCC_APB2RSTR_TIM8RST            BIT(RCC_APB2RSTR_TIM8RST_BIT)
-#define RCC_APB2RSTR_SPI1RST            BIT(RCC_APB2RSTR_SPI1RST_BIT)
-#define RCC_APB2RSTR_TIM1RST            BIT(RCC_APB2RSTR_TIM1RST_BIT)
-#define RCC_APB2RSTR_ADC2RST            BIT(RCC_APB2RSTR_ADC2RST_BIT)
-#define RCC_APB2RSTR_ADC1RST            BIT(RCC_APB2RSTR_ADC1RST_BIT)
-#define RCC_APB2RSTR_IOPGRST            BIT(RCC_APB2RSTR_IOPGRST_BIT)
-#define RCC_APB2RSTR_IOPFRST            BIT(RCC_APB2RSTR_IOPFRST_BIT)
-#define RCC_APB2RSTR_IOPERST            BIT(RCC_APB2RSTR_IOPERST_BIT)
-#define RCC_APB2RSTR_IOPDRST            BIT(RCC_APB2RSTR_IOPDRST_BIT)
-#define RCC_APB2RSTR_IOPCRST            BIT(RCC_APB2RSTR_IOPCRST_BIT)
-#define RCC_APB2RSTR_IOPBRST            BIT(RCC_APB2RSTR_IOPBRST_BIT)
-#define RCC_APB2RSTR_IOPARST            BIT(RCC_APB2RSTR_IOPARST_BIT)
-#define RCC_APB2RSTR_AFIORST            BIT(RCC_APB2RSTR_AFIORST_BIT)
-
-/* APB1 peripheral reset register */
-
-#define RCC_APB1RSTR_DACRST_BIT         29
-#define RCC_APB1RSTR_PWRRST_BIT         28
-#define RCC_APB1RSTR_BKPRST_BIT         27
-#define RCC_APB1RSTR_CANRST_BIT         25
-#define RCC_APB1RSTR_USBRST_BIT         23
-#define RCC_APB1RSTR_I2C2RST_BIT        22
-#define RCC_APB1RSTR_I2C1RST_BIT        21
-#define RCC_APB1RSTR_UART5RST_BIT       20
-#define RCC_APB1RSTR_UART4RST_BIT       19
-#define RCC_APB1RSTR_USART3RST_BIT      18
-#define RCC_APB1RSTR_USART2RST_BIT      17
-#define RCC_APB1RSTR_SPI3RST_BIT        15
-#define RCC_APB1RSTR_SPI2RST_BIT        14
-#define RCC_APB1RSTR_WWDRST_BIT         11
-#define RCC_APB1RSTR_TIM14RST_BIT       8
-#define RCC_APB1RSTR_TIM13RST_BIT       7
-#define RCC_APB1RSTR_TIM12RST_BIT       6
-#define RCC_APB1RSTR_TIM7RST_BIT        5
-#define RCC_APB1RSTR_TIM6RST_BIT        4
-#define RCC_APB1RSTR_TIM5RST_BIT        3
-#define RCC_APB1RSTR_TIM4RST_BIT        2
-#define RCC_APB1RSTR_TIM3RST_BIT        1
-#define RCC_APB1RSTR_TIM2RST_BIT        0
-
-#define RCC_APB1RSTR_DACRST             BIT(RCC_APB1RSTR_DACRST_BIT)
-#define RCC_APB1RSTR_PWRRST             BIT(RCC_APB1RSTR_PWRRST_BIT)
-#define RCC_APB1RSTR_BKPRST             BIT(RCC_APB1RSTR_BKPRST_BIT)
-#define RCC_APB1RSTR_CANRST             BIT(RCC_APB1RSTR_CANRST_BIT)
-#define RCC_APB1RSTR_USBRST             BIT(RCC_APB1RSTR_USBRST_BIT)
-#define RCC_APB1RSTR_I2C2RST            BIT(RCC_APB1RSTR_I2C2RST_BIT)
-#define RCC_APB1RSTR_I2C1RST            BIT(RCC_APB1RSTR_I2C1RST_BIT)
-#define RCC_APB1RSTR_UART5RST           BIT(RCC_APB1RSTR_UART5RST_BIT)
-#define RCC_APB1RSTR_UART4RST           BIT(RCC_APB1RSTR_UART4RST_BIT)
-#define RCC_APB1RSTR_USART3RST          BIT(RCC_APB1RSTR_USART3RST_BIT)
-#define RCC_APB1RSTR_USART2RST          BIT(RCC_APB1RSTR_USART2RST_BIT)
-#define RCC_APB1RSTR_SPI3RST            BIT(RCC_APB1RSTR_SPI3RST_BIT)
-#define RCC_APB1RSTR_SPI2RST            BIT(RCC_APB1RSTR_SPI2RST_BIT)
-#define RCC_APB1RSTR_WWDRST             BIT(RCC_APB1RSTR_WWDRST_BIT)
-#define RCC_APB1RSTR_TIM14RST           BIT(RCC_APB1RSTR_TIM14RST_BIT)
-#define RCC_APB1RSTR_TIM13RST           BIT(RCC_APB1RSTR_TIM13RST_BIT)
-#define RCC_APB1RSTR_TIM12RST           BIT(RCC_APB1RSTR_TIM12RST_BIT)
-#define RCC_APB1RSTR_TIM7RST            BIT(RCC_APB1RSTR_TIM7RST_BIT)
-#define RCC_APB1RSTR_TIM6RST            BIT(RCC_APB1RSTR_TIM6RST_BIT)
-#define RCC_APB1RSTR_TIM5RST            BIT(RCC_APB1RSTR_TIM5RST_BIT)
-#define RCC_APB1RSTR_TIM4RST            BIT(RCC_APB1RSTR_TIM4RST_BIT)
-#define RCC_APB1RSTR_TIM3RST            BIT(RCC_APB1RSTR_TIM3RST_BIT)
-#define RCC_APB1RSTR_TIM2RST            BIT(RCC_APB1RSTR_TIM2RST_BIT)
-
-/* AHB peripheral clock enable register */
-
-#define RCC_AHBENR_SDIOEN_BIT           10
-#define RCC_AHBENR_FSMCEN_BIT           8
-#define RCC_AHBENR_CRCEN_BIT            7
-#define RCC_AHBENR_FLITFEN_BIT          4
-#define RCC_AHBENR_SRAMEN_BIT           2
-#define RCC_AHBENR_DMA2EN_BIT           1
-#define RCC_AHBENR_DMA1EN_BIT           0
-
-#define RCC_AHBENR_SDIOEN               BIT(RCC_AHBENR_SDIOEN_BIT)
-#define RCC_AHBENR_FSMCEN               BIT(RCC_AHBENR_FSMCEN_BIT)
-#define RCC_AHBENR_CRCEN                BIT(RCC_AHBENR_CRCEN_BIT)
-#define RCC_AHBENR_FLITFEN              BIT(RCC_AHBENR_FLITFEN_BIT)
-#define RCC_AHBENR_SRAMEN               BIT(RCC_AHBENR_SRAMEN_BIT)
-#define RCC_AHBENR_DMA2EN               BIT(RCC_AHBENR_DMA2EN_BIT)
-#define RCC_AHBENR_DMA1EN               BIT(RCC_AHBENR_DMA1EN_BIT)
-
-/* APB2 peripheral clock enable register */
-
-#define RCC_APB2ENR_TIM11EN_BIT         21
-#define RCC_APB2ENR_TIM10EN_BIT         20
-#define RCC_APB2ENR_TIM9EN_BIT          19
-#define RCC_APB2ENR_ADC3EN_BIT          15
-#define RCC_APB2ENR_USART1EN_BIT        14
-#define RCC_APB2ENR_TIM8EN_BIT          13
-#define RCC_APB2ENR_SPI1EN_BIT          12
-#define RCC_APB2ENR_TIM1EN_BIT          11
-#define RCC_APB2ENR_ADC2EN_BIT          10
-#define RCC_APB2ENR_ADC1EN_BIT          9
-#define RCC_APB2ENR_IOPGEN_BIT          8
-#define RCC_APB2ENR_IOPFEN_BIT          7
-#define RCC_APB2ENR_IOPEEN_BIT          6
-#define RCC_APB2ENR_IOPDEN_BIT          5
-#define RCC_APB2ENR_IOPCEN_BIT          4
-#define RCC_APB2ENR_IOPBEN_BIT          3
-#define RCC_APB2ENR_IOPAEN_BIT          2
-#define RCC_APB2ENR_AFIOEN_BIT          0
-
-#define RCC_APB2ENR_TIM11EN             BIT(RCC_APB2ENR_TIM11EN_BIT)
-#define RCC_APB2ENR_TIM10EN             BIT(RCC_APB2ENR_TIM10EN_BIT)
-#define RCC_APB2ENR_TIM9EN              BIT(RCC_APB2ENR_TIM9EN_BIT)
-#define RCC_APB2ENR_ADC3EN              BIT(RCC_APB2ENR_ADC3EN_BIT)
-#define RCC_APB2ENR_USART1EN            BIT(RCC_APB2ENR_USART1EN_BIT)
-#define RCC_APB2ENR_TIM8EN              BIT(RCC_APB2ENR_TIM8EN_BIT)
-#define RCC_APB2ENR_SPI1EN              BIT(RCC_APB2ENR_SPI1EN_BIT)
-#define RCC_APB2ENR_TIM1EN              BIT(RCC_APB2ENR_TIM1EN_BIT)
-#define RCC_APB2ENR_ADC2EN              BIT(RCC_APB2ENR_ADC2EN_BIT)
-#define RCC_APB2ENR_ADC1EN              BIT(RCC_APB2ENR_ADC1EN_BIT)
-#define RCC_APB2ENR_IOPGEN              BIT(RCC_APB2ENR_IOPGEN_BIT)
-#define RCC_APB2ENR_IOPFEN              BIT(RCC_APB2ENR_IOPFEN_BIT)
-#define RCC_APB2ENR_IOPEEN              BIT(RCC_APB2ENR_IOPEEN_BIT)
-#define RCC_APB2ENR_IOPDEN              BIT(RCC_APB2ENR_IOPDEN_BIT)
-#define RCC_APB2ENR_IOPCEN              BIT(RCC_APB2ENR_IOPCEN_BIT)
-#define RCC_APB2ENR_IOPBEN              BIT(RCC_APB2ENR_IOPBEN_BIT)
-#define RCC_APB2ENR_IOPAEN              BIT(RCC_APB2ENR_IOPAEN_BIT)
-#define RCC_APB2ENR_AFIOEN              BIT(RCC_APB2ENR_AFIOEN_BIT)
-
-/* APB1 peripheral clock enable register */
-
-#define RCC_APB1ENR_DACEN_BIT           29
-#define RCC_APB1ENR_PWREN_BIT           28
-#define RCC_APB1ENR_BKPEN_BIT           27
-#define RCC_APB1ENR_CANEN_BIT           25
-#define RCC_APB1ENR_USBEN_BIT           23
-#define RCC_APB1ENR_I2C2EN_BIT          22
-#define RCC_APB1ENR_I2C1EN_BIT          21
-#define RCC_APB1ENR_UART5EN_BIT         20
-#define RCC_APB1ENR_UART4EN_BIT         19
-#define RCC_APB1ENR_USART3EN_BIT        18
-#define RCC_APB1ENR_USART2EN_BIT        17
-#define RCC_APB1ENR_SPI3EN_BIT          15
-#define RCC_APB1ENR_SPI2EN_BIT          14
-#define RCC_APB1ENR_WWDEN_BIT           11
-#define RCC_APB1ENR_TIM14EN_BIT         8
-#define RCC_APB1ENR_TIM13EN_BIT         7
-#define RCC_APB1ENR_TIM12EN_BIT         6
-#define RCC_APB1ENR_TIM7EN_BIT          5
-#define RCC_APB1ENR_TIM6EN_BIT          4
-#define RCC_APB1ENR_TIM5EN_BIT          3
-#define RCC_APB1ENR_TIM4EN_BIT          2
-#define RCC_APB1ENR_TIM3EN_BIT          1
-#define RCC_APB1ENR_TIM2EN_BIT          0
-
-#define RCC_APB1ENR_DACEN               BIT(RCC_APB1ENR_DACEN_BIT)
-#define RCC_APB1ENR_PWREN               BIT(RCC_APB1ENR_PWREN_BIT)
-#define RCC_APB1ENR_BKPEN               BIT(RCC_APB1ENR_BKPEN_BIT)
-#define RCC_APB1ENR_CANEN               BIT(RCC_APB1ENR_CANEN_BIT)
-#define RCC_APB1ENR_USBEN               BIT(RCC_APB1ENR_USBEN_BIT)
-#define RCC_APB1ENR_I2C2EN              BIT(RCC_APB1ENR_I2C2EN_BIT)
-#define RCC_APB1ENR_I2C1EN              BIT(RCC_APB1ENR_I2C1EN_BIT)
-#define RCC_APB1ENR_UART5EN             BIT(RCC_APB1ENR_UART5EN_BIT)
-#define RCC_APB1ENR_UART4EN             BIT(RCC_APB1ENR_UART4EN_BIT)
-#define RCC_APB1ENR_USART3EN            BIT(RCC_APB1ENR_USART3EN_BIT)
-#define RCC_APB1ENR_USART2EN            BIT(RCC_APB1ENR_USART2EN_BIT)
-#define RCC_APB1ENR_SPI3EN              BIT(RCC_APB1ENR_SPI3EN_BIT)
-#define RCC_APB1ENR_SPI2EN              BIT(RCC_APB1ENR_SPI2EN_BIT)
-#define RCC_APB1ENR_WWDEN               BIT(RCC_APB1ENR_WWDEN_BIT)
-#define RCC_APB1ENR_TIM14EN             BIT(RCC_APB1ENR_TIM14EN_BIT)
-#define RCC_APB1ENR_TIM13EN             BIT(RCC_APB1ENR_TIM13EN_BIT)
-#define RCC_APB1ENR_TIM12EN             BIT(RCC_APB1ENR_TIM12EN_BIT)
-#define RCC_APB1ENR_TIM7EN              BIT(RCC_APB1ENR_TIM7EN_BIT)
-#define RCC_APB1ENR_TIM6EN              BIT(RCC_APB1ENR_TIM6EN_BIT)
-#define RCC_APB1ENR_TIM5EN              BIT(RCC_APB1ENR_TIM5EN_BIT)
-#define RCC_APB1ENR_TIM4EN              BIT(RCC_APB1ENR_TIM4EN_BIT)
-#define RCC_APB1ENR_TIM3EN              BIT(RCC_APB1ENR_TIM3EN_BIT)
-#define RCC_APB1ENR_TIM2EN              BIT(RCC_APB1ENR_TIM2EN_BIT)
-
-/* Backup domain control register */
-
-#define RCC_BDCR_BDRST_BIT              16
-#define RCC_BDCR_RTCEN_BIT              15
-#define RCC_BDCR_LSEBYP_BIT             2
-#define RCC_BDCR_LSERDY_BIT             1
-#define RCC_BDCR_LSEON_BIT              0
-
-#define RCC_BDCR_BDRST                  BIT(RCC_BDCR_BDRST_BIT)
-#define RCC_BDCR_RTCEN                  BIT(RCC_BDCR_RTC_BIT)
-#define RCC_BDCR_RTCSEL                 (0x3 << 8)
-#define RCC_BDCR_RTCSEL_NONE            (0x0 << 8)
-#define RCC_BDCR_RTCSEL_LSE             (0x1 << 8)
-#define RCC_BDCR_RTCSEL_HSE             (0x3 << 8)
-#define RCC_BDCR_LSEBYP                 BIT(RCC_BDCR_LSEBYP_BIT)
-#define RCC_BDCR_LSERDY                 BIT(RCC_BDCR_LSERDY_BIT)
-#define RCC_BDCR_LSEON                  BIT(RCC_BDCR_LSEON_BIT)
-
-/* Control/status register */
-
-#define RCC_CSR_LPWRRSTF_BIT            31
-#define RCC_CSR_WWDGRSTF_BIT            30
-#define RCC_CSR_IWDGRSTF_BIT            29
-#define RCC_CSR_SFTRSTF_BIT             28
-#define RCC_CSR_PORRSTF_BIT             27
-#define RCC_CSR_PINRSTF_BIT             26
-#define RCC_CSR_RMVF_BIT                24
-#define RCC_CSR_LSIRDY_BIT              1
-#define RCC_CSR_LSION_BIT               0
-
-#define RCC_CSR_LPWRRSTF                BIT(RCC_CSR_LPWRRSTF_BIT)
-#define RCC_CSR_WWDGRSTF                BIT(RCC_CSR_WWDGRSTF_BIT)
-#define RCC_CSR_IWDGRSTF                BIT(RCC_CSR_IWDGRSTF_BIT)
-#define RCC_CSR_SFTRSTF                 BIT(RCC_CSR_SFTRSTF_BIT)
-#define RCC_CSR_PORRSTF                 BIT(RCC_CSR_PORRSTF_BIT)
-#define RCC_CSR_PINRSTF                 BIT(RCC_CSR_PINRSTF_BIT)
-#define RCC_CSR_RMVF                    BIT(RCC_CSR_RMVF_BIT)
-#define RCC_CSR_LSIRDY                  BIT(RCC_CSR_LSIRDY_BIT)
-#define RCC_CSR_LSION                   BIT(RCC_CSR_LSION_BIT)
-
-/*
- * Convenience routines
- */
-
-/**
- * SYSCLK sources
- * @see rcc_clk_init()
- */
-typedef enum rcc_sysclk_src {
-    RCC_CLKSRC_HSI = 0x0,
-    RCC_CLKSRC_HSE = 0x1,
-    RCC_CLKSRC_PLL = 0x2,
-} rcc_sysclk_src;
-
-/**
- * PLL entry clock source
- * @see rcc_clk_init()
- */
-typedef enum rcc_pllsrc {
-    RCC_PLLSRC_HSE = (0x1 << 16),
-    RCC_PLLSRC_HSI_DIV_2 = (0x0 << 16)
-} rcc_pllsrc;
-
-/**
- * PLL multipliers
- * @see rcc_clk_init()
- */
-typedef enum rcc_pll_multiplier {
-    RCC_PLLMUL_2 = (0x0 << 18),
-    RCC_PLLMUL_3 = (0x1 << 18),
-    RCC_PLLMUL_4 = (0x2 << 18),
-    RCC_PLLMUL_5 = (0x3 << 18),
-    RCC_PLLMUL_6 = (0x4 << 18),
-    RCC_PLLMUL_7 = (0x5 << 18),
-    RCC_PLLMUL_8 = (0x6 << 18),
-    RCC_PLLMUL_9 = (0x7 << 18),
-    RCC_PLLMUL_10 = (0x8 << 18),
-    RCC_PLLMUL_11 = (0x9 << 18),
-    RCC_PLLMUL_12 = (0xA << 18),
-    RCC_PLLMUL_13 = (0xB << 18),
-    RCC_PLLMUL_14 = (0xC << 18),
-    RCC_PLLMUL_15 = (0xD << 18),
-    RCC_PLLMUL_16 = (0xE << 18),
-} rcc_pll_multiplier;
-
-/**
- * @brief Identifies bus and clock line for a peripheral.
- *
- * Also generally useful as a unique identifier for that peripheral
- * (or its corresponding device struct).
- */
-typedef enum rcc_clk_id {
-    RCC_GPIOA,
-    RCC_GPIOB,
-    RCC_GPIOC,
-    RCC_GPIOD,
-    RCC_AFIO,
-    RCC_ADC1,
-    RCC_ADC2,
-    RCC_ADC3,
-    RCC_USART1,
-    RCC_USART2,
-    RCC_USART3,
-    RCC_TIMER1,
-    RCC_TIMER2,
-    RCC_TIMER3,
-    RCC_TIMER4,
-    RCC_SPI1,
-    RCC_SPI2,
-    RCC_DMA1,
-    RCC_PWR,
-    RCC_BKP,
-    RCC_I2C1,
-    RCC_I2C2,
-    RCC_CRC,
-    RCC_FLITF,
-    RCC_SRAM,
-#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
-    RCC_GPIOE,
-    RCC_GPIOF,
-    RCC_GPIOG,
-    RCC_UART4,
-    RCC_UART5,
-    RCC_TIMER5,
-    RCC_TIMER6,
-    RCC_TIMER7,
-    RCC_TIMER8,
-    RCC_FSMC,
-    RCC_DAC,
-    RCC_DMA2,
-    RCC_SDIO,
-    RCC_SPI3,
-#endif
-#ifdef STM32_XL_DENSITY
-    RCC_TIMER9,
-    RCC_TIMER10,
-    RCC_TIMER11,
-    RCC_TIMER12,
-    RCC_TIMER13,
-    RCC_TIMER14,
-#endif
-} rcc_clk_id;
-
-void rcc_clk_init(rcc_sysclk_src sysclk_src,
-                  rcc_pllsrc pll_src,
-                  rcc_pll_multiplier pll_mul);
-void rcc_clk_enable(rcc_clk_id device);
-void rcc_reset_dev(rcc_clk_id device);
-
-typedef enum rcc_clk_domain {
-    RCC_APB1,
-    RCC_APB2,
-    RCC_AHB
-} rcc_clk_domain;
-
-rcc_clk_domain rcc_dev_clk(rcc_clk_id device);
-
-uint32 rcc_dev_clk_speed(rcc_clk_id id);
-uint32 rcc_dev_timer_clk_speed(rcc_clk_id id);
-
-/**
- * Prescaler identifiers
- * @see rcc_set_prescaler()
- */
-typedef enum rcc_prescaler {
-    RCC_PRESCALER_AHB,
-    RCC_PRESCALER_APB1,
-    RCC_PRESCALER_APB2,
-    RCC_PRESCALER_USB,
-    RCC_PRESCALER_ADC
-} rcc_prescaler;
-
-/**
- * ADC prescaler dividers
- * @see rcc_set_prescaler()
- */
-typedef enum rcc_adc_divider {
-    RCC_ADCPRE_PCLK_DIV_2 = 0x0 << 14,
-    RCC_ADCPRE_PCLK_DIV_4 = 0x1 << 14,
-    RCC_ADCPRE_PCLK_DIV_6 = 0x2 << 14,
-    RCC_ADCPRE_PCLK_DIV_8 = 0x3 << 14,
-} rcc_adc_divider;
-
-/**
- * APB1 prescaler dividers
- * @see rcc_set_prescaler()
- */
-typedef enum rcc_apb1_divider {
-    RCC_APB1_HCLK_DIV_1 = 0x0 << 8,
-    RCC_APB1_HCLK_DIV_2 = 0x4 << 8,
-    RCC_APB1_HCLK_DIV_4 = 0x5 << 8,
-    RCC_APB1_HCLK_DIV_8 = 0x6 << 8,
-    RCC_APB1_HCLK_DIV_16 = 0x7 << 8,
-} rcc_apb1_divider;
-
-/**
- * APB2 prescaler dividers
- * @see rcc_set_prescaler()
- */
-typedef enum rcc_apb2_divider {
-    RCC_APB2_HCLK_DIV_1 = 0x0 << 11,
-    RCC_APB2_HCLK_DIV_2 = 0x4 << 11,
-    RCC_APB2_HCLK_DIV_4 = 0x5 << 11,
-    RCC_APB2_HCLK_DIV_8 = 0x6 << 11,
-    RCC_APB2_HCLK_DIV_16 = 0x7 << 11,
-} rcc_apb2_divider;
-
-/**
- * AHB prescaler dividers
- * @see rcc_set_prescaler()
- */
-typedef enum rcc_ahb_divider {
-    RCC_AHB_SYSCLK_DIV_1 = 0x0 << 4,
-    RCC_AHB_SYSCLK_DIV_2 = 0x8 << 4,
-    RCC_AHB_SYSCLK_DIV_4 = 0x9 << 4,
-    RCC_AHB_SYSCLK_DIV_8 = 0xA << 4,
-    RCC_AHB_SYSCLK_DIV_16 = 0xB << 4,
-    RCC_AHB_SYSCLK_DIV_32 = 0xC << 4,
-    RCC_AHB_SYSCLK_DIV_64 = 0xD << 4,
-    RCC_AHB_SYSCLK_DIV_128 = 0xD << 4,
-    RCC_AHB_SYSCLK_DIV_256 = 0xE << 4,
-    RCC_AHB_SYSCLK_DIV_512 = 0xF << 4,
-} rcc_ahb_divider;
-
-void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider);
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
-#endif
diff --git a/STM32F4/cores/maple/libmaple/rccF2.c b/STM32F4/cores/maple/libmaple/rccF2.c
deleted file mode 100644
index 691393a8d..000000000
--- a/STM32F4/cores/maple/libmaple/rccF2.c
+++ /dev/null
@@ -1,707 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
- #ifdef STM32F2
- 
-/**
- * @file rcc.c
- * @brief Implements pretty much only the basic clock setup on the
- *        stm32, clock enable/disable and peripheral reset commands.
- */
-
-#include "libmaple.h"
-#include "flash.h"
-#include "gpio.h"
-#include "rcc.h"
-#include "bitband.h"
-
-#define APB1                            RCC_APB1
-#define APB2                            RCC_APB2
-#define AHB1                            RCC_AHB1
-#define AHB2                            RCC_AHB2
-#define AHB3                            RCC_AHB3
-
-struct rcc_dev_info {
-    const rcc_clk_domain clk_domain;
-    const uint8 line_num;
-};
-
-static uint32 rcc_dev_clk_speed_table[AHB3];
-
-/* Device descriptor table, maps rcc_clk_id onto bus and enable/reset
- * register bit numbers. */
-static const struct rcc_dev_info rcc_dev_table[] = {
-    [RCC_GPIOA]   = { .clk_domain = AHB1, .line_num =  0 }, //*
-    [RCC_GPIOB]   = { .clk_domain = AHB1, .line_num =  1 }, //*
-    [RCC_GPIOC]   = { .clk_domain = AHB1, .line_num =  2 }, //*
-    [RCC_GPIOD]   = { .clk_domain = AHB1, .line_num =  3 }, //*
-
-//    [RCC_AFIO]    = { .clk_domain = APB2, .line_num =  0 },
-    [RCC_ADC1]    = { .clk_domain = APB2, .line_num =  8 }, //*
-    [RCC_ADC2]    = { .clk_domain = APB2, .line_num =  9 }, //*
-    [RCC_ADC3]    = { .clk_domain = APB2, .line_num = 10 }, //*
-    [RCC_USART1]  = { .clk_domain = APB2, .line_num =  4 }, //*
-    [RCC_USART2]  = { .clk_domain = APB1, .line_num = 17 }, //unchanged
-    [RCC_USART3]  = { .clk_domain = APB1, .line_num = 18 }, //unchanged
-    [RCC_TIMER1]  = { .clk_domain = APB2, .line_num =  0 }, //*
-    [RCC_TIMER2]  = { .clk_domain = APB1, .line_num =  0 }, //unchanged
-    [RCC_TIMER3]  = { .clk_domain = APB1, .line_num =  1 }, //unchanged
-    [RCC_TIMER4]  = { .clk_domain = APB1, .line_num =  2 }, //unchanged
-    [RCC_SPI1]    = { .clk_domain = APB2, .line_num = 12 }, //unchanged
-    [RCC_SPI2]    = { .clk_domain = APB1, .line_num = 14 }, //unchanged
-    [RCC_DMA1]    = { .clk_domain = AHB1, .line_num = 21 }, //*
-    [RCC_PWR]     = { .clk_domain = APB1, .line_num = 28},  //unchanged
-    [RCC_BKP]     = { .clk_domain = AHB1, .line_num = 18},  //*
-    [RCC_I2C1]    = { .clk_domain = APB1, .line_num = 21 }, //unchanged
-    [RCC_I2C2]    = { .clk_domain = APB1, .line_num = 22 }, //unchanged
-    [RCC_CRC]     = { .clk_domain = AHB1, .line_num = 12},  //*
-//    [RCC_FLITF]   = { .clk_domain = AHB,  .line_num =  4},
-//    [RCC_SRAM]    = { .clk_domain = AHB,  .line_num =  2},
-
-    [RCC_GPIOE]   = { .clk_domain = AHB1, .line_num =  4 }, //*
-    [RCC_GPIOF]   = { .clk_domain = AHB1, .line_num =  5 }, //*
-    [RCC_GPIOG]   = { .clk_domain = AHB1, .line_num =  6 }, //*
-    [RCC_UART4]   = { .clk_domain = APB1, .line_num = 19 }, //unchanged
-    [RCC_UART5]   = { .clk_domain = APB1, .line_num = 20 }, //unchanged
-    [RCC_TIMER5]  = { .clk_domain = APB1, .line_num =  3 }, //unchanged
-    [RCC_TIMER6]  = { .clk_domain = APB1, .line_num =  4 }, //unchanged
-    [RCC_TIMER7]  = { .clk_domain = APB1, .line_num =  5 }, //unchanged
-    [RCC_TIMER8]  = { .clk_domain = APB2, .line_num =  1 }, //*
-    [RCC_FSMC]    = { .clk_domain = AHB3, .line_num =  0 }, //*
-    [RCC_DAC]     = { .clk_domain = APB1, .line_num = 29 }, //unchanged
-    [RCC_DMA2]    = { .clk_domain = AHB1, .line_num = 22 }, //*
-    [RCC_SDIO]    = { .clk_domain = APB2, .line_num = 11 }, //*
-    [RCC_SPI3]    = { .clk_domain = APB1, .line_num = 15 }, //unchanged
-    [RCC_TIMER9]  = { .clk_domain = APB2, .line_num = 16 }, //*
-    [RCC_TIMER10] = { .clk_domain = APB2, .line_num = 17 }, //*
-    [RCC_TIMER11] = { .clk_domain = APB2, .line_num = 18 }, //*
-    [RCC_TIMER12] = { .clk_domain = APB1, .line_num =  6 }, //unchanged
-    [RCC_TIMER13] = { .clk_domain = APB1, .line_num =  7 }, //unchanged
-    [RCC_TIMER14] = { .clk_domain = APB1, .line_num =  8 }, //unchanged
-    [RCC_USBFS]   = { .clk_domain = AHB2, .line_num =  7 }, //*
-    [RCC_SYSCFG]  = { .clk_domain = APB2, .line_num =  14 }, //*
-    [RCC_SPI4]    = { .clk_domain = APB1, .line_num = 15 },
-};
-
-/**
- * @brief Initialize the clock control system. Initializes the system
- *        clock source to use the PLL driven by an external oscillator
- * @param sysclk_src system clock source, must be PLL
- * @param pll_src pll clock source, must be HSE
- * @param pll_mul pll multiplier
- */
-
-#define HSE_STARTUP_TIMEOUT  ((uint16)0x0500)   /*!< Time out for HSE start up */
-#define  RCC_CFGR_HPRE_DIV1                  ((uint32)0x00000000)        /*!< SYSCLK not divided */
-#define  RCC_CFGR_PPRE1_DIV2                 ((uint32)0x00001000)        /*!< HCLK divided by 2 */
-#define  RCC_CFGR_PPRE1_DIV4                 ((uint32)0x00001400)        /*!< HCLK divided by 4 */
-#define  RCC_CFGR_PPRE2_DIV1                 ((uint32)0x00000000)        /*!< HCLK not divided */
-#define  RCC_CFGR_PPRE2_DIV2                 ((uint32)0x00008000)        /*!< HCLK divided by 2 */
-
-#define  RCC_PLLCFGR_PLLSRC_HSE              ((uint32)0x00400000)
-
-/*******************  Bits definition for FLASH_ACR register  *****************/
-//#define FLASH_ACR_LATENCY                    ((uint32_t)0x00000007)
-#define FLASH_ACR_LATENCY_0WS                ((uint32)0x00000000)
-#define FLASH_ACR_LATENCY_1WS                ((uint32)0x00000001)
-#define FLASH_ACR_LATENCY_2WS                ((uint32)0x00000002)
-#define FLASH_ACR_LATENCY_3WS                ((uint32)0x00000003)
-#define FLASH_ACR_LATENCY_4WS                ((uint32)0x00000004)
-#define FLASH_ACR_LATENCY_5WS                ((uint32)0x00000005)
-#define FLASH_ACR_LATENCY_6WS                ((uint32)0x00000006)
-#define FLASH_ACR_LATENCY_7WS                ((uint32)0x00000007)
-
-#define FLASH_ACR_PRFTEN                     ((uint32)0x00000100)
-#define FLASH_ACR_ICEN                       ((uint32)0x00000200)
-#define FLASH_ACR_DCEN                       ((uint32)0x00000400)
-#define FLASH_ACR_ICRST                      ((uint32)0x00000800)
-#define FLASH_ACR_DCRST                      ((uint32)0x00001000)
-#define FLASH_ACR_BYTE0_ADDRESS              ((uint32)0x40023C00)
-#define FLASH_ACR_BYTE2_ADDRESS              ((uint32)0x40023C03)
-
-typedef struct
-{
-  __io uint32 CR;   /*!< PWR power control register,        Address offset: 0x00 */
-  __io uint32 CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
-} PWR_TypeDef;
-
-#define PWR_BASE                             (0x40007000)
-#define PWR                                  ((PWR_TypeDef *) PWR_BASE)
-#define PWR_CR_VOS                           ((uint16)0x4000)     /*!< Regulator voltage scaling output selection */
-
-typedef struct
-{
-  __io uint32 ACR;      /*!< FLASH access control register, Address offset: 0x00 */
-  __io uint32 KEYR;     /*!< FLASH key register,            Address offset: 0x04 */
-  __io uint32 OPTKEYR;  /*!< FLASH option key register,     Address offset: 0x08 */
-  __io uint32 SR;       /*!< FLASH status register,         Address offset: 0x0C */
-  __io uint32 CR;       /*!< FLASH control register,        Address offset: 0x10 */
-  __io uint32 OPTCR;    /*!< FLASH option control register, Address offset: 0x14 */
-} FLASH_TypeDef;
-
-#define FLASH_R_BASE          (0x40023C00)
-#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
-#define RESET 0
-
-typedef uint32 uint32_t;
-
-void InitMCO1()
-{
-    rcc_reg_map *RCC = RCC_BASE;
-    // Turn MCO1 Master Clock Output mode
-    RCC->CFGR &= RCC_CFGR_MCO1_RESET_MASK;
-    RCC->CFGR |= RCC_CFGR_MCO1Source_HSE | RCC_CFGR_MCO1Div_1;
-    // PA8 Output the Master Clock MCO1
-    gpio_set_af_mode(GPIOA, 8, 0);
-    gpio_set_mode(GPIOA, 8, GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
-}
-
-
-void SetupClock72MHz()
-{
-	uint32_t SystemCoreClock = 72000000;
-
-	/******************************************************************************/
-	/*            PLL (clocked by HSE) used as System clock source                */
-	/******************************************************************************/
-	/************************* PLL Parameters *************************************/
-	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
-	int PLL_M = 4;
-	int PLL_N = 216;
-
-	/* SYSCLK = PLL_VCO / PLL_P */
-	int PLL_P = 6;
-
-	/* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
-	int PLL_Q = 9;
-
-
-	uint32 StartUpCounter = 0, HSEStatus = 0;
-	rcc_reg_map *RCC = RCC_BASE;
-
-	/* Enable HSE */
-	RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
-	/* Wait till HSE is ready and if Time out is reached exit */
-	do
-	{
-		HSEStatus = RCC->CR & RCC_CR_HSERDY;
-		StartUpCounter++;
-	} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-	if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-	{
-		HSEStatus = (uint32_t)0x01;
-	}
-	else
-	{
-		HSEStatus = (uint32_t)0x00;
-	}
-
-	if (HSEStatus == (uint32_t)0x01)
-	{
-		/* Select regulator voltage output Scale 2 mode, System frequency up to 144 MHz */
-		RCC->APB1ENR |= RCC_APB1ENR_PWREN;
-		PWR->CR &= (uint32_t)~(PWR_CR_VOS);
-
-		/* HCLK = SYSCLK / 1*/
-		RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
-
-		/* PCLK2 = HCLK / 1*/
-		RCC->CFGR |= RCC_CFGR_PPRE2_DIV1;
-
-		/* PCLK1 = HCLK / 2*/
-		RCC->CFGR |= RCC_CFGR_PPRE1_DIV2;
-
-		// save bus clock values
-		rcc_dev_clk_speed_table[RCC_AHB1] = (SystemCoreClock/1);
-		rcc_dev_clk_speed_table[RCC_APB2] = (SystemCoreClock/1);
-		rcc_dev_clk_speed_table[RCC_APB1] = (SystemCoreClock/2);
-
-		/* Configure the main PLL */
-		RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
-			(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
-
-		/* Enable the main PLL */
-		RCC->CR |= RCC_CR_PLLON;
-
-		/* Wait till the main PLL is ready */
-		while((RCC->CR & RCC_CR_PLLRDY) == 0)
-		{
-		}
-
-		/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
-		FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_2WS;
-
-		/* Select the main PLL as system clock source */
-		RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-		RCC->CFGR |= RCC_CFGR_SW_PLL;
-
-		/* Wait till the main PLL is used as system clock source */
-		while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
-		{
-		}
-	}
-	else
-	{ /* If HSE fails to start-up, the application will have wrong clock
-	  configuration. User can add here some code to deal with this error */
-	}
-}
-
-
-void SetupClock120MHz()
-{
-	uint32_t SystemCoreClock = 120000000;
-
-	/******************************************************************************/
-	/*            PLL (clocked by HSE) used as System clock source                */
-	/******************************************************************************/
-	/************************* PLL Parameters *************************************/
-	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
-	int PLL_M = 8;
-	int PLL_N = 240;
-
-	/* SYSCLK = PLL_VCO / PLL_P */
-	int PLL_P = 2;
-
-	/* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
-	int PLL_Q = 5;
-
-
-	uint32 StartUpCounter = 0, HSEStatus = 0;
-	rcc_reg_map *RCC = RCC_BASE;
-
-	/* Enable HSE */
-	RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
-	/* Wait till HSE is ready and if Time out is reached exit */
-	do
-	{
-		HSEStatus = RCC->CR & RCC_CR_HSERDY;
-		StartUpCounter++;
-	} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-	if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-	{
-		HSEStatus = (uint32_t)0x01;
-	}
-	else
-	{
-		HSEStatus = (uint32_t)0x00;
-	}
-
-	if (HSEStatus == (uint32_t)0x01)
-	{
-		/* Select regulator voltage output Scale 2 mode, System frequency up to 144 MHz */
-		RCC->APB1ENR |= RCC_APB1ENR_PWREN;
-		PWR->CR &= (uint32_t)~(PWR_CR_VOS);
-
-		/* HCLK = SYSCLK / 1*/
-		RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
-
-		/* PCLK2 = HCLK / 2*/
-		RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
-
-		/* PCLK1 = HCLK / 4*/
-		RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
-
-		// save bus clock values
-		rcc_dev_clk_speed_table[RCC_AHB1] = (SystemCoreClock/1);
-		rcc_dev_clk_speed_table[RCC_APB2] = (SystemCoreClock/2);
-		rcc_dev_clk_speed_table[RCC_APB1] = (SystemCoreClock/4);
-
-		/* Configure the main PLL */
-		RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
-			(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
-
-		/* Enable the main PLL */
-		RCC->CR |= RCC_CR_PLLON;
-
-		/* Wait till the main PLL is ready */
-		while((RCC->CR & RCC_CR_PLLRDY) == 0)
-		{
-		}
-
-		/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
-		FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_3WS;
-
-		/* Select the main PLL as system clock source */
-		RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-		RCC->CFGR |= RCC_CFGR_SW_PLL;
-
-		/* Wait till the main PLL is used as system clock source */
-		while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
-		{
-		}
-	}
-	else
-	{ /* If HSE fails to start-up, the application will have wrong clock
-	  configuration. User can add here some code to deal with this error */
-	}
-}
-
-
-void SetupClock168MHz()
-{
-	uint32_t SystemCoreClock = 168000000;
-
-	/******************************************************************************/
-	/*            PLL (clocked by HSE) used as System clock source                */
-	/******************************************************************************/
-	/************************* PLL Parameters *************************************/
-	/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
-#ifdef ARDUINO_STM32F4_NETDUINO2PLUS
-	int PLL_M = 25; // The NETDUINO has a 25MHz external oscillator
-#else
-	int PLL_M = 8;
-#endif
-	int PLL_N = 336;
-
-	/* SYSCLK = PLL_VCO / PLL_P */
-	int PLL_P = 2;
-
-	/* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
-	int PLL_Q = 7;
-
-
-	uint32 StartUpCounter = 0, HSEStatus = 0;
-	rcc_reg_map *RCC = RCC_BASE;
-
-#ifdef ARDUINO_STM32F4_NETDUINO2PLUS
-        InitMCO1();
-#endif
-        
-	/* Enable HSE */
-	RCC->CR |= ((uint32_t)RCC_CR_HSEON);
-
-	/* Wait till HSE is ready and if Time out is reached exit */
-	do
-	{
-		HSEStatus = RCC->CR & RCC_CR_HSERDY;
-		StartUpCounter++;
-	} while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-	if ((RCC->CR & RCC_CR_HSERDY) != RESET)
-	{
-		HSEStatus = (uint32_t)0x01;
-	}
-	else
-	{
-		HSEStatus = (uint32_t)0x00;
-	}
-
-	if (HSEStatus == (uint32_t)0x01)
-	{
-		/* Select regulator voltage output Scale 1 mode, System frequency up to 168 MHz */
-		RCC->APB1ENR |= RCC_APB1ENR_PWREN;
-		PWR->CR |= PWR_CR_VOS;
-
-		/* HCLK = SYSCLK / 1*/
-		RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
-
-		/* PCLK2 = HCLK / 2*/
-		RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
-
-		/* PCLK1 = HCLK / 4*/
-		RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
-
-		// save bus clock values
-		rcc_dev_clk_speed_table[RCC_AHB1] = (SystemCoreClock/1);
-		rcc_dev_clk_speed_table[RCC_APB2] = (SystemCoreClock/2);
-		rcc_dev_clk_speed_table[RCC_APB1] = (SystemCoreClock/4);
-
-		/* Configure the main PLL */
-		RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
-			(RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
-
-		/* Enable the main PLL */
-		RCC->CR |= RCC_CR_PLLON;
-
-		/* Wait till the main PLL is ready */
-		while((RCC->CR & RCC_CR_PLLRDY) == 0)
-		{
-		}
-
-		/* Configure Flash prefetch, Instruction cache, Data cache and wait state */
-		FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
-
-		/* Select the main PLL as system clock source */
-		RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
-		RCC->CFGR |= RCC_CFGR_SW_PLL;
-
-		/* Wait till the main PLL is used as system clock source */
-		while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
-		{
-		}
-	}
-	else
-	{ /* If HSE fails to start-up, the application will have wrong clock
-	  configuration. User can add here some code to deal with this error */
-	}
-}
-
-
-void rcc_clk_init(rcc_sysclk_src sysclk_src,
-                  rcc_pllsrc pll_src,
-                  rcc_pll_multiplier pll_mul) {
-
-  //SetupClock72MHz();
-#if STM32_TICKS_PER_US == 168
-	  SetupClock168MHz();
-#endif
-#if STM32_TICKS_PER_US == 120
-	  SetupClock120MHz();
-#endif
-#if STM32_TICKS_PER_US == 72
-	  SetupClock72MHz();
-#endif
-}
-
-
-
-
-#define PLL_M      8
-#define PLL_N      240
-/* SYSCLK = PLL_VCO / PLL_P */
-#define PLL_P      2
-
-/* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
-#define PLL_Q      5
-
-
-void rcc_clk_init2(rcc_sysclk_src sysclk_src,
-                  rcc_pllsrc pll_src,
-                  rcc_pll_multiplier pll_mul) {
-
-/******************************************************************************/
-/*            PLL (clocked by HSE) used as System clock source                */
-/******************************************************************************/
-  uint32 StartUpCounter = 0, HSEStatus = 0;
-  rcc_reg_map *pRCC = RCC_BASE;
-
-  /* Enable HSE */
-  pRCC->CR |= RCC_CR_HSEON;
-
-  /* Wait till HSE is ready and if Time out is reached exit */
-  do
-  {
-    HSEStatus = pRCC->CR & RCC_CR_HSERDY;
-    StartUpCounter++;
-  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
-
-  if ((pRCC->CR & RCC_CR_HSERDY) != 0)
-  {
-    HSEStatus = 0x01;
-  }
-  else
-  {
-    HSEStatus = 0x00;
-  }
-
-  if (HSEStatus == 0x01)
-  {
-    /* HCLK = SYSCLK / 1*/
-    pRCC->CFGR |= RCC_CFGR_HPRE_DIV1;
-
-    /* PCLK2 = HCLK / 2*/
-    pRCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
-
-    /* PCLK1 = HCLK / 4*/
-    pRCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
-
-    /* Configure the main PLL */
-    pRCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
-                   (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
-
-    /* Enable the main PLL */
-    pRCC->CR |= RCC_CR_PLLON;
-
-    /* Wait till the main PLL is ready */
-    while((pRCC->CR & RCC_CR_PLLRDY) == 0)
-    {
-    }
-
-    /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
-    ((FLASH_TypeDef*)FLASH)->ACR = FLASH_ACR_PRFTEN |FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_3WS;
-
-    /* Select the main PLL as system clock source */
-    pRCC->CFGR &= ~RCC_CFGR_SW;
-    pRCC->CFGR |= RCC_CFGR_SW_PLL;
-
-    /* Wait till the main PLL is used as system clock source */
-    while ((pRCC->CFGR & RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
-    {
-    }
-  }
-  else
-  { /* If HSE fails to start-up, the application will have wrong clock
-         configuration. User can add here some code to deal with this error */
-  }
-
-#if 0
-    uint32 cfgr = 0;
-    uint32 cr;
-
-    /* Assume that we're going to clock the chip off the PLL, fed by
-     * the HSE */
-    ASSERT(sysclk_src == RCC_CLKSRC_PLL &&
-           pll_src    == RCC_PLLSRC_HSE);
-
-    RCC_BASE->CFGR = pll_src | pll_mul;
-
-    /* Turn on the HSE */
-    cr = RCC_BASE->CR;
-    cr |= RCC_CR_HSEON;
-    RCC_BASE->CR = cr;
-    while (!(RCC_BASE->CR & RCC_CR_HSERDY))
-        ;
-
-    /* Now the PLL */
-    cr |= RCC_CR_PLLON;
-    RCC_BASE->CR = cr;
-    while (!(RCC_BASE->CR & RCC_CR_PLLRDY))
-        ;
-
-    /* Finally, let's switch over to the PLL */
-    cfgr &= ~RCC_CFGR_SW;
-    cfgr |= RCC_CFGR_SW_PLL;
-    RCC_BASE->CFGR = cfgr;
-    while ((RCC_BASE->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL)
-        ;
-#endif
-}
-
-/**
- * @brief Turn on the clock line on a peripheral
- * @param id Clock ID of the peripheral to turn on.
- */
-void rcc_clk_enable(rcc_clk_id id) {
-    static const __io uint32* enable_regs[] = {
-        [APB1] = &RCC_BASE->APB1ENR,
-        [APB2] = &RCC_BASE->APB2ENR,
-        [AHB1] = &RCC_BASE->AHB1ENR,
-        [AHB2] = &RCC_BASE->AHB2ENR,
-        [AHB3] = &RCC_BASE->AHB3ENR,
-    };
-
-    rcc_clk_domain clk_domain = rcc_dev_clk(id);
-    __io uint32* enr = (__io uint32*)enable_regs[clk_domain];
-    uint8 lnum = rcc_dev_table[id].line_num;
-
-    bb_peri_set_bit(enr, lnum, 1);
-}
-
-/**
- * @brief Turn on the clock line on a peripheral
- * @param id Clock ID of the peripheral to turn on.
- */
-void rcc_clk_disable(rcc_clk_id id) {
-    static const __io uint32* enable_regs[] = {
-        [APB1] = &RCC_BASE->APB1ENR,
-        [APB2] = &RCC_BASE->APB2ENR,
-        [AHB1] = &RCC_BASE->AHB1ENR,
-        [AHB2] = &RCC_BASE->AHB2ENR,
-        [AHB3] = &RCC_BASE->AHB3ENR,
-    };
-
-    rcc_clk_domain clk_domain = rcc_dev_clk(id);
-    __io uint32* enr = (__io uint32*)enable_regs[clk_domain];
-    uint8 lnum = rcc_dev_table[id].line_num;
-
-    bb_peri_set_bit(enr, lnum, 0);
-}
-
-/**
- * @brief Reset a peripheral.
- * @param id Clock ID of the peripheral to reset.
- */
-void rcc_reset_dev(rcc_clk_id id) {
-    static const __io uint32* reset_regs[] = {
-        [APB1] = &RCC_BASE->APB1RSTR,
-        [APB2] = &RCC_BASE->APB2RSTR,
-        [AHB1] = &RCC_BASE->AHB1RSTR,
-        [AHB2] = &RCC_BASE->AHB2RSTR,
-        [AHB3] = &RCC_BASE->AHB3RSTR,
-    };
-
-    rcc_clk_domain clk_domain = rcc_dev_clk(id);
-    __io void* addr = (__io void*)reset_regs[clk_domain];
-    uint8 lnum = rcc_dev_table[id].line_num;
-
-    bb_peri_set_bit(addr, lnum, 1);
-    bb_peri_set_bit(addr, lnum, 0);
-}
-
-/**
- * @brief Get a peripheral's clock domain
- * @param id Clock ID of the peripheral whose clock domain to return
- * @return Clock source for the given clock ID
- */
-rcc_clk_domain rcc_dev_clk(rcc_clk_id id) {
-    return rcc_dev_table[id].clk_domain;
-}
-
-/**
- * @brief Get a peripheral's clock domain speed
- * @param id Clock ID of the peripheral whose clock domain speed to return
- * @return Clock speed for the given clock ID
- */
-uint32 rcc_dev_clk_speed(rcc_clk_id id) {
-    return rcc_dev_clk_speed_table[rcc_dev_clk(id)];
-}
-
-/**
- * @brief Get a peripheral's timer clock domain speed
- * @param id Clock ID of the peripheral whose clock domain speed to return
- * @return Clock speed for the given clock ID
- */
-uint32 rcc_dev_timer_clk_speed(rcc_clk_id id) {
-    return 2*rcc_dev_clk_speed(id);
-}
-
-/**
- * @brief Set the divider on a peripheral prescaler
- * @param prescaler prescaler to set
- * @param divider prescaler divider
- */
-void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider) {
-#if 0
-    static const uint32 masks[] = {
-        [RCC_PRESCALER_AHB] = RCC_CFGR_HPRE,
-        [RCC_PRESCALER_APB1] = RCC_CFGR_PPRE1,
-        [RCC_PRESCALER_APB2] = RCC_CFGR_PPRE2,
-        [RCC_PRESCALER_USB] = RCC_CFGR_USBPRE,
-        [RCC_PRESCALER_ADC] = RCC_CFGR_ADCPRE,
-    };
-
-    uint32 cfgr = RCC_BASE->CFGR;
-    cfgr &= ~masks[prescaler];
-    cfgr |= divider;
-    RCC_BASE->CFGR = cfgr;
-#endif
-}
-
-#endif
diff --git a/STM32F4/cores/maple/libmaple/rccF2.h b/STM32F4/cores/maple/libmaple/rccF2.h
deleted file mode 100644
index 99c5ff25d..000000000
--- a/STM32F4/cores/maple/libmaple/rccF2.h
+++ /dev/null
@@ -1,642 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file rcc.h
- * @brief reset and clock control definitions and prototypes
- */
-
-#include "libmaple_types.h"
-#include "bitband.h"
-
-#ifndef _RCC_H_
-#define _RCC_H_
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-/** RCC register map type */
-typedef struct
-{
-  __io uint32 CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
-  __io uint32 PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
-  __io uint32 CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
-  __io uint32 CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
-  __io uint32 AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
-  __io uint32 AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
-  __io uint32 AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
-  uint32      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
-  __io uint32 APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
-  __io uint32 APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
-  uint32      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
-  __io uint32 AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
-  __io uint32 AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
-  __io uint32 AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
-  uint32      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
-  __io uint32 APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
-  __io uint32 APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
-  uint32      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
-  __io uint32 AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
-  __io uint32 AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
-  __io uint32 AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
-  uint32      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
-  __io uint32 APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
-  __io uint32 APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
-  uint32      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
-  __io uint32 BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
-  __io uint32 CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
-  uint32      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
-  __io uint32 SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
-  __io uint32 PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
-} rcc_reg_map;
-
-/** RCC register map base pointer */
-//#define RCC_BASE                        ((struct rcc_reg_map*)0x40021000)
-#define RCC_BASE              ((rcc_reg_map*)0x40023800)
-
-/*
- * Register bit definitions
- */
-
-/* Clock control register */
-
-#define RCC_CR_PLLRDY_BIT               25
-#define RCC_CR_PLLON_BIT                24
-#define RCC_CR_CSSON_BIT                19
-#define RCC_CR_HSEBYP_BIT               18
-#define RCC_CR_HSERDY_BIT               17
-#define RCC_CR_HSEON_BIT                16
-#define RCC_CR_HSIRDY_BIT               1
-#define RCC_CR_HSION_BIT                0
-
-#define RCC_CR_PLLRDY                   BIT(RCC_CR_PLLRDY_BIT)
-#define RCC_CR_PLLON                    BIT(RCC_CR_PLLON_BIT)
-#define RCC_CR_CSSON                    BIT(RCC_CR_CSSON_BIT)
-#define RCC_CR_HSEBYP                   BIT(RCC_CR_HSEBYP_BIT)
-#define RCC_CR_HSERDY                   BIT(RCC_CR_HSERDY_BIT)
-#define RCC_CR_HSEON                    BIT(RCC_CR_HSEON_BIT)
-#define RCC_CR_HSICAL                   (0xFF << 8)
-#define RCC_CR_HSITRIM                  (0x1F << 3)
-#define RCC_CR_HSIRDY                   BIT(RCC_CR_HSIRDY_BIT)
-#define RCC_CR_HSION                    BIT(RCC_CR_HSION_BIT)
-
-/* Clock configuration register */
-
-#define RCC_CFGR_USBPRE_BIT             22
-#define RCC_CFGR_PLLXTPRE_BIT           17
-#define RCC_CFGR_PLLSRC_BIT             16
-
-#define RCC_CFGR_MCO                    (0x3 << 24)
-#define RCC_CFGR_USBPRE                 BIT(RCC_CFGR_USBPRE_BIT)
-#define RCC_CFGR_PLLMUL                 (0xF << 18)
-#define RCC_CFGR_PLLXTPRE               BIT(RCC_CFGR_PLLXTPRE_BIT)
-#define RCC_CFGR_PLLSRC                 BIT(RCC_CFGR_PLLSRC_BIT)
-#define RCC_CFGR_ADCPRE                 (0x3 << 14)
-#define RCC_CFGR_PPRE2                  (0x7 << 11)
-#define RCC_CFGR_PPRE1                  (0x7 << 8)
-#define RCC_CFGR_HPRE                   (0xF << 4)
-#define RCC_CFGR_SWS                    (0x3 << 2)
-#define RCC_CFGR_SWS_PLL                (0x2 << 2)
-#define RCC_CFGR_SWS_HSE                (0x1 << 2)
-#define RCC_CFGR_SW                     0x3
-#define RCC_CFGR_SW_PLL                 0x2
-#define RCC_CFGR_SW_HSE                 0x1
-
-#define  RCC_CFGR_MCO1Source_HSI             ((uint32_t)0x00000000)
-#define  RCC_CFGR_MCO1Source_LSE             ((uint32_t)0x00200000)
-#define  RCC_CFGR_MCO1Source_HSE             ((uint32_t)0x00400000)
-#define  RCC_CFGR_MCO1Source_PLLCLK          ((uint32_t)0x00600000)
-#define  RCC_CFGR_MCO1Div_1                  ((uint32_t)0x00000000)
-#define  RCC_CFGR_MCO1Div_2                  ((uint32_t)0x04000000)
-#define  RCC_CFGR_MCO1Div_3                  ((uint32_t)0x05000000)
-#define  RCC_CFGR_MCO1Div_4                  ((uint32_t)0x06000000)
-#define  RCC_CFGR_MCO1Div_5                  ((uint32_t)0x07000000)
-#define  RCC_CFGR_MCO1_RESET_MASK            ((uint32_t)0xF89FFFFF)
-
-/* Clock interrupt register */
-
-#define RCC_CIR_CSSC_BIT                23
-#define RCC_CIR_PLLRDYC_BIT             20
-#define RCC_CIR_HSERDYC_BIT             19
-#define RCC_CIR_HSIRDYC_BIT             18
-#define RCC_CIR_LSERDYC_BIT             17
-#define RCC_CIR_LSIRDYC_BIT             16
-#define RCC_CIR_PLLRDYIE_BIT            12
-#define RCC_CIR_HSERDYIE_BIT            11
-#define RCC_CIR_HSIRDYIE_BIT            10
-#define RCC_CIR_LSERDYIE_BIT            9
-#define RCC_CIR_LSIRDYIE_BIT            8
-#define RCC_CIR_CSSF_BIT                7
-#define RCC_CIR_PLLRDYF_BIT             4
-#define RCC_CIR_HSERDYF_BIT             3
-#define RCC_CIR_HSIRDYF_BIT             2
-#define RCC_CIR_LSERDYF_BIT             1
-#define RCC_CIR_LSIRDYF_BIT             0
-
-#define RCC_CIR_CSSC                    BIT(RCC_CIR_CSSC_BIT)
-#define RCC_CIR_PLLRDYC                 BIT(RCC_CIR_PLLRDYC_BIT)
-#define RCC_CIR_HSERDYC                 BIT(RCC_CIR_HSERDYC_BIT)
-#define RCC_CIR_HSIRDYC                 BIT(RCC_CIR_HSIRDYC_BIT)
-#define RCC_CIR_LSERDYC                 BIT(RCC_CIR_LSERDYC_BIT)
-#define RCC_CIR_LSIRDYC                 BIT(RCC_CIR_LSIRDYC_BIT)
-#define RCC_CIR_PLLRDYIE                BIT(RCC_CIR_PLLRDYIE_BIT)
-#define RCC_CIR_HSERDYIE                BIT(RCC_CIR_HSERDYIE_BIT)
-#define RCC_CIR_HSIRDYIE                BIT(RCC_CIR_HSIRDYIE_BIT)
-#define RCC_CIR_LSERDYIE                BIT(RCC_CIR_LSERDYIE_BIT)
-#define RCC_CIR_LSIRDYIE                BIT(RCC_CIR_LSIRDYIE_BIT)
-#define RCC_CIR_CSSF                    BIT(RCC_CIR_CSSF_BIT)
-#define RCC_CIR_PLLRDYF                 BIT(RCC_CIR_PLLRDYF_BIT)
-#define RCC_CIR_HSERDYF                 BIT(RCC_CIR_HSERDYF_BIT)
-#define RCC_CIR_HSIRDYF                 BIT(RCC_CIR_HSIRDYF_BIT)
-#define RCC_CIR_LSERDYF                 BIT(RCC_CIR_LSERDYF_BIT)
-#define RCC_CIR_LSIRDYF                 BIT(RCC_CIR_LSIRDYF_BIT)
-
-/* APB2 peripheral reset register */
-
-#define RCC_APB2RSTR_TIM11RST_BIT       21
-#define RCC_APB2RSTR_TIM10RST_BIT       20
-#define RCC_APB2RSTR_TIM9RST_BIT        19
-#define RCC_APB2RSTR_ADC3RST_BIT        15
-#define RCC_APB2RSTR_USART1RST_BIT      14
-#define RCC_APB2RSTR_TIM8RST_BIT        13
-#define RCC_APB2RSTR_SPI1RST_BIT        12
-#define RCC_APB2RSTR_TIM1RST_BIT        11
-#define RCC_APB2RSTR_ADC2RST_BIT        10
-#define RCC_APB2RSTR_ADC1RST_BIT        9
-#define RCC_APB2RSTR_IOPGRST_BIT        8
-#define RCC_APB2RSTR_IOPFRST_BIT        7
-#define RCC_APB2RSTR_IOPERST_BIT        6
-#define RCC_APB2RSTR_IOPDRST_BIT        5
-#define RCC_APB2RSTR_IOPCRST_BIT        4
-#define RCC_APB2RSTR_IOPBRST_BIT        3
-#define RCC_APB2RSTR_IOPARST_BIT        2
-#define RCC_APB2RSTR_AFIORST_BIT        0
-
-#define RCC_APB2RSTR_TIM11RST           BIT(RCC_APB2RSTR_TIM11RST_BIT)
-#define RCC_APB2RSTR_TIM10RST           BIT(RCC_APB2RSTR_TIM10RST_BIT)
-#define RCC_APB2RSTR_TIM9RST            BIT(RCC_APB2RSTR_TIM9RST_BIT)
-#define RCC_APB2RSTR_ADC3RST            BIT(RCC_APB2RSTR_ADC3RST_BIT)
-#define RCC_APB2RSTR_USART1RST          BIT(RCC_APB2RSTR_USART1RST_BIT)
-#define RCC_APB2RSTR_TIM8RST            BIT(RCC_APB2RSTR_TIM8RST_BIT)
-#define RCC_APB2RSTR_SPI1RST            BIT(RCC_APB2RSTR_SPI1RST_BIT)
-#define RCC_APB2RSTR_TIM1RST            BIT(RCC_APB2RSTR_TIM1RST_BIT)
-#define RCC_APB2RSTR_ADC2RST            BIT(RCC_APB2RSTR_ADC2RST_BIT)
-#define RCC_APB2RSTR_ADC1RST            BIT(RCC_APB2RSTR_ADC1RST_BIT)
-#define RCC_APB2RSTR_IOPGRST            BIT(RCC_APB2RSTR_IOPGRST_BIT)
-#define RCC_APB2RSTR_IOPFRST            BIT(RCC_APB2RSTR_IOPFRST_BIT)
-#define RCC_APB2RSTR_IOPERST            BIT(RCC_APB2RSTR_IOPERST_BIT)
-#define RCC_APB2RSTR_IOPDRST            BIT(RCC_APB2RSTR_IOPDRST_BIT)
-#define RCC_APB2RSTR_IOPCRST            BIT(RCC_APB2RSTR_IOPCRST_BIT)
-#define RCC_APB2RSTR_IOPBRST            BIT(RCC_APB2RSTR_IOPBRST_BIT)
-#define RCC_APB2RSTR_IOPARST            BIT(RCC_APB2RSTR_IOPARST_BIT)
-#define RCC_APB2RSTR_AFIORST            BIT(RCC_APB2RSTR_AFIORST_BIT)
-
-/* APB1 peripheral reset register */
-
-#define RCC_APB1RSTR_DACRST_BIT         29
-#define RCC_APB1RSTR_PWRRST_BIT         28
-#define RCC_APB1RSTR_BKPRST_BIT         27
-#define RCC_APB1RSTR_CANRST_BIT         25
-#define RCC_APB1RSTR_USBRST_BIT         23
-#define RCC_APB1RSTR_I2C2RST_BIT        22
-#define RCC_APB1RSTR_I2C1RST_BIT        21
-#define RCC_APB1RSTR_UART5RST_BIT       20
-#define RCC_APB1RSTR_UART4RST_BIT       19
-#define RCC_APB1RSTR_USART3RST_BIT      18
-#define RCC_APB1RSTR_USART2RST_BIT      17
-#define RCC_APB1RSTR_SPI3RST_BIT        15
-#define RCC_APB1RSTR_SPI2RST_BIT        14
-#define RCC_APB1RSTR_WWDRST_BIT         11
-#define RCC_APB1RSTR_TIM14RST_BIT       8
-#define RCC_APB1RSTR_TIM13RST_BIT       7
-#define RCC_APB1RSTR_TIM12RST_BIT       6
-#define RCC_APB1RSTR_TIM7RST_BIT        5
-#define RCC_APB1RSTR_TIM6RST_BIT        4
-#define RCC_APB1RSTR_TIM5RST_BIT        3
-#define RCC_APB1RSTR_TIM4RST_BIT        2
-#define RCC_APB1RSTR_TIM3RST_BIT        1
-#define RCC_APB1RSTR_TIM2RST_BIT        0
-
-#define RCC_APB1RSTR_DACRST             BIT(RCC_APB1RSTR_DACRST_BIT)
-#define RCC_APB1RSTR_PWRRST             BIT(RCC_APB1RSTR_PWRRST_BIT)
-#define RCC_APB1RSTR_BKPRST             BIT(RCC_APB1RSTR_BKPRST_BIT)
-#define RCC_APB1RSTR_CANRST             BIT(RCC_APB1RSTR_CANRST_BIT)
-#define RCC_APB1RSTR_USBRST             BIT(RCC_APB1RSTR_USBRST_BIT)
-#define RCC_APB1RSTR_I2C2RST            BIT(RCC_APB1RSTR_I2C2RST_BIT)
-#define RCC_APB1RSTR_I2C1RST            BIT(RCC_APB1RSTR_I2C1RST_BIT)
-#define RCC_APB1RSTR_UART5RST           BIT(RCC_APB1RSTR_UART5RST_BIT)
-#define RCC_APB1RSTR_UART4RST           BIT(RCC_APB1RSTR_UART4RST_BIT)
-#define RCC_APB1RSTR_USART3RST          BIT(RCC_APB1RSTR_USART3RST_BIT)
-#define RCC_APB1RSTR_USART2RST          BIT(RCC_APB1RSTR_USART2RST_BIT)
-#define RCC_APB1RSTR_SPI3RST            BIT(RCC_APB1RSTR_SPI3RST_BIT)
-#define RCC_APB1RSTR_SPI2RST            BIT(RCC_APB1RSTR_SPI2RST_BIT)
-#define RCC_APB1RSTR_WWDRST             BIT(RCC_APB1RSTR_WWDRST_BIT)
-#define RCC_APB1RSTR_TIM14RST           BIT(RCC_APB1RSTR_TIM14RST_BIT)
-#define RCC_APB1RSTR_TIM13RST           BIT(RCC_APB1RSTR_TIM13RST_BIT)
-#define RCC_APB1RSTR_TIM12RST           BIT(RCC_APB1RSTR_TIM12RST_BIT)
-#define RCC_APB1RSTR_TIM7RST            BIT(RCC_APB1RSTR_TIM7RST_BIT)
-#define RCC_APB1RSTR_TIM6RST            BIT(RCC_APB1RSTR_TIM6RST_BIT)
-#define RCC_APB1RSTR_TIM5RST            BIT(RCC_APB1RSTR_TIM5RST_BIT)
-#define RCC_APB1RSTR_TIM4RST            BIT(RCC_APB1RSTR_TIM4RST_BIT)
-#define RCC_APB1RSTR_TIM3RST            BIT(RCC_APB1RSTR_TIM3RST_BIT)
-#define RCC_APB1RSTR_TIM2RST            BIT(RCC_APB1RSTR_TIM2RST_BIT)
-
-/* AHB peripheral clock enable register */
-
-#define RCC_AHBENR_SDIOEN_BIT           10
-#define RCC_AHBENR_FSMCEN_BIT           8
-#define RCC_AHBENR_CRCEN_BIT            7
-#define RCC_AHBENR_FLITFEN_BIT          4
-#define RCC_AHBENR_SRAMEN_BIT           2
-#define RCC_AHBENR_DMA2EN_BIT           1
-#define RCC_AHBENR_DMA1EN_BIT           0
-
-#define RCC_AHBENR_SDIOEN               BIT(RCC_AHBENR_SDIOEN_BIT)
-#define RCC_AHBENR_FSMCEN               BIT(RCC_AHBENR_FSMCEN_BIT)
-#define RCC_AHBENR_CRCEN                BIT(RCC_AHBENR_CRCEN_BIT)
-#define RCC_AHBENR_FLITFEN              BIT(RCC_AHBENR_FLITFEN_BIT)
-#define RCC_AHBENR_SRAMEN               BIT(RCC_AHBENR_SRAMEN_BIT)
-#define RCC_AHBENR_DMA2EN               BIT(RCC_AHBENR_DMA2EN_BIT)
-#define RCC_AHBENR_DMA1EN               BIT(RCC_AHBENR_DMA1EN_BIT)
-
-/* APB2 peripheral clock enable register */
-
-#define RCC_APB2ENR_TIM11EN_BIT         21
-#define RCC_APB2ENR_TIM10EN_BIT         20
-#define RCC_APB2ENR_TIM9EN_BIT          19
-#define RCC_APB2ENR_ADC3EN_BIT          15
-#define RCC_APB2ENR_USART1EN_BIT        14
-#define RCC_APB2ENR_TIM8EN_BIT          13
-#define RCC_APB2ENR_SPI1EN_BIT          12
-#define RCC_APB2ENR_TIM1EN_BIT          11
-#define RCC_APB2ENR_ADC2EN_BIT          10
-#define RCC_APB2ENR_ADC1EN_BIT          9
-#define RCC_APB2ENR_IOPGEN_BIT          8
-#define RCC_APB2ENR_IOPFEN_BIT          7
-#define RCC_APB2ENR_IOPEEN_BIT          6
-#define RCC_APB2ENR_IOPDEN_BIT          5
-#define RCC_APB2ENR_IOPCEN_BIT          4
-#define RCC_APB2ENR_IOPBEN_BIT          3
-#define RCC_APB2ENR_IOPAEN_BIT          2
-#define RCC_APB2ENR_AFIOEN_BIT          0
-
-#define RCC_APB2ENR_TIM11EN             BIT(RCC_APB2ENR_TIM11EN_BIT)
-#define RCC_APB2ENR_TIM10EN             BIT(RCC_APB2ENR_TIM10EN_BIT)
-#define RCC_APB2ENR_TIM9EN              BIT(RCC_APB2ENR_TIM9EN_BIT)
-#define RCC_APB2ENR_ADC3EN              BIT(RCC_APB2ENR_ADC3EN_BIT)
-#define RCC_APB2ENR_USART1EN            BIT(RCC_APB2ENR_USART1EN_BIT)
-#define RCC_APB2ENR_TIM8EN              BIT(RCC_APB2ENR_TIM8EN_BIT)
-#define RCC_APB2ENR_SPI1EN              BIT(RCC_APB2ENR_SPI1EN_BIT)
-#define RCC_APB2ENR_TIM1EN              BIT(RCC_APB2ENR_TIM1EN_BIT)
-#define RCC_APB2ENR_ADC2EN              BIT(RCC_APB2ENR_ADC2EN_BIT)
-#define RCC_APB2ENR_ADC1EN              BIT(RCC_APB2ENR_ADC1EN_BIT)
-#define RCC_APB2ENR_IOPGEN              BIT(RCC_APB2ENR_IOPGEN_BIT)
-#define RCC_APB2ENR_IOPFEN              BIT(RCC_APB2ENR_IOPFEN_BIT)
-#define RCC_APB2ENR_IOPEEN              BIT(RCC_APB2ENR_IOPEEN_BIT)
-#define RCC_APB2ENR_IOPDEN              BIT(RCC_APB2ENR_IOPDEN_BIT)
-#define RCC_APB2ENR_IOPCEN              BIT(RCC_APB2ENR_IOPCEN_BIT)
-#define RCC_APB2ENR_IOPBEN              BIT(RCC_APB2ENR_IOPBEN_BIT)
-#define RCC_APB2ENR_IOPAEN              BIT(RCC_APB2ENR_IOPAEN_BIT)
-#define RCC_APB2ENR_AFIOEN              BIT(RCC_APB2ENR_AFIOEN_BIT)
-
-/* APB1 peripheral clock enable register */
-
-#define RCC_APB1ENR_DACEN_BIT           29
-#define RCC_APB1ENR_PWREN_BIT           28
-#define RCC_APB1ENR_BKPEN_BIT           27
-#define RCC_APB1ENR_CANEN_BIT           25
-#define RCC_APB1ENR_USBEN_BIT           23
-#define RCC_APB1ENR_I2C2EN_BIT          22
-#define RCC_APB1ENR_I2C1EN_BIT          21
-#define RCC_APB1ENR_UART5EN_BIT         20
-#define RCC_APB1ENR_UART4EN_BIT         19
-#define RCC_APB1ENR_USART3EN_BIT        18
-#define RCC_APB1ENR_USART2EN_BIT        17
-#define RCC_APB1ENR_SPI3EN_BIT          15
-#define RCC_APB1ENR_SPI2EN_BIT          14
-#define RCC_APB1ENR_WWDEN_BIT           11
-#define RCC_APB1ENR_TIM14EN_BIT         8
-#define RCC_APB1ENR_TIM13EN_BIT         7
-#define RCC_APB1ENR_TIM12EN_BIT         6
-#define RCC_APB1ENR_TIM7EN_BIT          5
-#define RCC_APB1ENR_TIM6EN_BIT          4
-#define RCC_APB1ENR_TIM5EN_BIT          3
-#define RCC_APB1ENR_TIM4EN_BIT          2
-#define RCC_APB1ENR_TIM3EN_BIT          1
-#define RCC_APB1ENR_TIM2EN_BIT          0
-
-#define RCC_APB1ENR_DACEN               BIT(RCC_APB1ENR_DACEN_BIT)
-#define RCC_APB1ENR_PWREN               BIT(RCC_APB1ENR_PWREN_BIT)
-#define RCC_APB1ENR_BKPEN               BIT(RCC_APB1ENR_BKPEN_BIT)
-#define RCC_APB1ENR_CANEN               BIT(RCC_APB1ENR_CANEN_BIT)
-#define RCC_APB1ENR_USBEN               BIT(RCC_APB1ENR_USBEN_BIT)
-#define RCC_APB1ENR_I2C2EN              BIT(RCC_APB1ENR_I2C2EN_BIT)
-#define RCC_APB1ENR_I2C1EN              BIT(RCC_APB1ENR_I2C1EN_BIT)
-#define RCC_APB1ENR_UART5EN             BIT(RCC_APB1ENR_UART5EN_BIT)
-#define RCC_APB1ENR_UART4EN             BIT(RCC_APB1ENR_UART4EN_BIT)
-#define RCC_APB1ENR_USART3EN            BIT(RCC_APB1ENR_USART3EN_BIT)
-#define RCC_APB1ENR_USART2EN            BIT(RCC_APB1ENR_USART2EN_BIT)
-#define RCC_APB1ENR_SPI3EN              BIT(RCC_APB1ENR_SPI3EN_BIT)
-#define RCC_APB1ENR_SPI2EN              BIT(RCC_APB1ENR_SPI2EN_BIT)
-#define RCC_APB1ENR_WWDEN               BIT(RCC_APB1ENR_WWDEN_BIT)
-#define RCC_APB1ENR_TIM14EN             BIT(RCC_APB1ENR_TIM14EN_BIT)
-#define RCC_APB1ENR_TIM13EN             BIT(RCC_APB1ENR_TIM13EN_BIT)
-#define RCC_APB1ENR_TIM12EN             BIT(RCC_APB1ENR_TIM12EN_BIT)
-#define RCC_APB1ENR_TIM7EN              BIT(RCC_APB1ENR_TIM7EN_BIT)
-#define RCC_APB1ENR_TIM6EN              BIT(RCC_APB1ENR_TIM6EN_BIT)
-#define RCC_APB1ENR_TIM5EN              BIT(RCC_APB1ENR_TIM5EN_BIT)
-#define RCC_APB1ENR_TIM4EN              BIT(RCC_APB1ENR_TIM4EN_BIT)
-#define RCC_APB1ENR_TIM3EN              BIT(RCC_APB1ENR_TIM3EN_BIT)
-#define RCC_APB1ENR_TIM2EN              BIT(RCC_APB1ENR_TIM2EN_BIT)
-
-/* Backup domain control register */
-
-#define RCC_BDCR_BDRST_BIT              16
-#define RCC_BDCR_RTCEN_BIT              15
-#define RCC_BDCR_LSEBYP_BIT             2
-#define RCC_BDCR_LSERDY_BIT             1
-#define RCC_BDCR_LSEON_BIT              0
-
-#define RCC_BDCR_BDRST                  BIT(RCC_BDCR_BDRST_BIT)
-#define RCC_BDCR_RTCEN                  BIT(RCC_BDCR_RTC_BIT)
-#define RCC_BDCR_RTCSEL                 (0x3 << 8)
-#define RCC_BDCR_RTCSEL_NONE            (0x0 << 8)
-#define RCC_BDCR_RTCSEL_LSE             (0x1 << 8)
-#define RCC_BDCR_RTCSEL_LSI             (0x2 << 8)
-#define RCC_BDCR_RTCSEL_HSE             (0x3 << 8)
-#define RCC_BDCR_LSEBYP                 BIT(RCC_BDCR_LSEBYP_BIT)
-#define RCC_BDCR_LSERDY                 BIT(RCC_BDCR_LSERDY_BIT)
-#define RCC_BDCR_LSEON                  BIT(RCC_BDCR_LSEON_BIT)
-
-/* Control/status register */
-
-#define RCC_CSR_LPWRRSTF_BIT            31
-#define RCC_CSR_WWDGRSTF_BIT            30
-#define RCC_CSR_IWDGRSTF_BIT            29
-#define RCC_CSR_SFTRSTF_BIT             28
-#define RCC_CSR_PORRSTF_BIT             27
-#define RCC_CSR_PINRSTF_BIT             26
-#define RCC_CSR_RMVF_BIT                24
-#define RCC_CSR_LSIRDY_BIT              1
-#define RCC_CSR_LSION_BIT               0
-
-#define RCC_CSR_LPWRRSTF                BIT(RCC_CSR_LPWRRSTF_BIT)
-#define RCC_CSR_WWDGRSTF                BIT(RCC_CSR_WWDGRSTF_BIT)
-#define RCC_CSR_IWDGRSTF                BIT(RCC_CSR_IWDGRSTF_BIT)
-#define RCC_CSR_SFTRSTF                 BIT(RCC_CSR_SFTRSTF_BIT)
-#define RCC_CSR_PORRSTF                 BIT(RCC_CSR_PORRSTF_BIT)
-#define RCC_CSR_PINRSTF                 BIT(RCC_CSR_PINRSTF_BIT)
-#define RCC_CSR_RMVF                    BIT(RCC_CSR_RMVF_BIT)
-#define RCC_CSR_LSIRDY                  BIT(RCC_CSR_LSIRDY_BIT)
-#define RCC_CSR_LSION                   BIT(RCC_CSR_LSION_BIT)
-
-/*
- * Convenience routines
- */
-
-/**
- * SYSCLK sources
- * @see rcc_clk_init()
- */
-typedef enum rcc_sysclk_src {
-    RCC_CLKSRC_HSI = 0x0,
-    RCC_CLKSRC_HSE = 0x1,
-    RCC_CLKSRC_PLL = 0x2,
-} rcc_sysclk_src;
-
-/**
- * PLL entry clock source
- * @see rcc_clk_init()
- */
-typedef enum rcc_pllsrc {
-    RCC_PLLSRC_HSE = (0x1 << 16),
-    RCC_PLLSRC_HSI_DIV_2 = (0x0 << 16)
-} rcc_pllsrc;
-
-/**
- * PLL multipliers
- * @see rcc_clk_init()
- */
-typedef enum rcc_pll_multiplier {
-    RCC_PLLMUL_2 = (0x0 << 18),
-    RCC_PLLMUL_3 = (0x1 << 18),
-    RCC_PLLMUL_4 = (0x2 << 18),
-    RCC_PLLMUL_5 = (0x3 << 18),
-    RCC_PLLMUL_6 = (0x4 << 18),
-    RCC_PLLMUL_7 = (0x5 << 18),
-    RCC_PLLMUL_8 = (0x6 << 18),
-    RCC_PLLMUL_9 = (0x7 << 18),
-    RCC_PLLMUL_10 = (0x8 << 18),
-    RCC_PLLMUL_11 = (0x9 << 18),
-    RCC_PLLMUL_12 = (0xA << 18),
-    RCC_PLLMUL_13 = (0xB << 18),
-    RCC_PLLMUL_14 = (0xC << 18),
-    RCC_PLLMUL_15 = (0xD << 18),
-    RCC_PLLMUL_16 = (0xE << 18),
-} rcc_pll_multiplier;
-
-/**
- * @brief Identifies bus and clock line for a peripheral.
- *
- * Also generally useful as a unique identifier for that peripheral
- * (or its corresponding device struct).
- */
-typedef enum rcc_clk_id {
-    RCC_GPIOA,
-    RCC_GPIOB,
-    RCC_GPIOC,
-    RCC_GPIOD,
-//    RCC_AFIO,
-    RCC_ADC1,
-    RCC_ADC2,
-    RCC_ADC3,
-    RCC_USART1,
-    RCC_USART2,
-    RCC_USART3,
-    RCC_TIMER1,
-    RCC_TIMER2,
-    RCC_TIMER3,
-    RCC_TIMER4,
-    RCC_SPI1,
-    RCC_SPI2,
-    RCC_DMA1,
-    RCC_PWR,
-    RCC_BKP,
-    RCC_I2C1,
-    RCC_I2C2,
-    RCC_CRC,
-//    RCC_FLITF,
-//    RCC_SRAM,
-    RCC_GPIOE,
-    RCC_GPIOF,
-    RCC_GPIOG,
-    RCC_UART4,
-    RCC_UART5,
-    RCC_TIMER5,
-    RCC_TIMER6,
-    RCC_TIMER7,
-    RCC_TIMER8,
-    RCC_FSMC,
-    RCC_DAC,
-    RCC_DMA2,
-    RCC_SDIO,
-    RCC_SPI3,
-    RCC_TIMER9,
-    RCC_TIMER10,
-    RCC_TIMER11,
-    RCC_TIMER12,
-    RCC_TIMER13,
-    RCC_TIMER14,
-    RCC_USBFS,
-    RCC_SYSCFG,
-	RCC_SPI4
-} rcc_clk_id;
-
-void rcc_clk_init(rcc_sysclk_src sysclk_src,
-                  rcc_pllsrc pll_src,
-                  rcc_pll_multiplier pll_mul);
-void rcc_clk_disable(rcc_clk_id device);
-void rcc_clk_enable(rcc_clk_id device);
-void rcc_reset_dev(rcc_clk_id device);
-
-void SetupClock72MHz();
-void SetupClock120MHz();
-void SetupClock168MHz();
-
-typedef enum rcc_clk_domain {
-    RCC_APB1,
-    RCC_APB2,
-    RCC_AHB1,
-    RCC_AHB2,
-    RCC_AHB3
-} rcc_clk_domain;
-
-rcc_clk_domain rcc_dev_clk(rcc_clk_id device);
-
-uint32 rcc_dev_clk_speed(rcc_clk_id id);
-uint32 rcc_dev_timer_clk_speed(rcc_clk_id id);
-
-/**
- * Prescaler identifiers
- * @see rcc_set_prescaler()
- */
-typedef enum rcc_prescaler {
-    RCC_PRESCALER_AHB,
-    RCC_PRESCALER_APB1,
-    RCC_PRESCALER_APB2,
-    RCC_PRESCALER_USB,
-    RCC_PRESCALER_ADC
-} rcc_prescaler;
-
-/**
- * ADC prescaler dividers
- * @see rcc_set_prescaler()
- */
-typedef enum rcc_adc_divider {
-    RCC_ADCPRE_PCLK_DIV_2 = 0x0 << 14,
-    RCC_ADCPRE_PCLK_DIV_4 = 0x1 << 14,
-    RCC_ADCPRE_PCLK_DIV_6 = 0x2 << 14,
-    RCC_ADCPRE_PCLK_DIV_8 = 0x3 << 14,
-} rcc_adc_divider;
-
-/**
- * APB1 prescaler dividers
- * @see rcc_set_prescaler()
- */
-typedef enum rcc_apb1_divider {
-    RCC_APB1_HCLK_DIV_1 = 0x0 << 8,
-    RCC_APB1_HCLK_DIV_2 = 0x4 << 8,
-    RCC_APB1_HCLK_DIV_4 = 0x5 << 8,
-    RCC_APB1_HCLK_DIV_8 = 0x6 << 8,
-    RCC_APB1_HCLK_DIV_16 = 0x7 << 8,
-} rcc_apb1_divider;
-
-/**
- * APB2 prescaler dividers
- * @see rcc_set_prescaler()
- */
-typedef enum rcc_apb2_divider {
-    RCC_APB2_HCLK_DIV_1 = 0x0 << 11,
-    RCC_APB2_HCLK_DIV_2 = 0x4 << 11,
-    RCC_APB2_HCLK_DIV_4 = 0x5 << 11,
-    RCC_APB2_HCLK_DIV_8 = 0x6 << 11,
-    RCC_APB2_HCLK_DIV_16 = 0x7 << 11,
-} rcc_apb2_divider;
-
-/**
- * AHB prescaler dividers
- * @see rcc_set_prescaler()
- */
-typedef enum rcc_ahb_divider {
-    RCC_AHB_SYSCLK_DIV_1 = 0x0 << 4,
-    RCC_AHB_SYSCLK_DIV_2 = 0x8 << 4,
-    RCC_AHB_SYSCLK_DIV_4 = 0x9 << 4,
-    RCC_AHB_SYSCLK_DIV_8 = 0xA << 4,
-    RCC_AHB_SYSCLK_DIV_16 = 0xB << 4,
-    RCC_AHB_SYSCLK_DIV_32 = 0xC << 4,
-    RCC_AHB_SYSCLK_DIV_64 = 0xD << 4,
-    RCC_AHB_SYSCLK_DIV_128 = 0xD << 4,
-    RCC_AHB_SYSCLK_DIV_256 = 0xE << 4,
-    RCC_AHB_SYSCLK_DIV_512 = 0xF << 4,
-} rcc_ahb_divider;
-
-void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider);
-
-
-/**
- * @brief Start the low speed internal oscillatior
- */
-static inline void rcc_start_lsi(void) {
-	*bb_perip(&RCC_BASE->CSR, RCC_CSR_LSION_BIT) = 1;
-	while (*bb_perip(&RCC_BASE->CSR, RCC_CSR_LSIRDY_BIT) == 0);
-}
-
-/* FIXME [0.0.13] Just have data point to an rcc_pll_multiplier! */
-/**
- * @brief Start the low speed external oscillatior
- */
-static inline void rcc_start_lse(void) {
-	bb_peri_set_bit(&RCC_BASE->BDCR, RCC_BDCR_LSEBYP_BIT, 0);
-	bb_peri_set_bit(&RCC_BASE->BDCR, RCC_BDCR_LSEON_BIT, 1);
-	while (bb_peri_get_bit(&RCC_BASE->BDCR, RCC_BDCR_LSERDY_BIT ) == 0);
-}
-
-/*
- * Deprecated bits.
- */
-static inline void rcc_start_hse(void) {				// Added to support RTClock
-//	*bb_perip(&RCC_BASE->CR, RCC_CR_HSEON_BIT) = 1;
-	while (bb_peri_get_bit(&RCC_BASE->CR, RCC_CR_HSERDY_BIT) == 0);
-}
-
-
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
-#endif
diff --git a/STM32F4/cores/maple/libmaple/usbF4/usb.c b/STM32F4/cores/maple/libmaple/usbF4/usb.c
index 263e76f84..c013f04de 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/usb.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/usb.c
@@ -11,8 +11,8 @@ USB_OTG_CORE_HANDLE  USB_OTG_dev;
 
 
 void setupUSB (void) {
-    #define USB_DISC_DEV         GPIOD
-    #define USB_DISC_PIN         11
+    #define USB_DISC_DEV         GPIOA
+    #define USB_DISC_PIN         12
 
 	gpio_set_mode(USB_DISC_DEV, USB_DISC_PIN, GPIO_OUTPUT_OD); // ala42
 #ifdef USB_DISC_OD
diff --git a/STM32F4/cores/maple/wirish_types.h b/STM32F4/cores/maple/wirish_types.h
index 2d6d6a9a6..55364ab45 100644
--- a/STM32F4/cores/maple/wirish_types.h
+++ b/STM32F4/cores/maple/wirish_types.h
@@ -48,7 +48,7 @@
  * @brief Stores STM32-specific information related to a given Maple pin.
  * @see PIN_MAP
  */
-#ifdef BOARD_black_f4
+#ifdef BOARD_generic_f407v
 // restructure members to build consecutive pairs
 typedef struct stm32_pin_info {
     gpio_dev *gpio_device;      /**< Maple pin's GPIO device */
diff --git a/STM32F4/variants/black_f407vet6/black_f4.h b/STM32F4/variants/generic_f407v/black_f4.h.old
similarity index 99%
rename from STM32F4/variants/black_f407vet6/black_f4.h
rename to STM32F4/variants/generic_f407v/black_f4.h.old
index 6f5d3dac7..20bb174c3 100644
--- a/STM32F4/variants/black_f407vet6/black_f4.h
+++ b/STM32F4/variants/generic_f407v/black_f4.h.old
@@ -121,7 +121,7 @@ PB0,PB1,PB2,PB3,PB4,PB5,PB6,PB7,PB8,PB9,PB10,PB11,PB12,PB13,PB14,PB15,
 PC0,PC1,PC2,PC3,PC4,PC5,PC6,PC7,PC8,PC9,PC10,PC11,PC12,PC13,PC14,PC15,
 PD0,PD1,PD2,PD3,PD4,PD5,PD6,PD7,PD8,PD9,PD10,PD11,PD12,PD13,PD14,PD15,
 PE0,PE1,PE2,PE3,PE4,PE5,PE6,PE7,PE8,PE9,PE10,PE11,PE12,PE13,PE14,PE15,
-#if 0
+#if 0 // not available on LQFP100 package
 PF0,PF1,PF2,PF3,PF4,PF5,PF6,PF7,PF8,PF9,PF10,PF11,PF12,PF13,PF14,PF15,
 PG0,PG1,PG2,PG3,PG4,PG5,PG6,PG7,PG8,PG9,PG10,PG11,PG12,PG13,PG14,PG15
 #endif
diff --git a/STM32F4/variants/black_f407vet6/black_f4.cpp b/STM32F4/variants/generic_f407v/generic_f407v.cpp
similarity index 99%
rename from STM32F4/variants/black_f407vet6/black_f4.cpp
rename to STM32F4/variants/generic_f407v/generic_f407v.cpp
index 78d37aafc..119906476 100644
--- a/STM32F4/variants/black_f407vet6/black_f4.cpp
+++ b/STM32F4/variants/generic_f407v/generic_f407v.cpp
@@ -25,14 +25,14 @@
  *****************************************************************************/
 
 /**
- * @file   black_f4.cpp
+ * @file   generic_f407v.cpp
  * @author ala42
- * @brief  black_f4 board file.
+ * @brief  generic_f407v board file.
  */
 
-#ifdef BOARD_black_f4
+#ifdef BOARD_generic_f407v
 
-#include "black_f4.h"
+#include "generic_f407v.h"
 
 //#include "fsmc.h"
 #include "gpio.h"
diff --git a/STM32F4/variants/generic_f407v/generic_f407v.h b/STM32F4/variants/generic_f407v/generic_f407v.h
new file mode 100644
index 000000000..15e93e457
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/generic_f407v.h
@@ -0,0 +1,130 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file   generic_f407v.h
+ * @author Marti Bolivar <mbolivar@leaflabs.com>
+ * @brief  Private include file for Maple Native in boards.h
+ *
+ * See maple.h for more information on these definitions.
+ */
+
+#ifndef _BOARD_GENERIC_F407V_H_
+#define _BOARD_GENERIC_F407V_H_
+
+#define Port2Pin(port, bit) ((port-'A')*16+bit)
+
+#define CYCLES_PER_MICROSECOND  168
+
+
+#undef  STM32_PCLK1
+#undef  STM32_PCLK2
+#define STM32_PCLK1   (CYCLES_PER_MICROSECOND*1000000/4)
+#define STM32_PCLK2   (CYCLES_PER_MICROSECOND*1000000/2)
+
+#define SYSTICK_RELOAD_VAL      (CYCLES_PER_MICROSECOND*1000-1)
+
+#define BOARD_USB_DM_PIN		PA11
+#define BOARD_USB_DP_PIN		PA12
+
+#define BOARD_LED_PIN           PA6 //Port2Pin('A', 6)
+#define BOARD_LED2_PIN          PA7 //Port2Pin('A', 7)
+#define BOARD_BUTTON1_PIN       PA0 //Port2Pin('A', 0)
+#define BOARD_BUTTON2_PIN       PE4 //Port2Pin('E', 4)
+#define BOARD_BUTTON3_PIN       PE3 //Port2Pin('E', 3)
+
+#define BOARD_NR_USARTS         5
+#define BOARD_USART1_TX_PIN     PA9  //Port2Pin('A', 9)
+#define BOARD_USART1_RX_PIN     PA10 //Port2Pin('A',10)
+#define BOARD_USART2_TX_PIN     PA2  //Port2Pin('A', 2)
+#define BOARD_USART2_RX_PIN     PA3  //Port2Pin('A', 3)
+#define BOARD_USART3_TX_PIN     PB10 //Port2Pin('B',10)
+#define BOARD_USART3_RX_PIN     PB11 //Port2Pin('B',11)
+#define BOARD_UART4_TX_PIN      PA0  //Port2Pin('A', 0)
+#define BOARD_UART4_RX_PIN      PA1  //Port2Pin('A', 1)
+#define BOARD_UART5_TX_PIN      PC12 //Port2Pin('C',12)
+#define BOARD_UART5_RX_PIN      PD2  //Port2Pin('D', 2)
+
+#define BOARD_NR_SPI            3
+#define BOARD_SPI1_NSS_PIN      PA4  //Port2Pin('A', 4)
+#define BOARD_SPI1_SCK_PIN      PA5  //Port2Pin('A', 5)
+#define BOARD_SPI1_MISO_PIN     PA6  //Port2Pin('A', 6)
+#define BOARD_SPI1_MOSI_PIN     PA7  //Port2Pin('A', 7)
+#define BOARD_SPI1A_NSS_PIN     PA15 //Port2Pin('A',15)
+#define BOARD_SPI1A_SCK_PIN     PB3  //Port2Pin('B', 3)
+#define BOARD_SPI1A_MISO_PIN    PB4  //Port2Pin('B', 4)
+#define BOARD_SPI1A_MOSI_PIN    PB5  //Port2Pin('B', 5)
+
+#define BOARD_SPI2_NSS_PIN      PB12 //Port2Pin('B',12)
+#define BOARD_SPI2_SCK_PIN      PB13 //Port2Pin('B',13)
+#define BOARD_SPI2_MISO_PIN     PB14 //Port2Pin('B',14)
+#define BOARD_SPI2_MOSI_PIN     PB15 //Port2Pin('B',15)
+#define BOARD_SPI2A_NSS_PIN     PB9  //Port2Pin('B', 9)
+#define BOARD_SPI2A_SCK_PIN     PB10 //Port2Pin('B',10)
+#define BOARD_SPI2A_MISO_PIN    PC2  //Port2Pin('C', 2)
+#define BOARD_SPI2A_MOSI_PIN    pc3  //Port2Pin('C', 3)
+
+#define BOARD_SPI3_NSS_PIN      PA15 //Port2Pin('A',15)
+#define BOARD_SPI3_SCK_PIN      PB3  //Port2Pin('B', 3)
+#define BOARD_SPI3_MISO_PIN     PB4  //Port2Pin('B', 4)
+#define BOARD_SPI3_MOSI_PIN     PB5  //Port2Pin('B', 5)
+/* overlap with the SDIO interface for SD card
+#define BOARD_SPI3A_NSS_PIN     Port2Pin('A', 4)
+#define BOARD_SPI3A_SCK_PIN     Port2Pin('C',10)
+#define BOARD_SPI3A_MISO_PIN    Port2Pin('C',11)
+#define BOARD_SPI3A_MOSI_PIN    Port2Pin('C',12)
+*/
+#define BOARD_SDIO_D0           PC8  //Port2Pin('C', 8)
+#define BOARD_SDIO_D1           PC9  //Port2Pin('C', 9)
+#define BOARD_SDIO_D2           PC10 //Port2Pin('C',10)
+#define BOARD_SDIO_D3           PC11 //Port2Pin('C',11)
+#define BOARD_SDIO_CK           PC12 //Port2Pin('C',12)
+#define BOARD_SDIO_CMD          PD2  //Port2Pin('D', 2)
+
+#define BOARD_NR_GPIO_PINS      80
+#define BOARD_NR_PWM_PINS       22
+#define BOARD_NR_ADC_PINS       16
+#define BOARD_NR_USED_PINS      22
+#define BOARD_JTMS_SWDIO_PIN    PA13 //Port2Pin('A',13)
+#define BOARD_JTCK_SWCLK_PIN    PA14 //Port2Pin('A',14)
+#define BOARD_JTDI_PIN          PA15 //Port2Pin('A',15)
+#define BOARD_JTDO_PIN          PB3  //Port2Pin('B', 3)
+#define BOARD_NJTRST_PIN        PB4  //Port2Pin('B', 4)
+
+
+enum {
+PA0,PA1,PA2,PA3,PA4,PA5,PA6,PA7,PA8,PA9,PA10,PA11,PA12,PA13,PA14,PA15,
+PB0,PB1,PB2,PB3,PB4,PB5,PB6,PB7,PB8,PB9,PB10,PB11,PB12,PB13,PB14,PB15,
+PC0,PC1,PC2,PC3,PC4,PC5,PC6,PC7,PC8,PC9,PC10,PC11,PC12,PC13,PC14,PC15,
+PD0,PD1,PD2,PD3,PD4,PD5,PD6,PD7,PD8,PD9,PD10,PD11,PD12,PD13,PD14,PD15,
+PE0,PE1,PE2,PE3,PE4,PE5,PE6,PE7,PE8,PE9,PE10,PE11,PE12,PE13,PE14,PE15,
+#if 0 // not available on LQFP100 package
+PF0,PF1,PF2,PF3,PF4,PF5,PF6,PF7,PF8,PF9,PF10,PF11,PF12,PF13,PF14,PF15,
+PG0,PG1,PG2,PG3,PG4,PG5,PG6,PG7,PG8,PG9,PG10,PG11,PG12,PG13,PG14,PG15
+#endif
+};
+
+#endif
diff --git a/STM32F4/variants/black_f407vet6/ld/common.inc b/STM32F4/variants/generic_f407v/ld/common.inc
similarity index 100%
rename from STM32F4/variants/black_f407vet6/ld/common.inc
rename to STM32F4/variants/generic_f407v/ld/common.inc
diff --git a/STM32F4/variants/black_f407vet6/ld/extra_libs.inc b/STM32F4/variants/generic_f407v/ld/extra_libs.inc
similarity index 100%
rename from STM32F4/variants/black_f407vet6/ld/extra_libs.inc
rename to STM32F4/variants/generic_f407v/ld/extra_libs.inc
diff --git a/STM32F4/variants/black_f407vet6/ld/flash.ld b/STM32F4/variants/generic_f407v/ld/flash.ld
similarity index 100%
rename from STM32F4/variants/black_f407vet6/ld/flash.ld
rename to STM32F4/variants/generic_f407v/ld/flash.ld
diff --git a/STM32F4/variants/black_f407vet6/ld/jtag.ld b/STM32F4/variants/generic_f407v/ld/jtag.ld
similarity index 100%
rename from STM32F4/variants/black_f407vet6/ld/jtag.ld
rename to STM32F4/variants/generic_f407v/ld/jtag.ld
diff --git a/STM32F4/variants/black_f407vet6/ld/names.inc b/STM32F4/variants/generic_f407v/ld/names.inc
similarity index 100%
rename from STM32F4/variants/black_f407vet6/ld/names.inc
rename to STM32F4/variants/generic_f407v/ld/names.inc
diff --git a/STM32F4/variants/black_f407vet6/ld/ram.ld b/STM32F4/variants/generic_f407v/ld/ram.ld
similarity index 100%
rename from STM32F4/variants/black_f407vet6/ld/ram.ld
rename to STM32F4/variants/generic_f407v/ld/ram.ld
diff --git a/STM32F4/variants/black_f407vet6/ld/vector_symbols.inc b/STM32F4/variants/generic_f407v/ld/vector_symbols.inc
similarity index 100%
rename from STM32F4/variants/black_f407vet6/ld/vector_symbols.inc
rename to STM32F4/variants/generic_f407v/ld/vector_symbols.inc
diff --git a/STM32F4/variants/black_f407vet6/pins_arduino.h b/STM32F4/variants/generic_f407v/pins_arduino.h
similarity index 100%
rename from STM32F4/variants/black_f407vet6/pins_arduino.h
rename to STM32F4/variants/generic_f407v/pins_arduino.h
diff --git a/STM32F4/variants/black_f407vet6/stm32_isrs.S b/STM32F4/variants/generic_f407v/stm32_isrs.S
similarity index 100%
rename from STM32F4/variants/black_f407vet6/stm32_isrs.S
rename to STM32F4/variants/generic_f407v/stm32_isrs.S
diff --git a/STM32F4/variants/black_f407vet6/stm32_vector_table.S b/STM32F4/variants/generic_f407v/stm32_vector_table.S
similarity index 100%
rename from STM32F4/variants/black_f407vet6/stm32_vector_table.S
rename to STM32F4/variants/generic_f407v/stm32_vector_table.S
diff --git a/STM32F4/variants/black_f407vet6/variant.h b/STM32F4/variants/generic_f407v/variant.h
similarity index 100%
rename from STM32F4/variants/black_f407vet6/variant.h
rename to STM32F4/variants/generic_f407v/variant.h
diff --git a/STM32F4/variants/black_f407vet6/wirish/start.S b/STM32F4/variants/generic_f407v/wirish/start.S
similarity index 100%
rename from STM32F4/variants/black_f407vet6/wirish/start.S
rename to STM32F4/variants/generic_f407v/wirish/start.S
diff --git a/STM32F4/variants/black_f407vet6/wirish/start_c.c b/STM32F4/variants/generic_f407v/wirish/start_c.c
similarity index 100%
rename from STM32F4/variants/black_f407vet6/wirish/start_c.c
rename to STM32F4/variants/generic_f407v/wirish/start_c.c

From cbfb87222fec84af899c11d2da8195fe92ad098f Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Giorgiogg=C3=AC?= <software@sukkology.net>
Date: Tue, 18 Apr 2017 12:24:06 +0200
Subject: [PATCH 050/307] Fix indentation

---
 STM32F1/cores/maple/usb_serial.h | 15 +++++++--------
 1 file changed, 7 insertions(+), 8 deletions(-)

diff --git a/STM32F1/cores/maple/usb_serial.h b/STM32F1/cores/maple/usb_serial.h
index 96bbefc25..c2de1c580 100644
--- a/STM32F1/cores/maple/usb_serial.h
+++ b/STM32F1/cores/maple/usb_serial.h
@@ -44,19 +44,19 @@ class USBSerial : public Stream {
 
     void begin(void);
 
-	// Roger Clark. Added dummy function so that existing Arduino sketches which specify baud rate will compile.
-	void begin(unsigned long);
-	void begin(unsigned long, uint8_t);
+    // Roger Clark. Added dummy function so that existing Arduino sketches which specify baud rate will compile.
+    void begin(unsigned long);
+    void begin(unsigned long, uint8_t);
     void end(void);
 
-	operator bool() { return true; } // Roger Clark. This is needed because in cardinfo.ino it does if (!Serial) . It seems to be a work around for the Leonardo that we needed to implement just to be compliant with the API
+    operator bool() { return true; } // Roger Clark. This is needed because in cardinfo.ino it does if (!Serial) . It seems to be a work around for the Leonardo that we needed to implement just to be compliant with the API
 
     virtual int available(void);// Changed to virtual
 
     uint32 read(uint8 * buf, uint32 len);
-   // uint8  read(void);
+    // uint8  read(void);
 
-	// Roger Clark. added functions to support Arduino 1.0 API
+    // Roger Clark. added functions to support Arduino 1.0 API
     virtual int peek(void);
     virtual int read(void);
     int availableForWrite(void);
@@ -74,8 +74,7 @@ class USBSerial : public Stream {
 };
 
 #ifdef SERIAL_USB 
-	extern USBSerial Serial;
+    extern USBSerial Serial;
 #endif
 
 #endif
-

From 0be991b434abc14f7ec9c91252977b60350d263c Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Giorgiogg=C3=AC?= <software@sukkology.net>
Date: Tue, 18 Apr 2017 12:43:01 +0200
Subject: [PATCH 051/307] Update usb_serial.h

---
 STM32F1/cores/maple/usb_serial.h | 16 +++++++++++++---
 1 file changed, 13 insertions(+), 3 deletions(-)

diff --git a/STM32F1/cores/maple/usb_serial.h b/STM32F1/cores/maple/usb_serial.h
index c2de1c580..ceb81e17b 100644
--- a/STM32F1/cores/maple/usb_serial.h
+++ b/STM32F1/cores/maple/usb_serial.h
@@ -49,8 +49,6 @@ class USBSerial : public Stream {
     void begin(unsigned long, uint8_t);
     void end(void);
 
-    operator bool() { return true; } // Roger Clark. This is needed because in cardinfo.ino it does if (!Serial) . It seems to be a work around for the Leonardo that we needed to implement just to be compliant with the API
-
     virtual int available(void);// Changed to virtual
 
     uint32 read(uint8 * buf, uint32 len);
@@ -69,8 +67,20 @@ class USBSerial : public Stream {
 
     uint8 getRTS();
     uint8 getDTR();
-    uint8 isConnected();
     uint8 pending();
+	
+    /* SukkoPera: This is the Arduino way to check if an USB CDC serial
+     * connection is open.
+     
+     * Used for instance in cardinfo.ino.
+     */
+    operator bool();
+	
+    /* Old libmaple way to check for serial connection.
+     *
+     * Deprecated, use the above.
+     */
+    uint8 isConnected() { return (bool) *this; }
 };
 
 #ifdef SERIAL_USB 

From 38525521fd9ea4713970073326c21b8e9c54c09b Mon Sep 17 00:00:00 2001
From: =?UTF-8?q?Giorgiogg=C3=AC?= <software@sukkology.net>
Date: Tue, 18 Apr 2017 12:44:10 +0200
Subject: [PATCH 052/307] Update usb_serial.cpp

---
 STM32F1/cores/maple/usb_serial.cpp | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/STM32F1/cores/maple/usb_serial.cpp b/STM32F1/cores/maple/usb_serial.cpp
index 5eaf70efb..2f7daddfd 100644
--- a/STM32F1/cores/maple/usb_serial.cpp
+++ b/STM32F1/cores/maple/usb_serial.cpp
@@ -178,10 +178,6 @@ uint8 USBSerial::pending(void) {
     return usb_cdcacm_get_pending();
 }
 
-uint8 USBSerial::isConnected(void) {
-    return usb_is_connected(USBLIB) && usb_is_configured(USBLIB) && usb_cdcacm_get_dtr();
-}
-
 uint8 USBSerial::getDTR(void) {
     return usb_cdcacm_get_dtr();
 }
@@ -190,6 +186,10 @@ uint8 USBSerial::getRTS(void) {
     return usb_cdcacm_get_rts();
 }
 
+uint8 USBSerial::operator bool() {
+    return usb_is_connected(USBLIB) && usb_is_configured(USBLIB) && usb_cdcacm_get_dtr();
+}
+
 #if BOARD_HAVE_SERIALUSB
 	#ifdef SERIAL_USB 
 		USBSerial Serial;

From 81b1b08b95695256f6253bd236c4ee4755eb0089 Mon Sep 17 00:00:00 2001
From: SukkoPera <software@sukkology.net>
Date: Tue, 18 Apr 2017 23:25:36 +0200
Subject: [PATCH 053/307] Fix return type

---
 STM32F1/cores/maple/usb_serial.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/cores/maple/usb_serial.cpp b/STM32F1/cores/maple/usb_serial.cpp
index 2f7daddfd..85c70246f 100644
--- a/STM32F1/cores/maple/usb_serial.cpp
+++ b/STM32F1/cores/maple/usb_serial.cpp
@@ -186,7 +186,7 @@ uint8 USBSerial::getRTS(void) {
     return usb_cdcacm_get_rts();
 }
 
-uint8 USBSerial::operator bool() {
+USBSerial::operator bool() {
     return usb_is_connected(USBLIB) && usb_is_configured(USBLIB) && usb_cdcacm_get_dtr();
 }
 

From 0590f27afaea2e007f7f5f672add36f462e509d1 Mon Sep 17 00:00:00 2001
From: Oleksandr Masliuchenko <omaslyuchenko@gmail.com>
Date: Sat, 22 Apr 2017 16:27:30 +0300
Subject: [PATCH 054/307] Compiler warning fixed

---
 STM32F1/cores/maple/libmaple/gpio_f1.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/STM32F1/cores/maple/libmaple/gpio_f1.c b/STM32F1/cores/maple/libmaple/gpio_f1.c
index ecd015d13..6de16f55a 100644
--- a/STM32F1/cores/maple/libmaple/gpio_f1.c
+++ b/STM32F1/cores/maple/libmaple/gpio_f1.c
@@ -142,7 +142,6 @@ gpio_pin_mode gpio_get_mode(gpio_dev *dev, uint8 pin) {
     gpio_reg_map *regs = dev->regs;
     __io uint32 *cr = &regs->CRL + (pin >> 3);
     uint32 shift = (pin & 0x7) * 4;
-    uint32 tmp = *cr;
 
 	uint32 crMode = (*cr>>shift) & 0x0F;
 	

From 83c834091c99589ae18cb374975fe20454687b81 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Wed, 26 Apr 2017 23:19:20 +0200
Subject: [PATCH 055/307] reworked gpio pin handling functions

---
 STM32F4/boards.txt                            | 11 +++
 STM32F4/cores/maple/boards.cpp                |  4 +
 STM32F4/cores/maple/boards.h                  | 23 ++---
 .../cores/maple/libmaple/HardwareSerial.cpp   | 28 +++---
 STM32F4/cores/maple/libmaple/HardwareSerial.h |  2 +-
 STM32F4/cores/maple/libmaple/dac.c            |  4 +-
 STM32F4/cores/maple/libmaple/fsmc.c           | 53 +++++-----
 STM32F4/cores/maple/libmaple/gpio.h           | 99 ++++++++++++++++++-
 STM32F4/cores/maple/libmaple/gpioF4.c         | 24 +++--
 .../maple/libmaple/{gpioF4.h => gpio_def.h}   | 76 ++------------
 STM32F4/cores/maple/libmaple/i2c.c            | 40 ++++----
 STM32F4/cores/maple/libmaple/i2c.h            |  2 +-
 STM32F4/cores/maple/libmaple/libmaple_types.h |  3 +
 STM32F4/cores/maple/libmaple/rccF4.c          |  5 +-
 STM32F4/cores/maple/libmaple/spi.h            | 12 +--
 STM32F4/cores/maple/libmaple/spiF4.h          | 11 ---
 STM32F4/cores/maple/libmaple/spi_f4.c         | 26 +++--
 .../cores/maple/libmaple/usbF4/VCP/usb_bsp.c  | 16 +--
 STM32F4/cores/maple/libmaple/usbF4/usb.c      | 13 ++-
 STM32F4/cores/maple/libmaple/util.c           |  6 +-
 STM32F4/cores/maple/usb_serial.cpp            |  4 +
 STM32F4/cores/maple/usb_serial.h              |  5 +
 STM32F4/cores/maple/wirish.h                  |  4 +-
 STM32F4/cores/maple/wirish_digital.cpp        | 17 ++--
 STM32F4/cores/maple/wirish_types.h            |  9 +-
 STM32F4/platform.txt                          |  2 +-
 .../variants/generic_f407v/generic_f407v.h    |  2 +-
 STM32F4/variants/generic_f407v/ld/jtag.ld     |  2 +-
 28 files changed, 275 insertions(+), 228 deletions(-)
 rename STM32F4/cores/maple/libmaple/{gpioF4.h => gpio_def.h} (91%)

diff --git a/STM32F4/boards.txt b/STM32F4/boards.txt
index df9f2b41a..04bfd0fd0 100644
--- a/STM32F4/boards.txt
+++ b/STM32F4/boards.txt
@@ -1,5 +1,7 @@
 # 
 
+menu.usb_cfg=USB configuration
+
 ##############################################################
 discovery_f407.name=STM32 Discovery F407
 
@@ -57,6 +59,15 @@ generic_f407v.build.error_led_port=GPIOA
 generic_f407v.build.error_led_pin=7
 generic_f407v.build.board=STM32GenericF407VET6
 
+generic_f407v.menu.usb_cfg.usb_nc=USB inactive
+generic_f407v.menu.usb_cfg.usb_nc.build.cpu_flags=-DUSB_NC
+
+generic_f407v.menu.usb_cfg.usb_serial=USB serial (CDC)
+generic_f407v.menu.usb_cfg.usb_serial.build.cpu_flags=-DSERIAL_USB
+
+generic_f407v.menu.usb_cfg.usb_msc=USB Mass Storage (MSC)
+generic_f407v.menu.usb_cfg.usb_msc.build.cpu_flags=-DUSB_MSC
+
 ##############################################################
 stm32f4stamp.name=STM32F4Stamp F405
 
diff --git a/STM32F4/cores/maple/boards.cpp b/STM32F4/cores/maple/boards.cpp
index c8ba97894..fc453fece 100644
--- a/STM32F4/cores/maple/boards.cpp
+++ b/STM32F4/cores/maple/boards.cpp
@@ -41,6 +41,7 @@
 #include "adc.h"
 #include "timer.h"
 #include "usb.h"
+#include "usb_serial.h"
 
 
 static void setupFlash(void);
@@ -67,7 +68,10 @@ void init(void) {
     setupADC();
     setupTimers();
 
+#ifdef SERIAL_USB
     setupUSB();
+    SerialUSB.begin();
+#endif
 }
 
 /* You could farm this out to the files in boards/ if e.g. it takes
diff --git a/STM32F4/cores/maple/boards.h b/STM32F4/cores/maple/boards.h
index e123341ed..50fd89d38 100644
--- a/STM32F4/cores/maple/boards.h
+++ b/STM32F4/cores/maple/boards.h
@@ -40,7 +40,6 @@
 #define _BOARDS_H_
 
 #include "libmaple.h"
-#include "gpio.h"
 #include "timer.h"
 
 #include "wirish_types.h"
@@ -55,9 +54,12 @@ enum {
     D32, D33, D34, D35, D36, D37, D38, D39, D40, D41, D42, D43, D44, D45, D46,
     D47, D48, D49, D50, D51, D52, D53, D54, D55, D56, D57, D58, D59, D60, D61,
     D62, D63, D64, D65, D66, D67, D68, D69, D70, D71, D72, D73, D74, D75, D76,
+#if 0 // not available on LQFP100 package
     D77, D78, D79, D80, D81, D82, D83, D84, D85, D86, D87, D88, D89, D90, D91,
     D92, D93, D94, D95, D96, D97, D98, D99, D100, D101, D102, D103, D104, D105,
-    D106, D107, D108, D109, D110, D111, };
+    D106, D107, D108, D109, D110, D111,
+#endif // not available on LQFP100 package
+};
 
 /**
  * @brief Maps each Maple pin to a corresponding stm32_pin_info.
@@ -115,26 +117,13 @@ extern void boardInit(void);
  * @return true if the given pin is in boardUsedPins, and false otherwise.
  * @see boardUsedPins
  */
-bool boardUsesPin(uint8 pin);
+extern bool boardUsesPin(uint8 pin);
 
 /* Include the appropriate private header from boards/: */
 
 /* FIXME HACK put boards/ before these paths once IDE uses make. */
 
-#ifdef BOARD_maple
-#include "maple.h"
-#elif defined(BOARD_maple_native)
-#include "maple_native.h"
-#elif defined(BOARD_maple_mini)
-#include "maple_mini.h"
-#elif defined(BOARD_maple_RET6)
-/*
- * **NOT** MAPLE REV6.  This the **Maple RET6 EDITION**, which is a
- * Maple with an STM32F103RET6 (...RET6) instead of an STM32F103RBT6
- * (...RBT6) on it.  Maple Rev6 (as of March 2011) DOES NOT EXIST.
- */
-#include "maple_RET6.h"
-#elif defined(BOARD_aeroquad32) || defined(BOARD_aeroquad32f1)
+#if defined(BOARD_aeroquad32) || defined(BOARD_aeroquad32f1)
 #include "aeroquad32.h"
 #elif defined(BOARD_aeroquad32mini)
 #include "aeroquad32mini.h"
diff --git a/STM32F4/cores/maple/libmaple/HardwareSerial.cpp b/STM32F4/cores/maple/libmaple/HardwareSerial.cpp
index 475116b17..f9387d15a 100644
--- a/STM32F4/cores/maple/libmaple/HardwareSerial.cpp
+++ b/STM32F4/cores/maple/libmaple/HardwareSerial.cpp
@@ -56,19 +56,19 @@
 #define RX5 BOARD_UART5_RX_PIN
 #endif
 
-HardwareSerial Serial(USART1, TX1, RX1);
+HardwareSerial Serial1(USART1, TX1, RX1);
 
 #ifdef TX2
-HardwareSerial Serial1(USART2, TX2, RX2);
+HardwareSerial Serial2(USART2, TX2, RX2);
 #endif
 
 #ifdef TX3
-HardwareSerial Serial2(USART3, TX3, RX3);
+HardwareSerial Serial3(USART3, TX3, RX3);
 #endif
 
 #if defined(STM32_HIGH_DENSITY) && !defined(BOARD_maple_RET6)
-HardwareSerial Serial3(UART4,  TX4, RX4);
-HardwareSerial Serial4(UART5,  TX5, RX5);
+HardwareSerial Serial4(UART4,  TX4, RX4);
+HardwareSerial Serial5(UART5,  TX5, RX5);
 #endif
 
 HardwareSerial::HardwareSerial(usart_dev *usart_device,
@@ -90,25 +90,23 @@ void HardwareSerial::begin(uint32 baud) {
         return;
     }
 
-    const stm32_pin_info *txi = &PIN_MAP[tx_pin];
-    const stm32_pin_info *rxi = &PIN_MAP[rx_pin];
 #ifdef STM32F4
 	// int af = 7<<8;
     if (usart_device == UART4 || usart_device == UART5) {
-        gpio_set_af_mode(txi->gpio_device, txi->gpio_bit, 8);
-        gpio_set_af_mode(rxi->gpio_device, rxi->gpio_bit, 8);
+        gpio_set_af_mode(tx_pin, 8);
+        gpio_set_af_mode(rx_pin, 8);
     }
     else {
-        gpio_set_af_mode(txi->gpio_device, txi->gpio_bit, 7);
-        gpio_set_af_mode(rxi->gpio_device, rxi->gpio_bit, 7);
+        gpio_set_af_mode(tx_pin, 7);
+        gpio_set_af_mode(rx_pin, 7);
     }
-    gpio_set_mode(txi->gpio_device, txi->gpio_bit, (gpio_pin_mode)(GPIO_AF_OUTPUT_PP | GPIO_PUPD_INPUT_PU | 0x700));
-    gpio_set_mode(rxi->gpio_device, rxi->gpio_bit, (gpio_pin_mode)(GPIO_MODE_AF      | GPIO_PUPD_INPUT_PU | 0x700));
+    gpio_set_mode(tx_pin, (gpio_pin_mode)(GPIO_AF_OUTPUT_PP | GPIO_PUPD_INPUT_PU | 0x700));
+    gpio_set_mode(rx_pin, (gpio_pin_mode)(GPIO_MODE_AF      | GPIO_PUPD_INPUT_PU | 0x700));
     //gpio_set_mode(txi->gpio_device, txi->gpio_bit, (gpio_pin_mode)(GPIO_PUPD_INPUT_PU));
     //gpio_set_mode(rxi->gpio_device, rxi->gpio_bit, (gpio_pin_mode)(GPIO_PUPD_INPUT_PU));
 #else
-	gpio_set_mode(txi->gpio_device, txi->gpio_bit, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(rxi->gpio_device, rxi->gpio_bit, GPIO_INPUT_FLOATING);
+	gpio_set_mode(tx_pin, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(rx_pin, GPIO_INPUT_FLOATING);
 #endif
 #if 0
     if (txi->timer_device != NULL) {
diff --git a/STM32F4/cores/maple/libmaple/HardwareSerial.h b/STM32F4/cores/maple/libmaple/HardwareSerial.h
index c09fe54f1..d7e8a3d1f 100644
--- a/STM32F4/cores/maple/libmaple/HardwareSerial.h
+++ b/STM32F4/cores/maple/libmaple/HardwareSerial.h
@@ -75,12 +75,12 @@ class HardwareSerial : public Stream {
     uint8 rx_pin;
 };
 
-extern HardwareSerial Serial;
 extern HardwareSerial Serial1;
 extern HardwareSerial Serial2;
 #if defined(STM32_HIGH_DENSITY) && !defined(BOARD_maple_RET6)
 extern HardwareSerial Serial3;
 extern HardwareSerial Serial4;
+extern HardwareSerial Serial5;
 #endif
 extern HardwareSerial &SerialDebug;
 #endif
diff --git a/STM32F4/cores/maple/libmaple/dac.c b/STM32F4/cores/maple/libmaple/dac.c
index 264e4e21a..3853f903c 100644
--- a/STM32F4/cores/maple/libmaple/dac.c
+++ b/STM32F4/cores/maple/libmaple/dac.c
@@ -126,11 +126,11 @@ void dac_enable_channel(const dac_dev *dev, uint8 channel) {
      */
     switch (channel) {
     case 1:
-        gpio_set_mode(GPIOA, 4, GPIO_INPUT_ANALOG);
+        gpio_set_mode((uint8_t)PA4, GPIO_INPUT_ANALOG);
         dev->regs->CR |= DAC_CR_EN1;
         break;
     case 2:
-        gpio_set_mode(GPIOA, 5, GPIO_INPUT_ANALOG);
+        gpio_set_mode((uint8_t)PA5, GPIO_INPUT_ANALOG);
         dev->regs->CR |= DAC_CR_EN2;
         break;
     }
diff --git a/STM32F4/cores/maple/libmaple/fsmc.c b/STM32F4/cores/maple/libmaple/fsmc.c
index 06ca7df6a..42b0d77b4 100644
--- a/STM32F4/cores/maple/libmaple/fsmc.c
+++ b/STM32F4/cores/maple/libmaple/fsmc.c
@@ -39,27 +39,28 @@
  */
 void fsmc_sram_init_gpios(void) {
     /* Data lines... */
-    gpio_set_mode(GPIOD,  0, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOD,  1, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOD,  8, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOD,  9, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOD, 10, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOD, 14, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOD, 15, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE,  7, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE,  8, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE,  9, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE, 10, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE, 11, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE, 12, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE, 13, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE, 14, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE, 15, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD0, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD1, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD8, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD9, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD10, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD14, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD15, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE7, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE8, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE9, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE10, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE11, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE12, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE13, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE14, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE15, GPIO_AF_OUTPUT_PP);
 
     /* Address lines... */
-    gpio_set_mode(GPIOD, 11, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOD, 12, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOD, 13, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD11, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD12, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD13, GPIO_AF_OUTPUT_PP);
+#if 0 // not available on LQFP package
     gpio_set_mode(GPIOF,  0, GPIO_AF_OUTPUT_PP);
     gpio_set_mode(GPIOF,  1, GPIO_AF_OUTPUT_PP);
     gpio_set_mode(GPIOF,  2, GPIO_AF_OUTPUT_PP);
@@ -76,18 +77,20 @@ void fsmc_sram_init_gpios(void) {
     gpio_set_mode(GPIOG,  3, GPIO_AF_OUTPUT_PP);
     gpio_set_mode(GPIOG,  4, GPIO_AF_OUTPUT_PP);
     gpio_set_mode(GPIOG,  5, GPIO_AF_OUTPUT_PP);
-
+#endif  // not available on LQFP package
     /* And control lines... */
-    gpio_set_mode(GPIOD,  4, GPIO_AF_OUTPUT_PP);   // NOE
-    gpio_set_mode(GPIOD,  5, GPIO_AF_OUTPUT_PP);   // NWE
+    gpio_set_mode(PD4, GPIO_AF_OUTPUT_PP);   // NOE
+    gpio_set_mode(PD5, GPIO_AF_OUTPUT_PP);   // NWE
 
-    gpio_set_mode(GPIOD,  7, GPIO_AF_OUTPUT_PP);   // NE1
+    gpio_set_mode(PD7, GPIO_AF_OUTPUT_PP);   // NE1
+#if 0 // not available on LQFP package
     gpio_set_mode(GPIOG,  9, GPIO_AF_OUTPUT_PP);   // NE2
     gpio_set_mode(GPIOG, 10, GPIO_AF_OUTPUT_PP);   // NE3
     gpio_set_mode(GPIOG, 12, GPIO_AF_OUTPUT_PP);   // NE4
+#endif  // not available on LQFP package
 
-    gpio_set_mode(GPIOE,  0, GPIO_AF_OUTPUT_PP);   // NBL0
-    gpio_set_mode(GPIOE,  1, GPIO_AF_OUTPUT_PP);   // NBL1
+    gpio_set_mode(PE0, GPIO_AF_OUTPUT_PP);   // NBL0
+    gpio_set_mode(PE1, GPIO_AF_OUTPUT_PP);   // NBL1
 }
 
 #endif  /* STM32_HIGH_DENSITY */
diff --git a/STM32F4/cores/maple/libmaple/gpio.h b/STM32F4/cores/maple/libmaple/gpio.h
index f065c7190..4c0ba7100 100644
--- a/STM32F4/cores/maple/libmaple/gpio.h
+++ b/STM32F4/cores/maple/libmaple/gpio.h
@@ -31,5 +31,102 @@
  *         (AFIO) prototypes, defines, and inlined access functions.
  */
 
+#ifndef _GPIO_H_
+#define _GPIO_H_
+
+#include "libmaple.h"
+#include "boards.h"
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+
+/**
+ * @brief Get a GPIO port's corresponding afio_exti_port.
+ * @param dev GPIO device whose afio_exti_port to return.
+ */
+static inline afio_exti_port gpio_exti_port(gpio_dev *dev) {
+    return dev->exti_port;
+}
+
+/**
+ * Set or reset a GPIO pin.
+ *
+ * Pin must have previously been configured to output mode.
+ *
+ * @param dev GPIO device whose pin to set.
+ * @param pin Pin on to set or reset
+ * @param val If true, set the pin.  If false, reset the pin.
+ */
+static inline void gpio_write_pin(uint8_t pin, uint8 val) {
+    if (val) {
+        (PIN_MAP[pin].gpio_device)->regs->BSRRL = BIT(PIN_MAP[pin].gpio_bit);
+    } else {
+        (PIN_MAP[pin].gpio_device)->regs->BSRRH = BIT(PIN_MAP[pin].gpio_bit);
+    }
+}
+
+static inline void gpio_set_pin(uint8_t pin) {
+	(PIN_MAP[pin].gpio_device)->regs->BSRRL = BIT(PIN_MAP[pin].gpio_bit);
+}
+
+static inline void gpio_clear_pin(uint8_t pin) {
+	(PIN_MAP[pin].gpio_device)->regs->BSRRH = BIT(PIN_MAP[pin].gpio_bit);
+}
+
+/**
+ * Determine whether or not a GPIO pin is set.
+ *
+ * Pin must have previously been configured to input mode.
+ *
+ * @param dev GPIO device whose pin to test.
+ * @param pin Pin on dev to test.
+ * @return True if the pin is set, false otherwise.
+ */
+static inline uint32 gpio_read_pin(uint8_t pin) {
+    return (PIN_MAP[pin].gpio_device)->regs->IDR & BIT(PIN_MAP[pin].gpio_bit);
+}
+
+/**
+ * Toggle a pin configured as output push-pull.
+ * @param dev GPIO device.
+ * @param pin Pin on dev to toggle.
+ */
+static inline void gpio_toggle_pin(uint8_t pin) {
+    (PIN_MAP[pin].gpio_device)->regs->ODR = (PIN_MAP[pin].gpio_device)->regs->ODR ^ BIT(PIN_MAP[pin].gpio_bit);
+}
+
+/*
+ * GPIO Convenience routines
+ */
+
+extern void gpio_init(gpio_dev *dev);
+extern void gpio_init_all(void);
+extern void gpio_set_mode(uint8_t pin, gpio_pin_mode mode);
+extern void gpio_set_af_mode(uint8_t pin, int mode);
+
+/*
+ * AFIO convenience routines
+ */
+
+extern void afio_init(void);
+extern void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port);
+extern void afio_remap(afio_remap_peripheral p);
+
+/**
+ * @brief Enable or disable the JTAG and SW debug ports.
+ * @param config Desired debug port configuration
+ * @see afio_debug_cfg
+ */
+static inline void afio_cfg_debug_ports(afio_debug_cfg config) {
+    //__io uint32 *mapr = &AFIO_BASE->MAPR;
+    //*mapr = (*mapr & ~AFIO_MAPR_SWJ_CFG) | config;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
 
-#include "gpioF4.h"
diff --git a/STM32F4/cores/maple/libmaple/gpioF4.c b/STM32F4/cores/maple/libmaple/gpioF4.c
index ba166f538..0792e121d 100644
--- a/STM32F4/cores/maple/libmaple/gpioF4.c
+++ b/STM32F4/cores/maple/libmaple/gpioF4.c
@@ -24,7 +24,7 @@
  * SOFTWARE.
  *****************************************************************************/
 
- #ifdef STM32F4
+#ifdef STM32F4
  
 /**
  * @file gpio.c
@@ -79,6 +79,7 @@ gpio_dev gpioe = {
 /** GPIO port E device. */
 gpio_dev* const GPIOE = &gpioe;
 
+ #if 0 // not available on LQFP 100 package
 gpio_dev gpiof = {
     .regs      = GPIOF_BASE,
     .clk_id    = RCC_GPIOF,
@@ -94,6 +95,7 @@ gpio_dev gpiog = {
 };
 /** GPIO port G device. */
 gpio_dev* const GPIOG = &gpiog;
+ #endif // not available on LQFP 100 package
 #endif
 
 /*
@@ -122,9 +124,11 @@ void gpio_init_all(void) {
     gpio_init(GPIOD);
 
 #ifdef STM32_HIGH_DENSITY
-    gpio_init(GPIOE);
-    gpio_init(GPIOF);
-    gpio_init(GPIOG);
+	gpio_init(GPIOE);
+  #if 0 // not available on LQFP 100 package
+	gpio_init(GPIOF);
+	gpio_init(GPIOG);
+  #endif // not available on LQFP 100 package
 #endif
 
 #ifdef ARDUINO_STM32F4_NETDUINO2PLUS
@@ -148,8 +152,9 @@ void gpio_init_all(void) {
  * @param mode General purpose or alternate function mode to set the pin to.
  * @see gpio_pin_mode
  */
-void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode) {
-    gpio_reg_map *regs = dev->regs;
+void gpio_set_mode(uint8_t io_pin, gpio_pin_mode mode) {
+    gpio_reg_map *regs = (PIN_MAP[io_pin].gpio_device)->regs;
+	uint8_t pin = PIN_MAP[io_pin].gpio_bit;
 
 	//regs->AFR[pin/8] = (regs->AFR[pin/8] & ~(15 << (4*(pin&7)))) | (((mode >> 8) & 15) << (4*(pin&7)));
 	//gpio_set_af_mode(dev, pin, mode>>8);
@@ -168,10 +173,11 @@ void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode) {
  * @param mode alternate function mode to set the pin to.
  * @see gpio_pin_mode
  */
-void gpio_set_af_mode(gpio_dev *dev, uint8 pin, int mode) {
-    gpio_reg_map *regs = dev->regs;
+void gpio_set_af_mode(uint8_t io_pin, int mode) {
+    gpio_reg_map *regs = (PIN_MAP[io_pin].gpio_device)->regs;
+	uint8_t pin = PIN_MAP[io_pin].gpio_bit;
 
-	regs->AFR[pin/8] = (regs->AFR[pin/8] & ~(15 << (4*(pin&7)))) | (((mode >> 0) & 15) << (4*(pin&7)));
+	regs->AFR[pin>>3] = (regs->AFR[pin>>3] & ~(15 << (4*(pin&7)))) | (((mode >> 0) & 15) << (4*(pin&7)));
 }
 
 /*
diff --git a/STM32F4/cores/maple/libmaple/gpioF4.h b/STM32F4/cores/maple/libmaple/gpio_def.h
similarity index 91%
rename from STM32F4/cores/maple/libmaple/gpioF4.h
rename to STM32F4/cores/maple/libmaple/gpio_def.h
index 91bd67be3..8b9e693ea 100644
--- a/STM32F4/cores/maple/libmaple/gpioF4.h
+++ b/STM32F4/cores/maple/libmaple/gpio_def.h
@@ -31,11 +31,12 @@
  *         (AFIO) prototypes, defines, and inlined access functions.
  */
 
-#ifndef _GPIO_H_
-#define _GPIO_H_
+#ifndef _GPIO_DEF_H_
+#define _GPIO_DEF_H_
 
 #include "libmaple.h"
 #include "rcc.h"
+#include "wirish_types.h"
 
 #ifdef __cplusplus
 extern "C"{
@@ -74,11 +75,14 @@ typedef enum afio_exti_port {
     AFIO_EXTI_PD,               /**< Use port D (PDx) pin. */
 #ifdef STM32_HIGH_DENSITY
     AFIO_EXTI_PE,               /**< Use port E (PEx) pin. */
+ #if 0 // not available on LQFP 100 package
     AFIO_EXTI_PF,               /**< Use port F (PFx) pin. */
     AFIO_EXTI_PG,               /**< Use port G (PGx) pin. */
+ #endif // not available on LQFP 100 package
 #endif
 } afio_exti_port;
 
+
 /** GPIO device type */
 typedef struct gpio_dev {
     gpio_reg_map *regs;       /**< Register map */
@@ -97,10 +101,12 @@ extern gpio_dev* const GPIOD;
 #ifdef STM32_HIGH_DENSITY
 extern gpio_dev gpioe;
 extern gpio_dev* const GPIOE;
+ #if 0 // not available on LQFP 100 package
 extern gpio_dev gpiof;
 extern gpio_dev* const GPIOF;
 extern gpio_dev gpiog;
 extern gpio_dev* const GPIOG;
+ #endif // not available on LQFP 100 package
 #endif
 
 /** GPIO port register map base pointer */
@@ -110,8 +116,10 @@ extern gpio_dev* const GPIOG;
 #define GPIOD_BASE                      ((struct gpio_reg_map*)0x40020C00)
 #ifdef STM32_HIGH_DENSITY
 #define GPIOE_BASE                      ((struct gpio_reg_map*)0x40021000)
+ #if 0 // not available on LQFP 100 package
 #define GPIOF_BASE                      ((struct gpio_reg_map*)0x40021400)
 #define GPIOG_BASE                      ((struct gpio_reg_map*)0x40021800)
+ #endif // not available on LQFP 100 package
 #endif
 
 /*
@@ -190,61 +198,6 @@ typedef enum gpio_pin_mode {
 	GPIO_BIGNUMBER = 0xfff
 } gpio_pin_mode;
 
-/*
- * GPIO Convenience routines
- */
-
-void gpio_init(gpio_dev *dev);
-void gpio_init_all(void);
-void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode);
-void gpio_set_af_mode(gpio_dev *dev, uint8 pin, int mode);
-
-/**
- * @brief Get a GPIO port's corresponding afio_exti_port.
- * @param dev GPIO device whose afio_exti_port to return.
- */
-static inline afio_exti_port gpio_exti_port(gpio_dev *dev) {
-    return dev->exti_port;
-}
-
-/**
- * Set or reset a GPIO pin.
- *
- * Pin must have previously been configured to output mode.
- *
- * @param dev GPIO device whose pin to set.
- * @param pin Pin on to set or reset
- * @param val If true, set the pin.  If false, reset the pin.
- */
-static inline void gpio_write_bit(gpio_dev *dev, uint8 pin, uint8 val) {
-    if (val) {
-        dev->regs->BSRRL = BIT(pin);
-    } else {
-        dev->regs->BSRRH = BIT(pin);
-    }
-}
-
-/**
- * Determine whether or not a GPIO pin is set.
- *
- * Pin must have previously been configured to input mode.
- *
- * @param dev GPIO device whose pin to test.
- * @param pin Pin on dev to test.
- * @return True if the pin is set, false otherwise.
- */
-static inline uint32 gpio_read_bit(gpio_dev *dev, uint8 pin) {
-    return dev->regs->IDR & BIT(pin);
-}
-
-/**
- * Toggle a pin configured as output push-pull.
- * @param dev GPIO device.
- * @param pin Pin on dev to toggle.
- */
-static inline void gpio_toggle_bit(gpio_dev *dev, uint8 pin) {
-    dev->regs->ODR = dev->regs->ODR ^ BIT(pin);
-}
 
 /*
  * AFIO register map
@@ -532,15 +485,6 @@ typedef enum afio_debug_cfg {
                                    for use as GPIOs. */
 } afio_debug_cfg;
 
-/**
- * @brief Enable or disable the JTAG and SW debug ports.
- * @param config Desired debug port configuration
- * @see afio_debug_cfg
- */
-static inline void afio_cfg_debug_ports(afio_debug_cfg config) {
-    //__io uint32 *mapr = &AFIO_BASE->MAPR;
-    //*mapr = (*mapr & ~AFIO_MAPR_SWJ_CFG) | config;
-}
 
 #ifdef __cplusplus
 }
diff --git a/STM32F4/cores/maple/libmaple/i2c.c b/STM32F4/cores/maple/libmaple/i2c.c
index e3f3199bc..a582ed056 100644
--- a/STM32F4/cores/maple/libmaple/i2c.c
+++ b/STM32F4/cores/maple/libmaple/i2c.c
@@ -41,9 +41,9 @@
 
 static i2c_dev i2c_dev1 = {
     .regs         = I2C1_BASE,
-    .gpio_port    = &gpiob,
-    .sda_pin      = 7,
-    .scl_pin      = 6,
+    //.gpio_port    = &gpiob,
+    .sda_pin      = PB7,
+    .scl_pin      = PB6,
     .clk_id       = RCC_I2C1,
     .ev_nvic_line = NVIC_I2C1_EV,
     .er_nvic_line = NVIC_I2C1_ER,
@@ -54,9 +54,9 @@ i2c_dev* const I2C1 = &i2c_dev1;
 
 static i2c_dev i2c_dev2 = {
     .regs         = I2C2_BASE,
-    .gpio_port    = &gpiob,
-    .sda_pin      = 11,
-    .scl_pin      = 10,
+    //.gpio_port    = &gpiob,
+    .sda_pin      = PB11,
+    .scl_pin      = PB10,
     .clk_id       = RCC_I2C2,
     .ev_nvic_line = NVIC_I2C2_EV,
     .er_nvic_line = NVIC_I2C2_ER,
@@ -336,38 +336,38 @@ void __irq_i2c2_er(void) {
  */
 void i2c_bus_reset(const i2c_dev *dev) {
     /* Release both lines */
-    gpio_write_bit(dev->gpio_port, dev->scl_pin, 1);
-    gpio_write_bit(dev->gpio_port, dev->sda_pin, 1);
-    gpio_set_mode(dev->gpio_port, dev->scl_pin, GPIO_OUTPUT_OD);
-    gpio_set_mode(dev->gpio_port, dev->sda_pin, GPIO_OUTPUT_OD);
+    gpio_set_pin(dev->scl_pin);
+    gpio_set_pin(dev->sda_pin);
+    gpio_set_mode(dev->scl_pin, GPIO_OUTPUT_OD);
+    gpio_set_mode(dev->sda_pin, GPIO_OUTPUT_OD);
 
     /*
      * Make sure the bus is free by clocking it until any slaves release the
      * bus.
      */
-    while (!gpio_read_bit(dev->gpio_port, dev->sda_pin)) {
+    while (!gpio_read_pin(dev->sda_pin)) {
         /* Wait for any clock stretching to finish */
-        while (!gpio_read_bit(dev->gpio_port, dev->scl_pin))
+        while (!gpio_read_pin(dev->scl_pin))
             ;
         delay_us(10);
 
         /* Pull low */
-        gpio_write_bit(dev->gpio_port, dev->scl_pin, 0);
+        gpio_clear_pin(dev->scl_pin);
         delay_us(10);
 
         /* Release high again */
-        gpio_write_bit(dev->gpio_port, dev->scl_pin, 1);
+        gpio_set_pin(dev->scl_pin);
         delay_us(10);
     }
 
     /* Generate start then stop condition */
-    gpio_write_bit(dev->gpio_port, dev->sda_pin, 0);
+    gpio_clear_pin(dev->sda_pin);
     delay_us(10);
-    gpio_write_bit(dev->gpio_port, dev->scl_pin, 0);
+    gpio_clear_pin(dev->scl_pin);
     delay_us(10);
-    gpio_write_bit(dev->gpio_port, dev->scl_pin, 1);
+    gpio_set_pin(dev->scl_pin);
     delay_us(10);
-    gpio_write_bit(dev->gpio_port, dev->sda_pin, 1);
+    gpio_set_pin(dev->sda_pin);
 }
 
 /**
@@ -413,8 +413,8 @@ void i2c_master_enable(i2c_dev *dev, uint32 flags) {
 
     /* Turn on clock and set GPIO modes */
     i2c_init(dev);
-    gpio_set_mode(dev->gpio_port, dev->sda_pin, GPIO_AF_OUTPUT_OD);
-    gpio_set_mode(dev->gpio_port, dev->scl_pin, GPIO_AF_OUTPUT_OD);
+    gpio_set_mode(dev->sda_pin, GPIO_AF_OUTPUT_OD);
+    gpio_set_mode(dev->scl_pin, GPIO_AF_OUTPUT_OD);
 
     /* I2C1 and I2C2 are fed from APB1, clocked at 36MHz */
     i2c_set_input_clk(dev, I2C_CLK);
diff --git a/STM32F4/cores/maple/libmaple/i2c.h b/STM32F4/cores/maple/libmaple/i2c.h
index 4c60ad713..28819a35b 100644
--- a/STM32F4/cores/maple/libmaple/i2c.h
+++ b/STM32F4/cores/maple/libmaple/i2c.h
@@ -78,7 +78,7 @@ typedef struct i2c_msg {
  */
 typedef struct i2c_dev {
     i2c_reg_map *regs;          /**< Register map */
-    gpio_dev *gpio_port;        /**< SDA, SCL pins' GPIO port */
+    //gpio_dev *gpio_port;        /**< SDA, SCL pins' GPIO port */
     uint8 sda_pin;              /**< SDA bit on gpio_port */
     uint8 scl_pin;              /**< SCL bit on gpio_port */
     rcc_clk_id clk_id;          /**< RCC clock information */
diff --git a/STM32F4/cores/maple/libmaple/libmaple_types.h b/STM32F4/cores/maple/libmaple/libmaple_types.h
index e20e3274f..d2e8673a1 100644
--- a/STM32F4/cores/maple/libmaple/libmaple_types.h
+++ b/STM32F4/cores/maple/libmaple/libmaple_types.h
@@ -33,6 +33,9 @@
 #ifndef _LIBMAPLE_TYPES_H_
 #define _LIBMAPLE_TYPES_H_
 
+#include <inttypes.h>
+#include <stdbool.h>
+
 typedef unsigned char uint8;
 typedef unsigned short uint16;
 typedef unsigned int uint32;
diff --git a/STM32F4/cores/maple/libmaple/rccF4.c b/STM32F4/cores/maple/libmaple/rccF4.c
index dd2ea2648..c4ff30dc4 100644
--- a/STM32F4/cores/maple/libmaple/rccF4.c
+++ b/STM32F4/cores/maple/libmaple/rccF4.c
@@ -166,7 +166,6 @@ typedef struct
 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
 #define RESET 0
 
-typedef uint32 uint32_t;
 
 void InitMCO1()
 {
@@ -175,8 +174,8 @@ void InitMCO1()
     RCC->CFGR &= RCC_CFGR_MCO1_RESET_MASK;
     RCC->CFGR |= RCC_CFGR_MCO1Source_HSE | RCC_CFGR_MCO1Div_1;
     // PA8 Output the Master Clock MCO1
-    gpio_set_af_mode(GPIOA, 8, 0);
-    gpio_set_mode(GPIOA, 8, GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
+    gpio_set_af_mode(PA8, 0);
+    gpio_set_mode(PA8, GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
 }
 
 
diff --git a/STM32F4/cores/maple/libmaple/spi.h b/STM32F4/cores/maple/libmaple/spi.h
index 88739c584..043635289 100644
--- a/STM32F4/cores/maple/libmaple/spi.h
+++ b/STM32F4/cores/maple/libmaple/spi.h
@@ -230,14 +230,10 @@ struct gpio_dev;
  */
 extern void spi_config_gpios(spi_dev *dev,
                              uint8 as_master,
-                             struct gpio_dev *nss_dev,
-                             uint8 nss_bit,
-                             struct gpio_dev *sck_dev,
-                             uint8 sck_bit,
-                             struct gpio_dev *miso_dev,
-                             uint8 miso_bit,
-                             struct gpio_dev *mosi_dev,
-                             uint8 mosi_bit);
+                             uint8 nss_pin,
+                             uint8 sck_pin,
+                             uint8 miso_pin,
+                             uint8 mosi_pin);
 
 /**
  * @brief SPI mode configuration.
diff --git a/STM32F4/cores/maple/libmaple/spiF4.h b/STM32F4/cores/maple/libmaple/spiF4.h
index 3f5116442..d2ae557fe 100644
--- a/STM32F4/cores/maple/libmaple/spiF4.h
+++ b/STM32F4/cores/maple/libmaple/spiF4.h
@@ -62,17 +62,6 @@ extern struct spi_dev *SPI2;
 extern struct spi_dev *SPI3;
 #endif
 
-/*
- * Routines
- */
-
-/* spi_gpio_cfg(): Backwards compatibility shim to spi_config_gpios() */
-struct gpio_dev;
-extern void spi_config_gpios(struct spi_dev*, uint8,
-                             struct gpio_dev*, uint8,
-                             struct gpio_dev*, uint8, 
-                             struct gpio_dev*, uint8, 
-                             struct gpio_dev*, uint8); 
 
 #ifdef __cplusplus
 }
diff --git a/STM32F4/cores/maple/libmaple/spi_f4.c b/STM32F4/cores/maple/libmaple/spi_f4.c
index b9beb68d2..43f5092c6 100644
--- a/STM32F4/cores/maple/libmaple/spi_f4.c
+++ b/STM32F4/cores/maple/libmaple/spi_f4.c
@@ -56,25 +56,21 @@ spi_dev *SPI3 = &spi3;
 
 void spi_config_gpios(spi_dev *ignored,
                       uint8 as_master,
-                      gpio_dev *nss_dev,
-                      uint8 nss_bit,
-                      gpio_dev *sck_dev,
-                      uint8 sck_bit,
-                      gpio_dev *miso_dev,
-                      uint8 miso_bit,
-                      gpio_dev *mosi_dev,
-                      uint8 mosi_bit) {
+                      uint8 nss_pin,
+                      uint8 sck_pin,
+                      uint8 miso_pin,
+                      uint8 mosi_pin) {
     if (as_master) {
 //        gpio_set_mode(nss_dev, nss_bit, GPIO_AF_OUTPUT_PP);
-        gpio_set_mode(sck_dev, sck_bit, GPIO_AF_OUTPUT_PP);
+        gpio_set_mode(sck_pin, GPIO_AF_OUTPUT_PP);
 //        gpio_set_mode(comm_dev, miso_bit, GPIO_INPUT_FLOATING);
-        gpio_set_mode(miso_dev, miso_bit, GPIO_AF_INPUT_PD);		
-        gpio_set_mode(mosi_dev, mosi_bit, GPIO_AF_OUTPUT_PP);
+        gpio_set_mode(miso_pin, GPIO_AF_INPUT_PD);		
+        gpio_set_mode(mosi_pin, GPIO_AF_OUTPUT_PP);
     } else {
-        gpio_set_mode(nss_dev, nss_bit, GPIO_INPUT_FLOATING);
-        gpio_set_mode(sck_dev, sck_bit, GPIO_INPUT_FLOATING);
-        gpio_set_mode(miso_dev, miso_bit, GPIO_AF_OUTPUT_PP);
-        gpio_set_mode(mosi_dev, mosi_bit, GPIO_INPUT_FLOATING);
+        gpio_set_mode(nss_pin, GPIO_INPUT_FLOATING);
+        gpio_set_mode(sck_pin, GPIO_INPUT_FLOATING);
+        gpio_set_mode(miso_pin, GPIO_AF_OUTPUT_PP);
+        gpio_set_mode(mosi_pin, GPIO_INPUT_FLOATING);
     }
 }
 
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_bsp.c b/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_bsp.c
index df23ccbd7..c402bbdfe 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_bsp.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_bsp.c
@@ -97,10 +97,10 @@ void USB_OTG_BSP_Init(USB_OTG_CORE_HANDLE *pdev)
 {
 	// ala42
 #define GPIO_AF_OTG1_FS         ((uint8_t)0xA)  /* OTG_FS Alternate Function mapping */
-	gpio_set_mode(GPIOA,11,GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
-	gpio_set_mode(GPIOA,12,GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
-	gpio_set_af_mode(GPIOA,11,GPIO_AF_OTG1_FS) ;	// OTG_FS_DM
-	gpio_set_af_mode(GPIOA,12,GPIO_AF_OTG1_FS) ;	// OTG_FS_DP
+	gpio_set_mode(BOARD_USB_DM_PIN,GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
+	gpio_set_mode(BOARD_USB_DP_PIN,GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
+	gpio_set_af_mode(BOARD_USB_DM_PIN,GPIO_AF_OTG1_FS) ;	// OTG_FS_DM
+	gpio_set_af_mode(BOARD_USB_DP_PIN,GPIO_AF_OTG1_FS) ;	// OTG_FS_DP
 #ifdef USB_OTG_FS_SOF_OUTPUT_ENABLED
 	gpio_set_mode(GPIOA, 8,GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
 	gpio_set_af_mode(GPIOA, 8,GPIO_AF_OTG1_FS) ;		// OTG_FS_SOF
@@ -122,10 +122,10 @@ void USB_OTG_BSP_DeInit(USB_OTG_CORE_HANDLE *pdev)
 {
 	// ala42
 #define GPIO_AF0         ((uint8_t)0)  /* OTG_FS Alternate Function mapping */
-	gpio_set_mode(GPIOA,11, GPIO_MODE_INPUT);
-	gpio_set_mode(GPIOA,12, GPIO_MODE_INPUT);
-	gpio_set_af_mode(GPIOA,11,GPIO_AF0) ;	// OTG_FS_DM
-	gpio_set_af_mode(GPIOA,12,GPIO_AF0) ;	// OTG_FS_DP
+	gpio_set_mode(BOARD_USB_DM_PIN, GPIO_MODE_INPUT);
+	gpio_set_mode(BOARD_USB_DP_PIN, GPIO_MODE_INPUT);
+	gpio_set_af_mode(BOARD_USB_DM_PIN,GPIO_AF0) ;	// OTG_FS_DM
+	gpio_set_af_mode(BOARD_USB_DP_PIN,GPIO_AF0) ;	// OTG_FS_DP
 #ifdef USB_OTG_FS_SOF_OUTPUT_ENABLED
 	gpio_set_mode(GPIOA, 8,GPIO_MODE_INPUT);
 	gpio_set_af_mode(GPIOA, 8,GPIO_AF0) ;		// OTG_FS_SOF
diff --git a/STM32F4/cores/maple/libmaple/usbF4/usb.c b/STM32F4/cores/maple/libmaple/usbF4/usb.c
index c013f04de..49ddc062f 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/usb.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/usb.c
@@ -5,23 +5,22 @@
 #include <gpio.h>
 #include <rccF4.h>
 #include <usbd_cdc_vcp.h>
+#include <boards.h>
 
 USB_OTG_CORE_HANDLE  USB_OTG_dev;
 
 
 
-void setupUSB (void) {
-    #define USB_DISC_DEV         GPIOA
-    #define USB_DISC_PIN         12
-
-	gpio_set_mode(USB_DISC_DEV, USB_DISC_PIN, GPIO_OUTPUT_OD); // ala42
+void setupUSB (void)
+{
+	gpio_set_mode(BOARD_USB_DP_PIN, GPIO_OUTPUT_OD); // ala42
 #ifdef USB_DISC_OD
   //gpio_set_mode(USB_DISC_DEV, USB_DISC_PIN, GPIO_OUTPUT_OD); // ala42
 #else
   //gpio_set_mode(USB_DISC_DEV, USB_DISC_PIN, GPIO_OUTPUT_PP); // ala42 for active pull-up on disconnect pin
 #endif
 
-  gpio_write_bit(USB_DISC_DEV, USB_DISC_PIN,0); // ala42
+  gpio_clear_pin(BOARD_USB_DP_PIN); // ala42
   delay_us(200000);
 
   /* setup the apb1 clock for USB */
@@ -29,7 +28,7 @@ void setupUSB (void) {
   //pRCC->APB1ENR |= RCC_APB1ENR_USBEN;
 
   /* initialize the usb application */
-  gpio_write_bit(USB_DISC_DEV, USB_DISC_PIN, 1); // ala42 // presents us to the host
+  gpio_set_pin(BOARD_USB_DP_PIN); // ala42 // presents us to the host
   USBD_Init(&USB_OTG_dev,
             USB_OTG_FS_CORE_ID,
             &USR_desc,
diff --git a/STM32F4/cores/maple/libmaple/util.c b/STM32F4/cores/maple/libmaple/util.c
index 8c03e1865..8a745e87d 100644
--- a/STM32F4/cores/maple/libmaple/util.c
+++ b/STM32F4/cores/maple/libmaple/util.c
@@ -128,7 +128,7 @@ void throb(void) {
     uint32 TOP_CNT = 0x0800;
     uint32 i       = 0;
 
-    gpio_set_mode(ERROR_LED_PORT, ERROR_LED_PIN, GPIO_OUTPUT_PP);
+    gpio_set_mode(ERROR_LED_PIN, GPIO_OUTPUT_PP);
     /* Error fade. */
     while (1) {
         if (CC == TOP_CNT)  {
@@ -143,9 +143,9 @@ void throb(void) {
         }
 
         if (i < CC) {
-            gpio_write_bit(ERROR_LED_PORT, ERROR_LED_PIN, 1);
+            gpio_set_pin(ERROR_LED_PIN);
         } else {
-            gpio_write_bit(ERROR_LED_PORT, ERROR_LED_PIN, 0);
+            gpio_clear_pin(ERROR_LED_PIN);
         }
         i++;
     }
diff --git a/STM32F4/cores/maple/usb_serial.cpp b/STM32F4/cores/maple/usb_serial.cpp
index cc726c2e2..cfeb382ea 100644
--- a/STM32F4/cores/maple/usb_serial.cpp
+++ b/STM32F4/cores/maple/usb_serial.cpp
@@ -33,6 +33,8 @@
 #include "wirish.h"
 #include "usb.h"
 
+#ifdef SERIAL_USB
+
 #define USB_TIMEOUT 50
 
 USBSerial::USBSerial(void) {
@@ -153,3 +155,5 @@ void USBSerial::disableBlockingTx(void) {
 }
 
 USBSerial SerialUSB;
+
+#endif
diff --git a/STM32F4/cores/maple/usb_serial.h b/STM32F4/cores/maple/usb_serial.h
index a551e9d4b..301dc4baf 100644
--- a/STM32F4/cores/maple/usb_serial.h
+++ b/STM32F4/cores/maple/usb_serial.h
@@ -33,6 +33,8 @@
 
 #include "Stream.h"
 
+#ifdef SERIAL_USB
+
 /**
  * @brief Virtual serial terminal.
  */
@@ -68,3 +70,6 @@ extern USBSerial SerialUSB;
 
 #endif
 
+
+#endif
+
diff --git a/STM32F4/cores/maple/wirish.h b/STM32F4/cores/maple/wirish.h
index a9068e7a7..7e94fb3a7 100644
--- a/STM32F4/cores/maple/wirish.h
+++ b/STM32F4/cores/maple/wirish.h
@@ -54,8 +54,8 @@
 #define HIGH 0x1
 #define LOW  0x0
 
-#define true 0x1
-#define false 0x0
+//#define true 0x1
+//#define false 0x0
 
 
 #define lowByte(w)                     ((w) & 0xFF)
diff --git a/STM32F4/cores/maple/wirish_digital.cpp b/STM32F4/cores/maple/wirish_digital.cpp
index da180dcb4..4a656199b 100644
--- a/STM32F4/cores/maple/wirish_digital.cpp
+++ b/STM32F4/cores/maple/wirish_digital.cpp
@@ -72,7 +72,7 @@ void pinMode(uint8 pin, WiringPinMode mode) {
         return;
     }
 
-    gpio_set_mode(PIN_MAP[pin].gpio_device, PIN_MAP[pin].gpio_bit, outputMode);
+    gpio_set_mode(pin, outputMode);
 
     if (PIN_MAP[pin].timer_device != NULL) {
         /* Enable/disable timer channels if we're switching into or
@@ -84,29 +84,32 @@ void pinMode(uint8 pin, WiringPinMode mode) {
 }
 
 
-uint32 digitalRead(uint8 pin) {
+uint32 digitalRead(uint8 pin)
+{
     if (pin >= BOARD_NR_GPIO_PINS) {
         return 0;
     }
 
-    return gpio_read_bit(PIN_MAP[pin].gpio_device, PIN_MAP[pin].gpio_bit) ?
+    return gpio_read_pin(pin) ?
         HIGH : LOW;
 }
 
-void digitalWrite(uint8 pin, uint8 val) {
+void digitalWrite(uint8 pin, uint8 val)
+{
     if (pin >= BOARD_NR_GPIO_PINS) {
         return;
     }
 
-    gpio_write_bit(PIN_MAP[pin].gpio_device, PIN_MAP[pin].gpio_bit, val);
+    gpio_write_pin(pin, val);
 }
 
-void togglePin(uint8 pin) {
+void togglePin(uint8 pin)
+{
     if (pin >= BOARD_NR_GPIO_PINS) {
         return;
     }
 
-    gpio_toggle_bit(PIN_MAP[pin].gpio_device, PIN_MAP[pin].gpio_bit);
+    gpio_toggle_pin(pin);
 }
 
 #define BUTTON_DEBOUNCE_DELAY 1
diff --git a/STM32F4/cores/maple/wirish_types.h b/STM32F4/cores/maple/wirish_types.h
index 55364ab45..95e524fee 100644
--- a/STM32F4/cores/maple/wirish_types.h
+++ b/STM32F4/cores/maple/wirish_types.h
@@ -30,14 +30,14 @@
  * @brief  Wirish library type definitions.
  */
 
+#ifndef _WIRISH_TYPES_H_
+#define _WIRISH_TYPES_H_
+
 #include "libmaple_types.h"
-#include "gpio.h"
+#include "gpio_def.h"
 #include "timer.h"
 #include "adc.h"
 
-#ifndef _WIRISH_TYPES_H_
-#define _WIRISH_TYPES_H_
-
 /**
  * Invalid stm32_pin_info adc_channel value.
  * @see stm32_pin_info
@@ -73,6 +73,7 @@ typedef struct stm32_pin_info {
 } stm32_pin_info;
 
 #endif
+
 /**
  * Variable attribute, instructs the linker to place the marked
  * variable in Flash instead of RAM. */
diff --git a/STM32F4/platform.txt b/STM32F4/platform.txt
index b32f283dc..5bfa22efe 100755
--- a/STM32F4/platform.txt
+++ b/STM32F4/platform.txt
@@ -64,7 +64,7 @@ compiler.libs.c.flags=-I{build.core.path} -I{build.core.path}/libmaple -I{build.
 # ---------------------
 
 ## Compile c files
-recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.c.flags} -mcpu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.c.extra_flags} {build.extra_flags} {compiler.libs.c.flags} {includes} "{source_file}" -o "{object_file}"
+recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.c.flags} -mcpu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.c.extra_flags} {build.extra_flags} {build.cpu_flags} {compiler.libs.c.flags} {includes} "{source_file}" -o "{object_file}"
 
 ## Compile c++ files
 recipe.cpp.o.pattern="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.flags} -mcpu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {build.cpu_flags} {build.hs_flag} {build.common_flags} {compiler.libs.c.flags} {includes} "{source_file}" -o "{object_file}"
diff --git a/STM32F4/variants/generic_f407v/generic_f407v.h b/STM32F4/variants/generic_f407v/generic_f407v.h
index 15e93e457..b9f034847 100644
--- a/STM32F4/variants/generic_f407v/generic_f407v.h
+++ b/STM32F4/variants/generic_f407v/generic_f407v.h
@@ -124,7 +124,7 @@ PE0,PE1,PE2,PE3,PE4,PE5,PE6,PE7,PE8,PE9,PE10,PE11,PE12,PE13,PE14,PE15,
 #if 0 // not available on LQFP100 package
 PF0,PF1,PF2,PF3,PF4,PF5,PF6,PF7,PF8,PF9,PF10,PF11,PF12,PF13,PF14,PF15,
 PG0,PG1,PG2,PG3,PG4,PG5,PG6,PG7,PG8,PG9,PG10,PG11,PG12,PG13,PG14,PG15
-#endif
+#endif // not available on LQFP100 package
 };
 
 #endif
diff --git a/STM32F4/variants/generic_f407v/ld/jtag.ld b/STM32F4/variants/generic_f407v/ld/jtag.ld
index fe70f68dc..1001db518 100644
--- a/STM32F4/variants/generic_f407v/ld/jtag.ld
+++ b/STM32F4/variants/generic_f407v/ld/jtag.ld
@@ -5,7 +5,7 @@
 
 MEMORY
 {
-  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
   rom (rx)  : ORIGIN = 0x08000000, LENGTH = 512K
 }
 

From 1d29d139677eb2b843deee4bea9183dad4c330b6 Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Thu, 27 Apr 2017 18:22:18 +0200
Subject: [PATCH 056/307] The ssd1306_128x64_i2c_STM32 example would not build
 because of a missing swap() macro.

---
 STM32F1/libraries/Adafruit_SSD1306/Adafruit_SSD1306_STM32.cpp | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/STM32F1/libraries/Adafruit_SSD1306/Adafruit_SSD1306_STM32.cpp b/STM32F1/libraries/Adafruit_SSD1306/Adafruit_SSD1306_STM32.cpp
index c0c24a048..349203915 100644
--- a/STM32F1/libraries/Adafruit_SSD1306/Adafruit_SSD1306_STM32.cpp
+++ b/STM32F1/libraries/Adafruit_SSD1306/Adafruit_SSD1306_STM32.cpp
@@ -29,6 +29,10 @@ HardWire HWIRE(2,I2C_FAST_MODE); // I2c2
 #include "Adafruit_GFX.h"
 #include "Adafruit_SSD1306_STM32.h"
 
+#ifndef swap
+#define swap(a, b) { int16_t t = a; a = b; b = t; }
+#endif
+
 // the memory buffer for the LCD
 
 static uint8_t buffer[SSD1306_LCDHEIGHT * SSD1306_LCDWIDTH / 8] = { 

From 9dbcefdec34bb4e1038021dbc2a01ed20c23e509 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Wed, 3 May 2017 18:27:39 +0200
Subject: [PATCH 057/307] bugfix to include external libraries: reworked
 include paths + moved Arduino.h + updated SPI lib

---
 STM32F4/cores/maple/Arduino.h                 |   6 -
 STM32F4/cores/maple/Client.h                  |   5 +-
 STM32F4/cores/maple/HardwareTimer.h           |   2 +-
 STM32F4/cores/maple/IPAddress.h               |   4 +-
 STM32F4/cores/maple/Server.h                  |   4 +-
 STM32F4/cores/maple/Stream.h                  |   4 +-
 STM32F4/cores/maple/Udp.h                     |   4 +-
 STM32F4/cores/maple/WProgram.h                |   7 +-
 STM32F4/cores/maple/WString.h                 |   7 +-
 STM32F4/cores/maple/bits.h                    |   5 +
 STM32F4/cores/maple/boards.cpp                |  14 +-
 STM32F4/cores/maple/boards.h                  |  14 +-
 STM32F4/cores/maple/ext_interrupts.cpp        |   4 +-
 STM32F4/cores/maple/ext_interrupts.h          |   9 +-
 STM32F4/cores/maple/io.h                      |   4 +-
 STM32F4/cores/maple/itoa.h                    |   4 +-
 STM32F4/cores/maple/libmaple/gpioF4.c         |  10 +-
 STM32F4/cores/maple/libmaple/gpio_def.h       |   1 -
 STM32F4/cores/maple/libmaple/libmaple.h       |   3 -
 STM32F4/cores/maple/libmaple/libmaple_types.h |   2 +-
 STM32F4/cores/maple/libmaple/spi.c            |  39 +-
 STM32F4/cores/maple/libmaple/spi.h            |   6 +-
 STM32F4/cores/maple/libmaple/spiF4.h          |   4 +-
 .../Class/audio/inc/usbd_audio_core.h         |   2 +-
 .../Class/cdc/inc/usbd_cdc_core.h             |   3 +-
 .../Class/cdc/src/usbd_cdc_core.c             |   7 +-
 .../Core/inc/usbd_core.h                      |   4 +-
 .../Core/inc/usbd_def.h                       |   2 +-
 .../Core/inc/usbd_req.h                       |   2 +-
 .../Core/src/usbd_core.c                      |  10 +-
 .../Core/src/usbd_ioreq.c                     |   2 +-
 .../Core/src/usbd_req.c                       |   6 +-
 .../usbF4/STM32_USB_OTG_Driver/inc/usb_core.h |   2 +-
 .../STM32_USB_OTG_Driver/inc/usb_defines.h    |   2 +-
 .../usbF4/STM32_USB_OTG_Driver/inc/usb_otg.h  |   1 +
 .../usbF4/STM32_USB_OTG_Driver/inc/usb_regs.h |   4 +-
 .../usbF4/STM32_USB_OTG_Driver/src/usb_core.c |   4 +-
 .../usbF4/STM32_USB_OTG_Driver/src/usb_dcd.c  |   4 +-
 .../STM32_USB_OTG_Driver/src/usb_dcd_int.c    |   4 +-
 .../cores/maple/libmaple/usbF4/VCP/core_cm4.h |   2 +-
 STM32F4/cores/maple/libmaple/usbF4/VCP/misc.c |   2 +-
 .../cores/maple/libmaple/usbF4/VCP/usb_bsp.c  |   6 +-
 .../maple/libmaple/usbF4/VCP/usbd_cdc_vcp.h   |   2 +-
 .../maple/libmaple/usbF4/VCP/usbd_conf.h      |   1 +
 .../maple/libmaple/usbF4/VCP/usbd_desc.c      |   6 +-
 .../maple/libmaple/usbF4/VCP/usbd_desc.h      |   2 +-
 .../cores/maple/libmaple/usbF4/VCP/usbd_usr.c |   4 +-
 STM32F4/cores/maple/libmaple/usbF4/usb.c      |  20 +-
 STM32F4/cores/maple/libmaple/usbF4/usb.h      |   2 +-
 STM32F4/cores/maple/libmaple/util.h           |   5 +-
 STM32F4/cores/maple/pwm.cpp                   |   4 +-
 STM32F4/cores/maple/wirish.h                  |  13 +-
 STM32F4/cores/maple/wirish_constants.h        |   4 +-
 STM32F4/cores/maple/wirish_debug.h            |   7 +-
 STM32F4/cores/maple/wirish_math.h             |   4 +-
 STM32F4/cores/maple/wirish_time.cpp           |   6 +-
 STM32F4/cores/maple/wirish_time.h             |   5 +-
 STM32F4/cores/maple/wirish_types.h            |   7 +-
 STM32F4/libraries/SPI/library.properties      |   1 +
 STM32F4/libraries/SPI/src/SPI.cpp             | 452 +++++++++---------
 STM32F4/libraries/SPI/src/SPI.h               | 138 ++++--
 STM32F4/platform.txt                          |  12 +-
 STM32F4/system/libmaple/Arduino.h             |  46 ++
 .../variants/generic_f407v/generic_f407v.cpp  |  37 +-
 .../variants/generic_f407v/generic_f407v.h    |  41 +-
 65 files changed, 578 insertions(+), 472 deletions(-)
 delete mode 100644 STM32F4/cores/maple/Arduino.h
 create mode 100644 STM32F4/system/libmaple/Arduino.h

diff --git a/STM32F4/cores/maple/Arduino.h b/STM32F4/cores/maple/Arduino.h
deleted file mode 100644
index d02a50cba..000000000
--- a/STM32F4/cores/maple/Arduino.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef Arduino_h
-#define Arduino_h
-#include "WProgram.h"
-#endif
-
-#include "variant.h"
diff --git a/STM32F4/cores/maple/Client.h b/STM32F4/cores/maple/Client.h
index b8e5d935f..57bedb8e0 100644
--- a/STM32F4/cores/maple/Client.h
+++ b/STM32F4/cores/maple/Client.h
@@ -17,8 +17,9 @@
   Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 
-#ifndef client_h
-#define client_h
+#ifndef _CLIENT_H_
+#define _CLIENT_H_
+
 #include "Print.h"
 #include "Stream.h"
 #include "IPAddress.h"
diff --git a/STM32F4/cores/maple/HardwareTimer.h b/STM32F4/cores/maple/HardwareTimer.h
index 89e356499..c90356bf6 100644
--- a/STM32F4/cores/maple/HardwareTimer.h
+++ b/STM32F4/cores/maple/HardwareTimer.h
@@ -33,7 +33,7 @@
 
 // TODO [0.1.0] Remove deprecated pieces, pick a better API
 
-#include "timer.h"
+#include <libmaple/timer.h>
 
 /** Timer mode. */
 typedef timer_mode TimerMode;
diff --git a/STM32F4/cores/maple/IPAddress.h b/STM32F4/cores/maple/IPAddress.h
index 271b24025..c6e06972a 100644
--- a/STM32F4/cores/maple/IPAddress.h
+++ b/STM32F4/cores/maple/IPAddress.h
@@ -17,8 +17,8 @@
   Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 
-#ifndef IPAddress_h
-#define IPAddress_h
+#ifndef _IPAddress_h_
+#define _IPAddress_h_
 
 #include <stdint.h>
 #include <WString.h>
diff --git a/STM32F4/cores/maple/Server.h b/STM32F4/cores/maple/Server.h
index 69e3e39fe..4a95c9f51 100644
--- a/STM32F4/cores/maple/Server.h
+++ b/STM32F4/cores/maple/Server.h
@@ -17,8 +17,8 @@
   Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 
-#ifndef server_h
-#define server_h
+#ifndef _SERVER_H_
+#define _SERVER_H_
 
 #include "Print.h"
 
diff --git a/STM32F4/cores/maple/Stream.h b/STM32F4/cores/maple/Stream.h
index abdcd1768..870fbf0e5 100644
--- a/STM32F4/cores/maple/Stream.h
+++ b/STM32F4/cores/maple/Stream.h
@@ -19,8 +19,8 @@
   parsing functions based on TextFinder library by Michael Margolis
 */
 
-#ifndef Stream_h
-#define Stream_h
+#ifndef _STREAM_H_
+#define _STREAM_H_
 
 #include <inttypes.h>
 #include "Print.h"
diff --git a/STM32F4/cores/maple/Udp.h b/STM32F4/cores/maple/Udp.h
index dc5644b9d..1652cafc9 100644
--- a/STM32F4/cores/maple/Udp.h
+++ b/STM32F4/cores/maple/Udp.h
@@ -32,8 +32,8 @@
  * bjoern@cs.stanford.edu 12/30/2008
  */
 
-#ifndef udp_h
-#define udp_h
+#ifndef _UDP_H_
+#define _UDP_H_
 
 #include <Stream.h>
 #include <IPAddress.h>
diff --git a/STM32F4/cores/maple/WProgram.h b/STM32F4/cores/maple/WProgram.h
index 2949a0a59..82b759a64 100644
--- a/STM32F4/cores/maple/WProgram.h
+++ b/STM32F4/cores/maple/WProgram.h
@@ -24,7 +24,12 @@
  * SOFTWARE.
  *****************************************************************************/
 
-#include "wirish.h"
+#ifndef _WPROGRAM_H_
+#define _WPROGRAM_H_
+
+#include <wirish.h>
 
 void setup();
 void loop();
+
+#endif
\ No newline at end of file
diff --git a/STM32F4/cores/maple/WString.h b/STM32F4/cores/maple/WString.h
index 903857809..ec0eae7fb 100644
--- a/STM32F4/cores/maple/WString.h
+++ b/STM32F4/cores/maple/WString.h
@@ -19,8 +19,9 @@
   Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 
-#ifndef String_class_h
-#define String_class_h
+#ifndef _WSTRING_H_
+#define _WSTRING_H_
+
 #ifdef __cplusplus
 
 #include <stdlib.h>
@@ -225,4 +226,4 @@ class StringSumHelper : public String
 };
 
 #endif  // __cplusplus
-#endif  // String_class_h
+#endif  // _WSTRING_H_
diff --git a/STM32F4/cores/maple/bits.h b/STM32F4/cores/maple/bits.h
index 3e755b7f4..3e3eff1ec 100644
--- a/STM32F4/cores/maple/bits.h
+++ b/STM32F4/cores/maple/bits.h
@@ -27,4 +27,9 @@
 /* Note: Use of this header file is deprecated.  Use bit_constants.h
    instead. */
 
+#ifndef _BITS_H_
+#define _BITS_H_
+
 #include "bit_constants.h"
+
+#endif
diff --git a/STM32F4/cores/maple/boards.cpp b/STM32F4/cores/maple/boards.cpp
index fc453fece..0d55e9414 100644
--- a/STM32F4/cores/maple/boards.cpp
+++ b/STM32F4/cores/maple/boards.cpp
@@ -33,13 +33,13 @@
  */
 #include "boards.h"
 
-#include "flash.h"
-#include "rcc.h"
-#include "nvic.h"
-#include "systick.h"
-#include "gpio.h"
-#include "adc.h"
-#include "timer.h"
+#include <libmaple/flash.h>
+#include <libmaple/rcc.h>
+#include <libmaple/nvic.h>
+#include <libmaple/systick.h>
+#include <libmaple/gpio.h>
+#include <libmaple/adc.h>
+#include <libmaple/timer.h>
 #include "usb.h"
 #include "usb_serial.h"
 
diff --git a/STM32F4/cores/maple/boards.h b/STM32F4/cores/maple/boards.h
index 50fd89d38..d37bff4a5 100644
--- a/STM32F4/cores/maple/boards.h
+++ b/STM32F4/cores/maple/boards.h
@@ -39,10 +39,8 @@
 #ifndef _BOARDS_H_
 #define _BOARDS_H_
 
-#include "libmaple.h"
-#include "timer.h"
-
-#include "wirish_types.h"
+#include <wirish_types.h>
+#include <stdbool.h>
 
 /* Set of all possible pin names; not all boards have all these (note
  * that we use the Dx convention since all of the Maple's pins are
@@ -151,4 +149,12 @@ extern bool boardUsesPin(uint8 pin);
 #define CLOCK_SPEED_MHZ                 CYCLES_PER_MICROSECOND
 #define CLOCK_SPEED_HZ                  (CLOCK_SPEED_MHZ * 1000000UL)
 
+#ifndef SYSTICK_RELOAD_VAL
+#define SYSTICK_RELOAD_VAL              (1000 * CYCLES_PER_MICROSECOND - 1)
+#endif
+
+#ifndef BOARD_BUTTON_PRESSED_LEVEL
+#define BOARD_BUTTON_PRESSED_LEVEL      HIGH
+#endif
+
 #endif
diff --git a/STM32F4/cores/maple/ext_interrupts.cpp b/STM32F4/cores/maple/ext_interrupts.cpp
index f014f1300..9e985485a 100644
--- a/STM32F4/cores/maple/ext_interrupts.cpp
+++ b/STM32F4/cores/maple/ext_interrupts.cpp
@@ -31,8 +31,8 @@
  */
 
 #include "boards.h"
-#include "gpio.h"
-#include "exti.h"
+#include <libmaple/gpio.h>
+#include <libmaple/exti.h>
 #include "ext_interrupts.h"
 
 static inline exti_trigger_mode exti_out_mode(ExtIntTriggerMode mode);
diff --git a/STM32F4/cores/maple/ext_interrupts.h b/STM32F4/cores/maple/ext_interrupts.h
index b5c6f983b..fe215dceb 100644
--- a/STM32F4/cores/maple/ext_interrupts.h
+++ b/STM32F4/cores/maple/ext_interrupts.h
@@ -24,8 +24,8 @@
  * SOFTWARE.
  *****************************************************************************/
 
-#include "libmaple_types.h"
-#include "nvic.h"
+#ifndef _EXT_INTERRUPTS_H_
+#define _EXT_INTERRUPTS_H_
 
 /**
  *  @file ext_interrupts.h
@@ -33,8 +33,9 @@
  *  @brief Wiring-like external interrupt prototypes and types.
  */
 
-#ifndef _EXT_INTERRUPTS_H_
-#define _EXT_INTERRUPTS_H_
+#include <libmaple/libmaple_types.h>
+#include <libmaple/nvic.h>
+
 
 /**
  * The kind of transition on an external pin which should trigger an
diff --git a/STM32F4/cores/maple/io.h b/STM32F4/cores/maple/io.h
index 1208be63f..aeaf0fd3a 100644
--- a/STM32F4/cores/maple/io.h
+++ b/STM32F4/cores/maple/io.h
@@ -34,8 +34,8 @@
 #define _IO_H_
 
 #include <inttypes.h>
-#include "gpio.h"
-#include "adc.h"
+#include <libmaple/gpio.h>
+#include <libmaple/adc.h>
 
 #include "wirish_time.h"
 
diff --git a/STM32F4/cores/maple/itoa.h b/STM32F4/cores/maple/itoa.h
index 59af10947..09e8b2f8e 100644
--- a/STM32F4/cores/maple/itoa.h
+++ b/STM32F4/cores/maple/itoa.h
@@ -16,8 +16,8 @@
   Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 
-#ifndef _ITOA_
-#define _ITOA_
+#ifndef _ITOA_H_
+#define _ITOA_H_
 
 #ifdef __cplusplus
 extern "C"{
diff --git a/STM32F4/cores/maple/libmaple/gpioF4.c b/STM32F4/cores/maple/libmaple/gpioF4.c
index 0792e121d..6fec61caa 100644
--- a/STM32F4/cores/maple/libmaple/gpioF4.c
+++ b/STM32F4/cores/maple/libmaple/gpioF4.c
@@ -159,10 +159,10 @@ void gpio_set_mode(uint8_t io_pin, gpio_pin_mode mode) {
 	//regs->AFR[pin/8] = (regs->AFR[pin/8] & ~(15 << (4*(pin&7)))) | (((mode >> 8) & 15) << (4*(pin&7)));
 	//gpio_set_af_mode(dev, pin, mode>>8);
 
-    regs->MODER      = (regs->MODER      & ~( 3 << (2*pin)))     | (((mode >> 0) & 3)  << (2*pin));
-    regs->PUPDR      = (regs->PUPDR      & ~( 3 << (2*pin)))     | (((mode >> 2) & 3)  << (2*pin));
-    regs->OSPEEDR    = (regs->OSPEEDR    & ~( 3 << (2*pin)))     | (((mode >> 4) & 3)  << (2*pin));
-    regs->OTYPER     = (regs->OTYPER     & ~( 1 << (1*pin)))     | (((mode >> 6) & 1)  << (1*pin));
+    regs->MODER      = (regs->MODER      & ~( 3 << (pin<<1)))     | (((mode >> 0) & 3)  << (pin<<1));
+    regs->PUPDR      = (regs->PUPDR      & ~( 3 << (pin<<1)))     | (((mode >> 2) & 3)  << (pin<<1));
+    regs->OSPEEDR    = (regs->OSPEEDR    & ~( 3 << (pin<<1)))     | (((mode >> 4) & 3)  << (pin<<1));
+    regs->OTYPER     = (regs->OTYPER     & ~( 1 << (pin<<1)))     | (((mode >> 6) & 1)  << (pin<<1));
 }
 
 /**
@@ -177,7 +177,7 @@ void gpio_set_af_mode(uint8_t io_pin, int mode) {
     gpio_reg_map *regs = (PIN_MAP[io_pin].gpio_device)->regs;
 	uint8_t pin = PIN_MAP[io_pin].gpio_bit;
 
-	regs->AFR[pin>>3] = (regs->AFR[pin>>3] & ~(15 << (4*(pin&7)))) | (((mode >> 0) & 15) << (4*(pin&7)));
+	regs->AFR[pin>>3] = (regs->AFR[pin>>3] & ~(15 << ((pin&7)<<2))) | (((mode >> 0) & 15) << ((pin&7)<<2));
 }
 
 /*
diff --git a/STM32F4/cores/maple/libmaple/gpio_def.h b/STM32F4/cores/maple/libmaple/gpio_def.h
index 8b9e693ea..e2176eacb 100644
--- a/STM32F4/cores/maple/libmaple/gpio_def.h
+++ b/STM32F4/cores/maple/libmaple/gpio_def.h
@@ -36,7 +36,6 @@
 
 #include "libmaple.h"
 #include "rcc.h"
-#include "wirish_types.h"
 
 #ifdef __cplusplus
 extern "C"{
diff --git a/STM32F4/cores/maple/libmaple/libmaple.h b/STM32F4/cores/maple/libmaple/libmaple.h
index 20a57bc6f..8360ba390 100644
--- a/STM32F4/cores/maple/libmaple/libmaple.h
+++ b/STM32F4/cores/maple/libmaple/libmaple.h
@@ -32,10 +32,7 @@
 #ifndef _LIBMAPLE_H_
 #define _LIBMAPLE_H_
 
-#include "libmaple_types.h"
-#include "stm32.h"
 #include "util.h"
-#include "delay.h"
 
 /*
  * Where to put usercode, based on space reserved for bootloader.
diff --git a/STM32F4/cores/maple/libmaple/libmaple_types.h b/STM32F4/cores/maple/libmaple/libmaple_types.h
index d2e8673a1..8e765b435 100644
--- a/STM32F4/cores/maple/libmaple/libmaple_types.h
+++ b/STM32F4/cores/maple/libmaple/libmaple_types.h
@@ -34,7 +34,6 @@
 #define _LIBMAPLE_TYPES_H_
 
 #include <inttypes.h>
-#include <stdbool.h>
 
 typedef unsigned char uint8;
 typedef unsigned short uint16;
@@ -49,6 +48,7 @@ typedef long long int64;
 typedef void (*voidFuncPtr)(void);
 
 #define __io volatile
+#define __IO volatile
 #ifndef __attr_flash
   #define __attr_flash __attribute__((section (".USER_FLASH")))
 #endif
diff --git a/STM32F4/cores/maple/libmaple/spi.c b/STM32F4/cores/maple/libmaple/spi.c
index 194a82efe..4b274cb37 100644
--- a/STM32F4/cores/maple/libmaple/spi.c
+++ b/STM32F4/cores/maple/libmaple/spi.c
@@ -83,25 +83,29 @@ void spi_slave_enable(spi_dev *dev, spi_mode mode, uint32 flags) {
 }
 
 /**
- * @brief Nonblocking SPI transmit.
+ * @brief Blocking SPI transmit.
  * @param dev SPI port to use for transmission
  * @param buf Buffer to transmit.  The sizeof buf's elements are
  *            inferred from dev's data frame format (i.e., are
  *            correctly treated as 8-bit or 16-bit quantities).
  * @param len Maximum number of elements to transmit.
- * @return Number of elements transmitted.
  */
-uint32 spi_tx(spi_dev *dev, const void *buf, uint32 len) {
-    uint32 txed = 0;
-    uint8 byte_frame = spi_dff(dev) == SPI_DFF_8_BIT;
-    while (spi_is_tx_empty(dev) && (txed < len)) {
-        if (byte_frame) {
-            dev->regs->DR = ((const uint8*)buf)[txed++];
-        } else {
-            dev->regs->DR = ((const uint16*)buf)[txed++];
-        }
-    }
-    return txed;
+void spi_tx(spi_dev *dev, void *buf, uint32 len)
+{
+	spi_reg_map *regs = dev->regs;
+    if ( spi_dff(dev) == SPI_DFF_8_BIT ) {
+		uint8 * dp8 = (uint8*)buf;
+		while ( len-- ) {
+			while ( (regs->SR & SPI_SR_TXE)==0 ) ; //while ( spi_is_tx_empty(dev)==0 ); // wait Tx to be empty
+			regs->DR = *dp8++;
+		}
+    } else {
+		uint16 * dp16 = (uint16*)buf;
+		while ( len-- ) {
+			while ( (regs->SR & SPI_SR_TXE)==0 ) ; //while ( spi_is_tx_empty(dev)==0 ); // wait Tx to be empty
+			regs->DR = *dp16++;
+		}
+	}
 }
 
 /**
@@ -157,8 +161,9 @@ void spi_rx_dma_disable(spi_dev *dev) {
  */
 
 static void spi_reconfigure(spi_dev *dev, uint32 cr1_config) {
-    spi_irq_disable(dev, SPI_INTERRUPTS_ALL);
-    spi_peripheral_disable(dev);
-    dev->regs->CR1 = cr1_config;
-    spi_peripheral_enable(dev);
+#define MASK (SPI_CR1_CRCEN|SPI_CR1_DFF)
+	spi_irq_disable(dev, SPI_INTERRUPTS_ALL);
+	if ( (dev->regs->CR1&MASK)!=(cr1_config&MASK) )	spi_peripheral_disable(dev);
+	dev->regs->CR1 = cr1_config;
+	spi_peripheral_enable(dev);
 }
diff --git a/STM32F4/cores/maple/libmaple/spi.h b/STM32F4/cores/maple/libmaple/spi.h
index 043635289..f96b462b5 100644
--- a/STM32F4/cores/maple/libmaple/spi.h
+++ b/STM32F4/cores/maple/libmaple/spi.h
@@ -219,13 +219,9 @@ struct gpio_dev;
  *
  * @param dev SPI device
  * @param as_master If true, configure as bus master; otherwise, as slave.
- * @param nss_dev NSS pin's GPIO device
  * @param nss_bit NSS pin's GPIO bit on nss_dev
- * @param sck_dev SCK pin's GPIO device
  * @param sck_bit SCK pin's GPIO bit on comm_dev
- * @param miso_dev MISO pin's GPIO device
  * @param miso_bit MISO pin's GPIO bit on comm_dev
- * @param mosi_dev MOSI pin's GPIO device
  * @param mosi_bit MOSI pin's GPIO bit on comm_dev
  */
 extern void spi_config_gpios(spi_dev *dev,
@@ -308,7 +304,7 @@ void spi_slave_enable(spi_dev *dev,
                       spi_mode mode,
                       uint32 flags);
 
-uint32 spi_tx(spi_dev *dev, const void *buf, uint32 len);
+void spi_tx(spi_dev *dev, void *buf, uint32 len);
 
 /**
  * @brief Call a function on each SPI port
diff --git a/STM32F4/cores/maple/libmaple/spiF4.h b/STM32F4/cores/maple/libmaple/spiF4.h
index d2ae557fe..cbdc91a73 100644
--- a/STM32F4/cores/maple/libmaple/spiF4.h
+++ b/STM32F4/cores/maple/libmaple/spiF4.h
@@ -31,8 +31,8 @@
  * @brief STM32F1 SPI/I2S series header.
  */
 
-#ifndef _LIBMAPLE_STM32F1_SPI_H_
-#define _LIBMAPLE_STM32F1_SPI_H_
+#ifndef _LIBMAPLE_SPI_F4_H_
+#define _LIBMAPLE_SPI_F4_H_
 
 #include <libmaple/libmaple_types.h>
 
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_core.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_core.h
index f58ff0601..7ac987dcb 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_core.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_core.h
@@ -26,7 +26,7 @@
 
 #include "usbd_ioreq.h"
 #include "usbd_req.h"
-#include "usbd_desc.h"
+#include <VCP\usbd_desc.h>
 
 
 
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h
index 926f42e13..b1c8cc117 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h
@@ -24,7 +24,8 @@
 #ifndef __USB_CDC_CORE_H_
 #define __USB_CDC_CORE_H_
 
-#include  "usbd_ioreq.h"
+#include <STM32_USB_Device_Library\Core\inc/usbd_ioreq.h>
+#include <STM32_USB_OTG_Driver\inc\usb_core.h>
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_core.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_core.c
index aac6776cd..8f97c5176 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_core.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_core.c
@@ -58,9 +58,10 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include "usbd_cdc_core.h"
-#include "usbd_desc.h"
-#include "usbd_req.h"
+#include <VCP\usb_conf.h>
+#include <STM32_USB_Device_Library\Class\cdc\inc\usbd_cdc_core.h>
+#include <VCP\usbd_desc.h>
+#include <STM32_USB_Device_Library\Core\inc\usbd_req.h>
 
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_core.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_core.h
index b876856a3..063a30e69 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_core.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_core.h
@@ -24,9 +24,9 @@
 #define __USBD_CORE_H
 
 /* Includes ------------------------------------------------------------------*/
-#include "usb_dcd.h"
+#include <STM32_USB_OTG_Driver/inc/usb_dcd.h>
 #include "usbd_def.h"
-#include "usbd_conf.h"
+#include <VCP\usbd_conf.h>
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_def.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_def.h
index a8c86710d..f2a31153a 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_def.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_def.h
@@ -24,7 +24,7 @@
 #ifndef __USBD_DEF_H
 #define __USBD_DEF_H
 /* Includes ------------------------------------------------------------------*/
-#include "usbd_conf.h"
+#include <VCP\usbd_conf.h>
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_req.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_req.h
index 9aa9e44a3..f9849c6f9 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_req.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_req.h
@@ -27,7 +27,7 @@
 /* Includes ------------------------------------------------------------------*/
 #include  "usbd_def.h"
 #include  "usbd_core.h"
-#include  "usbd_conf.h"
+#include  <VCP\usbd_conf.h>
 
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_core.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_core.c
index af758427d..00bb25140 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_core.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_core.c
@@ -20,11 +20,11 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include "usbd_core.h"
-#include "usbd_req.h"
-#include "usbd_ioreq.h"
-#include "usb_dcd_int.h"
-#include "usb_bsp.h"
+#include <STM32_USB_Device_Library\Core\inc\usbd_core.h>
+#include <STM32_USB_Device_Library\Core\inc\usbd_req.h>
+#include <STM32_USB_Device_Library\Core\inc\usbd_ioreq.h>
+#include <STM32_USB_OTG_Driver\inc\usb_dcd_int.h>
+#include <STM32_USB_OTG_Driver\inc\usb_bsp.h>
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
 * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_ioreq.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_ioreq.c
index 6964766bd..20ee5a0f1 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_ioreq.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_ioreq.c
@@ -20,7 +20,7 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include "usbd_ioreq.h"
+#include <STM32_USB_Device_Library\Core\inc\usbd_ioreq.h>
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
   * @{
   */
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_req.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_req.c
index f08d26c6c..5fc2e036c 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_req.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_req.c
@@ -20,9 +20,9 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include "usbd_req.h"
-#include "usbd_ioreq.h"
-#include "usbd_desc.h"
+#include <STM32_USB_Device_Library\Core\inc\usbd_req.h>
+#include <STM32_USB_Device_Library\Core\inc\usbd_ioreq.h>
+#include <VCP\usbd_desc.h>
 
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_core.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_core.h
index 82a09e15c..43c478126 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_core.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_core.h
@@ -24,7 +24,7 @@
 #define __USB_CORE_H__
 
 /* Includes ------------------------------------------------------------------*/
-#include "usb_conf.h"
+#include <VCP\usbd_conf.h>
 #include "usb_regs.h"
 #include "usb_defines.h"
 
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_defines.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_defines.h
index 8c23d72d9..ee2c1a009 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_defines.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_defines.h
@@ -24,7 +24,7 @@
 #define __USB_DEF_H__
 
 /* Includes ------------------------------------------------------------------*/
-#include  "usb_conf.h"
+#include  <VCP\usbd_conf.h>
 
 /** @addtogroup USB_OTG_DRIVER
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_otg.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_otg.h
index 54d61b827..1347f315d 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_otg.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_otg.h
@@ -23,6 +23,7 @@
 #ifndef __USB_OTG__
 #define __USB_OTG__
 
+#include "usb_core.h"
 
 /** @addtogroup USB_OTG_DRIVER
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_regs.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_regs.h
index cd71ddfaf..99f844e58 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_regs.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_regs.h
@@ -24,8 +24,8 @@
 #define __USB_OTG_REGS_H__
 
 /* Includes ------------------------------------------------------------------*/
-#include "usb_conf.h"
-
+#include <VCP\usbd_conf.h>
+#include <libmaple\libmaple_types.h>
 
 /** @addtogroup USB_OTG_DRIVER
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_core.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_core.c
index cb9eabc8c..1687afa7c 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_core.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_core.c
@@ -20,8 +20,8 @@
   */
 
 /* Includes ------------------------------------------------------------------*/
-#include "usb_bsp.h"
-#include "usb_core.h"
+#include <STM32_USB_OTG_Driver\inc\usb_bsp.h>
+#include <STM32_USB_OTG_Driver\inc\usb_core.h>
 
 
 /** @addtogroup USB_OTG_DRIVER
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd.c
index c3336cb84..dc9e53839 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd.c
@@ -20,8 +20,8 @@
   */
 
 /* Includes ------------------------------------------------------------------*/
-#include "usb_dcd.h"
-#include "usb_bsp.h"
+#include <STM32_USB_OTG_Driver\inc\usb_dcd.h>
+#include <STM32_USB_OTG_Driver\inc\usb_bsp.h>
 
 
 /** @addtogroup USB_OTG_DRIVER
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd_int.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd_int.c
index 3a49ede25..f9e561f14 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd_int.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd_int.c
@@ -20,12 +20,12 @@
   */
 
 /* Includes ------------------------------------------------------------------*/
-#include "usb_dcd_int.h"
+#include <STM32_USB_OTG_Driver\inc\usb_dcd_int.h>
 
 typedef int IRQn_Type;
 #define __NVIC_PRIO_BITS          4
 #define __Vendor_SysTickConfig    1
-#include <core_cm4.h>
+#include <VCP\core_cm4.h>
 
 
 /** @addtogroup USB_OTG_DRIVER
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/core_cm4.h b/STM32F4/cores/maple/libmaple/usbF4/VCP/core_cm4.h
index 443665c70..ff5e9a6d4 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/core_cm4.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/core_cm4.h
@@ -141,7 +141,7 @@
 #endif
 
 #include <stdint.h>                      /*!< standard types definitions                      */
-#include <core_cmInstr.h>                /*!< Core Instruction Access                         */
+#include "core_cmInstr.h"                /*!< Core Instruction Access                         */
 //#include <core_cmFunc.h>                 /*!< Core Function Access                            */
 //#include <core_cm4_simd.h>               /*!< Compiler specific SIMD Intrinsics               */
 
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/misc.c b/STM32F4/cores/maple/libmaple/usbF4/VCP/misc.c
index 9f33150cf..15a715e87 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/misc.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/misc.c
@@ -80,7 +80,7 @@ typedef unsigned char		u8;
 typedef int IRQn_Type;
 #define __NVIC_PRIO_BITS          4
 #define __Vendor_SysTickConfig    1
-#include <core_cm4.h>
+#include "core_cm4.h"
 
 /** @addtogroup STM32F4xx_StdPeriph_Driver
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_bsp.c b/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_bsp.c
index c402bbdfe..e794cb144 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_bsp.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_bsp.c
@@ -21,13 +21,13 @@
   */
 
 /* Includes ------------------------------------------------------------------*/
-#include "usb_bsp.h"
+#include <STM32_USB_OTG_Driver\inc\usb_bsp.h>
 #include "usbd_conf.h"
-#include <gpio.h>
+#include <libmaple/gpio.h>
 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
 #define OTG_FS_IRQn 67
 //typedef unsigned char uint8_t;
-#include <misc.h>
+#include "misc.h"
 
 //#include "stm32f4_discovery.h"
 
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.h b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.h
index 67475e7a4..8398dbdbb 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.h
@@ -26,7 +26,7 @@
 /* Includes ------------------------------------------------------------------*/
 //#include "stm32f4xx.h"
 
-#include "usbd_cdc_core.h"
+#include <STM32_USB_Device_Library\Class\cdc\inc\usbd_cdc_core.h>
 #include "usbd_conf.h"
 
 
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_conf.h b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_conf.h
index 516a2fbb3..62a40c27c 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_conf.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_conf.h
@@ -25,6 +25,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 //#include   "stm32f4_discovery.h"
+#include "usb_conf.h"
 
 /** @defgroup USB_CONF_Exported_Defines
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.c b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.c
index 537f2665c..0153858fc 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.c
@@ -20,11 +20,11 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include "usbd_core.h"
+#include <STM32_USB_Device_Library\Core\inc\usbd_core.h>
 #include "usbd_desc.h"
-#include "usbd_req.h"
+#include <STM32_USB_Device_Library\Core\inc\usbd_req.h>
 #include "usbd_conf.h"
-#include "usb_regs.h"
+#include <STM32_USB_OTG_Driver\inc\usb_regs.h>
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.h b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.h
index ed999dc62..4ae998cee 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.h
@@ -25,7 +25,7 @@
 #define __USB_DESC_H
 
 /* Includes ------------------------------------------------------------------*/
-#include "usbd_def.h"
+#include <STM32_USB_Device_Library\Core\inc\usbd_def.h>
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_usr.c b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_usr.c
index 84e8d6a54..a16ce40c5 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_usr.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_usr.c
@@ -20,8 +20,8 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include "usbd_usr.h"
-#include "usbd_ioreq.h"
+#include <STM32_USB_Device_Library\Core\inc\usbd_usr.h>
+#include <STM32_USB_Device_Library\Core\inc\usbd_ioreq.h>
 
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
diff --git a/STM32F4/cores/maple/libmaple/usbF4/usb.c b/STM32F4/cores/maple/libmaple/usbF4/usb.c
index 49ddc062f..385071982 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/usb.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/usb.c
@@ -1,10 +1,14 @@
-#include "usbd_cdc_core.h"
-#include "usbd_usr.h"
-#include "usbd_desc.h"
+#ifndef _USBF4_USB_H_
+#define _USBF4_USB_H_
+
+
+#include <STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h>
+#include <STM32_USB_Device_Library/Core/inc/usbd_usr.h>
+#include <VCP\usbd_desc.h>
 #include "usb.h"
-#include <gpio.h>
-#include <rccF4.h>
-#include <usbd_cdc_vcp.h>
+#include <libmaple/gpio.h>
+#include <libmaple/rccF4.h>
+#include <VCP\usbd_cdc_vcp.h>
 #include <boards.h>
 
 USB_OTG_CORE_HANDLE  USB_OTG_dev;
@@ -92,7 +96,7 @@ RESULT usbPowerOff(void) {
 
 void usbDsbISR(void) {};
 
-#include "usb_dcd_int.h"
+#include <STM32_USB_OTG_Driver\inc\usb_dcd_int.h>
 void __irq_OTG_FS_IRQHandler(void)
 {
   USBD_OTG_ISR_Handler (&USB_OTG_dev);
@@ -101,3 +105,5 @@ void __irq_OTG_FS_IRQHandler(void)
 void x__irq_usbwakeup(void)
 {
 }
+
+#endif
diff --git a/STM32F4/cores/maple/libmaple/usbF4/usb.h b/STM32F4/cores/maple/libmaple/usbF4/usb.h
index f09f2bd0c..ce1a5585f 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/usb.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/usb.h
@@ -5,7 +5,7 @@
 extern "C" {
 #endif
 
-#include "usb_conf.h"
+#include <VCP\usb_conf.h>
 
 typedef enum _RESULT
 {
diff --git a/STM32F4/cores/maple/libmaple/util.h b/STM32F4/cores/maple/libmaple/util.h
index 62ad8af37..c5ed2de07 100644
--- a/STM32F4/cores/maple/libmaple/util.h
+++ b/STM32F4/cores/maple/libmaple/util.h
@@ -29,11 +29,12 @@
  * @brief Miscellaneous utility macros and procedures.
  */
 
-#include "libmaple_types.h"
-
 #ifndef _UTIL_H_
 #define _UTIL_H_
 
+#include "libmaple_types.h"
+#include "delay.h"
+
 #ifdef __cplusplus
 extern "C"{
 #endif
diff --git a/STM32F4/cores/maple/pwm.cpp b/STM32F4/cores/maple/pwm.cpp
index 1806348c2..c5f2ccbc6 100644
--- a/STM32F4/cores/maple/pwm.cpp
+++ b/STM32F4/cores/maple/pwm.cpp
@@ -28,8 +28,8 @@
  *  @brief Arduino-style PWM implementation.
  */
 
-#include "libmaple_types.h"
-#include "timer.h"
+#include <libmaple/libmaple_types.h>
+#include <libmaple/timer.h>
 
 #include "boards.h"
 #include "pwm.h"
diff --git a/STM32F4/cores/maple/wirish.h b/STM32F4/cores/maple/wirish.h
index 7e94fb3a7..d9a17bfdd 100644
--- a/STM32F4/cores/maple/wirish.h
+++ b/STM32F4/cores/maple/wirish.h
@@ -34,9 +34,9 @@
 #define _WIRISH_H_
 
 #include <stdlib.h>
-#include "libmaple.h"
+#include <stdio.h>
+#include <stdint.h>
 
-#include "wirish_types.h"
 #include "boards.h"
 #include "io.h"
 #include "bits.h"
@@ -44,9 +44,8 @@
 #include "ext_interrupts.h"
 #include "wirish_debug.h"
 #include "wirish_math.h"
-#include "wirish_time.h"
 #include <wirish_constants.h>
-#include "HardwareSerial.h"
+#include <libmaple/HardwareSerial.h>
 #include "HardwareTimer.h"
 #include "usb_serial.h"
 
@@ -54,8 +53,10 @@
 #define HIGH 0x1
 #define LOW  0x0
 
-//#define true 0x1
-//#define false 0x0
+#ifndef true
+  #define true 0x1
+  #define false 0x0
+#endif
 
 
 #define lowByte(w)                     ((w) & 0xFF)
diff --git a/STM32F4/cores/maple/wirish_constants.h b/STM32F4/cores/maple/wirish_constants.h
index 06a85ae8c..f39c0777e 100644
--- a/STM32F4/cores/maple/wirish_constants.h
+++ b/STM32F4/cores/maple/wirish_constants.h
@@ -1,5 +1,5 @@
-#ifndef _WIRING_CONSTANTS_
-#define _WIRING_CONSTANTS_
+#ifndef _WIRISH_CONSTANTS_H_
+#define _WIRISH_CONSTANTS_H_
 
 #ifdef __cplusplus
 extern "C"{
diff --git a/STM32F4/cores/maple/wirish_debug.h b/STM32F4/cores/maple/wirish_debug.h
index d4c0bab4d..d7dea2391 100644
--- a/STM32F4/cores/maple/wirish_debug.h
+++ b/STM32F4/cores/maple/wirish_debug.h
@@ -24,6 +24,9 @@
  * SOFTWARE.
  *****************************************************************************/
 
+#ifndef _WIRISH_DEBUG_H_
+#define _WIRISH_DEBUG_H_
+
 /**
  * @file wirish_debug.h
  * @brief High level debug port configuration
@@ -50,5 +53,7 @@ static inline void disableDebugPorts(void) {
  * @see disableDebugPorts()
  */
 static inline void enableDebugPorts(void) {
-    afio_cfg_debug_ports(AFIO_DEBUG_FULL_SWJ);
+    afio_cfg_debug_ports(AFIO_DEBUG_SW_ONLY); //AFIO_DEBUG_FULL_SWJ);
 }
+
+#endif
diff --git a/STM32F4/cores/maple/wirish_math.h b/STM32F4/cores/maple/wirish_math.h
index a85b30ada..0b8b22260 100644
--- a/STM32F4/cores/maple/wirish_math.h
+++ b/STM32F4/cores/maple/wirish_math.h
@@ -29,8 +29,8 @@
  * @brief Includes <math.h>; provides Arduino-compatible math routines.
  */
 
-#ifndef _WIRING_MATH_H_
-#define _WIRING_MATH_H_
+#ifndef _WIRISH_MATH_H_
+#define _WIRISH_MATH_H_
 
 #include <math.h>
 
diff --git a/STM32F4/cores/maple/wirish_time.cpp b/STM32F4/cores/maple/wirish_time.cpp
index 270da28ac..654c1a2d2 100644
--- a/STM32F4/cores/maple/wirish_time.cpp
+++ b/STM32F4/cores/maple/wirish_time.cpp
@@ -28,10 +28,10 @@
  *  @brief Delay implementation.
  */
 
-#include "libmaple.h"
-#include "systick.h"
+#include <libmaple/libmaple.h>
+#include <libmaple/systick.h>
 #include "wirish_time.h"
-#include "delay.h"
+#include <libmaple/delay.h>
 
 void delay(unsigned long ms) {
     uint32 i;
diff --git a/STM32F4/cores/maple/wirish_time.h b/STM32F4/cores/maple/wirish_time.h
index 20a2fbfc4..3a117863c 100644
--- a/STM32F4/cores/maple/wirish_time.h
+++ b/STM32F4/cores/maple/wirish_time.h
@@ -32,10 +32,9 @@
 #ifndef __WIRISH_TIME_H_
 #define __WIRISH_TIME_H_
 
-#include "libmaple.h"
-#include "nvic.h"
-#include "systick.h"
 #include "boards.h"
+#include <libmaple/nvic.h>
+#include <libmaple/systick.h>
 
 #define US_PER_MS               1000
 
diff --git a/STM32F4/cores/maple/wirish_types.h b/STM32F4/cores/maple/wirish_types.h
index 95e524fee..aea86fbd8 100644
--- a/STM32F4/cores/maple/wirish_types.h
+++ b/STM32F4/cores/maple/wirish_types.h
@@ -33,10 +33,9 @@
 #ifndef _WIRISH_TYPES_H_
 #define _WIRISH_TYPES_H_
 
-#include "libmaple_types.h"
-#include "gpio_def.h"
-#include "timer.h"
-#include "adc.h"
+#include <libmaple/gpio_def.h>
+#include <libmaple/timer.h>
+#include <libmaple/adc.h>
 
 /**
  * Invalid stm32_pin_info adc_channel value.
diff --git a/STM32F4/libraries/SPI/library.properties b/STM32F4/libraries/SPI/library.properties
index 6f20f0185..ba3a57704 100644
--- a/STM32F4/libraries/SPI/library.properties
+++ b/STM32F4/libraries/SPI/library.properties
@@ -7,3 +7,4 @@ paragraph=SPI for STM32F4
 category=Communication
 url=
 architectures=STM32F4
+maintainer=
\ No newline at end of file
diff --git a/STM32F4/libraries/SPI/src/SPI.cpp b/STM32F4/libraries/SPI/src/SPI.cpp
index 08fbbd5d7..baef0abf2 100644
--- a/STM32F4/libraries/SPI/src/SPI.cpp
+++ b/STM32F4/libraries/SPI/src/SPI.cpp
@@ -40,9 +40,7 @@
 #include "wirish.h"
 #include "boards.h"
 
-//#include "HardwareSerial.h"
-
-#if CYCLES_PER_MICROSECOND != 72
+#if CYCLES_PER_MICROSECOND != 168
 /* TODO [0.2.0?] something smarter than this */
 #warning "Unexpected clock speed; SPI frequency calculation will be incorrect"
 #endif
@@ -91,77 +89,105 @@ static const spi_pins board_spi_pins[] __FLASH__ = {
  */
 
 SPIClass::SPIClass(uint32 spi_num) {
+
+	_currentSetting=&_settings[spi_num-1];// SPI channels are called 1 2 and 3 but the array is zero indexed
+
+	
     switch (spi_num) {
 #if BOARD_NR_SPI >= 1
     case 1:
-        this->spi_d = SPI1;
+        _currentSetting->spi_d = SPI1;
         break;
 #endif
 #if BOARD_NR_SPI >= 2
     case 2:
-        this->spi_d = SPI2;
+        _currentSetting->spi_d = SPI2;
         break;
 #endif
 #if BOARD_NR_SPI >= 3
     case 3:
-        this->spi_d = SPI3;
+        _currentSetting->spi_d = SPI3;
         break;
 #endif
     default:
         ASSERT(0);
     }
 	
-    //pinMode(BOARD_SPI_DEFAULT_SS,OUTPUT);
-    
-    clockDivider = SPI_BAUD_PCLK_DIV_16;
-    dataMode = SPI_MODE0;
+	// Init things specific to each SPI device
+	// clock divider setup is a bit of hack, and needs to be improved at a later date.
+	_settings[0].spi_d = SPI1;
+	_settings[0].clockDivider = determine_baud_rate(_settings[0].spi_d, _settings[0].clock);
+#ifdef SPI_DMA
+	_settings[0].spiDmaDev = DMA1;
+	_settings[0].spiTxDmaChannel = DMA_CH3;
+	_settings[0].spiRxDmaChannel = DMA_CH2;
+#endif
+	_settings[1].spi_d = SPI2;
+	_settings[1].clockDivider = determine_baud_rate(_settings[1].spi_d, _settings[1].clock);
+#ifdef SPI_DMA
+	_settings[1].spiDmaDev = DMA1;
+	_settings[1].spiTxDmaChannel = DMA_CH5;
+	_settings[1].spiRxDmaChannel = DMA_CH4;
+#endif
+#if BOARD_NR_SPI >= 3
+	_settings[2].spi_d = SPI3;
+	_settings[2].clockDivider = determine_baud_rate(_settings[2].spi_d, _settings[2].clock);
+#ifdef SPI_DMA
+	_settings[2].spiDmaDev = DMA2;
+	_settings[2].spiTxDmaChannel = DMA_CH2;
+	_settings[2].spiRxDmaChannel = DMA_CH1;
+#endif
+#endif
+
 }
 
 /*
  * Set up/tear down
  */
-
-void SPIClass::begin(void) {
-
-    uint32 flags = ((bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | SPI_DFF_8_BIT | SPI_SW_SLAVE | SPI_SOFT_SS);
-    spi_init(spi_d);
-    configure_gpios(spi_d, 1);
+void SPIClass::updateSettings(void) {
+	uint32 flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | _currentSetting->dataSize | SPI_SW_SLAVE | SPI_SOFT_SS);
 	#ifdef SPI_DEBUG
-	Serial.print("spi_master_enable("); Serial.print(clockDivider); Serial.print(","); Serial.print(dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
+	Serial.print("spi_master_enable("); Serial.print(_currentSetting->clockDivider); Serial.print(","); Serial.print(_currentSetting->dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
 	#endif
-    spi_master_enable(spi_d, (spi_baud_rate)clockDivider, (spi_mode)dataMode, flags);
+	spi_master_enable(_currentSetting->spi_d, (spi_baud_rate)_currentSetting->clockDivider, (spi_mode)_currentSetting->dataMode, flags);
+}
+
+void SPIClass::begin(void) {
+    spi_init(_currentSetting->spi_d);
+    configure_gpios(_currentSetting->spi_d, 1);
+    updateSettings();
+#ifdef SPI_USE_DMA_BUFFER
+	dmaSendBufferInit();
+#endif
+//Serial.println("SPI class begin - end");
 }
 
 void SPIClass::beginSlave(void) {
-    if (dataMode >= 4) {
-        ASSERT(0);
-        return;
-    }
-    uint32 flags = ((bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | SPI_DFF_8_BIT | SPI_SW_SLAVE);
-    spi_init(spi_d);
-    configure_gpios(spi_d, 0);
+    spi_init(_currentSetting->spi_d);
+    configure_gpios(_currentSetting->spi_d, 0);
+    uint32 flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | _currentSetting->dataSize | SPI_RX_ONLY);
 	#ifdef SPI_DEBUG
-	Serial.print("spi_slave_enable("); Serial.print(dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
+	Serial.print("spi_slave_enable("); Serial.print(_currentSetting->dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
 	#endif
-    spi_slave_enable(spi_d, (spi_mode)dataMode, flags);
+    spi_slave_enable(_currentSetting->spi_d, (spi_mode)_currentSetting->dataMode, flags);
 }
 
 void SPIClass::end(void) {
-    if (!spi_is_enabled(this->spi_d)) {
+    if (!spi_is_enabled(_currentSetting->spi_d)) {
         return;
     }
 
     // Follows RM0008's sequence for disabling a SPI in master/slave
     // full duplex mode.
-    while (spi_is_rx_nonempty(this->spi_d)) {
+    while (spi_is_rx_nonempty(_currentSetting->spi_d)) {
         // FIXME [0.1.0] remove this once you have an interrupt based driver
-        volatile uint16 rx __attribute__((unused)) = spi_rx_reg(this->spi_d);
+        volatile uint16 rx __attribute__((unused)) = spi_rx_reg(_currentSetting->spi_d);
     }
-    while (!spi_is_tx_empty(this->spi_d))
+    while (!spi_is_tx_empty(_currentSetting->spi_d))
         ;
-    while (spi_is_busy(this->spi_d))
+    while (spi_is_busy(_currentSetting->spi_d))
         ;
-    spi_peripheral_disable(this->spi_d);
+    spi_peripheral_disable(_currentSetting->spi_d);
 }
 
 /* Roger Clark added  3 functions */
@@ -170,8 +196,9 @@ void SPIClass::setClockDivider(uint32_t clockDivider)
 	#ifdef SPI_DEBUG
 	Serial.print("Clock divider set to "); Serial.println(clockDivider);
 	#endif
-	this->clockDivider = clockDivider;
-	this->begin();
+	_currentSetting->clockDivider = clockDivider;
+	uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_BR);
+	_currentSetting->spi_d->regs->CR1 = cr1 | (clockDivider & SPI_CR1_BR);
 }
 
 void SPIClass::setBitOrder(BitOrder bitOrder)
@@ -179,8 +206,10 @@ void SPIClass::setBitOrder(BitOrder bitOrder)
 	#ifdef SPI_DEBUG
 	Serial.print("Bit order set to "); Serial.println(bitOrder);
 	#endif
-	this->bitOrder = bitOrder;
-	this->begin();
+	_currentSetting->bitOrder = bitOrder;
+	uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_LSBFIRST);
+	if ( bitOrder==LSBFIRST )	cr1 |= SPI_CR1_LSBFIRST;
+	_currentSetting->spi_d->regs->CR1 = cr1;
 }
 
 /*	Victor Perez. Added to test changing datasize from 8 to 16 bit modes on the fly.
@@ -189,11 +218,11 @@ void SPIClass::setBitOrder(BitOrder bitOrder)
 */
 void SPIClass::setDataSize(uint32 datasize)
 {
-		uint32 cr1 = this->spi_d->regs->CR1; 
-		datasize &= SPI_CR1_DFF;
-		cr1 &= ~(SPI_CR1_DFF); 
-		cr1 |= datasize;  
-		this->spi_d->regs->CR1 = cr1; 
+	_currentSetting->dataSize = datasize;
+	uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_DFF);
+	uint8 en = spi_is_enabled(_currentSetting->spi_d);
+	spi_peripheral_disable(_currentSetting->spi_d);
+	_currentSetting->spi_d->regs->CR1 = cr1 | (datasize & SPI_CR1_DFF) | en;
 }
 
 void SPIClass::setDataMode(uint8_t dataMode)
@@ -212,13 +241,11 @@ SPI Mode 	CPOL 	CPHA 	Shift SCK-edge 	Capture SCK-edge
 On the STM32 it appears to be
 
 bit 1 - CPOL : Clock polarity
-
     (This bit should not be changed when communication is ongoing)
     0 : CLK to 0 when idle
     1 : CLK to 1 when idle
  
 bit 0 - CPHA : Clock phase
-
     (This bit should not be changed when communication is ongoing)
     0 : The first clock transition is the first data capture edge
     1 : The second clock transition is the first data capture edge
@@ -228,10 +255,10 @@ If someone finds this is not the case or sees a logic error with this let me kno
 	#ifdef SPI_DEBUG
 	Serial.print("Data mode set to "); Serial.println(dataMode);
 	#endif
-	this->dataMode = dataMode;
-	this->begin();
-}	
-
+	_currentSetting->dataMode = dataMode;
+	uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_CPOL|SPI_CR1_CPHA);
+	_currentSetting->spi_d->regs->CR1 = cr1 | (dataMode & (SPI_CR1_CPOL|SPI_CR1_CPHA));
+}
 
 void SPIClass::beginTransaction(uint8_t pin, SPISettings settings)
 {
@@ -243,29 +270,20 @@ void SPIClass::beginTransaction(uint8_t pin, SPISettings settings)
 	//digitalWrite(_SSPin,LOW);
 	setBitOrder(settings.bitOrder);
 	setDataMode(settings.dataMode);
-	setClockDivider(determine_baud_rate(spi_d, settings.clock));
+	setDataSize(settings.dataSize);
+	setClockDivider(determine_baud_rate(_currentSetting->spi_d, settings.clock));
 	begin();
-#if 0
-// code from SAM core	
-	uint8_t mode = interruptMode;
-	if (mode > 0) {
-		if (mode < 16) {
-			if (mode & 1) PIOA->PIO_IDR = interruptMask[0];
-			if (mode & 2) PIOB->PIO_IDR = interruptMask[1];
-			if (mode & 4) PIOC->PIO_IDR = interruptMask[2];
-			if (mode & 8) PIOD->PIO_IDR = interruptMask[3];
-		} else {
-			interruptSave = interruptsStatus();
-			noInterrupts();
-		}
-	}
-	uint32_t ch = BOARD_PIN_TO_SPI_CHANNEL(pin);
-	bitOrder[ch] = settings.border;
-	SPI_ConfigureNPCS(spi, ch, settings.config);
-	//setBitOrder(pin, settings.border);
-	//setDataMode(pin, settings.datamode);
-	//setClockDivider(pin, settings.clockdiv);
-#endif
+}
+
+void SPIClass::beginTransactionSlave(SPISettings settings)
+{
+	#ifdef SPI_DEBUG
+	Serial.println(F("SPIClass::beginTransactionSlave"));
+	#endif
+	setBitOrder(settings.bitOrder);
+	setDataMode(settings.dataMode);
+	setDataSize(settings.dataSize);
+	beginSlave();
 }
 
 void SPIClass::endTransaction(void)
@@ -295,131 +313,127 @@ void SPIClass::endTransaction(void)
  * I/O
  */
 
-uint8 SPIClass::read(void) {
-    uint8 buf[1];
-    this->read(buf, 1);
-    return buf[0];
+uint16 SPIClass::read(void)
+{
+	while ( spi_is_rx_nonempty(_currentSetting->spi_d)==0 ) ;
+	return (uint16)spi_rx_reg(_currentSetting->spi_d);
 }
 
-void SPIClass::read(uint8 *buf, uint32 len) {
-    uint32 rxed = 0;
-    while (rxed < len) {
-        while (!spi_is_rx_nonempty(this->spi_d))
-            ;
-        buf[rxed++] = (uint8)spi_rx_reg(this->spi_d);
+void SPIClass::read(uint8 *buf, uint32 len)
+{
+	spi_rx_reg(_currentSetting->spi_d); // clear the RX buffer in case a byte is waiting on it.
+	spi_reg_map * regs = _currentSetting->spi_d->regs;
+	// start sequence
+	while ( (len--)>0) {
+		regs->DR = 0x00FF; // " write the data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
+		while ( (regs->SR & SPI_SR_RXNE)==0 ) ; // wait till data is available in the Rx register
+		*buf++ = (uint8)(regs->DR); // read and store the received byte
     }
 }
 
-void SPIClass::write(uint16 data) {
-	#ifdef SPI_DEBUG
-//	Serial.print("SPIClass::write("); Serial.print(data); Serial.println(")");
-	#endif
-	//  this->write(&data, 1);
-
+void SPIClass::write(uint16 data)
+{
 	/* Added for 16bit data Victor Perez. Roger Clark 
-	 * Improved speed by just directly writing the single byte to the SPI data reg and wait for completion,	 * by taking the Tx code from transfer(byte)
-	 * The original method, of calling write(*data, length) .
+	 * Improved speed by just directly writing the single byte to the SPI data reg and wait for completion,
+	 * by taking the Tx code from transfer(byte)
 	 * This almost doubles the speed of this function.
 	 */
-  
-	spi_tx_reg(this->spi_d, data); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-	while (spi_is_tx_empty(this->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(this->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
+	spi_tx_reg(_currentSetting->spi_d, data); // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
+//return;
+	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
 }
 
-//void SPIClass::write(uint8 byte) {
-  //  this->write(&byte, 1);
+void SPIClass::write(uint16 data, uint32 n)
+{
+	// Added by stevstrong: Repeatedly send same data by the specified number of times
+	spi_reg_map * regs = _currentSetting->spi_d->regs;
+	while ( (n--)>0 ) {
+		regs->DR = data; // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
+		while ( (regs->SR & SPI_SR_TXE)==0 ) ; // wait till Tx empty
+	}
+	while ( (regs->SR & SPI_SR_BSY) != 0); // wait until BSY=0 before returning 
+}
 
-	/* Roger Clark 
-	 * Improved speed by just directly writing the single byte to the SPI data reg and wait for completion,	 * by taking the Tx code from transfer(byte)
-	 * The original method, of calling write(*data, length) .
-	 * This almost doubles the speed of this function.
-	 */
-  
-//	spi_tx_reg(this->spi_d, byte); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-//	while (spi_is_tx_empty(this->spi_d) == 0); // "5. Wait until TXE=1 ..."
-//	while (spi_is_busy(this->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
-//}
+void SPIClass::write(void *data, uint32 length)
+{
+	spi_dev * spi_d = _currentSetting->spi_d;
+	spi_tx(spi_d, (void*)data, length); // data can be array of bytes or words
+	while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
+}
 
-void SPIClass::write(const uint8 *data, uint32 length) {
-	#ifdef SPI_DEBUG
-	Serial.print("SPIClass::write(data, "); Serial.print(length); Serial.println(")");
-	#endif
-    uint32 txed = 0;
-    while (txed < length) {
-        txed += spi_tx(this->spi_d, data + txed, length - txed);
-    }
-	while (spi_is_tx_empty(this->spi_d) == 0); // "4. After writing the last data item into the SPI_DR register, wait until TXE=1 ..."
-	while (spi_is_busy(this->spi_d) != 0); // "... then wait until BSY=0, this indicates that the transmission of the last data is complete."
+uint8 SPIClass::transfer(uint8 byte) const
+{
+	spi_dev * spi_d = _currentSetting->spi_d;
+	spi_rx_reg(spi_d); // read any previous data
+	spi_tx_reg(spi_d, byte); // Write the data item to be transmitted into the SPI_DR register
+	while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
+	return (uint8)spi_rx_reg(spi_d); // "... and read the last received data."
 }
 
-uint8 SPIClass::transfer(uint8 byte) const {
-	#ifdef SPI_DEBUG
-//	Serial.print("SPIClass::transfer("); Serial.print(byte); Serial.println(")");
-	#endif
-	uint8 b;
-	spi_tx_reg(this->spi_d, byte); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-  	while (spi_is_rx_nonempty(this->spi_d) == 0); // "4. Wait until RXNE=1 ..."
-  	b = spi_rx_reg(this->spi_d); // "... and read the last received data."
-  	while (spi_is_tx_empty(this->spi_d) == 0); // "5. Wait until TXE=1 ..."
-  	while (spi_is_busy(this->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
-    return b;
+uint16_t SPIClass::transfer16(uint16_t wr_data) const
+{
+	spi_dev * spi_d = _currentSetting->spi_d;
+	spi_rx_reg(spi_d); // read any previous data
+	spi_tx_reg(spi_d, wr_data); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
+	while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
+	return (uint16)spi_rx_reg(spi_d); // "... and read the last received data."
 }
+
+#ifdef SPI_DMA
 /*  Roger Clark and Victor Perez, 2015
 *	Performs a DMA SPI transfer with at least a receive buffer.
-*	If a TX buffer is not provided, FF is sent over and over for the lenght of the transfer. 
-*	On exit TX buffer is not modified, and RX buffer cotains the received data.
+*	If a TX buffer is not provided, FF is sent over and over for the length of the transfer. 
+*	On exit TX buffer is not modified, and RX buffer contains the received data.
 *	Still in progress.
 */
-uint8 SPIClass::dmaTransfer(uint8 *transmitBuf, uint8 *receiveBuf, uint16 length) {
+uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length)
+{
 	if (length == 0) return 0;
-	uint8 b;
-	if (spi_is_rx_nonempty(this->spi_d) == 1) b = spi_rx_reg(this->spi_d); //Clear the RX buffer in case a byte is waiting on it.
-	dma1_ch3_Active=true;
-    dma_init(DMA1);
-	dma_attach_interrupt(DMA1, DMA_CH3, &SPIClass::DMA1_CH3_Event);
-	
+	uint8 b = 0;
+	spi_rx_reg(_currentSetting->spi_d); //Clear the RX buffer in case a byte is waiting on it.
+//	dma1_ch3_Active=true;
+    dma_init(_currentSetting->spiDmaDev);
+//	dma_attach_interrupt(DMA1, DMA_CH3, &SPIClass::DMA1_CH3_Event);
+
 	// RX
-	spi_rx_dma_enable(SPI1);
-	dma_setup_transfer(DMA1, DMA_CH2, &SPI1->regs->DR, DMA_SIZE_8BITS,
-                     receiveBuf, DMA_SIZE_8BITS, (DMA_MINC_MODE | DMA_TRNS_CMPLT));// receive buffer DMA
-	dma_set_num_transfers(DMA1, DMA_CH2, length);
-	
+	spi_rx_dma_enable(_currentSetting->spi_d);
+	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==SPI_DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
+	dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
+                     receiveBuf, dma_bit_size, (DMA_MINC_MODE | DMA_TRNS_CMPLT));// receive buffer DMA
+	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, length);
+
 	// TX
-	spi_tx_dma_enable(SPI1);	
-	if (!transmitBuf) {
-	static uint8_t ff = 0XFF;
-	transmitBuf = &ff;
-	dma_setup_transfer(DMA1, DMA_CH3, &SPI1->regs->DR, DMA_SIZE_8BITS,
-                       transmitBuf, DMA_SIZE_8BITS, (DMA_FROM_MEM | DMA_TRNS_CMPLT));// Transmit FF repeatedly
-	}
-	else {
-    dma_setup_transfer(DMA1, DMA_CH3, &SPI1->regs->DR, DMA_SIZE_8BITS,
-                       transmitBuf, DMA_SIZE_8BITS, (DMA_MINC_MODE |  DMA_FROM_MEM | DMA_TRNS_CMPLT));// Transmit buffer DMA 
+	uint32 flags = (DMA_MINC_MODE | DMA_FROM_MEM | DMA_TRNS_CMPLT);
+	spi_tx_dma_enable(_currentSetting->spi_d);	
+	if ( transmitBuf==0 ) {
+		static uint8_t ff = 0XFF;
+		transmitBuf = &ff;
+		flags ^= DMA_MINC_MODE; // remove increment mode
 	}
-	dma_set_num_transfers(DMA1, DMA_CH3, length);
+    dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
+                       transmitBuf, dma_bit_size, flags);// Transmit buffer DMA 
+	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
 
-	dma_enable(DMA1, DMA_CH2);// enable receive
-	dma_enable(DMA1, DMA_CH3);// enable transmit
+	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);// enable receive
+	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
 	
-//	while (dma1_ch3_Active);
-//	if (receiveBuf) {
     uint32_t m = millis();
-    while (dma1_ch3_Active) {
-      if ((millis() - m) > 100)  {
-        dma1_ch3_Active = 0;
-		b = 2;
-		break;
-      }
+	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
+		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
     }
-
-//	}
-	while (spi_is_tx_empty(this->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(this->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
-    dma_disable(DMA1, DMA_CH3);
-	dma_disable(DMA1, DMA_CH2);
-	spi_rx_dma_disable(SPI1);
-	spi_tx_dma_disable(SPI1);
+	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+
+	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
+    dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
+	spi_rx_dma_disable(_currentSetting->spi_d); // And disable generation of DMA request from the SPI port so other peripherals can use the channels
+	spi_tx_dma_disable(_currentSetting->spi_d);
+	//uint16 x = spi_rx_reg(_currentSetting->spi_d); // dummy read, needed, don't remove!
     return b;
 }
 
@@ -427,56 +441,37 @@ uint8 SPIClass::dmaTransfer(uint8 *transmitBuf, uint8 *receiveBuf, uint16 length
 *	Performs a DMA SPI send using a TX buffer.
 *	On exit TX buffer is not modified.
 *	Still in progress.
+*	2016 - stevstrong - reworked to automatically detect bit size from SPI setting
 */
-uint8 SPIClass::dmaSend(uint8 *transmitBuf, uint16 length, bool minc) {
+uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length, bool minc)
+{
 	if (length == 0) return 0;
-	uint32 flags = ((DMA_MINC_MODE * minc) |  DMA_FROM_MEM | DMA_TRNS_CMPLT);
-	uint8 b;
-	dma1_ch3_Active=true;
-    dma_init(DMA1);
-	dma_attach_interrupt(DMA1, DMA_CH3, &SPIClass::DMA1_CH3_Event);
-
+	uint32 flags = ( (DMA_MINC_MODE*minc) | DMA_FROM_MEM | DMA_TRNS_CMPLT);
+	uint8 b = 0;
+	dma_init(_currentSetting->spiDmaDev);
 	// TX
-	spi_tx_dma_enable(SPI1);	
-    dma_setup_transfer(DMA1, DMA_CH3, &SPI1->regs->DR, DMA_SIZE_8BITS,
-                       transmitBuf, DMA_SIZE_8BITS, flags);// Transmit buffer DMA 
-	dma_set_num_transfers(DMA1, DMA_CH3, length);
-	dma_enable(DMA1, DMA_CH3);// enable transmit
-	
-    while (dma1_ch3_Active);
-	while (spi_is_rx_nonempty(this->spi_d) == 0); // "4. Wait until RXNE=1 ..."
-  	b = spi_rx_reg(this->spi_d); // "... and read the last received data."
-	while (spi_is_tx_empty(this->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(this->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
-	dma_disable(DMA1, DMA_CH3);
-	spi_tx_dma_disable(SPI1);
-    return b;
+	spi_tx_dma_enable(_currentSetting->spi_d);
+	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==SPI_DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
+	dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
+                       transmitBuf, dma_bit_size, flags);// Transmit buffer DMA
+	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
+	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
+
+	uint32_t m = millis();
+	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
+		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
+	}
+	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+
+	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
+	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+	spi_tx_dma_disable(_currentSetting->spi_d);
+	//uint16 x = spi_rx_reg(_currentSetting->spi_d); // dummy read, needed, don't remove!
+	return b;
 }
+#endif
 
-uint8 SPIClass::dmaSend(uint16 *transmitBuf, uint16 length, bool minc) {
-	if (length == 0) return 0;
-	uint32 flags = ((DMA_MINC_MODE * minc) |  DMA_FROM_MEM | DMA_TRNS_CMPLT);
-	uint8 b;
-	dma1_ch3_Active=true;
-    dma_init(DMA1);
-	dma_attach_interrupt(DMA1, DMA_CH3, &SPIClass::DMA1_CH3_Event);
-
-	// TX
-	spi_tx_dma_enable(SPI1);	
-    dma_setup_transfer(DMA1, DMA_CH3, &SPI1->regs->DR, DMA_SIZE_16BITS,
-                       transmitBuf, DMA_SIZE_16BITS, flags);// Transmit buffer DMA 
-	dma_set_num_transfers(DMA1, DMA_CH3, length);
-	dma_enable(DMA1, DMA_CH3);// enable transmit
-	
-    while (dma1_ch3_Active);
-	while (spi_is_rx_nonempty(this->spi_d) == 0); // "4. Wait until RXNE=1 ..."
-  	b = spi_rx_reg(this->spi_d); // "... and read the last received data."
-	while (spi_is_tx_empty(this->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(this->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
-	dma_disable(DMA1, DMA_CH3);
-	spi_tx_dma_disable(SPI1);
-    return b;
-}
 
 
 void SPIClass::attachInterrupt(void) {
@@ -492,19 +487,19 @@ void SPIClass::detachInterrupt(void) {
  */
 
 uint8 SPIClass::misoPin(void) {
-    return dev_to_spi_pins(this->spi_d)->miso;
+    return dev_to_spi_pins(_currentSetting->spi_d)->miso;
 }
 
 uint8 SPIClass::mosiPin(void) {
-    return dev_to_spi_pins(this->spi_d)->mosi;
+    return dev_to_spi_pins(_currentSetting->spi_d)->mosi;
 }
 
 uint8 SPIClass::sckPin(void) {
-    return dev_to_spi_pins(this->spi_d)->sck;
+    return dev_to_spi_pins(_currentSetting->spi_d)->sck;
 }
 
 uint8 SPIClass::nssPin(void) {
-    return dev_to_spi_pins(this->spi_d)->nss;
+    return dev_to_spi_pins(_currentSetting->spi_d)->nss;
 }
 
 /*
@@ -585,29 +580,26 @@ static void configure_gpios(spi_dev *dev, bool as_master) {
 	if(dev->clk_id <= RCC_SPI2) {
 		if(nssi) {
 			if(!as_master) {
-				gpio_set_af_mode(nssi->gpio_device,  scki->gpio_bit, 5);
+				gpio_set_af_mode(pins->nss, 5);
 			}
 		}
-		gpio_set_af_mode(scki->gpio_device,  scki->gpio_bit, 5);
-		gpio_set_af_mode(misoi->gpio_device, misoi->gpio_bit, 5);
-		gpio_set_af_mode(mosii->gpio_device, mosii->gpio_bit, 5);
+		gpio_set_af_mode(pins->sck, 5);
+		gpio_set_af_mode(pins->miso, 5);
+		gpio_set_af_mode(pins->mosi, 5);
 	} else {
 		if(nssi) {
 			if(!as_master) {
-				gpio_set_af_mode(nssi->gpio_device,  scki->gpio_bit, 6);
+				gpio_set_af_mode(pins->nss, 6);
 			}
 		}
-		gpio_set_af_mode(scki->gpio_device,  scki->gpio_bit, 6);
-		gpio_set_af_mode(misoi->gpio_device, misoi->gpio_bit, 6);
-		gpio_set_af_mode(mosii->gpio_device, mosii->gpio_bit, 6);
+		gpio_set_af_mode(pins->sck, 6);
+		gpio_set_af_mode(pins->miso, 6);
+		gpio_set_af_mode(pins->mosi, 6);
 	}
 	
 #endif
 
-    spi_config_gpios(dev, as_master, nssi->gpio_device, nssi->gpio_bit,
-                     scki->gpio_device, scki->gpio_bit, 
-                     misoi->gpio_device, misoi->gpio_bit,
-                     mosii->gpio_device, mosii->gpio_bit);
+    spi_config_gpios(dev, as_master, pins->nss, pins->sck, pins->miso, pins->mosi);
 }
 
 static const spi_baud_rate baud_rates[8] __FLASH__ = {
@@ -634,6 +626,8 @@ static spi_baud_rate determine_baud_rate(spi_dev *dev, uint32_t freq) {
     {
     	case RCC_APB2: clock = STM32_PCLK2; break; // 72 Mhz
     	case RCC_APB1: clock = STM32_PCLK1; break; // 36 Mhz
+		case RCC_AHB1: break;
+		default: break;
     }
     clock /= 2;
     i = 0;
diff --git a/STM32F4/libraries/SPI/src/SPI.h b/STM32F4/libraries/SPI/src/SPI.h
index 490d58b2e..1b01d9b25 100644
--- a/STM32F4/libraries/SPI/src/SPI.h
+++ b/STM32F4/libraries/SPI/src/SPI.h
@@ -34,16 +34,12 @@
 /* TODO [0.1.0] Remove deprecated methods. */
 
 
-
-#ifndef _SPI_H_INCLUDED
-#define _SPI_H_INCLUDED
+#ifndef _LIB_SPI_H_
+#define _LIB_SPI_H_
 
 #include <libmaple/libmaple_types.h>
 #include <libmaple/spi.h>
 #include <libmaple/dma.h>
-
-#include <boards.h>
-#include <stdint.h>
 #include <wirish.h>
 
 // SPI_HAS_TRANSACTION means SPI has
@@ -96,33 +92,61 @@
 #define SPI_MODE2 SPI_MODE_2
 #define SPI_MODE3 SPI_MODE_3
 
+#define SPI_DATA_SIZE_8BIT SPI_CR1_DFF_8_BIT
+#define SPI_DATA_SIZE_16BIT SPI_CR1_DFF_16_BIT
+
 class SPISettings {
 public:
 	SPISettings(uint32_t clock, BitOrder bitOrder, uint8_t dataMode) {
 		if (__builtin_constant_p(clock)) {
-			init_AlwaysInline(clock, bitOrder, dataMode);
+			init_AlwaysInline(clock, bitOrder, dataMode, SPI_DATA_SIZE_8BIT);
+		} else {
+			init_MightInline(clock, bitOrder, dataMode, SPI_DATA_SIZE_8BIT);
+		}
+	}
+	SPISettings(uint32_t clock, BitOrder bitOrder, uint8_t dataMode, uint32_t dataSize) {
+		if (__builtin_constant_p(clock)) {
+			init_AlwaysInline(clock, bitOrder, dataMode, dataSize);
+		} else {
+			init_MightInline(clock, bitOrder, dataMode, dataSize);
+		}
+	}
+	SPISettings(uint32_t clock) {
+		if (__builtin_constant_p(clock)) {
+			init_AlwaysInline(clock, MSBFIRST, SPI_MODE0, SPI_DATA_SIZE_8BIT);
 		} else {
-			init_MightInline(clock, bitOrder, dataMode);
+			init_MightInline(clock, MSBFIRST, SPI_MODE0, SPI_DATA_SIZE_8BIT);
 		}
 	}
-	SPISettings() { init_AlwaysInline(4000000, MSBFIRST, SPI_MODE0); }
+	SPISettings() { init_AlwaysInline(4000000, MSBFIRST, SPI_MODE0, SPI_DATA_SIZE_8BIT); }
 private:
-	void init_MightInline(uint32_t clock, BitOrder bitOrder, uint8_t dataMode) {
-		init_AlwaysInline(clock, bitOrder, dataMode);
+	void init_MightInline(uint32_t clock, BitOrder bitOrder, uint8_t dataMode, uint32_t dataSize) {
+		init_AlwaysInline(clock, bitOrder, dataMode, dataSize);
 	}
-	void init_AlwaysInline(uint32_t clock, BitOrder bitOrder, uint8_t dataMode) __attribute__((__always_inline__)) {
+	void init_AlwaysInline(uint32_t clock, BitOrder bitOrder, uint8_t dataMode, uint32_t dataSize) __attribute__((__always_inline__)) {
 		this->clock = clock;
 		this->bitOrder = bitOrder;
 		this->dataMode = dataMode;
+		this->dataSize = dataSize;
 	}
 	uint32_t clock;
 	BitOrder bitOrder;
 	uint8_t dataMode;
+	uint32_t dataSize;
+	
+	spi_dev *spi_d;
+	//uint8_t _SSPin;
+	uint32_t clockDivider;
+#ifdef SPI_DMA
+	dma_channel spiRxDmaChannel, spiTxDmaChannel;
+	dma_dev* spiDmaDev;
+#endif
+
 	friend class SPIClass;
 };
 
 
-volatile static bool dma1_ch3_Active;
+
 
 /**
  * @brief Wirish SPI interface.
@@ -175,6 +199,8 @@ class SPIClass {
 	void beginTransaction(uint8_t pin, SPISettings settings);
 	void endTransaction(void);
 
+	void beginTransactionSlave(SPISettings settings);
+
 	void setClockDivider(uint32_t clockDivider);
 	void setBitOrder(BitOrder bitOrder);	
 	void setDataMode(uint8_t dataMode);		
@@ -195,40 +221,40 @@ class SPIClass {
      */
 
     /**
-     * @brief Return the next unread byte.
+     * @brief Return the next unread byte/word.
      *
-     * If there is no unread byte waiting, this function will block
+     * If there is no unread byte/word waiting, this function will block
      * until one is received.
      */
-    uint8 read(void);
+    uint16 read(void);
 
     /**
      * @brief Read length bytes, storing them into buffer.
      * @param buffer Buffer to store received bytes into.
-     * @param length Number of bytes to store in buffer.  This
+     * @param length Number of bytes to store in buffer. This
      *               function will block until the desired number of
      *               bytes have been read.
      */
     void read(uint8 *buffer, uint32 length);
 
     /**
-     * @brief Transmit a byte.
-     * @param data Byte to transmit.
+     * @brief Transmit one byte/word.
+     * @param data to transmit.
      */
-//    void write(uint8 data);
-
+    void write(uint16 data);	
+	
     /**
-     * @brief Transmit a half word.
+     * @brief Transmit one byte/word a specified number of times.
      * @param data to transmit.
      */
-    void write(uint16 data);	
+    void write(uint16 data, uint32 n);	
 	
     /**
-     * @brief Transmit multiple bytes.
-     * @param buffer Bytes to transmit.
-     * @param length Number of bytes in buffer to transmit.
+     * @brief Transmit multiple bytes/words.
+     * @param buffer Bytes/words to transmit.
+     * @param length Number of bytes/words in buffer to transmit.
      */
-    void write(const uint8 *buffer, uint32 length);
+    void write(void * buffer, uint32 length);
 
     /**
      * @brief Transmit a byte, then return the next unread byte.
@@ -239,9 +265,12 @@ class SPIClass {
      * @return Next unread byte.
      */
     uint8 transfer(uint8 data) const;
+    uint16_t transfer16(uint16_t data) const;
 	
+#ifdef SPI_DMA
 	/**
      * @brief Sets up a DMA Transfer for "length" bytes.
+	 * The transfer mode (8 or 16 bit mode) is evaluated from the SPI peripheral setting.
      *
      * This function transmits and receives to buffers.
      *
@@ -249,30 +278,19 @@ class SPIClass {
      * @param receiveBuf buffer Bytes to save received data. 
      * @param length Number of bytes in buffer to transmit.
 	 */
-	uint8 dmaTransfer(uint8 *transmitBuf, uint8 *receiveBuf, uint16 length);
+	uint8 dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length);
 
 	/**
-     * @brief Sets up a DMA Transmit for bytes.
-     *
-     * This function transmits and does not care about the RX fifo.
-     *
-     * @param transmitBuf buffer Bytes to transmit,
-     * @param length Number of bytes in buffer to transmit.
-	 * @param minc Set to use Memory Increment mode, clear to use Circular mode.
-     */
-	uint8 dmaSend(uint8 *transmitBuf, uint16 length, bool minc = 1);
-	
-	/**
-     * @brief Sets up a DMA Transmit for half words.
-	 * SPI PERFIPHERAL MUST BE SET TO 16 BIT MODE BEFORE
+     * @brief Sets up a DMA Transmit for SPI 8 or 16 bit transfer mode.
+	 * The transfer mode (8 or 16 bit mode) is evaluated from the SPI peripheral setting.
      *
-     * This function transmits and does not care about the RX fifo.
+     * This function only transmits and does not care about the RX fifo.
      *
      * @param data buffer half words to transmit,
      * @param length Number of bytes in buffer to transmit.
-     * @param minc Set to use Memory Increment mode (default if blank), clear to use Circular mode.
      */
-	uint8 dmaSend(uint16 *transmitBuf, uint16 length, bool minc = 1);
+	uint8 dmaSend(void * transmitBuf, uint16 length, bool minc = 1);
+#endif
 
     /*
      * Pin accessors
@@ -304,7 +322,24 @@ class SPIClass {
      * @brief Get a pointer to the underlying libmaple spi_dev for
      *        this HardwareSPI instance.
      */
-    spi_dev* c_dev(void) { return this->spi_d; }
+    spi_dev* c_dev(void) { return _currentSetting->spi_d; }
+	
+		
+	spi_dev *dev(){ return _currentSetting->spi_d;}
+	
+	 /**
+     * @brief Sets the number of the SPI peripheral to be used by
+     *        this HardwareSPI instance.
+	 *
+	 * @param spi_num Number of the SPI port. 1-2 in low density devices
+	 *			or 1-3 in high density devices.
+     */
+	
+	void setModule(int spi_num)
+	{
+		_currentSetting=&_settings[spi_num-1];// SPI channels are called 1 2 and 3 but the array is zero indexed
+	}
+
 
     /* -- The following methods are deprecated --------------------------- */
 
@@ -338,12 +373,8 @@ class SPIClass {
      */
     uint8 recv(void);
 	
-	spi_dev *dev(){ return spi_d;}
-	
-	
-	
 private:
-
+/*
 	static inline void DMA1_CH3_Event() {
 		dma1_ch3_Active = 0;
 //		dma_disable(DMA1, DMA_CH3);
@@ -351,11 +382,18 @@ class SPIClass {
 		
 		// To Do. Need to wait for 
 	}
+*/	
+	SPISettings _settings[BOARD_NR_SPI];
+	SPISettings *_currentSetting;
+	
+	void updateSettings(void);
+	/*
 	spi_dev *spi_d;
 	uint8_t _SSPin;
 	uint32_t clockDivider;
 	uint8_t dataMode;
 	BitOrder bitOrder;
+	*/
 };
 
 
diff --git a/STM32F4/platform.txt b/STM32F4/platform.txt
index 5bfa22efe..2bb1946b0 100755
--- a/STM32F4/platform.txt
+++ b/STM32F4/platform.txt
@@ -8,8 +8,6 @@ version=0.1.0
 
 # compiler variables
 # ----------------------
-#build.gcc_ver=gcc-arm-none-eabi-4.8.3-2014q1
-
 compiler.path={runtime.tools.arm-none-eabi-gcc.path}/bin/
 compiler.c.cmd=arm-none-eabi-gcc
 compiler.c.flags=-c -g -Os -Wall -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
@@ -30,6 +28,8 @@ compiler.size.cmd=arm-none-eabi-size
 compiler.define=-DARDUINO=                            
 
 # this can be overriden in boards.txt
+build.f_cpu=168000000L
+build.mcu=cortex-m4
 build.cpu_flags=
 build.hs_flag=
 build.common_flags=-mthumb -D__STM32F4__
@@ -44,10 +44,10 @@ compiler.ar.extra_flags=
 compiler.elf2hex.extra_flags=
 
 
-##compiler.libs.c.flags="-I{build.system.path}/libmaple" "-I{build.system.path}/libmaple/include" "-I{build.system.path}/libmaple/stm32f1/include" "-I{build.system.path}/libmaple/stm32f1/include/series" "-I{build.system.path}/libmaple/usb/stm32f1" "-I{build.system.path}/libmaple/usb/usb_lib" 
-#compiler.libs.c.flags="-I{build.system.path}/libmaple" "-I{build.system.path}/libmaple/include" "-I{build.system.path}/libmaple/stm32f1/include"                                                           "-I{build.system.path}/libmaple/usb/stm32f1" "-I{build.system.path}/libmaple/usb/usb_lib" 
+##compiler.libs.c.flags="-I{build.system.path}/libmaple" "-I{build.system.path}/libmaple/include" "-I{build.system.path}/libmaple/stm32f1/include"                                                           "-I{build.system.path}/libmaple/usb/stm32f1" "-I{build.system.path}/libmaple/usb/usb_lib" 
+#compiler.libs.c.flags="-I{build.core.path}" "-I{build.core.path}/libmaple" "-I{build.core.path}/libmaple/usbF4" "-I{build.core.path}/libmaple/usbF4/STM32_USB_Device_Library/Core/inc" "-I{build.core.path}/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/inc" "-I{build.core.path}/libmaple/usbF4/STM32_USB_OTG_Driver/inc" "-I{build.core.path}/libmaple/usbF4/VCP" 
+compiler.libs.c.flags="-I{build.system.path}/libmaple" "-I{build.core.path}/libmaple/usbF4"
 
-compiler.libs.c.flags=-I{build.core.path} -I{build.core.path}/libmaple -I{build.core.path}/libmaple/usbF4 -I{build.core.path}/libmaple/usbF4/STM32_USB_Device_Library/Core/inc -I{build.core.path}/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/inc -I{build.core.path}/libmaple/usbF4/STM32_USB_OTG_Driver/inc -I{build.core.path}/libmaple/usbF4/VCP 
 
 
 
@@ -71,7 +71,6 @@ recipe.cpp.o.pattern="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.flags} -m
 
 ## Compile S files
 recipe.S.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.S.flags} -mcpu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.S.extra_flags} {build.extra_flags} {build.cpu_flags} {build.hs_flag} {build.common_flags} {compiler.libs.c.flags} {includes} "{source_file}" -o "{object_file}"
-#recipe.S.o.pattern="{compiler.path}{compiler.c.cmd}" "{source_file}" -o "{object_file}"
 
 ## Create archives
 recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} {compiler.ar.extra_flags} "{archive_file_path}" "{object_file}"
@@ -90,7 +89,6 @@ recipe.objcopy.hex.pattern="{compiler.path}{compiler.elf2hex.cmd}" {compiler.elf
 
 ## Compute size
 recipe.size.pattern="{compiler.path}{compiler.size.cmd}" -A "{build.path}/{build.project_name}.elf"
-#recipe.size.regex=\.text\s+([0-9]+).*
 recipe.size.regex=^(?:\.text|\.rodata|\.ARM.exidx)\s+([0-9]+).*
 recipe.size.regex.data=^(?:\.data|\.bss|\.noinit)\s+([0-9]+).*
 
diff --git a/STM32F4/system/libmaple/Arduino.h b/STM32F4/system/libmaple/Arduino.h
new file mode 100644
index 000000000..cef8f089f
--- /dev/null
+++ b/STM32F4/system/libmaple/Arduino.h
@@ -0,0 +1,46 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 LeafLabs LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+#ifndef _WIRISH_ARDUINO_H_
+#define _WIRISH_ARDUINO_H_
+
+//#warning Include Arduino.h from system\libmaple
+
+#include "wirish.h"
+
+void setup();
+void loop();
+#ifdef __cplusplus
+extern "C"{
+#endif // __cplusplus
+void yield(void);
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#include "variant.h"
+
+#endif
diff --git a/STM32F4/variants/generic_f407v/generic_f407v.cpp b/STM32F4/variants/generic_f407v/generic_f407v.cpp
index 119906476..a4a5ecbb4 100644
--- a/STM32F4/variants/generic_f407v/generic_f407v.cpp
+++ b/STM32F4/variants/generic_f407v/generic_f407v.cpp
@@ -35,40 +35,11 @@
 #include "generic_f407v.h"
 
 //#include "fsmc.h"
-#include "gpio.h"
-#include "rcc.h"
-#include "timer.h"
+#include <libmaple/gpio.h>
+#include <libmaple/rcc.h>
+#include <libmaple/timer.h>
 
-#include "wirish_types.h"
-
-// Pins reserved for the on-board hardware
-#define USB_DM_PIN		BOARD_USB_DM_PIN // PA11
-#define USB_DP_PIN		BOARD_USB_DP_PIN // PA12
-
-#define FLASH_CS_PIN	PB0
-#define FLASH_CLK_PIN	BOARD_SPI3_SCK_PIN	// PB3
-#define FLASH_DO_PIN	BOARD_SPI3_MISO_PIN	// PB4
-#define FLASH_DI_PIN	BOARD_SPI3_MOSI_PIN	// PB5
-
-#define NRF24_CLK_PIN	BOARD_SPI3_SCK_PIN	// PB3
-#define NRF24_DO_PIN	BOARD_SPI3_MISO_PIN	// PB4
-#define NRF24_DI_PIN	BOARD_SPI3_MOSI_PIN	// PB5
-#define NRF24_CE_PIN	PB6
-#define NRF24_CS_PIN	PB7
-#define NRF24_IRQ_PIN	PB8
-
-// SD card, SDIO mode
-#define SD_DAT0         BOARD_SDIO_D0	// PC8
-#define SD_DAT1         BOARD_SDIO_D1	// PC9
-#define SD_DAT2         BOARD_SDIO_D2	// PC10
-#define SD_DAT3         BOARD_SDIO_D3	// PC11
-#define SD_CLK          BOARD_SDIO_CK	// PC12
-#define SD_CMD          BOARD_SDIO_CMD	// PD2
-// SD card, SPI mode, only usable with software SPI
-#define SD_DI           BOARD_SDIO_CMD	// PD2
-#define SD_DO           BOARD_SDIO_D0	// PC8
-#define SD_CS           BOARD_SDIO_D3	// PC11
-#define SD_SCLK         BOARD_SDIO_CK	// PC12
+#include <wirish_types.h>
 
 //static void initSRAMChip(void);
 /*****************************************************************************/
diff --git a/STM32F4/variants/generic_f407v/generic_f407v.h b/STM32F4/variants/generic_f407v/generic_f407v.h
index b9f034847..927f9cd9c 100644
--- a/STM32F4/variants/generic_f407v/generic_f407v.h
+++ b/STM32F4/variants/generic_f407v/generic_f407v.h
@@ -47,6 +47,8 @@
 
 #define SYSTICK_RELOAD_VAL      (CYCLES_PER_MICROSECOND*1000-1)
 
+/*****************************************************************************/
+// Board pin definitions
 #define BOARD_USB_DM_PIN		PA11
 #define BOARD_USB_DP_PIN		PA12
 
@@ -92,10 +94,10 @@
 #define BOARD_SPI3_MISO_PIN     PB4  //Port2Pin('B', 4)
 #define BOARD_SPI3_MOSI_PIN     PB5  //Port2Pin('B', 5)
 /* overlap with the SDIO interface for SD card
-#define BOARD_SPI3A_NSS_PIN     Port2Pin('A', 4)
-#define BOARD_SPI3A_SCK_PIN     Port2Pin('C',10)
-#define BOARD_SPI3A_MISO_PIN    Port2Pin('C',11)
-#define BOARD_SPI3A_MOSI_PIN    Port2Pin('C',12)
+#define BOARD_SPI3A_NSS_PIN     PA4  //Port2Pin('A', 4)
+#define BOARD_SPI3A_SCK_PIN     PC10 //Port2Pin('C',10)
+#define BOARD_SPI3A_MISO_PIN    PC11 //Port2Pin('C',11)
+#define BOARD_SPI3A_MOSI_PIN    PC12 //Port2Pin('C',12)
 */
 #define BOARD_SDIO_D0           PC8  //Port2Pin('C', 8)
 #define BOARD_SDIO_D1           PC9  //Port2Pin('C', 9)
@@ -114,6 +116,37 @@
 #define BOARD_JTDO_PIN          PB3  //Port2Pin('B', 3)
 #define BOARD_NJTRST_PIN        PB4  //Port2Pin('B', 4)
 
+/*****************************************************************************/
+// Pins reserved for the on-board hardware
+#define USB_DM_PIN		BOARD_USB_DM_PIN // PA11
+#define USB_DP_PIN		BOARD_USB_DP_PIN // PA12
+
+#define FLASH_CS_PIN	PB0
+#define FLASH_CLK_PIN	BOARD_SPI3_SCK_PIN	// PB3
+#define FLASH_DO_PIN	BOARD_SPI3_MISO_PIN	// PB4
+#define FLASH_DI_PIN	BOARD_SPI3_MOSI_PIN	// PB5
+
+#define NRF24_CLK_PIN	BOARD_SPI3_SCK_PIN	// PB3
+#define NRF24_DO_PIN	BOARD_SPI3_MISO_PIN	// PB4
+#define NRF24_DI_PIN	BOARD_SPI3_MOSI_PIN	// PB5
+#define NRF24_CE_PIN	PB6
+#define NRF24_CS_PIN	PB7
+#define NRF24_IRQ_PIN	PB8
+
+// SD card, SDIO mode
+#define SD_DAT0         BOARD_SDIO_D0	// PC8
+#define SD_DAT1         BOARD_SDIO_D1	// PC9
+#define SD_DAT2         BOARD_SDIO_D2	// PC10
+#define SD_DAT3         BOARD_SDIO_D3	// PC11
+#define SD_CLK          BOARD_SDIO_CK	// PC12
+#define SD_CMD          BOARD_SDIO_CMD	// PD2
+// SD card, SPI mode, only usable with software SPI
+#define SD_DI           BOARD_SDIO_CMD	// PD2
+#define SD_DO           BOARD_SDIO_D0	// PC8
+#define SD_CS           BOARD_SDIO_D3	// PC11
+#define SD_SCLK         BOARD_SDIO_CK	// PC12
+
+/*****************************************************************************/
 
 enum {
 PA0,PA1,PA2,PA3,PA4,PA5,PA6,PA7,PA8,PA9,PA10,PA11,PA12,PA13,PA14,PA15,

From 483bbe17d3ddbe827a9c1ddd1197745f8b69a016 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Thu, 4 May 2017 17:18:11 +0200
Subject: [PATCH 058/307] corrected OTYPER register setting

---
 STM32F4/cores/maple/libmaple/gpioF4.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F4/cores/maple/libmaple/gpioF4.c b/STM32F4/cores/maple/libmaple/gpioF4.c
index 6fec61caa..fe3cc876f 100644
--- a/STM32F4/cores/maple/libmaple/gpioF4.c
+++ b/STM32F4/cores/maple/libmaple/gpioF4.c
@@ -162,7 +162,7 @@ void gpio_set_mode(uint8_t io_pin, gpio_pin_mode mode) {
     regs->MODER      = (regs->MODER      & ~( 3 << (pin<<1)))     | (((mode >> 0) & 3)  << (pin<<1));
     regs->PUPDR      = (regs->PUPDR      & ~( 3 << (pin<<1)))     | (((mode >> 2) & 3)  << (pin<<1));
     regs->OSPEEDR    = (regs->OSPEEDR    & ~( 3 << (pin<<1)))     | (((mode >> 4) & 3)  << (pin<<1));
-    regs->OTYPER     = (regs->OTYPER     & ~( 1 << (pin<<1)))     | (((mode >> 6) & 1)  << (pin<<1));
+    regs->OTYPER     = (regs->OTYPER     & ~( 1 << (pin<<0)))     | (((mode >> 6) & 1)  << (pin<<0));
 }
 
 /**

From 30d1bf490071c6beeeb3b6f1eb108f4450e0fdf6 Mon Sep 17 00:00:00 2001
From: syfre <syfre92@gmail.com>
Date: Sat, 6 May 2017 23:02:54 +0200
Subject: [PATCH 059/307] Fix, add ADC_CR2_EXTTRIG to adc_set_extsel() to
 enable the external trigger mode

---
 STM32F1/cores/maple/libmaple/adc.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/STM32F1/cores/maple/libmaple/adc.c b/STM32F1/cores/maple/libmaple/adc.c
index 7c48ee41f..416cfaac5 100644
--- a/STM32F1/cores/maple/libmaple/adc.c
+++ b/STM32F1/cores/maple/libmaple/adc.c
@@ -59,6 +59,7 @@ void adc_set_extsel(adc_dev *dev, adc_extsel_event event) {
     uint32 cr2 = dev->regs->CR2;
     cr2 &= ~ADC_CR2_EXTSEL;
     cr2 |= event;
+    cr2 |= ADC_CR2_EXTTRIG;
     dev->regs->CR2 = cr2;
 }
 

From 50e4d84db49dbe20d759f99614bb6d71ef8737e5 Mon Sep 17 00:00:00 2001
From: syfre <syfre92@gmail.com>
Date: Sat, 6 May 2017 23:03:47 +0200
Subject: [PATCH 060/307] Add, setMasterModeTrGo to configure the TrGo mode Use
 to trigger the ADC on TIMx_TRGO

---
 STM32F1/cores/maple/HardwareTimer.cpp |  5 +++++
 STM32F1/cores/maple/HardwareTimer.h   | 17 +++++++++++++++++
 2 files changed, 22 insertions(+)

diff --git a/STM32F1/cores/maple/HardwareTimer.cpp b/STM32F1/cores/maple/HardwareTimer.cpp
index 48d040037..ecd1b11cf 100644
--- a/STM32F1/cores/maple/HardwareTimer.cpp
+++ b/STM32F1/cores/maple/HardwareTimer.cpp
@@ -142,6 +142,11 @@ void HardwareTimer::refresh(void) {
     timer_generate_update(this->dev);
 }
 
+void HardwareTimer::setMasterModeTrGo(uint32_t mode) {
+	this->dev->regs.bas->CR2 &= ~TIMER_CR2_MMS;
+	this->dev->regs.bas->CR2 |= mode;
+}
+
 /*  CARLOS Changes to add encoder mode.*/
 
 //direction of movement. (to be better described). 
diff --git a/STM32F1/cores/maple/HardwareTimer.h b/STM32F1/cores/maple/HardwareTimer.h
index 45272ec0b..75601d0cb 100644
--- a/STM32F1/cores/maple/HardwareTimer.h
+++ b/STM32F1/cores/maple/HardwareTimer.h
@@ -209,6 +209,23 @@ class HardwareTimer {
      */
     void refresh(void);
 
+	// SYFRE
+    /**
+     * @brief Set the Master mode TRGO signal 
+     *        These bits allow to select the information to be sent in master mode to slave timers for 
+     *        synchronization (TRGO). 
+	 *	mode:
+	 * 		TIMER_CR2_MMS_RESET
+	 * 		TIMER_CR2_MMS_ENABLE
+	 * 		TIMER_CR2_MMS_UPDATE
+	 * 		TIMER_CR2_MMS_COMPARE_PULSE
+	 * 		TIMER_CR2_MMS_COMPARE_OC1REF
+	 * 		TIMER_CR2_MMS_COMPARE_OC2REF
+	 * 		TIMER_CR2_MMS_COMPARE_OC3REF
+	 * 		TIMER_CR2_MMS_COMPARE_OC4REF
+     */
+	void setMasterModeTrGo(uint32_t mode);
+	
 //CARLOS.
 /*
     added these functions to make sense for the encoder mode. 

From d240a7efa737a4f4a7a8f053c4a3d1eb4da68841 Mon Sep 17 00:00:00 2001
From: syfre <syfre92@gmail.com>
Date: Sat, 6 May 2017 23:04:11 +0200
Subject: [PATCH 061/307] Fix, compile error in enable_internal_reading()

---
 STM32F1/libraries/STM32ADC/src/utility/util_adc.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/libraries/STM32ADC/src/utility/util_adc.c b/STM32F1/libraries/STM32ADC/src/utility/util_adc.c
index 5d44939c9..e64b58e20 100644
--- a/STM32F1/libraries/STM32ADC/src/utility/util_adc.c
+++ b/STM32F1/libraries/STM32ADC/src/utility/util_adc.c
@@ -45,7 +45,7 @@ void enable_adc_irq(adc_dev* dev) {//ADC1 for now.
     Enable the reading of the internal variables (Temperature and Vref).
 */
 void enable_internal_reading(adc_dev *dev) {
-  dev->regs->CR2 |= ADC_CR2_TSEREFE;
+  dev->regs->CR2 |= ADC_CR2_TSVREFE;
   }
 
 /*

From c8df44228ced3ad7a08f0275ad7acc3458dede70 Mon Sep 17 00:00:00 2001
From: syfre <syfre92@gmail.com>
Date: Sun, 7 May 2017 11:41:58 +0200
Subject: [PATCH 062/307] Add, SMT32ADC example, Single channel at fixed sample
 rate (timer) using circular buffer (DMA)

---
 ...ingleChannelAtSampleRateCircularBuffer.ino | 87 +++++++++++++++++++
 1 file changed, 87 insertions(+)
 create mode 100644 STM32F1/libraries/STM32ADC/examples/SingleChannelAtSampleRateCircularBuffer/SingleChannelAtSampleRateCircularBuffer.ino

diff --git a/STM32F1/libraries/STM32ADC/examples/SingleChannelAtSampleRateCircularBuffer/SingleChannelAtSampleRateCircularBuffer.ino b/STM32F1/libraries/STM32ADC/examples/SingleChannelAtSampleRateCircularBuffer/SingleChannelAtSampleRateCircularBuffer.ino
new file mode 100644
index 000000000..e63fe3260
--- /dev/null
+++ b/STM32F1/libraries/STM32ADC/examples/SingleChannelAtSampleRateCircularBuffer/SingleChannelAtSampleRateCircularBuffer.ino
@@ -0,0 +1,87 @@
+#include <HardwareTimer.h>
+#include <STM32ADC.h>
+
+#define pinLED  PC13
+#define pinOUT  PB0
+
+#define _SEND_BY_USB
+#ifdef SEND_BY_USB
+USBSerial usb;
+#endif
+
+// Channels to be acquired. 
+// A0 (adc1 channel 1)
+uint8 pins = 0;
+
+#define maxSamples  2000
+uint16_t buffer[maxSamples];
+uint16_t *buffers[2];
+uint8_t bufr;
+uint8_t bufw;
+
+#define sampleFreqKhz       200
+#define samplePeriodus      1000 / sampleFreqKhz
+#define ticksPerSecond      2 * sampleFreqKhz * 1000 / maxSamples
+
+
+STM32ADC myADC(ADC1);
+
+
+long ticks;
+void TimerIRQ(void) {
+  ticks++;
+}
+void DmaIRQ(void) {
+  digitalWrite(pinOUT, ! digitalRead(pinOUT));
+  bufw = (bufw+1)%2;
+  ticks++;
+}
+
+void setup() {
+  
+  pinMode(pinLED, OUTPUT);
+  pinMode(pinOUT, OUTPUT);
+  pinMode(pins, INPUT_ANALOG);
+
+  Serial.begin(115200);
+  Serial.println("START");  
+
+  #ifdef SEND_BY_USB
+  usb.begin();
+  while (!usb.isConnected()) ;
+  #endif
+
+  ticks = 0;
+  bufr = 0;
+  bufw = 0;
+  buffers[0] = &buffer[0];
+  buffers[1] = &buffer[maxSamples/2];
+
+  Timer3.setPeriod(samplePeriodus);
+  Timer3.setMasterModeTrGo(TIMER_CR2_MMS_UPDATE);
+
+  myADC.calibrate();
+  myADC.setSampleRate(ADC_SMPR_1_5); // ?
+  myADC.setPins(&pins, 1);
+  myADC.setDMA(buffer, maxSamples, (DMA_MINC_MODE | DMA_CIRC_MODE | DMA_HALF_TRNS | DMA_TRNS_CMPLT), DmaIRQ);
+  myADC.setTrigger(ADC_EXT_EV_TIM3_TRGO);
+  myADC.startConversion();
+}
+
+void loop() {
+
+  if (bufr!=bufw) {
+    // process data 
+    
+    #ifdef SEND_BY_USB
+    if (usb.isConnected()) usb.write((uint8_t *)buffers[bufr],maxSamples); // send it : (maxSamples /2 )*2 (bytes)
+    #endif
+
+    bufr = (bufr+1)%2;
+  }
+  
+  if (ticks==ticksPerSecond) {
+    digitalWrite(pinLED, ! digitalRead(pinLED));
+    ticks = 0;
+  }
+}

From 28fa836f4f65e6a25c2f7e34765116f283c4f6c7 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Sun, 7 May 2017 15:09:15 +0200
Subject: [PATCH 063/307] PIN_MAP moved to flash

---
 STM32F4/cores/maple/ext_interrupts.cpp        |   4 +-
 STM32F4/cores/maple/libmaple/adc.c            |  21 +-
 STM32F4/cores/maple/libmaple/adc.h            |   6 +-
 STM32F4/cores/maple/libmaple/gpio.h           |  16 +-
 STM32F4/cores/maple/libmaple/gpioF4.c         |  57 ++---
 STM32F4/cores/maple/libmaple/gpio_def.h       |  15 +-
 STM32F4/cores/maple/libmaple/spi.h            |   1 -
 STM32F4/cores/maple/libmaple/timer.c          |  16 +-
 STM32F4/cores/maple/usb_serial.cpp            |   2 +-
 STM32F4/cores/maple/usb_serial.h              |  12 +-
 STM32F4/cores/maple/wirish.h                  |   1 -
 STM32F4/cores/maple/wirish_types.h            |   8 +-
 STM32F4/libraries/SPI/src/SPI.h               |   1 -
 STM32F4/variants/generic_f407v/black_f4.h.old | 130 -----------
 .../variants/generic_f407v/generic_f407v.cpp  | 156 +------------
 STM32F4/variants/generic_f407v/pin_map.c      | 214 ++++++++++++++++++
 16 files changed, 286 insertions(+), 374 deletions(-)
 delete mode 100644 STM32F4/variants/generic_f407v/black_f4.h.old
 create mode 100644 STM32F4/variants/generic_f407v/pin_map.c

diff --git a/STM32F4/cores/maple/ext_interrupts.cpp b/STM32F4/cores/maple/ext_interrupts.cpp
index 9e985485a..7111d0c86 100644
--- a/STM32F4/cores/maple/ext_interrupts.cpp
+++ b/STM32F4/cores/maple/ext_interrupts.cpp
@@ -51,7 +51,7 @@ void attachInterrupt(uint8 pin, voidFuncPtr handler, ExtIntTriggerMode mode) {
 
     exti_trigger_mode outMode = exti_out_mode(mode);
 
-    exti_attach_interrupt((afio_exti_num)(PIN_MAP[pin].gpio_bit),
+    exti_attach_interrupt((afio_exti_num)(pin&0x0F),
                           gpio_exti_port(PIN_MAP[pin].gpio_device),
                           handler,
                           outMode);
@@ -66,7 +66,7 @@ void detachInterrupt(uint8 pin) {
         return;
     }
 
-    exti_detach_interrupt((afio_exti_num)(PIN_MAP[pin].gpio_bit));
+    exti_detach_interrupt((afio_exti_num)(pin&0x0F));
 }
 
 static inline exti_trigger_mode exti_out_mode(ExtIntTriggerMode mode) {
diff --git a/STM32F4/cores/maple/libmaple/adc.c b/STM32F4/cores/maple/libmaple/adc.c
index b803f29cb..0f4c02c3c 100644
--- a/STM32F4/cores/maple/libmaple/adc.c
+++ b/STM32F4/cores/maple/libmaple/adc.c
@@ -41,27 +41,24 @@
 #include "rcc.h"
 #include "adc.h"
 
-static adc_dev adc1 = {
+/** ADC1 device. */
+const adc_dev ADC1 = {
     .regs   = ADC1_BASE,
     .clk_id = RCC_ADC1
 };
-/** ADC1 device. */
-const adc_dev *ADC1 = &adc1;
 
-static adc_dev adc2 = {
+/** ADC2 device. */
+const adc_dev ADC2 = {
     .regs   = ADC2_BASE,
     .clk_id = RCC_ADC2
 };
-/** ADC2 device. */
-const adc_dev *ADC2 = &adc2;
 
 #ifdef STM32_HIGH_DENSITY
-adc_dev adc3 = {
+/** ADC3 device. */
+const adc_dev ADC3 = {
     .regs   = ADC3_BASE,
     .clk_id = RCC_ADC3
 };
-/** ADC3 device. */
-const adc_dev *ADC3 = &adc3;
 #endif
 
 /**
@@ -101,10 +98,10 @@ void adc_set_extsel(const adc_dev *dev, adc_extsel_event event) {
  * @param fn Function to call on each ADC device.
  */
 void adc_foreach(void (*fn)(const adc_dev*)) {
-    fn(ADC1);
-    fn(ADC2);
+    fn(&ADC1);
+    fn(&ADC2);
 #ifdef STM32_HIGH_DENSITY
-    fn(ADC3);
+    fn(&ADC3);
 #endif
 }
 
diff --git a/STM32F4/cores/maple/libmaple/adc.h b/STM32F4/cores/maple/libmaple/adc.h
index 7a395102d..6fa61f5ea 100644
--- a/STM32F4/cores/maple/libmaple/adc.h
+++ b/STM32F4/cores/maple/libmaple/adc.h
@@ -82,10 +82,10 @@ typedef struct adc_dev {
     rcc_clk_id clk_id; /**< RCC clock information */
 } adc_dev;
 
-extern const adc_dev *ADC1;
-extern const adc_dev *ADC2;
+extern const adc_dev ADC1;
+extern const adc_dev ADC2;
 #ifdef STM32_HIGH_DENSITY
-extern const adc_dev *ADC3;
+extern const adc_dev ADC3;
 #endif
 
 /*
diff --git a/STM32F4/cores/maple/libmaple/gpio.h b/STM32F4/cores/maple/libmaple/gpio.h
index 4c0ba7100..f1a141fee 100644
--- a/STM32F4/cores/maple/libmaple/gpio.h
+++ b/STM32F4/cores/maple/libmaple/gpio.h
@@ -46,7 +46,7 @@ extern "C"{
  * @brief Get a GPIO port's corresponding afio_exti_port.
  * @param dev GPIO device whose afio_exti_port to return.
  */
-static inline afio_exti_port gpio_exti_port(gpio_dev *dev) {
+static inline afio_exti_port gpio_exti_port(const gpio_dev *dev) {
     return dev->exti_port;
 }
 
@@ -61,18 +61,18 @@ static inline afio_exti_port gpio_exti_port(gpio_dev *dev) {
  */
 static inline void gpio_write_pin(uint8_t pin, uint8 val) {
     if (val) {
-        (PIN_MAP[pin].gpio_device)->regs->BSRRL = BIT(PIN_MAP[pin].gpio_bit);
+        (PIN_MAP[pin].gpio_device)->regs->BSRRL = BIT(pin&0x0F);
     } else {
-        (PIN_MAP[pin].gpio_device)->regs->BSRRH = BIT(PIN_MAP[pin].gpio_bit);
+        (PIN_MAP[pin].gpio_device)->regs->BSRRH = BIT(pin&0x0F);
     }
 }
 
 static inline void gpio_set_pin(uint8_t pin) {
-	(PIN_MAP[pin].gpio_device)->regs->BSRRL = BIT(PIN_MAP[pin].gpio_bit);
+	(PIN_MAP[pin].gpio_device)->regs->BSRRL = BIT(pin&0x0F);
 }
 
 static inline void gpio_clear_pin(uint8_t pin) {
-	(PIN_MAP[pin].gpio_device)->regs->BSRRH = BIT(PIN_MAP[pin].gpio_bit);
+	(PIN_MAP[pin].gpio_device)->regs->BSRRH = BIT(pin&0x0F);
 }
 
 /**
@@ -85,7 +85,7 @@ static inline void gpio_clear_pin(uint8_t pin) {
  * @return True if the pin is set, false otherwise.
  */
 static inline uint32 gpio_read_pin(uint8_t pin) {
-    return (PIN_MAP[pin].gpio_device)->regs->IDR & BIT(PIN_MAP[pin].gpio_bit);
+    return (PIN_MAP[pin].gpio_device)->regs->IDR & BIT(pin&0x0F);
 }
 
 /**
@@ -94,14 +94,14 @@ static inline uint32 gpio_read_pin(uint8_t pin) {
  * @param pin Pin on dev to toggle.
  */
 static inline void gpio_toggle_pin(uint8_t pin) {
-    (PIN_MAP[pin].gpio_device)->regs->ODR = (PIN_MAP[pin].gpio_device)->regs->ODR ^ BIT(PIN_MAP[pin].gpio_bit);
+    (PIN_MAP[pin].gpio_device)->regs->ODR = (PIN_MAP[pin].gpio_device)->regs->ODR ^ BIT(pin&0x0F);
 }
 
 /*
  * GPIO Convenience routines
  */
 
-extern void gpio_init(gpio_dev *dev);
+extern void gpio_init(const gpio_dev *dev);
 extern void gpio_init_all(void);
 extern void gpio_set_mode(uint8_t pin, gpio_pin_mode mode);
 extern void gpio_set_af_mode(uint8_t pin, int mode);
diff --git a/STM32F4/cores/maple/libmaple/gpioF4.c b/STM32F4/cores/maple/libmaple/gpioF4.c
index fe3cc876f..67d3bea53 100644
--- a/STM32F4/cores/maple/libmaple/gpioF4.c
+++ b/STM32F4/cores/maple/libmaple/gpioF4.c
@@ -24,8 +24,6 @@
  * SOFTWARE.
  *****************************************************************************/
 
-#ifdef STM32F4
- 
 /**
  * @file gpio.c
  * @brief GPIO initialization routine
@@ -38,64 +36,57 @@
  * GPIO devices
  */
 
-gpio_dev gpioa = {
+/** GPIO port A device. */
+const gpio_dev GPIOA = {
     .regs      = GPIOA_BASE,
     .clk_id    = RCC_GPIOA,
     .exti_port = AFIO_EXTI_PA,
 };
-/** GPIO port A device. */
-gpio_dev* const GPIOA = &gpioa;
 
-gpio_dev gpiob = {
+/** GPIO port B device. */
+const gpio_dev GPIOB = {
     .regs      = GPIOB_BASE,
     .clk_id    = RCC_GPIOB,
     .exti_port = AFIO_EXTI_PB,
 };
-/** GPIO port B device. */
-gpio_dev* const GPIOB = &gpiob;
 
-gpio_dev gpioc = {
+/** GPIO port C device. */
+const gpio_dev GPIOC = {
     .regs      = GPIOC_BASE,
     .clk_id    = RCC_GPIOC,
     .exti_port = AFIO_EXTI_PC,
 };
-/** GPIO port C device. */
-gpio_dev* const GPIOC = &gpioc;
 
-gpio_dev gpiod = {
+/** GPIO port D device. */
+const gpio_dev GPIOD = {
     .regs      = GPIOD_BASE,
     .clk_id    = RCC_GPIOD,
     .exti_port = AFIO_EXTI_PD,
 };
-/** GPIO port D device. */
-gpio_dev* const GPIOD = &gpiod;
 
 #ifdef STM32_HIGH_DENSITY
-gpio_dev gpioe = {
+/** GPIO port E device. */
+const gpio_dev GPIOE = {
     .regs      = GPIOE_BASE,
     .clk_id    = RCC_GPIOE,
     .exti_port = AFIO_EXTI_PE,
 };
-/** GPIO port E device. */
-gpio_dev* const GPIOE = &gpioe;
 
  #if 0 // not available on LQFP 100 package
-gpio_dev gpiof = {
+/** GPIO port F device. */
+const gpio_dev GPIOF = {
     .regs      = GPIOF_BASE,
     .clk_id    = RCC_GPIOF,
     .exti_port = AFIO_EXTI_PF,
 };
-/** GPIO port F device. */
-gpio_dev* const GPIOF = &gpiof;
 
-gpio_dev gpiog = {
+/** GPIO port G device. */
+const gpio_dev GPIOG = {
     .regs      = GPIOG_BASE,
     .clk_id    = RCC_GPIOG,
     .exti_port = AFIO_EXTI_PG,
 };
-/** GPIO port G device. */
-gpio_dev* const GPIOG = &gpiog;
- #endif // not available on LQFP 100 package
+#endif
 #endif
 
 /*
@@ -109,7 +100,7 @@ gpio_dev* const GPIOG = &gpiog;
  *
  * @param dev GPIO device to initialize.
  */
-void gpio_init(gpio_dev *dev) {
+void gpio_init(const gpio_dev *dev) {
     rcc_clk_enable(dev->clk_id);
     rcc_reset_dev(dev->clk_id);
 }
@@ -118,13 +109,13 @@ void gpio_init(gpio_dev *dev) {
  * Initialize and reset all available GPIO devices.
  */
 void gpio_init_all(void) {
-    gpio_init(GPIOA);
-    gpio_init(GPIOB);
-    gpio_init(GPIOC);
-    gpio_init(GPIOD);
+    gpio_init(&GPIOA);
+    gpio_init(&GPIOB);
+    gpio_init(&GPIOC);
+    gpio_init(&GPIOD);
 
 #ifdef STM32_HIGH_DENSITY
-	gpio_init(GPIOE);
+	gpio_init(&GPIOE);
   #if 0 // not available on LQFP 100 package
 	gpio_init(GPIOF);
 	gpio_init(GPIOG);
@@ -154,7 +145,7 @@ void gpio_init_all(void) {
  */
 void gpio_set_mode(uint8_t io_pin, gpio_pin_mode mode) {
     gpio_reg_map *regs = (PIN_MAP[io_pin].gpio_device)->regs;
-	uint8_t pin = PIN_MAP[io_pin].gpio_bit;
+	uint8_t pin = io_pin&0x0f;
 
 	//regs->AFR[pin/8] = (regs->AFR[pin/8] & ~(15 << (4*(pin&7)))) | (((mode >> 8) & 15) << (4*(pin&7)));
 	//gpio_set_af_mode(dev, pin, mode>>8);
@@ -175,7 +166,7 @@ void gpio_set_mode(uint8_t io_pin, gpio_pin_mode mode) {
  */
 void gpio_set_af_mode(uint8_t io_pin, int mode) {
     gpio_reg_map *regs = (PIN_MAP[io_pin].gpio_device)->regs;
-	uint8_t pin = PIN_MAP[io_pin].gpio_bit;
+	uint8_t pin = io_pin&0x0F;
 
 	regs->AFR[pin>>3] = (regs->AFR[pin>>3] & ~(15 << ((pin&7)<<2))) | (((mode >> 0) & 15) << ((pin&7)<<2));
 }
@@ -226,5 +217,3 @@ void afio_remap(afio_remap_peripheral remapping) {
     }
 }
 #endif
-
-#endif
diff --git a/STM32F4/cores/maple/libmaple/gpio_def.h b/STM32F4/cores/maple/libmaple/gpio_def.h
index e2176eacb..cd1fb3843 100644
--- a/STM32F4/cores/maple/libmaple/gpio_def.h
+++ b/STM32F4/cores/maple/libmaple/gpio_def.h
@@ -89,17 +89,12 @@ typedef struct gpio_dev {
     afio_exti_port exti_port; /**< AFIO external interrupt port value */
 } gpio_dev;
 
-extern gpio_dev gpioa;
-extern gpio_dev* const GPIOA;
-extern gpio_dev gpiob;
-extern gpio_dev* const GPIOB;
-extern gpio_dev gpioc;
-extern gpio_dev* const GPIOC;
-extern gpio_dev gpiod;
-extern gpio_dev* const GPIOD;
+extern const gpio_dev GPIOA;
+extern const gpio_dev GPIOB;
+extern const gpio_dev GPIOC;
+extern const gpio_dev GPIOD;
 #ifdef STM32_HIGH_DENSITY
-extern gpio_dev gpioe;
-extern gpio_dev* const GPIOE;
+extern const gpio_dev GPIOE;
  #if 0 // not available on LQFP 100 package
 extern gpio_dev gpiof;
 extern gpio_dev* const GPIOF;
diff --git a/STM32F4/cores/maple/libmaple/spi.h b/STM32F4/cores/maple/libmaple/spi.h
index f96b462b5..abed68c12 100644
--- a/STM32F4/cores/maple/libmaple/spi.h
+++ b/STM32F4/cores/maple/libmaple/spi.h
@@ -213,7 +213,6 @@ typedef struct spi_dev {
 
 void spi_init(spi_dev *dev);
 
-struct gpio_dev;
 /**
  * @brief Configure GPIO bit modes for use as a SPI port's pins.
  *
diff --git a/STM32F4/cores/maple/libmaple/timer.c b/STM32F4/cores/maple/libmaple/timer.c
index 83e9ace33..f8e55a185 100644
--- a/STM32F4/cores/maple/libmaple/timer.c
+++ b/STM32F4/cores/maple/libmaple/timer.c
@@ -44,7 +44,7 @@
 /* Update only. */
 #define NR_BAS_HANDLERS                 1
 
-static timer_dev timer1 = {
+timer_dev timer1 = {
     .regs         = { .adv = TIMER1_BASE },
     .clk_id       = RCC_TIMER1,
     .type         = TIMER_ADVANCED,
@@ -53,7 +53,7 @@ static timer_dev timer1 = {
 /** Timer 1 device (advanced) */
 timer_dev *TIMER1 = &timer1;
 
-static timer_dev timer2 = {
+timer_dev timer2 = {
     .regs         = { .gen = TIMER2_BASE },
     .clk_id       = RCC_TIMER2,
     .type         = TIMER_GENERAL,
@@ -62,7 +62,7 @@ static timer_dev timer2 = {
 /** Timer 2 device (general-purpose) */
 timer_dev *TIMER2 = &timer2;
 
-static timer_dev timer3 = {
+timer_dev timer3 = {
     .regs         = { .gen = TIMER3_BASE },
     .clk_id       = RCC_TIMER3,
     .type         = TIMER_GENERAL,
@@ -71,7 +71,7 @@ static timer_dev timer3 = {
 /** Timer 3 device (general-purpose) */
 timer_dev *TIMER3 = &timer3;
 
-static timer_dev timer4 = {
+timer_dev timer4 = {
     .regs         = { .gen = TIMER4_BASE },
     .clk_id       = RCC_TIMER4,
     .type         = TIMER_GENERAL,
@@ -81,7 +81,7 @@ static timer_dev timer4 = {
 timer_dev *TIMER4 = &timer4;
 
 #ifdef STM32_HIGH_DENSITY
-static timer_dev timer5 = {
+timer_dev timer5 = {
     .regs         = { .gen = TIMER5_BASE },
     .clk_id       = RCC_TIMER5,
     .type         = TIMER_GENERAL,
@@ -90,7 +90,7 @@ static timer_dev timer5 = {
 /** Timer 5 device (general-purpose) */
 timer_dev *TIMER5 = &timer5;
 
-static timer_dev timer6 = {
+timer_dev timer6 = {
     .regs         = { .bas = TIMER6_BASE },
     .clk_id       = RCC_TIMER6,
     .type         = TIMER_BASIC,
@@ -99,7 +99,7 @@ static timer_dev timer6 = {
 /** Timer 6 device (basic) */
 timer_dev *TIMER6 = &timer6;
 
-static timer_dev timer7 = {
+timer_dev timer7 = {
     .regs         = { .bas = TIMER7_BASE },
     .clk_id       = RCC_TIMER7,
     .type         = TIMER_BASIC,
@@ -108,7 +108,7 @@ static timer_dev timer7 = {
 /** Timer 7 device (basic) */
 timer_dev *TIMER7 = &timer7;
 
-static timer_dev timer8 = {
+timer_dev timer8 = {
     .regs         = { .adv = TIMER8_BASE },
     .clk_id       = RCC_TIMER8,
     .type         = TIMER_ADVANCED,
diff --git a/STM32F4/cores/maple/usb_serial.cpp b/STM32F4/cores/maple/usb_serial.cpp
index cfeb382ea..fadcb91af 100644
--- a/STM32F4/cores/maple/usb_serial.cpp
+++ b/STM32F4/cores/maple/usb_serial.cpp
@@ -134,7 +134,7 @@ uint8 USBSerial::pending(void) {
     return usbGetPending();
 }
 
-uint8 USBSerial::isConnected(void) {
+USBSerial::operator bool() {
     return usbIsConnected() && usbIsConfigured();
 }
 
diff --git a/STM32F4/cores/maple/usb_serial.h b/STM32F4/cores/maple/usb_serial.h
index 301dc4baf..8eeed966a 100644
--- a/STM32F4/cores/maple/usb_serial.h
+++ b/STM32F4/cores/maple/usb_serial.h
@@ -59,7 +59,8 @@ class USBSerial : public Stream {
 
     uint8 getRTS();
     uint8 getDTR();
-    uint8 isConnected();
+	operator bool();
+	uint8 isConnected() { return (bool) *this; }
     uint8 pending();
 
     void enableBlockingTx(void);
@@ -67,9 +68,14 @@ class USBSerial : public Stream {
 };
 
 extern USBSerial SerialUSB;
+#define Serial SerialUSB
 
-#endif
+#else //  _USB_SERIAL_H_
 
+#define Serial Serial1
 
-#endif
+#endif //  SERIAL_USB
+
+
+#endif //  _USB_SERIAL_H_
 
diff --git a/STM32F4/cores/maple/wirish.h b/STM32F4/cores/maple/wirish.h
index d9a17bfdd..945e8fb94 100644
--- a/STM32F4/cores/maple/wirish.h
+++ b/STM32F4/cores/maple/wirish.h
@@ -58,7 +58,6 @@
   #define false 0x0
 #endif
 
-
 #define lowByte(w)                     ((w) & 0xFF)
 #define highByte(w)                    (((w) >> 8) & 0xFF)
 #define bitRead(value, bit)            (((value) >> (bit)) & 0x01)
diff --git a/STM32F4/cores/maple/wirish_types.h b/STM32F4/cores/maple/wirish_types.h
index aea86fbd8..6a8c85c3e 100644
--- a/STM32F4/cores/maple/wirish_types.h
+++ b/STM32F4/cores/maple/wirish_types.h
@@ -50,13 +50,11 @@
 #ifdef BOARD_generic_f407v
 // restructure members to build consecutive pairs
 typedef struct stm32_pin_info {
-    gpio_dev *gpio_device;      /**< Maple pin's GPIO device */
-    uint8 gpio_bit;             /**< Pin's GPIO port bit. */
-    timer_dev *timer_device;    /**< Pin's timer device, if any. */
+    const gpio_dev * gpio_device;      /**< Maple pin's GPIO device */
+    timer_dev * timer_device;    /**< Pin's timer device, if any. */
     uint8 timer_channel;        /**< Timer channel, or 0 if none. */
-    const adc_dev *adc_device;  /**< ADC device, if any. */
     uint8 adc_channel;          /**< Pin ADC channel, or ADCx if none. */
-    uint8 filler;
+    const adc_dev *adc_device;  /**< ADC device, if any. */
 } stm32_pin_info;
 
 #else
diff --git a/STM32F4/libraries/SPI/src/SPI.h b/STM32F4/libraries/SPI/src/SPI.h
index 1b01d9b25..39a5a9eac 100644
--- a/STM32F4/libraries/SPI/src/SPI.h
+++ b/STM32F4/libraries/SPI/src/SPI.h
@@ -397,5 +397,4 @@ class SPIClass {
 };
 
 
-extern SPIClass SPI;//(1);// dummy params
 #endif
diff --git a/STM32F4/variants/generic_f407v/black_f4.h.old b/STM32F4/variants/generic_f407v/black_f4.h.old
deleted file mode 100644
index 20bb174c3..000000000
--- a/STM32F4/variants/generic_f407v/black_f4.h.old
+++ /dev/null
@@ -1,130 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2011 LeafLabs, LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file   black_f4.h
- * @author Marti Bolivar <mbolivar@leaflabs.com>
- * @brief  Private include file for Maple Native in boards.h
- *
- * See maple.h for more information on these definitions.
- */
-
-#ifndef _BOARD_BLACK_F4_H_
-#define _BOARD_BLACK_F4_H_
-
-#define Port2Pin(port, bit) ((port-'A')*16+bit)
-
-#define CYCLES_PER_MICROSECOND  168
-
-
-#undef  STM32_PCLK1
-#undef  STM32_PCLK2
-#define STM32_PCLK1   (CYCLES_PER_MICROSECOND*1000000/4)
-#define STM32_PCLK2   (CYCLES_PER_MICROSECOND*1000000/2)
-
-#define SYSTICK_RELOAD_VAL      (CYCLES_PER_MICROSECOND*1000-1)
-
-#define BOARD_USB_DM_PIN		PA11
-#define BOARD_USB_DP_PIN		PA12
-
-#define BOARD_LED_PIN           PA6 //Port2Pin('A', 6)
-#define BOARD_LED2_PIN          PA7 //Port2Pin('A', 7)
-#define BOARD_BUTTON1_PIN       PA0 //Port2Pin('A', 0)
-#define BOARD_BUTTON2_PIN       PE4 //Port2Pin('E', 4)
-#define BOARD_BUTTON3_PIN       PE3 //Port2Pin('E', 3)
-
-#define BOARD_NR_USARTS         5
-#define BOARD_USART1_TX_PIN     PA9  //Port2Pin('A', 9)
-#define BOARD_USART1_RX_PIN     PA10 //Port2Pin('A',10)
-#define BOARD_USART2_TX_PIN     PA2  //Port2Pin('A', 2)
-#define BOARD_USART2_RX_PIN     PA3  //Port2Pin('A', 3)
-#define BOARD_USART3_TX_PIN     PB10 //Port2Pin('B',10)
-#define BOARD_USART3_RX_PIN     PB11 //Port2Pin('B',11)
-#define BOARD_UART4_TX_PIN      PA0  //Port2Pin('A', 0)
-#define BOARD_UART4_RX_PIN      PA1  //Port2Pin('A', 1)
-#define BOARD_UART5_TX_PIN      PC12 //Port2Pin('C',12)
-#define BOARD_UART5_RX_PIN      PD2  //Port2Pin('D', 2)
-
-#define BOARD_NR_SPI            3
-#define BOARD_SPI1_NSS_PIN      PA4  //Port2Pin('A', 4)
-#define BOARD_SPI1_SCK_PIN      PA5  //Port2Pin('A', 5)
-#define BOARD_SPI1_MISO_PIN     PA6  //Port2Pin('A', 6)
-#define BOARD_SPI1_MOSI_PIN     PA7  //Port2Pin('A', 7)
-#define BOARD_SPI1A_NSS_PIN     PA15 //Port2Pin('A',15)
-#define BOARD_SPI1A_SCK_PIN     PB3  //Port2Pin('B', 3)
-#define BOARD_SPI1A_MISO_PIN    PB4  //Port2Pin('B', 4)
-#define BOARD_SPI1A_MOSI_PIN    PB5  //Port2Pin('B', 5)
-
-#define BOARD_SPI2_NSS_PIN      PB12 //Port2Pin('B',12)
-#define BOARD_SPI2_SCK_PIN      PB13 //Port2Pin('B',13)
-#define BOARD_SPI2_MISO_PIN     PB14 //Port2Pin('B',14)
-#define BOARD_SPI2_MOSI_PIN     PB15 //Port2Pin('B',15)
-#define BOARD_SPI2A_NSS_PIN     PB9  //Port2Pin('B', 9)
-#define BOARD_SPI2A_SCK_PIN     PB10 //Port2Pin('B',10)
-#define BOARD_SPI2A_MISO_PIN    PC2  //Port2Pin('C', 2)
-#define BOARD_SPI2A_MOSI_PIN    pc3  //Port2Pin('C', 3)
-
-#define BOARD_SPI3_NSS_PIN      PA15 //Port2Pin('A',15)
-#define BOARD_SPI3_SCK_PIN      PB3  //Port2Pin('B', 3)
-#define BOARD_SPI3_MISO_PIN     PB4  //Port2Pin('B', 4)
-#define BOARD_SPI3_MOSI_PIN     PB5  //Port2Pin('B', 5)
-/* overlap with the SDIO interface for SD card
-#define BOARD_SPI3A_NSS_PIN     Port2Pin('A', 4)
-#define BOARD_SPI3A_SCK_PIN     Port2Pin('C',10)
-#define BOARD_SPI3A_MISO_PIN    Port2Pin('C',11)
-#define BOARD_SPI3A_MOSI_PIN    Port2Pin('C',12)
-*/
-#define BOARD_SDIO_D0           PC8  //Port2Pin('C', 8)
-#define BOARD_SDIO_D1           PC9  //Port2Pin('C', 9)
-#define BOARD_SDIO_D2           PC10 //Port2Pin('C',10)
-#define BOARD_SDIO_D3           PC11 //Port2Pin('C',11)
-#define BOARD_SDIO_CK           PC12 //Port2Pin('C',12)
-#define BOARD_SDIO_CMD          PD2  //Port2Pin('D', 2)
-
-#define BOARD_NR_GPIO_PINS      80
-#define BOARD_NR_PWM_PINS       22
-#define BOARD_NR_ADC_PINS       16
-#define BOARD_NR_USED_PINS      22
-#define BOARD_JTMS_SWDIO_PIN    PA13 //Port2Pin('A',13)
-#define BOARD_JTCK_SWCLK_PIN    PA14 //Port2Pin('A',14)
-#define BOARD_JTDI_PIN          PA15 //Port2Pin('A',15)
-#define BOARD_JTDO_PIN          PB3  //Port2Pin('B', 3)
-#define BOARD_NJTRST_PIN        PB4  //Port2Pin('B', 4)
-
-
-enum {
-PA0,PA1,PA2,PA3,PA4,PA5,PA6,PA7,PA8,PA9,PA10,PA11,PA12,PA13,PA14,PA15,
-PB0,PB1,PB2,PB3,PB4,PB5,PB6,PB7,PB8,PB9,PB10,PB11,PB12,PB13,PB14,PB15,
-PC0,PC1,PC2,PC3,PC4,PC5,PC6,PC7,PC8,PC9,PC10,PC11,PC12,PC13,PC14,PC15,
-PD0,PD1,PD2,PD3,PD4,PD5,PD6,PD7,PD8,PD9,PD10,PD11,PD12,PD13,PD14,PD15,
-PE0,PE1,PE2,PE3,PE4,PE5,PE6,PE7,PE8,PE9,PE10,PE11,PE12,PE13,PE14,PE15,
-#if 0 // not available on LQFP100 package
-PF0,PF1,PF2,PF3,PF4,PF5,PF6,PF7,PF8,PF9,PF10,PF11,PF12,PF13,PF14,PF15,
-PG0,PG1,PG2,PG3,PG4,PG5,PG6,PG7,PG8,PG9,PG10,PG11,PG12,PG13,PG14,PG15
-#endif
-};
-
-#endif
diff --git a/STM32F4/variants/generic_f407v/generic_f407v.cpp b/STM32F4/variants/generic_f407v/generic_f407v.cpp
index a4a5ecbb4..c51ff9b55 100644
--- a/STM32F4/variants/generic_f407v/generic_f407v.cpp
+++ b/STM32F4/variants/generic_f407v/generic_f407v.cpp
@@ -34,12 +34,7 @@
 
 #include "generic_f407v.h"
 
-//#include "fsmc.h"
-#include <libmaple/gpio.h>
-#include <libmaple/rcc.h>
-#include <libmaple/timer.h>
-
-#include <wirish_types.h>
+#include "wirish_types.h"
 
 //static void initSRAMChip(void);
 /*****************************************************************************/
@@ -70,155 +65,6 @@ void boardInit(void) {
 	return;
 }
 
-/*
-typedef struct stm32_pin_info {
-    gpio_dev *gpio_device;      // Maple pin's GPIO device
-    uint8 gpio_bit;             // Pin's GPIO port bit.
-    timer_dev *timer_device;    // Pin's timer device, if any.
-    uint8 timer_channel;        // Timer channel, or 0 if none.
-    const adc_dev *adc_device;  // ADC device, if any.
-    uint8 adc_channel;          // Pin ADC channel, or ADCx if none.
-} stm32_pin_info;
-*/
-
-extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = { // LQFP100 package pin
-    {GPIOA,  0, TIMER5, 1, ADC1,    0}, // D00/PA0  | 23 | USART2_CTS | UART4_TX       | ETH_MII_CRS      | TIM2_CH1_ETR   | TIM5_CH1       | TIM8_ETR                      | ADC123_IN0/WKUP
-    {GPIOA,  1, TIMER5, 2, ADC1,    1}, // D01/PA1  | 24 | USART2_RTS | UART4_RX       | ETH_RMII_REF_CLK | ETH_MII_RX_CLK | TIM5_CH2       | TIM2_CH2                      | ADC123_IN1
-    {GPIOA,  2, TIMER5, 3, ADC1,    2}, // D02/PA2  | 25 | USART2_TX  | TIM5_CH3       | TIM9_CH1         | TIM2_CH3       | ETH_MDIO                                       | ADC123_IN2
-    {GPIOA,  3, TIMER5, 4, ADC1,    3}, // D03/PA3  | 26 | USART2_RX  | TIM5_CH4       | TIM9_CH2         | TIM2_CH4       | OTG_HS_ULPI_D0 | ETH_MII_COL                   | ADC123_IN3
-    {GPIOA,  4,   NULL, 0, ADC1,    4}, // D04/PA4  | 29 | SPI1_NSS   | SPI3_NSS       | USART2_CK        | DCMI_HSYNC     | OTG_HS_SOF     | I2S3_WS                       | ADC12_IN4 / DAC_OUT1
-    {GPIOA,  5,   NULL, 0, ADC1,    5}, // D05/PA5  | 30 | SPI1_SCK   | OTG_HS_ULPI_CK | TIM2_CH1_ETR     | TIM8_CH1N                                                       | ADC12_IN5 / DAC_OUT2
-    {GPIOA,  6,   NULL, 1, ADC1,    6}, // D06/PA6  | 31 | SPI1_MISO  | TIM8_BKIN      | TIM13_CH1        | DCMI_PIXCLK    | TIM3_CH1       | TIM1_BKIN                     | ADC12_IN6
-    {GPIOA,  7,   NULL, 0, ADC1,    7}, // D07/PA7  | 32 | SPI1_MOSI  | TIM8_CH1N      | TIM14_CH1        | TIM3_CH2       | ETH_MII_RX_DV  | TIM1_CH1N   / ETH_RMII_CRS_DV | ADC12_IN7
-    {GPIOA,  8,   NULL, 0, NULL, ADCx}, // D08/PA8  | 67 | MCO1       | USART1_CK      | TIM1_CH1         | I2C3_SCL       | OTG_FS_SOF
-    {GPIOA,  9,   NULL, 0, NULL, ADCx}, // D09/PA9  | 68 | USART1_TX  | TIM1_CH2       | I2C3_SMBA        | DCMI_D0
-    {GPIOA, 10,   NULL, 0, NULL, ADCx}, // D10/PA10 | 69 | USART1_RX  | TIM1_CH3       | OTG_FS_ID        | DCMI_D1
-    {GPIOA, 11,   NULL, 0, NULL, ADCx}, // D11/PA11 | 70 | USART1_CTS | CAN1_RX        | TIM1_CH4         | OTG_FS_DM
-    {GPIOA, 12,   NULL, 0, NULL, ADCx}, // D12/PA12 | 71 | USART1_RTS | CAN1_TX        | TIM1_ETR         | OTG_FS_DP
-    {GPIOA, 13,   NULL, 0, NULL, ADCx}, // D13/PA13 | 72 | JTMS-SWDIO
-    {GPIOA, 14,   NULL, 0, NULL, ADCx}, // D14/PA14 | 76 | JTCK-SWCLK
-    {GPIOA, 15, TIMER2, 1, NULL, ADCx}, // D15/PA15 | 77 | JTDI       | SPI3_NSS       | I2S3_WS          | TIM2_CH1_ETR   | SPI1_NSS
-
-    {GPIOB,  0, TIMER3, 3, ADC1,    8}, // D16/PB0  | 35 | TIM3_CH3   | TIM8_CH2N | OTG_HS_ULPI_D1 | ETH_MII_RXD2   | TIM1_CH2N      | ADC12_IN8
-    {GPIOB,  1, TIMER3, 4, ADC1,    9}, // D17/PB1  | 36 | TIM3_CH4   | TIM8_CH3N | OTG_HS_ULPI_D2 | ETH_MII_RXD3   | TIM1_CH3N      | ADC12_IN9
-    {GPIOB,  2,   NULL, 0, NULL, ADCx}, // D18/PB2  | 37 | BOOT1    
-    {GPIOB,  3, TIMER2, 2, NULL, ADCx}, // D19/PB3  | 89 | JTDO       | TRACESWO  | SPI3_SCK       | I2S3_CK        | TIM2_CH2       | SPI1_SCK
-    {GPIOB,  4, TIMER3, 1, NULL, ADCx}, // D20/PB4  | 90 | NJTRST     | SPI3_MISO | TIM3_CH1       | SPI1_MISO      | I2S3ext_SD
-    {GPIOB,  5, TIMER3, 2, NULL, ADCx}, // D21/PB5  | 91 | I2C1_SMBA  | CAN2_RX   | OTG_HS_ULPI_D7 | ETH_PPS_OUT    | TIM3_CH2       | SPI1_MOSI      | SPI3_MOSI      | DCMI_D10      | I2S3_SD
-    {GPIOB,  6,   NULL, 0, NULL, ADCx}, // D22/PB6  | 92 | I2C1_SCL   | TIM4_CH1  | CAN2_TX        | DCMI_D5        | USART1_TX
-    {GPIOB,  7,   NULL, 0, NULL, ADCx}, // D23/PB7  | 93 | I2C1_SDA   | FSMC_NL   | DCMI_VSYNC     | USART1_RX      | TIM4_CH2
-    {GPIOB,  8,   NULL, 0, NULL, ADCx}, // D24/PB8  | 95 | TIM4_CH3   | SDIO_D4   | TIM10_CH1      | DCMI_D6        | ETH_MII_TXD3   | I2C1_SCL       | CAN1_RX
-    {GPIOB,  9,   NULL, 0, NULL, ADCx}, // D25/PB9  | 96 | SPI2_NSS   | I2S2_WS   | TIM4_CH4       | TIM11_CH1      | SDIO_D5        | DCMI_D7        | I2C1_SDA       | CAN1_TX
-    {GPIOB, 10,   NULL, 0, NULL, ADCx}, // D26/PB10 | 47 | SPI2_SCK   | I2S2_CK   | I2C2_SCL       | USART3_TX      | OTG_HS_ULPI_D3 | ETH_MII_RX_ER  | TIM2_CH3
-    {GPIOB, 11,   NULL, 0, NULL, ADCx}, // D27/PB11 | 48 | I2C2_SDA   | USART3_RX | OTG_HS_ULPI_D4 | ETH_RMII_TX_EN | ETH_MII_TX_EN  | TIM2_CH4
-    {GPIOB, 12,   NULL, 0, NULL, ADCx}, // D28/PB12 | 51 | SPI2_NSS   | I2S2_WS   | I2C2_SMBA      | USART3_CK      | TIM1_BKIN      | CAN2_RX        | OTG_HS_ULPI_D5 | ETH_RMII_TXD0 | ETH_MII_TXD0 | OTG_HS_ID
-    {GPIOB, 13,   NULL, 0, NULL, ADCx}, // D29/PB13 | 52 | SPI2_SCK   | I2S2_CK   | USART3_CTS     | TIM1_CH1N      | CAN2_TX        | OTG_HS_ULPI_D6 | ETH_RMII_TXD1  | ETH_MII_TXD1
-    {GPIOB, 14,   NULL, 0, NULL, ADCx}, // D30/PB14 | 53 | SPI2_MISO  | TIM1_CH2N | TIM12_CH1      | OTG_HS_DM      | USART3_RTS     | TIM8_CH2N      | I2S2ext_SD
-    {GPIOB, 15,   NULL, 0, NULL, ADCx}, // D31/PB15 | 54 | SPI2_MOSI  | I2S2_SD   | TIM1_CH3N      | TIM8_CH3N      | TIM12_CH2      | OTG_HS_DP
-
-    {GPIOC,  0,   NULL, 0, ADC1,   10}, // D32/PC0  | 15 | OTG_HS_ULPI_STP                                                  | ADC123_IN10
-    {GPIOC,  1,   NULL, 0, ADC1,   11}, // D33/PC1  | 16 | ETH_MDC                                                          | ADC123_IN11
-    {GPIOC,  2,   NULL, 0, ADC1,   12}, // D34/PC2  | 17 | SPI2_MISO  | OTG_HS_ULPI_DIR  | ETH_MII_TXD2    | I2S2ext_SD     | ADC123_IN12
-    {GPIOC,  3,   NULL, 0, ADC1,   13}, // D35/PC3  | 18 | SPI2_MOSI  | I2S2_SD          | OTG_HS_ULPI_NXT | ETH_MII_TX_CLK | ADC123_IN13
-    {GPIOC,  4,   NULL, 0, ADC1,   14}, // D36/PC4  | 33 | ETH_RMII_RX_D0                | ETH_MII_RX_D0                    | ADC12_IN14
-    {GPIOC,  5,   NULL, 0, ADC1,   15}, // D37/PC5  | 34 | ETH_RMII_RX_D1                | ETH_MII_RX_D1                    | ADC12_IN15
-    {GPIOC,  6, TIMER8, 1, NULL, ADCx}, // D38/PC6  | 63 | I2S2_MCK   | TIM8_CH1/SDIO_D6 | USART6_TX       | DCMI_D0/TIM3_CH1 
-    {GPIOC,  7, TIMER8, 2, NULL, ADCx}, // D39/PC7  | 64 | I2S3_MCK   | TIM8_CH2/SDIO_D7 | USART6_RX       | DCMI_D1/TIM3_CH2
-    {GPIOC,  8, TIMER8, 3, NULL, ADCx}, // D40/PC8  | 65 | TIM8_CH3   | SDIO_D0          | TIM3_CH3        | USART6_CK      | DCMI_D2
-    {GPIOC,  9, TIMER8, 4, NULL, ADCx}, // D41/PC9  | 66 | I2S_CKIN   | MCO2             | TIM8_CH4        | SDIO_D1        | I2C3_SDA  | DCMI_D3    | TIM3_CH4
-    {GPIOC, 10,   NULL, 0, NULL, ADCx}, // D42/PC10 | 78 | SPI3_SCK   | I2S3_CK          | UART4_TX        | SDIO_D2        | DCMI_D8   | USART3_TX
-    {GPIOC, 11,   NULL, 0, NULL, ADCx}, // D43/PC11 | 79 | UART4_RX   | SPI3_MISO        | SDIO_D3         | DCMI_D4        | USART3_RX | I2S3ext_SD
-    {GPIOC, 12,   NULL, 0, NULL, ADCx}, // D44/PC12 | 80 | UART5_TX   | SDIO_CK          | DCMI_D9         | SPI3_MOSI      | I2S3_SD   | USART3_CK
-    {GPIOC, 13,   NULL, 0, NULL, ADCx}, // D45/PC13 |  7 | RTC_OUT, RTC_TAMP1, RTC_TS
-    {GPIOC, 14,   NULL, 0, NULL, ADCx}, // D46/PC14 |  8 | OSC32_IN
-    {GPIOC, 15,   NULL, 0, NULL, ADCx}, // D47/PC15 |  9 | OSC32_OUT
-                       
-    {GPIOD,  0,   NULL, 0, NULL, ADCx}, // D48/PD0  | 81 | FSMC_D2    | CAN1_RX
-    {GPIOD,  1,   NULL, 0, NULL, ADCx}, // D49/PD1  | 82 | FSMC_D3    | CAN1_TX
-    {GPIOD,  2,   NULL, 0, NULL, ADCx}, // D50/PD2  | 83 | TIM3_ETR   | UART5_RX   | SDIO_CMD | DCMI_D11
-    {GPIOD,  3,   NULL, 0, NULL, ADCx}, // D51/PD3  | 84 | FSMC_CLK   | USART2_CTS
-    {GPIOD,  4,   NULL, 0, NULL, ADCx}, // D52/PD4  | 85 | FSMC_NOE   | USART2_RTS
-    {GPIOD,  5,   NULL, 0, NULL, ADCx}, // D53/PD5  | 86 | FSMC_NWE   | USART2_TX
-    {GPIOD,  6,   NULL, 0, NULL, ADCx}, // D54/PD6  | 87 | FSMC_NWAIT | USART2_RX
-    {GPIOD,  7,   NULL, 0, NULL, ADCx}, // D55/PD7  | 88 | USART2_CK  | FSMC_NE1   | FSMC_NCE2
-    {GPIOD,  8,   NULL, 0, NULL, ADCx}, // D56/PD8  | 55 | FSMC_D13   | USART3_TX
-    {GPIOD,  9,   NULL, 0, NULL, ADCx}, // D57/PD9  | 56 | FSMC_D14   | USART3_RX
-    {GPIOD, 10,   NULL, 0, NULL, ADCx}, // D58/PD10 | 57 | FSMC_D15   | USART3_CK
-    {GPIOD, 11,   NULL, 0, NULL, ADCx}, // D59/PD11 | 58 | FSMC_CLE   | FSMC_A16   | USART3_CTS
-    {GPIOD, 12, TIMER4, 1, NULL, ADCx}, // D60/PD12 | 59 | FSMC_ALE   | FSMC_A17   | TIM4_CH1   | USART3_RTS // remap in
-    {GPIOD, 13, TIMER4, 2, NULL, ADCx}, // D61/PD13 | 60 | FSMC_A18                | TIM4_CH2                // remap in
-    {GPIOD, 14, TIMER4, 3, NULL, ADCx}, // D62/PD14 | 61 | FSMC_D0                 | TIM4_CH3                // remap in
-    {GPIOD, 15, TIMER4, 4, NULL, ADCx}, // D63/PD15 | 62 | FSMC_D1                 | TIM4_CH4                // remap in
-
-    {GPIOE,  0,   NULL, 0, NULL, ADCx}, // D64/PE0  | 97 | TIM4_ETR  | FSMC_NBL0 | DCMI_D2
-    {GPIOE,  1,   NULL, 0, NULL, ADCx}, // D65/PE1  | 98 | FSMC_NBL1 | DCMI_D3
-    {GPIOE,  2,   NULL, 0, NULL, ADCx}, // D66/PE2  |  1 | TRACECLK  | FSMC_A23  | ETH_MII_TXD3
-    {GPIOE,  3,   NULL, 0, NULL, ADCx}, // D67/PE3  |  2 | TRACED0   | FSMC_A19
-    {GPIOE,  4,   NULL, 0, NULL, ADCx}, // D68/PE4  |  3 | TRACED1   | FSMC_A20  | DCMI_D4
-    {GPIOE,  5,   NULL, 0, NULL, ADCx}, // D69/PE5  |  4 | TRACED2   | FSMC_A21  | TIM9_CH1     / DCMI_D6
-    {GPIOE,  6,   NULL, 0, NULL, ADCx}, // D70/PE6  |  5 | TRACED3   | FSMC_A22  | TIM9_CH2     / DCMI_D7
-    {GPIOE,  7,   NULL, 0, NULL, ADCx}, // D71/PE7  | 38 | FSMC_D4   | TIM1_ETR
-    {GPIOE,  8,   NULL, 0, NULL, ADCx}, // D72/PE8  | 39 | FSMC_D5   | TIM1_CH1N
-    {GPIOE,  9, TIMER1, 1, NULL, ADCx}, // D73/PE9  | 40 | FSMC_D6   | TIM1_CH1   // remap in
-    {GPIOE, 10,   NULL, 0, NULL, ADCx}, // D74/PE10 | 41 | FSMC_D7   | TIM1_CH2N
-    {GPIOE, 11, TIMER1, 2, NULL, ADCx}, // D75/PE11 | 42 | FSMC_D8   | TIM1_CH2   // remap in
-    {GPIOE, 12,   NULL, 0, NULL, ADCx}, // D76/PE12 | 43 | FSMC_D9   | TIM1_CH3N
-    {GPIOE, 13, TIMER1, 3, NULL, ADCx}, // D77/PE13 | 44 | FSMC_D10  | TIM1_CH3   // remap in
-    {GPIOE, 14, TIMER1, 4, NULL, ADCx}, // D78/PE14 | 45 | FSMC_D11  | TIM1_CH4   // remap in
-    {GPIOE, 15,   NULL, 0, NULL, ADCx}, // D79/PE15 | 46 | FSMC_D12  | TIM1_BKIN
-#if 0
-    {GPIOF,  0,   NULL, 0, NULL, ADCx}, // D80/PF0
-    {GPIOF,  1,   NULL, 0, NULL, ADCx}, // D81/PF1
-    {GPIOF,  2,   NULL, 0, NULL, ADCx}, // D82/PF2
-    {GPIOF,  3,   NULL, 0, NULL, ADCx}, // D83/PF3
-    {GPIOF,  4,   NULL, 0, NULL, ADCx}, // D84/PF4
-    {GPIOF,  5,   NULL, 0, NULL, ADCx}, // D85/PF5
-    {GPIOF,  6,   NULL, 0, NULL, ADCx}, // D86/PF6
-    {GPIOF,  7,   NULL, 0, NULL, ADCx}, // D87/PF7
-    {GPIOF,  8,   NULL, 0, NULL, ADCx}, // D88/PF8
-    {GPIOF,  9,   NULL, 0, NULL, ADCx}, // D89/PF9
-    {GPIOF, 10,   NULL, 0, NULL, ADCx}, // D90/PF10
-    {GPIOF, 11,   NULL, 0, NULL, ADCx}, // D91/PF11
-    {GPIOF, 12,   NULL, 0, NULL, ADCx}, // D92/PF12
-    {GPIOF, 13,   NULL, 0, NULL, ADCx}, // D93/PF13
-    {GPIOF, 14,   NULL, 0, NULL, ADCx}, // D94/PF14
-    {GPIOF, 15,   NULL, 0, NULL, ADCx}, // D95/PF15
-
-    {GPIOG,  0,   NULL, 0, NULL, ADCx}, // D96/PG0
-    {GPIOG,  1,   NULL, 0, NULL, ADCx}, // D97/PG1
-    {GPIOG,  2,   NULL, 0, NULL, ADCx}, // D98/PG2
-    {GPIOG,  3,   NULL, 0, NULL, ADCx}, // D99/PG3
-    {GPIOG,  4,   NULL, 0, NULL, ADCx}, // D100/PG4
-    {GPIOG,  5,   NULL, 0, NULL, ADCx}, // D101/PG5
-    {GPIOG,  6,   NULL, 0, NULL, ADCx}, // D102/PG6
-    {GPIOG,  7,   NULL, 0, NULL, ADCx}, // D103/PG7 
-    {GPIOG,  8,   NULL, 0, NULL, ADCx}, // D104/PG8
-    {GPIOG,  9,   NULL, 0, NULL, ADCx}, // D105/PG9
-    {GPIOG, 10,   NULL, 0, NULL, ADCx}, // D106/PG10
-    {GPIOG, 11,   NULL, 0, NULL, ADCx}, // D107/PG11
-    {GPIOG, 12,   NULL, 0, NULL, ADCx}, // D108/PG12
-    {GPIOG, 13,   NULL, 0, NULL, ADCx}, // D109/PG13
-    {GPIOG, 14,   NULL, 0, NULL, ADCx}, // D110/PG14
-    {GPIOG, 15,   NULL, 0, NULL, ADCx}  // D111/PG15
-#endif
-};
-/* to be defined
-extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
-    0, 1, 2, 3, 15, 16, 17, 19, 20, 21, 38, 39, 49, 41, 60, 61, 62, 63, 73, 75, 77, 78
-};
-*/
-extern const uint8 boardADCPins[BOARD_NR_ADC_PINS] __FLASH__ = {
-    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PB0, PB1, PC0, PC1, PC2, PC3, PC4, PC5
-};
-
-extern const uint8 boardUsedPins[BOARD_NR_USED_PINS] __FLASH__ = {
-    BOARD_LED_PIN, BOARD_LED2_PIN, BOARD_BUTTON1_PIN, BOARD_BUTTON2_PIN, BOARD_BUTTON2_PIN,
-	BOARD_JTMS_SWDIO_PIN, BOARD_JTCK_SWCLK_PIN,
-	FLASH_CS_PIN, FLASH_CLK_PIN, FLASH_DO_PIN, FLASH_DI_PIN,
-	NRF24_CE_PIN, NRF24_CS_PIN, NRF24_IRQ_PIN,
-	BOARD_SDIO_D0, BOARD_SDIO_D1, BOARD_SDIO_D2, BOARD_SDIO_D3, BOARD_SDIO_CK, BOARD_SDIO_CMD,
-	USB_DM_PIN, USB_DP_PIN
-};
 /*
 static void initSRAMChip(void) {
     fsmc_nor_psram_reg_map *regs = FSMC_NOR_PSRAM1_BASE;
diff --git a/STM32F4/variants/generic_f407v/pin_map.c b/STM32F4/variants/generic_f407v/pin_map.c
new file mode 100644
index 000000000..58eeca4be
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/pin_map.c
@@ -0,0 +1,214 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file   generic_f407v.cpp
+ * @author ala42
+ * @brief  generic_f407v board file.
+ */
+
+#ifdef BOARD_generic_f407v
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+//#include "generic_f407v.h"
+
+//#include "fsmc.h"
+#include <libmaple\gpio.h>
+#include <libmaple\rcc.h>
+#include <libmaple\timer.h>
+
+#include <wirish_types.h>
+
+extern timer_dev timer1;
+extern timer_dev timer2;
+extern timer_dev timer3;
+extern timer_dev timer4;
+extern timer_dev timer5;
+extern timer_dev timer6;
+extern timer_dev timer7;
+extern timer_dev timer8;
+/*
+typedef struct stm32_pin_info {
+    gpio_dev *gpio_device;      // Maple pin's GPIO device
+    uint8 gpio_bit;             // Pin's GPIO port bit.
+    timer_dev *timer_device;    // Pin's timer device, if any.
+    uint8 timer_channel;        // Timer channel, or 0 if none.
+    const adc_dev *adc_device;  // ADC device, if any.
+    uint8 adc_channel;          // Pin ADC channel, or ADCx if none.
+} stm32_pin_info;
+*/
+const stm32_pin_info PIN_MAP1[] = { // LQFP100 package pin
+    {&GPIOA, &timer5, 1,    0, &ADC1}, // D00/PA0  | 23 | USART2_CTS | UART4_TX       | ETH_MII_CRS      | TIM2_CH1_ETR   | TIM5_CH1       | TIM8_ETR                      | ADC123_IN0/WKUP
+};
+
+const stm32_pin_info PIN_MAP[] = { // LQFP100 package pin
+    {&GPIOA, &timer5, 1,    0, &ADC1}, // D00/PA0  | 23 | USART2_CTS | UART4_TX       | ETH_MII_CRS      | TIM2_CH1_ETR   | TIM5_CH1       | TIM8_ETR                      | ADC123_IN0/WKUP
+    {&GPIOA, &timer5, 2,    1, &ADC1}, // D01/PA1  | 24 | USART2_RTS | UART4_RX       | ETH_RMII_REF_CLK | ETH_MII_RX_CLK | TIM5_CH2       | TIM2_CH2                      | ADC123_IN1
+    {&GPIOA, &timer5, 3,    2, &ADC1}, // D02/PA2  | 25 | USART2_TX  | TIM5_CH3       | TIM9_CH1         | TIM2_CH3       | ETH_MDIO                                       | ADC123_IN2
+    {&GPIOA, &timer5, 4,    3, &ADC1}, // D03/PA3  | 26 | USART2_RX  | TIM5_CH4       | TIM9_CH2         | TIM2_CH4       | OTG_HS_ULPI_D0 | ETH_MII_COL                   | ADC123_IN3
+    {&GPIOA,    NULL, 0,    4, &ADC1}, // D04/PA4  | 29 | SPI1_NSS   | SPI3_NSS       | USART2_CK        | DCMI_HSYNC     | OTG_HS_SOF     | I2S3_WS                       | ADC12_IN4 / DAC_OUT1
+    {&GPIOA,    NULL, 0,    5, &ADC1}, // D05/PA5  | 30 | SPI1_SCK   | OTG_HS_ULPI_CK | TIM2_CH1_ETR     | TIM8_CH1N                                                       | ADC12_IN5 / DAC_OUT2
+    {&GPIOA,    NULL, 1,    6, &ADC1}, // D06/PA6  | 31 | SPI1_MISO  | TIM8_BKIN      | TIM13_CH1        | DCMI_PIXCLK    | TIM3_CH1       | TIM1_BKIN                     | ADC12_IN6
+    {&GPIOA,    NULL, 0,    7, &ADC1}, // D07/PA7  | 32 | SPI1_MOSI  | TIM8_CH1N      | TIM14_CH1        | TIM3_CH2       | ETH_MII_RX_DV  | TIM1_CH1N   / ETH_RMII_CRS_DV | ADC12_IN7
+    {&GPIOA,    NULL, 0, ADCx,  NULL}, // D08/PA8  | 67 | MCO1       | USART1_CK      | TIM1_CH1         | I2C3_SCL       | OTG_FS_SOF
+    {&GPIOA,    NULL, 0, ADCx,  NULL}, // D09/PA9  | 68 | USART1_TX  | TIM1_CH2       | I2C3_SMBA        | DCMI_D0
+    {&GPIOA,    NULL, 0, ADCx,  NULL}, // D10/PA10 | 69 | USART1_RX  | TIM1_CH3       | OTG_FS_ID        | DCMI_D1
+    {&GPIOA,    NULL, 0, ADCx,  NULL}, // D11/PA11 | 70 | USART1_CTS | CAN1_RX        | TIM1_CH4         | OTG_FS_DM
+    {&GPIOA,    NULL, 0, ADCx,  NULL}, // D12/PA12 | 71 | USART1_RTS | CAN1_TX        | TIM1_ETR         | OTG_FS_DP
+    {&GPIOA,    NULL, 0, ADCx,  NULL}, // D13/PA13 | 72 | JTMS-SWDIO
+    {&GPIOA,    NULL, 0, ADCx,  NULL}, // D14/PA14 | 76 | JTCK-SWCLK
+    {&GPIOA, &timer2, 1, ADCx,  NULL}, // D15/PA15 | 77 | JTDI       | SPI3_NSS       | I2S3_WS          | TIM2_CH1_ETR   | SPI1_NSS
+
+    {&GPIOB, &timer3, 3,    8, &ADC1}, // D16/PB0  | 35 | TIM3_CH3   | TIM8_CH2N | OTG_HS_ULPI_D1 | ETH_MII_RXD2   | TIM1_CH2N      | ADC12_IN8
+    {&GPIOB, &timer3, 4,    9, &ADC1}, // D17/PB1  | 36 | TIM3_CH4   | TIM8_CH3N | OTG_HS_ULPI_D2 | ETH_MII_RXD3   | TIM1_CH3N      | ADC12_IN9
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D18/PB2  | 37 | BOOT1    
+    {&GPIOB, &timer2, 2, ADCx,  NULL}, // D19/PB3  | 89 | JTDO       | TRACESWO  | SPI3_SCK       | I2S3_CK        | TIM2_CH2       | SPI1_SCK
+    {&GPIOB, &timer3, 1, ADCx,  NULL}, // D20/PB4  | 90 | NJTRST     | SPI3_MISO | TIM3_CH1       | SPI1_MISO      | I2S3ext_SD
+    {&GPIOB, &timer3, 2, ADCx,  NULL}, // D21/PB5  | 91 | I2C1_SMBA  | CAN2_RX   | OTG_HS_ULPI_D7 | ETH_PPS_OUT    | TIM3_CH2       | SPI1_MOSI      | SPI3_MOSI      | DCMI_D10      | I2S3_SD
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D22/PB6  | 92 | I2C1_SCL   | TIM4_CH1  | CAN2_TX        | DCMI_D5        | USART1_TX
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D23/PB7  | 93 | I2C1_SDA   | FSMC_NL   | DCMI_VSYNC     | USART1_RX      | TIM4_CH2
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D24/PB8  | 95 | TIM4_CH3   | SDIO_D4   | TIM10_CH1      | DCMI_D6        | ETH_MII_TXD3   | I2C1_SCL       | CAN1_RX
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D25/PB9  | 96 | SPI2_NSS   | I2S2_WS   | TIM4_CH4       | TIM11_CH1      | SDIO_D5        | DCMI_D7        | I2C1_SDA       | CAN1_TX
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D26/PB10 | 47 | SPI2_SCK   | I2S2_CK   | I2C2_SCL       | USART3_TX      | OTG_HS_ULPI_D3 | ETH_MII_RX_ER  | TIM2_CH3
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D27/PB11 | 48 | I2C2_SDA   | USART3_RX | OTG_HS_ULPI_D4 | ETH_RMII_TX_EN | ETH_MII_TX_EN  | TIM2_CH4
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D28/PB12 | 51 | SPI2_NSS   | I2S2_WS   | I2C2_SMBA      | USART3_CK      | TIM1_BKIN      | CAN2_RX        | OTG_HS_ULPI_D5 | ETH_RMII_TXD0 | ETH_MII_TXD0 | OTG_HS_ID
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D29/PB13 | 52 | SPI2_SCK   | I2S2_CK   | USART3_CTS     | TIM1_CH1N      | CAN2_TX        | OTG_HS_ULPI_D6 | ETH_RMII_TXD1  | ETH_MII_TXD1
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D30/PB14 | 53 | SPI2_MISO  | TIM1_CH2N | TIM12_CH1      | OTG_HS_DM      | USART3_RTS     | TIM8_CH2N      | I2S2ext_SD
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D31/PB15 | 54 | SPI2_MOSI  | I2S2_SD   | TIM1_CH3N      | TIM8_CH3N      | TIM12_CH2      | OTG_HS_DP
+                             
+    {&GPIOC,    NULL, 0,   10, &ADC1}, // D32/PC0  | 15 | OTG_HS_ULPI_STP                                                  | ADC123_IN10
+    {&GPIOC,    NULL, 0,   11, &ADC1}, // D33/PC1  | 16 | ETH_MDC                                                          | ADC123_IN11
+    {&GPIOC,    NULL, 0,   12, &ADC1}, // D34/PC2  | 17 | SPI2_MISO  | OTG_HS_ULPI_DIR  | ETH_MII_TXD2    | I2S2ext_SD     | ADC123_IN12
+    {&GPIOC,    NULL, 0,   13, &ADC1}, // D35/PC3  | 18 | SPI2_MOSI  | I2S2_SD          | OTG_HS_ULPI_NXT | ETH_MII_TX_CLK | ADC123_IN13
+    {&GPIOC,    NULL, 0,   14, &ADC1}, // D36/PC4  | 33 | ETH_RMII_RX_D0                | ETH_MII_RX_D0                    | ADC12_IN14
+    {&GPIOC,    NULL, 0,   15, &ADC1}, // D37/PC5  | 34 | ETH_RMII_RX_D1                | ETH_MII_RX_D1                    | ADC12_IN15
+    {&GPIOC, &timer8, 1, ADCx,  NULL}, // D38/PC6  | 63 | I2S2_MCK   | TIM8_CH1/SDIO_D6 | USART6_TX       | DCMI_D0/TIM3_CH1 
+    {&GPIOC, &timer8, 2, ADCx,  NULL}, // D39/PC7  | 64 | I2S3_MCK   | TIM8_CH2/SDIO_D7 | USART6_RX       | DCMI_D1/TIM3_CH2
+    {&GPIOC, &timer8, 3, ADCx,  NULL}, // D40/PC8  | 65 | TIM8_CH3   | SDIO_D0          | TIM3_CH3        | USART6_CK      | DCMI_D2
+    {&GPIOC, &timer8, 4, ADCx,  NULL}, // D41/PC9  | 66 | I2S_CKIN   | MCO2             | TIM8_CH4        | SDIO_D1        | I2C3_SDA  | DCMI_D3    | TIM3_CH4
+    {&GPIOC,    NULL, 0, ADCx,  NULL}, // D42/PC10 | 78 | SPI3_SCK   | I2S3_CK          | UART4_TX        | SDIO_D2        | DCMI_D8   | USART3_TX
+    {&GPIOC,    NULL, 0, ADCx,  NULL}, // D43/PC11 | 79 | UART4_RX   | SPI3_MISO        | SDIO_D3         | DCMI_D4        | USART3_RX | I2S3ext_SD
+    {&GPIOC,    NULL, 0, ADCx,  NULL}, // D44/PC12 | 80 | UART5_TX   | SDIO_CK          | DCMI_D9         | SPI3_MOSI      | I2S3_SD   | USART3_CK
+    {&GPIOC,    NULL, 0, ADCx,  NULL}, // D45/PC13 |  7 | RTC_OUT, RTC_TAMP1, RTC_TS
+    {&GPIOC,    NULL, 0, ADCx,  NULL}, // D46/PC14 |  8 | OSC32_IN
+    {&GPIOC,    NULL, 0, ADCx,  NULL}, // D47/PC15 |  9 | OSC32_OUT
+                             
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D48/PD0  | 81 | FSMC_D2    | CAN1_RX
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D49/PD1  | 82 | FSMC_D3    | CAN1_TX
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D50/PD2  | 83 | TIM3_ETR   | UART5_RX   | SDIO_CMD | DCMI_D11
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D51/PD3  | 84 | FSMC_CLK   | USART2_CTS
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D52/PD4  | 85 | FSMC_NOE   | USART2_RTS
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D53/PD5  | 86 | FSMC_NWE   | USART2_TX
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D54/PD6  | 87 | FSMC_NWAIT | USART2_RX
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D55/PD7  | 88 | USART2_CK  | FSMC_NE1   | FSMC_NCE2
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D56/PD8  | 55 | FSMC_D13   | USART3_TX
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D57/PD9  | 56 | FSMC_D14   | USART3_RX
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D58/PD10 | 57 | FSMC_D15   | USART3_CK
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D59/PD11 | 58 | FSMC_CLE   | FSMC_A16   | USART3_CTS
+    {&GPIOD, &timer4, 1, ADCx,  NULL}, // D60/PD12 | 59 | FSMC_ALE   | FSMC_A17   | TIM4_CH1   | USART3_RTS // remap in
+    {&GPIOD, &timer4, 2, ADCx,  NULL}, // D61/PD13 | 60 | FSMC_A18                | TIM4_CH2                // remap in
+    {&GPIOD, &timer4, 3, ADCx,  NULL}, // D62/PD14 | 61 | FSMC_D0                 | TIM4_CH3                // remap in
+    {&GPIOD, &timer4, 4, ADCx,  NULL}, // D63/PD15 | 62 | FSMC_D1                 | TIM4_CH4                // remap in
+
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D64/PE0  | 97 | TIM4_ETR  | FSMC_NBL0 | DCMI_D2
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D65/PE1  | 98 | FSMC_NBL1 | DCMI_D3
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D66/PE2  |  1 | TRACECLK  | FSMC_A23  | ETH_MII_TXD3
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D67/PE3  |  2 | TRACED0   | FSMC_A19
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D68/PE4  |  3 | TRACED1   | FSMC_A20  | DCMI_D4
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D69/PE5  |  4 | TRACED2   | FSMC_A21  | TIM9_CH1     / DCMI_D6
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D70/PE6  |  5 | TRACED3   | FSMC_A22  | TIM9_CH2     / DCMI_D7
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D71/PE7  | 38 | FSMC_D4   | TIM1_ETR
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D72/PE8  | 39 | FSMC_D5   | TIM1_CH1N
+    {&GPIOE, &timer1, 1, ADCx,  NULL}, // D73/PE9  | 40 | FSMC_D6   | TIM1_CH1   // remap in
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D74/PE10 | 41 | FSMC_D7   | TIM1_CH2N
+    {&GPIOE, &timer1, 2, ADCx,  NULL}, // D75/PE11 | 42 | FSMC_D8   | TIM1_CH2   // remap in
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D76/PE12 | 43 | FSMC_D9   | TIM1_CH3N
+    {&GPIOE, &timer1, 3, ADCx,  NULL}, // D77/PE13 | 44 | FSMC_D10  | TIM1_CH3   // remap in
+    {&GPIOE, &timer1, 4, ADCx,  NULL}, // D78/PE14 | 45 | FSMC_D11  | TIM1_CH4   // remap in
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D79/PE15 | 46 | FSMC_D12  | TIM1_BKIN
+#if 0
+    {GPIOF,  0,   NULL, 0, NULL, ADCx}, // D80/PF0
+    {GPIOF,  1,   NULL, 0, NULL, ADCx}, // D81/PF1
+    {GPIOF,  2,   NULL, 0, NULL, ADCx}, // D82/PF2
+    {GPIOF,  3,   NULL, 0, NULL, ADCx}, // D83/PF3
+    {GPIOF,  4,   NULL, 0, NULL, ADCx}, // D84/PF4
+    {GPIOF,  5,   NULL, 0, NULL, ADCx}, // D85/PF5
+    {GPIOF,  6,   NULL, 0, NULL, ADCx}, // D86/PF6
+    {GPIOF,  7,   NULL, 0, NULL, ADCx}, // D87/PF7
+    {GPIOF,  8,   NULL, 0, NULL, ADCx}, // D88/PF8
+    {GPIOF,  9,   NULL, 0, NULL, ADCx}, // D89/PF9
+    {GPIOF, 10,   NULL, 0, NULL, ADCx}, // D90/PF10
+    {GPIOF, 11,   NULL, 0, NULL, ADCx}, // D91/PF11
+    {GPIOF, 12,   NULL, 0, NULL, ADCx}, // D92/PF12
+    {GPIOF, 13,   NULL, 0, NULL, ADCx}, // D93/PF13
+    {GPIOF, 14,   NULL, 0, NULL, ADCx}, // D94/PF14
+    {GPIOF, 15,   NULL, 0, NULL, ADCx}, // D95/PF15
+
+    {GPIOG,  0,   NULL, 0, NULL, ADCx}, // D96/PG0
+    {GPIOG,  1,   NULL, 0, NULL, ADCx}, // D97/PG1
+    {GPIOG,  2,   NULL, 0, NULL, ADCx}, // D98/PG2
+    {GPIOG,  3,   NULL, 0, NULL, ADCx}, // D99/PG3
+    {GPIOG,  4,   NULL, 0, NULL, ADCx}, // D100/PG4
+    {GPIOG,  5,   NULL, 0, NULL, ADCx}, // D101/PG5
+    {GPIOG,  6,   NULL, 0, NULL, ADCx}, // D102/PG6
+    {GPIOG,  7,   NULL, 0, NULL, ADCx}, // D103/PG7 
+    {GPIOG,  8,   NULL, 0, NULL, ADCx}, // D104/PG8
+    {GPIOG,  9,   NULL, 0, NULL, ADCx}, // D105/PG9
+    {GPIOG, 10,   NULL, 0, NULL, ADCx}, // D106/PG10
+    {GPIOG, 11,   NULL, 0, NULL, ADCx}, // D107/PG11
+    {GPIOG, 12,   NULL, 0, NULL, ADCx}, // D108/PG12
+    {GPIOG, 13,   NULL, 0, NULL, ADCx}, // D109/PG13
+    {GPIOG, 14,   NULL, 0, NULL, ADCx}, // D110/PG14
+    {GPIOG, 15,   NULL, 0, NULL, ADCx}  // D111/PG15
+#endif
+};
+/* to be defined
+extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
+    0, 1, 2, 3, 15, 16, 17, 19, 20, 21, 38, 39, 49, 41, 60, 61, 62, 63, 73, 75, 77, 78
+};
+*/
+const uint8 boardADCPins[BOARD_NR_ADC_PINS] = {
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PB0, PB1, PC0, PC1, PC2, PC3, PC4, PC5
+};
+
+const uint8 boardUsedPins[BOARD_NR_USED_PINS] = {
+    BOARD_LED_PIN, BOARD_LED2_PIN, BOARD_BUTTON1_PIN, BOARD_BUTTON2_PIN, BOARD_BUTTON2_PIN,
+	BOARD_JTMS_SWDIO_PIN, BOARD_JTCK_SWCLK_PIN,
+	FLASH_CS_PIN, FLASH_CLK_PIN, FLASH_DO_PIN, FLASH_DI_PIN,
+	NRF24_CE_PIN, NRF24_CS_PIN, NRF24_IRQ_PIN,
+	BOARD_SDIO_D0, BOARD_SDIO_D1, BOARD_SDIO_D2, BOARD_SDIO_D3, BOARD_SDIO_CK, BOARD_SDIO_CMD,
+	USB_DM_PIN, USB_DP_PIN
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif // BOARD_generic_f407v

From 467c450449ded9a8f92710be817418611a5bb571 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Tue, 9 May 2017 14:35:13 +0200
Subject: [PATCH 064/307] revert removing SPI declaration (needed by SdFat lib)
 + remove unused lines

---
 STM32F4/libraries/SPI/src/SPI.h | 19 +++----------------
 1 file changed, 3 insertions(+), 16 deletions(-)

diff --git a/STM32F4/libraries/SPI/src/SPI.h b/STM32F4/libraries/SPI/src/SPI.h
index 39a5a9eac..78e70660a 100644
--- a/STM32F4/libraries/SPI/src/SPI.h
+++ b/STM32F4/libraries/SPI/src/SPI.h
@@ -37,6 +37,8 @@
 #ifndef _LIB_SPI_H_
 #define _LIB_SPI_H_
 
+//#define SPI_DMA // enable this to use DMA for SPI transfers
+
 #include <libmaple/libmaple_types.h>
 #include <libmaple/spi.h>
 #include <libmaple/dma.h>
@@ -374,27 +376,12 @@ class SPIClass {
     uint8 recv(void);
 	
 private:
-/*
-	static inline void DMA1_CH3_Event() {
-		dma1_ch3_Active = 0;
-//		dma_disable(DMA1, DMA_CH3);
-//		dma_disable(DMA1, DMA_CH2);
-		
-		// To Do. Need to wait for 
-	}
-*/	
 	SPISettings _settings[BOARD_NR_SPI];
 	SPISettings *_currentSetting;
 	
 	void updateSettings(void);
-	/*
-	spi_dev *spi_d;
-	uint8_t _SSPin;
-	uint32_t clockDivider;
-	uint8_t dataMode;
-	BitOrder bitOrder;
-	*/
 };
 
+extern SPIClass SPI; // needed bx SdFat(EX) lib
 
 #endif

From e37d7eac483b5719f17264086c3c06ebea3f3ecf Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Tue, 9 May 2017 14:37:47 +0200
Subject: [PATCH 065/307] removed unused const array

---
 STM32F4/variants/generic_f407v/pin_map.c | 8 ++------
 1 file changed, 2 insertions(+), 6 deletions(-)

diff --git a/STM32F4/variants/generic_f407v/pin_map.c b/STM32F4/variants/generic_f407v/pin_map.c
index 58eeca4be..2189902d6 100644
--- a/STM32F4/variants/generic_f407v/pin_map.c
+++ b/STM32F4/variants/generic_f407v/pin_map.c
@@ -53,20 +53,16 @@ extern timer_dev timer5;
 extern timer_dev timer6;
 extern timer_dev timer7;
 extern timer_dev timer8;
+
 /*
 typedef struct stm32_pin_info {
     gpio_dev *gpio_device;      // Maple pin's GPIO device
-    uint8 gpio_bit;             // Pin's GPIO port bit.
     timer_dev *timer_device;    // Pin's timer device, if any.
     uint8 timer_channel;        // Timer channel, or 0 if none.
-    const adc_dev *adc_device;  // ADC device, if any.
     uint8 adc_channel;          // Pin ADC channel, or ADCx if none.
+    const adc_dev *adc_device;  // ADC device, if any.
 } stm32_pin_info;
 */
-const stm32_pin_info PIN_MAP1[] = { // LQFP100 package pin
-    {&GPIOA, &timer5, 1,    0, &ADC1}, // D00/PA0  | 23 | USART2_CTS | UART4_TX       | ETH_MII_CRS      | TIM2_CH1_ETR   | TIM5_CH1       | TIM8_ETR                      | ADC123_IN0/WKUP
-};
-
 const stm32_pin_info PIN_MAP[] = { // LQFP100 package pin
     {&GPIOA, &timer5, 1,    0, &ADC1}, // D00/PA0  | 23 | USART2_CTS | UART4_TX       | ETH_MII_CRS      | TIM2_CH1_ETR   | TIM5_CH1       | TIM8_ETR                      | ADC123_IN0/WKUP
     {&GPIOA, &timer5, 2,    1, &ADC1}, // D01/PA1  | 24 | USART2_RTS | UART4_RX       | ETH_RMII_REF_CLK | ETH_MII_RX_CLK | TIM5_CH2       | TIM2_CH2                      | ADC123_IN1

From 59b71f1370229a180484903e65dca0514d5475e8 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Tue, 9 May 2017 17:00:27 +0200
Subject: [PATCH 066/307] improved block read routine

---
 STM32F4/libraries/SPI/src/SPI.cpp | 23 ++++++++++++++++++++---
 1 file changed, 20 insertions(+), 3 deletions(-)

diff --git a/STM32F4/libraries/SPI/src/SPI.cpp b/STM32F4/libraries/SPI/src/SPI.cpp
index baef0abf2..2d2cc48b5 100644
--- a/STM32F4/libraries/SPI/src/SPI.cpp
+++ b/STM32F4/libraries/SPI/src/SPI.cpp
@@ -321,14 +321,32 @@ uint16 SPIClass::read(void)
 
 void SPIClass::read(uint8 *buf, uint32 len)
 {
-	spi_rx_reg(_currentSetting->spi_d); // clear the RX buffer in case a byte is waiting on it.
+	if ( len == 0 ) return;
+	spi_rx_reg(_currentSetting->spi_d);		// clear the RX buffer in case a byte is waiting on it.
 	spi_reg_map * regs = _currentSetting->spi_d->regs;
+#if 1
+	// start sequence: write byte 0
+	regs->DR = 0x00FF;						// write the first byte
+	// main loop
+	while ( (--len) ) {
+		while( !(regs->SR & SPI_SR_TXE) );		// wait for TXE flag
+		noInterrupts();							// go atomic level - avoid interrupts to surely get the previously received data
+		regs->DR = 0x00FF;						// write the next data item to be transmitted into the SPI_DR register. This clears the TXE flag.
+		while ( !(regs->SR & SPI_SR_RXNE) );	// wait till data is available in the DR register
+		*buf++ = (uint8)(regs->DR);				// read and store the received byte. This clears the RXNE flag.
+		interrupts();							// let systick do its job
+	}
+	// read remaining last byte
+	while ( !(regs->SR & SPI_SR_RXNE) );	// wait till data is available in the Rx register
+	*buf++ = (uint8)(regs->DR);				// read and store the received byte
+#else
 	// start sequence
 	while ( (len--)>0) {
 		regs->DR = 0x00FF; // " write the data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
 		while ( (regs->SR & SPI_SR_RXNE)==0 ) ; // wait till data is available in the Rx register
 		*buf++ = (uint8)(regs->DR); // read and store the received byte
-    }
+	}
+#endif
 }
 
 void SPIClass::write(uint16 data)
@@ -339,7 +357,6 @@ void SPIClass::write(uint16 data)
 	 * This almost doubles the speed of this function.
 	 */
 	spi_tx_reg(_currentSetting->spi_d, data); // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
-//return;
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
 }

From 54cd854161ffe5d84cde14a3763b5abe68a30ae7 Mon Sep 17 00:00:00 2001
From: SukkoPera <software@sukkology.net>
Date: Tue, 9 May 2017 23:16:10 +0200
Subject: [PATCH 067/307] Tag isConnected() with __attribute__(deprecated)

---
 STM32F1/cores/maple/usb_serial.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/cores/maple/usb_serial.h b/STM32F1/cores/maple/usb_serial.h
index ceb81e17b..40745c15d 100644
--- a/STM32F1/cores/maple/usb_serial.h
+++ b/STM32F1/cores/maple/usb_serial.h
@@ -80,7 +80,7 @@ class USBSerial : public Stream {
      *
      * Deprecated, use the above.
      */
-    uint8 isConnected() { return (bool) *this; }
+    uint8 isConnected() __attribute__((deprecated("Use !Serial instead"))) { return (bool) *this; }
 };
 
 #ifdef SERIAL_USB 

From ad51f6f8f8888f528badcea133953f525fd1116b Mon Sep 17 00:00:00 2001
From: SukkoPera <software@sukkology.net>
Date: Tue, 9 May 2017 23:16:47 +0200
Subject: [PATCH 068/307] Avoid usage of deprecated function

---
 STM32F1/cores/maple/usb_serial.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/cores/maple/usb_serial.cpp b/STM32F1/cores/maple/usb_serial.cpp
index 85c70246f..57b439f75 100644
--- a/STM32F1/cores/maple/usb_serial.cpp
+++ b/STM32F1/cores/maple/usb_serial.cpp
@@ -107,7 +107,7 @@ size_t n = 0;
 size_t USBSerial::write(const uint8 *buf, uint32 len)
 {
 size_t n = 0;
-    if (!this->isConnected() || !buf) {
+    if (!(bool) *this || !buf) {
         return 0;
     }
 

From 59ebf2a818b803094ee2319021630440e3bc0daf Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Wed, 10 May 2017 20:48:14 +0200
Subject: [PATCH 069/307] improved SPI no DMA block read + added SPI DMA

---
 STM32F4/cores/maple/libmaple/dmaF4.c      | 35 +++--------
 STM32F4/cores/maple/libmaple/dmaF4.h      | 72 +++++++++++++++++------
 STM32F4/cores/maple/libmaple/dma_common.h | 12 +---
 STM32F4/cores/maple/libmaple/spi_f4.c     |  2 +-
 STM32F4/libraries/SPI/src/SPI.h           |  8 ++-
 5 files changed, 71 insertions(+), 58 deletions(-)

diff --git a/STM32F4/cores/maple/libmaple/dmaF4.c b/STM32F4/cores/maple/libmaple/dmaF4.c
index 4b530aff8..add3d8e51 100644
--- a/STM32F4/cores/maple/libmaple/dmaF4.c
+++ b/STM32F4/cores/maple/libmaple/dmaF4.c
@@ -117,33 +117,16 @@ void dma_detach_interrupt(dma_dev *dev, dma_stream stream) {
     dev->handlers[stream].handler = NULL;
 }
 
+const uint8 dma_isr_bits_shift[] = { 0, 6, 16, 22};
+
+uint8 dma_get_isr_bits(dma_dev *dev, dma_stream stream) {
+	if ( stream&0xFC )	return ((dev->regs->HISR)>>dma_isr_bits_shift[stream&0x03]) & 0x3d;
+	else				return ((dev->regs->LISR)>>dma_isr_bits_shift[stream&0x03]) & 0x3d;
+}
+
 void dma_clear_isr_bits(dma_dev *dev, dma_stream stream) {
-    switch (stream) {
-    case 0:
-        dev->regs->LIFCR|=0x0000003d;
-        break;
-    case 1:
-        dev->regs->LIFCR|=0x00000f40;
-        break;
-    case 2:
-        dev->regs->LIFCR|=0x003d0000;
-        break;
-    case 3:
-        dev->regs->LIFCR|=0x0f400000;
-        break;
-    case 4:
-        dev->regs->HIFCR|=0x0000003d;
-        break;
-    case 5:
-        dev->regs->HIFCR|=0x00000f40;
-        break;
-    case 6:
-        dev->regs->HIFCR|=0x003d0000;
-        break;
-    case 7:
-        dev->regs->HIFCR|=0x0f400000;
-        break;
-    }
+	if ( stream&0xFC )	dev->regs->HIFCR = (uint32)0x0000003d << dma_isr_bits_shift[stream&0x03];
+	else				dev->regs->LIFCR = (uint32)0x0000003d << dma_isr_bits_shift[stream&0x03];
 }
 
 /*
diff --git a/STM32F4/cores/maple/libmaple/dmaF4.h b/STM32F4/cores/maple/libmaple/dmaF4.h
index 6f7086f36..757906c82 100644
--- a/STM32F4/cores/maple/libmaple/dmaF4.h
+++ b/STM32F4/cores/maple/libmaple/dmaF4.h
@@ -25,7 +25,7 @@
  *****************************************************************************/
 
 /**
- * @file dma.h
+ * @file dmaF4.h
  *
  * @author Marti Bolivar <mbolivar@leaflabs.com>;
  *         Original implementation by Michael Hope
@@ -84,7 +84,7 @@ typedef struct dma_reg_map {
  * Register bit definitions
  */
 
-/* Channel configuration register */
+/* Stream configuration register */
 
 #define DMA_CR_CH0                      (0x0 << 25)
 #define DMA_CR_CH1                      (0x1 << 25)
@@ -136,6 +136,25 @@ typedef struct dma_reg_map {
 #define DMA_CR_DMEIE                    (0x1 << 1)
 #define DMA_CR_EN                       (0x1)
 
+typedef enum dma_channel {
+    DMA_CH0 = DMA_CR_CH0,                /**< Channel 0 */
+    DMA_CH1 = DMA_CR_CH1,                /**< Channel 1 */
+    DMA_CH2 = DMA_CR_CH2,                /**< Channel 2 */
+    DMA_CH3 = DMA_CR_CH3,                /**< Channel 3 */
+    DMA_CH4 = DMA_CR_CH4,                /**< Channel 4 */
+    DMA_CH5 = DMA_CR_CH5,                /**< Channel 5 */
+    DMA_CH6 = DMA_CR_CH6,                /**< Channel 6 */
+    DMA_CH7 = DMA_CR_CH7,                /**< Channel 7 */
+} dma_channel;
+
+/* Device interrupt status register flags */
+
+#define DMA_ISR_TCIF    (1 << 5)
+#define DMA_ISR_HTIF    (1 << 4)
+#define DMA_ISR_TEIF    (1 << 3)
+#define DMA_ISR_DMEIF   (1 << 2)
+#define DMA_ISR_FEIF    (1 << 0)
+
 /*
  * Devices
  */
@@ -166,25 +185,35 @@ extern dma_dev *DMA2;
  * Convenience functions
  */
 
-void dma_init(dma_dev *dev);
+extern void dma_init(dma_dev *dev);
 
 /** Flags for DMA transfer configuration. */
 typedef enum dma_mode_flags {
-    DMA_MEM_2_MEM  = 1 << 14, /**< Memory to memory mode */
-    DMA_MINC_MODE  = 1 << 7,  /**< Auto-increment memory address */
-    DMA_PINC_MODE  = 1 << 6,  /**< Auto-increment peripheral address */
-    DMA_CIRC_MODE  = 1 << 5,  /**< Circular mode */
-    DMA_FROM_MEM   = 1 << 4,  /**< Read from memory to peripheral */
-    DMA_TRNS_ERR   = 1 << 3,  /**< Interrupt on transfer error */
-    DMA_HALF_TRNS  = 1 << 2,  /**< Interrupt on half-transfer */
-    DMA_TRNS_CMPLT = 1 << 1   /**< Interrupt on transfer completion */
+    DMA_MEM_BUF_0 = DMA_CR_CT0, /**< Current memory target buffer 0 */
+    DMA_MEM_BUF_1 = DMA_CR_CT1, /**< Current memory target buffer 1 */
+    DMA_DBL_BUF_MODE = DMA_CR_DBM,  /**< Current memory double buffer mode */
+    DMA_PINC_OFFSET  = DMA_CR_PINCOS,  /**< Peripheral increment offset size */
+    DMA_MINC_MODE  = DMA_CR_MINC,  /**< Memory increment mode */
+    DMA_PINC_MODE  = DMA_CR_PINC,  /**< Peripheral increment mode */
+    DMA_CIRC_MODE  = DMA_CR_CIRC,  /**< Memory Circular mode */
+    DMA_FROM_PER   = DMA_CR_DIR_P2M,  /**< Read from memory to peripheral */
+    DMA_FROM_MEM   = DMA_CR_DIR_M2P,  /**< Read from memory to peripheral */
+    DMA_MEM_TO_MEM = DMA_CR_DIR_M2M,  /**< Read from memory to memory */
+    DMA_PERIF_CTRL   = DMA_CR_PFCTRL,  /**< Peripheral flow controller */
+    DMA_PRIO_MEDIUM    = DMA_CR_PL_MEDIUM,    /**< Medium priority */
+    DMA_PRIO_HIGH      = DMA_CR_PL_HIGH,      /**< High priority */
+    DMA_PRIO_VERY_HIGH = DMA_CR_PL_VERY_HIGH, /**< Very high priority */
+    DMA_TRNS_CMPLT   = DMA_CR_TCIE,   /**< Interrupt on transfer completion */
+    DMA_TRNS_HALF    = DMA_CR_HTIE,  /**< Interrupt on half-transfer */
+    DMA_TRNS_ERR       = DMA_CR_TEIE,  /**< Interrupt on transfer error */
+    DMA_DIR_MODE_ERR   = DMA_CR_DMEIE  /**< Interrupt on direct mode error */
 } dma_mode_flags;
 
 /** Source and destination transfer sizes. */
 typedef enum dma_xfer_size {
-    DMA_SIZE_8BITS  = 0,        /**< 8-bit transfers */
-    DMA_SIZE_16BITS = 1,        /**< 16-bit transfers */
-    DMA_SIZE_32BITS = 2         /**< 32-bit transfers */
+    DMA_SIZE_8BITS  = ( DMA_CR_MSIZE_8BITS|DMA_CR_PSIZE_8BITS ),        /**< 8-bit transfers */
+    DMA_SIZE_16BITS = (DMA_CR_MSIZE_16BITS|DMA_CR_PSIZE_16BITS),        /**< 16-bit transfers */
+    DMA_SIZE_32BITS = (DMA_CR_MSIZE_32BITS|DMA_CR_PSIZE_32BITS)         /**< 32-bit transfers */
 } dma_xfer_size;
 
 /** DMA channel */
@@ -201,17 +230,17 @@ typedef enum dma_stream {
     
 static inline void dma_setup_transfer(dma_dev       *dev,
                                       dma_stream    stream,
+                                      dma_channel   channel,
+                                      dma_xfer_size trx_size,
                                       __io void     *peripheral_address,
                                       __io void     *memory_address0,
                                       __io void     *memory_address1,
-                                      uint32         flags,
-                                      uint32         fifo_flags) {
+                                      uint32        flags) {
     dev->regs->STREAM[stream].CR &= ~DMA_CR_EN; // disable
     dev->regs->STREAM[stream].PAR = (uint32)peripheral_address;
     dev->regs->STREAM[stream].M0AR = (uint32)memory_address0;
     dev->regs->STREAM[stream].M1AR = (uint32)memory_address1;
-    dev->regs->STREAM[stream].FCR = fifo_flags & 0x87; // mask out reserved bits
-    dev->regs->STREAM[stream].CR = flags & 0x0feffffe; // mask out reserved and enable
+    dev->regs->STREAM[stream].CR = ((flags|channel|trx_size) & 0x0feffffe); // mask out reserved and enable
 }
     
 static inline void dma_set_num_transfers(dma_dev *dev,
@@ -220,6 +249,12 @@ static inline void dma_set_num_transfers(dma_dev *dev,
     dev->regs->STREAM[stream].NDTR = num_transfers;
 }
 
+static inline void dma_set_fifo_flags(dma_dev *dev,
+                                      dma_stream stream,
+                                      uint8 fifo_flags) {
+    dev->regs->STREAM[stream].FCR = fifo_flags & 0x87; // mask out reserved bits
+}
+
 void dma_attach_interrupt(dma_dev *dev,
                           dma_stream stream,
                           void (*handler)(void));
@@ -232,6 +267,7 @@ static inline void dma_enable(dma_dev *dev, dma_stream stream) {
 
 static inline void dma_disable(dma_dev *dev, dma_stream stream) {
     dev->regs->STREAM[stream].CR &= ~DMA_CR_EN;
+	while (dev->regs->STREAM[stream].CR & DMA_CR_EN); // wait till EN bit is reset, see AN4031, chapter 4.1
 }    
 
 /**
diff --git a/STM32F4/cores/maple/libmaple/dma_common.h b/STM32F4/cores/maple/libmaple/dma_common.h
index 15dfab9c8..5f989219a 100644
--- a/STM32F4/cores/maple/libmaple/dma_common.h
+++ b/STM32F4/cores/maple/libmaple/dma_common.h
@@ -56,7 +56,7 @@ extern "C"{
  * Devices
  */
 
-struct dma_reg_map;
+//struct dma_reg_map;
 
 /* Encapsulates state related to user interrupt handlers. You
  * shouldn't touch these directly; use dma_attach_interrupt() and
@@ -82,16 +82,6 @@ struct dma_reg_map;
  *
  * @see dma_tube
  */
-typedef enum dma_channel {
-    DMA_CH0 = 0,                /**< Channel 0 */
-    DMA_CH1 = 1,                /**< Channel 1 */
-    DMA_CH2 = 2,                /**< Channel 2 */
-    DMA_CH3 = 3,                /**< Channel 3 */
-    DMA_CH4 = 4,                /**< Channel 4 */
-    DMA_CH5 = 5,                /**< Channel 5 */
-    DMA_CH6 = 6,                /**< Channel 6 */
-    DMA_CH7 = 7,                /**< Channel 7 */
-} dma_channel;
 
 /**
  * @brief Source and destination transfer sizes.
diff --git a/STM32F4/cores/maple/libmaple/spi_f4.c b/STM32F4/cores/maple/libmaple/spi_f4.c
index 43f5092c6..8e1bc15bf 100644
--- a/STM32F4/cores/maple/libmaple/spi_f4.c
+++ b/STM32F4/cores/maple/libmaple/spi_f4.c
@@ -28,7 +28,7 @@
 /**
  * @file libmaple/stm32f1/spi.c
  * @author Marti Bolivar <mbolivar@leaflabs.com>
- * @brief STM32F1 SPI/I2S.
+ * @brief STM32F4 SPI/I2S.
  */
 
 #include <libmaple/spi.h>
diff --git a/STM32F4/libraries/SPI/src/SPI.h b/STM32F4/libraries/SPI/src/SPI.h
index 39a5a9eac..fe728b519 100644
--- a/STM32F4/libraries/SPI/src/SPI.h
+++ b/STM32F4/libraries/SPI/src/SPI.h
@@ -42,6 +42,8 @@
 #include <libmaple/dma.h>
 #include <wirish.h>
 
+#define SPI_DMA
+
 // SPI_HAS_TRANSACTION means SPI has
 //   - beginTransaction()
 //   - endTransaction()
@@ -135,11 +137,12 @@ class SPISettings {
 	uint32_t dataSize;
 	
 	spi_dev *spi_d;
-	//uint8_t _SSPin;
 	uint32_t clockDivider;
+
 #ifdef SPI_DMA
-	dma_channel spiRxDmaChannel, spiTxDmaChannel;
 	dma_dev* spiDmaDev;
+	dma_channel spiDmaChannel;
+	dma_stream spiRxDmaStream, spiTxDmaStream;
 #endif
 
 	friend class SPIClass;
@@ -396,5 +399,6 @@ class SPIClass {
 	*/
 };
 
+extern SPIClass SPI;
 
 #endif

From fc0ee241841d71a5e7e289f6d715c160581dfc38 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Thu, 11 May 2017 00:01:53 +0200
Subject: [PATCH 070/307] Revert "improved SPI no DMA block read + added SPI
 DMA"

This reverts commit 59ebf2a818b803094ee2319021630440e3bc0daf.
---
 STM32F4/cores/maple/libmaple/dmaF4.c      | 35 ++++++++---
 STM32F4/cores/maple/libmaple/dmaF4.h      | 72 ++++++-----------------
 STM32F4/cores/maple/libmaple/dma_common.h | 12 +++-
 STM32F4/cores/maple/libmaple/spi_f4.c     |  2 +-
 STM32F4/libraries/SPI/src/SPI.h           |  8 +--
 5 files changed, 58 insertions(+), 71 deletions(-)

diff --git a/STM32F4/cores/maple/libmaple/dmaF4.c b/STM32F4/cores/maple/libmaple/dmaF4.c
index add3d8e51..4b530aff8 100644
--- a/STM32F4/cores/maple/libmaple/dmaF4.c
+++ b/STM32F4/cores/maple/libmaple/dmaF4.c
@@ -117,16 +117,33 @@ void dma_detach_interrupt(dma_dev *dev, dma_stream stream) {
     dev->handlers[stream].handler = NULL;
 }
 
-const uint8 dma_isr_bits_shift[] = { 0, 6, 16, 22};
-
-uint8 dma_get_isr_bits(dma_dev *dev, dma_stream stream) {
-	if ( stream&0xFC )	return ((dev->regs->HISR)>>dma_isr_bits_shift[stream&0x03]) & 0x3d;
-	else				return ((dev->regs->LISR)>>dma_isr_bits_shift[stream&0x03]) & 0x3d;
-}
-
 void dma_clear_isr_bits(dma_dev *dev, dma_stream stream) {
-	if ( stream&0xFC )	dev->regs->HIFCR = (uint32)0x0000003d << dma_isr_bits_shift[stream&0x03];
-	else				dev->regs->LIFCR = (uint32)0x0000003d << dma_isr_bits_shift[stream&0x03];
+    switch (stream) {
+    case 0:
+        dev->regs->LIFCR|=0x0000003d;
+        break;
+    case 1:
+        dev->regs->LIFCR|=0x00000f40;
+        break;
+    case 2:
+        dev->regs->LIFCR|=0x003d0000;
+        break;
+    case 3:
+        dev->regs->LIFCR|=0x0f400000;
+        break;
+    case 4:
+        dev->regs->HIFCR|=0x0000003d;
+        break;
+    case 5:
+        dev->regs->HIFCR|=0x00000f40;
+        break;
+    case 6:
+        dev->regs->HIFCR|=0x003d0000;
+        break;
+    case 7:
+        dev->regs->HIFCR|=0x0f400000;
+        break;
+    }
 }
 
 /*
diff --git a/STM32F4/cores/maple/libmaple/dmaF4.h b/STM32F4/cores/maple/libmaple/dmaF4.h
index 757906c82..6f7086f36 100644
--- a/STM32F4/cores/maple/libmaple/dmaF4.h
+++ b/STM32F4/cores/maple/libmaple/dmaF4.h
@@ -25,7 +25,7 @@
  *****************************************************************************/
 
 /**
- * @file dmaF4.h
+ * @file dma.h
  *
  * @author Marti Bolivar <mbolivar@leaflabs.com>;
  *         Original implementation by Michael Hope
@@ -84,7 +84,7 @@ typedef struct dma_reg_map {
  * Register bit definitions
  */
 
-/* Stream configuration register */
+/* Channel configuration register */
 
 #define DMA_CR_CH0                      (0x0 << 25)
 #define DMA_CR_CH1                      (0x1 << 25)
@@ -136,25 +136,6 @@ typedef struct dma_reg_map {
 #define DMA_CR_DMEIE                    (0x1 << 1)
 #define DMA_CR_EN                       (0x1)
 
-typedef enum dma_channel {
-    DMA_CH0 = DMA_CR_CH0,                /**< Channel 0 */
-    DMA_CH1 = DMA_CR_CH1,                /**< Channel 1 */
-    DMA_CH2 = DMA_CR_CH2,                /**< Channel 2 */
-    DMA_CH3 = DMA_CR_CH3,                /**< Channel 3 */
-    DMA_CH4 = DMA_CR_CH4,                /**< Channel 4 */
-    DMA_CH5 = DMA_CR_CH5,                /**< Channel 5 */
-    DMA_CH6 = DMA_CR_CH6,                /**< Channel 6 */
-    DMA_CH7 = DMA_CR_CH7,                /**< Channel 7 */
-} dma_channel;
-
-/* Device interrupt status register flags */
-
-#define DMA_ISR_TCIF    (1 << 5)
-#define DMA_ISR_HTIF    (1 << 4)
-#define DMA_ISR_TEIF    (1 << 3)
-#define DMA_ISR_DMEIF   (1 << 2)
-#define DMA_ISR_FEIF    (1 << 0)
-
 /*
  * Devices
  */
@@ -185,35 +166,25 @@ extern dma_dev *DMA2;
  * Convenience functions
  */
 
-extern void dma_init(dma_dev *dev);
+void dma_init(dma_dev *dev);
 
 /** Flags for DMA transfer configuration. */
 typedef enum dma_mode_flags {
-    DMA_MEM_BUF_0 = DMA_CR_CT0, /**< Current memory target buffer 0 */
-    DMA_MEM_BUF_1 = DMA_CR_CT1, /**< Current memory target buffer 1 */
-    DMA_DBL_BUF_MODE = DMA_CR_DBM,  /**< Current memory double buffer mode */
-    DMA_PINC_OFFSET  = DMA_CR_PINCOS,  /**< Peripheral increment offset size */
-    DMA_MINC_MODE  = DMA_CR_MINC,  /**< Memory increment mode */
-    DMA_PINC_MODE  = DMA_CR_PINC,  /**< Peripheral increment mode */
-    DMA_CIRC_MODE  = DMA_CR_CIRC,  /**< Memory Circular mode */
-    DMA_FROM_PER   = DMA_CR_DIR_P2M,  /**< Read from memory to peripheral */
-    DMA_FROM_MEM   = DMA_CR_DIR_M2P,  /**< Read from memory to peripheral */
-    DMA_MEM_TO_MEM = DMA_CR_DIR_M2M,  /**< Read from memory to memory */
-    DMA_PERIF_CTRL   = DMA_CR_PFCTRL,  /**< Peripheral flow controller */
-    DMA_PRIO_MEDIUM    = DMA_CR_PL_MEDIUM,    /**< Medium priority */
-    DMA_PRIO_HIGH      = DMA_CR_PL_HIGH,      /**< High priority */
-    DMA_PRIO_VERY_HIGH = DMA_CR_PL_VERY_HIGH, /**< Very high priority */
-    DMA_TRNS_CMPLT   = DMA_CR_TCIE,   /**< Interrupt on transfer completion */
-    DMA_TRNS_HALF    = DMA_CR_HTIE,  /**< Interrupt on half-transfer */
-    DMA_TRNS_ERR       = DMA_CR_TEIE,  /**< Interrupt on transfer error */
-    DMA_DIR_MODE_ERR   = DMA_CR_DMEIE  /**< Interrupt on direct mode error */
+    DMA_MEM_2_MEM  = 1 << 14, /**< Memory to memory mode */
+    DMA_MINC_MODE  = 1 << 7,  /**< Auto-increment memory address */
+    DMA_PINC_MODE  = 1 << 6,  /**< Auto-increment peripheral address */
+    DMA_CIRC_MODE  = 1 << 5,  /**< Circular mode */
+    DMA_FROM_MEM   = 1 << 4,  /**< Read from memory to peripheral */
+    DMA_TRNS_ERR   = 1 << 3,  /**< Interrupt on transfer error */
+    DMA_HALF_TRNS  = 1 << 2,  /**< Interrupt on half-transfer */
+    DMA_TRNS_CMPLT = 1 << 1   /**< Interrupt on transfer completion */
 } dma_mode_flags;
 
 /** Source and destination transfer sizes. */
 typedef enum dma_xfer_size {
-    DMA_SIZE_8BITS  = ( DMA_CR_MSIZE_8BITS|DMA_CR_PSIZE_8BITS ),        /**< 8-bit transfers */
-    DMA_SIZE_16BITS = (DMA_CR_MSIZE_16BITS|DMA_CR_PSIZE_16BITS),        /**< 16-bit transfers */
-    DMA_SIZE_32BITS = (DMA_CR_MSIZE_32BITS|DMA_CR_PSIZE_32BITS)         /**< 32-bit transfers */
+    DMA_SIZE_8BITS  = 0,        /**< 8-bit transfers */
+    DMA_SIZE_16BITS = 1,        /**< 16-bit transfers */
+    DMA_SIZE_32BITS = 2         /**< 32-bit transfers */
 } dma_xfer_size;
 
 /** DMA channel */
@@ -230,17 +201,17 @@ typedef enum dma_stream {
     
 static inline void dma_setup_transfer(dma_dev       *dev,
                                       dma_stream    stream,
-                                      dma_channel   channel,
-                                      dma_xfer_size trx_size,
                                       __io void     *peripheral_address,
                                       __io void     *memory_address0,
                                       __io void     *memory_address1,
-                                      uint32        flags) {
+                                      uint32         flags,
+                                      uint32         fifo_flags) {
     dev->regs->STREAM[stream].CR &= ~DMA_CR_EN; // disable
     dev->regs->STREAM[stream].PAR = (uint32)peripheral_address;
     dev->regs->STREAM[stream].M0AR = (uint32)memory_address0;
     dev->regs->STREAM[stream].M1AR = (uint32)memory_address1;
-    dev->regs->STREAM[stream].CR = ((flags|channel|trx_size) & 0x0feffffe); // mask out reserved and enable
+    dev->regs->STREAM[stream].FCR = fifo_flags & 0x87; // mask out reserved bits
+    dev->regs->STREAM[stream].CR = flags & 0x0feffffe; // mask out reserved and enable
 }
     
 static inline void dma_set_num_transfers(dma_dev *dev,
@@ -249,12 +220,6 @@ static inline void dma_set_num_transfers(dma_dev *dev,
     dev->regs->STREAM[stream].NDTR = num_transfers;
 }
 
-static inline void dma_set_fifo_flags(dma_dev *dev,
-                                      dma_stream stream,
-                                      uint8 fifo_flags) {
-    dev->regs->STREAM[stream].FCR = fifo_flags & 0x87; // mask out reserved bits
-}
-
 void dma_attach_interrupt(dma_dev *dev,
                           dma_stream stream,
                           void (*handler)(void));
@@ -267,7 +232,6 @@ static inline void dma_enable(dma_dev *dev, dma_stream stream) {
 
 static inline void dma_disable(dma_dev *dev, dma_stream stream) {
     dev->regs->STREAM[stream].CR &= ~DMA_CR_EN;
-	while (dev->regs->STREAM[stream].CR & DMA_CR_EN); // wait till EN bit is reset, see AN4031, chapter 4.1
 }    
 
 /**
diff --git a/STM32F4/cores/maple/libmaple/dma_common.h b/STM32F4/cores/maple/libmaple/dma_common.h
index 5f989219a..15dfab9c8 100644
--- a/STM32F4/cores/maple/libmaple/dma_common.h
+++ b/STM32F4/cores/maple/libmaple/dma_common.h
@@ -56,7 +56,7 @@ extern "C"{
  * Devices
  */
 
-//struct dma_reg_map;
+struct dma_reg_map;
 
 /* Encapsulates state related to user interrupt handlers. You
  * shouldn't touch these directly; use dma_attach_interrupt() and
@@ -82,6 +82,16 @@ extern "C"{
  *
  * @see dma_tube
  */
+typedef enum dma_channel {
+    DMA_CH0 = 0,                /**< Channel 0 */
+    DMA_CH1 = 1,                /**< Channel 1 */
+    DMA_CH2 = 2,                /**< Channel 2 */
+    DMA_CH3 = 3,                /**< Channel 3 */
+    DMA_CH4 = 4,                /**< Channel 4 */
+    DMA_CH5 = 5,                /**< Channel 5 */
+    DMA_CH6 = 6,                /**< Channel 6 */
+    DMA_CH7 = 7,                /**< Channel 7 */
+} dma_channel;
 
 /**
  * @brief Source and destination transfer sizes.
diff --git a/STM32F4/cores/maple/libmaple/spi_f4.c b/STM32F4/cores/maple/libmaple/spi_f4.c
index 8e1bc15bf..43f5092c6 100644
--- a/STM32F4/cores/maple/libmaple/spi_f4.c
+++ b/STM32F4/cores/maple/libmaple/spi_f4.c
@@ -28,7 +28,7 @@
 /**
  * @file libmaple/stm32f1/spi.c
  * @author Marti Bolivar <mbolivar@leaflabs.com>
- * @brief STM32F4 SPI/I2S.
+ * @brief STM32F1 SPI/I2S.
  */
 
 #include <libmaple/spi.h>
diff --git a/STM32F4/libraries/SPI/src/SPI.h b/STM32F4/libraries/SPI/src/SPI.h
index fe728b519..39a5a9eac 100644
--- a/STM32F4/libraries/SPI/src/SPI.h
+++ b/STM32F4/libraries/SPI/src/SPI.h
@@ -42,8 +42,6 @@
 #include <libmaple/dma.h>
 #include <wirish.h>
 
-#define SPI_DMA
-
 // SPI_HAS_TRANSACTION means SPI has
 //   - beginTransaction()
 //   - endTransaction()
@@ -137,12 +135,11 @@ class SPISettings {
 	uint32_t dataSize;
 	
 	spi_dev *spi_d;
+	//uint8_t _SSPin;
 	uint32_t clockDivider;
-
 #ifdef SPI_DMA
+	dma_channel spiRxDmaChannel, spiTxDmaChannel;
 	dma_dev* spiDmaDev;
-	dma_channel spiDmaChannel;
-	dma_stream spiRxDmaStream, spiTxDmaStream;
 #endif
 
 	friend class SPIClass;
@@ -399,6 +396,5 @@ class SPIClass {
 	*/
 };
 
-extern SPIClass SPI;
 
 #endif

From bd3fb68a5ed4bd040809020955891492d909b5c7 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Thu, 11 May 2017 00:05:08 +0200
Subject: [PATCH 071/307] SPI improvements: non-DMA block read + added DMA
 transfer functions

---
 STM32F4/cores/maple/libmaple/dmaF4.c |  35 ++----
 STM32F4/cores/maple/libmaple/dmaF4.h |  72 +++++++++---
 STM32F4/libraries/SPI/src/SPI.cpp    | 161 +++++++++++++++++----------
 STM32F4/libraries/SPI/src/SPI.h      |  17 +--
 4 files changed, 169 insertions(+), 116 deletions(-)

diff --git a/STM32F4/cores/maple/libmaple/dmaF4.c b/STM32F4/cores/maple/libmaple/dmaF4.c
index 4b530aff8..add3d8e51 100644
--- a/STM32F4/cores/maple/libmaple/dmaF4.c
+++ b/STM32F4/cores/maple/libmaple/dmaF4.c
@@ -117,33 +117,16 @@ void dma_detach_interrupt(dma_dev *dev, dma_stream stream) {
     dev->handlers[stream].handler = NULL;
 }
 
+const uint8 dma_isr_bits_shift[] = { 0, 6, 16, 22};
+
+uint8 dma_get_isr_bits(dma_dev *dev, dma_stream stream) {
+	if ( stream&0xFC )	return ((dev->regs->HISR)>>dma_isr_bits_shift[stream&0x03]) & 0x3d;
+	else				return ((dev->regs->LISR)>>dma_isr_bits_shift[stream&0x03]) & 0x3d;
+}
+
 void dma_clear_isr_bits(dma_dev *dev, dma_stream stream) {
-    switch (stream) {
-    case 0:
-        dev->regs->LIFCR|=0x0000003d;
-        break;
-    case 1:
-        dev->regs->LIFCR|=0x00000f40;
-        break;
-    case 2:
-        dev->regs->LIFCR|=0x003d0000;
-        break;
-    case 3:
-        dev->regs->LIFCR|=0x0f400000;
-        break;
-    case 4:
-        dev->regs->HIFCR|=0x0000003d;
-        break;
-    case 5:
-        dev->regs->HIFCR|=0x00000f40;
-        break;
-    case 6:
-        dev->regs->HIFCR|=0x003d0000;
-        break;
-    case 7:
-        dev->regs->HIFCR|=0x0f400000;
-        break;
-    }
+	if ( stream&0xFC )	dev->regs->HIFCR = (uint32)0x0000003d << dma_isr_bits_shift[stream&0x03];
+	else				dev->regs->LIFCR = (uint32)0x0000003d << dma_isr_bits_shift[stream&0x03];
 }
 
 /*
diff --git a/STM32F4/cores/maple/libmaple/dmaF4.h b/STM32F4/cores/maple/libmaple/dmaF4.h
index 6f7086f36..757906c82 100644
--- a/STM32F4/cores/maple/libmaple/dmaF4.h
+++ b/STM32F4/cores/maple/libmaple/dmaF4.h
@@ -25,7 +25,7 @@
  *****************************************************************************/
 
 /**
- * @file dma.h
+ * @file dmaF4.h
  *
  * @author Marti Bolivar <mbolivar@leaflabs.com>;
  *         Original implementation by Michael Hope
@@ -84,7 +84,7 @@ typedef struct dma_reg_map {
  * Register bit definitions
  */
 
-/* Channel configuration register */
+/* Stream configuration register */
 
 #define DMA_CR_CH0                      (0x0 << 25)
 #define DMA_CR_CH1                      (0x1 << 25)
@@ -136,6 +136,25 @@ typedef struct dma_reg_map {
 #define DMA_CR_DMEIE                    (0x1 << 1)
 #define DMA_CR_EN                       (0x1)
 
+typedef enum dma_channel {
+    DMA_CH0 = DMA_CR_CH0,                /**< Channel 0 */
+    DMA_CH1 = DMA_CR_CH1,                /**< Channel 1 */
+    DMA_CH2 = DMA_CR_CH2,                /**< Channel 2 */
+    DMA_CH3 = DMA_CR_CH3,                /**< Channel 3 */
+    DMA_CH4 = DMA_CR_CH4,                /**< Channel 4 */
+    DMA_CH5 = DMA_CR_CH5,                /**< Channel 5 */
+    DMA_CH6 = DMA_CR_CH6,                /**< Channel 6 */
+    DMA_CH7 = DMA_CR_CH7,                /**< Channel 7 */
+} dma_channel;
+
+/* Device interrupt status register flags */
+
+#define DMA_ISR_TCIF    (1 << 5)
+#define DMA_ISR_HTIF    (1 << 4)
+#define DMA_ISR_TEIF    (1 << 3)
+#define DMA_ISR_DMEIF   (1 << 2)
+#define DMA_ISR_FEIF    (1 << 0)
+
 /*
  * Devices
  */
@@ -166,25 +185,35 @@ extern dma_dev *DMA2;
  * Convenience functions
  */
 
-void dma_init(dma_dev *dev);
+extern void dma_init(dma_dev *dev);
 
 /** Flags for DMA transfer configuration. */
 typedef enum dma_mode_flags {
-    DMA_MEM_2_MEM  = 1 << 14, /**< Memory to memory mode */
-    DMA_MINC_MODE  = 1 << 7,  /**< Auto-increment memory address */
-    DMA_PINC_MODE  = 1 << 6,  /**< Auto-increment peripheral address */
-    DMA_CIRC_MODE  = 1 << 5,  /**< Circular mode */
-    DMA_FROM_MEM   = 1 << 4,  /**< Read from memory to peripheral */
-    DMA_TRNS_ERR   = 1 << 3,  /**< Interrupt on transfer error */
-    DMA_HALF_TRNS  = 1 << 2,  /**< Interrupt on half-transfer */
-    DMA_TRNS_CMPLT = 1 << 1   /**< Interrupt on transfer completion */
+    DMA_MEM_BUF_0 = DMA_CR_CT0, /**< Current memory target buffer 0 */
+    DMA_MEM_BUF_1 = DMA_CR_CT1, /**< Current memory target buffer 1 */
+    DMA_DBL_BUF_MODE = DMA_CR_DBM,  /**< Current memory double buffer mode */
+    DMA_PINC_OFFSET  = DMA_CR_PINCOS,  /**< Peripheral increment offset size */
+    DMA_MINC_MODE  = DMA_CR_MINC,  /**< Memory increment mode */
+    DMA_PINC_MODE  = DMA_CR_PINC,  /**< Peripheral increment mode */
+    DMA_CIRC_MODE  = DMA_CR_CIRC,  /**< Memory Circular mode */
+    DMA_FROM_PER   = DMA_CR_DIR_P2M,  /**< Read from memory to peripheral */
+    DMA_FROM_MEM   = DMA_CR_DIR_M2P,  /**< Read from memory to peripheral */
+    DMA_MEM_TO_MEM = DMA_CR_DIR_M2M,  /**< Read from memory to memory */
+    DMA_PERIF_CTRL   = DMA_CR_PFCTRL,  /**< Peripheral flow controller */
+    DMA_PRIO_MEDIUM    = DMA_CR_PL_MEDIUM,    /**< Medium priority */
+    DMA_PRIO_HIGH      = DMA_CR_PL_HIGH,      /**< High priority */
+    DMA_PRIO_VERY_HIGH = DMA_CR_PL_VERY_HIGH, /**< Very high priority */
+    DMA_TRNS_CMPLT   = DMA_CR_TCIE,   /**< Interrupt on transfer completion */
+    DMA_TRNS_HALF    = DMA_CR_HTIE,  /**< Interrupt on half-transfer */
+    DMA_TRNS_ERR       = DMA_CR_TEIE,  /**< Interrupt on transfer error */
+    DMA_DIR_MODE_ERR   = DMA_CR_DMEIE  /**< Interrupt on direct mode error */
 } dma_mode_flags;
 
 /** Source and destination transfer sizes. */
 typedef enum dma_xfer_size {
-    DMA_SIZE_8BITS  = 0,        /**< 8-bit transfers */
-    DMA_SIZE_16BITS = 1,        /**< 16-bit transfers */
-    DMA_SIZE_32BITS = 2         /**< 32-bit transfers */
+    DMA_SIZE_8BITS  = ( DMA_CR_MSIZE_8BITS|DMA_CR_PSIZE_8BITS ),        /**< 8-bit transfers */
+    DMA_SIZE_16BITS = (DMA_CR_MSIZE_16BITS|DMA_CR_PSIZE_16BITS),        /**< 16-bit transfers */
+    DMA_SIZE_32BITS = (DMA_CR_MSIZE_32BITS|DMA_CR_PSIZE_32BITS)         /**< 32-bit transfers */
 } dma_xfer_size;
 
 /** DMA channel */
@@ -201,17 +230,17 @@ typedef enum dma_stream {
     
 static inline void dma_setup_transfer(dma_dev       *dev,
                                       dma_stream    stream,
+                                      dma_channel   channel,
+                                      dma_xfer_size trx_size,
                                       __io void     *peripheral_address,
                                       __io void     *memory_address0,
                                       __io void     *memory_address1,
-                                      uint32         flags,
-                                      uint32         fifo_flags) {
+                                      uint32        flags) {
     dev->regs->STREAM[stream].CR &= ~DMA_CR_EN; // disable
     dev->regs->STREAM[stream].PAR = (uint32)peripheral_address;
     dev->regs->STREAM[stream].M0AR = (uint32)memory_address0;
     dev->regs->STREAM[stream].M1AR = (uint32)memory_address1;
-    dev->regs->STREAM[stream].FCR = fifo_flags & 0x87; // mask out reserved bits
-    dev->regs->STREAM[stream].CR = flags & 0x0feffffe; // mask out reserved and enable
+    dev->regs->STREAM[stream].CR = ((flags|channel|trx_size) & 0x0feffffe); // mask out reserved and enable
 }
     
 static inline void dma_set_num_transfers(dma_dev *dev,
@@ -220,6 +249,12 @@ static inline void dma_set_num_transfers(dma_dev *dev,
     dev->regs->STREAM[stream].NDTR = num_transfers;
 }
 
+static inline void dma_set_fifo_flags(dma_dev *dev,
+                                      dma_stream stream,
+                                      uint8 fifo_flags) {
+    dev->regs->STREAM[stream].FCR = fifo_flags & 0x87; // mask out reserved bits
+}
+
 void dma_attach_interrupt(dma_dev *dev,
                           dma_stream stream,
                           void (*handler)(void));
@@ -232,6 +267,7 @@ static inline void dma_enable(dma_dev *dev, dma_stream stream) {
 
 static inline void dma_disable(dma_dev *dev, dma_stream stream) {
     dev->regs->STREAM[stream].CR &= ~DMA_CR_EN;
+	while (dev->regs->STREAM[stream].CR & DMA_CR_EN); // wait till EN bit is reset, see AN4031, chapter 4.1
 }    
 
 /**
diff --git a/STM32F4/libraries/SPI/src/SPI.cpp b/STM32F4/libraries/SPI/src/SPI.cpp
index baef0abf2..6edbcebed 100644
--- a/STM32F4/libraries/SPI/src/SPI.cpp
+++ b/STM32F4/libraries/SPI/src/SPI.cpp
@@ -40,6 +40,8 @@
 #include "wirish.h"
 #include "boards.h"
 
+#define DMA_TIMEOUT 100
+
 #if CYCLES_PER_MICROSECOND != 168
 /* TODO [0.2.0?] something smarter than this */
 #warning "Unexpected clock speed; SPI frequency calculation will be incorrect"
@@ -115,27 +117,37 @@ SPIClass::SPIClass(uint32 spi_num) {
 	
 	// Init things specific to each SPI device
 	// clock divider setup is a bit of hack, and needs to be improved at a later date.
+/*****************************************************************************/
+//           DMA / Channel / Stream 
+//            Rx             Tx
+// SPI1:  2 / 3 / 0 (2) - 2 / 3 / 3 (5)
+// SPI2:  1 / 0 / 3     - 1 / 0 / 4
+// SPI3:  1 / 0 / 0 (2) - 1 / 0 / 5 (7)
+/*****************************************************************************/
 	_settings[0].spi_d = SPI1;
 	_settings[0].clockDivider = determine_baud_rate(_settings[0].spi_d, _settings[0].clock);
 #ifdef SPI_DMA
-	_settings[0].spiDmaDev = DMA1;
-	_settings[0].spiTxDmaChannel = DMA_CH3;
-	_settings[0].spiRxDmaChannel = DMA_CH2;
+	_settings[0].spiDmaDev = DMA2;
+	_settings[0].spiDmaChannel = DMA_CH3;
+	_settings[0].spiRxDmaStream  = DMA_STREAM0; // alternative: DMA_STREAM2
+	_settings[0].spiTxDmaStream  = DMA_STREAM3; // alternative: DMA_STREAM5
 #endif
 	_settings[1].spi_d = SPI2;
 	_settings[1].clockDivider = determine_baud_rate(_settings[1].spi_d, _settings[1].clock);
 #ifdef SPI_DMA
 	_settings[1].spiDmaDev = DMA1;
-	_settings[1].spiTxDmaChannel = DMA_CH5;
-	_settings[1].spiRxDmaChannel = DMA_CH4;
+	_settings[1].spiDmaChannel = DMA_CH0;
+	_settings[1].spiRxDmaStream  = DMA_STREAM3; // alternative: -
+	_settings[1].spiTxDmaStream  = DMA_STREAM4; // alternative: -
 #endif
 #if BOARD_NR_SPI >= 3
 	_settings[2].spi_d = SPI3;
 	_settings[2].clockDivider = determine_baud_rate(_settings[2].spi_d, _settings[2].clock);
 #ifdef SPI_DMA
-	_settings[2].spiDmaDev = DMA2;
-	_settings[2].spiTxDmaChannel = DMA_CH2;
-	_settings[2].spiRxDmaChannel = DMA_CH1;
+	_settings[2].spiDmaDev = DMA1;
+	_settings[2].spiDmaChannel = DMA_CH0;
+	_settings[2].spiRxDmaStream  = DMA_STREAM0; // alternative: DMA_STREAM2
+	_settings[2].spiTxDmaStream  = DMA_STREAM5; // alternative: DMA_STREAM7
 #endif
 #endif
 
@@ -265,9 +277,6 @@ void SPIClass::beginTransaction(uint8_t pin, SPISettings settings)
 	#ifdef SPI_DEBUG
 	Serial.println("SPIClass::beginTransaction");
 	#endif
-	//_SSPin=pin;
-	//pinMode(_SSPin,OUTPUT);
-	//digitalWrite(_SSPin,LOW);
 	setBitOrder(settings.bitOrder);
 	setDataMode(settings.dataMode);
 	setDataSize(settings.dataSize);
@@ -321,14 +330,23 @@ uint16 SPIClass::read(void)
 
 void SPIClass::read(uint8 *buf, uint32 len)
 {
-	spi_rx_reg(_currentSetting->spi_d); // clear the RX buffer in case a byte is waiting on it.
+	if ( len == 0 ) return;
+	spi_rx_reg(_currentSetting->spi_d);		// clear the RX buffer in case a byte is waiting on it.
 	spi_reg_map * regs = _currentSetting->spi_d->regs;
-	// start sequence
-	while ( (len--)>0) {
-		regs->DR = 0x00FF; // " write the data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-		while ( (regs->SR & SPI_SR_RXNE)==0 ) ; // wait till data is available in the Rx register
-		*buf++ = (uint8)(regs->DR); // read and store the received byte
-    }
+	// start sequence: write byte 0
+	regs->DR = 0x00FF;						// write the first byte
+	// main loop
+	while ( (--len) ) {
+		while( !(regs->SR & SPI_SR_TXE) );		// wait for TXE flag
+		noInterrupts();							// go atomic level - avoid interrupts to surely get the previously received data
+		regs->DR = 0x00FF;						// write the next data item to be transmitted into the SPI_DR register. This clears the TXE flag.
+		while ( !(regs->SR & SPI_SR_RXNE) );	// wait till data is available in the DR register
+		*buf++ = (uint8)(regs->DR);				// read and store the received byte. This clears the RXNE flag.
+		interrupts();							// let systick do its job
+	}
+	// read remaining last byte
+	while ( !(regs->SR & SPI_SR_RXNE) );	// wait till data is available in the Rx register
+	*buf++ = (uint8)(regs->DR);				// read and store the received byte
 }
 
 void SPIClass::write(uint16 data)
@@ -393,47 +411,66 @@ uint16_t SPIClass::transfer16(uint16_t wr_data) const
 uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length)
 {
 	if (length == 0) return 0;
+
 	uint8 b = 0;
-	spi_rx_reg(_currentSetting->spi_d); //Clear the RX buffer in case a byte is waiting on it.
-//	dma1_ch3_Active=true;
+
     dma_init(_currentSetting->spiDmaDev);
 //	dma_attach_interrupt(DMA1, DMA_CH3, &SPIClass::DMA1_CH3_Event);
-
 	// RX
-	spi_rx_dma_enable(_currentSetting->spi_d);
 	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==SPI_DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
-	dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
-                     receiveBuf, dma_bit_size, (DMA_MINC_MODE | DMA_TRNS_CMPLT));// receive buffer DMA
-	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, length);
+	dma_setup_transfer(	_currentSetting->spiDmaDev,
+						_currentSetting->spiRxDmaStream,
+						_currentSetting->spiDmaChannel,
+						dma_bit_size,
+						&_currentSetting->spi_d->regs->DR,	// peripheral address
+						receiveBuf,							// memory bank 0 address
+						NULL,								// memory bank 1 address
+						(DMA_MINC_MODE | DMA_FROM_PER | DMA_PRIO_VERY_HIGH)		// flags
+	);
+	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaStream, length);
+	dma_set_fifo_flags(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaStream, 0);
+	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaStream);
 
 	// TX
-	uint32 flags = (DMA_MINC_MODE | DMA_FROM_MEM | DMA_TRNS_CMPLT);
-	spi_tx_dma_enable(_currentSetting->spi_d);	
+	uint32 flags = (DMA_MINC_MODE | DMA_FROM_MEM); // | DMA_TRNS_CMPLT);
 	if ( transmitBuf==0 ) {
 		static uint8_t ff = 0XFF;
 		transmitBuf = &ff;
-		flags ^= DMA_MINC_MODE; // remove increment mode
+		flags &= ~((uint32)DMA_MINC_MODE); // remove increment mode
 	}
-    dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
-                       transmitBuf, dma_bit_size, flags);// Transmit buffer DMA 
-	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
-
-	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);// enable receive
-	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
+	dma_setup_transfer(	_currentSetting->spiDmaDev,
+						_currentSetting->spiTxDmaStream,
+						_currentSetting->spiDmaChannel,
+						dma_bit_size,
+						&_currentSetting->spi_d->regs->DR,	// peripheral address
+						transmitBuf,						// memory bank 0 address
+						NULL,								// memory bank 1 address
+						flags
+	);
+	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream, length);
+	dma_set_fifo_flags(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream, 0);
+	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream);
+	// software enable sequence, see AN4031, chapter 4.3
+	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaStream);// enable receive
+	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream);// enable transmit
+	spi_rx_reg(_currentSetting->spi_d); //Clear the RX buffer in case a byte is waiting on it.
+	spi_rx_dma_enable(_currentSetting->spi_d);
+	spi_tx_dma_enable(_currentSetting->spi_d);	// must be the last enable to avoid DMA error flag
 	
     uint32_t m = millis();
-	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
+	while ((b = dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream) & DMA_ISR_TCIF)==0 ) {// wait for completion flag to be set
+		if ( b&(DMA_ISR_TEIF|DMA_ISR_DMEIF|DMA_ISR_FEIF) ) { b = 1; break; } // break on any error flag
 		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
     }
-	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+	if (b & DMA_ISR_TCIF) b = 0;
 
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
-    dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
-	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
-	spi_rx_dma_disable(_currentSetting->spi_d); // And disable generation of DMA request from the SPI port so other peripherals can use the channels
+	// software disable sequence, see AN4031, chapter 4.1
 	spi_tx_dma_disable(_currentSetting->spi_d);
-	//uint16 x = spi_rx_reg(_currentSetting->spi_d); // dummy read, needed, don't remove!
+	spi_rx_dma_disable(_currentSetting->spi_d);
+	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaStream);
+    dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream);
     return b;
 }
 
@@ -446,28 +483,36 @@ uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length
 uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length, bool minc)
 {
 	if (length == 0) return 0;
-	uint32 flags = ( (DMA_MINC_MODE*minc) | DMA_FROM_MEM | DMA_TRNS_CMPLT);
 	uint8 b = 0;
 	dma_init(_currentSetting->spiDmaDev);
 	// TX
-	spi_tx_dma_enable(_currentSetting->spi_d);
 	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==SPI_DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
-	dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
-                       transmitBuf, dma_bit_size, flags);// Transmit buffer DMA
-	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
-	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
+	dma_setup_transfer(	_currentSetting->spiDmaDev,
+						_currentSetting->spiTxDmaStream,
+						_currentSetting->spiDmaChannel,
+						dma_bit_size,
+						&_currentSetting->spi_d->regs->DR,	// peripheral address
+						transmitBuf,						// memory bank 0 address
+						NULL,								// memory bank 1 address
+						( (DMA_MINC_MODE*minc) | DMA_FROM_MEM ) //| DMA_TRNS_CMPLT ) // flags
+	);// Transmit buffer DMA 
+	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream, length);
+	dma_set_fifo_flags(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream, 0);
+	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream);
+	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream);// enable transmit
+	spi_tx_dma_enable(_currentSetting->spi_d);
 
 	uint32_t m = millis();
-	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
+	while ((b = dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream) & DMA_ISR_TCIF)==0 ) {// wait for completion flag to be set
+		if ( b&(DMA_ISR_TEIF|DMA_ISR_DMEIF|DMA_ISR_FEIF) ) { b = 1; break; } // break on any error flag
 		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
-	}
-	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+    }
+	if (b & DMA_ISR_TCIF) b = 0;
 
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
-	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 	spi_tx_dma_disable(_currentSetting->spi_d);
-	//uint16 x = spi_rx_reg(_currentSetting->spi_d); // dummy read, needed, don't remove!
+	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream);
 	return b;
 }
 #endif
@@ -507,18 +552,13 @@ uint8 SPIClass::nssPin(void) {
  */
 
 uint8 SPIClass::send(uint8 data) {
-    uint8 buf[] = {data};
-    return this->send(buf, 1);
+    this->write(data);
+    return 1;
 }
 
 uint8 SPIClass::send(uint8 *buf, uint32 len) {
-    uint32 txed = 0;
-    uint8 ret = 0;
-    while (txed < len) {
-        this->write(buf[txed++]);
-        ret = this->read();
-    }
-    return ret;
+    this->write(buf, len);
+    return len;
 }
 
 uint8 SPIClass::recv(void) {
@@ -640,4 +680,3 @@ static spi_baud_rate determine_baud_rate(spi_dev *dev, uint32_t freq) {
 
 
 //SPIClass SPI(3);
-
diff --git a/STM32F4/libraries/SPI/src/SPI.h b/STM32F4/libraries/SPI/src/SPI.h
index 39a5a9eac..d9e1e7a8b 100644
--- a/STM32F4/libraries/SPI/src/SPI.h
+++ b/STM32F4/libraries/SPI/src/SPI.h
@@ -42,6 +42,8 @@
 #include <libmaple/dma.h>
 #include <wirish.h>
 
+#define SPI_DMA
+
 // SPI_HAS_TRANSACTION means SPI has
 //   - beginTransaction()
 //   - endTransaction()
@@ -135,19 +137,18 @@ class SPISettings {
 	uint32_t dataSize;
 	
 	spi_dev *spi_d;
-	//uint8_t _SSPin;
 	uint32_t clockDivider;
+
 #ifdef SPI_DMA
-	dma_channel spiRxDmaChannel, spiTxDmaChannel;
 	dma_dev* spiDmaDev;
+	dma_channel spiDmaChannel;
+	dma_stream spiRxDmaStream, spiTxDmaStream;
 #endif
 
 	friend class SPIClass;
 };
 
 
-
-
 /**
  * @brief Wirish SPI interface.
  *
@@ -157,18 +158,11 @@ class SPISettings {
 class SPIClass {
 public:
 
-
-
     /**
      * @param spiPortNumber Number of the SPI port to manage.
      */
     SPIClass(uint32 spiPortNumber);
 
-    /*
-     * Set up/tear down
-     */
-
-
 
     /**
      * @brief Equivalent to begin(SPI_1_125MHZ, MSBFIRST, 0).
@@ -396,5 +390,6 @@ class SPIClass {
 	*/
 };
 
+extern SPIClass SPI;
 
 #endif

From 679217dfafc66b0f0a3c3741396328c8e70df5ad Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Thu, 11 May 2017 00:57:08 +0200
Subject: [PATCH 072/307] F4 development

- added generic F4 variant
- removed F1 and F2 files/defines
- resolved include headers - now libraries are detected within sketches
- reworked + added new GPIO access functions
- moved and size-optimized PIN_MAP in flash
- SPI improvements: optimized block read + added DMA
---
 STM32F4/boards.txt                            |  39 ++
 STM32F4/cores/maple/Arduino.h                 |   6 -
 STM32F4/cores/maple/Client.h                  |   5 +-
 STM32F4/cores/maple/HardwareTimer.h           |   2 +-
 STM32F4/cores/maple/IPAddress.h               |   4 +-
 STM32F4/cores/maple/Server.h                  |   4 +-
 STM32F4/cores/maple/Stream.h                  |   4 +-
 STM32F4/cores/maple/Udp.h                     |   4 +-
 STM32F4/cores/maple/WProgram.h                |   7 +-
 STM32F4/cores/maple/WString.h                 |   7 +-
 STM32F4/cores/maple/bits.h                    |   5 +
 STM32F4/cores/maple/boards.cpp                |  32 +-
 STM32F4/cores/maple/boards.h                  |  39 +-
 STM32F4/cores/maple/ext_interrupts.cpp        |   8 +-
 STM32F4/cores/maple/ext_interrupts.h          |   9 +-
 STM32F4/cores/maple/io.h                      |  13 +-
 STM32F4/cores/maple/itoa.h                    |   4 +-
 STM32F4/cores/maple/libmaple/HardwareSPI.cpp  | 424 -------------
 STM32F4/cores/maple/libmaple/HardwareSPI.h    | 279 ---------
 .../cores/maple/libmaple/HardwareSerial.cpp   |  30 +-
 STM32F4/cores/maple/libmaple/HardwareSerial.h |   2 +-
 STM32F4/cores/maple/libmaple/adc.c            |  33 +-
 STM32F4/cores/maple/libmaple/adc.h            |  54 +-
 STM32F4/cores/maple/libmaple/dac.c            |   4 +-
 STM32F4/cores/maple/libmaple/dma.h            |   7 +-
 STM32F4/cores/maple/libmaple/dmaF1.c          | 383 ------------
 STM32F4/cores/maple/libmaple/dmaF1.h          | 453 --------------
 .../cores/maple/libmaple/{dmaF2.c => dmaF4.c} |  39 +-
 .../cores/maple/libmaple/{dmaF2.h => dmaF4.h} |  72 ++-
 STM32F4/cores/maple/libmaple/exti.h           |   4 -
 STM32F4/cores/maple/libmaple/fsmc.c           |  53 +-
 STM32F4/cores/maple/libmaple/gpio.h           | 102 +++-
 STM32F4/cores/maple/libmaple/gpioF1.c         | 200 ------
 STM32F4/cores/maple/libmaple/gpioF1.h         | 530 ----------------
 .../maple/libmaple/{gpioF2.c => gpioF4.c}     |  79 ++-
 .../maple/libmaple/{gpioF2.h => gpio_def.h}   |  90 +--
 STM32F4/cores/maple/libmaple/i2c.c            |  40 +-
 STM32F4/cores/maple/libmaple/i2c.h            |   2 +-
 STM32F4/cores/maple/libmaple/libmaple.h       |  14 +-
 STM32F4/cores/maple/libmaple/libmaple_types.h |  15 +-
 STM32F4/cores/maple/libmaple/rcc.h            |   7 +-
 STM32F4/cores/maple/libmaple/rccF1.c          | 233 -------
 STM32F4/cores/maple/libmaple/rccF1.h          | 572 ------------------
 .../cores/maple/libmaple/{rccF2.c => rccF4.c} |   7 +-
 .../cores/maple/libmaple/{rccF2.h => rccF4.h} |   0
 STM32F4/cores/maple/libmaple/rules.mk         |  22 -
 STM32F4/cores/maple/libmaple/spi.c            |  39 +-
 STM32F4/cores/maple/libmaple/spi.h            |  19 +-
 STM32F4/cores/maple/libmaple/spiF4.h          |  15 +-
 STM32F4/cores/maple/libmaple/spi_f4.c         |  26 +-
 STM32F4/cores/maple/libmaple/stm32.h          |  63 +-
 STM32F4/cores/maple/libmaple/timer.c          |  16 +-
 STM32F4/cores/maple/libmaple/timer.h          |  19 +-
 STM32F4/cores/maple/libmaple/usart.h          |   6 +-
 .../Class/audio/inc/usbd_audio_core.h         |   2 +-
 .../Class/cdc/inc/usbd_cdc_core.h             |   3 +-
 .../Class/cdc/src/usbd_cdc_core.c             |   7 +-
 .../Core/inc/usbd_core.h                      |   4 +-
 .../Core/inc/usbd_def.h                       |   2 +-
 .../Core/inc/usbd_req.h                       |   2 +-
 .../Core/src/usbd_core.c                      |  10 +-
 .../Core/src/usbd_ioreq.c                     |   2 +-
 .../Core/src/usbd_req.c                       |   6 +-
 .../usbF4/STM32_USB_OTG_Driver/inc/usb_core.h |   2 +-
 .../STM32_USB_OTG_Driver/inc/usb_defines.h    |   2 +-
 .../usbF4/STM32_USB_OTG_Driver/inc/usb_otg.h  |   1 +
 .../usbF4/STM32_USB_OTG_Driver/inc/usb_regs.h |   4 +-
 .../usbF4/STM32_USB_OTG_Driver/src/usb_core.c |   4 +-
 .../usbF4/STM32_USB_OTG_Driver/src/usb_dcd.c  |   4 +-
 .../STM32_USB_OTG_Driver/src/usb_dcd_int.c    |   4 +-
 .../cores/maple/libmaple/usbF4/VCP/core_cm4.h |   2 +-
 STM32F4/cores/maple/libmaple/usbF4/VCP/misc.c |   2 +-
 .../cores/maple/libmaple/usbF4/VCP/usb_bsp.c  |  22 +-
 .../cores/maple/libmaple/usbF4/VCP/usb_conf.h |   4 +
 .../maple/libmaple/usbF4/VCP/usbd_cdc_vcp.c   |   2 +-
 .../maple/libmaple/usbF4/VCP/usbd_cdc_vcp.h   |   2 +-
 .../maple/libmaple/usbF4/VCP/usbd_conf.h      |   1 +
 .../maple/libmaple/usbF4/VCP/usbd_desc.c      |   6 +-
 .../maple/libmaple/usbF4/VCP/usbd_desc.h      |   2 +-
 .../cores/maple/libmaple/usbF4/VCP/usbd_usr.c |   4 +-
 STM32F4/cores/maple/libmaple/usbF4/usb.c      |  33 +-
 STM32F4/cores/maple/libmaple/usbF4/usb.h      |   2 +-
 STM32F4/cores/maple/libmaple/util.c           |   6 +-
 STM32F4/cores/maple/libmaple/util.h           |   5 +-
 STM32F4/cores/maple/pwm.cpp                   |   4 +-
 STM32F4/cores/maple/usb_serial.cpp            |   6 +-
 STM32F4/cores/maple/usb_serial.h              |  15 +-
 STM32F4/cores/maple/wirish.h                  |  15 +-
 STM32F4/cores/maple/wirish_analog.cpp         |   2 -
 STM32F4/cores/maple/wirish_constants.h        |   4 +-
 STM32F4/cores/maple/wirish_debug.h            |   7 +-
 STM32F4/cores/maple/wirish_digital.cpp        |  31 +-
 STM32F4/cores/maple/wirish_math.h             |   4 +-
 STM32F4/cores/maple/wirish_time.cpp           |   6 +-
 STM32F4/cores/maple/wirish_time.h             |   5 +-
 STM32F4/cores/maple/wirish_types.h            |  23 +-
 STM32F4/libraries/SPI/library.properties      |   1 +
 STM32F4/libraries/SPI/src/SPI.cpp             | 518 ++++++++--------
 STM32F4/libraries/SPI/src/SPI.h               | 157 ++---
 STM32F4/platform.txt                          |  20 +-
 .../gpio.c => system/libmaple/Arduino.h}      |  30 +-
 .../variants/generic_f407v/generic_f407v.cpp  |  81 +++
 .../variants/generic_f407v/generic_f407v.h    | 163 +++++
 STM32F4/variants/generic_f407v/ld/common.inc  | 219 +++++++
 .../variants/generic_f407v/ld/extra_libs.inc  |   7 +
 STM32F4/variants/generic_f407v/ld/flash.ld    |  20 +
 STM32F4/variants/generic_f407v/ld/jtag.ld     |  20 +
 STM32F4/variants/generic_f407v/ld/names.inc   |  78 +++
 STM32F4/variants/generic_f407v/ld/ram.ld      |  19 +
 .../generic_f407v/ld/vector_symbols.inc       |  78 +++
 STM32F4/variants/generic_f407v/pin_map.c      | 210 +++++++
 STM32F4/variants/generic_f407v/pins_arduino.h |   6 +
 STM32F4/variants/generic_f407v/stm32_isrs.S   | 323 ++++++++++
 .../generic_f407v/stm32_vector_table.S        | 113 ++++
 STM32F4/variants/generic_f407v/variant.h      |  21 +
 .../generic_f407v/wirish/start.S}             |  40 +-
 .../variants/generic_f407v/wirish/start_c.c   |  95 +++
 117 files changed, 2546 insertions(+), 4092 deletions(-)
 delete mode 100644 STM32F4/cores/maple/Arduino.h
 delete mode 100644 STM32F4/cores/maple/libmaple/HardwareSPI.cpp
 delete mode 100644 STM32F4/cores/maple/libmaple/HardwareSPI.h
 delete mode 100644 STM32F4/cores/maple/libmaple/dmaF1.c
 delete mode 100644 STM32F4/cores/maple/libmaple/dmaF1.h
 rename STM32F4/cores/maple/libmaple/{dmaF2.c => dmaF4.c} (91%)
 rename STM32F4/cores/maple/libmaple/{dmaF2.h => dmaF4.h} (74%)
 delete mode 100644 STM32F4/cores/maple/libmaple/gpioF1.c
 delete mode 100644 STM32F4/cores/maple/libmaple/gpioF1.h
 rename STM32F4/cores/maple/libmaple/{gpioF2.c => gpioF4.c} (78%)
 rename STM32F4/cores/maple/libmaple/{gpioF2.h => gpio_def.h} (90%)
 delete mode 100644 STM32F4/cores/maple/libmaple/rccF1.c
 delete mode 100644 STM32F4/cores/maple/libmaple/rccF1.h
 rename STM32F4/cores/maple/libmaple/{rccF2.c => rccF4.c} (99%)
 rename STM32F4/cores/maple/libmaple/{rccF2.h => rccF4.h} (100%)
 rename STM32F4/{cores/maple/libmaple/gpio.c => system/libmaple/Arduino.h} (79%)
 create mode 100644 STM32F4/variants/generic_f407v/generic_f407v.cpp
 create mode 100644 STM32F4/variants/generic_f407v/generic_f407v.h
 create mode 100644 STM32F4/variants/generic_f407v/ld/common.inc
 create mode 100644 STM32F4/variants/generic_f407v/ld/extra_libs.inc
 create mode 100644 STM32F4/variants/generic_f407v/ld/flash.ld
 create mode 100644 STM32F4/variants/generic_f407v/ld/jtag.ld
 create mode 100644 STM32F4/variants/generic_f407v/ld/names.inc
 create mode 100644 STM32F4/variants/generic_f407v/ld/ram.ld
 create mode 100644 STM32F4/variants/generic_f407v/ld/vector_symbols.inc
 create mode 100644 STM32F4/variants/generic_f407v/pin_map.c
 create mode 100644 STM32F4/variants/generic_f407v/pins_arduino.h
 create mode 100644 STM32F4/variants/generic_f407v/stm32_isrs.S
 create mode 100644 STM32F4/variants/generic_f407v/stm32_vector_table.S
 create mode 100644 STM32F4/variants/generic_f407v/variant.h
 rename STM32F4/{cores/maple/libmaple/rcc.c => variants/generic_f407v/wirish/start.S} (54%)
 create mode 100644 STM32F4/variants/generic_f407v/wirish/start_c.c

diff --git a/STM32F4/boards.txt b/STM32F4/boards.txt
index 7577d1949..04bfd0fd0 100644
--- a/STM32F4/boards.txt
+++ b/STM32F4/boards.txt
@@ -1,5 +1,7 @@
 # 
 
+menu.usb_cfg=USB configuration
+
 ##############################################################
 discovery_f407.name=STM32 Discovery F407
 
@@ -29,6 +31,43 @@ discovery_f407.build.error_led_port=GPIOD
 discovery_f407.build.error_led_pin=14
 discovery_f407.build.board=STM32DiscoveryF407
 
+##############################################################
+generic_f407v.name=Generic STM32F407V series
+
+generic_f407v.upload.tool=stlink_upload
+generic_f407v.upload.protocol=stlink
+
+generic_f407v.upload.file_type=bin
+generic_f407v.upload.ram.maximum_size=131072
+generic_f407v.upload.flash.maximum_size=514288
+generic_f407v.upload.maximum_size=514288
+
+#generic_f407v.upload.usbID=0483:3748
+#generic_f407v.upload.altID=1
+#generic_f407v.upload.auto_reset=true
+
+generic_f407v.build.mcu=cortex-m4
+generic_f407v.build.f_cpu=168000000L
+generic_f407v.build.core=maple
+generic_f407v.build.extra_flags=-mthumb -DSTM32_HIGH_DENSITY -DSTM32F4 -DBOARD_generic_f407v
+generic_f407v.build.ldscript=ld/jtag.ld
+generic_f407v.build.variant=generic_f407v
+generic_f407v.build.variant_system_lib=lib_f407.a
+generic_f407v.build.vect=VECT_TAB_BASE
+generic_f407v.build.density=STM32_HIGH_DENSITY
+generic_f407v.build.error_led_port=GPIOA
+generic_f407v.build.error_led_pin=7
+generic_f407v.build.board=STM32GenericF407VET6
+
+generic_f407v.menu.usb_cfg.usb_nc=USB inactive
+generic_f407v.menu.usb_cfg.usb_nc.build.cpu_flags=-DUSB_NC
+
+generic_f407v.menu.usb_cfg.usb_serial=USB serial (CDC)
+generic_f407v.menu.usb_cfg.usb_serial.build.cpu_flags=-DSERIAL_USB
+
+generic_f407v.menu.usb_cfg.usb_msc=USB Mass Storage (MSC)
+generic_f407v.menu.usb_cfg.usb_msc.build.cpu_flags=-DUSB_MSC
+
 ##############################################################
 stm32f4stamp.name=STM32F4Stamp F405
 
diff --git a/STM32F4/cores/maple/Arduino.h b/STM32F4/cores/maple/Arduino.h
deleted file mode 100644
index d02a50cba..000000000
--- a/STM32F4/cores/maple/Arduino.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef Arduino_h
-#define Arduino_h
-#include "WProgram.h"
-#endif
-
-#include "variant.h"
diff --git a/STM32F4/cores/maple/Client.h b/STM32F4/cores/maple/Client.h
index b8e5d935f..57bedb8e0 100644
--- a/STM32F4/cores/maple/Client.h
+++ b/STM32F4/cores/maple/Client.h
@@ -17,8 +17,9 @@
   Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 
-#ifndef client_h
-#define client_h
+#ifndef _CLIENT_H_
+#define _CLIENT_H_
+
 #include "Print.h"
 #include "Stream.h"
 #include "IPAddress.h"
diff --git a/STM32F4/cores/maple/HardwareTimer.h b/STM32F4/cores/maple/HardwareTimer.h
index 89e356499..c90356bf6 100644
--- a/STM32F4/cores/maple/HardwareTimer.h
+++ b/STM32F4/cores/maple/HardwareTimer.h
@@ -33,7 +33,7 @@
 
 // TODO [0.1.0] Remove deprecated pieces, pick a better API
 
-#include "timer.h"
+#include <libmaple/timer.h>
 
 /** Timer mode. */
 typedef timer_mode TimerMode;
diff --git a/STM32F4/cores/maple/IPAddress.h b/STM32F4/cores/maple/IPAddress.h
index 271b24025..c6e06972a 100644
--- a/STM32F4/cores/maple/IPAddress.h
+++ b/STM32F4/cores/maple/IPAddress.h
@@ -17,8 +17,8 @@
   Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 
-#ifndef IPAddress_h
-#define IPAddress_h
+#ifndef _IPAddress_h_
+#define _IPAddress_h_
 
 #include <stdint.h>
 #include <WString.h>
diff --git a/STM32F4/cores/maple/Server.h b/STM32F4/cores/maple/Server.h
index 69e3e39fe..4a95c9f51 100644
--- a/STM32F4/cores/maple/Server.h
+++ b/STM32F4/cores/maple/Server.h
@@ -17,8 +17,8 @@
   Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 
-#ifndef server_h
-#define server_h
+#ifndef _SERVER_H_
+#define _SERVER_H_
 
 #include "Print.h"
 
diff --git a/STM32F4/cores/maple/Stream.h b/STM32F4/cores/maple/Stream.h
index abdcd1768..870fbf0e5 100644
--- a/STM32F4/cores/maple/Stream.h
+++ b/STM32F4/cores/maple/Stream.h
@@ -19,8 +19,8 @@
   parsing functions based on TextFinder library by Michael Margolis
 */
 
-#ifndef Stream_h
-#define Stream_h
+#ifndef _STREAM_H_
+#define _STREAM_H_
 
 #include <inttypes.h>
 #include "Print.h"
diff --git a/STM32F4/cores/maple/Udp.h b/STM32F4/cores/maple/Udp.h
index dc5644b9d..1652cafc9 100644
--- a/STM32F4/cores/maple/Udp.h
+++ b/STM32F4/cores/maple/Udp.h
@@ -32,8 +32,8 @@
  * bjoern@cs.stanford.edu 12/30/2008
  */
 
-#ifndef udp_h
-#define udp_h
+#ifndef _UDP_H_
+#define _UDP_H_
 
 #include <Stream.h>
 #include <IPAddress.h>
diff --git a/STM32F4/cores/maple/WProgram.h b/STM32F4/cores/maple/WProgram.h
index 2949a0a59..82b759a64 100644
--- a/STM32F4/cores/maple/WProgram.h
+++ b/STM32F4/cores/maple/WProgram.h
@@ -24,7 +24,12 @@
  * SOFTWARE.
  *****************************************************************************/
 
-#include "wirish.h"
+#ifndef _WPROGRAM_H_
+#define _WPROGRAM_H_
+
+#include <wirish.h>
 
 void setup();
 void loop();
+
+#endif
\ No newline at end of file
diff --git a/STM32F4/cores/maple/WString.h b/STM32F4/cores/maple/WString.h
index 903857809..ec0eae7fb 100644
--- a/STM32F4/cores/maple/WString.h
+++ b/STM32F4/cores/maple/WString.h
@@ -19,8 +19,9 @@
   Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 
-#ifndef String_class_h
-#define String_class_h
+#ifndef _WSTRING_H_
+#define _WSTRING_H_
+
 #ifdef __cplusplus
 
 #include <stdlib.h>
@@ -225,4 +226,4 @@ class StringSumHelper : public String
 };
 
 #endif  // __cplusplus
-#endif  // String_class_h
+#endif  // _WSTRING_H_
diff --git a/STM32F4/cores/maple/bits.h b/STM32F4/cores/maple/bits.h
index 3e755b7f4..3e3eff1ec 100644
--- a/STM32F4/cores/maple/bits.h
+++ b/STM32F4/cores/maple/bits.h
@@ -27,4 +27,9 @@
 /* Note: Use of this header file is deprecated.  Use bit_constants.h
    instead. */
 
+#ifndef _BITS_H_
+#define _BITS_H_
+
 #include "bit_constants.h"
+
+#endif
diff --git a/STM32F4/cores/maple/boards.cpp b/STM32F4/cores/maple/boards.cpp
index a85657163..0d55e9414 100644
--- a/STM32F4/cores/maple/boards.cpp
+++ b/STM32F4/cores/maple/boards.cpp
@@ -33,17 +33,16 @@
  */
 #include "boards.h"
 
-#include "flash.h"
-#include "rcc.h"
-#include "nvic.h"
-#include "systick.h"
-#include "gpio.h"
-#include "adc.h"
-#include "timer.h"
+#include <libmaple/flash.h>
+#include <libmaple/rcc.h>
+#include <libmaple/nvic.h>
+#include <libmaple/systick.h>
+#include <libmaple/gpio.h>
+#include <libmaple/adc.h>
+#include <libmaple/timer.h>
 #include "usb.h"
-#ifdef STM32F2
-//#include "usbF4.h"
-#endif
+#include "usb_serial.h"
+
 
 static void setupFlash(void);
 static void setupClocks(void);
@@ -59,7 +58,7 @@ void init(void) {
 	systick_init(SYSTICK_RELOAD_VAL);
 	gpio_init_all();
 
-#ifdef STM32F2
+#ifdef STM32F4
 	rcc_clk_enable(RCC_SYSCFG);
 #else
     afio_init();
@@ -69,7 +68,10 @@ void init(void) {
     setupADC();
     setupTimers();
 
-    //setupUSB();
+#ifdef SERIAL_USB
+    setupUSB();
+    SerialUSB.begin();
+#endif
 }
 
 /* You could farm this out to the files in boards/ if e.g. it takes
@@ -84,11 +86,13 @@ bool boardUsesPin(uint8 pin) {
 }
 
 static void setupFlash(void) {
+/*
 #ifndef STM32F2
 	// for F2 and F4 CPUs this is done in SetupClock...(), e.g. in SetupClock168MHz()
     flash_enable_prefetch();
     flash_set_latency(FLASH_WAIT_STATE_2);
 #endif
+*/
 }
 
 /*
@@ -121,8 +125,8 @@ static void setupNVIC() {
 static void adcDefaultConfig(const adc_dev* dev);
 
 static void setupADC() {
-#ifdef STM32F2
-	setupADC_F2();
+#ifdef STM32F4
+	setupADC_F4();
 #else
 	rcc_set_prescaler(RCC_PRESCALER_ADC, RCC_ADCPRE_PCLK_DIV_6);
 #endif
diff --git a/STM32F4/cores/maple/boards.h b/STM32F4/cores/maple/boards.h
index 00d07cddb..d37bff4a5 100644
--- a/STM32F4/cores/maple/boards.h
+++ b/STM32F4/cores/maple/boards.h
@@ -39,11 +39,8 @@
 #ifndef _BOARDS_H_
 #define _BOARDS_H_
 
-#include "libmaple.h"
-#include "gpio.h"
-#include "timer.h"
-
-#include "wirish_types.h"
+#include <wirish_types.h>
+#include <stdbool.h>
 
 /* Set of all possible pin names; not all boards have all these (note
  * that we use the Dx convention since all of the Maple's pins are
@@ -55,9 +52,12 @@ enum {
     D32, D33, D34, D35, D36, D37, D38, D39, D40, D41, D42, D43, D44, D45, D46,
     D47, D48, D49, D50, D51, D52, D53, D54, D55, D56, D57, D58, D59, D60, D61,
     D62, D63, D64, D65, D66, D67, D68, D69, D70, D71, D72, D73, D74, D75, D76,
+#if 0 // not available on LQFP100 package
     D77, D78, D79, D80, D81, D82, D83, D84, D85, D86, D87, D88, D89, D90, D91,
     D92, D93, D94, D95, D96, D97, D98, D99, D100, D101, D102, D103, D104, D105,
-    D106, D107, D108, D109, D110, D111, };
+    D106, D107, D108, D109, D110, D111,
+#endif // not available on LQFP100 package
+};
 
 /**
  * @brief Maps each Maple pin to a corresponding stm32_pin_info.
@@ -115,31 +115,20 @@ extern void boardInit(void);
  * @return true if the given pin is in boardUsedPins, and false otherwise.
  * @see boardUsedPins
  */
-bool boardUsesPin(uint8 pin);
+extern bool boardUsesPin(uint8 pin);
 
 /* Include the appropriate private header from boards/: */
 
 /* FIXME HACK put boards/ before these paths once IDE uses make. */
 
-#ifdef BOARD_maple
-#include "maple.h"
-#elif defined(BOARD_maple_native)
-#include "maple_native.h"
-#elif defined(BOARD_maple_mini)
-#include "maple_mini.h"
-#elif defined(BOARD_maple_RET6)
-/*
- * **NOT** MAPLE REV6.  This the **Maple RET6 EDITION**, which is a
- * Maple with an STM32F103RET6 (...RET6) instead of an STM32F103RBT6
- * (...RBT6) on it.  Maple Rev6 (as of March 2011) DOES NOT EXIST.
- */
-#include "maple_RET6.h"
-#elif defined(BOARD_aeroquad32) || defined(BOARD_aeroquad32f1)
+#if defined(BOARD_aeroquad32) || defined(BOARD_aeroquad32f1)
 #include "aeroquad32.h"
 #elif defined(BOARD_aeroquad32mini)
 #include "aeroquad32mini.h"
 #elif defined(BOARD_discovery_f4)
 #include "discovery_f4.h"
+#elif defined(BOARD_generic_f407v)
+#include "generic_f407v.h"
 #elif defined(BOARD_freeflight)
 #include "freeflight.h"
 #else
@@ -160,4 +149,12 @@ bool boardUsesPin(uint8 pin);
 #define CLOCK_SPEED_MHZ                 CYCLES_PER_MICROSECOND
 #define CLOCK_SPEED_HZ                  (CLOCK_SPEED_MHZ * 1000000UL)
 
+#ifndef SYSTICK_RELOAD_VAL
+#define SYSTICK_RELOAD_VAL              (1000 * CYCLES_PER_MICROSECOND - 1)
+#endif
+
+#ifndef BOARD_BUTTON_PRESSED_LEVEL
+#define BOARD_BUTTON_PRESSED_LEVEL      HIGH
+#endif
+
 #endif
diff --git a/STM32F4/cores/maple/ext_interrupts.cpp b/STM32F4/cores/maple/ext_interrupts.cpp
index f014f1300..7111d0c86 100644
--- a/STM32F4/cores/maple/ext_interrupts.cpp
+++ b/STM32F4/cores/maple/ext_interrupts.cpp
@@ -31,8 +31,8 @@
  */
 
 #include "boards.h"
-#include "gpio.h"
-#include "exti.h"
+#include <libmaple/gpio.h>
+#include <libmaple/exti.h>
 #include "ext_interrupts.h"
 
 static inline exti_trigger_mode exti_out_mode(ExtIntTriggerMode mode);
@@ -51,7 +51,7 @@ void attachInterrupt(uint8 pin, voidFuncPtr handler, ExtIntTriggerMode mode) {
 
     exti_trigger_mode outMode = exti_out_mode(mode);
 
-    exti_attach_interrupt((afio_exti_num)(PIN_MAP[pin].gpio_bit),
+    exti_attach_interrupt((afio_exti_num)(pin&0x0F),
                           gpio_exti_port(PIN_MAP[pin].gpio_device),
                           handler,
                           outMode);
@@ -66,7 +66,7 @@ void detachInterrupt(uint8 pin) {
         return;
     }
 
-    exti_detach_interrupt((afio_exti_num)(PIN_MAP[pin].gpio_bit));
+    exti_detach_interrupt((afio_exti_num)(pin&0x0F));
 }
 
 static inline exti_trigger_mode exti_out_mode(ExtIntTriggerMode mode) {
diff --git a/STM32F4/cores/maple/ext_interrupts.h b/STM32F4/cores/maple/ext_interrupts.h
index b5c6f983b..fe215dceb 100644
--- a/STM32F4/cores/maple/ext_interrupts.h
+++ b/STM32F4/cores/maple/ext_interrupts.h
@@ -24,8 +24,8 @@
  * SOFTWARE.
  *****************************************************************************/
 
-#include "libmaple_types.h"
-#include "nvic.h"
+#ifndef _EXT_INTERRUPTS_H_
+#define _EXT_INTERRUPTS_H_
 
 /**
  *  @file ext_interrupts.h
@@ -33,8 +33,9 @@
  *  @brief Wiring-like external interrupt prototypes and types.
  */
 
-#ifndef _EXT_INTERRUPTS_H_
-#define _EXT_INTERRUPTS_H_
+#include <libmaple/libmaple_types.h>
+#include <libmaple/nvic.h>
+
 
 /**
  * The kind of transition on an external pin which should trigger an
diff --git a/STM32F4/cores/maple/io.h b/STM32F4/cores/maple/io.h
index df1ab969e..aeaf0fd3a 100644
--- a/STM32F4/cores/maple/io.h
+++ b/STM32F4/cores/maple/io.h
@@ -33,8 +33,9 @@
 #ifndef _IO_H_
 #define _IO_H_
 
-#include "gpio.h"
-#include "adc.h"
+#include <inttypes.h>
+#include <libmaple/gpio.h>
+#include <libmaple/adc.h>
 
 #include "wirish_time.h"
 
@@ -179,9 +180,11 @@ static inline void toggleLED() {
  * accomplished portably over all LeafLabs boards by calling
  * pinMode(BOARD_BUTTON_PIN, INPUT).
  *
+ * @param button - one of available on-board buttons (up to 3 for generic F4)
+ *
  * @see pinMode()
  */
-uint8 isButtonPressed();
+uint8 isButtonPressed(uint8_t button);
 
 /**
  * Wait until the button is pressed and released, timing out if no
@@ -195,12 +198,14 @@ uint8 isButtonPressed();
  * button is pressed.  If timeout_millis is left out (or 0), wait
  * forever.
  *
+ * @param button - one of available on-board buttons (up to 3 for generic F4)
+ *
  * @return true, if the button was pressed; false, if the timeout was
  * reached.
  *
  * @see pinMode()
  */
-uint8 waitForButtonPress(uint32 timeout_millis=0);
+uint8 waitForButtonPress(uint8_t button, uint32 timeout_millis=0);
 
 /**
  * Shift out a byte of data, one bit at a time.
diff --git a/STM32F4/cores/maple/itoa.h b/STM32F4/cores/maple/itoa.h
index 59af10947..09e8b2f8e 100644
--- a/STM32F4/cores/maple/itoa.h
+++ b/STM32F4/cores/maple/itoa.h
@@ -16,8 +16,8 @@
   Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 
-#ifndef _ITOA_
-#define _ITOA_
+#ifndef _ITOA_H_
+#define _ITOA_H_
 
 #ifdef __cplusplus
 extern "C"{
diff --git a/STM32F4/cores/maple/libmaple/HardwareSPI.cpp b/STM32F4/cores/maple/libmaple/HardwareSPI.cpp
deleted file mode 100644
index a5b4711be..000000000
--- a/STM32F4/cores/maple/libmaple/HardwareSPI.cpp
+++ /dev/null
@@ -1,424 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @author Marti Bolivar <mbolivar@leaflabs.com>
- * @brief Wirish SPI implementation.
- */
-
-#include "HardwareSPI.h"
-
-#include "timer.h"
-#include "util.h"
-#include "rcc.h"
-
-#include "wirish.h"
-#include "boards.h"
-
-struct spi_pins {
-    uint8 nss;
-    uint8 sck;
-    uint8 miso;
-    uint8 mosi;
-};
-
-static const spi_pins* dev_to_spi_pins(spi_dev *dev);
-
-static void enable_device(spi_dev *dev,
-                          bool as_master,
-                          SPIFrequency frequency,
-                          spi_cfg_flag endianness,
-                          spi_mode mode);
-
-static const spi_pins board_spi_pins[] __FLASH__ = {
-    {BOARD_SPI1_NSS_PIN,
-     BOARD_SPI1_SCK_PIN,
-     BOARD_SPI1_MISO_PIN,
-     BOARD_SPI1_MOSI_PIN},
-#ifdef BOARD_SPI2_NSS_PIN
-	{BOARD_SPI2_NSS_PIN,
-     BOARD_SPI2_SCK_PIN,
-     BOARD_SPI2_MISO_PIN,
-     BOARD_SPI2_MOSI_PIN},
-#endif
-#ifdef STM32_HIGH_DENSITY
-    {BOARD_SPI3B_NSS_PIN,
-     BOARD_SPI3B_SCK_PIN,
-     BOARD_SPI3B_MISO_PIN,
-     BOARD_SPI3B_MOSI_PIN},
-#endif
-#ifdef STM32F4
-    {BOARD_SPI3B_NSS_PIN,
-     BOARD_SPI3B_SCK_PIN,
-     BOARD_SPI3B_MISO_PIN,
-     BOARD_SPI3B_MOSI_PIN},
-#endif
-};
-
-
-/*
- * Constructor
- */
-
-HardwareSPI::HardwareSPI(uint32 spi_num) {
-    switch (spi_num) {
-    case 1:
-        this->spi_d = SPI1;
-        break;
-    case 2:
-        this->spi_d = SPI2;
-        break;
-#ifdef STM32_HIGH_DENSITY
-    case 3:
-        this->spi_d = SPI3;
-        break;
-#endif
-#ifdef STM32F4
-//    case 4:
-//        this->spi_d = SPI4;
-//        break;
-#endif
-    default:
-        ASSERT(0);
-    }
-}
-
-/*
- * Set up/tear down
- */
-
-void HardwareSPI::begin(SPIFrequency frequency, uint32 bitOrder, uint32 mode) {
-    if (mode >= 4) {
-        ASSERT(0);
-        return;
-    }
-    spi_cfg_flag end = bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB;
-    spi_mode m = (spi_mode)mode;
-    enable_device(this->spi_d, true, frequency, end, m);
-}
-
-void HardwareSPI::begin(void) {
-    this->begin(SPI_1_125MHZ, MSBFIRST, 0);
-}
-
-void HardwareSPI::beginSlave(uint32 bitOrder, uint32 mode) {
-    if (mode >= 4) {
-        ASSERT(0);
-        return;
-    }
-    spi_cfg_flag end = bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB;
-    spi_mode m = (spi_mode)mode;
-    enable_device(this->spi_d, false, (SPIFrequency)0, end, m);
-}
-
-void HardwareSPI::beginSlave(void) {
-    this->beginSlave(MSBFIRST, 0);
-}
-
-
-/*
-void HardwareSPI::beginTransaction(uint8_t pin, SPISettings settings)
-{
-//    this->begin(settings.clock, settings.bitOrder, settings.dataMode);
-    this->begin(SPI_1_125MHZ, settings.bitOrder, settings.dataMode);
-}
-*/
-
-void HardwareSPI::end(void) {
-    if (!spi_is_enabled(this->spi_d)) {
-        return;
-    }
-
-    // Follows RM0008's sequence for disabling a SPI in master/slave
-    // full duplex mode.
-    while (spi_is_rx_nonempty(this->spi_d)) {
-        // FIXME [0.1.0] remove this once you have an interrupt based driver
-        volatile uint16 rx __attribute__((unused)) = spi_rx_reg(this->spi_d);
-    }
-    while (!spi_is_tx_empty(this->spi_d))
-        ;
-    while (spi_is_busy(this->spi_d))
-        ;
-    spi_peripheral_disable(this->spi_d);
-}
-
-/*
- * I/O
- */
-
-uint8 HardwareSPI::read(void) {
-    uint8 buf[1];
-    this->read(buf, 1);
-    return buf[0];
-}
-
-void HardwareSPI::read(uint8 *buf, uint32 len) {
-    uint32 rxed = 0;
-    while (rxed < len) {
-        while (!spi_is_rx_nonempty(this->spi_d))
-            ;
-        buf[rxed++] = (uint8)spi_rx_reg(this->spi_d);
-    }
-}
-
-#if 0
-void HardwareSPI::readMaster(uint8 *buf, uint32 len) {
-    uint32 rxed = 0;
-    while (rxed < len) {
-		spi_tx_reg(this->spi_d, 0xff);
-        while (!spi_is_rx_nonempty(this->spi_d))
-            ;
-        buf[rxed++] = (uint8)spi_rx_reg(this->spi_d);
-		buf[rxed++] = this->spi_d->regs->DR;
-    }
-}
-#endif
-void HardwareSPI::readMaster(uint8 *buf, uint32 len) {
-	spi_reg_map *r = this->spi_d->regs;
-    uint32 rxed = 0;
-    while (rxed < len) {
-		r->DR = 0xff;
-        while (!(r->SR & SPI_SR_RXNE))
-            ;
-		buf[rxed++] = r->DR;
-    }
-}
-
-
-void HardwareSPI::waitReady() {
-	while (!spi_is_rx_nonempty(this->spi_d))
-		;
-}
-
-void HardwareSPI::write(uint8 byte) {
-    this->write(&byte, 1);
-}
-
-void HardwareSPI::write(const uint8 *data, uint32 length) {
-    uint32 txed = 0;
-    while (txed < length) {
-        txed += spi_tx(this->spi_d, data + txed, length - txed);
-    }
-}
-
-uint8 HardwareSPI::transfer(uint8 byte) {
-    this->write(byte);
-    return this->read();
-}
-
-/*
- * Pin accessors
- */
-
-uint8 HardwareSPI::misoPin(void) {
-    return dev_to_spi_pins(this->spi_d)->miso;
-}
-
-uint8 HardwareSPI::mosiPin(void) {
-    return dev_to_spi_pins(this->spi_d)->mosi;
-}
-
-uint8 HardwareSPI::sckPin(void) {
-    return dev_to_spi_pins(this->spi_d)->sck;
-}
-
-uint8 HardwareSPI::nssPin(void) {
-    return dev_to_spi_pins(this->spi_d)->nss;
-}
-
-/*
- * Deprecated functions
- */
-
-uint8 HardwareSPI::send(uint8 data) {
-    uint8 buf[] = {data};
-    return this->send(buf, 1);
-}
-
-#if 1	
-uint8 HardwareSPI::send(const uint8 *buf, uint32 len) {
-    uint32 txed = 0;
-    uint8 ret = 0;
-    while (txed < len) {
-        this->write(buf[txed++]);
-        ret = this->read();
-    }
-    return ret;
-}
-#else
-// this does not work for an unknown reason
-uint8 HardwareSPI::send(const uint8 *buf, uint32 len) {
-	volatile uint32 *dr = &(this->spi_d->regs->DR);
-	volatile uint32 *sr = &(this->spi_d->regs->SR);
-    uint32 txed = 0;
-	uint32 rx=0;
-    while (txed < len) {
-        //while (!(*sr & SPI_SR_TXE))
-        //    ;
-		//*dr = buf[txed++];
-		this->write(buf[txed++]);
-
-        while (!(*sr & SPI_SR_RXNE))
-			;
-		rx = *dr;
-		//rx = this->read();
-    }
-
-	return rx;
-}
-#endif
-
-uint8 HardwareSPI::recv(void) {
-    return this->read();
-}
-
-/*
- * Auxiliary functions
- */
-
-static void configure_gpios(spi_dev *dev, bool as_master);
-static spi_baud_rate determine_baud_rate(spi_dev *dev, SPIFrequency freq);
-
-static const spi_pins* dev_to_spi_pins(spi_dev *dev) {
-    switch (dev->clk_id) {
-    case RCC_SPI1: return board_spi_pins;
-    case RCC_SPI2: return board_spi_pins + 1;
-#ifdef STM32_HIGH_DENSITY
-    case RCC_SPI3: return board_spi_pins + 2;
-#endif
-#ifdef STM32F4
-    case RCC_SPI4: return board_spi_pins + 3;
-#endif
-    default:       return NULL;
-    }
-}
-
-/* Enables the device in master or slave full duplex mode.  If you
- * change this code, you must ensure that appropriate changes are made
- * to HardwareSPI::end(). */
-static void enable_device(spi_dev *dev,
-                          bool as_master,
-                          SPIFrequency freq,
-                          spi_cfg_flag endianness,
-                          spi_mode mode) {
-    spi_baud_rate baud = determine_baud_rate(dev, freq);
-    uint32 cfg_flags = (endianness | SPI_DFF_8_BIT | SPI_SW_SLAVE |
-                        (as_master ? SPI_SOFT_SS : 0));
-
-    spi_init(dev);
-    configure_gpios(dev, as_master);
-    if (as_master) {
-        spi_master_enable(dev, baud, mode, cfg_flags);
-    } else {
-        spi_slave_enable(dev, mode, cfg_flags);
-    }
-}
-
-static void disable_pwm(const stm32_pin_info *i) {
-    if (i->timer_device) {
-        timer_set_mode(i->timer_device, i->timer_channel, TIMER_DISABLED);
-    }
-}
-
-static void configure_gpios(spi_dev *dev, bool as_master) {
-    const spi_pins *pins = dev_to_spi_pins(dev);
-
-    if (!pins) {
-        return;
-    }
-
-	const stm32_pin_info *nssi = (pins->nss >= 0) ? &PIN_MAP[pins->nss] : NULL;
-    const stm32_pin_info *scki = &PIN_MAP[pins->sck];
-    const stm32_pin_info *misoi = &PIN_MAP[pins->miso];
-    const stm32_pin_info *mosii = &PIN_MAP[pins->mosi];
-
-	if(nssi) {
-		disable_pwm(nssi);
-	}
-    disable_pwm(scki);
-    disable_pwm(misoi);
-    disable_pwm(mosii);
-
-#ifdef STM32F4
-	if(dev->clk_id <= RCC_SPI2) {
-		if(nssi) {
-			if(!as_master) {
-				gpio_set_af_mode(nssi->gpio_device,  scki->gpio_bit, 5);
-			}
-		}
-		gpio_set_af_mode(scki->gpio_device,  scki->gpio_bit, 5);
-		gpio_set_af_mode(misoi->gpio_device, misoi->gpio_bit, 5);
-		gpio_set_af_mode(mosii->gpio_device, mosii->gpio_bit, 5);
-	} else {
-		if(nssi) {
-			if(!as_master) {
-				gpio_set_af_mode(nssi->gpio_device,  scki->gpio_bit, 6);
-			}
-		}
-		gpio_set_af_mode(scki->gpio_device,  scki->gpio_bit, 6);
-		gpio_set_af_mode(misoi->gpio_device, misoi->gpio_bit, 6);
-		gpio_set_af_mode(mosii->gpio_device, mosii->gpio_bit, 6);
-	}
-#endif
-
-		if(nssi) {
-                    spi_config_gpios(dev, as_master, nssi->gpio_device, nssi->gpio_bit,
-                                                     scki->gpio_device, scki->gpio_bit, 
-                                                     misoi->gpio_device, misoi->gpio_bit,
-                                                     mosii->gpio_device, mosii->gpio_bit);
-		} else {
-                    spi_config_gpios(dev, as_master, NULL, -1,
-                                                     scki->gpio_device, scki->gpio_bit, 
-                                                     misoi->gpio_device, misoi->gpio_bit,
-                                                     mosii->gpio_device, mosii->gpio_bit);
-		}
-}
-
-static const spi_baud_rate baud_rates[MAX_SPI_FREQS] __FLASH__ = {
-    SPI_BAUD_PCLK_DIV_2,
-    SPI_BAUD_PCLK_DIV_4,
-    SPI_BAUD_PCLK_DIV_8,
-    SPI_BAUD_PCLK_DIV_16,
-    SPI_BAUD_PCLK_DIV_32,
-    SPI_BAUD_PCLK_DIV_64,
-    SPI_BAUD_PCLK_DIV_128,
-    SPI_BAUD_PCLK_DIV_256,
-};
-
-/*
- * Note: This assumes you're on a LeafLabs-style board
- * (CYCLES_PER_MICROSECOND == 72, APB2 at 72MHz, APB1 at 36MHz).
- */
-static spi_baud_rate determine_baud_rate(spi_dev *dev, SPIFrequency freq) {
-    if (rcc_dev_clk(dev->clk_id) == RCC_APB2 && freq == SPI_140_625KHZ) {
-        /* APB2 peripherals are too fast for 140.625 KHz */
-        ASSERT(0);
-        return (spi_baud_rate)~0;
-    }
-    return (rcc_dev_clk(dev->clk_id) == RCC_APB2 ?
-            baud_rates[freq + 1] :
-            baud_rates[freq]);
-}
diff --git a/STM32F4/cores/maple/libmaple/HardwareSPI.h b/STM32F4/cores/maple/libmaple/HardwareSPI.h
deleted file mode 100644
index 327f29da1..000000000
--- a/STM32F4/cores/maple/libmaple/HardwareSPI.h
+++ /dev/null
@@ -1,279 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file HardwareSPI.h
- * @brief High-level SPI interface
- *
- * This is a "bare essentials" polling driver for now.
- */
-
-/* TODO [0.1.0] Remove deprecated methods. */
-
-#include "libmaple_types.h"
-#include "spi.h"
-
-#include "boards.h"
-#include "wirish.h"
-
-#ifndef _HARDWARESPI_H_
-#define _HARDWARESPI_H_
-
-/**
- * @brief Defines the possible SPI communication speeds.
- */
-typedef enum SPIFrequency {
-    SPI_18MHZ       = 0, /**< 18 MHz */
-    SPI_9MHZ        = 1, /**< 9 MHz */
-    SPI_4_5MHZ      = 2, /**< 4.5 MHz */
-    SPI_2_25MHZ     = 3, /**< 2.25 MHz */
-    SPI_1_125MHZ    = 4, /**< 1.125 MHz */
-    SPI_562_500KHZ  = 5, /**< 562.500 KHz */
-    SPI_281_250KHZ  = 6, /**< 281.250 KHz */
-    SPI_140_625KHZ  = 7, /**< 140.625 KHz */
-} SPIFrequency;
-
-#define MAX_SPI_FREQS 8
-
-#if CYCLES_PER_MICROSECOND != 72
-/* TODO [0.2.0?] something smarter than this */
-//#warning "Unexpected clock speed; SPI frequency calculation will be incorrect"
-#endif
-
-
-//#define BOARD_SPI_DEFAULT_SS PC13
-#define BOARD_SPI_DEFAULT_SS PB0
-#define SPI_MODE0 SPI_MODE_0
-#define SPI_MODE1 SPI_MODE_1
-#define SPI_MODE2 SPI_MODE_2
-#define SPI_MODE3 SPI_MODE_3
-
-/*
-class SPISettings {
-public:
-	SPISettings(uint32 clock, BitOrder bitOrder, uint8 dataMode) {
-		if (__builtin_constant_p(clock)) {
-			init_AlwaysInline(clock, bitOrder, dataMode);
-		} else {
-			init_MightInline(clock, bitOrder, dataMode);
-		}
-	}
-	SPISettings() { init_AlwaysInline(4000000, MSBFIRST, SPI_MODE0); }
-private:
-	void init_MightInline(uint32 clock, BitOrder bitOrder, uint8 dataMode) {
-		init_AlwaysInline(clock, bitOrder, dataMode);
-	}
-	void init_AlwaysInline(uint32 clock, BitOrder bitOrder, uint8 dataMode) __attribute__((__always_inline__)) {
-		this->clock = clock;
-		this->bitOrder = bitOrder;
-		this->dataMode = dataMode;
-	}
-	uint32 clock;
-	BitOrder bitOrder;
-	uint8 dataMode;
-	friend class HardwareSPI;
-};
-*/
-
-
-/**
- * @brief Wirish SPI interface.
- *
- * This implementation uses software slave management, so the caller
- * is responsible for controlling the slave select line.
- */
-class HardwareSPI {
-public:
-    /**
-     * @param spiPortNumber Number of the SPI port to manage.
-     */
-    HardwareSPI(uint32 spiPortNumber);
-
-    /*
-     * Set up/tear down
-     */
-
-    /**
-     * @brief Turn on a SPI port and set its GPIO pin modes for use as master.
-     *
-     * SPI port is enabled in full duplex mode, with software slave management.
-     *
-     * @param frequency Communication frequency
-     * @param bitOrder Either LSBFIRST (little-endian) or MSBFIRST (big-endian)
-     * @param mode SPI mode to use, one of SPI_MODE_0, SPI_MODE_1,
-     *             SPI_MODE_2, and SPI_MODE_3.
-     */
-    void begin(SPIFrequency frequency, uint32 bitOrder, uint32 mode);
-
-    /**
-     * @brief Equivalent to begin(SPI_1_125MHZ, MSBFIRST, 0).
-     */
-    void begin(void);
-
-    /**
-     * @brief Turn on a SPI port and set its GPIO pin modes for use as a slave.
-     *
-     * SPI port is enabled in full duplex mode, with software slave management.
-     *
-     * @param bitOrder Either LSBFIRST (little-endian) or MSBFIRST(big-endian)
-     * @param mode SPI mode to use
-     */
-    void beginSlave(uint32 bitOrder, uint32 mode);
-
-    /**
-     * @brief Equivalent to beginSlave(MSBFIRST, 0).
-     */
-    void beginSlave(void);
-
-    /**
-     * @brief Disables the SPI port, but leaves its GPIO pin modes unchanged.
-     */
-    void end(void);
-
-    /*
-     * I/O
-     */
-
-    /**
-     * @brief Return the next unread byte.
-     *
-     * If there is no unread byte waiting, this function will block
-     * until one is received.
-     */
-    uint8 read(void);
-
-    /**
-     * @brief Read length bytes, storing them into buffer.
-     * @param buffer Buffer to store received bytes into.
-     * @param length Number of bytes to store in buffer.  This
-     *               function will block until the desired number of
-     *               bytes have been read.
-     */
-    void read(uint8 *buffer, uint32 length);
-
-	/**
-     * @brief Read length bytes, storing them into buffer.
-     * @param buffer Buffer to store received bytes into.
-     * @param length Number of bytes to store in buffer.  This
-     *               function will block until the desired number of
-     *               bytes have been read.
-     */
-    void readMaster(uint8 *buffer, uint32 length);
-
-
-	void waitReady();
-    /**
-     * @brief Transmit a byte.
-     * @param data Byte to transmit.
-     */
-    void write(uint8 data);
-
-    /**
-     * @brief Transmit multiple bytes.
-     * @param buffer Bytes to transmit.
-     * @param length Number of bytes in buffer to transmit.
-     */
-    void write(const uint8 *buffer, uint32 length);
-
-    /**
-     * @brief Transmit a byte, then return the next unread byte.
-     *
-     * This function transmits before receiving.
-     *
-     * @param data Byte to transmit.
-     * @return Next unread byte.
-     */
-    uint8 transfer(uint8 data);
-
-    /*
-     * Pin accessors
-     */
-
-    /**
-     * @brief Return the number of the MISO (master in, slave out) pin
-     */
-    uint8 misoPin(void);
-
-    /**
-     * @brief Return the number of the MOSI (master out, slave in) pin
-     */
-    uint8 mosiPin(void);
-
-    /**
-     * @brief Return the number of the SCK (serial clock) pin
-     */
-    uint8 sckPin(void);
-
-    /**
-     * @brief Return the number of the NSS (slave select) pin
-     */
-    uint8 nssPin(void);
-
-    /* -- The following methods are deprecated --------------------------- */
-
-    /**
-     * @brief Deprecated.
-     *
-     * Use HardwareSPI::transfer() instead.
-     *
-     * @see HardwareSPI::transfer()
-     */
-    uint8 send(uint8 data);
-
-    /**
-     * @brief Deprecated.
-     *
-     * Use HardwareSPI::write() in combination with
-     * HardwareSPI::read() (or HardwareSPI::transfer()) instead.
-     *
-     * @see HardwareSPI::write()
-     * @see HardwareSPI::read()
-     * @see HardwareSPI::transfer()
-     */
-    uint8 send(const uint8 *data, uint32 length);
-
-    /**
-     * @brief Deprecated.
-     *
-     * Use HardwareSPI::read() instead.
-     *
-     * @see HardwareSPI::read()
-     */
-    uint8 recv(void);
-    
-//    void beginTransaction(SPISettings settings) { beginTransaction(BOARD_SPI_DEFAULT_SS, settings); }
-//    void beginTransaction(uint8 pin, SPISettings settings);
-    void endTransaction(void) { }
-                            
-private:
-    spi_dev *spi_d;
-};
-
-
-extern HardwareSPI SPI;
-
-#endif
-
diff --git a/STM32F4/cores/maple/libmaple/HardwareSerial.cpp b/STM32F4/cores/maple/libmaple/HardwareSerial.cpp
index 59ce71d11..f9387d15a 100644
--- a/STM32F4/cores/maple/libmaple/HardwareSerial.cpp
+++ b/STM32F4/cores/maple/libmaple/HardwareSerial.cpp
@@ -56,19 +56,19 @@
 #define RX5 BOARD_UART5_RX_PIN
 #endif
 
-HardwareSerial Serial(USART1, TX1, RX1);
+HardwareSerial Serial1(USART1, TX1, RX1);
 
 #ifdef TX2
-HardwareSerial Serial1(USART2, TX2, RX2);
+HardwareSerial Serial2(USART2, TX2, RX2);
 #endif
 
 #ifdef TX3
-HardwareSerial Serial2(USART3, TX3, RX3);
+HardwareSerial Serial3(USART3, TX3, RX3);
 #endif
 
 #if defined(STM32_HIGH_DENSITY) && !defined(BOARD_maple_RET6)
-HardwareSerial Serial3(UART4,  TX4, RX4);
-HardwareSerial Serial4(UART5,  TX5, RX5);
+HardwareSerial Serial4(UART4,  TX4, RX4);
+HardwareSerial Serial5(UART5,  TX5, RX5);
 #endif
 
 HardwareSerial::HardwareSerial(usart_dev *usart_device,
@@ -90,25 +90,23 @@ void HardwareSerial::begin(uint32 baud) {
         return;
     }
 
-    const stm32_pin_info *txi = &PIN_MAP[tx_pin];
-    const stm32_pin_info *rxi = &PIN_MAP[rx_pin];
-#ifdef STM32F2
+#ifdef STM32F4
 	// int af = 7<<8;
     if (usart_device == UART4 || usart_device == UART5) {
-        gpio_set_af_mode(txi->gpio_device, txi->gpio_bit, 8);
-        gpio_set_af_mode(rxi->gpio_device, rxi->gpio_bit, 8);
+        gpio_set_af_mode(tx_pin, 8);
+        gpio_set_af_mode(rx_pin, 8);
     }
     else {
-        gpio_set_af_mode(txi->gpio_device, txi->gpio_bit, 7);
-        gpio_set_af_mode(rxi->gpio_device, rxi->gpio_bit, 7);
+        gpio_set_af_mode(tx_pin, 7);
+        gpio_set_af_mode(rx_pin, 7);
     }
-    gpio_set_mode(txi->gpio_device, txi->gpio_bit, (gpio_pin_mode)(GPIO_AF_OUTPUT_PP | GPIO_PUPD_INPUT_PU | 0x700));
-    gpio_set_mode(rxi->gpio_device, rxi->gpio_bit, (gpio_pin_mode)(GPIO_MODE_AF      | GPIO_PUPD_INPUT_PU | 0x700));
+    gpio_set_mode(tx_pin, (gpio_pin_mode)(GPIO_AF_OUTPUT_PP | GPIO_PUPD_INPUT_PU | 0x700));
+    gpio_set_mode(rx_pin, (gpio_pin_mode)(GPIO_MODE_AF      | GPIO_PUPD_INPUT_PU | 0x700));
     //gpio_set_mode(txi->gpio_device, txi->gpio_bit, (gpio_pin_mode)(GPIO_PUPD_INPUT_PU));
     //gpio_set_mode(rxi->gpio_device, rxi->gpio_bit, (gpio_pin_mode)(GPIO_PUPD_INPUT_PU));
 #else
-	gpio_set_mode(txi->gpio_device, txi->gpio_bit, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(rxi->gpio_device, rxi->gpio_bit, GPIO_INPUT_FLOATING);
+	gpio_set_mode(tx_pin, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(rx_pin, GPIO_INPUT_FLOATING);
 #endif
 #if 0
     if (txi->timer_device != NULL) {
diff --git a/STM32F4/cores/maple/libmaple/HardwareSerial.h b/STM32F4/cores/maple/libmaple/HardwareSerial.h
index c09fe54f1..d7e8a3d1f 100644
--- a/STM32F4/cores/maple/libmaple/HardwareSerial.h
+++ b/STM32F4/cores/maple/libmaple/HardwareSerial.h
@@ -75,12 +75,12 @@ class HardwareSerial : public Stream {
     uint8 rx_pin;
 };
 
-extern HardwareSerial Serial;
 extern HardwareSerial Serial1;
 extern HardwareSerial Serial2;
 #if defined(STM32_HIGH_DENSITY) && !defined(BOARD_maple_RET6)
 extern HardwareSerial Serial3;
 extern HardwareSerial Serial4;
+extern HardwareSerial Serial5;
 #endif
 extern HardwareSerial &SerialDebug;
 #endif
diff --git a/STM32F4/cores/maple/libmaple/adc.c b/STM32F4/cores/maple/libmaple/adc.c
index aeeb43c0e..0f4c02c3c 100644
--- a/STM32F4/cores/maple/libmaple/adc.c
+++ b/STM32F4/cores/maple/libmaple/adc.c
@@ -41,27 +41,24 @@
 #include "rcc.h"
 #include "adc.h"
 
-static adc_dev adc1 = {
+/** ADC1 device. */
+const adc_dev ADC1 = {
     .regs   = ADC1_BASE,
     .clk_id = RCC_ADC1
 };
-/** ADC1 device. */
-const adc_dev *ADC1 = &adc1;
 
-static adc_dev adc2 = {
+/** ADC2 device. */
+const adc_dev ADC2 = {
     .regs   = ADC2_BASE,
     .clk_id = RCC_ADC2
 };
-/** ADC2 device. */
-const adc_dev *ADC2 = &adc2;
 
 #ifdef STM32_HIGH_DENSITY
-adc_dev adc3 = {
+/** ADC3 device. */
+const adc_dev ADC3 = {
     .regs   = ADC3_BASE,
     .clk_id = RCC_ADC3
 };
-/** ADC3 device. */
-const adc_dev *ADC3 = &adc3;
 #endif
 
 /**
@@ -74,7 +71,7 @@ const adc_dev *ADC3 = &adc3;
  */
 void adc_init(const adc_dev *dev) {
     rcc_clk_enable(dev->clk_id);
-#ifdef STM32F2
+#ifdef STM32F4
     if(dev->clk_id == RCC_ADC1) {
     	rcc_reset_dev(dev->clk_id);
     }
@@ -101,10 +98,10 @@ void adc_set_extsel(const adc_dev *dev, adc_extsel_event event) {
  * @param fn Function to call on each ADC device.
  */
 void adc_foreach(void (*fn)(const adc_dev*)) {
-    fn(ADC1);
-    fn(ADC2);
+    fn(&ADC1);
+    fn(&ADC2);
 #ifdef STM32_HIGH_DENSITY
-    fn(ADC3);
+    fn(&ADC3);
 #endif
 }
 
@@ -136,7 +133,9 @@ void adc_set_sample_rate(const adc_dev *dev, adc_smp_rate smp_rate) {
  * @brief Calibrate an ADC peripheral
  * @param dev adc device
  */
-void adc_calibrate(const adc_dev *dev) {
+void adc_calibrate(const adc_dev *dev)
+{
+/*
 #ifndef STM32F2
     __io uint32 *rstcal_bit = bb_perip(&(dev->regs->CR2), 3);
     __io uint32 *cal_bit = bb_perip(&(dev->regs->CR2), 2);
@@ -149,6 +148,7 @@ void adc_calibrate(const adc_dev *dev) {
     while (*cal_bit)
         ;
 #endif
+*/
 }
 
 /**
@@ -171,8 +171,8 @@ uint16 adc_read(const adc_dev *dev, uint8 channel) {
     return (uint16)(regs->DR & ADC_DR_DATA);
 }
 
-void setupADC_F2() {
-#ifdef STM32F2
+void setupADC_F4(void)
+{
 		  uint32 tmpreg1 = 0;
 
 		  tmpreg1 = ADC_COMMON->CCR;
@@ -196,5 +196,4 @@ void setupADC_F2() {
 
 		  /* Write to ADC CCR */
 		  ADC_COMMON->CCR = tmpreg1;
-#endif
 }
diff --git a/STM32F4/cores/maple/libmaple/adc.h b/STM32F4/cores/maple/libmaple/adc.h
index 3a40d4c58..6fa61f5ea 100644
--- a/STM32F4/cores/maple/libmaple/adc.h
+++ b/STM32F4/cores/maple/libmaple/adc.h
@@ -42,17 +42,15 @@ extern "C"{
 #endif
 
 
-#ifdef STM32F2
-  typedef struct
-  {
-    __io uint32 CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-    __io uint32 CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-    __io uint32 CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-  } ADC_Common_TypeDef;
+typedef struct
+{
+	__io uint32 CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
+	__io uint32 CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
+	__io uint32 CDR;    /*!< ADC common regular data register for dual
+							 AND triple modes,                            Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
 #define ADC_COMMON  ((ADC_Common_TypeDef *) 0x40012300)
 
-#endif
 
 /** ADC register map type. */
 typedef struct adc_reg_map {
@@ -84,33 +82,22 @@ typedef struct adc_dev {
     rcc_clk_id clk_id; /**< RCC clock information */
 } adc_dev;
 
-extern const adc_dev *ADC1;
-extern const adc_dev *ADC2;
+extern const adc_dev ADC1;
+extern const adc_dev ADC2;
 #ifdef STM32_HIGH_DENSITY
-extern const adc_dev *ADC3;
+extern const adc_dev ADC3;
 #endif
 
 /*
  * Register map base pointers
  */
 
-#ifdef STM32F2
-	/** ADC1 register map base pointer. */
-	#define ADC1_BASE                       ((struct adc_reg_map*)0x40012000)
-	/** ADC2 register map base pointer. */
-	#define ADC2_BASE                       ((struct adc_reg_map*)0x40012100)
-  /** ADC3 register map base pointer. */
-  #define ADC3_BASE                       ((struct adc_reg_map*)0x40012200)
-#else
-	/** ADC1 register map base pointer. */
-	#define ADC1_BASE                       ((struct adc_reg_map*)0x40012400)
-	/** ADC2 register map base pointer. */
-	#define ADC2_BASE                       ((struct adc_reg_map*)0x40012800)
-	#ifdef STM32_HIGH_DENSITY
-  	/** ADC3 register map base pointer. */
-	  #define ADC3_BASE                       ((struct adc_reg_map*)0x40013C00)
-  #endif
-#endif
+/** ADC1 register map base pointer. */
+#define ADC1_BASE                       ((struct adc_reg_map*)0x40012000)
+/** ADC2 register map base pointer. */
+#define ADC2_BASE                       ((struct adc_reg_map*)0x40012100)
+/** ADC3 register map base pointer. */
+#define ADC3_BASE                       ((struct adc_reg_map*)0x40012200)
 
 /*
  * Register bit definitions
@@ -167,17 +154,10 @@ extern const adc_dev *ADC3;
 #define ADC_CR2_JEXTTRIG_BIT            15
 #define ADC_CR2_EXTTRIG_BIT             20
 #define ADC_CR2_TSEREFE_BIT             23
-#ifdef STM32F2
 #define ADC_CR2_JSWSTART_BIT            22
 #define ADC_CR2_SWSTART_BIT             30
 #define ADC_CR2_EXTSEL                  (0x0F000000)
 #define ADC_CR2_JEXTSEL                 (0x000F0000)
-#else
-#define ADC_CR2_JSWSTART_BIT            21
-#define ADC_CR2_SWSTART_BIT             22
-#define ADC_CR2_EXTSEL                  (0x000E0000)
-#define ADC_CR2_JEXTSEL                 (0x00007000)
-#endif
 
 
 
@@ -388,7 +368,7 @@ static inline void adc_disable_all(void) {
     adc_foreach(adc_disable);
 }
 
-void setupADC_F2();
+extern void setupADC_F4(void);
 
 #ifdef __cplusplus
 } // extern "C"
diff --git a/STM32F4/cores/maple/libmaple/dac.c b/STM32F4/cores/maple/libmaple/dac.c
index 264e4e21a..3853f903c 100644
--- a/STM32F4/cores/maple/libmaple/dac.c
+++ b/STM32F4/cores/maple/libmaple/dac.c
@@ -126,11 +126,11 @@ void dac_enable_channel(const dac_dev *dev, uint8 channel) {
      */
     switch (channel) {
     case 1:
-        gpio_set_mode(GPIOA, 4, GPIO_INPUT_ANALOG);
+        gpio_set_mode((uint8_t)PA4, GPIO_INPUT_ANALOG);
         dev->regs->CR |= DAC_CR_EN1;
         break;
     case 2:
-        gpio_set_mode(GPIOA, 5, GPIO_INPUT_ANALOG);
+        gpio_set_mode((uint8_t)PA5, GPIO_INPUT_ANALOG);
         dev->regs->CR |= DAC_CR_EN2;
         break;
     }
diff --git a/STM32F4/cores/maple/libmaple/dma.h b/STM32F4/cores/maple/libmaple/dma.h
index a965c036f..420adf8a4 100644
--- a/STM32F4/cores/maple/libmaple/dma.h
+++ b/STM32F4/cores/maple/libmaple/dma.h
@@ -30,9 +30,4 @@
  *  @brief Direct Memory Access peripheral support
  */
 
-#ifdef STM32F2
-#include "dmaF2.h"
-#include <libmaple/dma_common.h>
-#else
-#include "dmaF1.h"
-#endif
+#include "dmaF4.h"
diff --git a/STM32F4/cores/maple/libmaple/dmaF1.c b/STM32F4/cores/maple/libmaple/dmaF1.c
deleted file mode 100644
index f8ddb2d22..000000000
--- a/STM32F4/cores/maple/libmaple/dmaF1.c
+++ /dev/null
@@ -1,383 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Michael Hope.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-#ifdef STM32F1
-
-/**
- * @file dma.c
- * @author Marti Bolivar <mbolivar@leaflabs.com>;
- *         Original implementation by Michael Hope
- * @brief Direct Memory Access peripheral support
- */
-
-#include "dma.h"
-#include "bitband.h"
-#include "util.h"
-
-/*
- * Devices
- */
-
-static dma_dev dma1 = {
-    .regs     = DMA1_BASE,
-    .clk_id   = RCC_DMA1,
-    .handlers = {{ .handler = NULL, .irq_line = NVIC_DMA_CH1 },
-                 { .handler = NULL, .irq_line = NVIC_DMA_CH2 },
-                 { .handler = NULL, .irq_line = NVIC_DMA_CH3 },
-                 { .handler = NULL, .irq_line = NVIC_DMA_CH4 },
-                 { .handler = NULL, .irq_line = NVIC_DMA_CH5 },
-                 { .handler = NULL, .irq_line = NVIC_DMA_CH6 },
-                 { .handler = NULL, .irq_line = NVIC_DMA_CH7 }}
-};
-/** DMA1 device */
-dma_dev *DMA1 = &dma1;
-
-#ifdef STM32_HIGH_DENSITY
-static dma_dev dma2 = {
-    .regs     = DMA2_BASE,
-    .clk_id   = RCC_DMA2,
-    .handlers = {{ .handler = NULL, .irq_line = NVIC_DMA2_CH1   },
-                 { .handler = NULL, .irq_line = NVIC_DMA2_CH2   },
-                 { .handler = NULL, .irq_line = NVIC_DMA2_CH3   },
-                 { .handler = NULL, .irq_line = NVIC_DMA2_CH_4_5 },
-                 { .handler = NULL, .irq_line = NVIC_DMA2_CH_4_5 }} /* !@#$ */
-};
-/** DMA2 device */
-dma_dev *DMA2 = &dma2;
-#endif
-
-/*
- * Convenience routines
- */
-
-/**
- * @brief Initialize a DMA device.
- * @param dev Device to initialize.
- */
-void dma_init(dma_dev *dev) {
-    rcc_clk_enable(dev->clk_id);
-}
-
-/**
- * @brief Set up a DMA transfer.
- *
- * The channel will be disabled before being reconfigured.  The
- * transfer will have low priority by default.  You may choose another
- * priority before the transfer begins using dma_set_priority(), as
- * well as performing any other configuration you desire.  When the
- * channel is configured to your liking, enable it using dma_enable().
- *
- * @param dev DMA device.
- * @param channel DMA channel.
- * @param peripheral_address Base address of peripheral data register
- *                           involved in the transfer.
- * @param peripheral_size Peripheral data transfer size.
- * @param memory_address Base memory address involved in the transfer.
- * @param memory_size Memory data transfer size.
- * @param mode Logical OR of dma_mode_flags
- * @sideeffect Disables the given DMA channel.
- * @see dma_xfer_size
- * @see dma_mode_flags
- * @see dma_set_num_transfers()
- * @see dma_set_priority()
- * @see dma_attach_interrupt()
- * @see dma_enable()
- */
-void dma_setup_transfer(dma_dev       *dev,
-                        dma_channel    channel,
-                        __io void     *peripheral_address,
-                        dma_xfer_size  peripheral_size,
-                        __io void     *memory_address,
-                        dma_xfer_size  memory_size,
-                        uint32         mode) {
-    dma_channel_reg_map *channel_regs = dma_channel_regs(dev, channel);
-
-    dma_disable(dev, channel);  /* can't write to CMAR/CPAR otherwise */
-    channel_regs->CCR = (memory_size << 10) | (peripheral_size << 8) | mode;
-    channel_regs->CMAR = (uint32)memory_address;
-    channel_regs->CPAR = (uint32)peripheral_address;
-}
-
-/**
- * @brief Set the number of data to be transferred on a DMA channel.
- *
- * You may not call this function while the channel is enabled.
- *
- * @param dev DMA device
- * @param channel Channel through which the transfer occurs.
- * @param num_transfers
- */
-void dma_set_num_transfers(dma_dev *dev,
-                           dma_channel channel,
-                           uint16 num_transfers) {
-    dma_channel_reg_map *channel_regs;
-
-    ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
-
-    channel_regs = dma_channel_regs(dev, channel);
-    channel_regs->CNDTR = num_transfers;
-}
-
-/**
- * @brief Set the priority of a DMA transfer.
- *
- * You may not call this function while the channel is enabled.
- *
- * @param dev DMA device
- * @param channel DMA channel
- * @param priority priority to set.
- */
-void dma_set_priority(dma_dev *dev,
-                      dma_channel channel,
-                      dma_priority priority) {
-    dma_channel_reg_map *channel_regs;
-    uint32 ccr;
-
-    ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
-
-    channel_regs = dma_channel_regs(dev, channel);
-    ccr = channel_regs->CCR;
-    ccr &= ~DMA_CCR_PL;
-    ccr |= priority;
-    channel_regs->CCR = ccr;
-}
-
-/**
- * @brief Attach an interrupt to a DMA transfer.
- *
- * Interrupts are enabled using appropriate mode flags in
- * dma_setup_transfer().
- *
- * @param dev DMA device
- * @param channel Channel to attach handler to
- * @param handler Interrupt handler to call when channel interrupt fires.
- * @see dma_setup_transfer()
- * @see dma_get_irq_cause()
- * @see dma_detach_interrupt()
- */
-void dma_attach_interrupt(dma_dev *dev,
-                          dma_channel channel,
-                          void (*handler)(void)) {
-    dev->handlers[channel - 1].handler = handler;
-    nvic_irq_enable(dev->handlers[channel - 1].irq_line);
-}
-
-/**
- * @brief Detach a DMA transfer interrupt handler.
- *
- * After calling this function, the given channel's interrupts will be
- * disabled.
- *
- * @param dev DMA device
- * @param channel Channel whose handler to detach
- * @sideeffect Clears interrupt enable bits in the channel's CCR register.
- * @see dma_attach_interrupt()
- */
-void dma_detach_interrupt(dma_dev *dev, dma_channel channel) {
-    /* Don't use nvic_irq_disable()! Think about DMA2 channels 4 and 5. */
-    dma_channel_regs(dev, channel)->CCR &= ~0xF;
-    dev->handlers[channel - 1].handler = NULL;
-}
-
-/**
- * @brief Discover the reason why a DMA interrupt was called.
- *
- * You may only call this function within an attached interrupt
- * handler for the given channel.
- *
- * This function resets the internal DMA register state which encodes
- * the cause of the interrupt; consequently, it can only be called
- * once per interrupt handler invocation.
- *
- * @param dev DMA device
- * @param channel Channel whose interrupt is being handled.
- * @return Reason why the interrupt fired.
- * @sideeffect Clears channel status flags in dev->regs->ISR.
- * @see dma_attach_interrupt()
- * @see dma_irq_cause
- */
-dma_irq_cause dma_get_irq_cause(dma_dev *dev, dma_channel channel) {
-    uint8 status_bits = dma_get_isr_bits(dev, channel);
-
-    /* If the channel global interrupt flag is cleared, then
-     * something's very wrong. */
-    ASSERT(status_bits & BIT(0));
-
-    dma_clear_isr_bits(dev, channel);
-
-    /* ISR flags get set even if the corresponding interrupt enable
-     * bits in the channel's configuration register are cleared, so we
-     * can't use a switch here.
-     *
-     * Don't change the order of these if statements. */
-    if (status_bits & BIT(3)) {
-        return DMA_TRANSFER_ERROR;
-    } else if (status_bits & BIT(1)) {
-        return DMA_TRANSFER_COMPLETE;
-    } else if (status_bits & BIT(2)) {
-        return DMA_TRANSFER_HALF_COMPLETE;
-    } else if (status_bits & BIT(0)) {
-        /* Shouldn't happen (unless someone messed up an IFCR write). */
-        throb();
-    }
-#if DEBUG_LEVEL < DEBUG_ALL
-    else {
-        /* We shouldn't have been called, but the debug level is too
-         * low for the above ASSERT() to have had any effect.  In
-         * order to fail fast, mimic the DMA controller's behavior
-         * when an error occurs. */
-        dma_disable(dev, channel);
-    }
-#endif
-    return DMA_TRANSFER_ERROR;
-}
-
-/**
- * @brief Enable a DMA channel.
- * @param dev DMA device
- * @param channel Channel to enable
- */
-void dma_enable(dma_dev *dev, dma_channel channel) {
-    dma_channel_reg_map *chan_regs = dma_channel_regs(dev, channel);
-    bb_peri_set_bit(&chan_regs->CCR, DMA_CCR_EN_BIT, 1);
-}
-
-/**
- * @brief Disable a DMA channel.
- * @param dev DMA device
- * @param channel Channel to disable
- */
-void dma_disable(dma_dev *dev, dma_channel channel) {
-    dma_channel_reg_map *chan_regs = dma_channel_regs(dev, channel);
-    bb_peri_set_bit(&chan_regs->CCR, DMA_CCR_EN_BIT, 0);
-}
-
-/**
- * @brief Set the base memory address where data will be read from or
- *        written to.
- *
- * You must not call this function while the channel is enabled.
- *
- * If the DMA memory size is 16 bits, the address is automatically
- * aligned to a half-word.  If the DMA memory size is 32 bits, the
- * address is aligned to a word.
- *
- * @param dev DMA Device
- * @param channel Channel whose base memory address to set.
- * @param addr Memory base address to use.
- */
-void dma_set_mem_addr(dma_dev *dev, dma_channel channel, __io void *addr) {
-    dma_channel_reg_map *chan_regs;
-
-    ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
-
-    chan_regs = dma_channel_regs(dev, channel);
-    chan_regs->CMAR = (uint32)addr;
-}
-
-/**
- * @brief Set the base peripheral address where data will be read from
- *        or written to.
- *
- * You must not call this function while the channel is enabled.
- *
- * If the DMA peripheral size is 16 bits, the address is automatically
- * aligned to a half-word.  If the DMA peripheral size is 32 bits, the
- * address is aligned to a word.
- *
- * @param dev DMA Device
- * @param channel Channel whose peripheral data register base address to set.
- * @param addr Peripheral memory base address to use.
- */
-void dma_set_per_addr(dma_dev *dev, dma_channel channel, __io void *addr) {
-    dma_channel_reg_map *chan_regs;
-
-    ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
-
-    chan_regs = dma_channel_regs(dev, channel);
-    chan_regs->CPAR = (uint32)addr;
-}
-
-/*
- * IRQ handlers
- */
-
-static inline void dispatch_handler(dma_dev *dev, dma_channel channel) {
-    void (*handler)(void) = dev->handlers[channel - 1].handler;
-    if (handler) {
-        handler();
-        dma_clear_isr_bits(dev, channel); /* in case handler doesn't */
-    }
-}
-
-void __irq_dma1_channel1(void) {
-    dispatch_handler(DMA1, DMA_CH1);
-}
-
-void __irq_dma1_channel2(void) {
-    dispatch_handler(DMA1, DMA_CH2);
-}
-
-void __irq_dma1_channel3(void) {
-    dispatch_handler(DMA1, DMA_CH3);
-}
-
-void __irq_dma1_channel4(void) {
-    dispatch_handler(DMA1, DMA_CH4);
-}
-
-void __irq_dma1_channel5(void) {
-    dispatch_handler(DMA1, DMA_CH5);
-}
-
-void __irq_dma1_channel6(void) {
-    dispatch_handler(DMA1, DMA_CH6);
-}
-
-void __irq_dma1_channel7(void) {
-    dispatch_handler(DMA1, DMA_CH7);
-}
-
-#ifdef STM32_HIGH_DENSITY
-void __irq_dma2_channel1(void) {
-    dispatch_handler(DMA2, DMA_CH1);
-}
-
-void __irq_dma2_channel2(void) {
-    dispatch_handler(DMA2, DMA_CH2);
-}
-
-void __irq_dma2_channel3(void) {
-    dispatch_handler(DMA2, DMA_CH3);
-}
-
-void __irq_dma2_channel4_5(void) {
-    dispatch_handler(DMA2, DMA_CH4);
-    dispatch_handler(DMA2, DMA_CH5);
-}
-#endif
-
-#endif
\ No newline at end of file
diff --git a/STM32F4/cores/maple/libmaple/dmaF1.h b/STM32F4/cores/maple/libmaple/dmaF1.h
deleted file mode 100644
index 6e8087f49..000000000
--- a/STM32F4/cores/maple/libmaple/dmaF1.h
+++ /dev/null
@@ -1,453 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Michael Hope.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file dma.h
- *
- * @author Marti Bolivar <mbolivar@leaflabs.com>;
- *         Original implementation by Michael Hope
- *
- * @brief Direct Memory Access peripheral support
- */
-
-/*
- * See /notes/dma.txt for more information.
- */
-
-#ifndef _DMA_H_
-#define _DMA_H_
-
-#include "libmaple_types.h"
-#include "rcc.h"
-#include "nvic.h"
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-/*
- * Register maps
- */
-
-/**
- * @brief DMA register map type.
- *
- * Note that DMA controller 2 (register map base pointer DMA2_BASE)
- * only supports channels 1--5.
- */
-typedef struct dma_reg_map {
-    __io uint32 ISR;            /**< Interrupt status register */
-    __io uint32 IFCR;           /**< Interrupt flag clear register */
-    __io uint32 CCR1;           /**< Channel 1 configuration register */
-    __io uint32 CNDTR1;         /**< Channel 1 number of data register */
-    __io uint32 CPAR1;          /**< Channel 1 peripheral address register */
-    __io uint32 CMAR1;          /**< Channel 1 memory address register */
-    const uint32 RESERVED1;     /**< Reserved. */
-    __io uint32 CCR2;           /**< Channel 2 configuration register */
-    __io uint32 CNDTR2;         /**< Channel 2 number of data register */
-    __io uint32 CPAR2;          /**< Channel 2 peripheral address register */
-    __io uint32 CMAR2;          /**< Channel 2 memory address register */
-    const uint32 RESERVED2;     /**< Reserved. */
-    __io uint32 CCR3;           /**< Channel 3 configuration register */
-    __io uint32 CNDTR3;         /**< Channel 3 number of data register */
-    __io uint32 CPAR3;          /**< Channel 3 peripheral address register */
-    __io uint32 CMAR3;          /**< Channel 3 memory address register */
-    const uint32 RESERVED3;     /**< Reserved. */
-    __io uint32 CCR4;           /**< Channel 4 configuration register */
-    __io uint32 CNDTR4;         /**< Channel 4 number of data register */
-    __io uint32 CPAR4;          /**< Channel 4 peripheral address register */
-    __io uint32 CMAR4;          /**< Channel 4 memory address register */
-    const uint32 RESERVED4;     /**< Reserved. */
-    __io uint32 CCR5;           /**< Channel 5 configuration register */
-    __io uint32 CNDTR5;         /**< Channel 5 number of data register */
-    __io uint32 CPAR5;          /**< Channel 5 peripheral address register */
-    __io uint32 CMAR5;          /**< Channel 5 memory address register */
-    const uint32 RESERVED5;     /**< Reserved. */
-    __io uint32 CCR6;           /**< Channel 6 configuration register */
-    __io uint32 CNDTR6;         /**< Channel 6 number of data register */
-    __io uint32 CPAR6;          /**< Channel 6 peripheral address register */
-    __io uint32 CMAR6;          /**< Channel 6 memory address register */
-    const uint32 RESERVED6;     /**< Reserved. */
-    __io uint32 CCR7;           /**< Channel 7 configuration register */
-    __io uint32 CNDTR7;         /**< Channel 7 number of data register */
-    __io uint32 CPAR7;          /**< Channel 7 peripheral address register */
-    __io uint32 CMAR7;          /**< Channel 7 memory address register */
-    const uint32 RESERVED7;     /**< Reserved. */
-} dma_reg_map;
-
-/** DMA controller 1 register map base pointer */
-#define DMA1_BASE                       ((struct dma_reg_map*)0x40020000)
-
-#ifdef STM32_HIGH_DENSITY
-/** DMA controller 2 register map base pointer */
-#define DMA2_BASE                       ((struct dma_reg_map*)0x40020400)
-#endif
-
-/*
- * Register bit definitions
- */
-
-/* Interrupt status register */
-
-#define DMA_ISR_TEIF7_BIT               27
-#define DMA_ISR_HTIF7_BIT               26
-#define DMA_ISR_TCIF7_BIT               25
-#define DMA_ISR_GIF7_BIT                24
-#define DMA_ISR_TEIF6_BIT               23
-#define DMA_ISR_HTIF6_BIT               22
-#define DMA_ISR_TCIF6_BIT               21
-#define DMA_ISR_GIF6_BIT                20
-#define DMA_ISR_TEIF5_BIT               19
-#define DMA_ISR_HTIF5_BIT               18
-#define DMA_ISR_TCIF5_BIT               17
-#define DMA_ISR_GIF5_BIT                16
-#define DMA_ISR_TEIF4_BIT               15
-#define DMA_ISR_HTIF4_BIT               14
-#define DMA_ISR_TCIF4_BIT               13
-#define DMA_ISR_GIF4_BIT                12
-#define DMA_ISR_TEIF3_BIT               11
-#define DMA_ISR_HTIF3_BIT               10
-#define DMA_ISR_TCIF3_BIT               9
-#define DMA_ISR_GIF3_BIT                8
-#define DMA_ISR_TEIF2_BIT               7
-#define DMA_ISR_HTIF2_BIT               6
-#define DMA_ISR_TCIF2_BIT               5
-#define DMA_ISR_GIF2_BIT                4
-#define DMA_ISR_TEIF1_BIT               3
-#define DMA_ISR_HTIF1_BIT               2
-#define DMA_ISR_TCIF1_BIT               1
-#define DMA_ISR_GIF1_BIT                0
-
-#define DMA_ISR_TEIF7                   BIT(DMA_ISR_TEIF7_BIT)
-#define DMA_ISR_HTIF7                   BIT(DMA_ISR_HTIF7_BIT)
-#define DMA_ISR_TCIF7                   BIT(DMA_ISR_TCIF7_BIT)
-#define DMA_ISR_GIF7                    BIT(DMA_ISR_GIF7_BIT)
-#define DMA_ISR_TEIF6                   BIT(DMA_ISR_TEIF6_BIT)
-#define DMA_ISR_HTIF6                   BIT(DMA_ISR_HTIF6_BIT)
-#define DMA_ISR_TCIF6                   BIT(DMA_ISR_TCIF6_BIT)
-#define DMA_ISR_GIF6                    BIT(DMA_ISR_GIF6_BIT)
-#define DMA_ISR_TEIF5                   BIT(DMA_ISR_TEIF5_BIT)
-#define DMA_ISR_HTIF5                   BIT(DMA_ISR_HTIF5_BIT)
-#define DMA_ISR_TCIF5                   BIT(DMA_ISR_TCIF5_BIT)
-#define DMA_ISR_GIF5                    BIT(DMA_ISR_GIF5_BIT)
-#define DMA_ISR_TEIF4                   BIT(DMA_ISR_TEIF4_BIT)
-#define DMA_ISR_HTIF4                   BIT(DMA_ISR_HTIF4_BIT)
-#define DMA_ISR_TCIF4                   BIT(DMA_ISR_TCIF4_BIT)
-#define DMA_ISR_GIF4                    BIT(DMA_ISR_GIF4_BIT)
-#define DMA_ISR_TEIF3                   BIT(DMA_ISR_TEIF3_BIT)
-#define DMA_ISR_HTIF3                   BIT(DMA_ISR_HTIF3_BIT)
-#define DMA_ISR_TCIF3                   BIT(DMA_ISR_TCIF3_BIT)
-#define DMA_ISR_GIF3                    BIT(DMA_ISR_GIF3_BIT)
-#define DMA_ISR_TEIF2                   BIT(DMA_ISR_TEIF2_BIT)
-#define DMA_ISR_HTIF2                   BIT(DMA_ISR_HTIF2_BIT)
-#define DMA_ISR_TCIF2                   BIT(DMA_ISR_TCIF2_BIT)
-#define DMA_ISR_GIF2                    BIT(DMA_ISR_GIF2_BIT)
-#define DMA_ISR_TEIF1                   BIT(DMA_ISR_TEIF1_BIT)
-#define DMA_ISR_HTIF1                   BIT(DMA_ISR_HTIF1_BIT)
-#define DMA_ISR_TCIF1                   BIT(DMA_ISR_TCIF1_BIT)
-#define DMA_ISR_GIF1                    BIT(DMA_ISR_GIF1_BIT)
-
-/* Interrupt flag clear register */
-
-#define DMA_IFCR_CTEIF7_BIT             27
-#define DMA_IFCR_CHTIF7_BIT             26
-#define DMA_IFCR_CTCIF7_BIT             25
-#define DMA_IFCR_CGIF7_BIT              24
-#define DMA_IFCR_CTEIF6_BIT             23
-#define DMA_IFCR_CHTIF6_BIT             22
-#define DMA_IFCR_CTCIF6_BIT             21
-#define DMA_IFCR_CGIF6_BIT              20
-#define DMA_IFCR_CTEIF5_BIT             19
-#define DMA_IFCR_CHTIF5_BIT             18
-#define DMA_IFCR_CTCIF5_BIT             17
-#define DMA_IFCR_CGIF5_BIT              16
-#define DMA_IFCR_CTEIF4_BIT             15
-#define DMA_IFCR_CHTIF4_BIT             14
-#define DMA_IFCR_CTCIF4_BIT             13
-#define DMA_IFCR_CGIF4_BIT              12
-#define DMA_IFCR_CTEIF3_BIT             11
-#define DMA_IFCR_CHTIF3_BIT             10
-#define DMA_IFCR_CTCIF3_BIT             9
-#define DMA_IFCR_CGIF3_BIT              8
-#define DMA_IFCR_CTEIF2_BIT             7
-#define DMA_IFCR_CHTIF2_BIT             6
-#define DMA_IFCR_CTCIF2_BIT             5
-#define DMA_IFCR_CGIF2_BIT              4
-#define DMA_IFCR_CTEIF1_BIT             3
-#define DMA_IFCR_CHTIF1_BIT             2
-#define DMA_IFCR_CTCIF1_BIT             1
-#define DMA_IFCR_CGIF1_BIT              0
-
-#define DMA_IFCR_CTEIF7                 BIT(DMA_IFCR_CTEIF7_BIT)
-#define DMA_IFCR_CHTIF7                 BIT(DMA_IFCR_CHTIF7_BIT)
-#define DMA_IFCR_CTCIF7                 BIT(DMA_IFCR_CTCIF7_BIT)
-#define DMA_IFCR_CGIF7                  BIT(DMA_IFCR_CGIF7_BIT)
-#define DMA_IFCR_CTEIF6                 BIT(DMA_IFCR_CTEIF6_BIT)
-#define DMA_IFCR_CHTIF6                 BIT(DMA_IFCR_CHTIF6_BIT)
-#define DMA_IFCR_CTCIF6                 BIT(DMA_IFCR_CTCIF6_BIT)
-#define DMA_IFCR_CGIF6                  BIT(DMA_IFCR_CGIF6_BIT)
-#define DMA_IFCR_CTEIF5                 BIT(DMA_IFCR_CTEIF5_BIT)
-#define DMA_IFCR_CHTIF5                 BIT(DMA_IFCR_CHTIF5_BIT)
-#define DMA_IFCR_CTCIF5                 BIT(DMA_IFCR_CTCIF5_BIT)
-#define DMA_IFCR_CGIF5                  BIT(DMA_IFCR_CGIF5_BIT)
-#define DMA_IFCR_CTEIF4                 BIT(DMA_IFCR_CTEIF4_BIT)
-#define DMA_IFCR_CHTIF4                 BIT(DMA_IFCR_CHTIF4_BIT)
-#define DMA_IFCR_CTCIF4                 BIT(DMA_IFCR_CTCIF4_BIT)
-#define DMA_IFCR_CGIF4                  BIT(DMA_IFCR_CGIF4_BIT)
-#define DMA_IFCR_CTEIF3                 BIT(DMA_IFCR_CTEIF3_BIT)
-#define DMA_IFCR_CHTIF3                 BIT(DMA_IFCR_CHTIF3_BIT)
-#define DMA_IFCR_CTCIF3                 BIT(DMA_IFCR_CTCIF3_BIT)
-#define DMA_IFCR_CGIF3                  BIT(DMA_IFCR_CGIF3_BIT)
-#define DMA_IFCR_CTEIF2                 BIT(DMA_IFCR_CTEIF2_BIT)
-#define DMA_IFCR_CHTIF2                 BIT(DMA_IFCR_CHTIF2_BIT)
-#define DMA_IFCR_CTCIF2                 BIT(DMA_IFCR_CTCIF2_BIT)
-#define DMA_IFCR_CGIF2                  BIT(DMA_IFCR_CGIF2_BIT)
-#define DMA_IFCR_CTEIF1                 BIT(DMA_IFCR_CTEIF1_BIT)
-#define DMA_IFCR_CHTIF1                 BIT(DMA_IFCR_CHTIF1_BIT)
-#define DMA_IFCR_CTCIF1                 BIT(DMA_IFCR_CTCIF1_BIT)
-#define DMA_IFCR_CGIF1                  BIT(DMA_IFCR_CGIF1_BIT)
-
-/* Channel configuration register */
-
-#define DMA_CCR_MEM2MEM_BIT             14
-#define DMA_CCR_MINC_BIT                7
-#define DMA_CCR_PINC_BIT                6
-#define DMA_CCR_CIRC_BIT                5
-#define DMA_CCR_DIR_BIT                 4
-#define DMA_CCR_TEIE_BIT                3
-#define DMA_CCR_HTIE_BIT                2
-#define DMA_CCR_TCIE_BIT                1
-#define DMA_CCR_EN_BIT                  0
-
-#define DMA_CCR_MEM2MEM                 BIT(DMA_CCR_MEM2MEM_BIT)
-#define DMA_CCR_PL                      (0x3 << 12)
-#define DMA_CCR_PL_LOW                  (0x0 << 12)
-#define DMA_CCR_PL_MEDIUM               (0x1 << 12)
-#define DMA_CCR_PL_HIGH                 (0x2 << 12)
-#define DMA_CCR_PL_VERY_HIGH            (0x3 << 12)
-#define DMA_CCR_MSIZE                   (0x3 << 10)
-#define DMA_CCR_MSIZE_8BITS             (0x0 << 10)
-#define DMA_CCR_MSIZE_16BITS            (0x1 << 10)
-#define DMA_CCR_MSIZE_32BITS            (0x2 << 10)
-#define DMA_CCR_PSIZE                   (0x3 << 8)
-#define DMA_CCR_PSIZE_8BITS             (0x0 << 8)
-#define DMA_CCR_PSIZE_16BITS            (0x1 << 8)
-#define DMA_CCR_PSIZE_32BITS            (0x2 << 8)
-#define DMA_CCR_MINC                    BIT(DMA_CCR_MINC_BIT)
-#define DMA_CCR_PINC                    BIT(DMA_CCR_PINC_BIT)
-#define DMA_CCR_CIRC                    BIT(DMA_CCR_CIRC_BIT)
-#define DMA_CCR_DIR                     BIT(DMA_CCR_DIR_BIT)
-#define DMA_CCR_TEIE                    BIT(DMA_CCR_TEIE_BIT)
-#define DMA_CCR_HTIE                    BIT(DMA_CCR_HTIE_BIT)
-#define DMA_CCR_TCIE                    BIT(DMA_CCR_TCIE_BIT)
-#define DMA_CCR_EN                      BIT(DMA_CCR_EN_BIT)
-
-/*
- * Devices
- */
-
-/** Encapsulates state related to a DMA channel interrupt. */
-typedef struct dma_handler_config {
-    void (*handler)(void);      /**< User-specified channel interrupt
-                                     handler */
-    nvic_irq_num irq_line;      /**< Channel's NVIC interrupt number */
-} dma_handler_config;
-
-/** DMA device type */
-typedef struct dma_dev {
-    dma_reg_map *regs;             /**< Register map */
-    rcc_clk_id clk_id;             /**< Clock ID */
-    dma_handler_config handlers[]; /**<
-                                    * @brief IRQ handlers and NVIC numbers.
-                                    *
-                                    * @see dma_attach_interrupt()
-                                    * @see dma_detach_interrupt()
-                                    */
-} dma_dev;
-
-extern dma_dev *DMA1;
-#ifdef STM32_HIGH_DENSITY
-extern dma_dev *DMA2;
-#endif
-
-/*
- * Convenience functions
- */
-
-void dma_init(dma_dev *dev);
-
-/** Flags for DMA transfer configuration. */
-typedef enum dma_mode_flags {
-    DMA_MEM_2_MEM  = 1 << 14, /**< Memory to memory mode */
-    DMA_MINC_MODE  = 1 << 7,  /**< Auto-increment memory address */
-    DMA_PINC_MODE  = 1 << 6,  /**< Auto-increment peripheral address */
-    DMA_CIRC_MODE  = 1 << 5,  /**< Circular mode */
-    DMA_FROM_MEM   = 1 << 4,  /**< Read from memory to peripheral */
-    DMA_TRNS_ERR   = 1 << 3,  /**< Interrupt on transfer error */
-    DMA_HALF_TRNS  = 1 << 2,  /**< Interrupt on half-transfer */
-    DMA_TRNS_CMPLT = 1 << 1   /**< Interrupt on transfer completion */
-} dma_mode_flags;
-
-/** Source and destination transfer sizes. */
-typedef enum dma_xfer_size {
-    DMA_SIZE_8BITS  = 0,        /**< 8-bit transfers */
-    DMA_SIZE_16BITS = 1,        /**< 16-bit transfers */
-    DMA_SIZE_32BITS = 2         /**< 32-bit transfers */
-} dma_xfer_size;
-
-/** DMA channel */
-typedef enum dma_channel {
-    DMA_CH1 = 1,                /**< Channel 1 */
-    DMA_CH2 = 2,                /**< Channel 2 */
-    DMA_CH3 = 3,                /**< Channel 3 */
-    DMA_CH4 = 4,                /**< Channel 4 */
-    DMA_CH5 = 5,                /**< Channel 5 */
-    DMA_CH6 = 6,                /**< Channel 6 */
-    DMA_CH7 = 7,                /**< Channel 7 */
-} dma_channel;
-
-void dma_setup_transfer(dma_dev       *dev,
-                        dma_channel    channel,
-                        __io void     *peripheral_address,
-                        dma_xfer_size  peripheral_size,
-                        __io void     *memory_address,
-                        dma_xfer_size  memory_size,
-                        uint32         mode);
-
-void dma_set_num_transfers(dma_dev *dev,
-                           dma_channel channel,
-                           uint16 num_transfers);
-
-/** DMA transfer priority. */
-typedef enum dma_priority {
-    DMA_PRIORITY_LOW       = DMA_CCR_PL_LOW,      /**< Low priority */
-    DMA_PRIORITY_MEDIUM    = DMA_CCR_PL_MEDIUM,   /**< Medium priority */
-    DMA_PRIORITY_HIGH      = DMA_CCR_PL_HIGH,     /**< High priority */
-    DMA_PRIORITY_VERY_HIGH = DMA_CCR_PL_VERY_HIGH /**< Very high priority */
-} dma_priority;
-
-void dma_set_priority(dma_dev *dev,
-                      dma_channel channel,
-                      dma_priority priority);
-
-void dma_attach_interrupt(dma_dev *dev,
-                          dma_channel channel,
-                          void (*handler)(void));
-void dma_detach_interrupt(dma_dev *dev, dma_channel channel);
-
-/**
- * Encodes the reason why a DMA interrupt was called.
- * @see dma_get_irq_cause()
- */
-typedef enum dma_irq_cause {
-    DMA_TRANSFER_COMPLETE,      /**< Transfer is complete. */
-    DMA_TRANSFER_HALF_COMPLETE, /**< Transfer is half complete. */
-    DMA_TRANSFER_ERROR,         /**< Error occurred during transfer. */
-} dma_irq_cause;
-
-dma_irq_cause dma_get_irq_cause(dma_dev *dev, dma_channel channel);
-
-void dma_enable(dma_dev *dev, dma_channel channel);
-void dma_disable(dma_dev *dev, dma_channel channel);
-
-void dma_set_mem_addr(dma_dev *dev, dma_channel channel, __io void *address);
-void dma_set_per_addr(dma_dev *dev, dma_channel channel, __io void *address);
-
-/**
- * @brief DMA channel register map type.
- *
- * Provides access to an individual channel's registers.
- */
-typedef struct dma_channel_reg_map {
-    __io uint32 CCR;           /**< Channel configuration register */
-    __io uint32 CNDTR;         /**< Channel number of data register */
-    __io uint32 CPAR;          /**< Channel peripheral address register */
-    __io uint32 CMAR;          /**< Channel memory address register */
-} dma_channel_reg_map;
-
-#define DMA_CHANNEL_NREGS 5
-
-/**
- * @brief Obtain a pointer to an individual DMA channel's registers.
- *
- * For example, dma_channel_regs(DMA1, DMA_CH1)->CCR is DMA1_BASE->CCR1.
- *
- * @param dev DMA device
- * @param channel DMA channel whose channel register map to obtain.
- */
-static inline dma_channel_reg_map* dma_channel_regs(dma_dev *dev,
-                                                    dma_channel channel) {
-    __io uint32 *ccr1 = &dev->regs->CCR1;
-    return (dma_channel_reg_map*)(ccr1 + DMA_CHANNEL_NREGS * (channel - 1));
-}
-
-/**
- * @brief Check if a DMA channel is enabled
- * @param dev DMA device
- * @param channel Channel whose enabled bit to check.
- */
-static inline uint8 dma_is_channel_enabled(dma_dev *dev, dma_channel channel) {
-    return (uint8)(dma_channel_regs(dev, channel)->CCR & DMA_CCR_EN);
-}
-
-/**
- * @brief Get the ISR status bits for a DMA channel.
- *
- * The bits are returned right-aligned, in the following order:
- * transfer error flag, half-transfer flag, transfer complete flag,
- * global interrupt flag.
- *
- * If you're attempting to figure out why a DMA interrupt fired; you
- * may find dma_get_irq_cause() more convenient.
- *
- * @param dev DMA device
- * @param channel Channel whose ISR bits to return.
- * @see dma_get_irq_cause().
- */
-static inline uint8 dma_get_isr_bits(dma_dev *dev, dma_channel channel) {
-    uint8 shift = (channel - 1) * 4;
-    return (dev->regs->ISR >> shift) & 0xF;
-}
-
-/**
- * @brief Clear the ISR status bits for a given DMA channel.
- *
- * If you're attempting to clean up after yourself in a DMA interrupt,
- * you may find dma_get_irq_cause() more convenient.
- *
- * @param dev DMA device
- * @param channel Channel whose ISR bits to clear.
- * @see dma_get_irq_cause()
- */
-static inline void dma_clear_isr_bits(dma_dev *dev, dma_channel channel) {
-    dev->regs->IFCR = BIT(4 * (channel - 1));
-}
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
-#endif
diff --git a/STM32F4/cores/maple/libmaple/dmaF2.c b/STM32F4/cores/maple/libmaple/dmaF4.c
similarity index 91%
rename from STM32F4/cores/maple/libmaple/dmaF2.c
rename to STM32F4/cores/maple/libmaple/dmaF4.c
index 0911e584a..add3d8e51 100644
--- a/STM32F4/cores/maple/libmaple/dmaF2.c
+++ b/STM32F4/cores/maple/libmaple/dmaF4.c
@@ -24,10 +24,10 @@
  * SOFTWARE.
  *****************************************************************************/
 
- #ifdef STM32F2
+#ifdef STM32F4
  
 /**
- * @file dmaF2.c
+ * @file dmaF4.c
  * @brief Direct Memory Access peripheral support
  */
 
@@ -117,33 +117,16 @@ void dma_detach_interrupt(dma_dev *dev, dma_stream stream) {
     dev->handlers[stream].handler = NULL;
 }
 
+const uint8 dma_isr_bits_shift[] = { 0, 6, 16, 22};
+
+uint8 dma_get_isr_bits(dma_dev *dev, dma_stream stream) {
+	if ( stream&0xFC )	return ((dev->regs->HISR)>>dma_isr_bits_shift[stream&0x03]) & 0x3d;
+	else				return ((dev->regs->LISR)>>dma_isr_bits_shift[stream&0x03]) & 0x3d;
+}
+
 void dma_clear_isr_bits(dma_dev *dev, dma_stream stream) {
-    switch (stream) {
-    case 0:
-        dev->regs->LIFCR|=0x0000003d;
-        break;
-    case 1:
-        dev->regs->LIFCR|=0x00000f40;
-        break;
-    case 2:
-        dev->regs->LIFCR|=0x003d0000;
-        break;
-    case 3:
-        dev->regs->LIFCR|=0x0f400000;
-        break;
-    case 4:
-        dev->regs->HIFCR|=0x0000003d;
-        break;
-    case 5:
-        dev->regs->HIFCR|=0x00000f40;
-        break;
-    case 6:
-        dev->regs->HIFCR|=0x003d0000;
-        break;
-    case 7:
-        dev->regs->HIFCR|=0x0f400000;
-        break;
-    }
+	if ( stream&0xFC )	dev->regs->HIFCR = (uint32)0x0000003d << dma_isr_bits_shift[stream&0x03];
+	else				dev->regs->LIFCR = (uint32)0x0000003d << dma_isr_bits_shift[stream&0x03];
 }
 
 /*
diff --git a/STM32F4/cores/maple/libmaple/dmaF2.h b/STM32F4/cores/maple/libmaple/dmaF4.h
similarity index 74%
rename from STM32F4/cores/maple/libmaple/dmaF2.h
rename to STM32F4/cores/maple/libmaple/dmaF4.h
index 6f7086f36..757906c82 100644
--- a/STM32F4/cores/maple/libmaple/dmaF2.h
+++ b/STM32F4/cores/maple/libmaple/dmaF4.h
@@ -25,7 +25,7 @@
  *****************************************************************************/
 
 /**
- * @file dma.h
+ * @file dmaF4.h
  *
  * @author Marti Bolivar <mbolivar@leaflabs.com>;
  *         Original implementation by Michael Hope
@@ -84,7 +84,7 @@ typedef struct dma_reg_map {
  * Register bit definitions
  */
 
-/* Channel configuration register */
+/* Stream configuration register */
 
 #define DMA_CR_CH0                      (0x0 << 25)
 #define DMA_CR_CH1                      (0x1 << 25)
@@ -136,6 +136,25 @@ typedef struct dma_reg_map {
 #define DMA_CR_DMEIE                    (0x1 << 1)
 #define DMA_CR_EN                       (0x1)
 
+typedef enum dma_channel {
+    DMA_CH0 = DMA_CR_CH0,                /**< Channel 0 */
+    DMA_CH1 = DMA_CR_CH1,                /**< Channel 1 */
+    DMA_CH2 = DMA_CR_CH2,                /**< Channel 2 */
+    DMA_CH3 = DMA_CR_CH3,                /**< Channel 3 */
+    DMA_CH4 = DMA_CR_CH4,                /**< Channel 4 */
+    DMA_CH5 = DMA_CR_CH5,                /**< Channel 5 */
+    DMA_CH6 = DMA_CR_CH6,                /**< Channel 6 */
+    DMA_CH7 = DMA_CR_CH7,                /**< Channel 7 */
+} dma_channel;
+
+/* Device interrupt status register flags */
+
+#define DMA_ISR_TCIF    (1 << 5)
+#define DMA_ISR_HTIF    (1 << 4)
+#define DMA_ISR_TEIF    (1 << 3)
+#define DMA_ISR_DMEIF   (1 << 2)
+#define DMA_ISR_FEIF    (1 << 0)
+
 /*
  * Devices
  */
@@ -166,25 +185,35 @@ extern dma_dev *DMA2;
  * Convenience functions
  */
 
-void dma_init(dma_dev *dev);
+extern void dma_init(dma_dev *dev);
 
 /** Flags for DMA transfer configuration. */
 typedef enum dma_mode_flags {
-    DMA_MEM_2_MEM  = 1 << 14, /**< Memory to memory mode */
-    DMA_MINC_MODE  = 1 << 7,  /**< Auto-increment memory address */
-    DMA_PINC_MODE  = 1 << 6,  /**< Auto-increment peripheral address */
-    DMA_CIRC_MODE  = 1 << 5,  /**< Circular mode */
-    DMA_FROM_MEM   = 1 << 4,  /**< Read from memory to peripheral */
-    DMA_TRNS_ERR   = 1 << 3,  /**< Interrupt on transfer error */
-    DMA_HALF_TRNS  = 1 << 2,  /**< Interrupt on half-transfer */
-    DMA_TRNS_CMPLT = 1 << 1   /**< Interrupt on transfer completion */
+    DMA_MEM_BUF_0 = DMA_CR_CT0, /**< Current memory target buffer 0 */
+    DMA_MEM_BUF_1 = DMA_CR_CT1, /**< Current memory target buffer 1 */
+    DMA_DBL_BUF_MODE = DMA_CR_DBM,  /**< Current memory double buffer mode */
+    DMA_PINC_OFFSET  = DMA_CR_PINCOS,  /**< Peripheral increment offset size */
+    DMA_MINC_MODE  = DMA_CR_MINC,  /**< Memory increment mode */
+    DMA_PINC_MODE  = DMA_CR_PINC,  /**< Peripheral increment mode */
+    DMA_CIRC_MODE  = DMA_CR_CIRC,  /**< Memory Circular mode */
+    DMA_FROM_PER   = DMA_CR_DIR_P2M,  /**< Read from memory to peripheral */
+    DMA_FROM_MEM   = DMA_CR_DIR_M2P,  /**< Read from memory to peripheral */
+    DMA_MEM_TO_MEM = DMA_CR_DIR_M2M,  /**< Read from memory to memory */
+    DMA_PERIF_CTRL   = DMA_CR_PFCTRL,  /**< Peripheral flow controller */
+    DMA_PRIO_MEDIUM    = DMA_CR_PL_MEDIUM,    /**< Medium priority */
+    DMA_PRIO_HIGH      = DMA_CR_PL_HIGH,      /**< High priority */
+    DMA_PRIO_VERY_HIGH = DMA_CR_PL_VERY_HIGH, /**< Very high priority */
+    DMA_TRNS_CMPLT   = DMA_CR_TCIE,   /**< Interrupt on transfer completion */
+    DMA_TRNS_HALF    = DMA_CR_HTIE,  /**< Interrupt on half-transfer */
+    DMA_TRNS_ERR       = DMA_CR_TEIE,  /**< Interrupt on transfer error */
+    DMA_DIR_MODE_ERR   = DMA_CR_DMEIE  /**< Interrupt on direct mode error */
 } dma_mode_flags;
 
 /** Source and destination transfer sizes. */
 typedef enum dma_xfer_size {
-    DMA_SIZE_8BITS  = 0,        /**< 8-bit transfers */
-    DMA_SIZE_16BITS = 1,        /**< 16-bit transfers */
-    DMA_SIZE_32BITS = 2         /**< 32-bit transfers */
+    DMA_SIZE_8BITS  = ( DMA_CR_MSIZE_8BITS|DMA_CR_PSIZE_8BITS ),        /**< 8-bit transfers */
+    DMA_SIZE_16BITS = (DMA_CR_MSIZE_16BITS|DMA_CR_PSIZE_16BITS),        /**< 16-bit transfers */
+    DMA_SIZE_32BITS = (DMA_CR_MSIZE_32BITS|DMA_CR_PSIZE_32BITS)         /**< 32-bit transfers */
 } dma_xfer_size;
 
 /** DMA channel */
@@ -201,17 +230,17 @@ typedef enum dma_stream {
     
 static inline void dma_setup_transfer(dma_dev       *dev,
                                       dma_stream    stream,
+                                      dma_channel   channel,
+                                      dma_xfer_size trx_size,
                                       __io void     *peripheral_address,
                                       __io void     *memory_address0,
                                       __io void     *memory_address1,
-                                      uint32         flags,
-                                      uint32         fifo_flags) {
+                                      uint32        flags) {
     dev->regs->STREAM[stream].CR &= ~DMA_CR_EN; // disable
     dev->regs->STREAM[stream].PAR = (uint32)peripheral_address;
     dev->regs->STREAM[stream].M0AR = (uint32)memory_address0;
     dev->regs->STREAM[stream].M1AR = (uint32)memory_address1;
-    dev->regs->STREAM[stream].FCR = fifo_flags & 0x87; // mask out reserved bits
-    dev->regs->STREAM[stream].CR = flags & 0x0feffffe; // mask out reserved and enable
+    dev->regs->STREAM[stream].CR = ((flags|channel|trx_size) & 0x0feffffe); // mask out reserved and enable
 }
     
 static inline void dma_set_num_transfers(dma_dev *dev,
@@ -220,6 +249,12 @@ static inline void dma_set_num_transfers(dma_dev *dev,
     dev->regs->STREAM[stream].NDTR = num_transfers;
 }
 
+static inline void dma_set_fifo_flags(dma_dev *dev,
+                                      dma_stream stream,
+                                      uint8 fifo_flags) {
+    dev->regs->STREAM[stream].FCR = fifo_flags & 0x87; // mask out reserved bits
+}
+
 void dma_attach_interrupt(dma_dev *dev,
                           dma_stream stream,
                           void (*handler)(void));
@@ -232,6 +267,7 @@ static inline void dma_enable(dma_dev *dev, dma_stream stream) {
 
 static inline void dma_disable(dma_dev *dev, dma_stream stream) {
     dev->regs->STREAM[stream].CR &= ~DMA_CR_EN;
+	while (dev->regs->STREAM[stream].CR & DMA_CR_EN); // wait till EN bit is reset, see AN4031, chapter 4.1
 }    
 
 /**
diff --git a/STM32F4/cores/maple/libmaple/exti.h b/STM32F4/cores/maple/libmaple/exti.h
index bac8adcf4..063f2d7f1 100644
--- a/STM32F4/cores/maple/libmaple/exti.h
+++ b/STM32F4/cores/maple/libmaple/exti.h
@@ -52,11 +52,7 @@ typedef struct exti_reg_map {
 } exti_reg_map;
 
 /** EXTI register map base pointer */
-#ifdef STM32F2
 #define EXTI_BASE                       ((struct exti_reg_map*)0x40013C00)
-#else
-#define EXTI_BASE                       ((struct exti_reg_map*)0x40010400)
-#endif
 
 /** External interrupt trigger mode */
 typedef enum exti_trigger_mode {
diff --git a/STM32F4/cores/maple/libmaple/fsmc.c b/STM32F4/cores/maple/libmaple/fsmc.c
index 06ca7df6a..42b0d77b4 100644
--- a/STM32F4/cores/maple/libmaple/fsmc.c
+++ b/STM32F4/cores/maple/libmaple/fsmc.c
@@ -39,27 +39,28 @@
  */
 void fsmc_sram_init_gpios(void) {
     /* Data lines... */
-    gpio_set_mode(GPIOD,  0, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOD,  1, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOD,  8, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOD,  9, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOD, 10, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOD, 14, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOD, 15, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE,  7, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE,  8, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE,  9, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE, 10, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE, 11, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE, 12, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE, 13, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE, 14, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE, 15, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD0, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD1, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD8, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD9, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD10, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD14, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD15, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE7, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE8, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE9, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE10, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE11, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE12, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE13, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE14, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE15, GPIO_AF_OUTPUT_PP);
 
     /* Address lines... */
-    gpio_set_mode(GPIOD, 11, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOD, 12, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOD, 13, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD11, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD12, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD13, GPIO_AF_OUTPUT_PP);
+#if 0 // not available on LQFP package
     gpio_set_mode(GPIOF,  0, GPIO_AF_OUTPUT_PP);
     gpio_set_mode(GPIOF,  1, GPIO_AF_OUTPUT_PP);
     gpio_set_mode(GPIOF,  2, GPIO_AF_OUTPUT_PP);
@@ -76,18 +77,20 @@ void fsmc_sram_init_gpios(void) {
     gpio_set_mode(GPIOG,  3, GPIO_AF_OUTPUT_PP);
     gpio_set_mode(GPIOG,  4, GPIO_AF_OUTPUT_PP);
     gpio_set_mode(GPIOG,  5, GPIO_AF_OUTPUT_PP);
-
+#endif  // not available on LQFP package
     /* And control lines... */
-    gpio_set_mode(GPIOD,  4, GPIO_AF_OUTPUT_PP);   // NOE
-    gpio_set_mode(GPIOD,  5, GPIO_AF_OUTPUT_PP);   // NWE
+    gpio_set_mode(PD4, GPIO_AF_OUTPUT_PP);   // NOE
+    gpio_set_mode(PD5, GPIO_AF_OUTPUT_PP);   // NWE
 
-    gpio_set_mode(GPIOD,  7, GPIO_AF_OUTPUT_PP);   // NE1
+    gpio_set_mode(PD7, GPIO_AF_OUTPUT_PP);   // NE1
+#if 0 // not available on LQFP package
     gpio_set_mode(GPIOG,  9, GPIO_AF_OUTPUT_PP);   // NE2
     gpio_set_mode(GPIOG, 10, GPIO_AF_OUTPUT_PP);   // NE3
     gpio_set_mode(GPIOG, 12, GPIO_AF_OUTPUT_PP);   // NE4
+#endif  // not available on LQFP package
 
-    gpio_set_mode(GPIOE,  0, GPIO_AF_OUTPUT_PP);   // NBL0
-    gpio_set_mode(GPIOE,  1, GPIO_AF_OUTPUT_PP);   // NBL1
+    gpio_set_mode(PE0, GPIO_AF_OUTPUT_PP);   // NBL0
+    gpio_set_mode(PE1, GPIO_AF_OUTPUT_PP);   // NBL1
 }
 
 #endif  /* STM32_HIGH_DENSITY */
diff --git a/STM32F4/cores/maple/libmaple/gpio.h b/STM32F4/cores/maple/libmaple/gpio.h
index 4d42386c1..f1a141fee 100644
--- a/STM32F4/cores/maple/libmaple/gpio.h
+++ b/STM32F4/cores/maple/libmaple/gpio.h
@@ -31,8 +31,102 @@
  *         (AFIO) prototypes, defines, and inlined access functions.
  */
 
-#ifdef STM32F2
-#include "gpioF2.h"
-#else
-#include "gpioF1.h"
+#ifndef _GPIO_H_
+#define _GPIO_H_
+
+#include "libmaple.h"
+#include "boards.h"
+
+#ifdef __cplusplus
+extern "C"{
 #endif
+
+
+/**
+ * @brief Get a GPIO port's corresponding afio_exti_port.
+ * @param dev GPIO device whose afio_exti_port to return.
+ */
+static inline afio_exti_port gpio_exti_port(const gpio_dev *dev) {
+    return dev->exti_port;
+}
+
+/**
+ * Set or reset a GPIO pin.
+ *
+ * Pin must have previously been configured to output mode.
+ *
+ * @param dev GPIO device whose pin to set.
+ * @param pin Pin on to set or reset
+ * @param val If true, set the pin.  If false, reset the pin.
+ */
+static inline void gpio_write_pin(uint8_t pin, uint8 val) {
+    if (val) {
+        (PIN_MAP[pin].gpio_device)->regs->BSRRL = BIT(pin&0x0F);
+    } else {
+        (PIN_MAP[pin].gpio_device)->regs->BSRRH = BIT(pin&0x0F);
+    }
+}
+
+static inline void gpio_set_pin(uint8_t pin) {
+	(PIN_MAP[pin].gpio_device)->regs->BSRRL = BIT(pin&0x0F);
+}
+
+static inline void gpio_clear_pin(uint8_t pin) {
+	(PIN_MAP[pin].gpio_device)->regs->BSRRH = BIT(pin&0x0F);
+}
+
+/**
+ * Determine whether or not a GPIO pin is set.
+ *
+ * Pin must have previously been configured to input mode.
+ *
+ * @param dev GPIO device whose pin to test.
+ * @param pin Pin on dev to test.
+ * @return True if the pin is set, false otherwise.
+ */
+static inline uint32 gpio_read_pin(uint8_t pin) {
+    return (PIN_MAP[pin].gpio_device)->regs->IDR & BIT(pin&0x0F);
+}
+
+/**
+ * Toggle a pin configured as output push-pull.
+ * @param dev GPIO device.
+ * @param pin Pin on dev to toggle.
+ */
+static inline void gpio_toggle_pin(uint8_t pin) {
+    (PIN_MAP[pin].gpio_device)->regs->ODR = (PIN_MAP[pin].gpio_device)->regs->ODR ^ BIT(pin&0x0F);
+}
+
+/*
+ * GPIO Convenience routines
+ */
+
+extern void gpio_init(const gpio_dev *dev);
+extern void gpio_init_all(void);
+extern void gpio_set_mode(uint8_t pin, gpio_pin_mode mode);
+extern void gpio_set_af_mode(uint8_t pin, int mode);
+
+/*
+ * AFIO convenience routines
+ */
+
+extern void afio_init(void);
+extern void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port);
+extern void afio_remap(afio_remap_peripheral p);
+
+/**
+ * @brief Enable or disable the JTAG and SW debug ports.
+ * @param config Desired debug port configuration
+ * @see afio_debug_cfg
+ */
+static inline void afio_cfg_debug_ports(afio_debug_cfg config) {
+    //__io uint32 *mapr = &AFIO_BASE->MAPR;
+    //*mapr = (*mapr & ~AFIO_MAPR_SWJ_CFG) | config;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/STM32F4/cores/maple/libmaple/gpioF1.c b/STM32F4/cores/maple/libmaple/gpioF1.c
deleted file mode 100644
index 846b7542a..000000000
--- a/STM32F4/cores/maple/libmaple/gpioF1.c
+++ /dev/null
@@ -1,200 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-#ifdef STM32F1
-
-/**
- * @file gpio.c
- * @brief GPIO initialization routine
- */
-
-#include "gpio.h"
-#include "rcc.h"
-
-/*
- * GPIO devices
- */
-
-gpio_dev gpioa = {
-    .regs      = GPIOA_BASE,
-    .clk_id    = RCC_GPIOA,
-    .exti_port = AFIO_EXTI_PA,
-};
-/** GPIO port A device. */
-gpio_dev* const GPIOA = &gpioa;
-
-gpio_dev gpiob = {
-    .regs      = GPIOB_BASE,
-    .clk_id    = RCC_GPIOB,
-    .exti_port = AFIO_EXTI_PB,
-};
-/** GPIO port B device. */
-gpio_dev* const GPIOB = &gpiob;
-
-gpio_dev gpioc = {
-    .regs      = GPIOC_BASE,
-    .clk_id    = RCC_GPIOC,
-    .exti_port = AFIO_EXTI_PC,
-};
-/** GPIO port C device. */
-gpio_dev* const GPIOC = &gpioc;
-
-gpio_dev gpiod = {
-    .regs      = GPIOD_BASE,
-    .clk_id    = RCC_GPIOD,
-    .exti_port = AFIO_EXTI_PD,
-};
-/** GPIO port D device. */
-gpio_dev* const GPIOD = &gpiod;
-
-#ifdef STM32_HIGH_DENSITY
-gpio_dev gpioe = {
-    .regs      = GPIOE_BASE,
-    .clk_id    = RCC_GPIOE,
-    .exti_port = AFIO_EXTI_PE,
-};
-/** GPIO port E device. */
-gpio_dev* const GPIOE = &gpioe;
-
-gpio_dev gpiof = {
-    .regs      = GPIOF_BASE,
-    .clk_id    = RCC_GPIOF,
-    .exti_port = AFIO_EXTI_PF,
-};
-/** GPIO port F device. */
-gpio_dev* const GPIOF = &gpiof;
-
-gpio_dev gpiog = {
-    .regs      = GPIOG_BASE,
-    .clk_id    = RCC_GPIOG,
-    .exti_port = AFIO_EXTI_PG,
-};
-/** GPIO port G device. */
-gpio_dev* const GPIOG = &gpiog;
-#endif
-
-/*
- * GPIO convenience routines
- */
-
-/**
- * Initialize a GPIO device.
- *
- * Enables the clock for and resets the given device.
- *
- * @param dev GPIO device to initialize.
- */
-void gpio_init(gpio_dev *dev) {
-    rcc_clk_enable(dev->clk_id);
-    rcc_reset_dev(dev->clk_id);
-}
-
-/**
- * Initialize and reset all available GPIO devices.
- */
-void gpio_init_all(void) {
-    gpio_init(GPIOA);
-    gpio_init(GPIOB);
-    gpio_init(GPIOC);
-    gpio_init(GPIOD);
-#ifdef STM32_HIGH_DENSITY
-    gpio_init(GPIOE);
-    gpio_init(GPIOF);
-    gpio_init(GPIOG);
-#endif
-}
-
-/**
- * Set the mode of a GPIO pin.
- *
- * @param dev GPIO device.
- * @param pin Pin on the device whose mode to set, 0--15.
- * @param mode General purpose or alternate function mode to set the pin to.
- * @see gpio_pin_mode
- */
-void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode) {
-    gpio_reg_map *regs = dev->regs;
-    __io uint32 *cr = &regs->CRL + (pin >> 3);
-    uint32 shift = (pin & 0x7) * 4;
-    uint32 tmp = *cr;
-
-    tmp &= ~(0xF << shift);
-    tmp |= (mode == GPIO_INPUT_PU ? GPIO_INPUT_PD : mode) << shift;
-    *cr = tmp;
-
-    if (mode == GPIO_INPUT_PD) {
-        regs->ODR &= ~BIT(pin);
-    } else if (mode == GPIO_INPUT_PU) {
-        regs->ODR |= BIT(pin);
-    }
-}
-
-/*
- * AFIO
- */
-
-/**
- * @brief Initialize the AFIO clock, and reset the AFIO registers.
- */
-void afio_init(void) {
-    rcc_clk_enable(RCC_AFIO);
-    rcc_reset_dev(RCC_AFIO);
-}
-
-#define AFIO_EXTI_SEL_MASK 0xF
-
-/**
- * @brief Select a source input for an external interrupt.
- *
- * @param exti      External interrupt.
- * @param gpio_port Port which contains pin to use as source input.
- * @see afio_exti_num
- * @see afio_exti_port
- */
-void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port) {
-    __io uint32 *exti_cr = &AFIO_BASE->EXTICR1 + exti / 4;
-    uint32 shift = 4 * (exti % 4);
-    uint32 cr = *exti_cr;
-
-    cr &= ~(AFIO_EXTI_SEL_MASK << shift);
-    cr |= gpio_port << shift;
-    *exti_cr = cr;
-}
-
-/**
- * @brief Perform an alternate function remap.
- * @param remapping Remapping to perform.
- */
-void afio_remap(afio_remap_peripheral remapping) {
-    if (remapping & AFIO_REMAP_USE_MAPR2) {
-        remapping &= ~AFIO_REMAP_USE_MAPR2;
-        AFIO_BASE->MAPR2 |= remapping;
-    } else {
-        AFIO_BASE->MAPR |= remapping;
-    }
-}
-
-#endif
diff --git a/STM32F4/cores/maple/libmaple/gpioF1.h b/STM32F4/cores/maple/libmaple/gpioF1.h
deleted file mode 100644
index c69efb417..000000000
--- a/STM32F4/cores/maple/libmaple/gpioF1.h
+++ /dev/null
@@ -1,530 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
-*****************************************************************************/
-
-/**
- *  @file gpio.h
- *
- *  @brief General purpose I/O (GPIO) and Alternate Function I/O
- *         (AFIO) prototypes, defines, and inlined access functions.
- */
-
-#ifndef _GPIO_H_
-#define _GPIO_H_
-
-#include "libmaple.h"
-#include "rcc.h"
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-/*
- * GPIO register maps and devices
- */
-
-/** GPIO register map type */
-typedef struct gpio_reg_map {
-    __io uint32 CRL;      /**< Port configuration register low */
-    __io uint32 CRH;      /**< Port configuration register high */
-    __io uint32 IDR;      /**< Port input data register */
-    __io uint32 ODR;      /**< Port output data register */
-    __io uint32 BSRR;     /**< Port bit set/reset register */
-    __io uint32 BRR;      /**< Port bit reset register */
-    __io uint32 LCKR;     /**< Port configuration lock register */
-} gpio_reg_map;
-
-/**
- * @brief External interrupt line port selector.
- *
- * Used to determine which GPIO port to map an external interrupt line
- * onto. */
-/* (See AFIO sections, below) */
-typedef enum afio_exti_port {
-    AFIO_EXTI_PA,               /**< Use port A (PAx) pin. */
-    AFIO_EXTI_PB,               /**< Use port B (PBx) pin. */
-    AFIO_EXTI_PC,               /**< Use port C (PCx) pin. */
-    AFIO_EXTI_PD,               /**< Use port D (PDx) pin. */
-#ifdef STM32_HIGH_DENSITY
-    AFIO_EXTI_PE,               /**< Use port E (PEx) pin. */
-    AFIO_EXTI_PF,               /**< Use port F (PFx) pin. */
-    AFIO_EXTI_PG,               /**< Use port G (PGx) pin. */
-#endif
-} afio_exti_port;
-
-/** GPIO device type */
-typedef struct gpio_dev {
-    gpio_reg_map *regs;       /**< Register map */
-    rcc_clk_id clk_id;        /**< RCC clock information */
-    afio_exti_port exti_port; /**< AFIO external interrupt port value */
-} gpio_dev;
-
-extern gpio_dev gpioa;
-extern gpio_dev* const GPIOA;
-extern gpio_dev gpiob;
-extern gpio_dev* const GPIOB;
-extern gpio_dev gpioc;
-extern gpio_dev* const GPIOC;
-extern gpio_dev gpiod;
-extern gpio_dev* const GPIOD;
-#ifdef STM32_HIGH_DENSITY
-extern gpio_dev gpioe;
-extern gpio_dev* const GPIOE;
-extern gpio_dev gpiof;
-extern gpio_dev* const GPIOF;
-extern gpio_dev gpiog;
-extern gpio_dev* const GPIOG;
-#endif
-
-/** GPIO port A register map base pointer */
-#define GPIOA_BASE                      ((struct gpio_reg_map*)0x40010800)
-/** GPIO port B register map base pointer */
-#define GPIOB_BASE                      ((struct gpio_reg_map*)0x40010C00)
-/** GPIO port C register map base pointer */
-#define GPIOC_BASE                      ((struct gpio_reg_map*)0x40011000)
-/** GPIO port D register map base pointer */
-#define GPIOD_BASE                      ((struct gpio_reg_map*)0x40011400)
-#ifdef STM32_HIGH_DENSITY
-/** GPIO port E register map base pointer */
-#define GPIOE_BASE                      ((struct gpio_reg_map*)0x40011800)
-/** GPIO port F register map base pointer */
-#define GPIOF_BASE                      ((struct gpio_reg_map*)0x40011C00)
-/** GPIO port G register map base pointer */
-#define GPIOG_BASE                      ((struct gpio_reg_map*)0x40012000)
-#endif
-
-/*
- * GPIO register bit definitions
- */
-
-/* Control registers, low and high */
-
-#define GPIO_CR_CNF                     (0x3 << 2)
-#define GPIO_CR_CNF_INPUT_ANALOG        (0x0 << 2)
-#define GPIO_CR_CNF_INPUT_FLOATING      (0x1 << 2)
-#define GPIO_CR_CNF_INPUT_PU_PD         (0x2 << 2)
-#define GPIO_CR_CNF_OUTPUT_PP           (0x0 << 2)
-#define GPIO_CR_CNF_OUTPUT_OD           (0x1 << 2)
-#define GPIO_CR_CNF_AF_OUTPUT_PP        (0x2 << 2)
-#define GPIO_CR_CNF_AF_OUTPUT_OD        (0x3 << 2)
-#define GPIO_CR_MODE                    0x3
-#define GPIO_CR_MODE_INPUT              0x0
-#define GPIO_CR_MODE_OUTPUT_10MHZ       0x1
-#define GPIO_CR_MODE_OUTPUT_2MHZ        0x2
-#define GPIO_CR_MODE_OUTPUT_50MHZ       0x3
-
-/**
- * @brief GPIO Pin modes.
- *
- * These only allow for 50MHZ max output speeds; if you want slower,
- * use direct register access.
- */
-typedef enum gpio_pin_mode {
-    GPIO_OUTPUT_PP = (GPIO_CR_CNF_OUTPUT_PP |
-                      GPIO_CR_MODE_OUTPUT_50MHZ), /**< Output push-pull. */
-    GPIO_OUTPUT_OD = (GPIO_CR_CNF_OUTPUT_OD |
-                      GPIO_CR_MODE_OUTPUT_50MHZ), /**< Output open-drain. */
-    GPIO_AF_OUTPUT_PP = (GPIO_CR_CNF_AF_OUTPUT_PP |
-                         GPIO_CR_MODE_OUTPUT_50MHZ), /**< Alternate function
-                                                        output push-pull. */
-    GPIO_AF_OUTPUT_OD = (GPIO_CR_CNF_AF_OUTPUT_OD |
-                         GPIO_CR_MODE_OUTPUT_50MHZ), /**< Alternate function
-                                                        output open drain. */
-    GPIO_INPUT_ANALOG = (GPIO_CR_CNF_INPUT_ANALOG |
-                         GPIO_CR_MODE_INPUT), /**< Analog input. */
-    GPIO_INPUT_FLOATING = (GPIO_CR_CNF_INPUT_FLOATING |
-                           GPIO_CR_MODE_INPUT), /**< Input floating. */
-    GPIO_INPUT_PD = (GPIO_CR_CNF_INPUT_PU_PD |
-                     GPIO_CR_MODE_INPUT), /**< Input pull-down. */
-    GPIO_AF_INPUT_PD = (GPIO_INPUT_PD), /**< Input pull-down. */
-    GPIO_INPUT_PU /**< Input pull-up. */
-
-
-    /* GPIO_INPUT_PU treated as a special case, for ODR twiddling */
-} gpio_pin_mode;
-
-/*
- * GPIO Convenience routines
- */
-
-void gpio_init(gpio_dev *dev);
-void gpio_init_all(void);
-void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode);
-
-/**
- * @brief Get a GPIO port's corresponding afio_exti_port.
- * @param dev GPIO device whose afio_exti_port to return.
- */
-static inline afio_exti_port gpio_exti_port(gpio_dev *dev) {
-    return dev->exti_port;
-}
-
-/**
- * Set or reset a GPIO pin.
- *
- * Pin must have previously been configured to output mode.
- *
- * @param dev GPIO device whose pin to set.
- * @param pin Pin on to set or reset
- * @param val If true, set the pin.  If false, reset the pin.
- */
-static inline void gpio_write_bit(gpio_dev *dev, uint8 pin, uint8 val) {
-    if (val) {
-        dev->regs->BSRR = BIT(pin);
-    } else {
-        dev->regs->BRR = BIT(pin);
-    }
-}
-
-/**
- * Determine whether or not a GPIO pin is set.
- *
- * Pin must have previously been configured to input mode.
- *
- * @param dev GPIO device whose pin to test.
- * @param pin Pin on dev to test.
- * @return True if the pin is set, false otherwise.
- */
-static inline uint32 gpio_read_bit(gpio_dev *dev, uint8 pin) {
-    return dev->regs->IDR & BIT(pin);
-}
-
-/**
- * Toggle a pin configured as output push-pull.
- * @param dev GPIO device.
- * @param pin Pin on dev to toggle.
- */
-static inline void gpio_toggle_bit(gpio_dev *dev, uint8 pin) {
-    dev->regs->ODR = dev->regs->ODR ^ BIT(pin);
-}
-
-/*
- * AFIO register map
- */
-
-/** AFIO register map */
-typedef struct afio_reg_map {
-    __io uint32 EVCR;        /**< Event control register.  */
-    __io uint32 MAPR;        /**< AF remap and debug I/O configuration
-                                register. */
-    __io uint32 EXTICR1;     /**< External interrupt configuration
-                                register 1. */
-    __io uint32 EXTICR2;     /**< External interrupt configuration
-                                register 2. */
-    __io uint32 EXTICR3;     /**< External interrupt configuration
-                                register 3. */
-    __io uint32 EXTICR4;     /**< External interrupt configuration
-                                register 4. */
-    __io uint32 MAPR2;       /**< AF remap and debug I/O configuration
-                                register 2. */
-} afio_reg_map;
-
-/** AFIO register map base pointer. */
-#define AFIO_BASE                       ((struct afio_reg_map *)0x40010000)
-
-/*
- * AFIO register bit definitions
- */
-
-/* Event control register */
-
-#define AFIO_EVCR_EVOE                  (0x1 << 7)
-#define AFIO_EVCR_PORT_PA               (0x0 << 4)
-#define AFIO_EVCR_PORT_PB               (0x1 << 4)
-#define AFIO_EVCR_PORT_PC               (0x2 << 4)
-#define AFIO_EVCR_PORT_PD               (0x3 << 4)
-#define AFIO_EVCR_PORT_PE               (0x4 << 4)
-#define AFIO_EVCR_PIN_0                 0x0
-#define AFIO_EVCR_PIN_1                 0x1
-#define AFIO_EVCR_PIN_2                 0x2
-#define AFIO_EVCR_PIN_3                 0x3
-#define AFIO_EVCR_PIN_4                 0x4
-#define AFIO_EVCR_PIN_5                 0x5
-#define AFIO_EVCR_PIN_6                 0x6
-#define AFIO_EVCR_PIN_7                 0x7
-#define AFIO_EVCR_PIN_8                 0x8
-#define AFIO_EVCR_PIN_9                 0x9
-#define AFIO_EVCR_PIN_10                0xA
-#define AFIO_EVCR_PIN_11                0xB
-#define AFIO_EVCR_PIN_12                0xC
-#define AFIO_EVCR_PIN_13                0xD
-#define AFIO_EVCR_PIN_14                0xE
-#define AFIO_EVCR_PIN_15                0xF
-
-/* AF remap and debug I/O configuration register */
-
-#define AFIO_MAPR_SWJ_CFG                      (0x7 << 24)
-#define AFIO_MAPR_SWJ_CFG_FULL_SWJ             (0x0 << 24)
-#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST    (0x1 << 24)
-#define AFIO_MAPR_SWJ_CFG_NO_JTAG_SW           (0x2 << 24)
-#define AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW        (0x4 << 24)
-#define AFIO_MAPR_ADC2_ETRGREG_REMAP           BIT(20)
-#define AFIO_MAPR_ADC2_ETRGINJ_REMAP           BIT(19)
-#define AFIO_MAPR_ADC1_ETRGREG_REMAP           BIT(18)
-#define AFIO_MAPR_ADC1_ETRGINJ_REMAP           BIT(17)
-#define AFIO_MAPR_TIM5CH4_IREMAP               BIT(16)
-#define AFIO_MAPR_PD01_REMAP                   BIT(15)
-#define AFIO_MAPR_CAN_REMAP                    (0x3 << 13)
-#define AFIO_MAPR_CAN_REMAP_NONE               (0x0 << 13)
-#define AFIO_MAPR_CAN_REMAP_PB8_PB9            (0x2 << 13)
-#define AFIO_MAPR_CAN_REMAP_PD0_PD1            (0x3 << 13)
-#define AFIO_MAPR_TIM4_REMAP                   BIT(12)
-#define AFIO_MAPR_TIM3_REMAP                   (0x3 << 10)
-#define AFIO_MAPR_TIM3_REMAP_NONE              (0x0 << 10)
-#define AFIO_MAPR_TIM3_REMAP_PARTIAL           (0x2 << 10)
-#define AFIO_MAPR_TIM3_REMAP_FULL              (0x3 << 10)
-#define AFIO_MAPR_TIM2_REMAP                   (0x3 << 8)
-#define AFIO_MAPR_TIM2_REMAP_NONE              (0x0 << 8)
-#define AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3  (0x1 << 8)
-#define AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11 (0x2 << 8)
-#define AFIO_MAPR_TIM2_REMAP_FULL              (0x3 << 8)
-#define AFIO_MAPR_TIM1_REMAP                   (0x3 << 6)
-#define AFIO_MAPR_TIM1_REMAP_NONE              (0x0 << 6)
-#define AFIO_MAPR_TIM1_REMAP_PARTIAL           (0x1 << 6)
-#define AFIO_MAPR_TIM1_REMAP_FULL              (0x3 << 6)
-#define AFIO_MAPR_USART3_REMAP                 (0x3 << 4)
-#define AFIO_MAPR_USART3_REMAP_NONE            (0x0 << 4)
-#define AFIO_MAPR_USART3_REMAP_PARTIAL         (0x1 << 4)
-#define AFIO_MAPR_USART3_REMAP_FULL            (0x3 << 4)
-#define AFIO_MAPR_USART2_REMAP                 BIT(3)
-#define AFIO_MAPR_USART1_REMAP                 BIT(2)
-#define AFIO_MAPR_I2C1_REMAP                   BIT(1)
-#define AFIO_MAPR_SPI1_REMAP                   BIT(0)
-
-/* External interrupt configuration register 1 */
-
-#define AFIO_EXTICR1_EXTI3              (0xF << 12)
-#define AFIO_EXTICR1_EXTI3_PA           (0x0 << 12)
-#define AFIO_EXTICR1_EXTI3_PB           (0x1 << 12)
-#define AFIO_EXTICR1_EXTI3_PC           (0x2 << 12)
-#define AFIO_EXTICR1_EXTI3_PD           (0x3 << 12)
-#define AFIO_EXTICR1_EXTI3_PE           (0x4 << 12)
-#define AFIO_EXTICR1_EXTI3_PF           (0x5 << 12)
-#define AFIO_EXTICR1_EXTI3_PG           (0x6 << 12)
-#define AFIO_EXTICR1_EXTI2              (0xF << 8)
-#define AFIO_EXTICR1_EXTI2_PA           (0x0 << 8)
-#define AFIO_EXTICR1_EXTI2_PB           (0x1 << 8)
-#define AFIO_EXTICR1_EXTI2_PC           (0x2 << 8)
-#define AFIO_EXTICR1_EXTI2_PD           (0x3 << 8)
-#define AFIO_EXTICR1_EXTI2_PE           (0x4 << 8)
-#define AFIO_EXTICR1_EXTI2_PF           (0x5 << 8)
-#define AFIO_EXTICR1_EXTI2_PG           (0x6 << 8)
-#define AFIO_EXTICR1_EXTI1              (0xF << 4)
-#define AFIO_EXTICR1_EXTI1_PA           (0x0 << 4)
-#define AFIO_EXTICR1_EXTI1_PB           (0x1 << 4)
-#define AFIO_EXTICR1_EXTI1_PC           (0x2 << 4)
-#define AFIO_EXTICR1_EXTI1_PD           (0x3 << 4)
-#define AFIO_EXTICR1_EXTI1_PE           (0x4 << 4)
-#define AFIO_EXTICR1_EXTI1_PF           (0x5 << 4)
-#define AFIO_EXTICR1_EXTI1_PG           (0x6 << 4)
-#define AFIO_EXTICR1_EXTI0              0xF
-#define AFIO_EXTICR1_EXTI0_PA           0x0
-#define AFIO_EXTICR1_EXTI0_PB           0x1
-#define AFIO_EXTICR1_EXTI0_PC           0x2
-#define AFIO_EXTICR1_EXTI0_PD           0x3
-#define AFIO_EXTICR1_EXTI0_PE           0x4
-#define AFIO_EXTICR1_EXTI0_PF           0x5
-#define AFIO_EXTICR1_EXTI0_PG           0x6
-
-/* External interrupt configuration register 2 */
-
-#define AFIO_EXTICR2_EXTI7              (0xF << 12)
-#define AFIO_EXTICR2_EXTI7_PA           (0x0 << 12)
-#define AFIO_EXTICR2_EXTI7_PB           (0x1 << 12)
-#define AFIO_EXTICR2_EXTI7_PC           (0x2 << 12)
-#define AFIO_EXTICR2_EXTI7_PD           (0x3 << 12)
-#define AFIO_EXTICR2_EXTI7_PE           (0x4 << 12)
-#define AFIO_EXTICR2_EXTI7_PF           (0x5 << 12)
-#define AFIO_EXTICR2_EXTI7_PG           (0x6 << 12)
-#define AFIO_EXTICR2_EXTI6              (0xF << 8)
-#define AFIO_EXTICR2_EXTI6_PA           (0x0 << 8)
-#define AFIO_EXTICR2_EXTI6_PB           (0x1 << 8)
-#define AFIO_EXTICR2_EXTI6_PC           (0x2 << 8)
-#define AFIO_EXTICR2_EXTI6_PD           (0x3 << 8)
-#define AFIO_EXTICR2_EXTI6_PE           (0x4 << 8)
-#define AFIO_EXTICR2_EXTI6_PF           (0x5 << 8)
-#define AFIO_EXTICR2_EXTI6_PG           (0x6 << 8)
-#define AFIO_EXTICR2_EXTI5              (0xF << 4)
-#define AFIO_EXTICR2_EXTI5_PA           (0x0 << 4)
-#define AFIO_EXTICR2_EXTI5_PB           (0x1 << 4)
-#define AFIO_EXTICR2_EXTI5_PC           (0x2 << 4)
-#define AFIO_EXTICR2_EXTI5_PD           (0x3 << 4)
-#define AFIO_EXTICR2_EXTI5_PE           (0x4 << 4)
-#define AFIO_EXTICR2_EXTI5_PF           (0x5 << 4)
-#define AFIO_EXTICR2_EXTI5_PG           (0x6 << 4)
-#define AFIO_EXTICR2_EXTI4              0xF
-#define AFIO_EXTICR2_EXTI4_PA           0x0
-#define AFIO_EXTICR2_EXTI4_PB           0x1
-#define AFIO_EXTICR2_EXTI4_PC           0x2
-#define AFIO_EXTICR2_EXTI4_PD           0x3
-#define AFIO_EXTICR2_EXTI4_PE           0x4
-#define AFIO_EXTICR2_EXTI4_PF           0x5
-#define AFIO_EXTICR2_EXTI4_PG           0x6
-
-/* AF remap and debug I/O configuration register 2 */
-
-#define AFIO_MAPR2_FSMC_NADV            BIT(10)
-#define AFIO_MAPR2_TIM14_REMAP          BIT(9)
-#define AFIO_MAPR2_TIM13_REMAP          BIT(8)
-#define AFIO_MAPR2_TIM11_REMAP          BIT(7)
-#define AFIO_MAPR2_TIM10_REMAP          BIT(6)
-#define AFIO_MAPR2_TIM9_REMAP           BIT(5)
-
-/*
- * AFIO convenience routines
- */
-
-void afio_init(void);
-
-/**
- * External interrupt line numbers.
- */
-typedef enum afio_exti_num {
-    AFIO_EXTI_0,                /**< External interrupt line 0. */
-    AFIO_EXTI_1,                /**< External interrupt line 1. */
-    AFIO_EXTI_2,                /**< External interrupt line 2. */
-    AFIO_EXTI_3,                /**< External interrupt line 3. */
-    AFIO_EXTI_4,                /**< External interrupt line 4. */
-    AFIO_EXTI_5,                /**< External interrupt line 5. */
-    AFIO_EXTI_6,                /**< External interrupt line 6. */
-    AFIO_EXTI_7,                /**< External interrupt line 7. */
-    AFIO_EXTI_8,                /**< External interrupt line 8. */
-    AFIO_EXTI_9,                /**< External interrupt line 9. */
-    AFIO_EXTI_10,               /**< External interrupt line 10. */
-    AFIO_EXTI_11,               /**< External interrupt line 11. */
-    AFIO_EXTI_12,               /**< External interrupt line 12. */
-    AFIO_EXTI_13,               /**< External interrupt line 13. */
-    AFIO_EXTI_14,               /**< External interrupt line 14. */
-    AFIO_EXTI_15,               /**< External interrupt line 15. */
-} afio_exti_num;
-
-void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port);
-
-/* HACK: Use upper bit to denote MAPR2, Bit 31 is reserved and
- * not used in either MAPR or MAPR2 */
-#define AFIO_REMAP_USE_MAPR2            (1 << 31)
-
-/**
- * @brief Available peripheral remaps.
- * @see afio_remap()
- */
-typedef enum afio_remap_peripheral {
-    AFIO_REMAP_ADC2_ETRGREG  = AFIO_MAPR_ADC2_ETRGREG_REMAP, /**<
-        ADC 2 external trigger regular conversion remapping */
-    AFIO_REMAP_ADC2_ETRGINJ  = AFIO_MAPR_ADC2_ETRGINJ_REMAP, /**<
-        ADC 2 external trigger injected conversion remapping */
-    AFIO_REMAP_ADC1_ETRGREG  = AFIO_MAPR_ADC1_ETRGREG_REMAP, /**<
-        ADC 1 external trigger regular conversion remapping */
-    AFIO_REMAP_ADC1_ETRGINJ  = AFIO_MAPR_ADC1_ETRGINJ_REMAP, /**<
-        ADC 1 external trigger injected conversion remapping */
-    AFIO_REMAP_TIM5CH4_I     = AFIO_MAPR_TIM5CH4_IREMAP, /**<
-        Timer 5 channel 4 internal remapping */
-    AFIO_REMAP_PD01          = AFIO_MAPR_PD01_REMAP, /**<
-        Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
-    AFIO_REMAP_CAN_1         = AFIO_MAPR_CAN_REMAP_PB8_PB9, /**<
-        CAN alternate function remapping 1 (RX on PB8, TX on PB9) */
-    AFIO_REMAP_CAN_2         = AFIO_MAPR_CAN_REMAP_PD0_PD1, /**<
-        CAN alternate function remapping 2 (RX on PD0, TX on PD1) */
-    AFIO_REMAP_TIM4          = AFIO_MAPR_TIM4_REMAP, /**<
-        Timer 4 remapping */
-    AFIO_REMAP_TIM3_PARTIAL  = AFIO_MAPR_TIM3_REMAP_PARTIAL, /**<
-        Timer 3 partial remapping */
-    AFIO_REMAP_TIM3_FULL      = AFIO_MAPR_TIM3_REMAP_FULL, /**<
-        Timer 3 full remapping */
-    AFIO_REMAP_TIM2_PARTIAL_1 = AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3, /**<
-        Timer 2 partial remapping 1 (CH1 and ETR on PA15, CH2 on PB3, CH3
-        on PA2, CH4 on PA3) */
-    AFIO_REMAP_TIM2_PARTIAL_2 = AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11, /**<
-        Timer 2 partial remapping 2 (CH1 and ETR on PA0, CH2 on PA1, CH3
-        on PB10, CH4 on PB11) */
-    AFIO_REMAP_TIM2_FULL      = AFIO_MAPR_TIM2_REMAP_FULL, /**<
-        Timer 2 full remapping */
-    AFIO_REMAP_USART2        = AFIO_MAPR_USART2_REMAP, /**<
-        USART 2 remapping */
-    AFIO_REMAP_USART1        = AFIO_MAPR_USART1_REMAP, /**<
-        USART 1 remapping */
-    AFIO_REMAP_I2C1          = AFIO_MAPR_I2C1_REMAP, /**<
-        I2C 1 remapping */
-    AFIO_REMAP_SPI1          = AFIO_MAPR_SPI1_REMAP, /**<
-        SPI 1 remapping */
-    AFIO_REMAP_FSMC_NADV     = (AFIO_MAPR2_FSMC_NADV |
-                                AFIO_REMAP_USE_MAPR2), /**<
-        NADV signal not connected */
-    AFIO_REMAP_TIM14         = (AFIO_MAPR2_TIM14_REMAP |
-                                AFIO_REMAP_USE_MAPR2), /**<
-        Timer 14 remapping */
-    AFIO_REMAP_TIM13         = (AFIO_MAPR2_TIM13_REMAP |
-                                AFIO_REMAP_USE_MAPR2), /**<
-        Timer 13 remapping */
-    AFIO_REMAP_TIM11         = (AFIO_MAPR2_TIM11_REMAP |
-                                AFIO_REMAP_USE_MAPR2), /**<
-        Timer 11 remapping */
-    AFIO_REMAP_TIM10         = (AFIO_MAPR2_TIM10_REMAP |
-                                AFIO_REMAP_USE_MAPR2), /**<
-        Timer 10 remapping */
-    AFIO_REMAP_TIM9          = (AFIO_MAPR2_TIM9_REMAP |
-                                AFIO_REMAP_USE_MAPR2) /**<
-        Timer 9 */
-} afio_remap_peripheral;
-
-void afio_remap(afio_remap_peripheral p);
-
-/**
- * @brief Debug port configuration
- *
- * Used to configure the behavior of JTAG and Serial Wire (SW) debug
- * ports and their associated GPIO pins.
- *
- * @see afio_cfg_debug_ports()
- */
-typedef enum afio_debug_cfg {
-    AFIO_DEBUG_FULL_SWJ = AFIO_MAPR_SWJ_CFG_FULL_SWJ, /**<
-                                   Full Serial Wire and JTAG debug */
-    AFIO_DEBUG_FULL_SWJ_NO_NJRST = AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST, /**<
-                                   Full Serial Wire and JTAG, but no NJTRST. */
-    AFIO_DEBUG_SW_ONLY = AFIO_MAPR_SWJ_CFG_NO_JTAG_SW, /**<
-                                   Serial Wire debug only (JTAG-DP disabled,
-                                   SW-DP enabled) */
-    AFIO_DEBUG_NONE = AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW /**<
-                                   No debug; all JTAG and SW pins are free
-                                   for use as GPIOs. */
-} afio_debug_cfg;
-
-/**
- * @brief Enable or disable the JTAG and SW debug ports.
- * @param config Desired debug port configuration
- * @see afio_debug_cfg
- */
-static inline void afio_cfg_debug_ports(afio_debug_cfg config) {
-    __io uint32 *mapr = &AFIO_BASE->MAPR;
-    *mapr = (*mapr & ~AFIO_MAPR_SWJ_CFG) | config;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
diff --git a/STM32F4/cores/maple/libmaple/gpioF2.c b/STM32F4/cores/maple/libmaple/gpioF4.c
similarity index 78%
rename from STM32F4/cores/maple/libmaple/gpioF2.c
rename to STM32F4/cores/maple/libmaple/gpioF4.c
index b04c7e9d6..67d3bea53 100644
--- a/STM32F4/cores/maple/libmaple/gpioF2.c
+++ b/STM32F4/cores/maple/libmaple/gpioF4.c
@@ -24,8 +24,6 @@
  * SOFTWARE.
  *****************************************************************************/
 
- #ifdef STM32F2
- 
 /**
  * @file gpio.c
  * @brief GPIO initialization routine
@@ -38,62 +36,57 @@
  * GPIO devices
  */
 
-gpio_dev gpioa = {
+/** GPIO port A device. */
+const gpio_dev GPIOA = {
     .regs      = GPIOA_BASE,
     .clk_id    = RCC_GPIOA,
     .exti_port = AFIO_EXTI_PA,
 };
-/** GPIO port A device. */
-gpio_dev* const GPIOA = &gpioa;
 
-gpio_dev gpiob = {
+/** GPIO port B device. */
+const gpio_dev GPIOB = {
     .regs      = GPIOB_BASE,
     .clk_id    = RCC_GPIOB,
     .exti_port = AFIO_EXTI_PB,
 };
-/** GPIO port B device. */
-gpio_dev* const GPIOB = &gpiob;
 
-gpio_dev gpioc = {
+/** GPIO port C device. */
+const gpio_dev GPIOC = {
     .regs      = GPIOC_BASE,
     .clk_id    = RCC_GPIOC,
     .exti_port = AFIO_EXTI_PC,
 };
-/** GPIO port C device. */
-gpio_dev* const GPIOC = &gpioc;
 
-gpio_dev gpiod = {
+/** GPIO port D device. */
+const gpio_dev GPIOD = {
     .regs      = GPIOD_BASE,
     .clk_id    = RCC_GPIOD,
     .exti_port = AFIO_EXTI_PD,
 };
-/** GPIO port D device. */
-gpio_dev* const GPIOD = &gpiod;
 
 #ifdef STM32_HIGH_DENSITY
-gpio_dev gpioe = {
+/** GPIO port E device. */
+const gpio_dev GPIOE = {
     .regs      = GPIOE_BASE,
     .clk_id    = RCC_GPIOE,
     .exti_port = AFIO_EXTI_PE,
 };
-/** GPIO port E device. */
-gpio_dev* const GPIOE = &gpioe;
 
-gpio_dev gpiof = {
+ #if 0 // not available on LQFP 100 package
+/** GPIO port F device. */
+const gpio_dev GPIOF = {
     .regs      = GPIOF_BASE,
     .clk_id    = RCC_GPIOF,
     .exti_port = AFIO_EXTI_PF,
 };
-/** GPIO port F device. */
-gpio_dev* const GPIOF = &gpiof;
 
-gpio_dev gpiog = {
+/** GPIO port G device. */
+const gpio_dev GPIOG = {
     .regs      = GPIOG_BASE,
     .clk_id    = RCC_GPIOG,
     .exti_port = AFIO_EXTI_PG,
 };
-/** GPIO port G device. */
-gpio_dev* const GPIOG = &gpiog;
+#endif
 #endif
 
 /*
@@ -107,7 +100,7 @@ gpio_dev* const GPIOG = &gpiog;
  *
  * @param dev GPIO device to initialize.
  */
-void gpio_init(gpio_dev *dev) {
+void gpio_init(const gpio_dev *dev) {
     rcc_clk_enable(dev->clk_id);
     rcc_reset_dev(dev->clk_id);
 }
@@ -116,15 +109,17 @@ void gpio_init(gpio_dev *dev) {
  * Initialize and reset all available GPIO devices.
  */
 void gpio_init_all(void) {
-    gpio_init(GPIOA);
-    gpio_init(GPIOB);
-    gpio_init(GPIOC);
-    gpio_init(GPIOD);
+    gpio_init(&GPIOA);
+    gpio_init(&GPIOB);
+    gpio_init(&GPIOC);
+    gpio_init(&GPIOD);
 
 #ifdef STM32_HIGH_DENSITY
-    gpio_init(GPIOE);
-    gpio_init(GPIOF);
-    gpio_init(GPIOG);
+	gpio_init(&GPIOE);
+  #if 0 // not available on LQFP 100 package
+	gpio_init(GPIOF);
+	gpio_init(GPIOG);
+  #endif // not available on LQFP 100 package
 #endif
 
 #ifdef ARDUINO_STM32F4_NETDUINO2PLUS
@@ -148,16 +143,17 @@ void gpio_init_all(void) {
  * @param mode General purpose or alternate function mode to set the pin to.
  * @see gpio_pin_mode
  */
-void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode) {
-    gpio_reg_map *regs = dev->regs;
+void gpio_set_mode(uint8_t io_pin, gpio_pin_mode mode) {
+    gpio_reg_map *regs = (PIN_MAP[io_pin].gpio_device)->regs;
+	uint8_t pin = io_pin&0x0f;
 
 	//regs->AFR[pin/8] = (regs->AFR[pin/8] & ~(15 << (4*(pin&7)))) | (((mode >> 8) & 15) << (4*(pin&7)));
 	//gpio_set_af_mode(dev, pin, mode>>8);
 
-    regs->MODER      = (regs->MODER      & ~( 3 << (2*pin)))     | (((mode >> 0) & 3)  << (2*pin));
-    regs->PUPDR      = (regs->PUPDR      & ~( 3 << (2*pin)))     | (((mode >> 2) & 3)  << (2*pin));
-    regs->OSPEEDR    = (regs->OSPEEDR    & ~( 3 << (2*pin)))     | (((mode >> 4) & 3)  << (2*pin));
-    regs->OTYPER     = (regs->OTYPER     & ~( 1 << (1*pin)))     | (((mode >> 6) & 1)  << (1*pin));
+    regs->MODER      = (regs->MODER      & ~( 3 << (pin<<1)))     | (((mode >> 0) & 3)  << (pin<<1));
+    regs->PUPDR      = (regs->PUPDR      & ~( 3 << (pin<<1)))     | (((mode >> 2) & 3)  << (pin<<1));
+    regs->OSPEEDR    = (regs->OSPEEDR    & ~( 3 << (pin<<1)))     | (((mode >> 4) & 3)  << (pin<<1));
+    regs->OTYPER     = (regs->OTYPER     & ~( 1 << (pin<<0)))     | (((mode >> 6) & 1)  << (pin<<0));
 }
 
 /**
@@ -168,10 +164,11 @@ void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode) {
  * @param mode alternate function mode to set the pin to.
  * @see gpio_pin_mode
  */
-void gpio_set_af_mode(gpio_dev *dev, uint8 pin, int mode) {
-    gpio_reg_map *regs = dev->regs;
+void gpio_set_af_mode(uint8_t io_pin, int mode) {
+    gpio_reg_map *regs = (PIN_MAP[io_pin].gpio_device)->regs;
+	uint8_t pin = io_pin&0x0F;
 
-	regs->AFR[pin/8] = (regs->AFR[pin/8] & ~(15 << (4*(pin&7)))) | (((mode >> 0) & 15) << (4*(pin&7)));
+	regs->AFR[pin>>3] = (regs->AFR[pin>>3] & ~(15 << ((pin&7)<<2))) | (((mode >> 0) & 15) << ((pin&7)<<2));
 }
 
 /*
@@ -220,5 +217,3 @@ void afio_remap(afio_remap_peripheral remapping) {
     }
 }
 #endif
-
-#endif
diff --git a/STM32F4/cores/maple/libmaple/gpioF2.h b/STM32F4/cores/maple/libmaple/gpio_def.h
similarity index 90%
rename from STM32F4/cores/maple/libmaple/gpioF2.h
rename to STM32F4/cores/maple/libmaple/gpio_def.h
index 91bd67be3..cd1fb3843 100644
--- a/STM32F4/cores/maple/libmaple/gpioF2.h
+++ b/STM32F4/cores/maple/libmaple/gpio_def.h
@@ -31,8 +31,8 @@
  *         (AFIO) prototypes, defines, and inlined access functions.
  */
 
-#ifndef _GPIO_H_
-#define _GPIO_H_
+#ifndef _GPIO_DEF_H_
+#define _GPIO_DEF_H_
 
 #include "libmaple.h"
 #include "rcc.h"
@@ -74,11 +74,14 @@ typedef enum afio_exti_port {
     AFIO_EXTI_PD,               /**< Use port D (PDx) pin. */
 #ifdef STM32_HIGH_DENSITY
     AFIO_EXTI_PE,               /**< Use port E (PEx) pin. */
+ #if 0 // not available on LQFP 100 package
     AFIO_EXTI_PF,               /**< Use port F (PFx) pin. */
     AFIO_EXTI_PG,               /**< Use port G (PGx) pin. */
+ #endif // not available on LQFP 100 package
 #endif
 } afio_exti_port;
 
+
 /** GPIO device type */
 typedef struct gpio_dev {
     gpio_reg_map *regs;       /**< Register map */
@@ -86,21 +89,18 @@ typedef struct gpio_dev {
     afio_exti_port exti_port; /**< AFIO external interrupt port value */
 } gpio_dev;
 
-extern gpio_dev gpioa;
-extern gpio_dev* const GPIOA;
-extern gpio_dev gpiob;
-extern gpio_dev* const GPIOB;
-extern gpio_dev gpioc;
-extern gpio_dev* const GPIOC;
-extern gpio_dev gpiod;
-extern gpio_dev* const GPIOD;
+extern const gpio_dev GPIOA;
+extern const gpio_dev GPIOB;
+extern const gpio_dev GPIOC;
+extern const gpio_dev GPIOD;
 #ifdef STM32_HIGH_DENSITY
-extern gpio_dev gpioe;
-extern gpio_dev* const GPIOE;
+extern const gpio_dev GPIOE;
+ #if 0 // not available on LQFP 100 package
 extern gpio_dev gpiof;
 extern gpio_dev* const GPIOF;
 extern gpio_dev gpiog;
 extern gpio_dev* const GPIOG;
+ #endif // not available on LQFP 100 package
 #endif
 
 /** GPIO port register map base pointer */
@@ -110,8 +110,10 @@ extern gpio_dev* const GPIOG;
 #define GPIOD_BASE                      ((struct gpio_reg_map*)0x40020C00)
 #ifdef STM32_HIGH_DENSITY
 #define GPIOE_BASE                      ((struct gpio_reg_map*)0x40021000)
+ #if 0 // not available on LQFP 100 package
 #define GPIOF_BASE                      ((struct gpio_reg_map*)0x40021400)
 #define GPIOG_BASE                      ((struct gpio_reg_map*)0x40021800)
+ #endif // not available on LQFP 100 package
 #endif
 
 /*
@@ -190,61 +192,6 @@ typedef enum gpio_pin_mode {
 	GPIO_BIGNUMBER = 0xfff
 } gpio_pin_mode;
 
-/*
- * GPIO Convenience routines
- */
-
-void gpio_init(gpio_dev *dev);
-void gpio_init_all(void);
-void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode);
-void gpio_set_af_mode(gpio_dev *dev, uint8 pin, int mode);
-
-/**
- * @brief Get a GPIO port's corresponding afio_exti_port.
- * @param dev GPIO device whose afio_exti_port to return.
- */
-static inline afio_exti_port gpio_exti_port(gpio_dev *dev) {
-    return dev->exti_port;
-}
-
-/**
- * Set or reset a GPIO pin.
- *
- * Pin must have previously been configured to output mode.
- *
- * @param dev GPIO device whose pin to set.
- * @param pin Pin on to set or reset
- * @param val If true, set the pin.  If false, reset the pin.
- */
-static inline void gpio_write_bit(gpio_dev *dev, uint8 pin, uint8 val) {
-    if (val) {
-        dev->regs->BSRRL = BIT(pin);
-    } else {
-        dev->regs->BSRRH = BIT(pin);
-    }
-}
-
-/**
- * Determine whether or not a GPIO pin is set.
- *
- * Pin must have previously been configured to input mode.
- *
- * @param dev GPIO device whose pin to test.
- * @param pin Pin on dev to test.
- * @return True if the pin is set, false otherwise.
- */
-static inline uint32 gpio_read_bit(gpio_dev *dev, uint8 pin) {
-    return dev->regs->IDR & BIT(pin);
-}
-
-/**
- * Toggle a pin configured as output push-pull.
- * @param dev GPIO device.
- * @param pin Pin on dev to toggle.
- */
-static inline void gpio_toggle_bit(gpio_dev *dev, uint8 pin) {
-    dev->regs->ODR = dev->regs->ODR ^ BIT(pin);
-}
 
 /*
  * AFIO register map
@@ -532,15 +479,6 @@ typedef enum afio_debug_cfg {
                                    for use as GPIOs. */
 } afio_debug_cfg;
 
-/**
- * @brief Enable or disable the JTAG and SW debug ports.
- * @param config Desired debug port configuration
- * @see afio_debug_cfg
- */
-static inline void afio_cfg_debug_ports(afio_debug_cfg config) {
-    //__io uint32 *mapr = &AFIO_BASE->MAPR;
-    //*mapr = (*mapr & ~AFIO_MAPR_SWJ_CFG) | config;
-}
 
 #ifdef __cplusplus
 }
diff --git a/STM32F4/cores/maple/libmaple/i2c.c b/STM32F4/cores/maple/libmaple/i2c.c
index e3f3199bc..a582ed056 100644
--- a/STM32F4/cores/maple/libmaple/i2c.c
+++ b/STM32F4/cores/maple/libmaple/i2c.c
@@ -41,9 +41,9 @@
 
 static i2c_dev i2c_dev1 = {
     .regs         = I2C1_BASE,
-    .gpio_port    = &gpiob,
-    .sda_pin      = 7,
-    .scl_pin      = 6,
+    //.gpio_port    = &gpiob,
+    .sda_pin      = PB7,
+    .scl_pin      = PB6,
     .clk_id       = RCC_I2C1,
     .ev_nvic_line = NVIC_I2C1_EV,
     .er_nvic_line = NVIC_I2C1_ER,
@@ -54,9 +54,9 @@ i2c_dev* const I2C1 = &i2c_dev1;
 
 static i2c_dev i2c_dev2 = {
     .regs         = I2C2_BASE,
-    .gpio_port    = &gpiob,
-    .sda_pin      = 11,
-    .scl_pin      = 10,
+    //.gpio_port    = &gpiob,
+    .sda_pin      = PB11,
+    .scl_pin      = PB10,
     .clk_id       = RCC_I2C2,
     .ev_nvic_line = NVIC_I2C2_EV,
     .er_nvic_line = NVIC_I2C2_ER,
@@ -336,38 +336,38 @@ void __irq_i2c2_er(void) {
  */
 void i2c_bus_reset(const i2c_dev *dev) {
     /* Release both lines */
-    gpio_write_bit(dev->gpio_port, dev->scl_pin, 1);
-    gpio_write_bit(dev->gpio_port, dev->sda_pin, 1);
-    gpio_set_mode(dev->gpio_port, dev->scl_pin, GPIO_OUTPUT_OD);
-    gpio_set_mode(dev->gpio_port, dev->sda_pin, GPIO_OUTPUT_OD);
+    gpio_set_pin(dev->scl_pin);
+    gpio_set_pin(dev->sda_pin);
+    gpio_set_mode(dev->scl_pin, GPIO_OUTPUT_OD);
+    gpio_set_mode(dev->sda_pin, GPIO_OUTPUT_OD);
 
     /*
      * Make sure the bus is free by clocking it until any slaves release the
      * bus.
      */
-    while (!gpio_read_bit(dev->gpio_port, dev->sda_pin)) {
+    while (!gpio_read_pin(dev->sda_pin)) {
         /* Wait for any clock stretching to finish */
-        while (!gpio_read_bit(dev->gpio_port, dev->scl_pin))
+        while (!gpio_read_pin(dev->scl_pin))
             ;
         delay_us(10);
 
         /* Pull low */
-        gpio_write_bit(dev->gpio_port, dev->scl_pin, 0);
+        gpio_clear_pin(dev->scl_pin);
         delay_us(10);
 
         /* Release high again */
-        gpio_write_bit(dev->gpio_port, dev->scl_pin, 1);
+        gpio_set_pin(dev->scl_pin);
         delay_us(10);
     }
 
     /* Generate start then stop condition */
-    gpio_write_bit(dev->gpio_port, dev->sda_pin, 0);
+    gpio_clear_pin(dev->sda_pin);
     delay_us(10);
-    gpio_write_bit(dev->gpio_port, dev->scl_pin, 0);
+    gpio_clear_pin(dev->scl_pin);
     delay_us(10);
-    gpio_write_bit(dev->gpio_port, dev->scl_pin, 1);
+    gpio_set_pin(dev->scl_pin);
     delay_us(10);
-    gpio_write_bit(dev->gpio_port, dev->sda_pin, 1);
+    gpio_set_pin(dev->sda_pin);
 }
 
 /**
@@ -413,8 +413,8 @@ void i2c_master_enable(i2c_dev *dev, uint32 flags) {
 
     /* Turn on clock and set GPIO modes */
     i2c_init(dev);
-    gpio_set_mode(dev->gpio_port, dev->sda_pin, GPIO_AF_OUTPUT_OD);
-    gpio_set_mode(dev->gpio_port, dev->scl_pin, GPIO_AF_OUTPUT_OD);
+    gpio_set_mode(dev->sda_pin, GPIO_AF_OUTPUT_OD);
+    gpio_set_mode(dev->scl_pin, GPIO_AF_OUTPUT_OD);
 
     /* I2C1 and I2C2 are fed from APB1, clocked at 36MHz */
     i2c_set_input_clk(dev, I2C_CLK);
diff --git a/STM32F4/cores/maple/libmaple/i2c.h b/STM32F4/cores/maple/libmaple/i2c.h
index 4c60ad713..28819a35b 100644
--- a/STM32F4/cores/maple/libmaple/i2c.h
+++ b/STM32F4/cores/maple/libmaple/i2c.h
@@ -78,7 +78,7 @@ typedef struct i2c_msg {
  */
 typedef struct i2c_dev {
     i2c_reg_map *regs;          /**< Register map */
-    gpio_dev *gpio_port;        /**< SDA, SCL pins' GPIO port */
+    //gpio_dev *gpio_port;        /**< SDA, SCL pins' GPIO port */
     uint8 sda_pin;              /**< SDA bit on gpio_port */
     uint8 scl_pin;              /**< SCL bit on gpio_port */
     rcc_clk_id clk_id;          /**< RCC clock information */
diff --git a/STM32F4/cores/maple/libmaple/libmaple.h b/STM32F4/cores/maple/libmaple/libmaple.h
index 10c6c0c00..8360ba390 100644
--- a/STM32F4/cores/maple/libmaple/libmaple.h
+++ b/STM32F4/cores/maple/libmaple/libmaple.h
@@ -32,29 +32,31 @@
 #ifndef _LIBMAPLE_H_
 #define _LIBMAPLE_H_
 
-#include "libmaple_types.h"
-#include "stm32.h"
 #include "util.h"
-#include "delay.h"
 
 /*
  * Where to put usercode, based on space reserved for bootloader.
  *
  * FIXME this has no business being here
  */
+/*
 #if defined(MCU_STM32F103VE) || defined(MCU_STM32F205VE) || defined(MCU_STM32F406VG)
-    /* e.g., Aeroquad32 */
-    #define USER_ADDR_ROM 0x08010000    /* ala42 */
+    // e.g., Aeroquad32
+    #define USER_ADDR_ROM 0x08010000    // ala42
     #define USER_ADDR_RAM 0x20000C00
     #define STACK_TOP     0x20000800
 #elif defined(BOARD_freeflight)
+*/
 #define USER_ADDR_ROM 0x08000000
-#define USER_ADDR_RAM 0x20000000
+#define USER_ADDR_RAM 0x20000C00
 #define STACK_TOP     0x20000800
+/*
 #else
 #define USER_ADDR_ROM 0x08005000
 #define USER_ADDR_RAM 0x20000C00
 #define STACK_TOP     0x20000800
 #endif
+*/
+
 #endif
 
diff --git a/STM32F4/cores/maple/libmaple/libmaple_types.h b/STM32F4/cores/maple/libmaple/libmaple_types.h
index 332ded176..8e765b435 100644
--- a/STM32F4/cores/maple/libmaple/libmaple_types.h
+++ b/STM32F4/cores/maple/libmaple/libmaple_types.h
@@ -33,6 +33,8 @@
 #ifndef _LIBMAPLE_TYPES_H_
 #define _LIBMAPLE_TYPES_H_
 
+#include <inttypes.h>
+
 typedef unsigned char uint8;
 typedef unsigned short uint16;
 typedef unsigned int uint32;
@@ -46,12 +48,15 @@ typedef long long int64;
 typedef void (*voidFuncPtr)(void);
 
 #define __io volatile
-#define __attr_flash __attribute__((section (".USER_FLASH")))
-
-#define __always_inline inline __attribute__((always_inline))
-
+#define __IO volatile
+#ifndef __attr_flash
+  #define __attr_flash __attribute__((section (".USER_FLASH")))
+#endif
+#ifndef __always_inline
+  #define __always_inline inline __attribute__((always_inline))
+#endif
 #ifndef NULL
-#define NULL 0
+  #define NULL 0
 #endif
 
 #endif
diff --git a/STM32F4/cores/maple/libmaple/rcc.h b/STM32F4/cores/maple/libmaple/rcc.h
index 6317cbdb8..75e2d3d7a 100644
--- a/STM32F4/cores/maple/libmaple/rcc.h
+++ b/STM32F4/cores/maple/libmaple/rcc.h
@@ -29,8 +29,5 @@
  * @brief reset and clock control definitions and prototypes
  */
 
-#ifdef STM32F2
-#include "rccF2.h"
-#else
-#include "rccF1.h"
-#endif
+
+#include "rccF4.h"
diff --git a/STM32F4/cores/maple/libmaple/rccF1.c b/STM32F4/cores/maple/libmaple/rccF1.c
deleted file mode 100644
index 9eb56b872..000000000
--- a/STM32F4/cores/maple/libmaple/rccF1.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
- #ifdef STM32F1
- 
-/**
- * @file rcc.c
- * @brief Implements pretty much only the basic clock setup on the
- *        stm32, clock enable/disable and peripheral reset commands.
- */
-
-#include "libmaple.h"
-#include "flash.h"
-#include "rcc.h"
-#include "bitband.h"
-
-#define APB1                            RCC_APB1
-#define APB2                            RCC_APB2
-#define AHB                             RCC_AHB
-
-struct rcc_dev_info {
-    const rcc_clk_domain clk_domain;
-    const uint8 line_num;
-};
-
-/* Device descriptor table, maps rcc_clk_id onto bus and enable/reset
- * register bit numbers. */
-static const struct rcc_dev_info rcc_dev_table[] = {
-    [RCC_GPIOA]  = { .clk_domain = APB2, .line_num = 2 },
-    [RCC_GPIOB]  = { .clk_domain = APB2, .line_num = 3 },
-    [RCC_GPIOC]  = { .clk_domain = APB2, .line_num = 4 },
-    [RCC_GPIOD]  = { .clk_domain = APB2, .line_num = 5 },
-    [RCC_AFIO]   = { .clk_domain = APB2, .line_num = 0 },
-    [RCC_ADC1]   = { .clk_domain = APB2, .line_num = 9 },
-    [RCC_ADC2]   = { .clk_domain = APB2, .line_num = 10 },
-    [RCC_ADC3]   = { .clk_domain = APB2, .line_num = 15 },
-    [RCC_USART1] = { .clk_domain = APB2, .line_num = 14 },
-    [RCC_USART2] = { .clk_domain = APB1, .line_num = 17 },
-    [RCC_USART3] = { .clk_domain = APB1, .line_num = 18 },
-    [RCC_TIMER1] = { .clk_domain = APB2, .line_num = 11 },
-    [RCC_TIMER2] = { .clk_domain = APB1, .line_num = 0 },
-    [RCC_TIMER3] = { .clk_domain = APB1, .line_num = 1 },
-    [RCC_TIMER4] = { .clk_domain = APB1, .line_num = 2 },
-    [RCC_SPI1]   = { .clk_domain = APB2, .line_num = 12 },
-    [RCC_SPI2]   = { .clk_domain = APB1, .line_num = 14 },
-    [RCC_DMA1]   = { .clk_domain = AHB,  .line_num = 0 },
-    [RCC_PWR]    = { .clk_domain = APB1, .line_num = 28},
-    [RCC_BKP]    = { .clk_domain = APB1, .line_num = 27},
-    [RCC_I2C1]   = { .clk_domain = APB1, .line_num = 21 },
-    [RCC_I2C2]   = { .clk_domain = APB1, .line_num = 22 },
-    [RCC_CRC]    = { .clk_domain = AHB,  .line_num = 6},
-    [RCC_FLITF]  = { .clk_domain = AHB,  .line_num = 4},
-    [RCC_SRAM]   = { .clk_domain = AHB,  .line_num = 2},
-#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
-    [RCC_GPIOE]  = { .clk_domain = APB2, .line_num = 6 },
-    [RCC_GPIOF]  = { .clk_domain = APB2, .line_num = 7 },
-    [RCC_GPIOG]  = { .clk_domain = APB2, .line_num = 8 },
-    [RCC_UART4]  = { .clk_domain = APB1, .line_num = 19 },
-    [RCC_UART5]  = { .clk_domain = APB1, .line_num = 20 },
-    [RCC_TIMER5] = { .clk_domain = APB1, .line_num = 3 },
-    [RCC_TIMER6] = { .clk_domain = APB1, .line_num = 4 },
-    [RCC_TIMER7] = { .clk_domain = APB1, .line_num = 5 },
-    [RCC_TIMER8] = { .clk_domain = APB2, .line_num = 13 },
-    [RCC_FSMC]   = { .clk_domain = AHB,  .line_num = 8 },
-    [RCC_DAC]    = { .clk_domain = APB1, .line_num = 29 },
-    [RCC_DMA2]   = { .clk_domain = AHB,  .line_num = 1 },
-    [RCC_SDIO]   = { .clk_domain = AHB,  .line_num = 10 },
-    [RCC_SPI3]   = { .clk_domain = APB1, .line_num = 15 },
-#endif
-#ifdef STM32_XL_DENSITY
-    [RCC_TIMER9]  = { .clk_domain = APB2, .line_num = 19 },
-    [RCC_TIMER10] = { .clk_domain = APB2, .line_num = 20 },
-    [RCC_TIMER11] = { .clk_domain = APB2, .line_num = 21 },
-    [RCC_TIMER12] = { .clk_domain = APB1, .line_num = 6 },
-    [RCC_TIMER13] = { .clk_domain = APB1, .line_num = 7 },
-    [RCC_TIMER14] = { .clk_domain = APB1, .line_num = 8 },
-#endif
-};
-
-/**
- * @brief Initialize the clock control system. Initializes the system
- *        clock source to use the PLL driven by an external oscillator
- * @param sysclk_src system clock source, must be PLL
- * @param pll_src pll clock source, must be HSE
- * @param pll_mul pll multiplier
- */
-void rcc_clk_init(rcc_sysclk_src sysclk_src,
-                  rcc_pllsrc pll_src,
-                  rcc_pll_multiplier pll_mul) {
-    uint32 cfgr = 0;
-    uint32 cr;
-
-    /* Assume that we're going to clock the chip off the PLL, fed by
-     * the HSE */
-    ASSERT(sysclk_src == RCC_CLKSRC_PLL &&
-           pll_src    == RCC_PLLSRC_HSE);
-
-    RCC_BASE->CFGR = pll_src | pll_mul;
-
-    /* Turn on the HSE */
-    cr = RCC_BASE->CR;
-    cr |= RCC_CR_HSEON;
-    RCC_BASE->CR = cr;
-    while (!(RCC_BASE->CR & RCC_CR_HSERDY))
-        ;
-
-    /* Now the PLL */
-    cr |= RCC_CR_PLLON;
-    RCC_BASE->CR = cr;
-    while (!(RCC_BASE->CR & RCC_CR_PLLRDY))
-        ;
-
-    /* Finally, let's switch over to the PLL */
-    cfgr &= ~RCC_CFGR_SW;
-    cfgr |= RCC_CFGR_SW_PLL;
-    RCC_BASE->CFGR = cfgr;
-    while ((RCC_BASE->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL)
-        ;
-}
-
-/**
- * @brief Turn on the clock line on a peripheral
- * @param id Clock ID of the peripheral to turn on.
- */
-void rcc_clk_enable(rcc_clk_id id) {
-    static const __io uint32* enable_regs[] = {
-        [APB1] = &RCC_BASE->APB1ENR,
-        [APB2] = &RCC_BASE->APB2ENR,
-        [AHB] = &RCC_BASE->AHBENR,
-    };
-
-    rcc_clk_domain clk_domain = rcc_dev_clk(id);
-    __io uint32* enr = (__io uint32*)enable_regs[clk_domain];
-    uint8 lnum = rcc_dev_table[id].line_num;
-
-    bb_peri_set_bit(enr, lnum, 1);
-}
-
-/**
- * @brief Reset a peripheral.
- * @param id Clock ID of the peripheral to reset.
- */
-void rcc_reset_dev(rcc_clk_id id) {
-    static const __io uint32* reset_regs[] = {
-        [APB1] = &RCC_BASE->APB1RSTR,
-        [APB2] = &RCC_BASE->APB2RSTR,
-    };
-
-    rcc_clk_domain clk_domain = rcc_dev_clk(id);
-    __io void* addr = (__io void*)reset_regs[clk_domain];
-    uint8 lnum = rcc_dev_table[id].line_num;
-
-    bb_peri_set_bit(addr, lnum, 1);
-    bb_peri_set_bit(addr, lnum, 0);
-}
-
-/**
- * @brief Get a peripheral's clock domain
- * @param id Clock ID of the peripheral whose clock domain to return
- * @return Clock source for the given clock ID
- */
-rcc_clk_domain rcc_dev_clk(rcc_clk_id id) {
-    return rcc_dev_table[id].clk_domain;
-}
-
-/**
- * @brief Get a peripheral's clock domain speed
- * @param id Clock ID of the peripheral whose clock domain speed to return
- * @return Clock speed for the given clock ID
- */
-uint32 rcc_dev_clk_speed(rcc_clk_id id) {
-    static const uint32 rcc_dev_clk_speed_table[] = {
-        [RCC_AHB]  = 72000000,
-        [RCC_APB1] = 36000000,
-        [RCC_APB2] = 72000000
-	  };
-    return rcc_dev_clk_speed_table[rcc_dev_clk(id)];
-}
-
-/**
- * @brief Get a peripheral's timer clock domain speed
- * @param id Clock ID of the peripheral whose clock domain speed to return
- * @return Clock speed for the given clock ID
- */
-uint32 rcc_dev_timer_clk_speed(rcc_clk_id id) {
-    return rcc_dev_clk_speed(RCC_APB2); // 72 MHz for all counter
-}
-
-/**
- * @brief Set the divider on a peripheral prescaler
- * @param prescaler prescaler to set
- * @param divider prescaler divider
- */
-void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider) {
-    static const uint32 masks[] = {
-        [RCC_PRESCALER_AHB] = RCC_CFGR_HPRE,
-        [RCC_PRESCALER_APB1] = RCC_CFGR_PPRE1,
-        [RCC_PRESCALER_APB2] = RCC_CFGR_PPRE2,
-        [RCC_PRESCALER_USB] = RCC_CFGR_USBPRE,
-        [RCC_PRESCALER_ADC] = RCC_CFGR_ADCPRE,
-    };
-
-    uint32 cfgr = RCC_BASE->CFGR;
-    cfgr &= ~masks[prescaler];
-    cfgr |= divider;
-    RCC_BASE->CFGR = cfgr;
-}
-
-
-#endif
diff --git a/STM32F4/cores/maple/libmaple/rccF1.h b/STM32F4/cores/maple/libmaple/rccF1.h
deleted file mode 100644
index dd79704d8..000000000
--- a/STM32F4/cores/maple/libmaple/rccF1.h
+++ /dev/null
@@ -1,572 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file rcc.h
- * @brief reset and clock control definitions and prototypes
- */
-
-#include "libmaple_types.h"
-
-#ifndef _RCC_H_
-#define _RCC_H_
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-/** RCC register map type */
-typedef struct rcc_reg_map {
-    __io uint32 CR;             /**< Clock control register */
-    __io uint32 CFGR;           /**< Clock configuration register */
-    __io uint32 CIR;            /**< Clock interrupt register */
-    __io uint32 APB2RSTR;       /**< APB2 peripheral reset register */
-    __io uint32 APB1RSTR;       /**< APB1 peripheral reset register */
-    __io uint32 AHBENR;         /**< AHB peripheral clock enable register */
-    __io uint32 APB2ENR;        /**< APB2 peripheral clock enable register */
-    __io uint32 APB1ENR;        /**< APB1 peripheral clock enable register */
-    __io uint32 BDCR;           /**< Backup domain control register */
-    __io uint32 CSR;            /**< Control/status register */
-} rcc_reg_map;
-
-/** RCC register map base pointer */
-#define RCC_BASE                        ((struct rcc_reg_map*)0x40021000)
-
-/*
- * Register bit definitions
- */
-
-/* Clock control register */
-
-#define RCC_CR_PLLRDY_BIT               25
-#define RCC_CR_PLLON_BIT                24
-#define RCC_CR_CSSON_BIT                19
-#define RCC_CR_HSEBYP_BIT               18
-#define RCC_CR_HSERDY_BIT               17
-#define RCC_CR_HSEON_BIT                16
-#define RCC_CR_HSIRDY_BIT               1
-#define RCC_CR_HSION_BIT                0
-
-#define RCC_CR_PLLRDY                   BIT(RCC_CR_PLLRDY_BIT)
-#define RCC_CR_PLLON                    BIT(RCC_CR_PLLON_BIT)
-#define RCC_CR_CSSON                    BIT(RCC_CR_CSSON_BIT)
-#define RCC_CR_HSEBYP                   BIT(RCC_CR_HSEBYP_BIT)
-#define RCC_CR_HSERDY                   BIT(RCC_CR_HSERDY_BIT)
-#define RCC_CR_HSEON                    BIT(RCC_CR_HSEON_BIT)
-#define RCC_CR_HSICAL                   (0xFF << 8)
-#define RCC_CR_HSITRIM                  (0x1F << 3)
-#define RCC_CR_HSIRDY                   BIT(RCC_CR_HSIRDY_BIT)
-#define RCC_CR_HSION                    BIT(RCC_CR_HSION_BIT)
-
-/* Clock configuration register */
-
-#define RCC_CFGR_USBPRE_BIT             22
-#define RCC_CFGR_PLLXTPRE_BIT           17
-#define RCC_CFGR_PLLSRC_BIT             16
-
-#define RCC_CFGR_MCO                    (0x3 << 24)
-#define RCC_CFGR_USBPRE                 BIT(RCC_CFGR_USBPRE_BIT)
-#define RCC_CFGR_PLLMUL                 (0xF << 18)
-#define RCC_CFGR_PLLXTPRE               BIT(RCC_CFGR_PLLXTPRE_BIT)
-#define RCC_CFGR_PLLSRC                 BIT(RCC_CFGR_PLLSRC_BIT)
-#define RCC_CFGR_ADCPRE                 (0x3 << 14)
-#define RCC_CFGR_PPRE2                  (0x7 << 11)
-#define RCC_CFGR_PPRE1                  (0x7 << 8)
-#define RCC_CFGR_HPRE                   (0xF << 4)
-#define RCC_CFGR_SWS                    (0x3 << 2)
-#define RCC_CFGR_SWS_PLL                (0x2 << 2)
-#define RCC_CFGR_SWS_HSE                (0x1 << 2)
-#define RCC_CFGR_SW                     0x3
-#define RCC_CFGR_SW_PLL                 0x2
-#define RCC_CFGR_SW_HSE                 0x1
-
-/* Clock interrupt register */
-
-#define RCC_CIR_CSSC_BIT                23
-#define RCC_CIR_PLLRDYC_BIT             20
-#define RCC_CIR_HSERDYC_BIT             19
-#define RCC_CIR_HSIRDYC_BIT             18
-#define RCC_CIR_LSERDYC_BIT             17
-#define RCC_CIR_LSIRDYC_BIT             16
-#define RCC_CIR_PLLRDYIE_BIT            12
-#define RCC_CIR_HSERDYIE_BIT            11
-#define RCC_CIR_HSIRDYIE_BIT            10
-#define RCC_CIR_LSERDYIE_BIT            9
-#define RCC_CIR_LSIRDYIE_BIT            8
-#define RCC_CIR_CSSF_BIT                7
-#define RCC_CIR_PLLRDYF_BIT             4
-#define RCC_CIR_HSERDYF_BIT             3
-#define RCC_CIR_HSIRDYF_BIT             2
-#define RCC_CIR_LSERDYF_BIT             1
-#define RCC_CIR_LSIRDYF_BIT             0
-
-#define RCC_CIR_CSSC                    BIT(RCC_CIR_CSSC_BIT)
-#define RCC_CIR_PLLRDYC                 BIT(RCC_CIR_PLLRDYC_BIT)
-#define RCC_CIR_HSERDYC                 BIT(RCC_CIR_HSERDYC_BIT)
-#define RCC_CIR_HSIRDYC                 BIT(RCC_CIR_HSIRDYC_BIT)
-#define RCC_CIR_LSERDYC                 BIT(RCC_CIR_LSERDYC_BIT)
-#define RCC_CIR_LSIRDYC                 BIT(RCC_CIR_LSIRDYC_BIT)
-#define RCC_CIR_PLLRDYIE                BIT(RCC_CIR_PLLRDYIE_BIT)
-#define RCC_CIR_HSERDYIE                BIT(RCC_CIR_HSERDYIE_BIT)
-#define RCC_CIR_HSIRDYIE                BIT(RCC_CIR_HSIRDYIE_BIT)
-#define RCC_CIR_LSERDYIE                BIT(RCC_CIR_LSERDYIE_BIT)
-#define RCC_CIR_LSIRDYIE                BIT(RCC_CIR_LSIRDYIE_BIT)
-#define RCC_CIR_CSSF                    BIT(RCC_CIR_CSSF_BIT)
-#define RCC_CIR_PLLRDYF                 BIT(RCC_CIR_PLLRDYF_BIT)
-#define RCC_CIR_HSERDYF                 BIT(RCC_CIR_HSERDYF_BIT)
-#define RCC_CIR_HSIRDYF                 BIT(RCC_CIR_HSIRDYF_BIT)
-#define RCC_CIR_LSERDYF                 BIT(RCC_CIR_LSERDYF_BIT)
-#define RCC_CIR_LSIRDYF                 BIT(RCC_CIR_LSIRDYF_BIT)
-
-/* APB2 peripheral reset register */
-
-#define RCC_APB2RSTR_TIM11RST_BIT       21
-#define RCC_APB2RSTR_TIM10RST_BIT       20
-#define RCC_APB2RSTR_TIM9RST_BIT        19
-#define RCC_APB2RSTR_ADC3RST_BIT        15
-#define RCC_APB2RSTR_USART1RST_BIT      14
-#define RCC_APB2RSTR_TIM8RST_BIT        13
-#define RCC_APB2RSTR_SPI1RST_BIT        12
-#define RCC_APB2RSTR_TIM1RST_BIT        11
-#define RCC_APB2RSTR_ADC2RST_BIT        10
-#define RCC_APB2RSTR_ADC1RST_BIT        9
-#define RCC_APB2RSTR_IOPGRST_BIT        8
-#define RCC_APB2RSTR_IOPFRST_BIT        7
-#define RCC_APB2RSTR_IOPERST_BIT        6
-#define RCC_APB2RSTR_IOPDRST_BIT        5
-#define RCC_APB2RSTR_IOPCRST_BIT        4
-#define RCC_APB2RSTR_IOPBRST_BIT        3
-#define RCC_APB2RSTR_IOPARST_BIT        2
-#define RCC_APB2RSTR_AFIORST_BIT        0
-
-#define RCC_APB2RSTR_TIM11RST           BIT(RCC_APB2RSTR_TIM11RST_BIT)
-#define RCC_APB2RSTR_TIM10RST           BIT(RCC_APB2RSTR_TIM10RST_BIT)
-#define RCC_APB2RSTR_TIM9RST            BIT(RCC_APB2RSTR_TIM9RST_BIT)
-#define RCC_APB2RSTR_ADC3RST            BIT(RCC_APB2RSTR_ADC3RST_BIT)
-#define RCC_APB2RSTR_USART1RST          BIT(RCC_APB2RSTR_USART1RST_BIT)
-#define RCC_APB2RSTR_TIM8RST            BIT(RCC_APB2RSTR_TIM8RST_BIT)
-#define RCC_APB2RSTR_SPI1RST            BIT(RCC_APB2RSTR_SPI1RST_BIT)
-#define RCC_APB2RSTR_TIM1RST            BIT(RCC_APB2RSTR_TIM1RST_BIT)
-#define RCC_APB2RSTR_ADC2RST            BIT(RCC_APB2RSTR_ADC2RST_BIT)
-#define RCC_APB2RSTR_ADC1RST            BIT(RCC_APB2RSTR_ADC1RST_BIT)
-#define RCC_APB2RSTR_IOPGRST            BIT(RCC_APB2RSTR_IOPGRST_BIT)
-#define RCC_APB2RSTR_IOPFRST            BIT(RCC_APB2RSTR_IOPFRST_BIT)
-#define RCC_APB2RSTR_IOPERST            BIT(RCC_APB2RSTR_IOPERST_BIT)
-#define RCC_APB2RSTR_IOPDRST            BIT(RCC_APB2RSTR_IOPDRST_BIT)
-#define RCC_APB2RSTR_IOPCRST            BIT(RCC_APB2RSTR_IOPCRST_BIT)
-#define RCC_APB2RSTR_IOPBRST            BIT(RCC_APB2RSTR_IOPBRST_BIT)
-#define RCC_APB2RSTR_IOPARST            BIT(RCC_APB2RSTR_IOPARST_BIT)
-#define RCC_APB2RSTR_AFIORST            BIT(RCC_APB2RSTR_AFIORST_BIT)
-
-/* APB1 peripheral reset register */
-
-#define RCC_APB1RSTR_DACRST_BIT         29
-#define RCC_APB1RSTR_PWRRST_BIT         28
-#define RCC_APB1RSTR_BKPRST_BIT         27
-#define RCC_APB1RSTR_CANRST_BIT         25
-#define RCC_APB1RSTR_USBRST_BIT         23
-#define RCC_APB1RSTR_I2C2RST_BIT        22
-#define RCC_APB1RSTR_I2C1RST_BIT        21
-#define RCC_APB1RSTR_UART5RST_BIT       20
-#define RCC_APB1RSTR_UART4RST_BIT       19
-#define RCC_APB1RSTR_USART3RST_BIT      18
-#define RCC_APB1RSTR_USART2RST_BIT      17
-#define RCC_APB1RSTR_SPI3RST_BIT        15
-#define RCC_APB1RSTR_SPI2RST_BIT        14
-#define RCC_APB1RSTR_WWDRST_BIT         11
-#define RCC_APB1RSTR_TIM14RST_BIT       8
-#define RCC_APB1RSTR_TIM13RST_BIT       7
-#define RCC_APB1RSTR_TIM12RST_BIT       6
-#define RCC_APB1RSTR_TIM7RST_BIT        5
-#define RCC_APB1RSTR_TIM6RST_BIT        4
-#define RCC_APB1RSTR_TIM5RST_BIT        3
-#define RCC_APB1RSTR_TIM4RST_BIT        2
-#define RCC_APB1RSTR_TIM3RST_BIT        1
-#define RCC_APB1RSTR_TIM2RST_BIT        0
-
-#define RCC_APB1RSTR_DACRST             BIT(RCC_APB1RSTR_DACRST_BIT)
-#define RCC_APB1RSTR_PWRRST             BIT(RCC_APB1RSTR_PWRRST_BIT)
-#define RCC_APB1RSTR_BKPRST             BIT(RCC_APB1RSTR_BKPRST_BIT)
-#define RCC_APB1RSTR_CANRST             BIT(RCC_APB1RSTR_CANRST_BIT)
-#define RCC_APB1RSTR_USBRST             BIT(RCC_APB1RSTR_USBRST_BIT)
-#define RCC_APB1RSTR_I2C2RST            BIT(RCC_APB1RSTR_I2C2RST_BIT)
-#define RCC_APB1RSTR_I2C1RST            BIT(RCC_APB1RSTR_I2C1RST_BIT)
-#define RCC_APB1RSTR_UART5RST           BIT(RCC_APB1RSTR_UART5RST_BIT)
-#define RCC_APB1RSTR_UART4RST           BIT(RCC_APB1RSTR_UART4RST_BIT)
-#define RCC_APB1RSTR_USART3RST          BIT(RCC_APB1RSTR_USART3RST_BIT)
-#define RCC_APB1RSTR_USART2RST          BIT(RCC_APB1RSTR_USART2RST_BIT)
-#define RCC_APB1RSTR_SPI3RST            BIT(RCC_APB1RSTR_SPI3RST_BIT)
-#define RCC_APB1RSTR_SPI2RST            BIT(RCC_APB1RSTR_SPI2RST_BIT)
-#define RCC_APB1RSTR_WWDRST             BIT(RCC_APB1RSTR_WWDRST_BIT)
-#define RCC_APB1RSTR_TIM14RST           BIT(RCC_APB1RSTR_TIM14RST_BIT)
-#define RCC_APB1RSTR_TIM13RST           BIT(RCC_APB1RSTR_TIM13RST_BIT)
-#define RCC_APB1RSTR_TIM12RST           BIT(RCC_APB1RSTR_TIM12RST_BIT)
-#define RCC_APB1RSTR_TIM7RST            BIT(RCC_APB1RSTR_TIM7RST_BIT)
-#define RCC_APB1RSTR_TIM6RST            BIT(RCC_APB1RSTR_TIM6RST_BIT)
-#define RCC_APB1RSTR_TIM5RST            BIT(RCC_APB1RSTR_TIM5RST_BIT)
-#define RCC_APB1RSTR_TIM4RST            BIT(RCC_APB1RSTR_TIM4RST_BIT)
-#define RCC_APB1RSTR_TIM3RST            BIT(RCC_APB1RSTR_TIM3RST_BIT)
-#define RCC_APB1RSTR_TIM2RST            BIT(RCC_APB1RSTR_TIM2RST_BIT)
-
-/* AHB peripheral clock enable register */
-
-#define RCC_AHBENR_SDIOEN_BIT           10
-#define RCC_AHBENR_FSMCEN_BIT           8
-#define RCC_AHBENR_CRCEN_BIT            7
-#define RCC_AHBENR_FLITFEN_BIT          4
-#define RCC_AHBENR_SRAMEN_BIT           2
-#define RCC_AHBENR_DMA2EN_BIT           1
-#define RCC_AHBENR_DMA1EN_BIT           0
-
-#define RCC_AHBENR_SDIOEN               BIT(RCC_AHBENR_SDIOEN_BIT)
-#define RCC_AHBENR_FSMCEN               BIT(RCC_AHBENR_FSMCEN_BIT)
-#define RCC_AHBENR_CRCEN                BIT(RCC_AHBENR_CRCEN_BIT)
-#define RCC_AHBENR_FLITFEN              BIT(RCC_AHBENR_FLITFEN_BIT)
-#define RCC_AHBENR_SRAMEN               BIT(RCC_AHBENR_SRAMEN_BIT)
-#define RCC_AHBENR_DMA2EN               BIT(RCC_AHBENR_DMA2EN_BIT)
-#define RCC_AHBENR_DMA1EN               BIT(RCC_AHBENR_DMA1EN_BIT)
-
-/* APB2 peripheral clock enable register */
-
-#define RCC_APB2ENR_TIM11EN_BIT         21
-#define RCC_APB2ENR_TIM10EN_BIT         20
-#define RCC_APB2ENR_TIM9EN_BIT          19
-#define RCC_APB2ENR_ADC3EN_BIT          15
-#define RCC_APB2ENR_USART1EN_BIT        14
-#define RCC_APB2ENR_TIM8EN_BIT          13
-#define RCC_APB2ENR_SPI1EN_BIT          12
-#define RCC_APB2ENR_TIM1EN_BIT          11
-#define RCC_APB2ENR_ADC2EN_BIT          10
-#define RCC_APB2ENR_ADC1EN_BIT          9
-#define RCC_APB2ENR_IOPGEN_BIT          8
-#define RCC_APB2ENR_IOPFEN_BIT          7
-#define RCC_APB2ENR_IOPEEN_BIT          6
-#define RCC_APB2ENR_IOPDEN_BIT          5
-#define RCC_APB2ENR_IOPCEN_BIT          4
-#define RCC_APB2ENR_IOPBEN_BIT          3
-#define RCC_APB2ENR_IOPAEN_BIT          2
-#define RCC_APB2ENR_AFIOEN_BIT          0
-
-#define RCC_APB2ENR_TIM11EN             BIT(RCC_APB2ENR_TIM11EN_BIT)
-#define RCC_APB2ENR_TIM10EN             BIT(RCC_APB2ENR_TIM10EN_BIT)
-#define RCC_APB2ENR_TIM9EN              BIT(RCC_APB2ENR_TIM9EN_BIT)
-#define RCC_APB2ENR_ADC3EN              BIT(RCC_APB2ENR_ADC3EN_BIT)
-#define RCC_APB2ENR_USART1EN            BIT(RCC_APB2ENR_USART1EN_BIT)
-#define RCC_APB2ENR_TIM8EN              BIT(RCC_APB2ENR_TIM8EN_BIT)
-#define RCC_APB2ENR_SPI1EN              BIT(RCC_APB2ENR_SPI1EN_BIT)
-#define RCC_APB2ENR_TIM1EN              BIT(RCC_APB2ENR_TIM1EN_BIT)
-#define RCC_APB2ENR_ADC2EN              BIT(RCC_APB2ENR_ADC2EN_BIT)
-#define RCC_APB2ENR_ADC1EN              BIT(RCC_APB2ENR_ADC1EN_BIT)
-#define RCC_APB2ENR_IOPGEN              BIT(RCC_APB2ENR_IOPGEN_BIT)
-#define RCC_APB2ENR_IOPFEN              BIT(RCC_APB2ENR_IOPFEN_BIT)
-#define RCC_APB2ENR_IOPEEN              BIT(RCC_APB2ENR_IOPEEN_BIT)
-#define RCC_APB2ENR_IOPDEN              BIT(RCC_APB2ENR_IOPDEN_BIT)
-#define RCC_APB2ENR_IOPCEN              BIT(RCC_APB2ENR_IOPCEN_BIT)
-#define RCC_APB2ENR_IOPBEN              BIT(RCC_APB2ENR_IOPBEN_BIT)
-#define RCC_APB2ENR_IOPAEN              BIT(RCC_APB2ENR_IOPAEN_BIT)
-#define RCC_APB2ENR_AFIOEN              BIT(RCC_APB2ENR_AFIOEN_BIT)
-
-/* APB1 peripheral clock enable register */
-
-#define RCC_APB1ENR_DACEN_BIT           29
-#define RCC_APB1ENR_PWREN_BIT           28
-#define RCC_APB1ENR_BKPEN_BIT           27
-#define RCC_APB1ENR_CANEN_BIT           25
-#define RCC_APB1ENR_USBEN_BIT           23
-#define RCC_APB1ENR_I2C2EN_BIT          22
-#define RCC_APB1ENR_I2C1EN_BIT          21
-#define RCC_APB1ENR_UART5EN_BIT         20
-#define RCC_APB1ENR_UART4EN_BIT         19
-#define RCC_APB1ENR_USART3EN_BIT        18
-#define RCC_APB1ENR_USART2EN_BIT        17
-#define RCC_APB1ENR_SPI3EN_BIT          15
-#define RCC_APB1ENR_SPI2EN_BIT          14
-#define RCC_APB1ENR_WWDEN_BIT           11
-#define RCC_APB1ENR_TIM14EN_BIT         8
-#define RCC_APB1ENR_TIM13EN_BIT         7
-#define RCC_APB1ENR_TIM12EN_BIT         6
-#define RCC_APB1ENR_TIM7EN_BIT          5
-#define RCC_APB1ENR_TIM6EN_BIT          4
-#define RCC_APB1ENR_TIM5EN_BIT          3
-#define RCC_APB1ENR_TIM4EN_BIT          2
-#define RCC_APB1ENR_TIM3EN_BIT          1
-#define RCC_APB1ENR_TIM2EN_BIT          0
-
-#define RCC_APB1ENR_DACEN               BIT(RCC_APB1ENR_DACEN_BIT)
-#define RCC_APB1ENR_PWREN               BIT(RCC_APB1ENR_PWREN_BIT)
-#define RCC_APB1ENR_BKPEN               BIT(RCC_APB1ENR_BKPEN_BIT)
-#define RCC_APB1ENR_CANEN               BIT(RCC_APB1ENR_CANEN_BIT)
-#define RCC_APB1ENR_USBEN               BIT(RCC_APB1ENR_USBEN_BIT)
-#define RCC_APB1ENR_I2C2EN              BIT(RCC_APB1ENR_I2C2EN_BIT)
-#define RCC_APB1ENR_I2C1EN              BIT(RCC_APB1ENR_I2C1EN_BIT)
-#define RCC_APB1ENR_UART5EN             BIT(RCC_APB1ENR_UART5EN_BIT)
-#define RCC_APB1ENR_UART4EN             BIT(RCC_APB1ENR_UART4EN_BIT)
-#define RCC_APB1ENR_USART3EN            BIT(RCC_APB1ENR_USART3EN_BIT)
-#define RCC_APB1ENR_USART2EN            BIT(RCC_APB1ENR_USART2EN_BIT)
-#define RCC_APB1ENR_SPI3EN              BIT(RCC_APB1ENR_SPI3EN_BIT)
-#define RCC_APB1ENR_SPI2EN              BIT(RCC_APB1ENR_SPI2EN_BIT)
-#define RCC_APB1ENR_WWDEN               BIT(RCC_APB1ENR_WWDEN_BIT)
-#define RCC_APB1ENR_TIM14EN             BIT(RCC_APB1ENR_TIM14EN_BIT)
-#define RCC_APB1ENR_TIM13EN             BIT(RCC_APB1ENR_TIM13EN_BIT)
-#define RCC_APB1ENR_TIM12EN             BIT(RCC_APB1ENR_TIM12EN_BIT)
-#define RCC_APB1ENR_TIM7EN              BIT(RCC_APB1ENR_TIM7EN_BIT)
-#define RCC_APB1ENR_TIM6EN              BIT(RCC_APB1ENR_TIM6EN_BIT)
-#define RCC_APB1ENR_TIM5EN              BIT(RCC_APB1ENR_TIM5EN_BIT)
-#define RCC_APB1ENR_TIM4EN              BIT(RCC_APB1ENR_TIM4EN_BIT)
-#define RCC_APB1ENR_TIM3EN              BIT(RCC_APB1ENR_TIM3EN_BIT)
-#define RCC_APB1ENR_TIM2EN              BIT(RCC_APB1ENR_TIM2EN_BIT)
-
-/* Backup domain control register */
-
-#define RCC_BDCR_BDRST_BIT              16
-#define RCC_BDCR_RTCEN_BIT              15
-#define RCC_BDCR_LSEBYP_BIT             2
-#define RCC_BDCR_LSERDY_BIT             1
-#define RCC_BDCR_LSEON_BIT              0
-
-#define RCC_BDCR_BDRST                  BIT(RCC_BDCR_BDRST_BIT)
-#define RCC_BDCR_RTCEN                  BIT(RCC_BDCR_RTC_BIT)
-#define RCC_BDCR_RTCSEL                 (0x3 << 8)
-#define RCC_BDCR_RTCSEL_NONE            (0x0 << 8)
-#define RCC_BDCR_RTCSEL_LSE             (0x1 << 8)
-#define RCC_BDCR_RTCSEL_HSE             (0x3 << 8)
-#define RCC_BDCR_LSEBYP                 BIT(RCC_BDCR_LSEBYP_BIT)
-#define RCC_BDCR_LSERDY                 BIT(RCC_BDCR_LSERDY_BIT)
-#define RCC_BDCR_LSEON                  BIT(RCC_BDCR_LSEON_BIT)
-
-/* Control/status register */
-
-#define RCC_CSR_LPWRRSTF_BIT            31
-#define RCC_CSR_WWDGRSTF_BIT            30
-#define RCC_CSR_IWDGRSTF_BIT            29
-#define RCC_CSR_SFTRSTF_BIT             28
-#define RCC_CSR_PORRSTF_BIT             27
-#define RCC_CSR_PINRSTF_BIT             26
-#define RCC_CSR_RMVF_BIT                24
-#define RCC_CSR_LSIRDY_BIT              1
-#define RCC_CSR_LSION_BIT               0
-
-#define RCC_CSR_LPWRRSTF                BIT(RCC_CSR_LPWRRSTF_BIT)
-#define RCC_CSR_WWDGRSTF                BIT(RCC_CSR_WWDGRSTF_BIT)
-#define RCC_CSR_IWDGRSTF                BIT(RCC_CSR_IWDGRSTF_BIT)
-#define RCC_CSR_SFTRSTF                 BIT(RCC_CSR_SFTRSTF_BIT)
-#define RCC_CSR_PORRSTF                 BIT(RCC_CSR_PORRSTF_BIT)
-#define RCC_CSR_PINRSTF                 BIT(RCC_CSR_PINRSTF_BIT)
-#define RCC_CSR_RMVF                    BIT(RCC_CSR_RMVF_BIT)
-#define RCC_CSR_LSIRDY                  BIT(RCC_CSR_LSIRDY_BIT)
-#define RCC_CSR_LSION                   BIT(RCC_CSR_LSION_BIT)
-
-/*
- * Convenience routines
- */
-
-/**
- * SYSCLK sources
- * @see rcc_clk_init()
- */
-typedef enum rcc_sysclk_src {
-    RCC_CLKSRC_HSI = 0x0,
-    RCC_CLKSRC_HSE = 0x1,
-    RCC_CLKSRC_PLL = 0x2,
-} rcc_sysclk_src;
-
-/**
- * PLL entry clock source
- * @see rcc_clk_init()
- */
-typedef enum rcc_pllsrc {
-    RCC_PLLSRC_HSE = (0x1 << 16),
-    RCC_PLLSRC_HSI_DIV_2 = (0x0 << 16)
-} rcc_pllsrc;
-
-/**
- * PLL multipliers
- * @see rcc_clk_init()
- */
-typedef enum rcc_pll_multiplier {
-    RCC_PLLMUL_2 = (0x0 << 18),
-    RCC_PLLMUL_3 = (0x1 << 18),
-    RCC_PLLMUL_4 = (0x2 << 18),
-    RCC_PLLMUL_5 = (0x3 << 18),
-    RCC_PLLMUL_6 = (0x4 << 18),
-    RCC_PLLMUL_7 = (0x5 << 18),
-    RCC_PLLMUL_8 = (0x6 << 18),
-    RCC_PLLMUL_9 = (0x7 << 18),
-    RCC_PLLMUL_10 = (0x8 << 18),
-    RCC_PLLMUL_11 = (0x9 << 18),
-    RCC_PLLMUL_12 = (0xA << 18),
-    RCC_PLLMUL_13 = (0xB << 18),
-    RCC_PLLMUL_14 = (0xC << 18),
-    RCC_PLLMUL_15 = (0xD << 18),
-    RCC_PLLMUL_16 = (0xE << 18),
-} rcc_pll_multiplier;
-
-/**
- * @brief Identifies bus and clock line for a peripheral.
- *
- * Also generally useful as a unique identifier for that peripheral
- * (or its corresponding device struct).
- */
-typedef enum rcc_clk_id {
-    RCC_GPIOA,
-    RCC_GPIOB,
-    RCC_GPIOC,
-    RCC_GPIOD,
-    RCC_AFIO,
-    RCC_ADC1,
-    RCC_ADC2,
-    RCC_ADC3,
-    RCC_USART1,
-    RCC_USART2,
-    RCC_USART3,
-    RCC_TIMER1,
-    RCC_TIMER2,
-    RCC_TIMER3,
-    RCC_TIMER4,
-    RCC_SPI1,
-    RCC_SPI2,
-    RCC_DMA1,
-    RCC_PWR,
-    RCC_BKP,
-    RCC_I2C1,
-    RCC_I2C2,
-    RCC_CRC,
-    RCC_FLITF,
-    RCC_SRAM,
-#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
-    RCC_GPIOE,
-    RCC_GPIOF,
-    RCC_GPIOG,
-    RCC_UART4,
-    RCC_UART5,
-    RCC_TIMER5,
-    RCC_TIMER6,
-    RCC_TIMER7,
-    RCC_TIMER8,
-    RCC_FSMC,
-    RCC_DAC,
-    RCC_DMA2,
-    RCC_SDIO,
-    RCC_SPI3,
-#endif
-#ifdef STM32_XL_DENSITY
-    RCC_TIMER9,
-    RCC_TIMER10,
-    RCC_TIMER11,
-    RCC_TIMER12,
-    RCC_TIMER13,
-    RCC_TIMER14,
-#endif
-} rcc_clk_id;
-
-void rcc_clk_init(rcc_sysclk_src sysclk_src,
-                  rcc_pllsrc pll_src,
-                  rcc_pll_multiplier pll_mul);
-void rcc_clk_enable(rcc_clk_id device);
-void rcc_reset_dev(rcc_clk_id device);
-
-typedef enum rcc_clk_domain {
-    RCC_APB1,
-    RCC_APB2,
-    RCC_AHB
-} rcc_clk_domain;
-
-rcc_clk_domain rcc_dev_clk(rcc_clk_id device);
-
-uint32 rcc_dev_clk_speed(rcc_clk_id id);
-uint32 rcc_dev_timer_clk_speed(rcc_clk_id id);
-
-/**
- * Prescaler identifiers
- * @see rcc_set_prescaler()
- */
-typedef enum rcc_prescaler {
-    RCC_PRESCALER_AHB,
-    RCC_PRESCALER_APB1,
-    RCC_PRESCALER_APB2,
-    RCC_PRESCALER_USB,
-    RCC_PRESCALER_ADC
-} rcc_prescaler;
-
-/**
- * ADC prescaler dividers
- * @see rcc_set_prescaler()
- */
-typedef enum rcc_adc_divider {
-    RCC_ADCPRE_PCLK_DIV_2 = 0x0 << 14,
-    RCC_ADCPRE_PCLK_DIV_4 = 0x1 << 14,
-    RCC_ADCPRE_PCLK_DIV_6 = 0x2 << 14,
-    RCC_ADCPRE_PCLK_DIV_8 = 0x3 << 14,
-} rcc_adc_divider;
-
-/**
- * APB1 prescaler dividers
- * @see rcc_set_prescaler()
- */
-typedef enum rcc_apb1_divider {
-    RCC_APB1_HCLK_DIV_1 = 0x0 << 8,
-    RCC_APB1_HCLK_DIV_2 = 0x4 << 8,
-    RCC_APB1_HCLK_DIV_4 = 0x5 << 8,
-    RCC_APB1_HCLK_DIV_8 = 0x6 << 8,
-    RCC_APB1_HCLK_DIV_16 = 0x7 << 8,
-} rcc_apb1_divider;
-
-/**
- * APB2 prescaler dividers
- * @see rcc_set_prescaler()
- */
-typedef enum rcc_apb2_divider {
-    RCC_APB2_HCLK_DIV_1 = 0x0 << 11,
-    RCC_APB2_HCLK_DIV_2 = 0x4 << 11,
-    RCC_APB2_HCLK_DIV_4 = 0x5 << 11,
-    RCC_APB2_HCLK_DIV_8 = 0x6 << 11,
-    RCC_APB2_HCLK_DIV_16 = 0x7 << 11,
-} rcc_apb2_divider;
-
-/**
- * AHB prescaler dividers
- * @see rcc_set_prescaler()
- */
-typedef enum rcc_ahb_divider {
-    RCC_AHB_SYSCLK_DIV_1 = 0x0 << 4,
-    RCC_AHB_SYSCLK_DIV_2 = 0x8 << 4,
-    RCC_AHB_SYSCLK_DIV_4 = 0x9 << 4,
-    RCC_AHB_SYSCLK_DIV_8 = 0xA << 4,
-    RCC_AHB_SYSCLK_DIV_16 = 0xB << 4,
-    RCC_AHB_SYSCLK_DIV_32 = 0xC << 4,
-    RCC_AHB_SYSCLK_DIV_64 = 0xD << 4,
-    RCC_AHB_SYSCLK_DIV_128 = 0xD << 4,
-    RCC_AHB_SYSCLK_DIV_256 = 0xE << 4,
-    RCC_AHB_SYSCLK_DIV_512 = 0xF << 4,
-} rcc_ahb_divider;
-
-void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider);
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
-#endif
diff --git a/STM32F4/cores/maple/libmaple/rccF2.c b/STM32F4/cores/maple/libmaple/rccF4.c
similarity index 99%
rename from STM32F4/cores/maple/libmaple/rccF2.c
rename to STM32F4/cores/maple/libmaple/rccF4.c
index 691393a8d..c4ff30dc4 100644
--- a/STM32F4/cores/maple/libmaple/rccF2.c
+++ b/STM32F4/cores/maple/libmaple/rccF4.c
@@ -24,7 +24,7 @@
  * SOFTWARE.
  *****************************************************************************/
 
- #ifdef STM32F2
+#ifdef STM32F4
  
 /**
  * @file rcc.c
@@ -166,7 +166,6 @@ typedef struct
 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
 #define RESET 0
 
-typedef uint32 uint32_t;
 
 void InitMCO1()
 {
@@ -175,8 +174,8 @@ void InitMCO1()
     RCC->CFGR &= RCC_CFGR_MCO1_RESET_MASK;
     RCC->CFGR |= RCC_CFGR_MCO1Source_HSE | RCC_CFGR_MCO1Div_1;
     // PA8 Output the Master Clock MCO1
-    gpio_set_af_mode(GPIOA, 8, 0);
-    gpio_set_mode(GPIOA, 8, GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
+    gpio_set_af_mode(PA8, 0);
+    gpio_set_mode(PA8, GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
 }
 
 
diff --git a/STM32F4/cores/maple/libmaple/rccF2.h b/STM32F4/cores/maple/libmaple/rccF4.h
similarity index 100%
rename from STM32F4/cores/maple/libmaple/rccF2.h
rename to STM32F4/cores/maple/libmaple/rccF4.h
diff --git a/STM32F4/cores/maple/libmaple/rules.mk b/STM32F4/cores/maple/libmaple/rules.mk
index c4924dc86..eb8d96d26 100644
--- a/STM32F4/cores/maple/libmaple/rules.mk
+++ b/STM32F4/cores/maple/libmaple/rules.mk
@@ -3,17 +3,11 @@ sp              := $(sp).x
 dirstack_$(sp)  := $(d)
 d               := $(dir)
 BUILDDIRS       += $(BUILD_PATH)/$(d)
-ifneq ($(MCU_FAMILY), STM32F2)
-BUILDDIRS       += $(BUILD_PATH)/$(d)/usb
-BUILDDIRS       += $(BUILD_PATH)/$(d)/usb/usb_lib
-LIBMAPLE_INCLUDES := -I$(LIBMAPLE_PATH) -I$(LIBMAPLE_PATH)/usb -I$(LIBMAPLE_PATH)/usb/usb_lib
-else
 BUILDDIRS       += $(BUILD_PATH)/$(d)/usbF4/STM32_USB_Device_Library/Core/src
 BUILDDIRS       += $(BUILD_PATH)/$(d)/usbF4/STM32_USB_Device_Library/Class/cdc/src
 BUILDDIRS       += $(BUILD_PATH)/$(d)/usbF4/STM32_USB_OTG_Driver/src
 BUILDDIRS       += $(BUILD_PATH)/$(d)/usbF4/VCP
 LIBMAPLE_INCLUDES := -I$(LIBMAPLE_PATH) -I$(LIBMAPLE_PATH)/usbF4
-endif
 
 
 # Local flags
@@ -42,18 +36,6 @@ cSRCS_$(d) := adc.c                    \
               usart.c                  \
               util.c                   
 
-ifneq ($(MCU_FAMILY), STM32F2)
-	cSRCS_$(d) += \
-              usb/descriptors.c        \
-              usb/usb.c                \
-              usb/usb_callbacks.c      \
-              usb/usb_hardware.c       \
-              usb/usb_lib/usb_core.c   \
-              usb/usb_lib/usb_init.c   \
-              usb/usb_lib/usb_int.c    \
-              usb/usb_lib/usb_mem.c    \
-              usb/usb_lib/usb_regs.c
-else
 	V=1
 	cSRCS_$(d) += \
 		usbF4/STM32_USB_Device_Library/Core/src/usbd_core.c \
@@ -69,11 +51,7 @@ else
 		usbF4/VCP/usbd_usr.c \
 		usbF4/usb.c \
 		usbF4/VCP/misc.c 
-endif
 
-ifneq ($(MCU_FAMILY), STM32F2)
-	cSRCS_$(d) += bkp.c
-endif
 
 sSRCS_$(d) := exc.S
 
diff --git a/STM32F4/cores/maple/libmaple/spi.c b/STM32F4/cores/maple/libmaple/spi.c
index 194a82efe..4b274cb37 100644
--- a/STM32F4/cores/maple/libmaple/spi.c
+++ b/STM32F4/cores/maple/libmaple/spi.c
@@ -83,25 +83,29 @@ void spi_slave_enable(spi_dev *dev, spi_mode mode, uint32 flags) {
 }
 
 /**
- * @brief Nonblocking SPI transmit.
+ * @brief Blocking SPI transmit.
  * @param dev SPI port to use for transmission
  * @param buf Buffer to transmit.  The sizeof buf's elements are
  *            inferred from dev's data frame format (i.e., are
  *            correctly treated as 8-bit or 16-bit quantities).
  * @param len Maximum number of elements to transmit.
- * @return Number of elements transmitted.
  */
-uint32 spi_tx(spi_dev *dev, const void *buf, uint32 len) {
-    uint32 txed = 0;
-    uint8 byte_frame = spi_dff(dev) == SPI_DFF_8_BIT;
-    while (spi_is_tx_empty(dev) && (txed < len)) {
-        if (byte_frame) {
-            dev->regs->DR = ((const uint8*)buf)[txed++];
-        } else {
-            dev->regs->DR = ((const uint16*)buf)[txed++];
-        }
-    }
-    return txed;
+void spi_tx(spi_dev *dev, void *buf, uint32 len)
+{
+	spi_reg_map *regs = dev->regs;
+    if ( spi_dff(dev) == SPI_DFF_8_BIT ) {
+		uint8 * dp8 = (uint8*)buf;
+		while ( len-- ) {
+			while ( (regs->SR & SPI_SR_TXE)==0 ) ; //while ( spi_is_tx_empty(dev)==0 ); // wait Tx to be empty
+			regs->DR = *dp8++;
+		}
+    } else {
+		uint16 * dp16 = (uint16*)buf;
+		while ( len-- ) {
+			while ( (regs->SR & SPI_SR_TXE)==0 ) ; //while ( spi_is_tx_empty(dev)==0 ); // wait Tx to be empty
+			regs->DR = *dp16++;
+		}
+	}
 }
 
 /**
@@ -157,8 +161,9 @@ void spi_rx_dma_disable(spi_dev *dev) {
  */
 
 static void spi_reconfigure(spi_dev *dev, uint32 cr1_config) {
-    spi_irq_disable(dev, SPI_INTERRUPTS_ALL);
-    spi_peripheral_disable(dev);
-    dev->regs->CR1 = cr1_config;
-    spi_peripheral_enable(dev);
+#define MASK (SPI_CR1_CRCEN|SPI_CR1_DFF)
+	spi_irq_disable(dev, SPI_INTERRUPTS_ALL);
+	if ( (dev->regs->CR1&MASK)!=(cr1_config&MASK) )	spi_peripheral_disable(dev);
+	dev->regs->CR1 = cr1_config;
+	spi_peripheral_enable(dev);
 }
diff --git a/STM32F4/cores/maple/libmaple/spi.h b/STM32F4/cores/maple/libmaple/spi.h
index 88739c584..abed68c12 100644
--- a/STM32F4/cores/maple/libmaple/spi.h
+++ b/STM32F4/cores/maple/libmaple/spi.h
@@ -213,31 +213,22 @@ typedef struct spi_dev {
 
 void spi_init(spi_dev *dev);
 
-struct gpio_dev;
 /**
  * @brief Configure GPIO bit modes for use as a SPI port's pins.
  *
  * @param dev SPI device
  * @param as_master If true, configure as bus master; otherwise, as slave.
- * @param nss_dev NSS pin's GPIO device
  * @param nss_bit NSS pin's GPIO bit on nss_dev
- * @param sck_dev SCK pin's GPIO device
  * @param sck_bit SCK pin's GPIO bit on comm_dev
- * @param miso_dev MISO pin's GPIO device
  * @param miso_bit MISO pin's GPIO bit on comm_dev
- * @param mosi_dev MOSI pin's GPIO device
  * @param mosi_bit MOSI pin's GPIO bit on comm_dev
  */
 extern void spi_config_gpios(spi_dev *dev,
                              uint8 as_master,
-                             struct gpio_dev *nss_dev,
-                             uint8 nss_bit,
-                             struct gpio_dev *sck_dev,
-                             uint8 sck_bit,
-                             struct gpio_dev *miso_dev,
-                             uint8 miso_bit,
-                             struct gpio_dev *mosi_dev,
-                             uint8 mosi_bit);
+                             uint8 nss_pin,
+                             uint8 sck_pin,
+                             uint8 miso_pin,
+                             uint8 mosi_pin);
 
 /**
  * @brief SPI mode configuration.
@@ -312,7 +303,7 @@ void spi_slave_enable(spi_dev *dev,
                       spi_mode mode,
                       uint32 flags);
 
-uint32 spi_tx(spi_dev *dev, const void *buf, uint32 len);
+void spi_tx(spi_dev *dev, void *buf, uint32 len);
 
 /**
  * @brief Call a function on each SPI port
diff --git a/STM32F4/cores/maple/libmaple/spiF4.h b/STM32F4/cores/maple/libmaple/spiF4.h
index 3f5116442..cbdc91a73 100644
--- a/STM32F4/cores/maple/libmaple/spiF4.h
+++ b/STM32F4/cores/maple/libmaple/spiF4.h
@@ -31,8 +31,8 @@
  * @brief STM32F1 SPI/I2S series header.
  */
 
-#ifndef _LIBMAPLE_STM32F1_SPI_H_
-#define _LIBMAPLE_STM32F1_SPI_H_
+#ifndef _LIBMAPLE_SPI_F4_H_
+#define _LIBMAPLE_SPI_F4_H_
 
 #include <libmaple/libmaple_types.h>
 
@@ -62,17 +62,6 @@ extern struct spi_dev *SPI2;
 extern struct spi_dev *SPI3;
 #endif
 
-/*
- * Routines
- */
-
-/* spi_gpio_cfg(): Backwards compatibility shim to spi_config_gpios() */
-struct gpio_dev;
-extern void spi_config_gpios(struct spi_dev*, uint8,
-                             struct gpio_dev*, uint8,
-                             struct gpio_dev*, uint8, 
-                             struct gpio_dev*, uint8, 
-                             struct gpio_dev*, uint8); 
 
 #ifdef __cplusplus
 }
diff --git a/STM32F4/cores/maple/libmaple/spi_f4.c b/STM32F4/cores/maple/libmaple/spi_f4.c
index b9beb68d2..43f5092c6 100644
--- a/STM32F4/cores/maple/libmaple/spi_f4.c
+++ b/STM32F4/cores/maple/libmaple/spi_f4.c
@@ -56,25 +56,21 @@ spi_dev *SPI3 = &spi3;
 
 void spi_config_gpios(spi_dev *ignored,
                       uint8 as_master,
-                      gpio_dev *nss_dev,
-                      uint8 nss_bit,
-                      gpio_dev *sck_dev,
-                      uint8 sck_bit,
-                      gpio_dev *miso_dev,
-                      uint8 miso_bit,
-                      gpio_dev *mosi_dev,
-                      uint8 mosi_bit) {
+                      uint8 nss_pin,
+                      uint8 sck_pin,
+                      uint8 miso_pin,
+                      uint8 mosi_pin) {
     if (as_master) {
 //        gpio_set_mode(nss_dev, nss_bit, GPIO_AF_OUTPUT_PP);
-        gpio_set_mode(sck_dev, sck_bit, GPIO_AF_OUTPUT_PP);
+        gpio_set_mode(sck_pin, GPIO_AF_OUTPUT_PP);
 //        gpio_set_mode(comm_dev, miso_bit, GPIO_INPUT_FLOATING);
-        gpio_set_mode(miso_dev, miso_bit, GPIO_AF_INPUT_PD);		
-        gpio_set_mode(mosi_dev, mosi_bit, GPIO_AF_OUTPUT_PP);
+        gpio_set_mode(miso_pin, GPIO_AF_INPUT_PD);		
+        gpio_set_mode(mosi_pin, GPIO_AF_OUTPUT_PP);
     } else {
-        gpio_set_mode(nss_dev, nss_bit, GPIO_INPUT_FLOATING);
-        gpio_set_mode(sck_dev, sck_bit, GPIO_INPUT_FLOATING);
-        gpio_set_mode(miso_dev, miso_bit, GPIO_AF_OUTPUT_PP);
-        gpio_set_mode(mosi_dev, mosi_bit, GPIO_INPUT_FLOATING);
+        gpio_set_mode(nss_pin, GPIO_INPUT_FLOATING);
+        gpio_set_mode(sck_pin, GPIO_INPUT_FLOATING);
+        gpio_set_mode(miso_pin, GPIO_AF_OUTPUT_PP);
+        gpio_set_mode(mosi_pin, GPIO_INPUT_FLOATING);
     }
 }
 
diff --git a/STM32F4/cores/maple/libmaple/stm32.h b/STM32F4/cores/maple/libmaple/stm32.h
index 0d4deaa41..3921788e7 100644
--- a/STM32F4/cores/maple/libmaple/stm32.h
+++ b/STM32F4/cores/maple/libmaple/stm32.h
@@ -138,69 +138,8 @@
 
 #endif
 
-#if defined(MCU_STM32F103RB)
-    /* e.g., LeafLabs Maple */
 
-    #define STM32_NR_GPIO_PORTS          4
-    #define STM32_DELAY_US_MULT         12
-    #define STM32_SRAM_END              ((void*)0x20005000)
-
-    #define NR_GPIO_PORTS               STM32_NR_GPIO_PORTS
-    #define DELAY_US_MULT               STM32_DELAY_US_MULT
-
-#elif defined(MCU_STM32F103ZE)
-    /* e.g., LeafLabs Maple Native */
-
-    #define STM32_NR_GPIO_PORTS          7
-    #define STM32_DELAY_US_MULT         12
-    #define STM32_SRAM_END              ((void*)0x20010000)
-
-    #define NR_GPIO_PORTS               STM32_NR_GPIO_PORTS
-    #define DELAY_US_MULT               STM32_DELAY_US_MULT
-
-#elif defined(MCU_STM32F103CB)
-    /* e.g., LeafLabs Maple Mini */
-
-    /* This STM32_NR_GPIO_PORTS value is not, strictly speaking, true.
-     * But only pins 0 and 1 exist, and they're used for OSC on the
-     * Mini, so we'll live with this for now. */
-    #define STM32_NR_GPIO_PORTS          3
-    #define STM32_DELAY_US_MULT         12
-    #define STM32_SRAM_END              ((void*)0x20005000)
-
-    #define NR_GPIO_PORTS               STM32_NR_GPIO_PORTS
-    #define DELAY_US_MULT               STM32_DELAY_US_MULT
-
-#elif defined(MCU_STM32F103RE)
-    /* e.g., LeafLabs Maple RET6 edition */
-
-    #define STM32_NR_GPIO_PORTS          4
-    #define STM32_DELAY_US_MULT         12
-    #define STM32_SRAM_END              ((void*)0x20010000)
-
-    #define NR_GPIO_PORTS               STM32_NR_GPIO_PORTS
-    #define DELAY_US_MULT               STM32_DELAY_US_MULT
-
-#elif defined(MCU_STM32F103VE)
-    /* e.g., LeafLabs Maple Native */
-
-    #define STM32_NR_GPIO_PORTS          5
-    #define STM32_DELAY_US_MULT         12
-    #define STM32_SRAM_END              ((void*)0x20010000)
-
-    #define NR_GPIO_PORTS               STM32_NR_GPIO_PORTS
-    #define DELAY_US_MULT               STM32_DELAY_US_MULT
-
-#elif defined(MCU_STM32F205VE)
-	#define STM32_TICKS_PER_US          120
-    #define STM32_NR_GPIO_PORTS          5
-    #define STM32_DELAY_US_MULT         (STM32_TICKS_PER_US/3)
-    #define STM32_SRAM_END              ((void*)0x20010000)
-
-    #define NR_GPIO_PORTS               STM32_NR_GPIO_PORTS
-    #define DELAY_US_MULT               STM32_DELAY_US_MULT
-
-#elif defined(MCU_STM32F406VG)
+#if defined( STM32F4 )
 	#define STM32_TICKS_PER_US          168
     #define STM32_NR_GPIO_PORTS          5
     #define STM32_DELAY_US_MULT         (STM32_TICKS_PER_US/3)
diff --git a/STM32F4/cores/maple/libmaple/timer.c b/STM32F4/cores/maple/libmaple/timer.c
index 83e9ace33..f8e55a185 100644
--- a/STM32F4/cores/maple/libmaple/timer.c
+++ b/STM32F4/cores/maple/libmaple/timer.c
@@ -44,7 +44,7 @@
 /* Update only. */
 #define NR_BAS_HANDLERS                 1
 
-static timer_dev timer1 = {
+timer_dev timer1 = {
     .regs         = { .adv = TIMER1_BASE },
     .clk_id       = RCC_TIMER1,
     .type         = TIMER_ADVANCED,
@@ -53,7 +53,7 @@ static timer_dev timer1 = {
 /** Timer 1 device (advanced) */
 timer_dev *TIMER1 = &timer1;
 
-static timer_dev timer2 = {
+timer_dev timer2 = {
     .regs         = { .gen = TIMER2_BASE },
     .clk_id       = RCC_TIMER2,
     .type         = TIMER_GENERAL,
@@ -62,7 +62,7 @@ static timer_dev timer2 = {
 /** Timer 2 device (general-purpose) */
 timer_dev *TIMER2 = &timer2;
 
-static timer_dev timer3 = {
+timer_dev timer3 = {
     .regs         = { .gen = TIMER3_BASE },
     .clk_id       = RCC_TIMER3,
     .type         = TIMER_GENERAL,
@@ -71,7 +71,7 @@ static timer_dev timer3 = {
 /** Timer 3 device (general-purpose) */
 timer_dev *TIMER3 = &timer3;
 
-static timer_dev timer4 = {
+timer_dev timer4 = {
     .regs         = { .gen = TIMER4_BASE },
     .clk_id       = RCC_TIMER4,
     .type         = TIMER_GENERAL,
@@ -81,7 +81,7 @@ static timer_dev timer4 = {
 timer_dev *TIMER4 = &timer4;
 
 #ifdef STM32_HIGH_DENSITY
-static timer_dev timer5 = {
+timer_dev timer5 = {
     .regs         = { .gen = TIMER5_BASE },
     .clk_id       = RCC_TIMER5,
     .type         = TIMER_GENERAL,
@@ -90,7 +90,7 @@ static timer_dev timer5 = {
 /** Timer 5 device (general-purpose) */
 timer_dev *TIMER5 = &timer5;
 
-static timer_dev timer6 = {
+timer_dev timer6 = {
     .regs         = { .bas = TIMER6_BASE },
     .clk_id       = RCC_TIMER6,
     .type         = TIMER_BASIC,
@@ -99,7 +99,7 @@ static timer_dev timer6 = {
 /** Timer 6 device (basic) */
 timer_dev *TIMER6 = &timer6;
 
-static timer_dev timer7 = {
+timer_dev timer7 = {
     .regs         = { .bas = TIMER7_BASE },
     .clk_id       = RCC_TIMER7,
     .type         = TIMER_BASIC,
@@ -108,7 +108,7 @@ static timer_dev timer7 = {
 /** Timer 7 device (basic) */
 timer_dev *TIMER7 = &timer7;
 
-static timer_dev timer8 = {
+timer_dev timer8 = {
     .regs         = { .adv = TIMER8_BASE },
     .clk_id       = RCC_TIMER8,
     .type         = TIMER_ADVANCED,
diff --git a/STM32F4/cores/maple/libmaple/timer.h b/STM32F4/cores/maple/libmaple/timer.h
index fce6345b2..79b7d2996 100644
--- a/STM32F4/cores/maple/libmaple/timer.h
+++ b/STM32F4/cores/maple/libmaple/timer.h
@@ -113,13 +113,8 @@ typedef struct timer_bas_reg_map {
 } timer_bas_reg_map;
 
 
-#ifdef STM32F2
-  /** Timer 1 register map base pointer */
-  #define TIMER1_BASE        ((struct timer_adv_reg_map*)0x40010000)
-#else
-  /** Timer 1 register map base pointer */
-  #define TIMER1_BASE        ((struct timer_adv_reg_map*)0x40012C00)
-#endif
+/** Timer 1 register map base pointer */
+#define TIMER1_BASE        ((struct timer_adv_reg_map*)0x40010000)
 /** Timer 2 register map base pointer */
 #define TIMER2_BASE        ((struct timer_gen_reg_map*)0x40000000)
 /** Timer 3 register map base pointer */
@@ -133,14 +128,8 @@ typedef struct timer_bas_reg_map {
 #define TIMER6_BASE        ((struct timer_bas_reg_map*)0x40001000)
 /** Timer 7 register map base pointer */
 #define TIMER7_BASE        ((struct timer_bas_reg_map*)0x40001400)
-
-#ifdef STM32F2
-  /** Timer 8 register map base pointer */
-  #define TIMER8_BASE        ((struct timer_adv_reg_map*)0x40010400)
-#else
-  /** Timer 8 register map base pointer */
-  #define TIMER8_BASE        ((struct timer_adv_reg_map*)0x40013400)
-#endif
+/** Timer 8 register map base pointer */
+#define TIMER8_BASE        ((struct timer_adv_reg_map*)0x40010400)
 #endif
 
 /*
diff --git a/STM32F4/cores/maple/libmaple/usart.h b/STM32F4/cores/maple/libmaple/usart.h
index 3f7c88590..282293a17 100644
--- a/STM32F4/cores/maple/libmaple/usart.h
+++ b/STM32F4/cores/maple/libmaple/usart.h
@@ -62,11 +62,7 @@ typedef struct usart_reg_map {
 } usart_reg_map;
 
 /** USART1 register map base pointer */
-#ifdef STM32F2
-  #define USART1_BASE                   ((struct usart_reg_map*)0x40011000)
-#else
-  #define USART1_BASE                   ((struct usart_reg_map*)0x40013800)
-#endif
+#define USART1_BASE                   ((struct usart_reg_map*)0x40011000)
 /** USART2 register map base pointer */
 #define USART2_BASE                     ((struct usart_reg_map*)0x40004400)
 /** USART3 register map base pointer */
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_core.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_core.h
index f58ff0601..7ac987dcb 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_core.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_core.h
@@ -26,7 +26,7 @@
 
 #include "usbd_ioreq.h"
 #include "usbd_req.h"
-#include "usbd_desc.h"
+#include <VCP\usbd_desc.h>
 
 
 
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h
index 926f42e13..b1c8cc117 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h
@@ -24,7 +24,8 @@
 #ifndef __USB_CDC_CORE_H_
 #define __USB_CDC_CORE_H_
 
-#include  "usbd_ioreq.h"
+#include <STM32_USB_Device_Library\Core\inc/usbd_ioreq.h>
+#include <STM32_USB_OTG_Driver\inc\usb_core.h>
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_core.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_core.c
index aac6776cd..8f97c5176 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_core.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_core.c
@@ -58,9 +58,10 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include "usbd_cdc_core.h"
-#include "usbd_desc.h"
-#include "usbd_req.h"
+#include <VCP\usb_conf.h>
+#include <STM32_USB_Device_Library\Class\cdc\inc\usbd_cdc_core.h>
+#include <VCP\usbd_desc.h>
+#include <STM32_USB_Device_Library\Core\inc\usbd_req.h>
 
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_core.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_core.h
index b876856a3..063a30e69 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_core.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_core.h
@@ -24,9 +24,9 @@
 #define __USBD_CORE_H
 
 /* Includes ------------------------------------------------------------------*/
-#include "usb_dcd.h"
+#include <STM32_USB_OTG_Driver/inc/usb_dcd.h>
 #include "usbd_def.h"
-#include "usbd_conf.h"
+#include <VCP\usbd_conf.h>
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_def.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_def.h
index a8c86710d..f2a31153a 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_def.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_def.h
@@ -24,7 +24,7 @@
 #ifndef __USBD_DEF_H
 #define __USBD_DEF_H
 /* Includes ------------------------------------------------------------------*/
-#include "usbd_conf.h"
+#include <VCP\usbd_conf.h>
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_req.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_req.h
index 9aa9e44a3..f9849c6f9 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_req.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_req.h
@@ -27,7 +27,7 @@
 /* Includes ------------------------------------------------------------------*/
 #include  "usbd_def.h"
 #include  "usbd_core.h"
-#include  "usbd_conf.h"
+#include  <VCP\usbd_conf.h>
 
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_core.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_core.c
index af758427d..00bb25140 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_core.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_core.c
@@ -20,11 +20,11 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include "usbd_core.h"
-#include "usbd_req.h"
-#include "usbd_ioreq.h"
-#include "usb_dcd_int.h"
-#include "usb_bsp.h"
+#include <STM32_USB_Device_Library\Core\inc\usbd_core.h>
+#include <STM32_USB_Device_Library\Core\inc\usbd_req.h>
+#include <STM32_USB_Device_Library\Core\inc\usbd_ioreq.h>
+#include <STM32_USB_OTG_Driver\inc\usb_dcd_int.h>
+#include <STM32_USB_OTG_Driver\inc\usb_bsp.h>
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
 * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_ioreq.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_ioreq.c
index 6964766bd..20ee5a0f1 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_ioreq.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_ioreq.c
@@ -20,7 +20,7 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include "usbd_ioreq.h"
+#include <STM32_USB_Device_Library\Core\inc\usbd_ioreq.h>
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
   * @{
   */
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_req.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_req.c
index f08d26c6c..5fc2e036c 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_req.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_req.c
@@ -20,9 +20,9 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include "usbd_req.h"
-#include "usbd_ioreq.h"
-#include "usbd_desc.h"
+#include <STM32_USB_Device_Library\Core\inc\usbd_req.h>
+#include <STM32_USB_Device_Library\Core\inc\usbd_ioreq.h>
+#include <VCP\usbd_desc.h>
 
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_core.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_core.h
index 82a09e15c..43c478126 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_core.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_core.h
@@ -24,7 +24,7 @@
 #define __USB_CORE_H__
 
 /* Includes ------------------------------------------------------------------*/
-#include "usb_conf.h"
+#include <VCP\usbd_conf.h>
 #include "usb_regs.h"
 #include "usb_defines.h"
 
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_defines.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_defines.h
index 8c23d72d9..ee2c1a009 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_defines.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_defines.h
@@ -24,7 +24,7 @@
 #define __USB_DEF_H__
 
 /* Includes ------------------------------------------------------------------*/
-#include  "usb_conf.h"
+#include  <VCP\usbd_conf.h>
 
 /** @addtogroup USB_OTG_DRIVER
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_otg.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_otg.h
index 54d61b827..1347f315d 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_otg.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_otg.h
@@ -23,6 +23,7 @@
 #ifndef __USB_OTG__
 #define __USB_OTG__
 
+#include "usb_core.h"
 
 /** @addtogroup USB_OTG_DRIVER
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_regs.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_regs.h
index cd71ddfaf..99f844e58 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_regs.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_regs.h
@@ -24,8 +24,8 @@
 #define __USB_OTG_REGS_H__
 
 /* Includes ------------------------------------------------------------------*/
-#include "usb_conf.h"
-
+#include <VCP\usbd_conf.h>
+#include <libmaple\libmaple_types.h>
 
 /** @addtogroup USB_OTG_DRIVER
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_core.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_core.c
index cb9eabc8c..1687afa7c 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_core.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_core.c
@@ -20,8 +20,8 @@
   */
 
 /* Includes ------------------------------------------------------------------*/
-#include "usb_bsp.h"
-#include "usb_core.h"
+#include <STM32_USB_OTG_Driver\inc\usb_bsp.h>
+#include <STM32_USB_OTG_Driver\inc\usb_core.h>
 
 
 /** @addtogroup USB_OTG_DRIVER
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd.c
index c3336cb84..dc9e53839 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd.c
@@ -20,8 +20,8 @@
   */
 
 /* Includes ------------------------------------------------------------------*/
-#include "usb_dcd.h"
-#include "usb_bsp.h"
+#include <STM32_USB_OTG_Driver\inc\usb_dcd.h>
+#include <STM32_USB_OTG_Driver\inc\usb_bsp.h>
 
 
 /** @addtogroup USB_OTG_DRIVER
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd_int.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd_int.c
index 3a49ede25..f9e561f14 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd_int.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd_int.c
@@ -20,12 +20,12 @@
   */
 
 /* Includes ------------------------------------------------------------------*/
-#include "usb_dcd_int.h"
+#include <STM32_USB_OTG_Driver\inc\usb_dcd_int.h>
 
 typedef int IRQn_Type;
 #define __NVIC_PRIO_BITS          4
 #define __Vendor_SysTickConfig    1
-#include <core_cm4.h>
+#include <VCP\core_cm4.h>
 
 
 /** @addtogroup USB_OTG_DRIVER
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/core_cm4.h b/STM32F4/cores/maple/libmaple/usbF4/VCP/core_cm4.h
index 443665c70..ff5e9a6d4 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/core_cm4.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/core_cm4.h
@@ -141,7 +141,7 @@
 #endif
 
 #include <stdint.h>                      /*!< standard types definitions                      */
-#include <core_cmInstr.h>                /*!< Core Instruction Access                         */
+#include "core_cmInstr.h"                /*!< Core Instruction Access                         */
 //#include <core_cmFunc.h>                 /*!< Core Function Access                            */
 //#include <core_cm4_simd.h>               /*!< Compiler specific SIMD Intrinsics               */
 
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/misc.c b/STM32F4/cores/maple/libmaple/usbF4/VCP/misc.c
index 9f33150cf..15a715e87 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/misc.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/misc.c
@@ -80,7 +80,7 @@ typedef unsigned char		u8;
 typedef int IRQn_Type;
 #define __NVIC_PRIO_BITS          4
 #define __Vendor_SysTickConfig    1
-#include <core_cm4.h>
+#include "core_cm4.h"
 
 /** @addtogroup STM32F4xx_StdPeriph_Driver
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_bsp.c b/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_bsp.c
index df23ccbd7..e794cb144 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_bsp.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_bsp.c
@@ -21,13 +21,13 @@
   */
 
 /* Includes ------------------------------------------------------------------*/
-#include "usb_bsp.h"
+#include <STM32_USB_OTG_Driver\inc\usb_bsp.h>
 #include "usbd_conf.h"
-#include <gpio.h>
+#include <libmaple/gpio.h>
 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
 #define OTG_FS_IRQn 67
 //typedef unsigned char uint8_t;
-#include <misc.h>
+#include "misc.h"
 
 //#include "stm32f4_discovery.h"
 
@@ -97,10 +97,10 @@ void USB_OTG_BSP_Init(USB_OTG_CORE_HANDLE *pdev)
 {
 	// ala42
 #define GPIO_AF_OTG1_FS         ((uint8_t)0xA)  /* OTG_FS Alternate Function mapping */
-	gpio_set_mode(GPIOA,11,GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
-	gpio_set_mode(GPIOA,12,GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
-	gpio_set_af_mode(GPIOA,11,GPIO_AF_OTG1_FS) ;	// OTG_FS_DM
-	gpio_set_af_mode(GPIOA,12,GPIO_AF_OTG1_FS) ;	// OTG_FS_DP
+	gpio_set_mode(BOARD_USB_DM_PIN,GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
+	gpio_set_mode(BOARD_USB_DP_PIN,GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
+	gpio_set_af_mode(BOARD_USB_DM_PIN,GPIO_AF_OTG1_FS) ;	// OTG_FS_DM
+	gpio_set_af_mode(BOARD_USB_DP_PIN,GPIO_AF_OTG1_FS) ;	// OTG_FS_DP
 #ifdef USB_OTG_FS_SOF_OUTPUT_ENABLED
 	gpio_set_mode(GPIOA, 8,GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
 	gpio_set_af_mode(GPIOA, 8,GPIO_AF_OTG1_FS) ;		// OTG_FS_SOF
@@ -122,10 +122,10 @@ void USB_OTG_BSP_DeInit(USB_OTG_CORE_HANDLE *pdev)
 {
 	// ala42
 #define GPIO_AF0         ((uint8_t)0)  /* OTG_FS Alternate Function mapping */
-	gpio_set_mode(GPIOA,11, GPIO_MODE_INPUT);
-	gpio_set_mode(GPIOA,12, GPIO_MODE_INPUT);
-	gpio_set_af_mode(GPIOA,11,GPIO_AF0) ;	// OTG_FS_DM
-	gpio_set_af_mode(GPIOA,12,GPIO_AF0) ;	// OTG_FS_DP
+	gpio_set_mode(BOARD_USB_DM_PIN, GPIO_MODE_INPUT);
+	gpio_set_mode(BOARD_USB_DP_PIN, GPIO_MODE_INPUT);
+	gpio_set_af_mode(BOARD_USB_DM_PIN,GPIO_AF0) ;	// OTG_FS_DM
+	gpio_set_af_mode(BOARD_USB_DP_PIN,GPIO_AF0) ;	// OTG_FS_DP
 #ifdef USB_OTG_FS_SOF_OUTPUT_ENABLED
 	gpio_set_mode(GPIOA, 8,GPIO_MODE_INPUT);
 	gpio_set_af_mode(GPIOA, 8,GPIO_AF0) ;		// OTG_FS_SOF
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_conf.h b/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_conf.h
index 61b0ac50c..fd45f4db3 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_conf.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_conf.h
@@ -173,7 +173,9 @@ typedef unsigned char		u8;
 #elif defined (__ICCARM__)     /* IAR Compiler */
   #define __packed    __packed
 #elif defined   ( __GNUC__ )   /* GNU Compiler */
+ #ifndef __packed
   #define __packed    __attribute__ ((__packed__))
+ #endif
 #elif defined   (__TASKING__)  /* TASKING Compiler */
   #define __packed    __unaligned
 #endif /* __CC_ARM */
@@ -206,7 +208,9 @@ typedef unsigned char		u8;
 #elif defined (__ICCARM__)     /* IAR Compiler */
   #define __packed    __packed
 #elif defined   ( __GNUC__ )   /* GNU Compiler */
+ #ifndef __packed
   #define __packed    __attribute__ ((__packed__))
+ #endif
 #elif defined   (__TASKING__)  /* TASKING Compiler */
   #define __packed    __unaligned
 #endif /* __CC_ARM */
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.c b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.c
index b13260ee5..28a2d1ff2 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.c
@@ -255,7 +255,7 @@ typedef struct {
 
 void systemHardReset(void) {
     SCB_TypeDef* rSCB = (SCB_TypeDef *) SCB_BASE;
-    typedef void (*funcPtr)(void);
+    //typedef void (*funcPtr)(void); // not used
 
     /* Reset */
     rSCB->AIRCR = (u32)AIRCR_RESET_REQ;
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.h b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.h
index 67475e7a4..8398dbdbb 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.h
@@ -26,7 +26,7 @@
 /* Includes ------------------------------------------------------------------*/
 //#include "stm32f4xx.h"
 
-#include "usbd_cdc_core.h"
+#include <STM32_USB_Device_Library\Class\cdc\inc\usbd_cdc_core.h>
 #include "usbd_conf.h"
 
 
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_conf.h b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_conf.h
index 516a2fbb3..62a40c27c 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_conf.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_conf.h
@@ -25,6 +25,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 //#include   "stm32f4_discovery.h"
+#include "usb_conf.h"
 
 /** @defgroup USB_CONF_Exported_Defines
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.c b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.c
index 537f2665c..0153858fc 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.c
@@ -20,11 +20,11 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include "usbd_core.h"
+#include <STM32_USB_Device_Library\Core\inc\usbd_core.h>
 #include "usbd_desc.h"
-#include "usbd_req.h"
+#include <STM32_USB_Device_Library\Core\inc\usbd_req.h>
 #include "usbd_conf.h"
-#include "usb_regs.h"
+#include <STM32_USB_OTG_Driver\inc\usb_regs.h>
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.h b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.h
index ed999dc62..4ae998cee 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.h
@@ -25,7 +25,7 @@
 #define __USB_DESC_H
 
 /* Includes ------------------------------------------------------------------*/
-#include "usbd_def.h"
+#include <STM32_USB_Device_Library\Core\inc\usbd_def.h>
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_usr.c b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_usr.c
index 84e8d6a54..a16ce40c5 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_usr.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_usr.c
@@ -20,8 +20,8 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include "usbd_usr.h"
-#include "usbd_ioreq.h"
+#include <STM32_USB_Device_Library\Core\inc\usbd_usr.h>
+#include <STM32_USB_Device_Library\Core\inc\usbd_ioreq.h>
 
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
diff --git a/STM32F4/cores/maple/libmaple/usbF4/usb.c b/STM32F4/cores/maple/libmaple/usbF4/usb.c
index 2c0672f6a..385071982 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/usb.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/usb.c
@@ -1,27 +1,30 @@
-#include "usbd_cdc_core.h"
-#include "usbd_usr.h"
-#include "usbd_desc.h"
+#ifndef _USBF4_USB_H_
+#define _USBF4_USB_H_
+
+
+#include <STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h>
+#include <STM32_USB_Device_Library/Core/inc/usbd_usr.h>
+#include <VCP\usbd_desc.h>
 #include "usb.h"
-#include <gpio.h>
-#include <rccF2.h>
-#include <usbd_cdc_vcp.h>
+#include <libmaple/gpio.h>
+#include <libmaple/rccF4.h>
+#include <VCP\usbd_cdc_vcp.h>
+#include <boards.h>
 
 USB_OTG_CORE_HANDLE  USB_OTG_dev;
 
 
 
-void setupUSB (void) {
-    #define USB_DISC_DEV         GPIOD
-    #define USB_DISC_PIN         11
-
-	gpio_set_mode(USB_DISC_DEV, USB_DISC_PIN, GPIO_OUTPUT_OD); // ala42
+void setupUSB (void)
+{
+	gpio_set_mode(BOARD_USB_DP_PIN, GPIO_OUTPUT_OD); // ala42
 #ifdef USB_DISC_OD
   //gpio_set_mode(USB_DISC_DEV, USB_DISC_PIN, GPIO_OUTPUT_OD); // ala42
 #else
   //gpio_set_mode(USB_DISC_DEV, USB_DISC_PIN, GPIO_OUTPUT_PP); // ala42 for active pull-up on disconnect pin
 #endif
 
-  gpio_write_bit(USB_DISC_DEV, USB_DISC_PIN,0); // ala42
+  gpio_clear_pin(BOARD_USB_DP_PIN); // ala42
   delay_us(200000);
 
   /* setup the apb1 clock for USB */
@@ -29,7 +32,7 @@ void setupUSB (void) {
   //pRCC->APB1ENR |= RCC_APB1ENR_USBEN;
 
   /* initialize the usb application */
-  gpio_write_bit(USB_DISC_DEV, USB_DISC_PIN, 1); // ala42 // presents us to the host
+  gpio_set_pin(BOARD_USB_DP_PIN); // ala42 // presents us to the host
   USBD_Init(&USB_OTG_dev,
             USB_OTG_FS_CORE_ID,
             &USR_desc,
@@ -93,7 +96,7 @@ RESULT usbPowerOff(void) {
 
 void usbDsbISR(void) {};
 
-#include "usb_dcd_int.h"
+#include <STM32_USB_OTG_Driver\inc\usb_dcd_int.h>
 void __irq_OTG_FS_IRQHandler(void)
 {
   USBD_OTG_ISR_Handler (&USB_OTG_dev);
@@ -102,3 +105,5 @@ void __irq_OTG_FS_IRQHandler(void)
 void x__irq_usbwakeup(void)
 {
 }
+
+#endif
diff --git a/STM32F4/cores/maple/libmaple/usbF4/usb.h b/STM32F4/cores/maple/libmaple/usbF4/usb.h
index f09f2bd0c..ce1a5585f 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/usb.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/usb.h
@@ -5,7 +5,7 @@
 extern "C" {
 #endif
 
-#include "usb_conf.h"
+#include <VCP\usb_conf.h>
 
 typedef enum _RESULT
 {
diff --git a/STM32F4/cores/maple/libmaple/util.c b/STM32F4/cores/maple/libmaple/util.c
index 8c03e1865..8a745e87d 100644
--- a/STM32F4/cores/maple/libmaple/util.c
+++ b/STM32F4/cores/maple/libmaple/util.c
@@ -128,7 +128,7 @@ void throb(void) {
     uint32 TOP_CNT = 0x0800;
     uint32 i       = 0;
 
-    gpio_set_mode(ERROR_LED_PORT, ERROR_LED_PIN, GPIO_OUTPUT_PP);
+    gpio_set_mode(ERROR_LED_PIN, GPIO_OUTPUT_PP);
     /* Error fade. */
     while (1) {
         if (CC == TOP_CNT)  {
@@ -143,9 +143,9 @@ void throb(void) {
         }
 
         if (i < CC) {
-            gpio_write_bit(ERROR_LED_PORT, ERROR_LED_PIN, 1);
+            gpio_set_pin(ERROR_LED_PIN);
         } else {
-            gpio_write_bit(ERROR_LED_PORT, ERROR_LED_PIN, 0);
+            gpio_clear_pin(ERROR_LED_PIN);
         }
         i++;
     }
diff --git a/STM32F4/cores/maple/libmaple/util.h b/STM32F4/cores/maple/libmaple/util.h
index 62ad8af37..c5ed2de07 100644
--- a/STM32F4/cores/maple/libmaple/util.h
+++ b/STM32F4/cores/maple/libmaple/util.h
@@ -29,11 +29,12 @@
  * @brief Miscellaneous utility macros and procedures.
  */
 
-#include "libmaple_types.h"
-
 #ifndef _UTIL_H_
 #define _UTIL_H_
 
+#include "libmaple_types.h"
+#include "delay.h"
+
 #ifdef __cplusplus
 extern "C"{
 #endif
diff --git a/STM32F4/cores/maple/pwm.cpp b/STM32F4/cores/maple/pwm.cpp
index 1806348c2..c5f2ccbc6 100644
--- a/STM32F4/cores/maple/pwm.cpp
+++ b/STM32F4/cores/maple/pwm.cpp
@@ -28,8 +28,8 @@
  *  @brief Arduino-style PWM implementation.
  */
 
-#include "libmaple_types.h"
-#include "timer.h"
+#include <libmaple/libmaple_types.h>
+#include <libmaple/timer.h>
 
 #include "boards.h"
 #include "pwm.h"
diff --git a/STM32F4/cores/maple/usb_serial.cpp b/STM32F4/cores/maple/usb_serial.cpp
index cc726c2e2..fadcb91af 100644
--- a/STM32F4/cores/maple/usb_serial.cpp
+++ b/STM32F4/cores/maple/usb_serial.cpp
@@ -33,6 +33,8 @@
 #include "wirish.h"
 #include "usb.h"
 
+#ifdef SERIAL_USB
+
 #define USB_TIMEOUT 50
 
 USBSerial::USBSerial(void) {
@@ -132,7 +134,7 @@ uint8 USBSerial::pending(void) {
     return usbGetPending();
 }
 
-uint8 USBSerial::isConnected(void) {
+USBSerial::operator bool() {
     return usbIsConnected() && usbIsConfigured();
 }
 
@@ -153,3 +155,5 @@ void USBSerial::disableBlockingTx(void) {
 }
 
 USBSerial SerialUSB;
+
+#endif
diff --git a/STM32F4/cores/maple/usb_serial.h b/STM32F4/cores/maple/usb_serial.h
index a551e9d4b..8eeed966a 100644
--- a/STM32F4/cores/maple/usb_serial.h
+++ b/STM32F4/cores/maple/usb_serial.h
@@ -33,6 +33,8 @@
 
 #include "Stream.h"
 
+#ifdef SERIAL_USB
+
 /**
  * @brief Virtual serial terminal.
  */
@@ -57,7 +59,8 @@ class USBSerial : public Stream {
 
     uint8 getRTS();
     uint8 getDTR();
-    uint8 isConnected();
+	operator bool();
+	uint8 isConnected() { return (bool) *this; }
     uint8 pending();
 
     void enableBlockingTx(void);
@@ -65,6 +68,14 @@ class USBSerial : public Stream {
 };
 
 extern USBSerial SerialUSB;
+#define Serial SerialUSB
+
+#else //  _USB_SERIAL_H_
+
+#define Serial Serial1
+
+#endif //  SERIAL_USB
+
 
-#endif
+#endif //  _USB_SERIAL_H_
 
diff --git a/STM32F4/cores/maple/wirish.h b/STM32F4/cores/maple/wirish.h
index 4aca74c0b..945e8fb94 100644
--- a/STM32F4/cores/maple/wirish.h
+++ b/STM32F4/cores/maple/wirish.h
@@ -34,9 +34,9 @@
 #define _WIRISH_H_
 
 #include <stdlib.h>
-#include "libmaple.h"
+#include <stdio.h>
+#include <stdint.h>
 
-#include "wirish_types.h"
 #include "boards.h"
 #include "io.h"
 #include "bits.h"
@@ -44,10 +44,8 @@
 #include "ext_interrupts.h"
 #include "wirish_debug.h"
 #include "wirish_math.h"
-#include "wirish_time.h"
 #include <wirish_constants.h>
-#include "HardwareSPI.h"
-#include "HardwareSerial.h"
+#include <libmaple/HardwareSerial.h>
 #include "HardwareTimer.h"
 #include "usb_serial.h"
 
@@ -55,9 +53,10 @@
 #define HIGH 0x1
 #define LOW  0x0
 
-#define true 0x1
-#define false 0x0
-
+#ifndef true
+  #define true 0x1
+  #define false 0x0
+#endif
 
 #define lowByte(w)                     ((w) & 0xFF)
 #define highByte(w)                    (((w) >> 8) & 0xFF)
diff --git a/STM32F4/cores/maple/wirish_analog.cpp b/STM32F4/cores/maple/wirish_analog.cpp
index 63b5eb2d0..4e920e7c7 100644
--- a/STM32F4/cores/maple/wirish_analog.cpp
+++ b/STM32F4/cores/maple/wirish_analog.cpp
@@ -28,9 +28,7 @@
  *  @brief Arduino-compatible ADC implementation.
  */
 
-#include "libmaple.h"
 #include "wirish.h"
-#include "io.h"
 
 /* Assumes that the ADC has been initialized and that the pin is set
  * to INPUT_ANALOG */
diff --git a/STM32F4/cores/maple/wirish_constants.h b/STM32F4/cores/maple/wirish_constants.h
index 06a85ae8c..f39c0777e 100644
--- a/STM32F4/cores/maple/wirish_constants.h
+++ b/STM32F4/cores/maple/wirish_constants.h
@@ -1,5 +1,5 @@
-#ifndef _WIRING_CONSTANTS_
-#define _WIRING_CONSTANTS_
+#ifndef _WIRISH_CONSTANTS_H_
+#define _WIRISH_CONSTANTS_H_
 
 #ifdef __cplusplus
 extern "C"{
diff --git a/STM32F4/cores/maple/wirish_debug.h b/STM32F4/cores/maple/wirish_debug.h
index d4c0bab4d..d7dea2391 100644
--- a/STM32F4/cores/maple/wirish_debug.h
+++ b/STM32F4/cores/maple/wirish_debug.h
@@ -24,6 +24,9 @@
  * SOFTWARE.
  *****************************************************************************/
 
+#ifndef _WIRISH_DEBUG_H_
+#define _WIRISH_DEBUG_H_
+
 /**
  * @file wirish_debug.h
  * @brief High level debug port configuration
@@ -50,5 +53,7 @@ static inline void disableDebugPorts(void) {
  * @see disableDebugPorts()
  */
 static inline void enableDebugPorts(void) {
-    afio_cfg_debug_ports(AFIO_DEBUG_FULL_SWJ);
+    afio_cfg_debug_ports(AFIO_DEBUG_SW_ONLY); //AFIO_DEBUG_FULL_SWJ);
 }
+
+#endif
diff --git a/STM32F4/cores/maple/wirish_digital.cpp b/STM32F4/cores/maple/wirish_digital.cpp
index a8b3ad811..4a656199b 100644
--- a/STM32F4/cores/maple/wirish_digital.cpp
+++ b/STM32F4/cores/maple/wirish_digital.cpp
@@ -29,7 +29,7 @@
  */
 
 #include "wirish.h"
-#include "io.h"
+
 
 void pinMode(uint8 pin, WiringPinMode mode) {
     gpio_pin_mode outputMode;
@@ -72,7 +72,7 @@ void pinMode(uint8 pin, WiringPinMode mode) {
         return;
     }
 
-    gpio_set_mode(PIN_MAP[pin].gpio_device, PIN_MAP[pin].gpio_bit, outputMode);
+    gpio_set_mode(pin, outputMode);
 
     if (PIN_MAP[pin].timer_device != NULL) {
         /* Enable/disable timer channels if we're switching into or
@@ -84,48 +84,51 @@ void pinMode(uint8 pin, WiringPinMode mode) {
 }
 
 
-uint32 digitalRead(uint8 pin) {
+uint32 digitalRead(uint8 pin)
+{
     if (pin >= BOARD_NR_GPIO_PINS) {
         return 0;
     }
 
-    return gpio_read_bit(PIN_MAP[pin].gpio_device, PIN_MAP[pin].gpio_bit) ?
+    return gpio_read_pin(pin) ?
         HIGH : LOW;
 }
 
-void digitalWrite(uint8 pin, uint8 val) {
+void digitalWrite(uint8 pin, uint8 val)
+{
     if (pin >= BOARD_NR_GPIO_PINS) {
         return;
     }
 
-    gpio_write_bit(PIN_MAP[pin].gpio_device, PIN_MAP[pin].gpio_bit, val);
+    gpio_write_pin(pin, val);
 }
 
-void togglePin(uint8 pin) {
+void togglePin(uint8 pin)
+{
     if (pin >= BOARD_NR_GPIO_PINS) {
         return;
     }
 
-    gpio_toggle_bit(PIN_MAP[pin].gpio_device, PIN_MAP[pin].gpio_bit);
+    gpio_toggle_pin(pin);
 }
 
 #define BUTTON_DEBOUNCE_DELAY 1
 
-uint8 isButtonPressed() {
-    if (digitalRead(BOARD_BUTTON_PIN)) {
+uint8 isButtonPressed(uint8_t button) {
+    if (digitalRead(button)) {
         delay(BUTTON_DEBOUNCE_DELAY);
-        while (digitalRead(BOARD_BUTTON_PIN))
+        while (digitalRead(button))
             ;
         return true;
     }
     return false;
 }
 
-uint8 waitForButtonPress(uint32 timeout) {
+uint8 waitForButtonPress(uint8_t button, uint32 timeout) {
     uint32 start = millis();
     uint32 time;
     if (timeout == 0) {
-        while (!isButtonPressed())
+        while (!isButtonPressed(button))
             ;
         return true;
     }
@@ -136,6 +139,6 @@ uint8 waitForButtonPress(uint32 timeout) {
             time - start > timeout) {
             return false;
         }
-    } while (!isButtonPressed());
+    } while (!isButtonPressed(button));
     return true;
 }
diff --git a/STM32F4/cores/maple/wirish_math.h b/STM32F4/cores/maple/wirish_math.h
index a85b30ada..0b8b22260 100644
--- a/STM32F4/cores/maple/wirish_math.h
+++ b/STM32F4/cores/maple/wirish_math.h
@@ -29,8 +29,8 @@
  * @brief Includes <math.h>; provides Arduino-compatible math routines.
  */
 
-#ifndef _WIRING_MATH_H_
-#define _WIRING_MATH_H_
+#ifndef _WIRISH_MATH_H_
+#define _WIRISH_MATH_H_
 
 #include <math.h>
 
diff --git a/STM32F4/cores/maple/wirish_time.cpp b/STM32F4/cores/maple/wirish_time.cpp
index 270da28ac..654c1a2d2 100644
--- a/STM32F4/cores/maple/wirish_time.cpp
+++ b/STM32F4/cores/maple/wirish_time.cpp
@@ -28,10 +28,10 @@
  *  @brief Delay implementation.
  */
 
-#include "libmaple.h"
-#include "systick.h"
+#include <libmaple/libmaple.h>
+#include <libmaple/systick.h>
 #include "wirish_time.h"
-#include "delay.h"
+#include <libmaple/delay.h>
 
 void delay(unsigned long ms) {
     uint32 i;
diff --git a/STM32F4/cores/maple/wirish_time.h b/STM32F4/cores/maple/wirish_time.h
index 20a2fbfc4..3a117863c 100644
--- a/STM32F4/cores/maple/wirish_time.h
+++ b/STM32F4/cores/maple/wirish_time.h
@@ -32,10 +32,9 @@
 #ifndef __WIRISH_TIME_H_
 #define __WIRISH_TIME_H_
 
-#include "libmaple.h"
-#include "nvic.h"
-#include "systick.h"
 #include "boards.h"
+#include <libmaple/nvic.h>
+#include <libmaple/systick.h>
 
 #define US_PER_MS               1000
 
diff --git a/STM32F4/cores/maple/wirish_types.h b/STM32F4/cores/maple/wirish_types.h
index a3c260a73..6a8c85c3e 100644
--- a/STM32F4/cores/maple/wirish_types.h
+++ b/STM32F4/cores/maple/wirish_types.h
@@ -30,14 +30,13 @@
  * @brief  Wirish library type definitions.
  */
 
-#include "libmaple_types.h"
-#include "gpio.h"
-#include "timer.h"
-#include "adc.h"
-
 #ifndef _WIRISH_TYPES_H_
 #define _WIRISH_TYPES_H_
 
+#include <libmaple/gpio_def.h>
+#include <libmaple/timer.h>
+#include <libmaple/adc.h>
+
 /**
  * Invalid stm32_pin_info adc_channel value.
  * @see stm32_pin_info
@@ -48,6 +47,18 @@
  * @brief Stores STM32-specific information related to a given Maple pin.
  * @see PIN_MAP
  */
+#ifdef BOARD_generic_f407v
+// restructure members to build consecutive pairs
+typedef struct stm32_pin_info {
+    const gpio_dev * gpio_device;      /**< Maple pin's GPIO device */
+    timer_dev * timer_device;    /**< Pin's timer device, if any. */
+    uint8 timer_channel;        /**< Timer channel, or 0 if none. */
+    uint8 adc_channel;          /**< Pin ADC channel, or ADCx if none. */
+    const adc_dev *adc_device;  /**< ADC device, if any. */
+} stm32_pin_info;
+
+#else
+
 typedef struct stm32_pin_info {
     gpio_dev *gpio_device;      /**< Maple pin's GPIO device */
     timer_dev *timer_device;    /**< Pin's timer device, if any. */
@@ -58,6 +69,8 @@ typedef struct stm32_pin_info {
     uint8 filler;
 } stm32_pin_info;
 
+#endif
+
 /**
  * Variable attribute, instructs the linker to place the marked
  * variable in Flash instead of RAM. */
diff --git a/STM32F4/libraries/SPI/library.properties b/STM32F4/libraries/SPI/library.properties
index 6f20f0185..ba3a57704 100644
--- a/STM32F4/libraries/SPI/library.properties
+++ b/STM32F4/libraries/SPI/library.properties
@@ -7,3 +7,4 @@ paragraph=SPI for STM32F4
 category=Communication
 url=
 architectures=STM32F4
+maintainer=
\ No newline at end of file
diff --git a/STM32F4/libraries/SPI/src/SPI.cpp b/STM32F4/libraries/SPI/src/SPI.cpp
index 08fbbd5d7..cb8f561c9 100644
--- a/STM32F4/libraries/SPI/src/SPI.cpp
+++ b/STM32F4/libraries/SPI/src/SPI.cpp
@@ -40,9 +40,9 @@
 #include "wirish.h"
 #include "boards.h"
 
-//#include "HardwareSerial.h"
+#define DMA_TIMEOUT 100
 
-#if CYCLES_PER_MICROSECOND != 72
+#if CYCLES_PER_MICROSECOND != 168
 /* TODO [0.2.0?] something smarter than this */
 #warning "Unexpected clock speed; SPI frequency calculation will be incorrect"
 #endif
@@ -91,77 +91,115 @@ static const spi_pins board_spi_pins[] __FLASH__ = {
  */
 
 SPIClass::SPIClass(uint32 spi_num) {
+
+	_currentSetting=&_settings[spi_num-1];// SPI channels are called 1 2 and 3 but the array is zero indexed
+
+	
     switch (spi_num) {
 #if BOARD_NR_SPI >= 1
     case 1:
-        this->spi_d = SPI1;
+        _currentSetting->spi_d = SPI1;
         break;
 #endif
 #if BOARD_NR_SPI >= 2
     case 2:
-        this->spi_d = SPI2;
+        _currentSetting->spi_d = SPI2;
         break;
 #endif
 #if BOARD_NR_SPI >= 3
     case 3:
-        this->spi_d = SPI3;
+        _currentSetting->spi_d = SPI3;
         break;
 #endif
     default:
         ASSERT(0);
     }
 	
-    //pinMode(BOARD_SPI_DEFAULT_SS,OUTPUT);
-    
-    clockDivider = SPI_BAUD_PCLK_DIV_16;
-    dataMode = SPI_MODE0;
+	// Init things specific to each SPI device
+	// clock divider setup is a bit of hack, and needs to be improved at a later date.
+/*****************************************************************************/
+//           DMA / Channel / Stream 
+//            Rx             Tx
+// SPI1:  2 / 3 / 0 (2) - 2 / 3 / 3 (5)
+// SPI2:  1 / 0 / 3     - 1 / 0 / 4
+// SPI3:  1 / 0 / 0 (2) - 1 / 0 / 5 (7)
+/*****************************************************************************/
+	_settings[0].spi_d = SPI1;
+	_settings[0].clockDivider = determine_baud_rate(_settings[0].spi_d, _settings[0].clock);
+#ifdef SPI_DMA
+	_settings[0].spiDmaDev = DMA2;
+	_settings[0].spiDmaChannel = DMA_CH3;
+	_settings[0].spiRxDmaStream  = DMA_STREAM0; // alternative: DMA_STREAM2
+	_settings[0].spiTxDmaStream  = DMA_STREAM3; // alternative: DMA_STREAM5
+#endif
+	_settings[1].spi_d = SPI2;
+	_settings[1].clockDivider = determine_baud_rate(_settings[1].spi_d, _settings[1].clock);
+#ifdef SPI_DMA
+	_settings[1].spiDmaDev = DMA1;
+	_settings[1].spiDmaChannel = DMA_CH0;
+	_settings[1].spiRxDmaStream  = DMA_STREAM3; // alternative: -
+	_settings[1].spiTxDmaStream  = DMA_STREAM4; // alternative: -
+#endif
+#if BOARD_NR_SPI >= 3
+	_settings[2].spi_d = SPI3;
+	_settings[2].clockDivider = determine_baud_rate(_settings[2].spi_d, _settings[2].clock);
+#ifdef SPI_DMA
+	_settings[2].spiDmaDev = DMA1;
+	_settings[2].spiDmaChannel = DMA_CH0;
+	_settings[2].spiRxDmaStream  = DMA_STREAM0; // alternative: DMA_STREAM2
+	_settings[2].spiTxDmaStream  = DMA_STREAM5; // alternative: DMA_STREAM7
+#endif
+#endif
+
 }
 
 /*
  * Set up/tear down
  */
-
-void SPIClass::begin(void) {
-
-    uint32 flags = ((bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | SPI_DFF_8_BIT | SPI_SW_SLAVE | SPI_SOFT_SS);
-    spi_init(spi_d);
-    configure_gpios(spi_d, 1);
+void SPIClass::updateSettings(void) {
+	uint32 flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | _currentSetting->dataSize | SPI_SW_SLAVE | SPI_SOFT_SS);
 	#ifdef SPI_DEBUG
-	Serial.print("spi_master_enable("); Serial.print(clockDivider); Serial.print(","); Serial.print(dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
+	Serial.print("spi_master_enable("); Serial.print(_currentSetting->clockDivider); Serial.print(","); Serial.print(_currentSetting->dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
 	#endif
-    spi_master_enable(spi_d, (spi_baud_rate)clockDivider, (spi_mode)dataMode, flags);
+	spi_master_enable(_currentSetting->spi_d, (spi_baud_rate)_currentSetting->clockDivider, (spi_mode)_currentSetting->dataMode, flags);
+}
+
+void SPIClass::begin(void) {
+    spi_init(_currentSetting->spi_d);
+    configure_gpios(_currentSetting->spi_d, 1);
+    updateSettings();
+#ifdef SPI_USE_DMA_BUFFER
+	dmaSendBufferInit();
+#endif
+//Serial.println("SPI class begin - end");
 }
 
 void SPIClass::beginSlave(void) {
-    if (dataMode >= 4) {
-        ASSERT(0);
-        return;
-    }
-    uint32 flags = ((bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | SPI_DFF_8_BIT | SPI_SW_SLAVE);
-    spi_init(spi_d);
-    configure_gpios(spi_d, 0);
+    spi_init(_currentSetting->spi_d);
+    configure_gpios(_currentSetting->spi_d, 0);
+    uint32 flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | _currentSetting->dataSize | SPI_RX_ONLY);
 	#ifdef SPI_DEBUG
-	Serial.print("spi_slave_enable("); Serial.print(dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
+	Serial.print("spi_slave_enable("); Serial.print(_currentSetting->dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
 	#endif
-    spi_slave_enable(spi_d, (spi_mode)dataMode, flags);
+    spi_slave_enable(_currentSetting->spi_d, (spi_mode)_currentSetting->dataMode, flags);
 }
 
 void SPIClass::end(void) {
-    if (!spi_is_enabled(this->spi_d)) {
+    if (!spi_is_enabled(_currentSetting->spi_d)) {
         return;
     }
 
     // Follows RM0008's sequence for disabling a SPI in master/slave
     // full duplex mode.
-    while (spi_is_rx_nonempty(this->spi_d)) {
+    while (spi_is_rx_nonempty(_currentSetting->spi_d)) {
         // FIXME [0.1.0] remove this once you have an interrupt based driver
-        volatile uint16 rx __attribute__((unused)) = spi_rx_reg(this->spi_d);
+        volatile uint16 rx __attribute__((unused)) = spi_rx_reg(_currentSetting->spi_d);
     }
-    while (!spi_is_tx_empty(this->spi_d))
+    while (!spi_is_tx_empty(_currentSetting->spi_d))
         ;
-    while (spi_is_busy(this->spi_d))
+    while (spi_is_busy(_currentSetting->spi_d))
         ;
-    spi_peripheral_disable(this->spi_d);
+    spi_peripheral_disable(_currentSetting->spi_d);
 }
 
 /* Roger Clark added  3 functions */
@@ -170,8 +208,9 @@ void SPIClass::setClockDivider(uint32_t clockDivider)
 	#ifdef SPI_DEBUG
 	Serial.print("Clock divider set to "); Serial.println(clockDivider);
 	#endif
-	this->clockDivider = clockDivider;
-	this->begin();
+	_currentSetting->clockDivider = clockDivider;
+	uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_BR);
+	_currentSetting->spi_d->regs->CR1 = cr1 | (clockDivider & SPI_CR1_BR);
 }
 
 void SPIClass::setBitOrder(BitOrder bitOrder)
@@ -179,8 +218,10 @@ void SPIClass::setBitOrder(BitOrder bitOrder)
 	#ifdef SPI_DEBUG
 	Serial.print("Bit order set to "); Serial.println(bitOrder);
 	#endif
-	this->bitOrder = bitOrder;
-	this->begin();
+	_currentSetting->bitOrder = bitOrder;
+	uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_LSBFIRST);
+	if ( bitOrder==LSBFIRST )	cr1 |= SPI_CR1_LSBFIRST;
+	_currentSetting->spi_d->regs->CR1 = cr1;
 }
 
 /*	Victor Perez. Added to test changing datasize from 8 to 16 bit modes on the fly.
@@ -189,11 +230,11 @@ void SPIClass::setBitOrder(BitOrder bitOrder)
 */
 void SPIClass::setDataSize(uint32 datasize)
 {
-		uint32 cr1 = this->spi_d->regs->CR1; 
-		datasize &= SPI_CR1_DFF;
-		cr1 &= ~(SPI_CR1_DFF); 
-		cr1 |= datasize;  
-		this->spi_d->regs->CR1 = cr1; 
+	_currentSetting->dataSize = datasize;
+	uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_DFF);
+	uint8 en = spi_is_enabled(_currentSetting->spi_d);
+	spi_peripheral_disable(_currentSetting->spi_d);
+	_currentSetting->spi_d->regs->CR1 = cr1 | (datasize & SPI_CR1_DFF) | en;
 }
 
 void SPIClass::setDataMode(uint8_t dataMode)
@@ -212,13 +253,11 @@ SPI Mode 	CPOL 	CPHA 	Shift SCK-edge 	Capture SCK-edge
 On the STM32 it appears to be
 
 bit 1 - CPOL : Clock polarity
-
     (This bit should not be changed when communication is ongoing)
     0 : CLK to 0 when idle
     1 : CLK to 1 when idle
  
 bit 0 - CPHA : Clock phase
-
     (This bit should not be changed when communication is ongoing)
     0 : The first clock transition is the first data capture edge
     1 : The second clock transition is the first data capture edge
@@ -228,44 +267,32 @@ If someone finds this is not the case or sees a logic error with this let me kno
 	#ifdef SPI_DEBUG
 	Serial.print("Data mode set to "); Serial.println(dataMode);
 	#endif
-	this->dataMode = dataMode;
-	this->begin();
-}	
-
+	_currentSetting->dataMode = dataMode;
+	uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_CPOL|SPI_CR1_CPHA);
+	_currentSetting->spi_d->regs->CR1 = cr1 | (dataMode & (SPI_CR1_CPOL|SPI_CR1_CPHA));
+}
 
 void SPIClass::beginTransaction(uint8_t pin, SPISettings settings)
 {
 	#ifdef SPI_DEBUG
 	Serial.println("SPIClass::beginTransaction");
 	#endif
-	//_SSPin=pin;
-	//pinMode(_SSPin,OUTPUT);
-	//digitalWrite(_SSPin,LOW);
 	setBitOrder(settings.bitOrder);
 	setDataMode(settings.dataMode);
-	setClockDivider(determine_baud_rate(spi_d, settings.clock));
+	setDataSize(settings.dataSize);
+	setClockDivider(determine_baud_rate(_currentSetting->spi_d, settings.clock));
 	begin();
-#if 0
-// code from SAM core	
-	uint8_t mode = interruptMode;
-	if (mode > 0) {
-		if (mode < 16) {
-			if (mode & 1) PIOA->PIO_IDR = interruptMask[0];
-			if (mode & 2) PIOB->PIO_IDR = interruptMask[1];
-			if (mode & 4) PIOC->PIO_IDR = interruptMask[2];
-			if (mode & 8) PIOD->PIO_IDR = interruptMask[3];
-		} else {
-			interruptSave = interruptsStatus();
-			noInterrupts();
-		}
-	}
-	uint32_t ch = BOARD_PIN_TO_SPI_CHANNEL(pin);
-	bitOrder[ch] = settings.border;
-	SPI_ConfigureNPCS(spi, ch, settings.config);
-	//setBitOrder(pin, settings.border);
-	//setDataMode(pin, settings.datamode);
-	//setClockDivider(pin, settings.clockdiv);
-#endif
+}
+
+void SPIClass::beginTransactionSlave(SPISettings settings)
+{
+	#ifdef SPI_DEBUG
+	Serial.println(F("SPIClass::beginTransactionSlave"));
+	#endif
+	setBitOrder(settings.bitOrder);
+	setDataMode(settings.dataMode);
+	setDataSize(settings.dataSize);
+	beginSlave();
 }
 
 void SPIClass::endTransaction(void)
@@ -295,131 +322,154 @@ void SPIClass::endTransaction(void)
  * I/O
  */
 
-uint8 SPIClass::read(void) {
-    uint8 buf[1];
-    this->read(buf, 1);
-    return buf[0];
+uint16 SPIClass::read(void)
+{
+	while ( spi_is_rx_nonempty(_currentSetting->spi_d)==0 ) ;
+	return (uint16)spi_rx_reg(_currentSetting->spi_d);
 }
 
-void SPIClass::read(uint8 *buf, uint32 len) {
-    uint32 rxed = 0;
-    while (rxed < len) {
-        while (!spi_is_rx_nonempty(this->spi_d))
-            ;
-        buf[rxed++] = (uint8)spi_rx_reg(this->spi_d);
-    }
+void SPIClass::read(uint8 *buf, uint32 len)
+{
+	if ( len == 0 ) return;
+	spi_rx_reg(_currentSetting->spi_d);		// clear the RX buffer in case a byte is waiting on it.
+	spi_reg_map * regs = _currentSetting->spi_d->regs;
+	// start sequence: write byte 0
+	regs->DR = 0x00FF;						// write the first byte
+	// main loop
+	while ( (--len) ) {
+		while( !(regs->SR & SPI_SR_TXE) );		// wait for TXE flag
+		noInterrupts();							// go atomic level - avoid interrupts to surely get the previously received data
+		regs->DR = 0x00FF;						// write the next data item to be transmitted into the SPI_DR register. This clears the TXE flag.
+		while ( !(regs->SR & SPI_SR_RXNE) );	// wait till data is available in the DR register
+		*buf++ = (uint8)(regs->DR);				// read and store the received byte. This clears the RXNE flag.
+		interrupts();							// let systick do its job
+	}
+	// read remaining last byte
+	while ( !(regs->SR & SPI_SR_RXNE) );	// wait till data is available in the Rx register
+	*buf++ = (uint8)(regs->DR);				// read and store the received byte
 }
 
-void SPIClass::write(uint16 data) {
-	#ifdef SPI_DEBUG
-//	Serial.print("SPIClass::write("); Serial.print(data); Serial.println(")");
-	#endif
-	//  this->write(&data, 1);
-
+void SPIClass::write(uint16 data)
+{
 	/* Added for 16bit data Victor Perez. Roger Clark 
-	 * Improved speed by just directly writing the single byte to the SPI data reg and wait for completion,	 * by taking the Tx code from transfer(byte)
-	 * The original method, of calling write(*data, length) .
+	 * Improved speed by just directly writing the single byte to the SPI data reg and wait for completion,
+	 * by taking the Tx code from transfer(byte)
 	 * This almost doubles the speed of this function.
 	 */
-  
-	spi_tx_reg(this->spi_d, data); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-	while (spi_is_tx_empty(this->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(this->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
+	spi_tx_reg(_currentSetting->spi_d, data); // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
+	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
 }
 
-//void SPIClass::write(uint8 byte) {
-  //  this->write(&byte, 1);
+void SPIClass::write(uint16 data, uint32 n)
+{
+	// Added by stevstrong: Repeatedly send same data by the specified number of times
+	spi_reg_map * regs = _currentSetting->spi_d->regs;
+	while ( (n--)>0 ) {
+		regs->DR = data; // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
+		while ( (regs->SR & SPI_SR_TXE)==0 ) ; // wait till Tx empty
+	}
+	while ( (regs->SR & SPI_SR_BSY) != 0); // wait until BSY=0 before returning 
+}
 
-	/* Roger Clark 
-	 * Improved speed by just directly writing the single byte to the SPI data reg and wait for completion,	 * by taking the Tx code from transfer(byte)
-	 * The original method, of calling write(*data, length) .
-	 * This almost doubles the speed of this function.
-	 */
-  
-//	spi_tx_reg(this->spi_d, byte); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-//	while (spi_is_tx_empty(this->spi_d) == 0); // "5. Wait until TXE=1 ..."
-//	while (spi_is_busy(this->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
-//}
+void SPIClass::write(void *data, uint32 length)
+{
+	spi_dev * spi_d = _currentSetting->spi_d;
+	spi_tx(spi_d, (void*)data, length); // data can be array of bytes or words
+	while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
+}
 
-void SPIClass::write(const uint8 *data, uint32 length) {
-	#ifdef SPI_DEBUG
-	Serial.print("SPIClass::write(data, "); Serial.print(length); Serial.println(")");
-	#endif
-    uint32 txed = 0;
-    while (txed < length) {
-        txed += spi_tx(this->spi_d, data + txed, length - txed);
-    }
-	while (spi_is_tx_empty(this->spi_d) == 0); // "4. After writing the last data item into the SPI_DR register, wait until TXE=1 ..."
-	while (spi_is_busy(this->spi_d) != 0); // "... then wait until BSY=0, this indicates that the transmission of the last data is complete."
+uint8 SPIClass::transfer(uint8 byte) const
+{
+	spi_dev * spi_d = _currentSetting->spi_d;
+	spi_rx_reg(spi_d); // read any previous data
+	spi_tx_reg(spi_d, byte); // Write the data item to be transmitted into the SPI_DR register
+	while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
+	return (uint8)spi_rx_reg(spi_d); // "... and read the last received data."
 }
 
-uint8 SPIClass::transfer(uint8 byte) const {
-	#ifdef SPI_DEBUG
-//	Serial.print("SPIClass::transfer("); Serial.print(byte); Serial.println(")");
-	#endif
-	uint8 b;
-	spi_tx_reg(this->spi_d, byte); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-  	while (spi_is_rx_nonempty(this->spi_d) == 0); // "4. Wait until RXNE=1 ..."
-  	b = spi_rx_reg(this->spi_d); // "... and read the last received data."
-  	while (spi_is_tx_empty(this->spi_d) == 0); // "5. Wait until TXE=1 ..."
-  	while (spi_is_busy(this->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
-    return b;
+uint16_t SPIClass::transfer16(uint16_t wr_data) const
+{
+	spi_dev * spi_d = _currentSetting->spi_d;
+	spi_rx_reg(spi_d); // read any previous data
+	spi_tx_reg(spi_d, wr_data); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
+	while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
+	return (uint16)spi_rx_reg(spi_d); // "... and read the last received data."
 }
+
+#ifdef SPI_DMA
 /*  Roger Clark and Victor Perez, 2015
 *	Performs a DMA SPI transfer with at least a receive buffer.
-*	If a TX buffer is not provided, FF is sent over and over for the lenght of the transfer. 
-*	On exit TX buffer is not modified, and RX buffer cotains the received data.
+*	If a TX buffer is not provided, FF is sent over and over for the length of the transfer. 
+*	On exit TX buffer is not modified, and RX buffer contains the received data.
 *	Still in progress.
 */
-uint8 SPIClass::dmaTransfer(uint8 *transmitBuf, uint8 *receiveBuf, uint16 length) {
+uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length)
+{
 	if (length == 0) return 0;
-	uint8 b;
-	if (spi_is_rx_nonempty(this->spi_d) == 1) b = spi_rx_reg(this->spi_d); //Clear the RX buffer in case a byte is waiting on it.
-	dma1_ch3_Active=true;
-    dma_init(DMA1);
-	dma_attach_interrupt(DMA1, DMA_CH3, &SPIClass::DMA1_CH3_Event);
-	
+
+	uint8 b = 0;
+
+    dma_init(_currentSetting->spiDmaDev);
+//	dma_attach_interrupt(DMA1, DMA_CH3, &SPIClass::DMA1_CH3_Event);
 	// RX
-	spi_rx_dma_enable(SPI1);
-	dma_setup_transfer(DMA1, DMA_CH2, &SPI1->regs->DR, DMA_SIZE_8BITS,
-                     receiveBuf, DMA_SIZE_8BITS, (DMA_MINC_MODE | DMA_TRNS_CMPLT));// receive buffer DMA
-	dma_set_num_transfers(DMA1, DMA_CH2, length);
-	
+	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==SPI_DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
+	dma_setup_transfer(	_currentSetting->spiDmaDev,
+						_currentSetting->spiRxDmaStream,
+						_currentSetting->spiDmaChannel,
+						dma_bit_size,
+						&_currentSetting->spi_d->regs->DR,	// peripheral address
+						receiveBuf,							// memory bank 0 address
+						NULL,								// memory bank 1 address
+						(DMA_MINC_MODE | DMA_FROM_PER | DMA_PRIO_VERY_HIGH)		// flags
+	);
+	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaStream, length);
+	dma_set_fifo_flags(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaStream, 0);
+	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaStream);
+
 	// TX
-	spi_tx_dma_enable(SPI1);	
-	if (!transmitBuf) {
-	static uint8_t ff = 0XFF;
-	transmitBuf = &ff;
-	dma_setup_transfer(DMA1, DMA_CH3, &SPI1->regs->DR, DMA_SIZE_8BITS,
-                       transmitBuf, DMA_SIZE_8BITS, (DMA_FROM_MEM | DMA_TRNS_CMPLT));// Transmit FF repeatedly
+	uint32 flags = (DMA_MINC_MODE | DMA_FROM_MEM); // | DMA_TRNS_CMPLT);
+	if ( transmitBuf==0 ) {
+		static uint8_t ff = 0XFF;
+		transmitBuf = &ff;
+		flags &= ~((uint32)DMA_MINC_MODE); // remove increment mode
 	}
-	else {
-    dma_setup_transfer(DMA1, DMA_CH3, &SPI1->regs->DR, DMA_SIZE_8BITS,
-                       transmitBuf, DMA_SIZE_8BITS, (DMA_MINC_MODE |  DMA_FROM_MEM | DMA_TRNS_CMPLT));// Transmit buffer DMA 
-	}
-	dma_set_num_transfers(DMA1, DMA_CH3, length);
-
-	dma_enable(DMA1, DMA_CH2);// enable receive
-	dma_enable(DMA1, DMA_CH3);// enable transmit
+	dma_setup_transfer(	_currentSetting->spiDmaDev,
+						_currentSetting->spiTxDmaStream,
+						_currentSetting->spiDmaChannel,
+						dma_bit_size,
+						&_currentSetting->spi_d->regs->DR,	// peripheral address
+						transmitBuf,						// memory bank 0 address
+						NULL,								// memory bank 1 address
+						flags
+	);
+	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream, length);
+	dma_set_fifo_flags(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream, 0);
+	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream);
+	// software enable sequence, see AN4031, chapter 4.3
+	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaStream);// enable receive
+	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream);// enable transmit
+	spi_rx_reg(_currentSetting->spi_d); //Clear the RX buffer in case a byte is waiting on it.
+	spi_rx_dma_enable(_currentSetting->spi_d);
+	spi_tx_dma_enable(_currentSetting->spi_d);	// must be the last enable to avoid DMA error flag
 	
-//	while (dma1_ch3_Active);
-//	if (receiveBuf) {
     uint32_t m = millis();
-    while (dma1_ch3_Active) {
-      if ((millis() - m) > 100)  {
-        dma1_ch3_Active = 0;
-		b = 2;
-		break;
-      }
+	while ((b = dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream) & DMA_ISR_TCIF)==0 ) {// wait for completion flag to be set
+		if ( b&(DMA_ISR_TEIF|DMA_ISR_DMEIF|DMA_ISR_FEIF) ) { b = 1; break; } // break on any error flag
+		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
     }
-
-//	}
-	while (spi_is_tx_empty(this->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(this->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
-    dma_disable(DMA1, DMA_CH3);
-	dma_disable(DMA1, DMA_CH2);
-	spi_rx_dma_disable(SPI1);
-	spi_tx_dma_disable(SPI1);
+	if (b & DMA_ISR_TCIF) b = 0;
+
+	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
+	// software disable sequence, see AN4031, chapter 4.1
+	spi_tx_dma_disable(_currentSetting->spi_d);
+	spi_rx_dma_disable(_currentSetting->spi_d);
+	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaStream);
+    dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream);
     return b;
 }
 
@@ -427,56 +477,45 @@ uint8 SPIClass::dmaTransfer(uint8 *transmitBuf, uint8 *receiveBuf, uint16 length
 *	Performs a DMA SPI send using a TX buffer.
 *	On exit TX buffer is not modified.
 *	Still in progress.
+*	2016 - stevstrong - reworked to automatically detect bit size from SPI setting
 */
-uint8 SPIClass::dmaSend(uint8 *transmitBuf, uint16 length, bool minc) {
+uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length, bool minc)
+{
 	if (length == 0) return 0;
-	uint32 flags = ((DMA_MINC_MODE * minc) |  DMA_FROM_MEM | DMA_TRNS_CMPLT);
-	uint8 b;
-	dma1_ch3_Active=true;
-    dma_init(DMA1);
-	dma_attach_interrupt(DMA1, DMA_CH3, &SPIClass::DMA1_CH3_Event);
-
+	uint8 b = 0;
+	dma_init(_currentSetting->spiDmaDev);
 	// TX
-	spi_tx_dma_enable(SPI1);	
-    dma_setup_transfer(DMA1, DMA_CH3, &SPI1->regs->DR, DMA_SIZE_8BITS,
-                       transmitBuf, DMA_SIZE_8BITS, flags);// Transmit buffer DMA 
-	dma_set_num_transfers(DMA1, DMA_CH3, length);
-	dma_enable(DMA1, DMA_CH3);// enable transmit
-	
-    while (dma1_ch3_Active);
-	while (spi_is_rx_nonempty(this->spi_d) == 0); // "4. Wait until RXNE=1 ..."
-  	b = spi_rx_reg(this->spi_d); // "... and read the last received data."
-	while (spi_is_tx_empty(this->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(this->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
-	dma_disable(DMA1, DMA_CH3);
-	spi_tx_dma_disable(SPI1);
-    return b;
-}
-
-uint8 SPIClass::dmaSend(uint16 *transmitBuf, uint16 length, bool minc) {
-	if (length == 0) return 0;
-	uint32 flags = ((DMA_MINC_MODE * minc) |  DMA_FROM_MEM | DMA_TRNS_CMPLT);
-	uint8 b;
-	dma1_ch3_Active=true;
-    dma_init(DMA1);
-	dma_attach_interrupt(DMA1, DMA_CH3, &SPIClass::DMA1_CH3_Event);
+	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==SPI_DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
+	dma_setup_transfer(	_currentSetting->spiDmaDev,
+						_currentSetting->spiTxDmaStream,
+						_currentSetting->spiDmaChannel,
+						dma_bit_size,
+						&_currentSetting->spi_d->regs->DR,	// peripheral address
+						transmitBuf,						// memory bank 0 address
+						NULL,								// memory bank 1 address
+						( (DMA_MINC_MODE*minc) | DMA_FROM_MEM ) //| DMA_TRNS_CMPLT ) // flags
+	);// Transmit buffer DMA 
+	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream, length);
+	dma_set_fifo_flags(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream, 0);
+	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream);
+	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream);// enable transmit
+	spi_tx_dma_enable(_currentSetting->spi_d);
+
+	uint32_t m = millis();
+	while ((b = dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream) & DMA_ISR_TCIF)==0 ) {// wait for completion flag to be set
+		if ( b&(DMA_ISR_TEIF|DMA_ISR_DMEIF|DMA_ISR_FEIF) ) { b = 1; break; } // break on any error flag
+		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
+    }
+	if (b & DMA_ISR_TCIF) b = 0;
 
-	// TX
-	spi_tx_dma_enable(SPI1);	
-    dma_setup_transfer(DMA1, DMA_CH3, &SPI1->regs->DR, DMA_SIZE_16BITS,
-                       transmitBuf, DMA_SIZE_16BITS, flags);// Transmit buffer DMA 
-	dma_set_num_transfers(DMA1, DMA_CH3, length);
-	dma_enable(DMA1, DMA_CH3);// enable transmit
-	
-    while (dma1_ch3_Active);
-	while (spi_is_rx_nonempty(this->spi_d) == 0); // "4. Wait until RXNE=1 ..."
-  	b = spi_rx_reg(this->spi_d); // "... and read the last received data."
-	while (spi_is_tx_empty(this->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(this->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
-	dma_disable(DMA1, DMA_CH3);
-	spi_tx_dma_disable(SPI1);
-    return b;
+	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
+	spi_tx_dma_disable(_currentSetting->spi_d);
+	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream);
+	return b;
 }
+#endif
+
 
 
 void SPIClass::attachInterrupt(void) {
@@ -492,19 +531,19 @@ void SPIClass::detachInterrupt(void) {
  */
 
 uint8 SPIClass::misoPin(void) {
-    return dev_to_spi_pins(this->spi_d)->miso;
+    return dev_to_spi_pins(_currentSetting->spi_d)->miso;
 }
 
 uint8 SPIClass::mosiPin(void) {
-    return dev_to_spi_pins(this->spi_d)->mosi;
+    return dev_to_spi_pins(_currentSetting->spi_d)->mosi;
 }
 
 uint8 SPIClass::sckPin(void) {
-    return dev_to_spi_pins(this->spi_d)->sck;
+    return dev_to_spi_pins(_currentSetting->spi_d)->sck;
 }
 
 uint8 SPIClass::nssPin(void) {
-    return dev_to_spi_pins(this->spi_d)->nss;
+    return dev_to_spi_pins(_currentSetting->spi_d)->nss;
 }
 
 /*
@@ -512,18 +551,13 @@ uint8 SPIClass::nssPin(void) {
  */
 
 uint8 SPIClass::send(uint8 data) {
-    uint8 buf[] = {data};
-    return this->send(buf, 1);
+    this->write(data);
+    return 1;
 }
 
 uint8 SPIClass::send(uint8 *buf, uint32 len) {
-    uint32 txed = 0;
-    uint8 ret = 0;
-    while (txed < len) {
-        this->write(buf[txed++]);
-        ret = this->read();
-    }
-    return ret;
+    this->write(buf, len);
+    return len;
 }
 
 uint8 SPIClass::recv(void) {
@@ -585,29 +619,26 @@ static void configure_gpios(spi_dev *dev, bool as_master) {
 	if(dev->clk_id <= RCC_SPI2) {
 		if(nssi) {
 			if(!as_master) {
-				gpio_set_af_mode(nssi->gpio_device,  scki->gpio_bit, 5);
+				gpio_set_af_mode(pins->nss, 5);
 			}
 		}
-		gpio_set_af_mode(scki->gpio_device,  scki->gpio_bit, 5);
-		gpio_set_af_mode(misoi->gpio_device, misoi->gpio_bit, 5);
-		gpio_set_af_mode(mosii->gpio_device, mosii->gpio_bit, 5);
+		gpio_set_af_mode(pins->sck, 5);
+		gpio_set_af_mode(pins->miso, 5);
+		gpio_set_af_mode(pins->mosi, 5);
 	} else {
 		if(nssi) {
 			if(!as_master) {
-				gpio_set_af_mode(nssi->gpio_device,  scki->gpio_bit, 6);
+				gpio_set_af_mode(pins->nss, 6);
 			}
 		}
-		gpio_set_af_mode(scki->gpio_device,  scki->gpio_bit, 6);
-		gpio_set_af_mode(misoi->gpio_device, misoi->gpio_bit, 6);
-		gpio_set_af_mode(mosii->gpio_device, mosii->gpio_bit, 6);
+		gpio_set_af_mode(pins->sck, 6);
+		gpio_set_af_mode(pins->miso, 6);
+		gpio_set_af_mode(pins->mosi, 6);
 	}
 	
 #endif
 
-    spi_config_gpios(dev, as_master, nssi->gpio_device, nssi->gpio_bit,
-                     scki->gpio_device, scki->gpio_bit, 
-                     misoi->gpio_device, misoi->gpio_bit,
-                     mosii->gpio_device, mosii->gpio_bit);
+    spi_config_gpios(dev, as_master, pins->nss, pins->sck, pins->miso, pins->mosi);
 }
 
 static const spi_baud_rate baud_rates[8] __FLASH__ = {
@@ -634,6 +665,8 @@ static spi_baud_rate determine_baud_rate(spi_dev *dev, uint32_t freq) {
     {
     	case RCC_APB2: clock = STM32_PCLK2; break; // 72 Mhz
     	case RCC_APB1: clock = STM32_PCLK1; break; // 36 Mhz
+		case RCC_AHB1: break;
+		default: break;
     }
     clock /= 2;
     i = 0;
@@ -646,4 +679,3 @@ static spi_baud_rate determine_baud_rate(spi_dev *dev, uint32_t freq) {
 
 
 //SPIClass SPI(3);
-
diff --git a/STM32F4/libraries/SPI/src/SPI.h b/STM32F4/libraries/SPI/src/SPI.h
index 490d58b2e..218449fb1 100644
--- a/STM32F4/libraries/SPI/src/SPI.h
+++ b/STM32F4/libraries/SPI/src/SPI.h
@@ -34,18 +34,15 @@
 /* TODO [0.1.0] Remove deprecated methods. */
 
 
-
-#ifndef _SPI_H_INCLUDED
-#define _SPI_H_INCLUDED
+#ifndef _LIB_SPI_H_
+#define _LIB_SPI_H_
 
 #include <libmaple/libmaple_types.h>
 #include <libmaple/spi.h>
 #include <libmaple/dma.h>
-
-#include <boards.h>
-#include <stdint.h>
 #include <wirish.h>
 
+
 // SPI_HAS_TRANSACTION means SPI has
 //   - beginTransaction()
 //   - endTransaction()
@@ -96,34 +93,61 @@
 #define SPI_MODE2 SPI_MODE_2
 #define SPI_MODE3 SPI_MODE_3
 
+#define SPI_DATA_SIZE_8BIT SPI_CR1_DFF_8_BIT
+#define SPI_DATA_SIZE_16BIT SPI_CR1_DFF_16_BIT
+
 class SPISettings {
 public:
 	SPISettings(uint32_t clock, BitOrder bitOrder, uint8_t dataMode) {
 		if (__builtin_constant_p(clock)) {
-			init_AlwaysInline(clock, bitOrder, dataMode);
+			init_AlwaysInline(clock, bitOrder, dataMode, SPI_DATA_SIZE_8BIT);
+		} else {
+			init_MightInline(clock, bitOrder, dataMode, SPI_DATA_SIZE_8BIT);
+		}
+	}
+	SPISettings(uint32_t clock, BitOrder bitOrder, uint8_t dataMode, uint32_t dataSize) {
+		if (__builtin_constant_p(clock)) {
+			init_AlwaysInline(clock, bitOrder, dataMode, dataSize);
 		} else {
-			init_MightInline(clock, bitOrder, dataMode);
+			init_MightInline(clock, bitOrder, dataMode, dataSize);
 		}
 	}
-	SPISettings() { init_AlwaysInline(4000000, MSBFIRST, SPI_MODE0); }
+	SPISettings(uint32_t clock) {
+		if (__builtin_constant_p(clock)) {
+			init_AlwaysInline(clock, MSBFIRST, SPI_MODE0, SPI_DATA_SIZE_8BIT);
+		} else {
+			init_MightInline(clock, MSBFIRST, SPI_MODE0, SPI_DATA_SIZE_8BIT);
+		}
+	}
+	SPISettings() { init_AlwaysInline(4000000, MSBFIRST, SPI_MODE0, SPI_DATA_SIZE_8BIT); }
 private:
-	void init_MightInline(uint32_t clock, BitOrder bitOrder, uint8_t dataMode) {
-		init_AlwaysInline(clock, bitOrder, dataMode);
+	void init_MightInline(uint32_t clock, BitOrder bitOrder, uint8_t dataMode, uint32_t dataSize) {
+		init_AlwaysInline(clock, bitOrder, dataMode, dataSize);
 	}
-	void init_AlwaysInline(uint32_t clock, BitOrder bitOrder, uint8_t dataMode) __attribute__((__always_inline__)) {
+	void init_AlwaysInline(uint32_t clock, BitOrder bitOrder, uint8_t dataMode, uint32_t dataSize) __attribute__((__always_inline__)) {
 		this->clock = clock;
 		this->bitOrder = bitOrder;
 		this->dataMode = dataMode;
+		this->dataSize = dataSize;
 	}
 	uint32_t clock;
 	BitOrder bitOrder;
 	uint8_t dataMode;
+	uint32_t dataSize;
+	
+	spi_dev *spi_d;
+	uint32_t clockDivider;
+
+#ifdef SPI_DMA
+	dma_dev* spiDmaDev;
+	dma_channel spiDmaChannel;
+	dma_stream spiRxDmaStream, spiTxDmaStream;
+#endif
+
 	friend class SPIClass;
 };
 
 
-volatile static bool dma1_ch3_Active;
-
 /**
  * @brief Wirish SPI interface.
  *
@@ -133,18 +157,11 @@ volatile static bool dma1_ch3_Active;
 class SPIClass {
 public:
 
-
-
     /**
      * @param spiPortNumber Number of the SPI port to manage.
      */
     SPIClass(uint32 spiPortNumber);
 
-    /*
-     * Set up/tear down
-     */
-
-
 
     /**
      * @brief Equivalent to begin(SPI_1_125MHZ, MSBFIRST, 0).
@@ -175,6 +192,8 @@ class SPIClass {
 	void beginTransaction(uint8_t pin, SPISettings settings);
 	void endTransaction(void);
 
+	void beginTransactionSlave(SPISettings settings);
+
 	void setClockDivider(uint32_t clockDivider);
 	void setBitOrder(BitOrder bitOrder);	
 	void setDataMode(uint8_t dataMode);		
@@ -195,40 +214,40 @@ class SPIClass {
      */
 
     /**
-     * @brief Return the next unread byte.
+     * @brief Return the next unread byte/word.
      *
-     * If there is no unread byte waiting, this function will block
+     * If there is no unread byte/word waiting, this function will block
      * until one is received.
      */
-    uint8 read(void);
+    uint16 read(void);
 
     /**
      * @brief Read length bytes, storing them into buffer.
      * @param buffer Buffer to store received bytes into.
-     * @param length Number of bytes to store in buffer.  This
+     * @param length Number of bytes to store in buffer. This
      *               function will block until the desired number of
      *               bytes have been read.
      */
     void read(uint8 *buffer, uint32 length);
 
     /**
-     * @brief Transmit a byte.
-     * @param data Byte to transmit.
+     * @brief Transmit one byte/word.
+     * @param data to transmit.
      */
-//    void write(uint8 data);
-
+    void write(uint16 data);	
+	
     /**
-     * @brief Transmit a half word.
+     * @brief Transmit one byte/word a specified number of times.
      * @param data to transmit.
      */
-    void write(uint16 data);	
+    void write(uint16 data, uint32 n);	
 	
     /**
-     * @brief Transmit multiple bytes.
-     * @param buffer Bytes to transmit.
-     * @param length Number of bytes in buffer to transmit.
+     * @brief Transmit multiple bytes/words.
+     * @param buffer Bytes/words to transmit.
+     * @param length Number of bytes/words in buffer to transmit.
      */
-    void write(const uint8 *buffer, uint32 length);
+    void write(void * buffer, uint32 length);
 
     /**
      * @brief Transmit a byte, then return the next unread byte.
@@ -239,9 +258,12 @@ class SPIClass {
      * @return Next unread byte.
      */
     uint8 transfer(uint8 data) const;
+    uint16_t transfer16(uint16_t data) const;
 	
+#ifdef SPI_DMA
 	/**
      * @brief Sets up a DMA Transfer for "length" bytes.
+	 * The transfer mode (8 or 16 bit mode) is evaluated from the SPI peripheral setting.
      *
      * This function transmits and receives to buffers.
      *
@@ -249,30 +271,19 @@ class SPIClass {
      * @param receiveBuf buffer Bytes to save received data. 
      * @param length Number of bytes in buffer to transmit.
 	 */
-	uint8 dmaTransfer(uint8 *transmitBuf, uint8 *receiveBuf, uint16 length);
+	uint8 dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length);
 
 	/**
-     * @brief Sets up a DMA Transmit for bytes.
-     *
-     * This function transmits and does not care about the RX fifo.
+     * @brief Sets up a DMA Transmit for SPI 8 or 16 bit transfer mode.
+	 * The transfer mode (8 or 16 bit mode) is evaluated from the SPI peripheral setting.
      *
-     * @param transmitBuf buffer Bytes to transmit,
-     * @param length Number of bytes in buffer to transmit.
-	 * @param minc Set to use Memory Increment mode, clear to use Circular mode.
-     */
-	uint8 dmaSend(uint8 *transmitBuf, uint16 length, bool minc = 1);
-	
-	/**
-     * @brief Sets up a DMA Transmit for half words.
-	 * SPI PERFIPHERAL MUST BE SET TO 16 BIT MODE BEFORE
-     *
-     * This function transmits and does not care about the RX fifo.
+     * This function only transmits and does not care about the RX fifo.
      *
      * @param data buffer half words to transmit,
      * @param length Number of bytes in buffer to transmit.
-     * @param minc Set to use Memory Increment mode (default if blank), clear to use Circular mode.
      */
-	uint8 dmaSend(uint16 *transmitBuf, uint16 length, bool minc = 1);
+	uint8 dmaSend(void * transmitBuf, uint16 length, bool minc = 1);
+#endif
 
     /*
      * Pin accessors
@@ -304,7 +315,24 @@ class SPIClass {
      * @brief Get a pointer to the underlying libmaple spi_dev for
      *        this HardwareSPI instance.
      */
-    spi_dev* c_dev(void) { return this->spi_d; }
+    spi_dev* c_dev(void) { return _currentSetting->spi_d; }
+	
+		
+	spi_dev *dev(){ return _currentSetting->spi_d;}
+	
+	 /**
+     * @brief Sets the number of the SPI peripheral to be used by
+     *        this HardwareSPI instance.
+	 *
+	 * @param spi_num Number of the SPI port. 1-2 in low density devices
+	 *			or 1-3 in high density devices.
+     */
+	
+	void setModule(int spi_num)
+	{
+		_currentSetting=&_settings[spi_num-1];// SPI channels are called 1 2 and 3 but the array is zero indexed
+	}
+
 
     /* -- The following methods are deprecated --------------------------- */
 
@@ -338,26 +366,13 @@ class SPIClass {
      */
     uint8 recv(void);
 	
-	spi_dev *dev(){ return spi_d;}
-	
-	
-	
 private:
-
-	static inline void DMA1_CH3_Event() {
-		dma1_ch3_Active = 0;
-//		dma_disable(DMA1, DMA_CH3);
-//		dma_disable(DMA1, DMA_CH2);
-		
-		// To Do. Need to wait for 
-	}
-	spi_dev *spi_d;
-	uint8_t _SSPin;
-	uint32_t clockDivider;
-	uint8_t dataMode;
-	BitOrder bitOrder;
+	SPISettings _settings[BOARD_NR_SPI];
+	SPISettings *_currentSetting;
+	
+	void updateSettings(void);
 };
 
+extern SPIClass SPI; // needed bx SdFat(EX) lib
 
-extern SPIClass SPI;//(1);// dummy params
 #endif
diff --git a/STM32F4/platform.txt b/STM32F4/platform.txt
index 99ae55549..2bb1946b0 100755
--- a/STM32F4/platform.txt
+++ b/STM32F4/platform.txt
@@ -8,17 +8,15 @@ version=0.1.0
 
 # compiler variables
 # ----------------------
-#build.gcc_ver=gcc-arm-none-eabi-4.8.3-2014q1
-
 compiler.path={runtime.tools.arm-none-eabi-gcc.path}/bin/
 compiler.c.cmd=arm-none-eabi-gcc
-compiler.c.flags=-c -g -Os -w -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
+compiler.c.flags=-c -g -Os -Wall -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
 compiler.c.elf.cmd=arm-none-eabi-g++
 compiler.c.elf.flags=-Os -Wl,--gc-sections
 compiler.S.cmd=arm-none-eabi-gcc
 compiler.S.flags=-c -g -x assembler-with-cpp -MMD
 compiler.cpp.cmd=arm-none-eabi-g++
-compiler.cpp.flags=-c -g -Os -w -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
+compiler.cpp.flags=-c -g -Os -Wall -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
 compiler.ar.cmd=arm-none-eabi-ar
 compiler.ar.flags=rcs
 compiler.objcopy.cmd=arm-none-eabi-objcopy
@@ -30,6 +28,8 @@ compiler.size.cmd=arm-none-eabi-size
 compiler.define=-DARDUINO=                            
 
 # this can be overriden in boards.txt
+build.f_cpu=168000000L
+build.mcu=cortex-m4
 build.cpu_flags=
 build.hs_flag=
 build.common_flags=-mthumb -D__STM32F4__
@@ -44,12 +44,10 @@ compiler.ar.extra_flags=
 compiler.elf2hex.extra_flags=
 
 
+##compiler.libs.c.flags="-I{build.system.path}/libmaple" "-I{build.system.path}/libmaple/include" "-I{build.system.path}/libmaple/stm32f1/include"                                                           "-I{build.system.path}/libmaple/usb/stm32f1" "-I{build.system.path}/libmaple/usb/usb_lib" 
+#compiler.libs.c.flags="-I{build.core.path}" "-I{build.core.path}/libmaple" "-I{build.core.path}/libmaple/usbF4" "-I{build.core.path}/libmaple/usbF4/STM32_USB_Device_Library/Core/inc" "-I{build.core.path}/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/inc" "-I{build.core.path}/libmaple/usbF4/STM32_USB_OTG_Driver/inc" "-I{build.core.path}/libmaple/usbF4/VCP" 
+compiler.libs.c.flags="-I{build.system.path}/libmaple" "-I{build.core.path}/libmaple/usbF4"
 
-##compiler.libs.c.flags="-I{build.system.path}/libmaple" "-I{build.system.path}/libmaple/include" "-I{build.system.path}/libmaple/stm32f1/include" "-I{build.system.path}/libmaple/stm32f1/include/series" "-I{build.system.path}/libmaple/usb/stm32f1" "-I{build.system.path}/libmaple/usb/usb_lib" 
-#compiler.libs.c.flags="-I{build.system.path}/libmaple" "-I{build.system.path}/libmaple/include" "-I{build.system.path}/libmaple/stm32f1/include"                                                           "-I{build.system.path}/libmaple/usb/stm32f1" "-I{build.system.path}/libmaple/usb/usb_lib" 
-
-
-compiler.libs.c.flags="-I{build.core.path}/libmaple" -I{build.core.path}/libmaple/usbF4 -I{build.core.path}/libmaple/usbF4/STM32_USB_Device_Library/Core/inc -I{build.core.path}/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/inc -I{build.core.path}/libmaple/usbF4/STM32_USB_OTG_Driver/inc -I{build.core.path}/libmaple/usbF4/VCP 
 
 
 
@@ -66,14 +64,13 @@ compiler.libs.c.flags="-I{build.core.path}/libmaple" -I{build.core.path}/libmapl
 # ---------------------
 
 ## Compile c files
-recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.c.flags} -mcpu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.c.extra_flags} {build.extra_flags} {compiler.libs.c.flags} {includes} "{source_file}" -o "{object_file}"
+recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.c.flags} -mcpu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.c.extra_flags} {build.extra_flags} {build.cpu_flags} {compiler.libs.c.flags} {includes} "{source_file}" -o "{object_file}"
 
 ## Compile c++ files
 recipe.cpp.o.pattern="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.flags} -mcpu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {build.cpu_flags} {build.hs_flag} {build.common_flags} {compiler.libs.c.flags} {includes} "{source_file}" -o "{object_file}"
 
 ## Compile S files
 recipe.S.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.S.flags} -mcpu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.S.extra_flags} {build.extra_flags} {build.cpu_flags} {build.hs_flag} {build.common_flags} {compiler.libs.c.flags} {includes} "{source_file}" -o "{object_file}"
-#recipe.S.o.pattern="{compiler.path}{compiler.c.cmd}" "{source_file}" -o "{object_file}"
 
 ## Create archives
 recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} {compiler.ar.extra_flags} "{archive_file_path}" "{object_file}"
@@ -92,7 +89,6 @@ recipe.objcopy.hex.pattern="{compiler.path}{compiler.elf2hex.cmd}" {compiler.elf
 
 ## Compute size
 recipe.size.pattern="{compiler.path}{compiler.size.cmd}" -A "{build.path}/{build.project_name}.elf"
-#recipe.size.regex=\.text\s+([0-9]+).*
 recipe.size.regex=^(?:\.text|\.rodata|\.ARM.exidx)\s+([0-9]+).*
 recipe.size.regex.data=^(?:\.data|\.bss|\.noinit)\s+([0-9]+).*
 
diff --git a/STM32F4/cores/maple/libmaple/gpio.c b/STM32F4/system/libmaple/Arduino.h
similarity index 79%
rename from STM32F4/cores/maple/libmaple/gpio.c
rename to STM32F4/system/libmaple/Arduino.h
index 3792220e3..cef8f089f 100644
--- a/STM32F4/cores/maple/libmaple/gpio.c
+++ b/STM32F4/system/libmaple/Arduino.h
@@ -1,7 +1,7 @@
 /******************************************************************************
  * The MIT License
  *
- * Copyright (c) 2010 Perry Hung.
+ * Copyright (c) 2010 LeafLabs LLC.
  *
  * Permission is hereby granted, free of charge, to any person
  * obtaining a copy of this software and associated documentation
@@ -24,13 +24,23 @@
  * SOFTWARE.
  *****************************************************************************/
 
-/**
- * @file gpio.c
- * @brief GPIO initialization routine
- */
+#ifndef _WIRISH_ARDUINO_H_
+#define _WIRISH_ARDUINO_H_
 
-// #ifdef STM32F2
-// #include "gpioF2.c"
-// #else
-// #include "gpioF1.c"
-// #endif
+//#warning Include Arduino.h from system\libmaple
+
+#include "wirish.h"
+
+void setup();
+void loop();
+#ifdef __cplusplus
+extern "C"{
+#endif // __cplusplus
+void yield(void);
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#include "variant.h"
+
+#endif
diff --git a/STM32F4/variants/generic_f407v/generic_f407v.cpp b/STM32F4/variants/generic_f407v/generic_f407v.cpp
new file mode 100644
index 000000000..c51ff9b55
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/generic_f407v.cpp
@@ -0,0 +1,81 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file   generic_f407v.cpp
+ * @author ala42
+ * @brief  generic_f407v board file.
+ */
+
+#ifdef BOARD_generic_f407v
+
+#include "generic_f407v.h"
+
+#include "wirish_types.h"
+
+//static void initSRAMChip(void);
+/*****************************************************************************/
+//  Alternate functions, see DocID022152 Rev 8, Table 9. 
+/*****************************************************************************/
+void boardInit(void) {
+/*	// remap TIMER8 to PC6-9
+	gpio_set_af_mode(GPIOC, 6, 3);
+	gpio_set_af_mode(GPIOC, 7, 3);
+	gpio_set_af_mode(GPIOC, 8, 3);
+	gpio_set_af_mode(GPIOC, 9, 3);
+
+	// remap TIMER1 to PE9,11,13,14
+	gpio_set_af_mode(GPIOE,  9, 1);
+	gpio_set_af_mode(GPIOE, 11, 1);
+	gpio_set_af_mode(GPIOE, 13, 1);
+	gpio_set_af_mode(GPIOE, 14, 1);
+
+	// remap TIMER3 to PB4,5,0,1
+	gpio_set_af_mode(GPIOB,  4, 2);
+	gpio_set_af_mode(GPIOB,  5, 2);
+	gpio_set_af_mode(GPIOB,  0, 2);
+	gpio_set_af_mode(GPIOB,  1, 2);
+
+	//gpio_set_af_mode(GPIOA, 2, 7);
+	//gpio_set_af_mode(GPIOA, 3, 7);
+*/
+	return;
+}
+
+/*
+static void initSRAMChip(void) {
+    fsmc_nor_psram_reg_map *regs = FSMC_NOR_PSRAM1_BASE;
+
+    fsmc_sram_init_gpios();
+    rcc_clk_enable(RCC_FSMC);
+
+    regs->BCR = (FSMC_BCR_WREN | FSMC_BCR_MWID_16BITS | FSMC_BCR_MTYP_SRAM |
+                 FSMC_BCR_MBKEN);
+    fsmc_nor_psram_set_addset(regs, 0);
+    fsmc_nor_psram_set_datast(regs, 3);
+}
+*/
+#endif
diff --git a/STM32F4/variants/generic_f407v/generic_f407v.h b/STM32F4/variants/generic_f407v/generic_f407v.h
new file mode 100644
index 000000000..927f9cd9c
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/generic_f407v.h
@@ -0,0 +1,163 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file   generic_f407v.h
+ * @author Marti Bolivar <mbolivar@leaflabs.com>
+ * @brief  Private include file for Maple Native in boards.h
+ *
+ * See maple.h for more information on these definitions.
+ */
+
+#ifndef _BOARD_GENERIC_F407V_H_
+#define _BOARD_GENERIC_F407V_H_
+
+#define Port2Pin(port, bit) ((port-'A')*16+bit)
+
+#define CYCLES_PER_MICROSECOND  168
+
+
+#undef  STM32_PCLK1
+#undef  STM32_PCLK2
+#define STM32_PCLK1   (CYCLES_PER_MICROSECOND*1000000/4)
+#define STM32_PCLK2   (CYCLES_PER_MICROSECOND*1000000/2)
+
+#define SYSTICK_RELOAD_VAL      (CYCLES_PER_MICROSECOND*1000-1)
+
+/*****************************************************************************/
+// Board pin definitions
+#define BOARD_USB_DM_PIN		PA11
+#define BOARD_USB_DP_PIN		PA12
+
+#define BOARD_LED_PIN           PA6 //Port2Pin('A', 6)
+#define BOARD_LED2_PIN          PA7 //Port2Pin('A', 7)
+#define BOARD_BUTTON1_PIN       PA0 //Port2Pin('A', 0)
+#define BOARD_BUTTON2_PIN       PE4 //Port2Pin('E', 4)
+#define BOARD_BUTTON3_PIN       PE3 //Port2Pin('E', 3)
+
+#define BOARD_NR_USARTS         5
+#define BOARD_USART1_TX_PIN     PA9  //Port2Pin('A', 9)
+#define BOARD_USART1_RX_PIN     PA10 //Port2Pin('A',10)
+#define BOARD_USART2_TX_PIN     PA2  //Port2Pin('A', 2)
+#define BOARD_USART2_RX_PIN     PA3  //Port2Pin('A', 3)
+#define BOARD_USART3_TX_PIN     PB10 //Port2Pin('B',10)
+#define BOARD_USART3_RX_PIN     PB11 //Port2Pin('B',11)
+#define BOARD_UART4_TX_PIN      PA0  //Port2Pin('A', 0)
+#define BOARD_UART4_RX_PIN      PA1  //Port2Pin('A', 1)
+#define BOARD_UART5_TX_PIN      PC12 //Port2Pin('C',12)
+#define BOARD_UART5_RX_PIN      PD2  //Port2Pin('D', 2)
+
+#define BOARD_NR_SPI            3
+#define BOARD_SPI1_NSS_PIN      PA4  //Port2Pin('A', 4)
+#define BOARD_SPI1_SCK_PIN      PA5  //Port2Pin('A', 5)
+#define BOARD_SPI1_MISO_PIN     PA6  //Port2Pin('A', 6)
+#define BOARD_SPI1_MOSI_PIN     PA7  //Port2Pin('A', 7)
+#define BOARD_SPI1A_NSS_PIN     PA15 //Port2Pin('A',15)
+#define BOARD_SPI1A_SCK_PIN     PB3  //Port2Pin('B', 3)
+#define BOARD_SPI1A_MISO_PIN    PB4  //Port2Pin('B', 4)
+#define BOARD_SPI1A_MOSI_PIN    PB5  //Port2Pin('B', 5)
+
+#define BOARD_SPI2_NSS_PIN      PB12 //Port2Pin('B',12)
+#define BOARD_SPI2_SCK_PIN      PB13 //Port2Pin('B',13)
+#define BOARD_SPI2_MISO_PIN     PB14 //Port2Pin('B',14)
+#define BOARD_SPI2_MOSI_PIN     PB15 //Port2Pin('B',15)
+#define BOARD_SPI2A_NSS_PIN     PB9  //Port2Pin('B', 9)
+#define BOARD_SPI2A_SCK_PIN     PB10 //Port2Pin('B',10)
+#define BOARD_SPI2A_MISO_PIN    PC2  //Port2Pin('C', 2)
+#define BOARD_SPI2A_MOSI_PIN    pc3  //Port2Pin('C', 3)
+
+#define BOARD_SPI3_NSS_PIN      PA15 //Port2Pin('A',15)
+#define BOARD_SPI3_SCK_PIN      PB3  //Port2Pin('B', 3)
+#define BOARD_SPI3_MISO_PIN     PB4  //Port2Pin('B', 4)
+#define BOARD_SPI3_MOSI_PIN     PB5  //Port2Pin('B', 5)
+/* overlap with the SDIO interface for SD card
+#define BOARD_SPI3A_NSS_PIN     PA4  //Port2Pin('A', 4)
+#define BOARD_SPI3A_SCK_PIN     PC10 //Port2Pin('C',10)
+#define BOARD_SPI3A_MISO_PIN    PC11 //Port2Pin('C',11)
+#define BOARD_SPI3A_MOSI_PIN    PC12 //Port2Pin('C',12)
+*/
+#define BOARD_SDIO_D0           PC8  //Port2Pin('C', 8)
+#define BOARD_SDIO_D1           PC9  //Port2Pin('C', 9)
+#define BOARD_SDIO_D2           PC10 //Port2Pin('C',10)
+#define BOARD_SDIO_D3           PC11 //Port2Pin('C',11)
+#define BOARD_SDIO_CK           PC12 //Port2Pin('C',12)
+#define BOARD_SDIO_CMD          PD2  //Port2Pin('D', 2)
+
+#define BOARD_NR_GPIO_PINS      80
+#define BOARD_NR_PWM_PINS       22
+#define BOARD_NR_ADC_PINS       16
+#define BOARD_NR_USED_PINS      22
+#define BOARD_JTMS_SWDIO_PIN    PA13 //Port2Pin('A',13)
+#define BOARD_JTCK_SWCLK_PIN    PA14 //Port2Pin('A',14)
+#define BOARD_JTDI_PIN          PA15 //Port2Pin('A',15)
+#define BOARD_JTDO_PIN          PB3  //Port2Pin('B', 3)
+#define BOARD_NJTRST_PIN        PB4  //Port2Pin('B', 4)
+
+/*****************************************************************************/
+// Pins reserved for the on-board hardware
+#define USB_DM_PIN		BOARD_USB_DM_PIN // PA11
+#define USB_DP_PIN		BOARD_USB_DP_PIN // PA12
+
+#define FLASH_CS_PIN	PB0
+#define FLASH_CLK_PIN	BOARD_SPI3_SCK_PIN	// PB3
+#define FLASH_DO_PIN	BOARD_SPI3_MISO_PIN	// PB4
+#define FLASH_DI_PIN	BOARD_SPI3_MOSI_PIN	// PB5
+
+#define NRF24_CLK_PIN	BOARD_SPI3_SCK_PIN	// PB3
+#define NRF24_DO_PIN	BOARD_SPI3_MISO_PIN	// PB4
+#define NRF24_DI_PIN	BOARD_SPI3_MOSI_PIN	// PB5
+#define NRF24_CE_PIN	PB6
+#define NRF24_CS_PIN	PB7
+#define NRF24_IRQ_PIN	PB8
+
+// SD card, SDIO mode
+#define SD_DAT0         BOARD_SDIO_D0	// PC8
+#define SD_DAT1         BOARD_SDIO_D1	// PC9
+#define SD_DAT2         BOARD_SDIO_D2	// PC10
+#define SD_DAT3         BOARD_SDIO_D3	// PC11
+#define SD_CLK          BOARD_SDIO_CK	// PC12
+#define SD_CMD          BOARD_SDIO_CMD	// PD2
+// SD card, SPI mode, only usable with software SPI
+#define SD_DI           BOARD_SDIO_CMD	// PD2
+#define SD_DO           BOARD_SDIO_D0	// PC8
+#define SD_CS           BOARD_SDIO_D3	// PC11
+#define SD_SCLK         BOARD_SDIO_CK	// PC12
+
+/*****************************************************************************/
+
+enum {
+PA0,PA1,PA2,PA3,PA4,PA5,PA6,PA7,PA8,PA9,PA10,PA11,PA12,PA13,PA14,PA15,
+PB0,PB1,PB2,PB3,PB4,PB5,PB6,PB7,PB8,PB9,PB10,PB11,PB12,PB13,PB14,PB15,
+PC0,PC1,PC2,PC3,PC4,PC5,PC6,PC7,PC8,PC9,PC10,PC11,PC12,PC13,PC14,PC15,
+PD0,PD1,PD2,PD3,PD4,PD5,PD6,PD7,PD8,PD9,PD10,PD11,PD12,PD13,PD14,PD15,
+PE0,PE1,PE2,PE3,PE4,PE5,PE6,PE7,PE8,PE9,PE10,PE11,PE12,PE13,PE14,PE15,
+#if 0 // not available on LQFP100 package
+PF0,PF1,PF2,PF3,PF4,PF5,PF6,PF7,PF8,PF9,PF10,PF11,PF12,PF13,PF14,PF15,
+PG0,PG1,PG2,PG3,PG4,PG5,PG6,PG7,PG8,PG9,PG10,PG11,PG12,PG13,PG14,PG15
+#endif // not available on LQFP100 package
+};
+
+#endif
diff --git a/STM32F4/variants/generic_f407v/ld/common.inc b/STM32F4/variants/generic_f407v/ld/common.inc
new file mode 100644
index 000000000..f5a0f5b6e
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/ld/common.inc
@@ -0,0 +1,219 @@
+/*
+ * Linker script for libmaple.
+ *
+ * Original author "lanchon" from ST forums, with modifications by LeafLabs.
+ */
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+
+/*
+ * Configure other libraries we want in the link.
+ *
+ * libgcc, libc, and libm are common across supported toolchains.
+ * However, some toolchains require additional archives which aren't
+ * present everywhere (e.g. ARM's gcc-arm-embedded releases).
+ *
+ * To hack around this, we let the build system specify additional
+ * archives by putting the right extra_libs.inc (in a directory under
+ * toolchains/) in our search path.
+ */
+GROUP(libgcc.a libc.a libm.a)
+INCLUDE extra_libs.inc
+
+/*
+ * These force the linker to search for vector table symbols.
+ *
+ * These symbols vary by STM32 family (and also within families).
+ * It's up to the build system to configure the link's search path
+ * properly for the target MCU.
+ */
+INCLUDE vector_symbols.inc
+
+/* STM32 vector table. */
+EXTERN(__stm32_vector_table)
+
+/* C runtime initialization function. */
+EXTERN(start_c)
+
+/* main entry point */
+EXTERN(main)
+
+/* Initial stack pointer value. */
+EXTERN(__msp_init)
+PROVIDE(__msp_init = ORIGIN(ram) + LENGTH(ram));
+
+/* Reset vector and chip reset entry point */
+EXTERN(__start__)
+ENTRY(__start__)
+PROVIDE(__exc_reset = __start__);
+
+/* Heap boundaries, for libmaple */
+EXTERN(_lm_heap_start);
+EXTERN(_lm_heap_end);
+
+SECTIONS
+{
+    .text :
+      {
+        __text_start__ = .;
+        /*
+         * STM32 vector table.  Leave this here.  Yes, really.
+         */
+        *(.stm32.interrupt_vector)
+
+        /*
+         * Program code and vague linking
+         */
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.plt)
+        *(.gnu.warning)
+        *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+        *(.gcc_except_table)
+        *(.eh_frame_hdr)
+        *(.eh_frame)
+
+        . = ALIGN(4);
+        KEEP(*(.init))
+
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+      } > REGION_TEXT
+
+    /*
+     * End of text
+     */
+    .text.align :
+      {
+        . = ALIGN(8);
+        __text_end__ = .;
+      } > REGION_TEXT
+
+    /*
+     * .ARM.exidx exception unwinding; mandated by ARM's C++ ABI
+     */
+    __exidx_start = .;
+    .ARM.exidx :
+      {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+      } > REGION_RODATA
+    __exidx_end = .;
+
+    /*
+     * .data
+     */
+    .data :
+      {
+        . = ALIGN(8);
+        __data_start__ = .;
+
+        *(.got.plt) *(.got)
+        *(.data .data.* .gnu.linkonce.d.*)
+
+        . = ALIGN(8);
+        __data_end__ = .;
+      } > REGION_DATA AT> REGION_RODATA
+
+    /*
+     * Read-only data
+     */
+    .rodata :
+      {
+        *(.rodata .rodata.* .gnu.linkonce.r.*)
+        /* .USER_FLASH: We allow users to allocate into Flash here */
+        *(.USER_FLASH)
+        /* ROM image configuration; for C startup */
+        . = ALIGN(4);
+        _lm_rom_img_cfgp = .;
+        LONG(LOADADDR(.data));
+        /*
+         * Heap: Linker scripts may choose a custom heap by overriding
+         * _lm_heap_start and _lm_heap_end. Otherwise, the heap is in
+         * internal SRAM, beginning after .bss, and growing towards
+         * the stack.
+         *
+         * I'm shoving these here naively; there's probably a cleaner way
+         * to go about this. [mbolivar]
+         */
+        _lm_heap_start = DEFINED(_lm_heap_start) ? _lm_heap_start : _end;
+        _lm_heap_end   = DEFINED(_lm_heap_end) ? _lm_heap_end : __msp_init;
+      } > REGION_RODATA
+
+    /*
+     * .bss
+     */
+    .bss :
+      {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss .bss.* .gnu.linkonce.b.*)
+        *(COMMON)
+        . = ALIGN (8);
+        __bss_end__ = .;
+        _end = __bss_end__;
+      } > REGION_BSS
+
+    /*
+     * Debugging sections
+     */
+    .stab 0 (NOLOAD) : { *(.stab) }
+    .stabstr 0 (NOLOAD) : { *(.stabstr) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+
+    .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+    .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+    /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/STM32F4/variants/generic_f407v/ld/extra_libs.inc b/STM32F4/variants/generic_f407v/ld/extra_libs.inc
new file mode 100644
index 000000000..dd2c84fa4
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/ld/extra_libs.inc
@@ -0,0 +1,7 @@
+/*
+ * Extra archives needed by ARM's GCC ARM Embedded arm-none-eabi-
+ * releases (https://launchpad.net/gcc-arm-embedded/).
+ */
+
+/* This is for the provided newlib. */
+GROUP(libnosys.a)
diff --git a/STM32F4/variants/generic_f407v/ld/flash.ld b/STM32F4/variants/generic_f407v/ld/flash.ld
new file mode 100644
index 000000000..c753a786c
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/ld/flash.ld
@@ -0,0 +1,20 @@
+/*
+ * Discovery F4 (STM32F407VGT6, high density) linker script for
+ * Flash builds.
+ */
+
+MEMORY
+{
+  ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 125K
+  rom (rx)  : ORIGIN = 0x08010000, LENGTH = 960K  /* ala42 */
+}
+
+/* GROUP(libcs4_stm32_high_density.a) */
+
+REGION_ALIAS("REGION_TEXT", rom);
+REGION_ALIAS("REGION_DATA", ram);
+REGION_ALIAS("REGION_BSS", ram);
+REGION_ALIAS("REGION_RODATA", rom);
+
+_FLASH_BUILD = 1;
+INCLUDE common.inc
diff --git a/STM32F4/variants/generic_f407v/ld/jtag.ld b/STM32F4/variants/generic_f407v/ld/jtag.ld
new file mode 100644
index 000000000..1001db518
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/ld/jtag.ld
@@ -0,0 +1,20 @@
+/*
+ * STM32F4xx high density linker script for
+ * JTAG (bare metal, no bootloader) builds.
+ */
+
+MEMORY
+{
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
+  rom (rx)  : ORIGIN = 0x08000000, LENGTH = 512K
+}
+
+/* GROUP(libcs3_stm32_high_density.a) */
+
+REGION_ALIAS("REGION_TEXT", rom);
+REGION_ALIAS("REGION_DATA", ram);
+REGION_ALIAS("REGION_BSS", ram);
+REGION_ALIAS("REGION_RODATA", rom);
+
+_FLASH_BUILD = 1;
+INCLUDE common.inc
diff --git a/STM32F4/variants/generic_f407v/ld/names.inc b/STM32F4/variants/generic_f407v/ld/names.inc
new file mode 100644
index 000000000..6d7ff6e94
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/ld/names.inc
@@ -0,0 +1,78 @@
+EXTERN(__cs3_stack)
+EXTERN(__cs3_reset)
+EXTERN(__exc_nmi)
+EXTERN(__exc_hardfault)
+EXTERN(__exc_memmanage)
+EXTERN(__exc_busfault)
+EXTERN(__exc_usagefault)
+EXTERN(__stm32reservedexception7)
+EXTERN(__stm32reservedexception8)
+EXTERN(__stm32reservedexception9)
+EXTERN(__stm32reservedexception10)
+EXTERN(__exc_svc)
+EXTERN(__exc_debug_monitor)
+EXTERN(__stm32reservedexception13)
+EXTERN(__exc_pendsv)
+EXTERN(__exc_systick)
+
+EXTERN(__irq_wwdg)
+EXTERN(__irq_pvd)
+EXTERN(__irq_tamper)
+EXTERN(__irq_rtc)
+EXTERN(__irq_flash)
+EXTERN(__irq_rcc)
+EXTERN(__irq_exti0)
+EXTERN(__irq_exti1)
+EXTERN(__irq_exti2)
+EXTERN(__irq_exti3)
+EXTERN(__irq_exti4)
+EXTERN(__irq_dma1_channel1)
+EXTERN(__irq_dma1_channel2)
+EXTERN(__irq_dma1_channel3)
+EXTERN(__irq_dma1_channel4)
+EXTERN(__irq_dma1_channel5)
+EXTERN(__irq_dma1_channel6)
+EXTERN(__irq_dma1_channel7)
+EXTERN(__irq_adc)
+EXTERN(__irq_usb_hp_can_tx)
+EXTERN(__irq_usb_lp_can_rx0)
+EXTERN(__irq_can_rx1)
+EXTERN(__irq_can_sce)
+EXTERN(__irq_exti9_5)
+EXTERN(__irq_tim1_brk)
+EXTERN(__irq_tim1_up)
+EXTERN(__irq_tim1_trg_com)
+EXTERN(__irq_tim1_cc)
+EXTERN(__irq_tim2)
+EXTERN(__irq_tim3)
+EXTERN(__irq_tim4)
+EXTERN(__irq_i2c1_ev)
+EXTERN(__irq_i2c1_er)
+EXTERN(__irq_i2c2_ev)
+EXTERN(__irq_i2c2_er)
+EXTERN(__irq_spi1)
+EXTERN(__irq_spi2)
+EXTERN(__irq_usart1)
+EXTERN(__irq_usart2)
+EXTERN(__irq_usart3)
+EXTERN(__irq_exti15_10)
+EXTERN(__irq_rtcalarm)
+EXTERN(__irq_usbwakeup)
+
+EXTERN(__irq_tim8_brk)
+EXTERN(__irq_tim8_up)
+EXTERN(__irq_tim8_trg_com)
+EXTERN(__irq_tim8_cc)
+EXTERN(__irq_adc3)
+EXTERN(__irq_fsmc)
+EXTERN(__irq_sdio)
+EXTERN(__irq_tim5)
+EXTERN(__irq_spi3)
+EXTERN(__irq_uart4)
+EXTERN(__irq_uart5)
+EXTERN(__irq_tim6)
+EXTERN(__irq_tim7)
+EXTERN(__irq_dma2_channel1)
+EXTERN(__irq_dma2_channel2)
+EXTERN(__irq_dma2_channel3)
+EXTERN(__irq_dma2_channel4_5)
diff --git a/STM32F4/variants/generic_f407v/ld/ram.ld b/STM32F4/variants/generic_f407v/ld/ram.ld
new file mode 100644
index 000000000..b57060c92
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/ld/ram.ld
@@ -0,0 +1,19 @@
+/*
+ * aeroquad32 (STM32F103VET6, high density) linker script for
+ * RAM builds.
+ */
+
+MEMORY
+{
+  ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 61K
+  rom (rx)  : ORIGIN = 0x08010000, LENGTH = 0K  /* ala42 */
+}
+
+GROUP(libcs3_stm32_high_density.a)
+
+REGION_ALIAS("REGION_TEXT", ram);
+REGION_ALIAS("REGION_DATA", ram);
+REGION_ALIAS("REGION_BSS", ram);
+REGION_ALIAS("REGION_RODATA", ram);
+
+INCLUDE common.inc
diff --git a/STM32F4/variants/generic_f407v/ld/vector_symbols.inc b/STM32F4/variants/generic_f407v/ld/vector_symbols.inc
new file mode 100644
index 000000000..f8519bba4
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/ld/vector_symbols.inc
@@ -0,0 +1,78 @@
+EXTERN(__msp_init)
+EXTERN(__exc_reset)
+EXTERN(__exc_nmi)
+EXTERN(__exc_hardfault)
+EXTERN(__exc_memmanage)
+EXTERN(__exc_busfault)
+EXTERN(__exc_usagefault)
+EXTERN(__stm32reservedexception7)
+EXTERN(__stm32reservedexception8)
+EXTERN(__stm32reservedexception9)
+EXTERN(__stm32reservedexception10)
+EXTERN(__exc_svc)
+EXTERN(__exc_debug_monitor)
+EXTERN(__stm32reservedexception13)
+EXTERN(__exc_pendsv)
+EXTERN(__exc_systick)
+
+EXTERN(__irq_wwdg)
+EXTERN(__irq_pvd)
+EXTERN(__irq_tamper)
+EXTERN(__irq_rtc)
+EXTERN(__irq_flash)
+EXTERN(__irq_rcc)
+EXTERN(__irq_exti0)
+EXTERN(__irq_exti1)
+EXTERN(__irq_exti2)
+EXTERN(__irq_exti3)
+EXTERN(__irq_exti4)
+EXTERN(__irq_dma1_channel1)
+EXTERN(__irq_dma1_channel2)
+EXTERN(__irq_dma1_channel3)
+EXTERN(__irq_dma1_channel4)
+EXTERN(__irq_dma1_channel5)
+EXTERN(__irq_dma1_channel6)
+EXTERN(__irq_dma1_channel7)
+EXTERN(__irq_adc)
+EXTERN(__irq_usb_hp_can_tx)
+EXTERN(__irq_usb_lp_can_rx0)
+EXTERN(__irq_can_rx1)
+EXTERN(__irq_can_sce)
+EXTERN(__irq_exti9_5)
+EXTERN(__irq_tim1_brk)
+EXTERN(__irq_tim1_up)
+EXTERN(__irq_tim1_trg_com)
+EXTERN(__irq_tim1_cc)
+EXTERN(__irq_tim2)
+EXTERN(__irq_tim3)
+EXTERN(__irq_tim4)
+EXTERN(__irq_i2c1_ev)
+EXTERN(__irq_i2c1_er)
+EXTERN(__irq_i2c2_ev)
+EXTERN(__irq_i2c2_er)
+EXTERN(__irq_spi1)
+EXTERN(__irq_spi2)
+EXTERN(__irq_usart1)
+EXTERN(__irq_usart2)
+EXTERN(__irq_usart3)
+EXTERN(__irq_exti15_10)
+EXTERN(__irq_rtcalarm)
+EXTERN(__irq_usbwakeup)
+
+EXTERN(__irq_tim8_brk)
+EXTERN(__irq_tim8_up)
+EXTERN(__irq_tim8_trg_com)
+EXTERN(__irq_tim8_cc)
+EXTERN(__irq_adc3)
+EXTERN(__irq_fsmc)
+EXTERN(__irq_sdio)
+EXTERN(__irq_tim5)
+EXTERN(__irq_spi3)
+EXTERN(__irq_uart4)
+EXTERN(__irq_uart5)
+EXTERN(__irq_tim6)
+EXTERN(__irq_tim7)
+EXTERN(__irq_dma2_channel1)
+EXTERN(__irq_dma2_channel2)
+EXTERN(__irq_dma2_channel3)
+EXTERN(__irq_dma2_channel4_5)
diff --git a/STM32F4/variants/generic_f407v/pin_map.c b/STM32F4/variants/generic_f407v/pin_map.c
new file mode 100644
index 000000000..2189902d6
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/pin_map.c
@@ -0,0 +1,210 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file   generic_f407v.cpp
+ * @author ala42
+ * @brief  generic_f407v board file.
+ */
+
+#ifdef BOARD_generic_f407v
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+//#include "generic_f407v.h"
+
+//#include "fsmc.h"
+#include <libmaple\gpio.h>
+#include <libmaple\rcc.h>
+#include <libmaple\timer.h>
+
+#include <wirish_types.h>
+
+extern timer_dev timer1;
+extern timer_dev timer2;
+extern timer_dev timer3;
+extern timer_dev timer4;
+extern timer_dev timer5;
+extern timer_dev timer6;
+extern timer_dev timer7;
+extern timer_dev timer8;
+
+/*
+typedef struct stm32_pin_info {
+    gpio_dev *gpio_device;      // Maple pin's GPIO device
+    timer_dev *timer_device;    // Pin's timer device, if any.
+    uint8 timer_channel;        // Timer channel, or 0 if none.
+    uint8 adc_channel;          // Pin ADC channel, or ADCx if none.
+    const adc_dev *adc_device;  // ADC device, if any.
+} stm32_pin_info;
+*/
+const stm32_pin_info PIN_MAP[] = { // LQFP100 package pin
+    {&GPIOA, &timer5, 1,    0, &ADC1}, // D00/PA0  | 23 | USART2_CTS | UART4_TX       | ETH_MII_CRS      | TIM2_CH1_ETR   | TIM5_CH1       | TIM8_ETR                      | ADC123_IN0/WKUP
+    {&GPIOA, &timer5, 2,    1, &ADC1}, // D01/PA1  | 24 | USART2_RTS | UART4_RX       | ETH_RMII_REF_CLK | ETH_MII_RX_CLK | TIM5_CH2       | TIM2_CH2                      | ADC123_IN1
+    {&GPIOA, &timer5, 3,    2, &ADC1}, // D02/PA2  | 25 | USART2_TX  | TIM5_CH3       | TIM9_CH1         | TIM2_CH3       | ETH_MDIO                                       | ADC123_IN2
+    {&GPIOA, &timer5, 4,    3, &ADC1}, // D03/PA3  | 26 | USART2_RX  | TIM5_CH4       | TIM9_CH2         | TIM2_CH4       | OTG_HS_ULPI_D0 | ETH_MII_COL                   | ADC123_IN3
+    {&GPIOA,    NULL, 0,    4, &ADC1}, // D04/PA4  | 29 | SPI1_NSS   | SPI3_NSS       | USART2_CK        | DCMI_HSYNC     | OTG_HS_SOF     | I2S3_WS                       | ADC12_IN4 / DAC_OUT1
+    {&GPIOA,    NULL, 0,    5, &ADC1}, // D05/PA5  | 30 | SPI1_SCK   | OTG_HS_ULPI_CK | TIM2_CH1_ETR     | TIM8_CH1N                                                       | ADC12_IN5 / DAC_OUT2
+    {&GPIOA,    NULL, 1,    6, &ADC1}, // D06/PA6  | 31 | SPI1_MISO  | TIM8_BKIN      | TIM13_CH1        | DCMI_PIXCLK    | TIM3_CH1       | TIM1_BKIN                     | ADC12_IN6
+    {&GPIOA,    NULL, 0,    7, &ADC1}, // D07/PA7  | 32 | SPI1_MOSI  | TIM8_CH1N      | TIM14_CH1        | TIM3_CH2       | ETH_MII_RX_DV  | TIM1_CH1N   / ETH_RMII_CRS_DV | ADC12_IN7
+    {&GPIOA,    NULL, 0, ADCx,  NULL}, // D08/PA8  | 67 | MCO1       | USART1_CK      | TIM1_CH1         | I2C3_SCL       | OTG_FS_SOF
+    {&GPIOA,    NULL, 0, ADCx,  NULL}, // D09/PA9  | 68 | USART1_TX  | TIM1_CH2       | I2C3_SMBA        | DCMI_D0
+    {&GPIOA,    NULL, 0, ADCx,  NULL}, // D10/PA10 | 69 | USART1_RX  | TIM1_CH3       | OTG_FS_ID        | DCMI_D1
+    {&GPIOA,    NULL, 0, ADCx,  NULL}, // D11/PA11 | 70 | USART1_CTS | CAN1_RX        | TIM1_CH4         | OTG_FS_DM
+    {&GPIOA,    NULL, 0, ADCx,  NULL}, // D12/PA12 | 71 | USART1_RTS | CAN1_TX        | TIM1_ETR         | OTG_FS_DP
+    {&GPIOA,    NULL, 0, ADCx,  NULL}, // D13/PA13 | 72 | JTMS-SWDIO
+    {&GPIOA,    NULL, 0, ADCx,  NULL}, // D14/PA14 | 76 | JTCK-SWCLK
+    {&GPIOA, &timer2, 1, ADCx,  NULL}, // D15/PA15 | 77 | JTDI       | SPI3_NSS       | I2S3_WS          | TIM2_CH1_ETR   | SPI1_NSS
+
+    {&GPIOB, &timer3, 3,    8, &ADC1}, // D16/PB0  | 35 | TIM3_CH3   | TIM8_CH2N | OTG_HS_ULPI_D1 | ETH_MII_RXD2   | TIM1_CH2N      | ADC12_IN8
+    {&GPIOB, &timer3, 4,    9, &ADC1}, // D17/PB1  | 36 | TIM3_CH4   | TIM8_CH3N | OTG_HS_ULPI_D2 | ETH_MII_RXD3   | TIM1_CH3N      | ADC12_IN9
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D18/PB2  | 37 | BOOT1    
+    {&GPIOB, &timer2, 2, ADCx,  NULL}, // D19/PB3  | 89 | JTDO       | TRACESWO  | SPI3_SCK       | I2S3_CK        | TIM2_CH2       | SPI1_SCK
+    {&GPIOB, &timer3, 1, ADCx,  NULL}, // D20/PB4  | 90 | NJTRST     | SPI3_MISO | TIM3_CH1       | SPI1_MISO      | I2S3ext_SD
+    {&GPIOB, &timer3, 2, ADCx,  NULL}, // D21/PB5  | 91 | I2C1_SMBA  | CAN2_RX   | OTG_HS_ULPI_D7 | ETH_PPS_OUT    | TIM3_CH2       | SPI1_MOSI      | SPI3_MOSI      | DCMI_D10      | I2S3_SD
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D22/PB6  | 92 | I2C1_SCL   | TIM4_CH1  | CAN2_TX        | DCMI_D5        | USART1_TX
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D23/PB7  | 93 | I2C1_SDA   | FSMC_NL   | DCMI_VSYNC     | USART1_RX      | TIM4_CH2
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D24/PB8  | 95 | TIM4_CH3   | SDIO_D4   | TIM10_CH1      | DCMI_D6        | ETH_MII_TXD3   | I2C1_SCL       | CAN1_RX
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D25/PB9  | 96 | SPI2_NSS   | I2S2_WS   | TIM4_CH4       | TIM11_CH1      | SDIO_D5        | DCMI_D7        | I2C1_SDA       | CAN1_TX
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D26/PB10 | 47 | SPI2_SCK   | I2S2_CK   | I2C2_SCL       | USART3_TX      | OTG_HS_ULPI_D3 | ETH_MII_RX_ER  | TIM2_CH3
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D27/PB11 | 48 | I2C2_SDA   | USART3_RX | OTG_HS_ULPI_D4 | ETH_RMII_TX_EN | ETH_MII_TX_EN  | TIM2_CH4
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D28/PB12 | 51 | SPI2_NSS   | I2S2_WS   | I2C2_SMBA      | USART3_CK      | TIM1_BKIN      | CAN2_RX        | OTG_HS_ULPI_D5 | ETH_RMII_TXD0 | ETH_MII_TXD0 | OTG_HS_ID
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D29/PB13 | 52 | SPI2_SCK   | I2S2_CK   | USART3_CTS     | TIM1_CH1N      | CAN2_TX        | OTG_HS_ULPI_D6 | ETH_RMII_TXD1  | ETH_MII_TXD1
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D30/PB14 | 53 | SPI2_MISO  | TIM1_CH2N | TIM12_CH1      | OTG_HS_DM      | USART3_RTS     | TIM8_CH2N      | I2S2ext_SD
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D31/PB15 | 54 | SPI2_MOSI  | I2S2_SD   | TIM1_CH3N      | TIM8_CH3N      | TIM12_CH2      | OTG_HS_DP
+                             
+    {&GPIOC,    NULL, 0,   10, &ADC1}, // D32/PC0  | 15 | OTG_HS_ULPI_STP                                                  | ADC123_IN10
+    {&GPIOC,    NULL, 0,   11, &ADC1}, // D33/PC1  | 16 | ETH_MDC                                                          | ADC123_IN11
+    {&GPIOC,    NULL, 0,   12, &ADC1}, // D34/PC2  | 17 | SPI2_MISO  | OTG_HS_ULPI_DIR  | ETH_MII_TXD2    | I2S2ext_SD     | ADC123_IN12
+    {&GPIOC,    NULL, 0,   13, &ADC1}, // D35/PC3  | 18 | SPI2_MOSI  | I2S2_SD          | OTG_HS_ULPI_NXT | ETH_MII_TX_CLK | ADC123_IN13
+    {&GPIOC,    NULL, 0,   14, &ADC1}, // D36/PC4  | 33 | ETH_RMII_RX_D0                | ETH_MII_RX_D0                    | ADC12_IN14
+    {&GPIOC,    NULL, 0,   15, &ADC1}, // D37/PC5  | 34 | ETH_RMII_RX_D1                | ETH_MII_RX_D1                    | ADC12_IN15
+    {&GPIOC, &timer8, 1, ADCx,  NULL}, // D38/PC6  | 63 | I2S2_MCK   | TIM8_CH1/SDIO_D6 | USART6_TX       | DCMI_D0/TIM3_CH1 
+    {&GPIOC, &timer8, 2, ADCx,  NULL}, // D39/PC7  | 64 | I2S3_MCK   | TIM8_CH2/SDIO_D7 | USART6_RX       | DCMI_D1/TIM3_CH2
+    {&GPIOC, &timer8, 3, ADCx,  NULL}, // D40/PC8  | 65 | TIM8_CH3   | SDIO_D0          | TIM3_CH3        | USART6_CK      | DCMI_D2
+    {&GPIOC, &timer8, 4, ADCx,  NULL}, // D41/PC9  | 66 | I2S_CKIN   | MCO2             | TIM8_CH4        | SDIO_D1        | I2C3_SDA  | DCMI_D3    | TIM3_CH4
+    {&GPIOC,    NULL, 0, ADCx,  NULL}, // D42/PC10 | 78 | SPI3_SCK   | I2S3_CK          | UART4_TX        | SDIO_D2        | DCMI_D8   | USART3_TX
+    {&GPIOC,    NULL, 0, ADCx,  NULL}, // D43/PC11 | 79 | UART4_RX   | SPI3_MISO        | SDIO_D3         | DCMI_D4        | USART3_RX | I2S3ext_SD
+    {&GPIOC,    NULL, 0, ADCx,  NULL}, // D44/PC12 | 80 | UART5_TX   | SDIO_CK          | DCMI_D9         | SPI3_MOSI      | I2S3_SD   | USART3_CK
+    {&GPIOC,    NULL, 0, ADCx,  NULL}, // D45/PC13 |  7 | RTC_OUT, RTC_TAMP1, RTC_TS
+    {&GPIOC,    NULL, 0, ADCx,  NULL}, // D46/PC14 |  8 | OSC32_IN
+    {&GPIOC,    NULL, 0, ADCx,  NULL}, // D47/PC15 |  9 | OSC32_OUT
+                             
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D48/PD0  | 81 | FSMC_D2    | CAN1_RX
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D49/PD1  | 82 | FSMC_D3    | CAN1_TX
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D50/PD2  | 83 | TIM3_ETR   | UART5_RX   | SDIO_CMD | DCMI_D11
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D51/PD3  | 84 | FSMC_CLK   | USART2_CTS
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D52/PD4  | 85 | FSMC_NOE   | USART2_RTS
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D53/PD5  | 86 | FSMC_NWE   | USART2_TX
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D54/PD6  | 87 | FSMC_NWAIT | USART2_RX
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D55/PD7  | 88 | USART2_CK  | FSMC_NE1   | FSMC_NCE2
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D56/PD8  | 55 | FSMC_D13   | USART3_TX
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D57/PD9  | 56 | FSMC_D14   | USART3_RX
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D58/PD10 | 57 | FSMC_D15   | USART3_CK
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D59/PD11 | 58 | FSMC_CLE   | FSMC_A16   | USART3_CTS
+    {&GPIOD, &timer4, 1, ADCx,  NULL}, // D60/PD12 | 59 | FSMC_ALE   | FSMC_A17   | TIM4_CH1   | USART3_RTS // remap in
+    {&GPIOD, &timer4, 2, ADCx,  NULL}, // D61/PD13 | 60 | FSMC_A18                | TIM4_CH2                // remap in
+    {&GPIOD, &timer4, 3, ADCx,  NULL}, // D62/PD14 | 61 | FSMC_D0                 | TIM4_CH3                // remap in
+    {&GPIOD, &timer4, 4, ADCx,  NULL}, // D63/PD15 | 62 | FSMC_D1                 | TIM4_CH4                // remap in
+
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D64/PE0  | 97 | TIM4_ETR  | FSMC_NBL0 | DCMI_D2
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D65/PE1  | 98 | FSMC_NBL1 | DCMI_D3
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D66/PE2  |  1 | TRACECLK  | FSMC_A23  | ETH_MII_TXD3
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D67/PE3  |  2 | TRACED0   | FSMC_A19
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D68/PE4  |  3 | TRACED1   | FSMC_A20  | DCMI_D4
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D69/PE5  |  4 | TRACED2   | FSMC_A21  | TIM9_CH1     / DCMI_D6
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D70/PE6  |  5 | TRACED3   | FSMC_A22  | TIM9_CH2     / DCMI_D7
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D71/PE7  | 38 | FSMC_D4   | TIM1_ETR
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D72/PE8  | 39 | FSMC_D5   | TIM1_CH1N
+    {&GPIOE, &timer1, 1, ADCx,  NULL}, // D73/PE9  | 40 | FSMC_D6   | TIM1_CH1   // remap in
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D74/PE10 | 41 | FSMC_D7   | TIM1_CH2N
+    {&GPIOE, &timer1, 2, ADCx,  NULL}, // D75/PE11 | 42 | FSMC_D8   | TIM1_CH2   // remap in
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D76/PE12 | 43 | FSMC_D9   | TIM1_CH3N
+    {&GPIOE, &timer1, 3, ADCx,  NULL}, // D77/PE13 | 44 | FSMC_D10  | TIM1_CH3   // remap in
+    {&GPIOE, &timer1, 4, ADCx,  NULL}, // D78/PE14 | 45 | FSMC_D11  | TIM1_CH4   // remap in
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D79/PE15 | 46 | FSMC_D12  | TIM1_BKIN
+#if 0
+    {GPIOF,  0,   NULL, 0, NULL, ADCx}, // D80/PF0
+    {GPIOF,  1,   NULL, 0, NULL, ADCx}, // D81/PF1
+    {GPIOF,  2,   NULL, 0, NULL, ADCx}, // D82/PF2
+    {GPIOF,  3,   NULL, 0, NULL, ADCx}, // D83/PF3
+    {GPIOF,  4,   NULL, 0, NULL, ADCx}, // D84/PF4
+    {GPIOF,  5,   NULL, 0, NULL, ADCx}, // D85/PF5
+    {GPIOF,  6,   NULL, 0, NULL, ADCx}, // D86/PF6
+    {GPIOF,  7,   NULL, 0, NULL, ADCx}, // D87/PF7
+    {GPIOF,  8,   NULL, 0, NULL, ADCx}, // D88/PF8
+    {GPIOF,  9,   NULL, 0, NULL, ADCx}, // D89/PF9
+    {GPIOF, 10,   NULL, 0, NULL, ADCx}, // D90/PF10
+    {GPIOF, 11,   NULL, 0, NULL, ADCx}, // D91/PF11
+    {GPIOF, 12,   NULL, 0, NULL, ADCx}, // D92/PF12
+    {GPIOF, 13,   NULL, 0, NULL, ADCx}, // D93/PF13
+    {GPIOF, 14,   NULL, 0, NULL, ADCx}, // D94/PF14
+    {GPIOF, 15,   NULL, 0, NULL, ADCx}, // D95/PF15
+
+    {GPIOG,  0,   NULL, 0, NULL, ADCx}, // D96/PG0
+    {GPIOG,  1,   NULL, 0, NULL, ADCx}, // D97/PG1
+    {GPIOG,  2,   NULL, 0, NULL, ADCx}, // D98/PG2
+    {GPIOG,  3,   NULL, 0, NULL, ADCx}, // D99/PG3
+    {GPIOG,  4,   NULL, 0, NULL, ADCx}, // D100/PG4
+    {GPIOG,  5,   NULL, 0, NULL, ADCx}, // D101/PG5
+    {GPIOG,  6,   NULL, 0, NULL, ADCx}, // D102/PG6
+    {GPIOG,  7,   NULL, 0, NULL, ADCx}, // D103/PG7 
+    {GPIOG,  8,   NULL, 0, NULL, ADCx}, // D104/PG8
+    {GPIOG,  9,   NULL, 0, NULL, ADCx}, // D105/PG9
+    {GPIOG, 10,   NULL, 0, NULL, ADCx}, // D106/PG10
+    {GPIOG, 11,   NULL, 0, NULL, ADCx}, // D107/PG11
+    {GPIOG, 12,   NULL, 0, NULL, ADCx}, // D108/PG12
+    {GPIOG, 13,   NULL, 0, NULL, ADCx}, // D109/PG13
+    {GPIOG, 14,   NULL, 0, NULL, ADCx}, // D110/PG14
+    {GPIOG, 15,   NULL, 0, NULL, ADCx}  // D111/PG15
+#endif
+};
+/* to be defined
+extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
+    0, 1, 2, 3, 15, 16, 17, 19, 20, 21, 38, 39, 49, 41, 60, 61, 62, 63, 73, 75, 77, 78
+};
+*/
+const uint8 boardADCPins[BOARD_NR_ADC_PINS] = {
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PB0, PB1, PC0, PC1, PC2, PC3, PC4, PC5
+};
+
+const uint8 boardUsedPins[BOARD_NR_USED_PINS] = {
+    BOARD_LED_PIN, BOARD_LED2_PIN, BOARD_BUTTON1_PIN, BOARD_BUTTON2_PIN, BOARD_BUTTON2_PIN,
+	BOARD_JTMS_SWDIO_PIN, BOARD_JTCK_SWCLK_PIN,
+	FLASH_CS_PIN, FLASH_CLK_PIN, FLASH_DO_PIN, FLASH_DI_PIN,
+	NRF24_CE_PIN, NRF24_CS_PIN, NRF24_IRQ_PIN,
+	BOARD_SDIO_D0, BOARD_SDIO_D1, BOARD_SDIO_D2, BOARD_SDIO_D3, BOARD_SDIO_CK, BOARD_SDIO_CMD,
+	USB_DM_PIN, USB_DP_PIN
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif // BOARD_generic_f407v
diff --git a/STM32F4/variants/generic_f407v/pins_arduino.h b/STM32F4/variants/generic_f407v/pins_arduino.h
new file mode 100644
index 000000000..3052f2eb2
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/pins_arduino.h
@@ -0,0 +1,6 @@
+
+
+
+
+// API compatibility
+#include "variant.h"
\ No newline at end of file
diff --git a/STM32F4/variants/generic_f407v/stm32_isrs.S b/STM32F4/variants/generic_f407v/stm32_isrs.S
new file mode 100644
index 000000000..34e515c08
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/stm32_isrs.S
@@ -0,0 +1,323 @@
+/* STM32 ISR weak declarations */
+
+	.thumb
+
+/* Default handler for all non-overridden interrupts and exceptions */
+	.globl	__default_handler
+	.type	__default_handler, %function
+
+__default_handler:
+	b .
+
+	.weak	__exc_nmi
+	.globl	__exc_nmi
+	.set	__exc_nmi, __default_handler
+	.weak	__exc_hardfault
+	.globl	__exc_hardfault
+	.set	__exc_hardfault, __default_handler
+	.weak	__exc_memmanage
+	.globl	__exc_memmanage
+	.set	__exc_memmanage, __default_handler
+	.weak	__exc_busfault
+	.globl	__exc_busfault
+	.set	__exc_busfault, __default_handler
+	.weak	__exc_usagefault
+	.globl	__exc_usagefault
+	.set	__exc_usagefault, __default_handler
+	.weak	__stm32reservedexception7
+	.globl	__stm32reservedexception7
+	.set	__stm32reservedexception7, __default_handler
+	.weak	__stm32reservedexception8
+	.globl	__stm32reservedexception8
+	.set	__stm32reservedexception8, __default_handler
+	.weak	__stm32reservedexception9
+	.globl	__stm32reservedexception9
+	.set	__stm32reservedexception9, __default_handler
+	.weak	__stm32reservedexception10
+	.globl	__stm32reservedexception10
+	.set	__stm32reservedexception10, __default_handler
+	.weak	__exc_svc
+	.globl	__exc_svc
+	.set	__exc_svc, __default_handler
+	.weak	__exc_debug_monitor
+	.globl	__exc_debug_monitor
+	.set	__exc_debug_monitor, __default_handler
+	.weak	__stm32reservedexception13
+	.globl	__stm32reservedexception13
+	.set	__stm32reservedexception13, __default_handler
+	.weak	__exc_pendsv
+	.globl	__exc_pendsv
+	.set	__exc_pendsv, __default_handler
+	.weak	__exc_systick
+	.globl	__exc_systick
+	.set	__exc_systick, __default_handler
+	.weak	__irq_wwdg
+	.globl	__irq_wwdg
+	.set	__irq_wwdg, __default_handler
+	.weak	__irq_pvd
+	.globl	__irq_pvd
+	.set	__irq_pvd, __default_handler
+	.weak	__irq_tamper
+	.globl	__irq_tamper
+	.set	__irq_tamper, __default_handler
+	.weak	__irq_rtc
+	.globl	__irq_rtc
+	.set	__irq_rtc, __default_handler
+	.weak	__irq_flash
+	.globl	__irq_flash
+	.set	__irq_flash, __default_handler
+	.weak	__irq_rcc
+	.globl	__irq_rcc
+	.set	__irq_rcc, __default_handler
+	.weak	__irq_exti0
+	.globl	__irq_exti0
+	.set	__irq_exti0, __default_handler
+	.weak	__irq_exti1
+	.globl	__irq_exti1
+	.set	__irq_exti1, __default_handler
+	.weak	__irq_exti2
+	.globl	__irq_exti2
+	.set	__irq_exti2, __default_handler
+	.weak	__irq_exti3
+	.globl	__irq_exti3
+	.set	__irq_exti3, __default_handler
+	.weak	__irq_exti4
+	.globl	__irq_exti4
+	.set	__irq_exti4, __default_handler
+	.weak	__irq_dma1_channel1
+	.globl	__irq_dma1_channel1
+	.set	__irq_dma1_channel1, __default_handler
+	.weak	__irq_dma1_channel2
+	.globl	__irq_dma1_channel2
+	.set	__irq_dma1_channel2, __default_handler
+	.weak	__irq_dma1_channel3
+	.globl	__irq_dma1_channel3
+	.set	__irq_dma1_channel3, __default_handler
+	.weak	__irq_dma1_channel4
+	.globl	__irq_dma1_channel4
+	.set	__irq_dma1_channel4, __default_handler
+	.weak	__irq_dma1_channel5
+	.globl	__irq_dma1_channel5
+	.set	__irq_dma1_channel5, __default_handler
+	.weak	__irq_dma1_channel6
+	.globl	__irq_dma1_channel6
+	.set	__irq_dma1_channel6, __default_handler
+	.weak	__irq_dma1_channel7
+	.globl	__irq_dma1_channel7
+	.set	__irq_dma1_channel7, __default_handler
+	.weak	__irq_adc
+	.globl	__irq_adc
+	.set	__irq_adc, __default_handler
+	.weak	__irq_usb_hp_can_tx
+	.globl	__irq_usb_hp_can_tx
+	.set	__irq_usb_hp_can_tx, __default_handler
+	.weak	__irq_usb_lp_can_rx0
+	.globl	__irq_usb_lp_can_rx0
+	.set	__irq_usb_lp_can_rx0, __default_handler
+	.weak	__irq_can_rx1
+	.globl	__irq_can_rx1
+	.set	__irq_can_rx1, __default_handler
+	.weak	__irq_can_sce
+	.globl	__irq_can_sce
+	.set	__irq_can_sce, __default_handler
+	.weak	__irq_exti9_5
+	.globl	__irq_exti9_5
+	.set	__irq_exti9_5, __default_handler
+	.weak	__irq_tim1_brk
+	.globl	__irq_tim1_brk
+	.set	__irq_tim1_brk, __default_handler
+	.weak	__irq_tim1_up
+	.globl	__irq_tim1_up
+	.set	__irq_tim1_up, __default_handler
+	.weak	__irq_tim1_trg_com
+	.globl	__irq_tim1_trg_com
+	.set	__irq_tim1_trg_com, __default_handler
+	.weak	__irq_tim1_cc
+	.globl	__irq_tim1_cc
+	.set	__irq_tim1_cc, __default_handler
+	.weak	__irq_tim2
+	.globl	__irq_tim2
+	.set	__irq_tim2, __default_handler
+	.weak	__irq_tim3
+	.globl	__irq_tim3
+	.set	__irq_tim3, __default_handler
+	.weak	__irq_tim4
+	.globl	__irq_tim4
+	.set	__irq_tim4, __default_handler
+	.weak	__irq_i2c1_ev
+	.globl	__irq_i2c1_ev
+	.set	__irq_i2c1_ev, __default_handler
+	.weak	__irq_i2c1_er
+	.globl	__irq_i2c1_er
+	.set	__irq_i2c1_er, __default_handler
+	.weak	__irq_i2c2_ev
+	.globl	__irq_i2c2_ev
+	.set	__irq_i2c2_ev, __default_handler
+	.weak	__irq_i2c2_er
+	.globl	__irq_i2c2_er
+	.set	__irq_i2c2_er, __default_handler
+	.weak	__irq_spi1
+	.globl	__irq_spi1
+	.set	__irq_spi1, __default_handler
+	.weak	__irq_spi2
+	.globl	__irq_spi2
+	.set	__irq_spi2, __default_handler
+	.weak	__irq_usart1
+	.globl	__irq_usart1
+	.set	__irq_usart1, __default_handler
+	.weak	__irq_usart2
+	.globl	__irq_usart2
+	.set	__irq_usart2, __default_handler
+	.weak	__irq_usart3
+	.globl	__irq_usart3
+	.set	__irq_usart3, __default_handler
+	.weak	__irq_exti15_10
+	.globl	__irq_exti15_10
+	.set	__irq_exti15_10, __default_handler
+	.weak	__irq_rtcalarm
+	.globl	__irq_rtcalarm
+	.set	__irq_rtcalarm, __default_handler
+	.weak	__irq_usbwakeup
+	.globl	__irq_usbwakeup
+	.set	__irq_usbwakeup, __default_handler
+#if defined (STM32_HIGH_DENSITY)
+	.weak	__irq_tim8_brk
+	.globl	__irq_tim8_brk
+	.set	__irq_tim8_brk, __default_handler
+	.weak	__irq_tim8_up
+	.globl	__irq_tim8_up
+	.set	__irq_tim8_up, __default_handler
+	.weak	__irq_tim8_trg_com
+	.globl	__irq_tim8_trg_com
+	.set	__irq_tim8_trg_com, __default_handler
+	.weak	__irq_tim8_cc
+	.globl	__irq_tim8_cc
+	.set	__irq_tim8_cc, __default_handler
+	.weak	__irq_adc3
+	.globl	__irq_adc3
+	.set	__irq_adc3, __default_handler
+	.weak	__irq_fsmc
+	.globl	__irq_fsmc
+	.set	__irq_fsmc, __default_handler
+	.weak	__irq_sdio
+	.globl	__irq_sdio
+	.set	__irq_sdio, __default_handler
+	.weak	__irq_tim5
+	.globl	__irq_tim5
+	.set	__irq_tim5, __default_handler
+	.weak	__irq_spi3
+	.globl	__irq_spi3
+	.set	__irq_spi3, __default_handler
+	.weak	__irq_uart4
+	.globl	__irq_uart4
+	.set	__irq_uart4, __default_handler
+	.weak	__irq_uart5
+	.globl	__irq_uart5
+	.set	__irq_uart5, __default_handler
+	.weak	__irq_tim6
+	.globl	__irq_tim6
+	.set	__irq_tim6, __default_handler
+	.weak	__irq_tim7
+	.globl	__irq_tim7
+	.set	__irq_tim7, __default_handler
+	.weak	__irq_dma2_channel1
+	.globl	__irq_dma2_channel1
+	.set	__irq_dma2_channel1, __default_handler
+	.weak	__irq_dma2_channel2
+	.globl	__irq_dma2_channel2
+	.set	__irq_dma2_channel2, __default_handler
+	.weak	__irq_dma2_channel3
+	.globl	__irq_dma2_channel3
+	.set	__irq_dma2_channel3, __default_handler
+	.weak	__irq_dma2_channel4_5
+	.globl	__irq_dma2_channel4_5
+	.set	__irq_dma2_channel4_5, __default_handler
+#endif /* STM32_HIGH_DENSITY */
+
+	.weak	__irq_DMA2_Stream4_IRQHandler              
+	.globl	__irq_DMA2_Stream4_IRQHandler              
+	.set	__irq_DMA2_Stream4_IRQHandler, __default_handler
+
+  .weak	__irq_ETH_IRQHandler                       
+  .globl	__irq_ETH_IRQHandler                       
+  .set	__irq_ETH_IRQHandler, __default_handler
+
+  .weak	__irq_ETH_WKUP_IRQHandler                         
+  .globl	__irq_ETH_WKUP_IRQHandler                         
+  .set	__irq_ETH_WKUP_IRQHandler, __default_handler  
+
+  .weak	__irq_CAN2_TX_IRQHandler                          
+  .globl	__irq_CAN2_TX_IRQHandler                          
+  .set	__irq_CAN2_TX_IRQHandler, __default_handler    
+
+  .weak	__irq_CAN2_RX0_IRQHandler                         
+  .globl	__irq_CAN2_RX0_IRQHandler                         
+  .set	__irq_CAN2_RX0_IRQHandler, __default_handler      
+
+  .weak	__irq_CAN2_RX1_IRQHandler                         
+  .globl	__irq_CAN2_RX1_IRQHandler                         
+  .set	__irq_CAN2_RX1_IRQHandler, __default_handler        
+
+  .weak	__irq_CAN2_SCE_IRQHandler                         
+  .globl	__irq_CAN2_SCE_IRQHandler                         
+  .set	__irq_CAN2_SCE_IRQHandler, __default_handler          
+
+  .weak	__irq_OTG_FS_IRQHandler                    
+  .globl	__irq_OTG_FS_IRQHandler                    
+  .set	__irq_OTG_FS_IRQHandler, __default_handler            
+
+  .weak	__irq_DMA2_Stream5_IRQHandler              
+  .globl	__irq_DMA2_Stream5_IRQHandler              
+  .set	__irq_DMA2_Stream5_IRQHandler, __default_handler              
+
+  .weak	__irq_DMA2_Stream6_IRQHandler              
+  .globl	__irq_DMA2_Stream6_IRQHandler              
+  .set	__irq_DMA2_Stream6_IRQHandler, __default_handler                
+
+  .weak	__irq_DMA2_Stream7_IRQHandler              
+  .globl	__irq_DMA2_Stream7_IRQHandler              
+  .set	__irq_DMA2_Stream7_IRQHandler, __default_handler                  
+
+  .weak	__irq_USART6_IRQHandler                     
+  .globl	__irq_USART6_IRQHandler                     
+  .set	__irq_USART6_IRQHandler, __default_handler                    
+
+  .weak	__irq_I2C3_EV_IRQHandler                          
+  .globl	__irq_I2C3_EV_IRQHandler                          
+  .set	__irq_I2C3_EV_IRQHandler, __default_handler                      
+
+  .weak	__irq_I2C3_ER_IRQHandler                          
+  .globl	__irq_I2C3_ER_IRQHandler                          
+  .set	__irq_I2C3_ER_IRQHandler, __default_handler                        
+
+  .weak	__irq_OTG_HS_EP1_OUT_IRQHandler              
+  .globl	__irq_OTG_HS_EP1_OUT_IRQHandler              
+  .set	__irq_OTG_HS_EP1_OUT_IRQHandler, __default_handler                          
+
+  .weak	__irq_OTG_HS_EP1_IN_IRQHandler              
+  .globl	__irq_OTG_HS_EP1_IN_IRQHandler              
+  .set	__irq_OTG_HS_EP1_IN_IRQHandler, __default_handler                            
+
+  .weak	__irq_OTG_HS_WKUP_IRQHandler                       
+  .globl	__irq_OTG_HS_WKUP_IRQHandler                       
+  .set	__irq_OTG_HS_WKUP_IRQHandler, __default_handler                              
+
+  .weak	__irq_OTG_HS_IRQHandler                    
+  .globl	__irq_OTG_HS_IRQHandler                    
+  .set	__irq_OTG_HS_IRQHandler, __default_handler                                
+
+  .weak	__irq_DCMI_IRQHandler                      
+  .globl	__irq_DCMI_IRQHandler                      
+  .set	__irq_DCMI_IRQHandler, __default_handler                                  
+
+  .weak	__irq_CRYP_IRQHandler                      
+  .globl	__irq_CRYP_IRQHandler                      
+  .set	__irq_CRYP_IRQHandler, __default_handler                                    
+
+  .weak	__irq_HASH_RNG_IRQHandler    
+  .globl	__irq_HASH_RNG_IRQHandler    
+  .set	__irq_HASH_RNG_IRQHandler, __default_handler                                      
+
+  .weak	__irq_FPU_IRQHandler         
+  .globl	__irq_FPU_IRQHandler         
+  .set	__irq_FPU_IRQHandler, __default_handler                                        
diff --git a/STM32F4/variants/generic_f407v/stm32_vector_table.S b/STM32F4/variants/generic_f407v/stm32_vector_table.S
new file mode 100644
index 000000000..9f08d6669
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/stm32_vector_table.S
@@ -0,0 +1,113 @@
+/* STM32 vector table */
+
+	.section	".stm32.interrupt_vector"
+
+	.globl	__stm32_vector_table
+	.type	__stm32_vector_table, %object
+
+__stm32_vector_table:
+/* CM3 core interrupts */
+	.long	__msp_init
+	.long	__exc_reset
+	.long	__exc_nmi
+	.long	__exc_hardfault
+	.long	__exc_memmanage
+	.long	__exc_busfault
+	.long	__exc_usagefault
+	.long	__stm32reservedexception7
+	.long	__stm32reservedexception8
+	.long	__stm32reservedexception9
+	.long	__stm32reservedexception10
+	.long	__exc_svc
+	.long	__exc_debug_monitor
+	.long	__stm32reservedexception13
+	.long	__exc_pendsv
+	.long	__exc_systick
+/* Peripheral interrupts */
+	.long	__irq_wwdg
+	.long	__irq_pvd
+	.long	__irq_tamper
+	.long	__irq_rtc
+	.long	__irq_flash
+	.long	__irq_rcc
+	.long	__irq_exti0
+	.long	__irq_exti1
+	.long	__irq_exti2
+	.long	__irq_exti3
+	.long	__irq_exti4
+	.long	__irq_dma1_channel1
+	.long	__irq_dma1_channel2
+	.long	__irq_dma1_channel3
+	.long	__irq_dma1_channel4
+	.long	__irq_dma1_channel5
+	.long	__irq_dma1_channel6
+	.long	__irq_dma1_channel7
+	.long	__irq_adc
+	.long	__irq_usb_hp_can_tx
+	.long	__irq_usb_lp_can_rx0
+	.long	__irq_can_rx1
+	.long	__irq_can_sce
+	.long	__irq_exti9_5
+	.long	__irq_tim1_brk
+	.long	__irq_tim1_up
+	.long	__irq_tim1_trg_com
+	.long	__irq_tim1_cc
+	.long	__irq_tim2
+	.long	__irq_tim3
+	.long	__irq_tim4
+	.long	__irq_i2c1_ev
+	.long	__irq_i2c1_er
+	.long	__irq_i2c2_ev
+	.long	__irq_i2c2_er
+	.long	__irq_spi1
+	.long	__irq_spi2
+	.long	__irq_usart1
+	.long	__irq_usart2
+	.long	__irq_usart3
+	.long	__irq_exti15_10
+	.long	__irq_rtcalarm
+	.long	__irq_usbwakeup
+#if defined (STM32_HIGH_DENSITY)
+	.long	__irq_tim8_brk
+	.long	__irq_tim8_up
+	.long	__irq_tim8_trg_com
+	.long	__irq_tim8_cc
+	.long	__irq_adc3
+	.long	__irq_fsmc
+	.long	__irq_sdio
+	.long	__irq_tim5
+	.long	__irq_spi3
+	.long	__irq_uart4
+	.long	__irq_uart5
+	.long	__irq_tim6
+	.long	__irq_tim7
+	.long	__irq_dma2_channel1
+	.long	__irq_dma2_channel2
+	.long	__irq_dma2_channel3
+	.long	__irq_dma2_channel4_5
+#endif /* STM32_HIGH_DENSITY */
+
+  .long	__irq_DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */                   
+  .long	__irq_ETH_IRQHandler                    /* Ethernet                     */                   
+  .long	__irq_ETH_WKUP_IRQHandler               /* Ethernet Wakeup through EXTI line */                     
+  .long	__irq_CAN2_TX_IRQHandler                /* CAN2 TX                      */                          
+  .long	__irq_CAN2_RX0_IRQHandler               /* CAN2 RX0                     */                          
+  .long	__irq_CAN2_RX1_IRQHandler               /* CAN2 RX1                     */                          
+  .long	__irq_CAN2_SCE_IRQHandler               /* CAN2 SCE                     */                          
+  .long	__irq_OTG_FS_IRQHandler                 /* USB OTG FS                   */                   
+  .long	__irq_DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */                   
+  .long	__irq_DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */                   
+  .long	__irq_DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */                   
+  .long	__irq_USART6_IRQHandler                 /* USART6                       */                    
+  .long	__irq_I2C3_EV_IRQHandler                /* I2C3 event                   */                          
+  .long	__irq_I2C3_ER_IRQHandler                /* I2C3 error                   */                          
+  .long	__irq_OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */                   
+  .long	__irq_OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */                   
+  .long	__irq_OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */                         
+  .long	__irq_OTG_HS_IRQHandler                 /* USB OTG HS                   */                   
+  .long	__irq_DCMI_IRQHandler                   /* DCMI                         */                   
+  .long	__irq_CRYP_IRQHandler                   /* CRYP crypto                  */                   
+  .long	__irq_HASH_RNG_IRQHandler               /* Hash and Rng                 */
+  .long	__irq_FPU_IRQHandler                    /* FPU                          */
+
+	.size	__stm32_vector_table, . - __stm32_vector_table
diff --git a/STM32F4/variants/generic_f407v/variant.h b/STM32F4/variants/generic_f407v/variant.h
new file mode 100644
index 000000000..cd0a96de4
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/variant.h
@@ -0,0 +1,21 @@
+#ifndef _VARIANT_ARDUINO_STM32_
+#define _VARIANT_ARDUINO_STM32_
+
+
+#define digitalPinToPort(P)        ( PIN_MAP[P].gpio_device )
+#define digitalPinToBitMask(P)     ( BIT(PIN_MAP[P].gpio_bit) )
+#define portOutputRegister(port)   ( &(port->regs->ODR) )
+#define portInputRegister(port)    ( &(port->regs->IDR) )
+
+#define portSetRegister(pin)		( &(PIN_MAP[pin].gpio_device->regs->BSRR) )
+#define portClearRegister(pin)		( &(PIN_MAP[pin].gpio_device->regs->BRR) )
+
+#define portConfigRegister(pin)		( &(PIN_MAP[pin].gpio_device->regs->CRL) )
+
+static const uint8_t SS   = BOARD_SPI1_NSS_PIN;
+static const uint8_t SS1  = BOARD_SPI2_NSS_PIN;
+static const uint8_t MOSI = BOARD_SPI1_MOSI_PIN;
+static const uint8_t MISO = BOARD_SPI1_MISO_PIN;
+static const uint8_t SCK  = BOARD_SPI1_SCK_PIN;
+
+#endif /* _VARIANT_ARDUINO_STM32_ */
\ No newline at end of file
diff --git a/STM32F4/cores/maple/libmaple/rcc.c b/STM32F4/variants/generic_f407v/wirish/start.S
similarity index 54%
rename from STM32F4/cores/maple/libmaple/rcc.c
rename to STM32F4/variants/generic_f407v/wirish/start.S
index b3cb9c5d1..8b181aa99 100644
--- a/STM32F4/cores/maple/libmaple/rcc.c
+++ b/STM32F4/variants/generic_f407v/wirish/start.S
@@ -1,7 +1,7 @@
 /******************************************************************************
  * The MIT License
  *
- * Copyright (c) 2010 Perry Hung.
+ * Copyright (c) 2011 LeafLabs, LLC.
  *
  * Permission is hereby granted, free of charge, to any person
  * obtaining a copy of this software and associated documentation
@@ -24,14 +24,34 @@
  * SOFTWARE.
  *****************************************************************************/
 
-/**
- * @file rcc.c
- * @brief Implements pretty much only the basic clock setup on the
- *        stm32, clock enable/disable and peripheral reset commands.
+/*
+ * This file is a modified version of a file obtained from
+ * CodeSourcery Inc. (now part of Mentor Graphics Corp.), in which the
+ * following text appeared:
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
  */
 
-// #ifdef STM32F2
-// #include "rccF2.c"
-// #else
-// #include "rccF1.c"
-// #endif
+        .text
+        .code 16
+        .thumb_func
+
+        .globl __start__
+        .type __start__, %function
+__start__:
+        .fnstart
+        ldr r1,=__msp_init
+        mov sp,r1
+        ldr r1,=start_c
+        bx r1
+        .pool
+        .cantunwind
+        .fnend
diff --git a/STM32F4/variants/generic_f407v/wirish/start_c.c b/STM32F4/variants/generic_f407v/wirish/start_c.c
new file mode 100644
index 000000000..655fefb88
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/wirish/start_c.c
@@ -0,0 +1,95 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/*
+ * This file is a modified version of a file obtained from
+ * CodeSourcery Inc. (now part of Mentor Graphics Corp.), in which the
+ * following text appeared:
+ *
+ * Copyright (c) 2006, 2007 CodeSourcery Inc
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+#include <stddef.h>
+
+extern void __libc_init_array(void);
+
+extern int main(int, char**, char**);
+
+extern void exit(int) __attribute__((noreturn, weak));
+
+/* The linker must ensure that these are at least 4-byte aligned. */
+extern char __data_start__, __data_end__;
+extern char __bss_start__, __bss_end__;
+
+struct rom_img_cfg {
+    int *img_start;
+};
+
+extern char _lm_rom_img_cfgp;
+
+void __attribute__((noreturn)) start_c(void) {
+    struct rom_img_cfg *img_cfg = (struct rom_img_cfg*)&_lm_rom_img_cfgp;
+    int *src = img_cfg->img_start;
+    int *dst = (int*)&__data_start__;
+    int exit_code;
+
+    /* Initialize .data, if necessary. */
+    if (src != dst) {
+        int *end = (int*)&__data_end__;
+        while (dst < end) {
+            *dst++ = *src++;
+        }
+    }
+
+    /* Zero .bss. */
+    dst = (int*)&__bss_start__;
+    while (dst < (int*)&__bss_end__) {
+        *dst++ = 0;
+    }
+
+    /* Run initializers. */
+    __libc_init_array();
+
+    /* Jump to main. */
+    exit_code = main(0, 0, 0);
+    if (exit) {
+        exit(exit_code);
+    }
+
+    /* If exit is NULL, make sure we don't return. */
+    for (;;)
+        continue;
+}

From 220247c115287b4208407c34ee080d609e5bab0e Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Fri, 12 May 2017 20:51:12 +0200
Subject: [PATCH 073/307] bugfix: other variants than generic did not work

---
 STM32F4/boards.txt                            |  22 +-
 STM32F4/cores/maple/libmaple/gpioF4.c         |  10 +-
 STM32F4/cores/maple/wirish_types.h            |   4 +-
 STM32F4/libraries/SPI/src/SPI.h               |   1 +
 .../variants/discovery_f407/discovery_f4.cpp  | 287 +++++++++---------
 .../variants/discovery_f407/discovery_f4.h    |   3 +
 6 files changed, 176 insertions(+), 151 deletions(-)

diff --git a/STM32F4/boards.txt b/STM32F4/boards.txt
index 04bfd0fd0..8fc143071 100644
--- a/STM32F4/boards.txt
+++ b/STM32F4/boards.txt
@@ -31,6 +31,12 @@ discovery_f407.build.error_led_port=GPIOD
 discovery_f407.build.error_led_pin=14
 discovery_f407.build.board=STM32DiscoveryF407
 
+discovery_f407.menu.usb_cfg.usb_nc=USB inactive
+discovery_f407.menu.usb_cfg.usb_nc.build.cpu_flags=-DUSB_NC
+discovery_f407.menu.usb_cfg.usb_serial=USB serial (CDC)
+discovery_f407.menu.usb_cfg.usb_serial.build.cpu_flags=-DSERIAL_USB
+discovery_f407.menu.usb_cfg.usb_msc=USB Mass Storage (MSC)
+discovery_f407.menu.usb_cfg.usb_msc.build.cpu_flags=-DUSB_MSC
 ##############################################################
 generic_f407v.name=Generic STM32F407V series
 
@@ -88,7 +94,7 @@ stm32f4stamp.upload.dfuse_addr=0x8000000
 stm32f4stamp.build.mcu=cortex-m4
 stm32f4stamp.build.f_cpu=168000000L
 stm32f4stamp.build.core=maple
-stm32f4stamp.build.extra_flags=-DMCU_STM32F406VG -mthumb -DSTM32_HIGH_DENSITY -DSTM32F2 -DSTM32F4 -DBOARD_discovery_f4
+stm32f4stamp.build.extra_flags=-DMCU_STM32F406VG -mthumb -DSTM32_HIGH_DENSITY -DSTM32F4 -DBOARD_discovery_f4
 stm32f4stamp.build.ldscript=ld/jtag.ld
 stm32f4stamp.build.variant=discovery_f407
 stm32f4stamp.build.variant_system_lib=lib_f407.a
@@ -98,6 +104,12 @@ stm32f4stamp.build.error_led_port=GPIOD
 stm32f4stamp.build.error_led_pin=14
 stm32f4stamp.build.board=STM32F4StampF405
 
+stm32f4stamp.menu.usb_cfg.usb_nc=USB inactive
+stm32f4stamp.menu.usb_cfg.usb_nc.build.cpu_flags=-DUSB_NC
+stm32f4stamp.menu.usb_cfg.usb_serial=USB serial (CDC)
+stm32f4stamp.menu.usb_cfg.usb_serial.build.cpu_flags=-DSERIAL_USB
+stm32f4stamp.menu.usb_cfg.usb_msc=USB Mass Storage (MSC)
+stm32f4stamp.menu.usb_cfg.usb_msc.build.cpu_flags=-DUSB_MSC
 ##############################################################
 netduino2plus.name=Netduino2 F405
 
@@ -118,7 +130,7 @@ netduino2plus.upload.dfuse_addr=0x8000000
 netduino2plus.build.mcu=cortex-m4
 netduino2plus.build.f_cpu=168000000L
 netduino2plus.build.core=maple
-netduino2plus.build.extra_flags=-DMCU_STM32F406VG -mthumb -DSTM32_HIGH_DENSITY -DSTM32F2 -DSTM32F4 -DBOARD_discovery_f4 -DARDUINO_STM32F4_NETDUINO2PLUS
+netduino2plus.build.extra_flags=-DMCU_STM32F406VG -mthumb -DSTM32_HIGH_DENSITY -DSTM32F4 -DBOARD_discovery_f4 -DARDUINO_STM32F4_NETDUINO2PLUS
 netduino2plus.build.ldscript=ld/jtag.ld
 netduino2plus.build.variant=discovery_f407
 netduino2plus.build.variant_system_lib=lib_f407.a
@@ -128,5 +140,11 @@ netduino2plus.build.error_led_port=GPIOD
 netduino2plus.build.error_led_pin=14
 netduino2plus.build.board=Netduino2F405
 
+netduino2plus.menu.usb_cfg.usb_nc=USB inactive
+netduino2plus.menu.usb_cfg.usb_nc.build.cpu_flags=-DUSB_NC
+netduino2plus.menu.usb_cfg.usb_serial=USB serial (CDC)
+netduino2plus.menu.usb_cfg.usb_serial.build.cpu_flags=-DSERIAL_USB
+netduino2plus.menu.usb_cfg.usb_msc=USB Mass Storage (MSC)
+netduino2plus.menu.usb_cfg.usb_msc.build.cpu_flags=-DUSB_MSC
 ##############################################################
 
diff --git a/STM32F4/cores/maple/libmaple/gpioF4.c b/STM32F4/cores/maple/libmaple/gpioF4.c
index 67d3bea53..af839ebea 100644
--- a/STM32F4/cores/maple/libmaple/gpioF4.c
+++ b/STM32F4/cores/maple/libmaple/gpioF4.c
@@ -124,14 +124,14 @@ void gpio_init_all(void) {
 
 #ifdef ARDUINO_STM32F4_NETDUINO2PLUS
     // PA8 Output the Master Clock MCO1
-    gpio_set_af_mode(GPIOA, 8, 0);
-    gpio_set_mode(GPIOA, 8, GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
+    gpio_set_af_mode(PA8, 0);
+    gpio_set_mode(PA8, GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
     // PB4 as alternate MISO Input
-    gpio_set_af_mode(GPIOB, 4, 5);
+    gpio_set_af_mode(PB4, 5);
     // PA5 as alternate SCK Output
-    gpio_set_af_mode(GPIOA, 5, 5);
+    gpio_set_af_mode(PA5, 5);
     // PA7 as alternate MOSI Output
-    gpio_set_af_mode(GPIOA, 7, 5);
+    gpio_set_af_mode(PA7, 5);
 #endif
 }
 
diff --git a/STM32F4/cores/maple/wirish_types.h b/STM32F4/cores/maple/wirish_types.h
index 6a8c85c3e..de685bf9f 100644
--- a/STM32F4/cores/maple/wirish_types.h
+++ b/STM32F4/cores/maple/wirish_types.h
@@ -60,13 +60,11 @@ typedef struct stm32_pin_info {
 #else
 
 typedef struct stm32_pin_info {
-    gpio_dev *gpio_device;      /**< Maple pin's GPIO device */
+    const gpio_dev *gpio_device;      /**< Maple pin's GPIO device */
     timer_dev *timer_device;    /**< Pin's timer device, if any. */
     const adc_dev *adc_device;  /**< ADC device, if any. */
-    uint8 gpio_bit;             /**< Pin's GPIO port bit. */
     uint8 timer_channel;        /**< Timer channel, or 0 if none. */
     uint8 adc_channel;          /**< Pin ADC channel, or ADCx if none. */
-    uint8 filler;
 } stm32_pin_info;
 
 #endif
diff --git a/STM32F4/libraries/SPI/src/SPI.h b/STM32F4/libraries/SPI/src/SPI.h
index 218449fb1..cabc0c260 100644
--- a/STM32F4/libraries/SPI/src/SPI.h
+++ b/STM32F4/libraries/SPI/src/SPI.h
@@ -42,6 +42,7 @@
 #include <libmaple/dma.h>
 #include <wirish.h>
 
+#define SPI_DMA
 
 // SPI_HAS_TRANSACTION means SPI has
 //   - beginTransaction()
diff --git a/STM32F4/variants/discovery_f407/discovery_f4.cpp b/STM32F4/variants/discovery_f407/discovery_f4.cpp
index d97074e5c..74660f0b9 100644
--- a/STM32F4/variants/discovery_f407/discovery_f4.cpp
+++ b/STM32F4/variants/discovery_f407/discovery_f4.cpp
@@ -34,182 +34,187 @@
 
 #include "discovery_f4.h"
 
-//#include "fsmc.h"
-#include "gpio.h"
-#include "rcc.h"
-#include "timer.h"
+#include <libmaple\gpio.h>
+#include <libmaple\rcc.h>
 
 #include "wirish_types.h"
 
 //static void initSRAMChip(void);
 void boardInit(void) {
 	// remap TIMER8 to PC6-9
-	gpio_set_af_mode(GPIOC, 6, 3);
-	gpio_set_af_mode(GPIOC, 7, 3);
-	gpio_set_af_mode(GPIOC, 8, 3);
-	gpio_set_af_mode(GPIOC, 9, 3);
+	gpio_set_af_mode(PC6, 3);
+	gpio_set_af_mode(PC7, 3);
+	gpio_set_af_mode(PC8, 3);
+	gpio_set_af_mode(PC9, 3);
 
 	// remap TIMER1 to PE9,11,13,14
-	gpio_set_af_mode(GPIOE,  9, 1);
-	gpio_set_af_mode(GPIOE, 11, 1);
-	gpio_set_af_mode(GPIOE, 13, 1);
-	gpio_set_af_mode(GPIOE, 14, 1);
+	gpio_set_af_mode(PE9, 1);
+	gpio_set_af_mode(PE11, 1);
+	gpio_set_af_mode(PE13, 1);
+	gpio_set_af_mode(PE14, 1);
 
 	// remap TIMER3 to PB4,5,0,1
-	gpio_set_af_mode(GPIOB,  4, 2);
-	gpio_set_af_mode(GPIOB,  5, 2);
-	gpio_set_af_mode(GPIOB,  0, 2);
-	gpio_set_af_mode(GPIOB,  1, 2);
+	gpio_set_af_mode(PB4, 2);
+	gpio_set_af_mode(PB5, 2);
+	gpio_set_af_mode(PB0, 2);
+	gpio_set_af_mode(PB1, 2);
 
 	//gpio_set_af_mode(GPIOA, 2, 7);
 	//gpio_set_af_mode(GPIOA, 3, 7);
 
 #ifdef ARDUINO_STM32F4_NETDUINO2PLUS
     // PA8 Output the Master Clock MCO1
-    gpio_set_af_mode(GPIOA, 8, 0);
+    gpio_set_af_mode(PA8, 0);
     // PB4 as alternate MISO Input
-    gpio_set_af_mode(GPIOB, 4, 5);
+    gpio_set_af_mode(PB4, 5);
     // PA5 as alternate SCK Output
-    gpio_set_af_mode(GPIOA, 5, 5);
+    gpio_set_af_mode(PA5, 5);
     // PA7 as alternate MOSI Output
-    gpio_set_af_mode(GPIOA, 7, 5);
+    gpio_set_af_mode(PA7, 5);
 #endif
 	return;
 }
 
 
+extern timer_dev timer1;
+extern timer_dev timer2;
+extern timer_dev timer3;
+extern timer_dev timer4;
+extern timer_dev timer5;
+extern timer_dev timer6;
+extern timer_dev timer7;
+extern timer_dev timer8;
+
 #if 0
 typedef struct stm32_pin_info {
     gpio_dev *gpio_device;      /**< Maple pin's GPIO device */
     timer_dev *timer_device;    /**< Pin's timer device, if any. */
     const adc_dev *adc_device;  /**< ADC device, if any. */
-    uint8 gpio_bit;             /**< Pin's GPIO port bit. */
     uint8 timer_channel;        /**< Timer channel, or 0 if none. */
     uint8 adc_channel;          /**< Pin ADC channel, or ADCx if none. */
 } stm32_pin_info;
-
 #endif
 
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
-    {GPIOA, TIMER5, ADC1,  0, 1,    0}, /* D00/PA0  */
-    {GPIOA, TIMER5, ADC1,  1, 2,    1}, /* D01/PA1  */
-    {GPIOA, TIMER5, ADC1,  2, 3,    2}, /* D02/PA2  */
-    {GPIOA, TIMER5, ADC1,  3, 4,    3}, /* D03/PA3  */
-    {GPIOA,   NULL, ADC1,  4, 0,    4}, /* D04/PA4  */
-    {GPIOA,   NULL, ADC1,  5, 0,    5}, /* D05/PA5  */
-    {GPIOA,   NULL, ADC1,  6, 1,    6}, /* D06/PA6  */ // ala check TIMER3
-    {GPIOA,   NULL, ADC1,  7, 0,    7}, /* D07/PA7  */
-    {GPIOA,   NULL, NULL,  8, 0, ADCx}, /* D08/PA8  */ // remap out
-    {GPIOA,   NULL, NULL,  9, 0, ADCx}, /* D09/PA9  */ // remap out
-    {GPIOA,   NULL, NULL, 10, 0, ADCx}, /* D10/PA10 */ // remap out
-    {GPIOA,   NULL, NULL, 11, 0, ADCx}, /* D11/PA11 */ // remap out
-    {GPIOA,   NULL, NULL, 12, 0, ADCx}, /* D12/PA12 */
-    {GPIOA,   NULL, NULL, 13, 0, ADCx}, /* D13/PA13 */
-    {GPIOA,   NULL, NULL, 14, 0, ADCx}, /* D14/PA14 */
-    {GPIOA, TIMER2, NULL, 15, 1, ADCx}, /* D15/PA15 */ // remap in
-
-    {GPIOB, TIMER3, ADC1,  0, 3,    8}, /* D16/PB0  */
-    {GPIOB, TIMER3, ADC1,  1, 4,    9}, /* D17/PB1  */
-    {GPIOB,   NULL, NULL,  2, 0, ADCx}, /* D18/PB2  */
-    {GPIOB, TIMER2, NULL,  3, 2, ADCx}, /* D19/PB3  */ // remap in
-    {GPIOB, TIMER3, NULL,  4, 1, ADCx}, /* D20/PB4  */ // remap in
-    {GPIOB, TIMER3, NULL,  5, 2, ADCx}, /* D21/PB5  */ // remap in
-    {GPIOB,   NULL, NULL,  6, 0, ADCx}, /* D22/PB6  */ // remap out
-    {GPIOB,   NULL, NULL,  7, 0, ADCx}, /* D23/PB7  */ // remap out
-    {GPIOB,   NULL, NULL,  8, 0, ADCx}, /* D24/PB8  */ // remap out
-    {GPIOB,   NULL, NULL,  9, 0, ADCx}, /* D25/PB9  */ // remap out
-    {GPIOB,   NULL, NULL, 10, 0, ADCx}, /* D26/PB10 */
-    {GPIOB,   NULL, NULL, 11, 0, ADCx}, /* D27/PB11 */
-    {GPIOB,   NULL, NULL, 12, 0, ADCx}, /* D28/PB12 */
-    {GPIOB,   NULL, NULL, 13, 0, ADCx}, /* D29/PB13 */
-    {GPIOB,   NULL, NULL, 14, 0, ADCx}, /* D30/PB14 */
-    {GPIOB,   NULL, NULL, 15, 0, ADCx}, /* D31/PB15 */
-
-    {GPIOC,   NULL, ADC1,  0, 0,   10}, /* D32/PC0  */
-    {GPIOC,   NULL, ADC1,  1, 0,   11}, /* D33/PC1  */
-    {GPIOC,   NULL, ADC1,  2, 0,   12}, /* D34/PC2  */
-    {GPIOC,   NULL, ADC1,  3, 0,   13}, /* D35/PC3  */
-    {GPIOC,   NULL, ADC1,  4, 0,   14}, /* D36/PC4  */
-    {GPIOC,   NULL, ADC1,  5, 0,   15}, /* D37/PC5  */
-    {GPIOC, TIMER8, NULL,  6, 1, ADCx}, /* D38/PC6  */
-    {GPIOC, TIMER8, NULL,  7, 2, ADCx}, /* D39/PC7  */
-    {GPIOC, TIMER8, NULL,  8, 3, ADCx}, /* D40/PC8  */
-    {GPIOC, TIMER8, NULL,  9, 4, ADCx}, /* D41/PC9  */
-    {GPIOC,   NULL, NULL, 10, 0, ADCx}, /* D42/PC10 */
-    {GPIOC,   NULL, NULL, 11, 0, ADCx}, /* D43/PC11 */
-    {GPIOC,   NULL, NULL, 12, 0, ADCx}, /* D44/PC12 */
-    {GPIOC,   NULL, NULL, 13, 0, ADCx}, /* D45/PC13 */
-    {GPIOC,   NULL, NULL, 14, 0, ADCx}, /* D46/PC14 */
-    {GPIOC,   NULL, NULL, 15, 0, ADCx}, /* D47/PC15 */
-
-    {GPIOD,   NULL, NULL,  0, 0, ADCx}, /* D48/PD0  */
-    {GPIOD,   NULL, NULL,  1, 0, ADCx}, /* D49/PD1  */
-    {GPIOD,   NULL, NULL,  2, 0, ADCx}, /* D50/PD2  */
-    {GPIOD,   NULL, NULL,  3, 0, ADCx}, /* D51/PD3  */
-    {GPIOD,   NULL, NULL,  4, 0, ADCx}, /* D52/PD4  */
-    {GPIOD,   NULL, NULL,  5, 0, ADCx}, /* D53/PD5  */
-    {GPIOD,   NULL, NULL,  6, 0, ADCx}, /* D54/PD6  */
-    {GPIOD,   NULL, NULL,  7, 0, ADCx}, /* D55/PD7  */
-    {GPIOD,   NULL, NULL,  8, 0, ADCx}, /* D56/PD8  */
-    {GPIOD,   NULL, NULL,  9, 0, ADCx}, /* D57/PD9  */
-    {GPIOD,   NULL, NULL, 10, 0, ADCx}, /* D58/PD10 */
-    {GPIOD,   NULL, NULL, 11, 0, ADCx}, /* D59/PD11 */
-    {GPIOD, TIMER4, NULL, 12, 1, ADCx}, /* D60/PD12 */  // remap in
-    {GPIOD, TIMER4, NULL, 13, 2, ADCx}, /* D61/PD13 */  // remap in
-    {GPIOD, TIMER4, NULL, 14, 3, ADCx}, /* D62/PD14 */  // remap in
-    {GPIOD, TIMER4, NULL, 15, 4, ADCx}, /* D63/PD15 */  // remap in
-
-    {GPIOE,   NULL, NULL,  0, 0, ADCx}, /* D64/PE0  */
-    {GPIOE,   NULL, NULL,  1, 0, ADCx}, /* D65/PE1  */
-    {GPIOE,   NULL, NULL,  2, 0, ADCx}, /* D66/PE2  */
-    {GPIOE,   NULL, NULL,  3, 0, ADCx}, /* D67/PE3  */
-    {GPIOE,   NULL, NULL,  4, 0, ADCx}, /* D68/PE4  */
-    {GPIOE,   NULL, NULL,  5, 0, ADCx}, /* D69/PE5  */
-    {GPIOE,   NULL, NULL,  6, 0, ADCx}, /* D70/PE6  */
-    {GPIOE,   NULL, NULL,  7, 0, ADCx}, /* D71/PE7  */
-    {GPIOE,   NULL, NULL,  8, 0, ADCx}, /* D72/PE8  */
-    {GPIOE, TIMER1, NULL,  9, 1, ADCx}, /* D73/PE9  */  // remap in
-    {GPIOE,   NULL, NULL, 10, 0, ADCx}, /* D74/PE10 */
-    {GPIOE, TIMER1, NULL, 11, 2, ADCx}, /* D75/PE11 */  // remap in
-    {GPIOE,   NULL, NULL, 12, 0, ADCx}, /* D76/PE12 */
-    {GPIOE, TIMER1, NULL, 13, 3, ADCx}, /* D77/PE13 */  // remap in
-    {GPIOE, TIMER1, NULL, 14, 4, ADCx}, /* D78/PE14 */  // remap in
-    {GPIOE,   NULL, NULL, 15, 0, ADCx},  /* D79/PE15 */
-
-    {GPIOF,   NULL, NULL,  0, 0, ADCx}, /* D80/PF0  */
-    {GPIOF,   NULL, NULL,  1, 0, ADCx}, /* D81/PF1  */
-    {GPIOF,   NULL, NULL,  2, 0, ADCx}, /* D82/PF2  */
-    {GPIOF,   NULL, NULL,  3, 0, ADCx}, /* D83/PF3  */
-    {GPIOF,   NULL, NULL,  4, 0, ADCx}, /* D84/PF4  */
-    {GPIOF,   NULL, NULL,  5, 0, ADCx}, /* D85/PF5  */
-    {GPIOF,   NULL, NULL,  6, 0, ADCx}, /* D86/PF6  */
-    {GPIOF,   NULL, NULL,  7, 0, ADCx}, /* D87/PF7  */
-    {GPIOF,   NULL, NULL,  8, 0, ADCx}, /* D88/PF8  */
-    {GPIOF,   NULL, NULL,  9, 0, ADCx}, /* D89/PF9  */
-    {GPIOF,   NULL, NULL, 10, 0, ADCx}, /* D90/PF10 */
-    {GPIOF,   NULL, NULL, 11, 0, ADCx}, /* D91/PF11 */
-    {GPIOF,   NULL, NULL, 12, 0, ADCx}, /* D92/PF12 */
-    {GPIOF,   NULL, NULL, 13, 0, ADCx}, /* D93/PF13 */
-    {GPIOF,   NULL, NULL, 14, 0, ADCx}, /* D94/PF14 */
-    {GPIOF,   NULL, NULL, 15, 0, ADCx}, /* D95/PF15 */
-
-    {GPIOG,   NULL, NULL,  0, 0, ADCx}, /* D96/PG0  */
-    {GPIOG,   NULL, NULL,  1, 0, ADCx}, /* D97/PG1  */
-    {GPIOG,   NULL, NULL,  2, 0, ADCx}, /* D98/PG2  */
-    {GPIOG,   NULL, NULL,  3, 0, ADCx}, /* D99/PG3  */
-    {GPIOG,   NULL, NULL,  4, 0, ADCx}, /* D100/PG4  */
-    {GPIOG,   NULL, NULL,  5, 0, ADCx}, /* D101/PG5  */
-    {GPIOG,   NULL, NULL,  6, 0, ADCx}, /* D102/PG6  */
-    {GPIOG,   NULL, NULL,  7, 0, ADCx}, /* D103/PG7  */
-    {GPIOG,   NULL, NULL,  8, 0, ADCx}, /* D104/PG8  */
-    {GPIOG,   NULL, NULL,  9, 0, ADCx}, /* D105/PG9  */
-    {GPIOG,   NULL, NULL, 10, 0, ADCx}, /* D106/PG10 */
-    {GPIOG,   NULL, NULL, 11, 0, ADCx}, /* D107/PG11 */
-    {GPIOG,   NULL, NULL, 12, 0, ADCx}, /* D108/PG12 */
-    {GPIOG,   NULL, NULL, 13, 0, ADCx}, /* D109/PG13 */
-    {GPIOG,   NULL, NULL, 14, 0, ADCx}, /* D110/PG14 */
-    {GPIOG,   NULL, NULL, 15, 0, ADCx}  /* D111/PG15 */
-
+    {&GPIOA, &timer5, &ADC1, 1,    0}, /* D00/PA0  */
+    {&GPIOA, &timer5, &ADC1, 2,    1}, /* D01/PA1  */
+    {&GPIOA, &timer5, &ADC1, 3,    2}, /* D02/PA2  */
+    {&GPIOA, &timer5, &ADC1, 4,    3}, /* D03/PA3  */
+    {&GPIOA,    NULL, &ADC1, 0,    4}, /* D04/PA4  */
+    {&GPIOA,    NULL, &ADC1, 0,    5}, /* D05/PA5  */
+    {&GPIOA,    NULL, &ADC1, 1,    6}, /* D06/PA6  */ // ala check TIMER3
+    {&GPIOA,    NULL, &ADC1, 0,    7}, /* D07/PA7  */
+    {&GPIOA,    NULL,  NULL, 0, ADCx}, /* D08/PA8  */ // remap out
+    {&GPIOA,    NULL,  NULL, 0, ADCx}, /* D09/PA9  */ // remap out
+    {&GPIOA,    NULL,  NULL, 0, ADCx}, /* D10/PA10 */ // remap out
+    {&GPIOA,    NULL,  NULL, 0, ADCx}, /* D11/PA11 */ // remap out
+    {&GPIOA,    NULL,  NULL, 0, ADCx}, /* D12/PA12 */
+    {&GPIOA,    NULL,  NULL, 0, ADCx}, /* D13/PA13 */
+    {&GPIOA,    NULL,  NULL, 0, ADCx}, /* D14/PA14 */
+    {&GPIOA, &timer2,  NULL, 1, ADCx}, /* D15/PA15 */ // remap in
+
+    {&GPIOB, &timer3, &ADC1, 3,    8}, /* D16/PB0  */
+    {&GPIOB, &timer3, &ADC1, 4,    9}, /* D17/PB1  */
+    {&GPIOB,    NULL,  NULL, 0, ADCx}, /* D18/PB2  */
+    {&GPIOB, &timer2,  NULL, 2, ADCx}, /* D19/PB3  */ // remap in
+    {&GPIOB, &timer3,  NULL, 1, ADCx}, /* D20/PB4  */ // remap in
+    {&GPIOB, &timer3,  NULL, 2, ADCx}, /* D21/PB5  */ // remap in
+    {&GPIOB,    NULL,  NULL, 0, ADCx}, /* D22/PB6  */ // remap out
+    {&GPIOB,    NULL,  NULL, 0, ADCx}, /* D23/PB7  */ // remap out
+    {&GPIOB,    NULL,  NULL, 0, ADCx}, /* D24/PB8  */ // remap out
+    {&GPIOB,    NULL,  NULL, 0, ADCx}, /* D25/PB9  */ // remap out
+    {&GPIOB,    NULL,  NULL, 0, ADCx}, /* D26/PB10 */
+    {&GPIOB,    NULL,  NULL, 0, ADCx}, /* D27/PB11 */
+    {&GPIOB,    NULL,  NULL, 0, ADCx}, /* D28/PB12 */
+    {&GPIOB,    NULL,  NULL, 0, ADCx}, /* D29/PB13 */
+    {&GPIOB,    NULL,  NULL, 0, ADCx}, /* D30/PB14 */
+    {&GPIOB,    NULL,  NULL, 0, ADCx}, /* D31/PB15 */
+
+    {&GPIOC,    NULL, &ADC1, 0,   10}, /* D32/PC0  */
+    {&GPIOC,    NULL, &ADC1, 0,   11}, /* D33/PC1  */
+    {&GPIOC,    NULL, &ADC1, 0,   12}, /* D34/PC2  */
+    {&GPIOC,    NULL, &ADC1, 0,   13}, /* D35/PC3  */
+    {&GPIOC,    NULL, &ADC1, 0,   14}, /* D36/PC4  */
+    {&GPIOC,    NULL, &ADC1, 0,   15}, /* D37/PC5  */
+    {&GPIOC, &timer8,  NULL, 1, ADCx}, /* D38/PC6  */
+    {&GPIOC, &timer8,  NULL, 2, ADCx}, /* D39/PC7  */
+    {&GPIOC, &timer8,  NULL, 3, ADCx}, /* D40/PC8  */
+    {&GPIOC, &timer8,  NULL, 4, ADCx}, /* D41/PC9  */
+    {&GPIOC,    NULL,  NULL, 0, ADCx}, /* D42/PC10 */
+    {&GPIOC,    NULL,  NULL, 0, ADCx}, /* D43/PC11 */
+    {&GPIOC,    NULL,  NULL, 0, ADCx}, /* D44/PC12 */
+    {&GPIOC,    NULL,  NULL, 0, ADCx}, /* D45/PC13 */
+    {&GPIOC,    NULL,  NULL, 0, ADCx}, /* D46/PC14 */
+    {&GPIOC,    NULL,  NULL, 0, ADCx}, /* D47/PC15 */
+
+    {&GPIOD,    NULL, NULL, 0, ADCx}, /* D48/PD0  */
+    {&GPIOD,    NULL, NULL, 0, ADCx}, /* D49/PD1  */
+    {&GPIOD,    NULL, NULL, 0, ADCx}, /* D50/PD2  */
+    {&GPIOD,    NULL, NULL, 0, ADCx}, /* D51/PD3  */
+    {&GPIOD,    NULL, NULL, 0, ADCx}, /* D52/PD4  */
+    {&GPIOD,    NULL, NULL, 0, ADCx}, /* D53/PD5  */
+    {&GPIOD,    NULL, NULL, 0, ADCx}, /* D54/PD6  */
+    {&GPIOD,    NULL, NULL, 0, ADCx}, /* D55/PD7  */
+    {&GPIOD,    NULL, NULL, 0, ADCx}, /* D56/PD8  */
+    {&GPIOD,    NULL, NULL, 0, ADCx}, /* D57/PD9  */
+    {&GPIOD,    NULL, NULL, 0, ADCx}, /* D58/PD10 */
+    {&GPIOD,    NULL, NULL, 0, ADCx}, /* D59/PD11 */
+    {&GPIOD, &timer4, NULL, 1, ADCx}, /* D60/PD12 */  // remap in
+    {&GPIOD, &timer4, NULL, 2, ADCx}, /* D61/PD13 */  // remap in
+    {&GPIOD, &timer4, NULL, 3, ADCx}, /* D62/PD14 */  // remap in
+    {&GPIOD, &timer4, NULL, 4, ADCx}, /* D63/PD15 */  // remap in
+
+    {&GPIOE,    NULL, NULL, 0, ADCx}, /* D64/PE0  */
+    {&GPIOE,    NULL, NULL, 0, ADCx}, /* D65/PE1  */
+    {&GPIOE,    NULL, NULL, 0, ADCx}, /* D66/PE2  */
+    {&GPIOE,    NULL, NULL, 0, ADCx}, /* D67/PE3  */
+    {&GPIOE,    NULL, NULL, 0, ADCx}, /* D68/PE4  */
+    {&GPIOE,    NULL, NULL, 0, ADCx}, /* D69/PE5  */
+    {&GPIOE,    NULL, NULL, 0, ADCx}, /* D70/PE6  */
+    {&GPIOE,    NULL, NULL, 0, ADCx}, /* D71/PE7  */
+    {&GPIOE,    NULL, NULL, 0, ADCx}, /* D72/PE8  */
+    {&GPIOE, &timer1, NULL, 1, ADCx}, /* D73/PE9  */  // remap in
+    {&GPIOE,    NULL, NULL, 0, ADCx}, /* D74/PE10 */
+    {&GPIOE, &timer1, NULL, 2, ADCx}, /* D75/PE11 */  // remap in
+    {&GPIOE,    NULL, NULL, 0, ADCx}, /* D76/PE12 */
+    {&GPIOE, &timer1, NULL, 3, ADCx}, /* D77/PE13 */  // remap in
+    {&GPIOE, &timer1, NULL, 4, ADCx}, /* D78/PE14 */  // remap in
+    {&GPIOE,    NULL, NULL, 0, ADCx},  /* D79/PE15 */
+#if 0 // not available on LQFP100 package
+    {&GPIOF,   NULL, NULL, 0, ADCx}, /* D80/PF0  */
+    {&GPIOF,   NULL, NULL, 0, ADCx}, /* D81/PF1  */
+    {&GPIOF,   NULL, NULL, 0, ADCx}, /* D82/PF2  */
+    {&GPIOF,   NULL, NULL, 0, ADCx}, /* D83/PF3  */
+    {&GPIOF,   NULL, NULL, 0, ADCx}, /* D84/PF4  */
+    {&GPIOF,   NULL, NULL, 0, ADCx}, /* D85/PF5  */
+    {&GPIOF,   NULL, NULL, 0, ADCx}, /* D86/PF6  */
+    {&GPIOF,   NULL, NULL, 0, ADCx}, /* D87/PF7  */
+    {&GPIOF,   NULL, NULL, 0, ADCx}, /* D88/PF8  */
+    {&GPIOF,   NULL, NULL, 0, ADCx}, /* D89/PF9  */
+    {&GPIOF,   NULL, NULL, 0, ADCx}, /* D90/PF10 */
+    {&GPIOF,   NULL, NULL, 0, ADCx}, /* D91/PF11 */
+    {&GPIOF,   NULL, NULL, 0, ADCx}, /* D92/PF12 */
+    {&GPIOF,   NULL, NULL, 0, ADCx}, /* D93/PF13 */
+    {&GPIOF,   NULL, NULL, 0, ADCx}, /* D94/PF14 */
+    {&GPIOF,   NULL, NULL, 0, ADCx}, /* D95/PF15 */
+
+    {&GPIOG,   NULL, NULL, 0, ADCx}, /* D96/PG0  */
+    {&GPIOG,   NULL, NULL, 0, ADCx}, /* D97/PG1  */
+    {&GPIOG,   NULL, NULL, 0, ADCx}, /* D98/PG2  */
+    {&GPIOG,   NULL, NULL, 0, ADCx}, /* D99/PG3  */
+    {&GPIOG,   NULL, NULL, 0, ADCx}, /* D100/PG4  */
+    {&GPIOG,   NULL, NULL, 0, ADCx}, /* D101/PG5  */
+    {&GPIOG,   NULL, NULL, 0, ADCx}, /* D102/PG6  */
+    {&GPIOG,   NULL, NULL, 0, ADCx}, /* D103/PG7  */
+    {&GPIOG,   NULL, NULL, 0, ADCx}, /* D104/PG8  */
+    {&GPIOG,   NULL, NULL, 0, ADCx}, /* D105/PG9  */
+    {&GPIOG,   NULL, NULL, 0, ADCx}, /* D106/PG10 */
+    {&GPIOG,   NULL, NULL, 0, ADCx}, /* D107/PG11 */
+    {&GPIOG,   NULL, NULL, 0, ADCx}, /* D108/PG12 */
+    {&GPIOG,   NULL, NULL, 0, ADCx}, /* D109/PG13 */
+    {&GPIOG,   NULL, NULL, 0, ADCx}, /* D110/PG14 */
+    {&GPIOG,   NULL, NULL, 0, ADCx}  /* D111/PG15 */
+#endif // not available on LQFP100 package
 };
 
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
diff --git a/STM32F4/variants/discovery_f407/discovery_f4.h b/STM32F4/variants/discovery_f407/discovery_f4.h
index 750175289..e3fa0466a 100644
--- a/STM32F4/variants/discovery_f407/discovery_f4.h
+++ b/STM32F4/variants/discovery_f407/discovery_f4.h
@@ -50,6 +50,9 @@
 #define BOARD_LED_PIN           Port2Pin('D', 12)
 #define BOARD_BUTTON_PIN        Port2Pin('A', 0)
 
+#define BOARD_USB_DM_PIN		PA11
+#define BOARD_USB_DP_PIN		PA12
+
 #define BOARD_NR_USARTS         5
 #define BOARD_USART1_TX_PIN     Port2Pin('A', 9)
 #define BOARD_USART1_RX_PIN     Port2Pin('A',10)

From 97329efca32eb20b01047c0afdfba6eea877b5da Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Sat, 13 May 2017 10:27:33 +0200
Subject: [PATCH 074/307] push the generic_f4 branch to master

---
 STM32F1/libraries/SPI/src/SPI.cpp             |   9 +-
 STM32F4/boards.txt                            |  61 +-
 STM32F4/cores/maple/Arduino.h                 |   6 -
 STM32F4/cores/maple/Client.h                  |   5 +-
 STM32F4/cores/maple/HardwareTimer.h           |   2 +-
 STM32F4/cores/maple/IPAddress.h               |   4 +-
 STM32F4/cores/maple/Server.h                  |   4 +-
 STM32F4/cores/maple/Stream.h                  |   4 +-
 STM32F4/cores/maple/Udp.h                     |   4 +-
 STM32F4/cores/maple/WProgram.h                |   7 +-
 STM32F4/cores/maple/WString.h                 |   7 +-
 STM32F4/cores/maple/bits.h                    |   5 +
 STM32F4/cores/maple/boards.cpp                |  32 +-
 STM32F4/cores/maple/boards.h                  |  39 +-
 STM32F4/cores/maple/ext_interrupts.cpp        |   8 +-
 STM32F4/cores/maple/ext_interrupts.h          |   9 +-
 STM32F4/cores/maple/io.h                      |  13 +-
 STM32F4/cores/maple/itoa.h                    |   4 +-
 STM32F4/cores/maple/libmaple/HardwareSPI.cpp  | 424 -------------
 STM32F4/cores/maple/libmaple/HardwareSPI.h    | 279 ---------
 .../cores/maple/libmaple/HardwareSerial.cpp   |  30 +-
 STM32F4/cores/maple/libmaple/HardwareSerial.h |   2 +-
 STM32F4/cores/maple/libmaple/adc.c            |  33 +-
 STM32F4/cores/maple/libmaple/adc.h            |  54 +-
 STM32F4/cores/maple/libmaple/dac.c            |   4 +-
 STM32F4/cores/maple/libmaple/dma.h            |   7 +-
 STM32F4/cores/maple/libmaple/dmaF1.c          | 383 ------------
 STM32F4/cores/maple/libmaple/dmaF1.h          | 453 --------------
 .../cores/maple/libmaple/{dmaF2.c => dmaF4.c} |  39 +-
 .../cores/maple/libmaple/{dmaF2.h => dmaF4.h} |  72 ++-
 STM32F4/cores/maple/libmaple/exti.h           |   4 -
 STM32F4/cores/maple/libmaple/fsmc.c           |  53 +-
 STM32F4/cores/maple/libmaple/gpio.h           | 102 +++-
 STM32F4/cores/maple/libmaple/gpioF1.c         | 200 ------
 STM32F4/cores/maple/libmaple/gpioF1.h         | 530 ----------------
 .../maple/libmaple/{gpioF2.c => gpioF4.c}     |  89 ++-
 .../maple/libmaple/{gpioF2.h => gpio_def.h}   |  90 +--
 STM32F4/cores/maple/libmaple/i2c.c            |  40 +-
 STM32F4/cores/maple/libmaple/i2c.h            |   2 +-
 STM32F4/cores/maple/libmaple/libmaple.h       |  14 +-
 STM32F4/cores/maple/libmaple/libmaple_types.h |  15 +-
 STM32F4/cores/maple/libmaple/rcc.h            |   7 +-
 STM32F4/cores/maple/libmaple/rccF1.c          | 233 -------
 STM32F4/cores/maple/libmaple/rccF1.h          | 572 ------------------
 .../cores/maple/libmaple/{rccF2.c => rccF4.c} |   7 +-
 .../cores/maple/libmaple/{rccF2.h => rccF4.h} |   0
 STM32F4/cores/maple/libmaple/rules.mk         |  22 -
 STM32F4/cores/maple/libmaple/spi.c            |  39 +-
 STM32F4/cores/maple/libmaple/spi.h            |  19 +-
 STM32F4/cores/maple/libmaple/spiF4.h          |  15 +-
 STM32F4/cores/maple/libmaple/spi_f4.c         |  26 +-
 STM32F4/cores/maple/libmaple/stm32.h          |  63 +-
 STM32F4/cores/maple/libmaple/timer.c          |  16 +-
 STM32F4/cores/maple/libmaple/timer.h          |  19 +-
 STM32F4/cores/maple/libmaple/usart.h          |   6 +-
 .../Class/audio/inc/usbd_audio_core.h         |   2 +-
 .../Class/cdc/inc/usbd_cdc_core.h             |   3 +-
 .../Class/cdc/src/usbd_cdc_core.c             |   7 +-
 .../Core/inc/usbd_core.h                      |   4 +-
 .../Core/inc/usbd_def.h                       |   2 +-
 .../Core/inc/usbd_req.h                       |   2 +-
 .../Core/src/usbd_core.c                      |  10 +-
 .../Core/src/usbd_ioreq.c                     |   2 +-
 .../Core/src/usbd_req.c                       |   6 +-
 .../usbF4/STM32_USB_OTG_Driver/inc/usb_core.h |   2 +-
 .../STM32_USB_OTG_Driver/inc/usb_defines.h    |   2 +-
 .../usbF4/STM32_USB_OTG_Driver/inc/usb_otg.h  |   1 +
 .../usbF4/STM32_USB_OTG_Driver/inc/usb_regs.h |   4 +-
 .../usbF4/STM32_USB_OTG_Driver/src/usb_core.c |   4 +-
 .../usbF4/STM32_USB_OTG_Driver/src/usb_dcd.c  |   4 +-
 .../STM32_USB_OTG_Driver/src/usb_dcd_int.c    |   4 +-
 .../cores/maple/libmaple/usbF4/VCP/core_cm4.h |   2 +-
 STM32F4/cores/maple/libmaple/usbF4/VCP/misc.c |   2 +-
 .../cores/maple/libmaple/usbF4/VCP/usb_bsp.c  |  22 +-
 .../cores/maple/libmaple/usbF4/VCP/usb_conf.h |   4 +
 .../maple/libmaple/usbF4/VCP/usbd_cdc_vcp.c   |   2 +-
 .../maple/libmaple/usbF4/VCP/usbd_cdc_vcp.h   |   2 +-
 .../maple/libmaple/usbF4/VCP/usbd_conf.h      |   1 +
 .../maple/libmaple/usbF4/VCP/usbd_desc.c      |   6 +-
 .../maple/libmaple/usbF4/VCP/usbd_desc.h      |   2 +-
 .../cores/maple/libmaple/usbF4/VCP/usbd_usr.c |   4 +-
 STM32F4/cores/maple/libmaple/usbF4/usb.c      |  33 +-
 STM32F4/cores/maple/libmaple/usbF4/usb.h      |   2 +-
 STM32F4/cores/maple/libmaple/util.c           |   6 +-
 STM32F4/cores/maple/libmaple/util.h           |   5 +-
 STM32F4/cores/maple/pwm.cpp                   |   4 +-
 STM32F4/cores/maple/usb_serial.cpp            |   6 +-
 STM32F4/cores/maple/usb_serial.h              |  15 +-
 STM32F4/cores/maple/wirish.h                  |  15 +-
 STM32F4/cores/maple/wirish_analog.cpp         |   2 -
 STM32F4/cores/maple/wirish_constants.h        |   4 +-
 STM32F4/cores/maple/wirish_debug.h            |   7 +-
 STM32F4/cores/maple/wirish_digital.cpp        |  31 +-
 STM32F4/cores/maple/wirish_math.h             |   4 +-
 STM32F4/cores/maple/wirish_time.cpp           |   6 +-
 STM32F4/cores/maple/wirish_time.h             |   5 +-
 STM32F4/cores/maple/wirish_types.h            |  27 +-
 STM32F4/libraries/SPI/library.properties      |   1 +
 STM32F4/libraries/SPI/src/SPI.cpp             | 518 ++++++++--------
 STM32F4/libraries/SPI/src/SPI.h               | 158 ++---
 STM32F4/platform.txt                          |  20 +-
 .../gpio.c => system/libmaple/Arduino.h}      |  30 +-
 .../variants/generic_f407v/generic_f407v.cpp  |  81 +++
 .../variants/generic_f407v/generic_f407v.h    | 163 +++++
 STM32F4/variants/generic_f407v/ld/common.inc  | 219 +++++++
 .../variants/generic_f407v/ld/extra_libs.inc  |   7 +
 STM32F4/variants/generic_f407v/ld/flash.ld    |  20 +
 STM32F4/variants/generic_f407v/ld/jtag.ld     |  20 +
 STM32F4/variants/generic_f407v/ld/names.inc   |  78 +++
 STM32F4/variants/generic_f407v/ld/ram.ld      |  19 +
 .../generic_f407v/ld/vector_symbols.inc       |  78 +++
 STM32F4/variants/generic_f407v/pin_map.c      | 210 +++++++
 STM32F4/variants/generic_f407v/pins_arduino.h |   6 +
 STM32F4/variants/generic_f407v/stm32_isrs.S   | 323 ++++++++++
 .../generic_f407v/stm32_vector_table.S        | 113 ++++
 STM32F4/variants/generic_f407v/variant.h      |  21 +
 .../generic_f407v/wirish/start.S}             |  40 +-
 .../variants/generic_f407v/wirish/start_c.c   |  95 +++
 118 files changed, 2577 insertions(+), 4107 deletions(-)
 delete mode 100644 STM32F4/cores/maple/Arduino.h
 delete mode 100644 STM32F4/cores/maple/libmaple/HardwareSPI.cpp
 delete mode 100644 STM32F4/cores/maple/libmaple/HardwareSPI.h
 delete mode 100644 STM32F4/cores/maple/libmaple/dmaF1.c
 delete mode 100644 STM32F4/cores/maple/libmaple/dmaF1.h
 rename STM32F4/cores/maple/libmaple/{dmaF2.c => dmaF4.c} (91%)
 rename STM32F4/cores/maple/libmaple/{dmaF2.h => dmaF4.h} (74%)
 delete mode 100644 STM32F4/cores/maple/libmaple/gpioF1.c
 delete mode 100644 STM32F4/cores/maple/libmaple/gpioF1.h
 rename STM32F4/cores/maple/libmaple/{gpioF2.c => gpioF4.c} (75%)
 rename STM32F4/cores/maple/libmaple/{gpioF2.h => gpio_def.h} (90%)
 delete mode 100644 STM32F4/cores/maple/libmaple/rccF1.c
 delete mode 100644 STM32F4/cores/maple/libmaple/rccF1.h
 rename STM32F4/cores/maple/libmaple/{rccF2.c => rccF4.c} (99%)
 rename STM32F4/cores/maple/libmaple/{rccF2.h => rccF4.h} (100%)
 rename STM32F4/{cores/maple/libmaple/gpio.c => system/libmaple/Arduino.h} (79%)
 create mode 100644 STM32F4/variants/generic_f407v/generic_f407v.cpp
 create mode 100644 STM32F4/variants/generic_f407v/generic_f407v.h
 create mode 100644 STM32F4/variants/generic_f407v/ld/common.inc
 create mode 100644 STM32F4/variants/generic_f407v/ld/extra_libs.inc
 create mode 100644 STM32F4/variants/generic_f407v/ld/flash.ld
 create mode 100644 STM32F4/variants/generic_f407v/ld/jtag.ld
 create mode 100644 STM32F4/variants/generic_f407v/ld/names.inc
 create mode 100644 STM32F4/variants/generic_f407v/ld/ram.ld
 create mode 100644 STM32F4/variants/generic_f407v/ld/vector_symbols.inc
 create mode 100644 STM32F4/variants/generic_f407v/pin_map.c
 create mode 100644 STM32F4/variants/generic_f407v/pins_arduino.h
 create mode 100644 STM32F4/variants/generic_f407v/stm32_isrs.S
 create mode 100644 STM32F4/variants/generic_f407v/stm32_vector_table.S
 create mode 100644 STM32F4/variants/generic_f407v/variant.h
 rename STM32F4/{cores/maple/libmaple/rcc.c => variants/generic_f407v/wirish/start.S} (54%)
 create mode 100644 STM32F4/variants/generic_f407v/wirish/start_c.c

diff --git a/STM32F1/libraries/SPI/src/SPI.cpp b/STM32F1/libraries/SPI/src/SPI.cpp
index 45ee25ab4..34c810234 100644
--- a/STM32F1/libraries/SPI/src/SPI.cpp
+++ b/STM32F1/libraries/SPI/src/SPI.cpp
@@ -391,11 +391,11 @@ uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length
 	spi_rx_dma_enable(_currentSetting->spi_d);
 	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
 	dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
-                     receiveBuf, dma_bit_size, (DMA_MINC_MODE | DMA_TRNS_CMPLT));// receive buffer DMA
+                     receiveBuf, dma_bit_size, (DMA_MINC_MODE));// receive buffer DMA
 	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, length);
 
 	// TX
-	uint32 flags = (DMA_MINC_MODE | DMA_FROM_MEM | DMA_TRNS_CMPLT);
+	uint32 flags = (DMA_MINC_MODE | DMA_FROM_MEM);
 	spi_tx_dma_enable(_currentSetting->spi_d);	
 	if ( transmitBuf==0 ) {
 		static uint8_t ff = 0XFF;
@@ -407,13 +407,13 @@ uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length
 	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
 
 	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);// enable receive
+	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
 	
     uint32_t m = millis();
 	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
 		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
     }
-	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
@@ -443,14 +443,13 @@ uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length, bool minc)
     dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
                        transmitBuf, dma_bit_size, flags);// Transmit buffer DMA 
 	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
+	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
 
-//    while (dma1_ch3_Active);
     uint32_t m = millis();
 	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
 		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
     }
-	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
diff --git a/STM32F4/boards.txt b/STM32F4/boards.txt
index 7577d1949..8fc143071 100644
--- a/STM32F4/boards.txt
+++ b/STM32F4/boards.txt
@@ -1,5 +1,7 @@
 # 
 
+menu.usb_cfg=USB configuration
+
 ##############################################################
 discovery_f407.name=STM32 Discovery F407
 
@@ -29,6 +31,49 @@ discovery_f407.build.error_led_port=GPIOD
 discovery_f407.build.error_led_pin=14
 discovery_f407.build.board=STM32DiscoveryF407
 
+discovery_f407.menu.usb_cfg.usb_nc=USB inactive
+discovery_f407.menu.usb_cfg.usb_nc.build.cpu_flags=-DUSB_NC
+discovery_f407.menu.usb_cfg.usb_serial=USB serial (CDC)
+discovery_f407.menu.usb_cfg.usb_serial.build.cpu_flags=-DSERIAL_USB
+discovery_f407.menu.usb_cfg.usb_msc=USB Mass Storage (MSC)
+discovery_f407.menu.usb_cfg.usb_msc.build.cpu_flags=-DUSB_MSC
+##############################################################
+generic_f407v.name=Generic STM32F407V series
+
+generic_f407v.upload.tool=stlink_upload
+generic_f407v.upload.protocol=stlink
+
+generic_f407v.upload.file_type=bin
+generic_f407v.upload.ram.maximum_size=131072
+generic_f407v.upload.flash.maximum_size=514288
+generic_f407v.upload.maximum_size=514288
+
+#generic_f407v.upload.usbID=0483:3748
+#generic_f407v.upload.altID=1
+#generic_f407v.upload.auto_reset=true
+
+generic_f407v.build.mcu=cortex-m4
+generic_f407v.build.f_cpu=168000000L
+generic_f407v.build.core=maple
+generic_f407v.build.extra_flags=-mthumb -DSTM32_HIGH_DENSITY -DSTM32F4 -DBOARD_generic_f407v
+generic_f407v.build.ldscript=ld/jtag.ld
+generic_f407v.build.variant=generic_f407v
+generic_f407v.build.variant_system_lib=lib_f407.a
+generic_f407v.build.vect=VECT_TAB_BASE
+generic_f407v.build.density=STM32_HIGH_DENSITY
+generic_f407v.build.error_led_port=GPIOA
+generic_f407v.build.error_led_pin=7
+generic_f407v.build.board=STM32GenericF407VET6
+
+generic_f407v.menu.usb_cfg.usb_nc=USB inactive
+generic_f407v.menu.usb_cfg.usb_nc.build.cpu_flags=-DUSB_NC
+
+generic_f407v.menu.usb_cfg.usb_serial=USB serial (CDC)
+generic_f407v.menu.usb_cfg.usb_serial.build.cpu_flags=-DSERIAL_USB
+
+generic_f407v.menu.usb_cfg.usb_msc=USB Mass Storage (MSC)
+generic_f407v.menu.usb_cfg.usb_msc.build.cpu_flags=-DUSB_MSC
+
 ##############################################################
 stm32f4stamp.name=STM32F4Stamp F405
 
@@ -49,7 +94,7 @@ stm32f4stamp.upload.dfuse_addr=0x8000000
 stm32f4stamp.build.mcu=cortex-m4
 stm32f4stamp.build.f_cpu=168000000L
 stm32f4stamp.build.core=maple
-stm32f4stamp.build.extra_flags=-DMCU_STM32F406VG -mthumb -DSTM32_HIGH_DENSITY -DSTM32F2 -DSTM32F4 -DBOARD_discovery_f4
+stm32f4stamp.build.extra_flags=-DMCU_STM32F406VG -mthumb -DSTM32_HIGH_DENSITY -DSTM32F4 -DBOARD_discovery_f4
 stm32f4stamp.build.ldscript=ld/jtag.ld
 stm32f4stamp.build.variant=discovery_f407
 stm32f4stamp.build.variant_system_lib=lib_f407.a
@@ -59,6 +104,12 @@ stm32f4stamp.build.error_led_port=GPIOD
 stm32f4stamp.build.error_led_pin=14
 stm32f4stamp.build.board=STM32F4StampF405
 
+stm32f4stamp.menu.usb_cfg.usb_nc=USB inactive
+stm32f4stamp.menu.usb_cfg.usb_nc.build.cpu_flags=-DUSB_NC
+stm32f4stamp.menu.usb_cfg.usb_serial=USB serial (CDC)
+stm32f4stamp.menu.usb_cfg.usb_serial.build.cpu_flags=-DSERIAL_USB
+stm32f4stamp.menu.usb_cfg.usb_msc=USB Mass Storage (MSC)
+stm32f4stamp.menu.usb_cfg.usb_msc.build.cpu_flags=-DUSB_MSC
 ##############################################################
 netduino2plus.name=Netduino2 F405
 
@@ -79,7 +130,7 @@ netduino2plus.upload.dfuse_addr=0x8000000
 netduino2plus.build.mcu=cortex-m4
 netduino2plus.build.f_cpu=168000000L
 netduino2plus.build.core=maple
-netduino2plus.build.extra_flags=-DMCU_STM32F406VG -mthumb -DSTM32_HIGH_DENSITY -DSTM32F2 -DSTM32F4 -DBOARD_discovery_f4 -DARDUINO_STM32F4_NETDUINO2PLUS
+netduino2plus.build.extra_flags=-DMCU_STM32F406VG -mthumb -DSTM32_HIGH_DENSITY -DSTM32F4 -DBOARD_discovery_f4 -DARDUINO_STM32F4_NETDUINO2PLUS
 netduino2plus.build.ldscript=ld/jtag.ld
 netduino2plus.build.variant=discovery_f407
 netduino2plus.build.variant_system_lib=lib_f407.a
@@ -89,5 +140,11 @@ netduino2plus.build.error_led_port=GPIOD
 netduino2plus.build.error_led_pin=14
 netduino2plus.build.board=Netduino2F405
 
+netduino2plus.menu.usb_cfg.usb_nc=USB inactive
+netduino2plus.menu.usb_cfg.usb_nc.build.cpu_flags=-DUSB_NC
+netduino2plus.menu.usb_cfg.usb_serial=USB serial (CDC)
+netduino2plus.menu.usb_cfg.usb_serial.build.cpu_flags=-DSERIAL_USB
+netduino2plus.menu.usb_cfg.usb_msc=USB Mass Storage (MSC)
+netduino2plus.menu.usb_cfg.usb_msc.build.cpu_flags=-DUSB_MSC
 ##############################################################
 
diff --git a/STM32F4/cores/maple/Arduino.h b/STM32F4/cores/maple/Arduino.h
deleted file mode 100644
index d02a50cba..000000000
--- a/STM32F4/cores/maple/Arduino.h
+++ /dev/null
@@ -1,6 +0,0 @@
-#ifndef Arduino_h
-#define Arduino_h
-#include "WProgram.h"
-#endif
-
-#include "variant.h"
diff --git a/STM32F4/cores/maple/Client.h b/STM32F4/cores/maple/Client.h
index b8e5d935f..57bedb8e0 100644
--- a/STM32F4/cores/maple/Client.h
+++ b/STM32F4/cores/maple/Client.h
@@ -17,8 +17,9 @@
   Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 
-#ifndef client_h
-#define client_h
+#ifndef _CLIENT_H_
+#define _CLIENT_H_
+
 #include "Print.h"
 #include "Stream.h"
 #include "IPAddress.h"
diff --git a/STM32F4/cores/maple/HardwareTimer.h b/STM32F4/cores/maple/HardwareTimer.h
index 89e356499..c90356bf6 100644
--- a/STM32F4/cores/maple/HardwareTimer.h
+++ b/STM32F4/cores/maple/HardwareTimer.h
@@ -33,7 +33,7 @@
 
 // TODO [0.1.0] Remove deprecated pieces, pick a better API
 
-#include "timer.h"
+#include <libmaple/timer.h>
 
 /** Timer mode. */
 typedef timer_mode TimerMode;
diff --git a/STM32F4/cores/maple/IPAddress.h b/STM32F4/cores/maple/IPAddress.h
index 271b24025..c6e06972a 100644
--- a/STM32F4/cores/maple/IPAddress.h
+++ b/STM32F4/cores/maple/IPAddress.h
@@ -17,8 +17,8 @@
   Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 
-#ifndef IPAddress_h
-#define IPAddress_h
+#ifndef _IPAddress_h_
+#define _IPAddress_h_
 
 #include <stdint.h>
 #include <WString.h>
diff --git a/STM32F4/cores/maple/Server.h b/STM32F4/cores/maple/Server.h
index 69e3e39fe..4a95c9f51 100644
--- a/STM32F4/cores/maple/Server.h
+++ b/STM32F4/cores/maple/Server.h
@@ -17,8 +17,8 @@
   Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 
-#ifndef server_h
-#define server_h
+#ifndef _SERVER_H_
+#define _SERVER_H_
 
 #include "Print.h"
 
diff --git a/STM32F4/cores/maple/Stream.h b/STM32F4/cores/maple/Stream.h
index abdcd1768..870fbf0e5 100644
--- a/STM32F4/cores/maple/Stream.h
+++ b/STM32F4/cores/maple/Stream.h
@@ -19,8 +19,8 @@
   parsing functions based on TextFinder library by Michael Margolis
 */
 
-#ifndef Stream_h
-#define Stream_h
+#ifndef _STREAM_H_
+#define _STREAM_H_
 
 #include <inttypes.h>
 #include "Print.h"
diff --git a/STM32F4/cores/maple/Udp.h b/STM32F4/cores/maple/Udp.h
index dc5644b9d..1652cafc9 100644
--- a/STM32F4/cores/maple/Udp.h
+++ b/STM32F4/cores/maple/Udp.h
@@ -32,8 +32,8 @@
  * bjoern@cs.stanford.edu 12/30/2008
  */
 
-#ifndef udp_h
-#define udp_h
+#ifndef _UDP_H_
+#define _UDP_H_
 
 #include <Stream.h>
 #include <IPAddress.h>
diff --git a/STM32F4/cores/maple/WProgram.h b/STM32F4/cores/maple/WProgram.h
index 2949a0a59..82b759a64 100644
--- a/STM32F4/cores/maple/WProgram.h
+++ b/STM32F4/cores/maple/WProgram.h
@@ -24,7 +24,12 @@
  * SOFTWARE.
  *****************************************************************************/
 
-#include "wirish.h"
+#ifndef _WPROGRAM_H_
+#define _WPROGRAM_H_
+
+#include <wirish.h>
 
 void setup();
 void loop();
+
+#endif
\ No newline at end of file
diff --git a/STM32F4/cores/maple/WString.h b/STM32F4/cores/maple/WString.h
index 903857809..ec0eae7fb 100644
--- a/STM32F4/cores/maple/WString.h
+++ b/STM32F4/cores/maple/WString.h
@@ -19,8 +19,9 @@
   Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 
-#ifndef String_class_h
-#define String_class_h
+#ifndef _WSTRING_H_
+#define _WSTRING_H_
+
 #ifdef __cplusplus
 
 #include <stdlib.h>
@@ -225,4 +226,4 @@ class StringSumHelper : public String
 };
 
 #endif  // __cplusplus
-#endif  // String_class_h
+#endif  // _WSTRING_H_
diff --git a/STM32F4/cores/maple/bits.h b/STM32F4/cores/maple/bits.h
index 3e755b7f4..3e3eff1ec 100644
--- a/STM32F4/cores/maple/bits.h
+++ b/STM32F4/cores/maple/bits.h
@@ -27,4 +27,9 @@
 /* Note: Use of this header file is deprecated.  Use bit_constants.h
    instead. */
 
+#ifndef _BITS_H_
+#define _BITS_H_
+
 #include "bit_constants.h"
+
+#endif
diff --git a/STM32F4/cores/maple/boards.cpp b/STM32F4/cores/maple/boards.cpp
index a85657163..0d55e9414 100644
--- a/STM32F4/cores/maple/boards.cpp
+++ b/STM32F4/cores/maple/boards.cpp
@@ -33,17 +33,16 @@
  */
 #include "boards.h"
 
-#include "flash.h"
-#include "rcc.h"
-#include "nvic.h"
-#include "systick.h"
-#include "gpio.h"
-#include "adc.h"
-#include "timer.h"
+#include <libmaple/flash.h>
+#include <libmaple/rcc.h>
+#include <libmaple/nvic.h>
+#include <libmaple/systick.h>
+#include <libmaple/gpio.h>
+#include <libmaple/adc.h>
+#include <libmaple/timer.h>
 #include "usb.h"
-#ifdef STM32F2
-//#include "usbF4.h"
-#endif
+#include "usb_serial.h"
+
 
 static void setupFlash(void);
 static void setupClocks(void);
@@ -59,7 +58,7 @@ void init(void) {
 	systick_init(SYSTICK_RELOAD_VAL);
 	gpio_init_all();
 
-#ifdef STM32F2
+#ifdef STM32F4
 	rcc_clk_enable(RCC_SYSCFG);
 #else
     afio_init();
@@ -69,7 +68,10 @@ void init(void) {
     setupADC();
     setupTimers();
 
-    //setupUSB();
+#ifdef SERIAL_USB
+    setupUSB();
+    SerialUSB.begin();
+#endif
 }
 
 /* You could farm this out to the files in boards/ if e.g. it takes
@@ -84,11 +86,13 @@ bool boardUsesPin(uint8 pin) {
 }
 
 static void setupFlash(void) {
+/*
 #ifndef STM32F2
 	// for F2 and F4 CPUs this is done in SetupClock...(), e.g. in SetupClock168MHz()
     flash_enable_prefetch();
     flash_set_latency(FLASH_WAIT_STATE_2);
 #endif
+*/
 }
 
 /*
@@ -121,8 +125,8 @@ static void setupNVIC() {
 static void adcDefaultConfig(const adc_dev* dev);
 
 static void setupADC() {
-#ifdef STM32F2
-	setupADC_F2();
+#ifdef STM32F4
+	setupADC_F4();
 #else
 	rcc_set_prescaler(RCC_PRESCALER_ADC, RCC_ADCPRE_PCLK_DIV_6);
 #endif
diff --git a/STM32F4/cores/maple/boards.h b/STM32F4/cores/maple/boards.h
index 00d07cddb..d37bff4a5 100644
--- a/STM32F4/cores/maple/boards.h
+++ b/STM32F4/cores/maple/boards.h
@@ -39,11 +39,8 @@
 #ifndef _BOARDS_H_
 #define _BOARDS_H_
 
-#include "libmaple.h"
-#include "gpio.h"
-#include "timer.h"
-
-#include "wirish_types.h"
+#include <wirish_types.h>
+#include <stdbool.h>
 
 /* Set of all possible pin names; not all boards have all these (note
  * that we use the Dx convention since all of the Maple's pins are
@@ -55,9 +52,12 @@ enum {
     D32, D33, D34, D35, D36, D37, D38, D39, D40, D41, D42, D43, D44, D45, D46,
     D47, D48, D49, D50, D51, D52, D53, D54, D55, D56, D57, D58, D59, D60, D61,
     D62, D63, D64, D65, D66, D67, D68, D69, D70, D71, D72, D73, D74, D75, D76,
+#if 0 // not available on LQFP100 package
     D77, D78, D79, D80, D81, D82, D83, D84, D85, D86, D87, D88, D89, D90, D91,
     D92, D93, D94, D95, D96, D97, D98, D99, D100, D101, D102, D103, D104, D105,
-    D106, D107, D108, D109, D110, D111, };
+    D106, D107, D108, D109, D110, D111,
+#endif // not available on LQFP100 package
+};
 
 /**
  * @brief Maps each Maple pin to a corresponding stm32_pin_info.
@@ -115,31 +115,20 @@ extern void boardInit(void);
  * @return true if the given pin is in boardUsedPins, and false otherwise.
  * @see boardUsedPins
  */
-bool boardUsesPin(uint8 pin);
+extern bool boardUsesPin(uint8 pin);
 
 /* Include the appropriate private header from boards/: */
 
 /* FIXME HACK put boards/ before these paths once IDE uses make. */
 
-#ifdef BOARD_maple
-#include "maple.h"
-#elif defined(BOARD_maple_native)
-#include "maple_native.h"
-#elif defined(BOARD_maple_mini)
-#include "maple_mini.h"
-#elif defined(BOARD_maple_RET6)
-/*
- * **NOT** MAPLE REV6.  This the **Maple RET6 EDITION**, which is a
- * Maple with an STM32F103RET6 (...RET6) instead of an STM32F103RBT6
- * (...RBT6) on it.  Maple Rev6 (as of March 2011) DOES NOT EXIST.
- */
-#include "maple_RET6.h"
-#elif defined(BOARD_aeroquad32) || defined(BOARD_aeroquad32f1)
+#if defined(BOARD_aeroquad32) || defined(BOARD_aeroquad32f1)
 #include "aeroquad32.h"
 #elif defined(BOARD_aeroquad32mini)
 #include "aeroquad32mini.h"
 #elif defined(BOARD_discovery_f4)
 #include "discovery_f4.h"
+#elif defined(BOARD_generic_f407v)
+#include "generic_f407v.h"
 #elif defined(BOARD_freeflight)
 #include "freeflight.h"
 #else
@@ -160,4 +149,12 @@ bool boardUsesPin(uint8 pin);
 #define CLOCK_SPEED_MHZ                 CYCLES_PER_MICROSECOND
 #define CLOCK_SPEED_HZ                  (CLOCK_SPEED_MHZ * 1000000UL)
 
+#ifndef SYSTICK_RELOAD_VAL
+#define SYSTICK_RELOAD_VAL              (1000 * CYCLES_PER_MICROSECOND - 1)
+#endif
+
+#ifndef BOARD_BUTTON_PRESSED_LEVEL
+#define BOARD_BUTTON_PRESSED_LEVEL      HIGH
+#endif
+
 #endif
diff --git a/STM32F4/cores/maple/ext_interrupts.cpp b/STM32F4/cores/maple/ext_interrupts.cpp
index f014f1300..7111d0c86 100644
--- a/STM32F4/cores/maple/ext_interrupts.cpp
+++ b/STM32F4/cores/maple/ext_interrupts.cpp
@@ -31,8 +31,8 @@
  */
 
 #include "boards.h"
-#include "gpio.h"
-#include "exti.h"
+#include <libmaple/gpio.h>
+#include <libmaple/exti.h>
 #include "ext_interrupts.h"
 
 static inline exti_trigger_mode exti_out_mode(ExtIntTriggerMode mode);
@@ -51,7 +51,7 @@ void attachInterrupt(uint8 pin, voidFuncPtr handler, ExtIntTriggerMode mode) {
 
     exti_trigger_mode outMode = exti_out_mode(mode);
 
-    exti_attach_interrupt((afio_exti_num)(PIN_MAP[pin].gpio_bit),
+    exti_attach_interrupt((afio_exti_num)(pin&0x0F),
                           gpio_exti_port(PIN_MAP[pin].gpio_device),
                           handler,
                           outMode);
@@ -66,7 +66,7 @@ void detachInterrupt(uint8 pin) {
         return;
     }
 
-    exti_detach_interrupt((afio_exti_num)(PIN_MAP[pin].gpio_bit));
+    exti_detach_interrupt((afio_exti_num)(pin&0x0F));
 }
 
 static inline exti_trigger_mode exti_out_mode(ExtIntTriggerMode mode) {
diff --git a/STM32F4/cores/maple/ext_interrupts.h b/STM32F4/cores/maple/ext_interrupts.h
index b5c6f983b..fe215dceb 100644
--- a/STM32F4/cores/maple/ext_interrupts.h
+++ b/STM32F4/cores/maple/ext_interrupts.h
@@ -24,8 +24,8 @@
  * SOFTWARE.
  *****************************************************************************/
 
-#include "libmaple_types.h"
-#include "nvic.h"
+#ifndef _EXT_INTERRUPTS_H_
+#define _EXT_INTERRUPTS_H_
 
 /**
  *  @file ext_interrupts.h
@@ -33,8 +33,9 @@
  *  @brief Wiring-like external interrupt prototypes and types.
  */
 
-#ifndef _EXT_INTERRUPTS_H_
-#define _EXT_INTERRUPTS_H_
+#include <libmaple/libmaple_types.h>
+#include <libmaple/nvic.h>
+
 
 /**
  * The kind of transition on an external pin which should trigger an
diff --git a/STM32F4/cores/maple/io.h b/STM32F4/cores/maple/io.h
index df1ab969e..aeaf0fd3a 100644
--- a/STM32F4/cores/maple/io.h
+++ b/STM32F4/cores/maple/io.h
@@ -33,8 +33,9 @@
 #ifndef _IO_H_
 #define _IO_H_
 
-#include "gpio.h"
-#include "adc.h"
+#include <inttypes.h>
+#include <libmaple/gpio.h>
+#include <libmaple/adc.h>
 
 #include "wirish_time.h"
 
@@ -179,9 +180,11 @@ static inline void toggleLED() {
  * accomplished portably over all LeafLabs boards by calling
  * pinMode(BOARD_BUTTON_PIN, INPUT).
  *
+ * @param button - one of available on-board buttons (up to 3 for generic F4)
+ *
  * @see pinMode()
  */
-uint8 isButtonPressed();
+uint8 isButtonPressed(uint8_t button);
 
 /**
  * Wait until the button is pressed and released, timing out if no
@@ -195,12 +198,14 @@ uint8 isButtonPressed();
  * button is pressed.  If timeout_millis is left out (or 0), wait
  * forever.
  *
+ * @param button - one of available on-board buttons (up to 3 for generic F4)
+ *
  * @return true, if the button was pressed; false, if the timeout was
  * reached.
  *
  * @see pinMode()
  */
-uint8 waitForButtonPress(uint32 timeout_millis=0);
+uint8 waitForButtonPress(uint8_t button, uint32 timeout_millis=0);
 
 /**
  * Shift out a byte of data, one bit at a time.
diff --git a/STM32F4/cores/maple/itoa.h b/STM32F4/cores/maple/itoa.h
index 59af10947..09e8b2f8e 100644
--- a/STM32F4/cores/maple/itoa.h
+++ b/STM32F4/cores/maple/itoa.h
@@ -16,8 +16,8 @@
   Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
 */
 
-#ifndef _ITOA_
-#define _ITOA_
+#ifndef _ITOA_H_
+#define _ITOA_H_
 
 #ifdef __cplusplus
 extern "C"{
diff --git a/STM32F4/cores/maple/libmaple/HardwareSPI.cpp b/STM32F4/cores/maple/libmaple/HardwareSPI.cpp
deleted file mode 100644
index a5b4711be..000000000
--- a/STM32F4/cores/maple/libmaple/HardwareSPI.cpp
+++ /dev/null
@@ -1,424 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @author Marti Bolivar <mbolivar@leaflabs.com>
- * @brief Wirish SPI implementation.
- */
-
-#include "HardwareSPI.h"
-
-#include "timer.h"
-#include "util.h"
-#include "rcc.h"
-
-#include "wirish.h"
-#include "boards.h"
-
-struct spi_pins {
-    uint8 nss;
-    uint8 sck;
-    uint8 miso;
-    uint8 mosi;
-};
-
-static const spi_pins* dev_to_spi_pins(spi_dev *dev);
-
-static void enable_device(spi_dev *dev,
-                          bool as_master,
-                          SPIFrequency frequency,
-                          spi_cfg_flag endianness,
-                          spi_mode mode);
-
-static const spi_pins board_spi_pins[] __FLASH__ = {
-    {BOARD_SPI1_NSS_PIN,
-     BOARD_SPI1_SCK_PIN,
-     BOARD_SPI1_MISO_PIN,
-     BOARD_SPI1_MOSI_PIN},
-#ifdef BOARD_SPI2_NSS_PIN
-	{BOARD_SPI2_NSS_PIN,
-     BOARD_SPI2_SCK_PIN,
-     BOARD_SPI2_MISO_PIN,
-     BOARD_SPI2_MOSI_PIN},
-#endif
-#ifdef STM32_HIGH_DENSITY
-    {BOARD_SPI3B_NSS_PIN,
-     BOARD_SPI3B_SCK_PIN,
-     BOARD_SPI3B_MISO_PIN,
-     BOARD_SPI3B_MOSI_PIN},
-#endif
-#ifdef STM32F4
-    {BOARD_SPI3B_NSS_PIN,
-     BOARD_SPI3B_SCK_PIN,
-     BOARD_SPI3B_MISO_PIN,
-     BOARD_SPI3B_MOSI_PIN},
-#endif
-};
-
-
-/*
- * Constructor
- */
-
-HardwareSPI::HardwareSPI(uint32 spi_num) {
-    switch (spi_num) {
-    case 1:
-        this->spi_d = SPI1;
-        break;
-    case 2:
-        this->spi_d = SPI2;
-        break;
-#ifdef STM32_HIGH_DENSITY
-    case 3:
-        this->spi_d = SPI3;
-        break;
-#endif
-#ifdef STM32F4
-//    case 4:
-//        this->spi_d = SPI4;
-//        break;
-#endif
-    default:
-        ASSERT(0);
-    }
-}
-
-/*
- * Set up/tear down
- */
-
-void HardwareSPI::begin(SPIFrequency frequency, uint32 bitOrder, uint32 mode) {
-    if (mode >= 4) {
-        ASSERT(0);
-        return;
-    }
-    spi_cfg_flag end = bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB;
-    spi_mode m = (spi_mode)mode;
-    enable_device(this->spi_d, true, frequency, end, m);
-}
-
-void HardwareSPI::begin(void) {
-    this->begin(SPI_1_125MHZ, MSBFIRST, 0);
-}
-
-void HardwareSPI::beginSlave(uint32 bitOrder, uint32 mode) {
-    if (mode >= 4) {
-        ASSERT(0);
-        return;
-    }
-    spi_cfg_flag end = bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB;
-    spi_mode m = (spi_mode)mode;
-    enable_device(this->spi_d, false, (SPIFrequency)0, end, m);
-}
-
-void HardwareSPI::beginSlave(void) {
-    this->beginSlave(MSBFIRST, 0);
-}
-
-
-/*
-void HardwareSPI::beginTransaction(uint8_t pin, SPISettings settings)
-{
-//    this->begin(settings.clock, settings.bitOrder, settings.dataMode);
-    this->begin(SPI_1_125MHZ, settings.bitOrder, settings.dataMode);
-}
-*/
-
-void HardwareSPI::end(void) {
-    if (!spi_is_enabled(this->spi_d)) {
-        return;
-    }
-
-    // Follows RM0008's sequence for disabling a SPI in master/slave
-    // full duplex mode.
-    while (spi_is_rx_nonempty(this->spi_d)) {
-        // FIXME [0.1.0] remove this once you have an interrupt based driver
-        volatile uint16 rx __attribute__((unused)) = spi_rx_reg(this->spi_d);
-    }
-    while (!spi_is_tx_empty(this->spi_d))
-        ;
-    while (spi_is_busy(this->spi_d))
-        ;
-    spi_peripheral_disable(this->spi_d);
-}
-
-/*
- * I/O
- */
-
-uint8 HardwareSPI::read(void) {
-    uint8 buf[1];
-    this->read(buf, 1);
-    return buf[0];
-}
-
-void HardwareSPI::read(uint8 *buf, uint32 len) {
-    uint32 rxed = 0;
-    while (rxed < len) {
-        while (!spi_is_rx_nonempty(this->spi_d))
-            ;
-        buf[rxed++] = (uint8)spi_rx_reg(this->spi_d);
-    }
-}
-
-#if 0
-void HardwareSPI::readMaster(uint8 *buf, uint32 len) {
-    uint32 rxed = 0;
-    while (rxed < len) {
-		spi_tx_reg(this->spi_d, 0xff);
-        while (!spi_is_rx_nonempty(this->spi_d))
-            ;
-        buf[rxed++] = (uint8)spi_rx_reg(this->spi_d);
-		buf[rxed++] = this->spi_d->regs->DR;
-    }
-}
-#endif
-void HardwareSPI::readMaster(uint8 *buf, uint32 len) {
-	spi_reg_map *r = this->spi_d->regs;
-    uint32 rxed = 0;
-    while (rxed < len) {
-		r->DR = 0xff;
-        while (!(r->SR & SPI_SR_RXNE))
-            ;
-		buf[rxed++] = r->DR;
-    }
-}
-
-
-void HardwareSPI::waitReady() {
-	while (!spi_is_rx_nonempty(this->spi_d))
-		;
-}
-
-void HardwareSPI::write(uint8 byte) {
-    this->write(&byte, 1);
-}
-
-void HardwareSPI::write(const uint8 *data, uint32 length) {
-    uint32 txed = 0;
-    while (txed < length) {
-        txed += spi_tx(this->spi_d, data + txed, length - txed);
-    }
-}
-
-uint8 HardwareSPI::transfer(uint8 byte) {
-    this->write(byte);
-    return this->read();
-}
-
-/*
- * Pin accessors
- */
-
-uint8 HardwareSPI::misoPin(void) {
-    return dev_to_spi_pins(this->spi_d)->miso;
-}
-
-uint8 HardwareSPI::mosiPin(void) {
-    return dev_to_spi_pins(this->spi_d)->mosi;
-}
-
-uint8 HardwareSPI::sckPin(void) {
-    return dev_to_spi_pins(this->spi_d)->sck;
-}
-
-uint8 HardwareSPI::nssPin(void) {
-    return dev_to_spi_pins(this->spi_d)->nss;
-}
-
-/*
- * Deprecated functions
- */
-
-uint8 HardwareSPI::send(uint8 data) {
-    uint8 buf[] = {data};
-    return this->send(buf, 1);
-}
-
-#if 1	
-uint8 HardwareSPI::send(const uint8 *buf, uint32 len) {
-    uint32 txed = 0;
-    uint8 ret = 0;
-    while (txed < len) {
-        this->write(buf[txed++]);
-        ret = this->read();
-    }
-    return ret;
-}
-#else
-// this does not work for an unknown reason
-uint8 HardwareSPI::send(const uint8 *buf, uint32 len) {
-	volatile uint32 *dr = &(this->spi_d->regs->DR);
-	volatile uint32 *sr = &(this->spi_d->regs->SR);
-    uint32 txed = 0;
-	uint32 rx=0;
-    while (txed < len) {
-        //while (!(*sr & SPI_SR_TXE))
-        //    ;
-		//*dr = buf[txed++];
-		this->write(buf[txed++]);
-
-        while (!(*sr & SPI_SR_RXNE))
-			;
-		rx = *dr;
-		//rx = this->read();
-    }
-
-	return rx;
-}
-#endif
-
-uint8 HardwareSPI::recv(void) {
-    return this->read();
-}
-
-/*
- * Auxiliary functions
- */
-
-static void configure_gpios(spi_dev *dev, bool as_master);
-static spi_baud_rate determine_baud_rate(spi_dev *dev, SPIFrequency freq);
-
-static const spi_pins* dev_to_spi_pins(spi_dev *dev) {
-    switch (dev->clk_id) {
-    case RCC_SPI1: return board_spi_pins;
-    case RCC_SPI2: return board_spi_pins + 1;
-#ifdef STM32_HIGH_DENSITY
-    case RCC_SPI3: return board_spi_pins + 2;
-#endif
-#ifdef STM32F4
-    case RCC_SPI4: return board_spi_pins + 3;
-#endif
-    default:       return NULL;
-    }
-}
-
-/* Enables the device in master or slave full duplex mode.  If you
- * change this code, you must ensure that appropriate changes are made
- * to HardwareSPI::end(). */
-static void enable_device(spi_dev *dev,
-                          bool as_master,
-                          SPIFrequency freq,
-                          spi_cfg_flag endianness,
-                          spi_mode mode) {
-    spi_baud_rate baud = determine_baud_rate(dev, freq);
-    uint32 cfg_flags = (endianness | SPI_DFF_8_BIT | SPI_SW_SLAVE |
-                        (as_master ? SPI_SOFT_SS : 0));
-
-    spi_init(dev);
-    configure_gpios(dev, as_master);
-    if (as_master) {
-        spi_master_enable(dev, baud, mode, cfg_flags);
-    } else {
-        spi_slave_enable(dev, mode, cfg_flags);
-    }
-}
-
-static void disable_pwm(const stm32_pin_info *i) {
-    if (i->timer_device) {
-        timer_set_mode(i->timer_device, i->timer_channel, TIMER_DISABLED);
-    }
-}
-
-static void configure_gpios(spi_dev *dev, bool as_master) {
-    const spi_pins *pins = dev_to_spi_pins(dev);
-
-    if (!pins) {
-        return;
-    }
-
-	const stm32_pin_info *nssi = (pins->nss >= 0) ? &PIN_MAP[pins->nss] : NULL;
-    const stm32_pin_info *scki = &PIN_MAP[pins->sck];
-    const stm32_pin_info *misoi = &PIN_MAP[pins->miso];
-    const stm32_pin_info *mosii = &PIN_MAP[pins->mosi];
-
-	if(nssi) {
-		disable_pwm(nssi);
-	}
-    disable_pwm(scki);
-    disable_pwm(misoi);
-    disable_pwm(mosii);
-
-#ifdef STM32F4
-	if(dev->clk_id <= RCC_SPI2) {
-		if(nssi) {
-			if(!as_master) {
-				gpio_set_af_mode(nssi->gpio_device,  scki->gpio_bit, 5);
-			}
-		}
-		gpio_set_af_mode(scki->gpio_device,  scki->gpio_bit, 5);
-		gpio_set_af_mode(misoi->gpio_device, misoi->gpio_bit, 5);
-		gpio_set_af_mode(mosii->gpio_device, mosii->gpio_bit, 5);
-	} else {
-		if(nssi) {
-			if(!as_master) {
-				gpio_set_af_mode(nssi->gpio_device,  scki->gpio_bit, 6);
-			}
-		}
-		gpio_set_af_mode(scki->gpio_device,  scki->gpio_bit, 6);
-		gpio_set_af_mode(misoi->gpio_device, misoi->gpio_bit, 6);
-		gpio_set_af_mode(mosii->gpio_device, mosii->gpio_bit, 6);
-	}
-#endif
-
-		if(nssi) {
-                    spi_config_gpios(dev, as_master, nssi->gpio_device, nssi->gpio_bit,
-                                                     scki->gpio_device, scki->gpio_bit, 
-                                                     misoi->gpio_device, misoi->gpio_bit,
-                                                     mosii->gpio_device, mosii->gpio_bit);
-		} else {
-                    spi_config_gpios(dev, as_master, NULL, -1,
-                                                     scki->gpio_device, scki->gpio_bit, 
-                                                     misoi->gpio_device, misoi->gpio_bit,
-                                                     mosii->gpio_device, mosii->gpio_bit);
-		}
-}
-
-static const spi_baud_rate baud_rates[MAX_SPI_FREQS] __FLASH__ = {
-    SPI_BAUD_PCLK_DIV_2,
-    SPI_BAUD_PCLK_DIV_4,
-    SPI_BAUD_PCLK_DIV_8,
-    SPI_BAUD_PCLK_DIV_16,
-    SPI_BAUD_PCLK_DIV_32,
-    SPI_BAUD_PCLK_DIV_64,
-    SPI_BAUD_PCLK_DIV_128,
-    SPI_BAUD_PCLK_DIV_256,
-};
-
-/*
- * Note: This assumes you're on a LeafLabs-style board
- * (CYCLES_PER_MICROSECOND == 72, APB2 at 72MHz, APB1 at 36MHz).
- */
-static spi_baud_rate determine_baud_rate(spi_dev *dev, SPIFrequency freq) {
-    if (rcc_dev_clk(dev->clk_id) == RCC_APB2 && freq == SPI_140_625KHZ) {
-        /* APB2 peripherals are too fast for 140.625 KHz */
-        ASSERT(0);
-        return (spi_baud_rate)~0;
-    }
-    return (rcc_dev_clk(dev->clk_id) == RCC_APB2 ?
-            baud_rates[freq + 1] :
-            baud_rates[freq]);
-}
diff --git a/STM32F4/cores/maple/libmaple/HardwareSPI.h b/STM32F4/cores/maple/libmaple/HardwareSPI.h
deleted file mode 100644
index 327f29da1..000000000
--- a/STM32F4/cores/maple/libmaple/HardwareSPI.h
+++ /dev/null
@@ -1,279 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file HardwareSPI.h
- * @brief High-level SPI interface
- *
- * This is a "bare essentials" polling driver for now.
- */
-
-/* TODO [0.1.0] Remove deprecated methods. */
-
-#include "libmaple_types.h"
-#include "spi.h"
-
-#include "boards.h"
-#include "wirish.h"
-
-#ifndef _HARDWARESPI_H_
-#define _HARDWARESPI_H_
-
-/**
- * @brief Defines the possible SPI communication speeds.
- */
-typedef enum SPIFrequency {
-    SPI_18MHZ       = 0, /**< 18 MHz */
-    SPI_9MHZ        = 1, /**< 9 MHz */
-    SPI_4_5MHZ      = 2, /**< 4.5 MHz */
-    SPI_2_25MHZ     = 3, /**< 2.25 MHz */
-    SPI_1_125MHZ    = 4, /**< 1.125 MHz */
-    SPI_562_500KHZ  = 5, /**< 562.500 KHz */
-    SPI_281_250KHZ  = 6, /**< 281.250 KHz */
-    SPI_140_625KHZ  = 7, /**< 140.625 KHz */
-} SPIFrequency;
-
-#define MAX_SPI_FREQS 8
-
-#if CYCLES_PER_MICROSECOND != 72
-/* TODO [0.2.0?] something smarter than this */
-//#warning "Unexpected clock speed; SPI frequency calculation will be incorrect"
-#endif
-
-
-//#define BOARD_SPI_DEFAULT_SS PC13
-#define BOARD_SPI_DEFAULT_SS PB0
-#define SPI_MODE0 SPI_MODE_0
-#define SPI_MODE1 SPI_MODE_1
-#define SPI_MODE2 SPI_MODE_2
-#define SPI_MODE3 SPI_MODE_3
-
-/*
-class SPISettings {
-public:
-	SPISettings(uint32 clock, BitOrder bitOrder, uint8 dataMode) {
-		if (__builtin_constant_p(clock)) {
-			init_AlwaysInline(clock, bitOrder, dataMode);
-		} else {
-			init_MightInline(clock, bitOrder, dataMode);
-		}
-	}
-	SPISettings() { init_AlwaysInline(4000000, MSBFIRST, SPI_MODE0); }
-private:
-	void init_MightInline(uint32 clock, BitOrder bitOrder, uint8 dataMode) {
-		init_AlwaysInline(clock, bitOrder, dataMode);
-	}
-	void init_AlwaysInline(uint32 clock, BitOrder bitOrder, uint8 dataMode) __attribute__((__always_inline__)) {
-		this->clock = clock;
-		this->bitOrder = bitOrder;
-		this->dataMode = dataMode;
-	}
-	uint32 clock;
-	BitOrder bitOrder;
-	uint8 dataMode;
-	friend class HardwareSPI;
-};
-*/
-
-
-/**
- * @brief Wirish SPI interface.
- *
- * This implementation uses software slave management, so the caller
- * is responsible for controlling the slave select line.
- */
-class HardwareSPI {
-public:
-    /**
-     * @param spiPortNumber Number of the SPI port to manage.
-     */
-    HardwareSPI(uint32 spiPortNumber);
-
-    /*
-     * Set up/tear down
-     */
-
-    /**
-     * @brief Turn on a SPI port and set its GPIO pin modes for use as master.
-     *
-     * SPI port is enabled in full duplex mode, with software slave management.
-     *
-     * @param frequency Communication frequency
-     * @param bitOrder Either LSBFIRST (little-endian) or MSBFIRST (big-endian)
-     * @param mode SPI mode to use, one of SPI_MODE_0, SPI_MODE_1,
-     *             SPI_MODE_2, and SPI_MODE_3.
-     */
-    void begin(SPIFrequency frequency, uint32 bitOrder, uint32 mode);
-
-    /**
-     * @brief Equivalent to begin(SPI_1_125MHZ, MSBFIRST, 0).
-     */
-    void begin(void);
-
-    /**
-     * @brief Turn on a SPI port and set its GPIO pin modes for use as a slave.
-     *
-     * SPI port is enabled in full duplex mode, with software slave management.
-     *
-     * @param bitOrder Either LSBFIRST (little-endian) or MSBFIRST(big-endian)
-     * @param mode SPI mode to use
-     */
-    void beginSlave(uint32 bitOrder, uint32 mode);
-
-    /**
-     * @brief Equivalent to beginSlave(MSBFIRST, 0).
-     */
-    void beginSlave(void);
-
-    /**
-     * @brief Disables the SPI port, but leaves its GPIO pin modes unchanged.
-     */
-    void end(void);
-
-    /*
-     * I/O
-     */
-
-    /**
-     * @brief Return the next unread byte.
-     *
-     * If there is no unread byte waiting, this function will block
-     * until one is received.
-     */
-    uint8 read(void);
-
-    /**
-     * @brief Read length bytes, storing them into buffer.
-     * @param buffer Buffer to store received bytes into.
-     * @param length Number of bytes to store in buffer.  This
-     *               function will block until the desired number of
-     *               bytes have been read.
-     */
-    void read(uint8 *buffer, uint32 length);
-
-	/**
-     * @brief Read length bytes, storing them into buffer.
-     * @param buffer Buffer to store received bytes into.
-     * @param length Number of bytes to store in buffer.  This
-     *               function will block until the desired number of
-     *               bytes have been read.
-     */
-    void readMaster(uint8 *buffer, uint32 length);
-
-
-	void waitReady();
-    /**
-     * @brief Transmit a byte.
-     * @param data Byte to transmit.
-     */
-    void write(uint8 data);
-
-    /**
-     * @brief Transmit multiple bytes.
-     * @param buffer Bytes to transmit.
-     * @param length Number of bytes in buffer to transmit.
-     */
-    void write(const uint8 *buffer, uint32 length);
-
-    /**
-     * @brief Transmit a byte, then return the next unread byte.
-     *
-     * This function transmits before receiving.
-     *
-     * @param data Byte to transmit.
-     * @return Next unread byte.
-     */
-    uint8 transfer(uint8 data);
-
-    /*
-     * Pin accessors
-     */
-
-    /**
-     * @brief Return the number of the MISO (master in, slave out) pin
-     */
-    uint8 misoPin(void);
-
-    /**
-     * @brief Return the number of the MOSI (master out, slave in) pin
-     */
-    uint8 mosiPin(void);
-
-    /**
-     * @brief Return the number of the SCK (serial clock) pin
-     */
-    uint8 sckPin(void);
-
-    /**
-     * @brief Return the number of the NSS (slave select) pin
-     */
-    uint8 nssPin(void);
-
-    /* -- The following methods are deprecated --------------------------- */
-
-    /**
-     * @brief Deprecated.
-     *
-     * Use HardwareSPI::transfer() instead.
-     *
-     * @see HardwareSPI::transfer()
-     */
-    uint8 send(uint8 data);
-
-    /**
-     * @brief Deprecated.
-     *
-     * Use HardwareSPI::write() in combination with
-     * HardwareSPI::read() (or HardwareSPI::transfer()) instead.
-     *
-     * @see HardwareSPI::write()
-     * @see HardwareSPI::read()
-     * @see HardwareSPI::transfer()
-     */
-    uint8 send(const uint8 *data, uint32 length);
-
-    /**
-     * @brief Deprecated.
-     *
-     * Use HardwareSPI::read() instead.
-     *
-     * @see HardwareSPI::read()
-     */
-    uint8 recv(void);
-    
-//    void beginTransaction(SPISettings settings) { beginTransaction(BOARD_SPI_DEFAULT_SS, settings); }
-//    void beginTransaction(uint8 pin, SPISettings settings);
-    void endTransaction(void) { }
-                            
-private:
-    spi_dev *spi_d;
-};
-
-
-extern HardwareSPI SPI;
-
-#endif
-
diff --git a/STM32F4/cores/maple/libmaple/HardwareSerial.cpp b/STM32F4/cores/maple/libmaple/HardwareSerial.cpp
index 59ce71d11..f9387d15a 100644
--- a/STM32F4/cores/maple/libmaple/HardwareSerial.cpp
+++ b/STM32F4/cores/maple/libmaple/HardwareSerial.cpp
@@ -56,19 +56,19 @@
 #define RX5 BOARD_UART5_RX_PIN
 #endif
 
-HardwareSerial Serial(USART1, TX1, RX1);
+HardwareSerial Serial1(USART1, TX1, RX1);
 
 #ifdef TX2
-HardwareSerial Serial1(USART2, TX2, RX2);
+HardwareSerial Serial2(USART2, TX2, RX2);
 #endif
 
 #ifdef TX3
-HardwareSerial Serial2(USART3, TX3, RX3);
+HardwareSerial Serial3(USART3, TX3, RX3);
 #endif
 
 #if defined(STM32_HIGH_DENSITY) && !defined(BOARD_maple_RET6)
-HardwareSerial Serial3(UART4,  TX4, RX4);
-HardwareSerial Serial4(UART5,  TX5, RX5);
+HardwareSerial Serial4(UART4,  TX4, RX4);
+HardwareSerial Serial5(UART5,  TX5, RX5);
 #endif
 
 HardwareSerial::HardwareSerial(usart_dev *usart_device,
@@ -90,25 +90,23 @@ void HardwareSerial::begin(uint32 baud) {
         return;
     }
 
-    const stm32_pin_info *txi = &PIN_MAP[tx_pin];
-    const stm32_pin_info *rxi = &PIN_MAP[rx_pin];
-#ifdef STM32F2
+#ifdef STM32F4
 	// int af = 7<<8;
     if (usart_device == UART4 || usart_device == UART5) {
-        gpio_set_af_mode(txi->gpio_device, txi->gpio_bit, 8);
-        gpio_set_af_mode(rxi->gpio_device, rxi->gpio_bit, 8);
+        gpio_set_af_mode(tx_pin, 8);
+        gpio_set_af_mode(rx_pin, 8);
     }
     else {
-        gpio_set_af_mode(txi->gpio_device, txi->gpio_bit, 7);
-        gpio_set_af_mode(rxi->gpio_device, rxi->gpio_bit, 7);
+        gpio_set_af_mode(tx_pin, 7);
+        gpio_set_af_mode(rx_pin, 7);
     }
-    gpio_set_mode(txi->gpio_device, txi->gpio_bit, (gpio_pin_mode)(GPIO_AF_OUTPUT_PP | GPIO_PUPD_INPUT_PU | 0x700));
-    gpio_set_mode(rxi->gpio_device, rxi->gpio_bit, (gpio_pin_mode)(GPIO_MODE_AF      | GPIO_PUPD_INPUT_PU | 0x700));
+    gpio_set_mode(tx_pin, (gpio_pin_mode)(GPIO_AF_OUTPUT_PP | GPIO_PUPD_INPUT_PU | 0x700));
+    gpio_set_mode(rx_pin, (gpio_pin_mode)(GPIO_MODE_AF      | GPIO_PUPD_INPUT_PU | 0x700));
     //gpio_set_mode(txi->gpio_device, txi->gpio_bit, (gpio_pin_mode)(GPIO_PUPD_INPUT_PU));
     //gpio_set_mode(rxi->gpio_device, rxi->gpio_bit, (gpio_pin_mode)(GPIO_PUPD_INPUT_PU));
 #else
-	gpio_set_mode(txi->gpio_device, txi->gpio_bit, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(rxi->gpio_device, rxi->gpio_bit, GPIO_INPUT_FLOATING);
+	gpio_set_mode(tx_pin, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(rx_pin, GPIO_INPUT_FLOATING);
 #endif
 #if 0
     if (txi->timer_device != NULL) {
diff --git a/STM32F4/cores/maple/libmaple/HardwareSerial.h b/STM32F4/cores/maple/libmaple/HardwareSerial.h
index c09fe54f1..d7e8a3d1f 100644
--- a/STM32F4/cores/maple/libmaple/HardwareSerial.h
+++ b/STM32F4/cores/maple/libmaple/HardwareSerial.h
@@ -75,12 +75,12 @@ class HardwareSerial : public Stream {
     uint8 rx_pin;
 };
 
-extern HardwareSerial Serial;
 extern HardwareSerial Serial1;
 extern HardwareSerial Serial2;
 #if defined(STM32_HIGH_DENSITY) && !defined(BOARD_maple_RET6)
 extern HardwareSerial Serial3;
 extern HardwareSerial Serial4;
+extern HardwareSerial Serial5;
 #endif
 extern HardwareSerial &SerialDebug;
 #endif
diff --git a/STM32F4/cores/maple/libmaple/adc.c b/STM32F4/cores/maple/libmaple/adc.c
index aeeb43c0e..0f4c02c3c 100644
--- a/STM32F4/cores/maple/libmaple/adc.c
+++ b/STM32F4/cores/maple/libmaple/adc.c
@@ -41,27 +41,24 @@
 #include "rcc.h"
 #include "adc.h"
 
-static adc_dev adc1 = {
+/** ADC1 device. */
+const adc_dev ADC1 = {
     .regs   = ADC1_BASE,
     .clk_id = RCC_ADC1
 };
-/** ADC1 device. */
-const adc_dev *ADC1 = &adc1;
 
-static adc_dev adc2 = {
+/** ADC2 device. */
+const adc_dev ADC2 = {
     .regs   = ADC2_BASE,
     .clk_id = RCC_ADC2
 };
-/** ADC2 device. */
-const adc_dev *ADC2 = &adc2;
 
 #ifdef STM32_HIGH_DENSITY
-adc_dev adc3 = {
+/** ADC3 device. */
+const adc_dev ADC3 = {
     .regs   = ADC3_BASE,
     .clk_id = RCC_ADC3
 };
-/** ADC3 device. */
-const adc_dev *ADC3 = &adc3;
 #endif
 
 /**
@@ -74,7 +71,7 @@ const adc_dev *ADC3 = &adc3;
  */
 void adc_init(const adc_dev *dev) {
     rcc_clk_enable(dev->clk_id);
-#ifdef STM32F2
+#ifdef STM32F4
     if(dev->clk_id == RCC_ADC1) {
     	rcc_reset_dev(dev->clk_id);
     }
@@ -101,10 +98,10 @@ void adc_set_extsel(const adc_dev *dev, adc_extsel_event event) {
  * @param fn Function to call on each ADC device.
  */
 void adc_foreach(void (*fn)(const adc_dev*)) {
-    fn(ADC1);
-    fn(ADC2);
+    fn(&ADC1);
+    fn(&ADC2);
 #ifdef STM32_HIGH_DENSITY
-    fn(ADC3);
+    fn(&ADC3);
 #endif
 }
 
@@ -136,7 +133,9 @@ void adc_set_sample_rate(const adc_dev *dev, adc_smp_rate smp_rate) {
  * @brief Calibrate an ADC peripheral
  * @param dev adc device
  */
-void adc_calibrate(const adc_dev *dev) {
+void adc_calibrate(const adc_dev *dev)
+{
+/*
 #ifndef STM32F2
     __io uint32 *rstcal_bit = bb_perip(&(dev->regs->CR2), 3);
     __io uint32 *cal_bit = bb_perip(&(dev->regs->CR2), 2);
@@ -149,6 +148,7 @@ void adc_calibrate(const adc_dev *dev) {
     while (*cal_bit)
         ;
 #endif
+*/
 }
 
 /**
@@ -171,8 +171,8 @@ uint16 adc_read(const adc_dev *dev, uint8 channel) {
     return (uint16)(regs->DR & ADC_DR_DATA);
 }
 
-void setupADC_F2() {
-#ifdef STM32F2
+void setupADC_F4(void)
+{
 		  uint32 tmpreg1 = 0;
 
 		  tmpreg1 = ADC_COMMON->CCR;
@@ -196,5 +196,4 @@ void setupADC_F2() {
 
 		  /* Write to ADC CCR */
 		  ADC_COMMON->CCR = tmpreg1;
-#endif
 }
diff --git a/STM32F4/cores/maple/libmaple/adc.h b/STM32F4/cores/maple/libmaple/adc.h
index 3a40d4c58..6fa61f5ea 100644
--- a/STM32F4/cores/maple/libmaple/adc.h
+++ b/STM32F4/cores/maple/libmaple/adc.h
@@ -42,17 +42,15 @@ extern "C"{
 #endif
 
 
-#ifdef STM32F2
-  typedef struct
-  {
-    __io uint32 CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
-    __io uint32 CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
-    __io uint32 CDR;    /*!< ADC common regular data register for dual
-                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
-  } ADC_Common_TypeDef;
+typedef struct
+{
+	__io uint32 CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
+	__io uint32 CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
+	__io uint32 CDR;    /*!< ADC common regular data register for dual
+							 AND triple modes,                            Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
 #define ADC_COMMON  ((ADC_Common_TypeDef *) 0x40012300)
 
-#endif
 
 /** ADC register map type. */
 typedef struct adc_reg_map {
@@ -84,33 +82,22 @@ typedef struct adc_dev {
     rcc_clk_id clk_id; /**< RCC clock information */
 } adc_dev;
 
-extern const adc_dev *ADC1;
-extern const adc_dev *ADC2;
+extern const adc_dev ADC1;
+extern const adc_dev ADC2;
 #ifdef STM32_HIGH_DENSITY
-extern const adc_dev *ADC3;
+extern const adc_dev ADC3;
 #endif
 
 /*
  * Register map base pointers
  */
 
-#ifdef STM32F2
-	/** ADC1 register map base pointer. */
-	#define ADC1_BASE                       ((struct adc_reg_map*)0x40012000)
-	/** ADC2 register map base pointer. */
-	#define ADC2_BASE                       ((struct adc_reg_map*)0x40012100)
-  /** ADC3 register map base pointer. */
-  #define ADC3_BASE                       ((struct adc_reg_map*)0x40012200)
-#else
-	/** ADC1 register map base pointer. */
-	#define ADC1_BASE                       ((struct adc_reg_map*)0x40012400)
-	/** ADC2 register map base pointer. */
-	#define ADC2_BASE                       ((struct adc_reg_map*)0x40012800)
-	#ifdef STM32_HIGH_DENSITY
-  	/** ADC3 register map base pointer. */
-	  #define ADC3_BASE                       ((struct adc_reg_map*)0x40013C00)
-  #endif
-#endif
+/** ADC1 register map base pointer. */
+#define ADC1_BASE                       ((struct adc_reg_map*)0x40012000)
+/** ADC2 register map base pointer. */
+#define ADC2_BASE                       ((struct adc_reg_map*)0x40012100)
+/** ADC3 register map base pointer. */
+#define ADC3_BASE                       ((struct adc_reg_map*)0x40012200)
 
 /*
  * Register bit definitions
@@ -167,17 +154,10 @@ extern const adc_dev *ADC3;
 #define ADC_CR2_JEXTTRIG_BIT            15
 #define ADC_CR2_EXTTRIG_BIT             20
 #define ADC_CR2_TSEREFE_BIT             23
-#ifdef STM32F2
 #define ADC_CR2_JSWSTART_BIT            22
 #define ADC_CR2_SWSTART_BIT             30
 #define ADC_CR2_EXTSEL                  (0x0F000000)
 #define ADC_CR2_JEXTSEL                 (0x000F0000)
-#else
-#define ADC_CR2_JSWSTART_BIT            21
-#define ADC_CR2_SWSTART_BIT             22
-#define ADC_CR2_EXTSEL                  (0x000E0000)
-#define ADC_CR2_JEXTSEL                 (0x00007000)
-#endif
 
 
 
@@ -388,7 +368,7 @@ static inline void adc_disable_all(void) {
     adc_foreach(adc_disable);
 }
 
-void setupADC_F2();
+extern void setupADC_F4(void);
 
 #ifdef __cplusplus
 } // extern "C"
diff --git a/STM32F4/cores/maple/libmaple/dac.c b/STM32F4/cores/maple/libmaple/dac.c
index 264e4e21a..3853f903c 100644
--- a/STM32F4/cores/maple/libmaple/dac.c
+++ b/STM32F4/cores/maple/libmaple/dac.c
@@ -126,11 +126,11 @@ void dac_enable_channel(const dac_dev *dev, uint8 channel) {
      */
     switch (channel) {
     case 1:
-        gpio_set_mode(GPIOA, 4, GPIO_INPUT_ANALOG);
+        gpio_set_mode((uint8_t)PA4, GPIO_INPUT_ANALOG);
         dev->regs->CR |= DAC_CR_EN1;
         break;
     case 2:
-        gpio_set_mode(GPIOA, 5, GPIO_INPUT_ANALOG);
+        gpio_set_mode((uint8_t)PA5, GPIO_INPUT_ANALOG);
         dev->regs->CR |= DAC_CR_EN2;
         break;
     }
diff --git a/STM32F4/cores/maple/libmaple/dma.h b/STM32F4/cores/maple/libmaple/dma.h
index a965c036f..420adf8a4 100644
--- a/STM32F4/cores/maple/libmaple/dma.h
+++ b/STM32F4/cores/maple/libmaple/dma.h
@@ -30,9 +30,4 @@
  *  @brief Direct Memory Access peripheral support
  */
 
-#ifdef STM32F2
-#include "dmaF2.h"
-#include <libmaple/dma_common.h>
-#else
-#include "dmaF1.h"
-#endif
+#include "dmaF4.h"
diff --git a/STM32F4/cores/maple/libmaple/dmaF1.c b/STM32F4/cores/maple/libmaple/dmaF1.c
deleted file mode 100644
index f8ddb2d22..000000000
--- a/STM32F4/cores/maple/libmaple/dmaF1.c
+++ /dev/null
@@ -1,383 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Michael Hope.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-#ifdef STM32F1
-
-/**
- * @file dma.c
- * @author Marti Bolivar <mbolivar@leaflabs.com>;
- *         Original implementation by Michael Hope
- * @brief Direct Memory Access peripheral support
- */
-
-#include "dma.h"
-#include "bitband.h"
-#include "util.h"
-
-/*
- * Devices
- */
-
-static dma_dev dma1 = {
-    .regs     = DMA1_BASE,
-    .clk_id   = RCC_DMA1,
-    .handlers = {{ .handler = NULL, .irq_line = NVIC_DMA_CH1 },
-                 { .handler = NULL, .irq_line = NVIC_DMA_CH2 },
-                 { .handler = NULL, .irq_line = NVIC_DMA_CH3 },
-                 { .handler = NULL, .irq_line = NVIC_DMA_CH4 },
-                 { .handler = NULL, .irq_line = NVIC_DMA_CH5 },
-                 { .handler = NULL, .irq_line = NVIC_DMA_CH6 },
-                 { .handler = NULL, .irq_line = NVIC_DMA_CH7 }}
-};
-/** DMA1 device */
-dma_dev *DMA1 = &dma1;
-
-#ifdef STM32_HIGH_DENSITY
-static dma_dev dma2 = {
-    .regs     = DMA2_BASE,
-    .clk_id   = RCC_DMA2,
-    .handlers = {{ .handler = NULL, .irq_line = NVIC_DMA2_CH1   },
-                 { .handler = NULL, .irq_line = NVIC_DMA2_CH2   },
-                 { .handler = NULL, .irq_line = NVIC_DMA2_CH3   },
-                 { .handler = NULL, .irq_line = NVIC_DMA2_CH_4_5 },
-                 { .handler = NULL, .irq_line = NVIC_DMA2_CH_4_5 }} /* !@#$ */
-};
-/** DMA2 device */
-dma_dev *DMA2 = &dma2;
-#endif
-
-/*
- * Convenience routines
- */
-
-/**
- * @brief Initialize a DMA device.
- * @param dev Device to initialize.
- */
-void dma_init(dma_dev *dev) {
-    rcc_clk_enable(dev->clk_id);
-}
-
-/**
- * @brief Set up a DMA transfer.
- *
- * The channel will be disabled before being reconfigured.  The
- * transfer will have low priority by default.  You may choose another
- * priority before the transfer begins using dma_set_priority(), as
- * well as performing any other configuration you desire.  When the
- * channel is configured to your liking, enable it using dma_enable().
- *
- * @param dev DMA device.
- * @param channel DMA channel.
- * @param peripheral_address Base address of peripheral data register
- *                           involved in the transfer.
- * @param peripheral_size Peripheral data transfer size.
- * @param memory_address Base memory address involved in the transfer.
- * @param memory_size Memory data transfer size.
- * @param mode Logical OR of dma_mode_flags
- * @sideeffect Disables the given DMA channel.
- * @see dma_xfer_size
- * @see dma_mode_flags
- * @see dma_set_num_transfers()
- * @see dma_set_priority()
- * @see dma_attach_interrupt()
- * @see dma_enable()
- */
-void dma_setup_transfer(dma_dev       *dev,
-                        dma_channel    channel,
-                        __io void     *peripheral_address,
-                        dma_xfer_size  peripheral_size,
-                        __io void     *memory_address,
-                        dma_xfer_size  memory_size,
-                        uint32         mode) {
-    dma_channel_reg_map *channel_regs = dma_channel_regs(dev, channel);
-
-    dma_disable(dev, channel);  /* can't write to CMAR/CPAR otherwise */
-    channel_regs->CCR = (memory_size << 10) | (peripheral_size << 8) | mode;
-    channel_regs->CMAR = (uint32)memory_address;
-    channel_regs->CPAR = (uint32)peripheral_address;
-}
-
-/**
- * @brief Set the number of data to be transferred on a DMA channel.
- *
- * You may not call this function while the channel is enabled.
- *
- * @param dev DMA device
- * @param channel Channel through which the transfer occurs.
- * @param num_transfers
- */
-void dma_set_num_transfers(dma_dev *dev,
-                           dma_channel channel,
-                           uint16 num_transfers) {
-    dma_channel_reg_map *channel_regs;
-
-    ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
-
-    channel_regs = dma_channel_regs(dev, channel);
-    channel_regs->CNDTR = num_transfers;
-}
-
-/**
- * @brief Set the priority of a DMA transfer.
- *
- * You may not call this function while the channel is enabled.
- *
- * @param dev DMA device
- * @param channel DMA channel
- * @param priority priority to set.
- */
-void dma_set_priority(dma_dev *dev,
-                      dma_channel channel,
-                      dma_priority priority) {
-    dma_channel_reg_map *channel_regs;
-    uint32 ccr;
-
-    ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
-
-    channel_regs = dma_channel_regs(dev, channel);
-    ccr = channel_regs->CCR;
-    ccr &= ~DMA_CCR_PL;
-    ccr |= priority;
-    channel_regs->CCR = ccr;
-}
-
-/**
- * @brief Attach an interrupt to a DMA transfer.
- *
- * Interrupts are enabled using appropriate mode flags in
- * dma_setup_transfer().
- *
- * @param dev DMA device
- * @param channel Channel to attach handler to
- * @param handler Interrupt handler to call when channel interrupt fires.
- * @see dma_setup_transfer()
- * @see dma_get_irq_cause()
- * @see dma_detach_interrupt()
- */
-void dma_attach_interrupt(dma_dev *dev,
-                          dma_channel channel,
-                          void (*handler)(void)) {
-    dev->handlers[channel - 1].handler = handler;
-    nvic_irq_enable(dev->handlers[channel - 1].irq_line);
-}
-
-/**
- * @brief Detach a DMA transfer interrupt handler.
- *
- * After calling this function, the given channel's interrupts will be
- * disabled.
- *
- * @param dev DMA device
- * @param channel Channel whose handler to detach
- * @sideeffect Clears interrupt enable bits in the channel's CCR register.
- * @see dma_attach_interrupt()
- */
-void dma_detach_interrupt(dma_dev *dev, dma_channel channel) {
-    /* Don't use nvic_irq_disable()! Think about DMA2 channels 4 and 5. */
-    dma_channel_regs(dev, channel)->CCR &= ~0xF;
-    dev->handlers[channel - 1].handler = NULL;
-}
-
-/**
- * @brief Discover the reason why a DMA interrupt was called.
- *
- * You may only call this function within an attached interrupt
- * handler for the given channel.
- *
- * This function resets the internal DMA register state which encodes
- * the cause of the interrupt; consequently, it can only be called
- * once per interrupt handler invocation.
- *
- * @param dev DMA device
- * @param channel Channel whose interrupt is being handled.
- * @return Reason why the interrupt fired.
- * @sideeffect Clears channel status flags in dev->regs->ISR.
- * @see dma_attach_interrupt()
- * @see dma_irq_cause
- */
-dma_irq_cause dma_get_irq_cause(dma_dev *dev, dma_channel channel) {
-    uint8 status_bits = dma_get_isr_bits(dev, channel);
-
-    /* If the channel global interrupt flag is cleared, then
-     * something's very wrong. */
-    ASSERT(status_bits & BIT(0));
-
-    dma_clear_isr_bits(dev, channel);
-
-    /* ISR flags get set even if the corresponding interrupt enable
-     * bits in the channel's configuration register are cleared, so we
-     * can't use a switch here.
-     *
-     * Don't change the order of these if statements. */
-    if (status_bits & BIT(3)) {
-        return DMA_TRANSFER_ERROR;
-    } else if (status_bits & BIT(1)) {
-        return DMA_TRANSFER_COMPLETE;
-    } else if (status_bits & BIT(2)) {
-        return DMA_TRANSFER_HALF_COMPLETE;
-    } else if (status_bits & BIT(0)) {
-        /* Shouldn't happen (unless someone messed up an IFCR write). */
-        throb();
-    }
-#if DEBUG_LEVEL < DEBUG_ALL
-    else {
-        /* We shouldn't have been called, but the debug level is too
-         * low for the above ASSERT() to have had any effect.  In
-         * order to fail fast, mimic the DMA controller's behavior
-         * when an error occurs. */
-        dma_disable(dev, channel);
-    }
-#endif
-    return DMA_TRANSFER_ERROR;
-}
-
-/**
- * @brief Enable a DMA channel.
- * @param dev DMA device
- * @param channel Channel to enable
- */
-void dma_enable(dma_dev *dev, dma_channel channel) {
-    dma_channel_reg_map *chan_regs = dma_channel_regs(dev, channel);
-    bb_peri_set_bit(&chan_regs->CCR, DMA_CCR_EN_BIT, 1);
-}
-
-/**
- * @brief Disable a DMA channel.
- * @param dev DMA device
- * @param channel Channel to disable
- */
-void dma_disable(dma_dev *dev, dma_channel channel) {
-    dma_channel_reg_map *chan_regs = dma_channel_regs(dev, channel);
-    bb_peri_set_bit(&chan_regs->CCR, DMA_CCR_EN_BIT, 0);
-}
-
-/**
- * @brief Set the base memory address where data will be read from or
- *        written to.
- *
- * You must not call this function while the channel is enabled.
- *
- * If the DMA memory size is 16 bits, the address is automatically
- * aligned to a half-word.  If the DMA memory size is 32 bits, the
- * address is aligned to a word.
- *
- * @param dev DMA Device
- * @param channel Channel whose base memory address to set.
- * @param addr Memory base address to use.
- */
-void dma_set_mem_addr(dma_dev *dev, dma_channel channel, __io void *addr) {
-    dma_channel_reg_map *chan_regs;
-
-    ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
-
-    chan_regs = dma_channel_regs(dev, channel);
-    chan_regs->CMAR = (uint32)addr;
-}
-
-/**
- * @brief Set the base peripheral address where data will be read from
- *        or written to.
- *
- * You must not call this function while the channel is enabled.
- *
- * If the DMA peripheral size is 16 bits, the address is automatically
- * aligned to a half-word.  If the DMA peripheral size is 32 bits, the
- * address is aligned to a word.
- *
- * @param dev DMA Device
- * @param channel Channel whose peripheral data register base address to set.
- * @param addr Peripheral memory base address to use.
- */
-void dma_set_per_addr(dma_dev *dev, dma_channel channel, __io void *addr) {
-    dma_channel_reg_map *chan_regs;
-
-    ASSERT_FAULT(!dma_is_channel_enabled(dev, channel));
-
-    chan_regs = dma_channel_regs(dev, channel);
-    chan_regs->CPAR = (uint32)addr;
-}
-
-/*
- * IRQ handlers
- */
-
-static inline void dispatch_handler(dma_dev *dev, dma_channel channel) {
-    void (*handler)(void) = dev->handlers[channel - 1].handler;
-    if (handler) {
-        handler();
-        dma_clear_isr_bits(dev, channel); /* in case handler doesn't */
-    }
-}
-
-void __irq_dma1_channel1(void) {
-    dispatch_handler(DMA1, DMA_CH1);
-}
-
-void __irq_dma1_channel2(void) {
-    dispatch_handler(DMA1, DMA_CH2);
-}
-
-void __irq_dma1_channel3(void) {
-    dispatch_handler(DMA1, DMA_CH3);
-}
-
-void __irq_dma1_channel4(void) {
-    dispatch_handler(DMA1, DMA_CH4);
-}
-
-void __irq_dma1_channel5(void) {
-    dispatch_handler(DMA1, DMA_CH5);
-}
-
-void __irq_dma1_channel6(void) {
-    dispatch_handler(DMA1, DMA_CH6);
-}
-
-void __irq_dma1_channel7(void) {
-    dispatch_handler(DMA1, DMA_CH7);
-}
-
-#ifdef STM32_HIGH_DENSITY
-void __irq_dma2_channel1(void) {
-    dispatch_handler(DMA2, DMA_CH1);
-}
-
-void __irq_dma2_channel2(void) {
-    dispatch_handler(DMA2, DMA_CH2);
-}
-
-void __irq_dma2_channel3(void) {
-    dispatch_handler(DMA2, DMA_CH3);
-}
-
-void __irq_dma2_channel4_5(void) {
-    dispatch_handler(DMA2, DMA_CH4);
-    dispatch_handler(DMA2, DMA_CH5);
-}
-#endif
-
-#endif
\ No newline at end of file
diff --git a/STM32F4/cores/maple/libmaple/dmaF1.h b/STM32F4/cores/maple/libmaple/dmaF1.h
deleted file mode 100644
index 6e8087f49..000000000
--- a/STM32F4/cores/maple/libmaple/dmaF1.h
+++ /dev/null
@@ -1,453 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Michael Hope.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file dma.h
- *
- * @author Marti Bolivar <mbolivar@leaflabs.com>;
- *         Original implementation by Michael Hope
- *
- * @brief Direct Memory Access peripheral support
- */
-
-/*
- * See /notes/dma.txt for more information.
- */
-
-#ifndef _DMA_H_
-#define _DMA_H_
-
-#include "libmaple_types.h"
-#include "rcc.h"
-#include "nvic.h"
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-/*
- * Register maps
- */
-
-/**
- * @brief DMA register map type.
- *
- * Note that DMA controller 2 (register map base pointer DMA2_BASE)
- * only supports channels 1--5.
- */
-typedef struct dma_reg_map {
-    __io uint32 ISR;            /**< Interrupt status register */
-    __io uint32 IFCR;           /**< Interrupt flag clear register */
-    __io uint32 CCR1;           /**< Channel 1 configuration register */
-    __io uint32 CNDTR1;         /**< Channel 1 number of data register */
-    __io uint32 CPAR1;          /**< Channel 1 peripheral address register */
-    __io uint32 CMAR1;          /**< Channel 1 memory address register */
-    const uint32 RESERVED1;     /**< Reserved. */
-    __io uint32 CCR2;           /**< Channel 2 configuration register */
-    __io uint32 CNDTR2;         /**< Channel 2 number of data register */
-    __io uint32 CPAR2;          /**< Channel 2 peripheral address register */
-    __io uint32 CMAR2;          /**< Channel 2 memory address register */
-    const uint32 RESERVED2;     /**< Reserved. */
-    __io uint32 CCR3;           /**< Channel 3 configuration register */
-    __io uint32 CNDTR3;         /**< Channel 3 number of data register */
-    __io uint32 CPAR3;          /**< Channel 3 peripheral address register */
-    __io uint32 CMAR3;          /**< Channel 3 memory address register */
-    const uint32 RESERVED3;     /**< Reserved. */
-    __io uint32 CCR4;           /**< Channel 4 configuration register */
-    __io uint32 CNDTR4;         /**< Channel 4 number of data register */
-    __io uint32 CPAR4;          /**< Channel 4 peripheral address register */
-    __io uint32 CMAR4;          /**< Channel 4 memory address register */
-    const uint32 RESERVED4;     /**< Reserved. */
-    __io uint32 CCR5;           /**< Channel 5 configuration register */
-    __io uint32 CNDTR5;         /**< Channel 5 number of data register */
-    __io uint32 CPAR5;          /**< Channel 5 peripheral address register */
-    __io uint32 CMAR5;          /**< Channel 5 memory address register */
-    const uint32 RESERVED5;     /**< Reserved. */
-    __io uint32 CCR6;           /**< Channel 6 configuration register */
-    __io uint32 CNDTR6;         /**< Channel 6 number of data register */
-    __io uint32 CPAR6;          /**< Channel 6 peripheral address register */
-    __io uint32 CMAR6;          /**< Channel 6 memory address register */
-    const uint32 RESERVED6;     /**< Reserved. */
-    __io uint32 CCR7;           /**< Channel 7 configuration register */
-    __io uint32 CNDTR7;         /**< Channel 7 number of data register */
-    __io uint32 CPAR7;          /**< Channel 7 peripheral address register */
-    __io uint32 CMAR7;          /**< Channel 7 memory address register */
-    const uint32 RESERVED7;     /**< Reserved. */
-} dma_reg_map;
-
-/** DMA controller 1 register map base pointer */
-#define DMA1_BASE                       ((struct dma_reg_map*)0x40020000)
-
-#ifdef STM32_HIGH_DENSITY
-/** DMA controller 2 register map base pointer */
-#define DMA2_BASE                       ((struct dma_reg_map*)0x40020400)
-#endif
-
-/*
- * Register bit definitions
- */
-
-/* Interrupt status register */
-
-#define DMA_ISR_TEIF7_BIT               27
-#define DMA_ISR_HTIF7_BIT               26
-#define DMA_ISR_TCIF7_BIT               25
-#define DMA_ISR_GIF7_BIT                24
-#define DMA_ISR_TEIF6_BIT               23
-#define DMA_ISR_HTIF6_BIT               22
-#define DMA_ISR_TCIF6_BIT               21
-#define DMA_ISR_GIF6_BIT                20
-#define DMA_ISR_TEIF5_BIT               19
-#define DMA_ISR_HTIF5_BIT               18
-#define DMA_ISR_TCIF5_BIT               17
-#define DMA_ISR_GIF5_BIT                16
-#define DMA_ISR_TEIF4_BIT               15
-#define DMA_ISR_HTIF4_BIT               14
-#define DMA_ISR_TCIF4_BIT               13
-#define DMA_ISR_GIF4_BIT                12
-#define DMA_ISR_TEIF3_BIT               11
-#define DMA_ISR_HTIF3_BIT               10
-#define DMA_ISR_TCIF3_BIT               9
-#define DMA_ISR_GIF3_BIT                8
-#define DMA_ISR_TEIF2_BIT               7
-#define DMA_ISR_HTIF2_BIT               6
-#define DMA_ISR_TCIF2_BIT               5
-#define DMA_ISR_GIF2_BIT                4
-#define DMA_ISR_TEIF1_BIT               3
-#define DMA_ISR_HTIF1_BIT               2
-#define DMA_ISR_TCIF1_BIT               1
-#define DMA_ISR_GIF1_BIT                0
-
-#define DMA_ISR_TEIF7                   BIT(DMA_ISR_TEIF7_BIT)
-#define DMA_ISR_HTIF7                   BIT(DMA_ISR_HTIF7_BIT)
-#define DMA_ISR_TCIF7                   BIT(DMA_ISR_TCIF7_BIT)
-#define DMA_ISR_GIF7                    BIT(DMA_ISR_GIF7_BIT)
-#define DMA_ISR_TEIF6                   BIT(DMA_ISR_TEIF6_BIT)
-#define DMA_ISR_HTIF6                   BIT(DMA_ISR_HTIF6_BIT)
-#define DMA_ISR_TCIF6                   BIT(DMA_ISR_TCIF6_BIT)
-#define DMA_ISR_GIF6                    BIT(DMA_ISR_GIF6_BIT)
-#define DMA_ISR_TEIF5                   BIT(DMA_ISR_TEIF5_BIT)
-#define DMA_ISR_HTIF5                   BIT(DMA_ISR_HTIF5_BIT)
-#define DMA_ISR_TCIF5                   BIT(DMA_ISR_TCIF5_BIT)
-#define DMA_ISR_GIF5                    BIT(DMA_ISR_GIF5_BIT)
-#define DMA_ISR_TEIF4                   BIT(DMA_ISR_TEIF4_BIT)
-#define DMA_ISR_HTIF4                   BIT(DMA_ISR_HTIF4_BIT)
-#define DMA_ISR_TCIF4                   BIT(DMA_ISR_TCIF4_BIT)
-#define DMA_ISR_GIF4                    BIT(DMA_ISR_GIF4_BIT)
-#define DMA_ISR_TEIF3                   BIT(DMA_ISR_TEIF3_BIT)
-#define DMA_ISR_HTIF3                   BIT(DMA_ISR_HTIF3_BIT)
-#define DMA_ISR_TCIF3                   BIT(DMA_ISR_TCIF3_BIT)
-#define DMA_ISR_GIF3                    BIT(DMA_ISR_GIF3_BIT)
-#define DMA_ISR_TEIF2                   BIT(DMA_ISR_TEIF2_BIT)
-#define DMA_ISR_HTIF2                   BIT(DMA_ISR_HTIF2_BIT)
-#define DMA_ISR_TCIF2                   BIT(DMA_ISR_TCIF2_BIT)
-#define DMA_ISR_GIF2                    BIT(DMA_ISR_GIF2_BIT)
-#define DMA_ISR_TEIF1                   BIT(DMA_ISR_TEIF1_BIT)
-#define DMA_ISR_HTIF1                   BIT(DMA_ISR_HTIF1_BIT)
-#define DMA_ISR_TCIF1                   BIT(DMA_ISR_TCIF1_BIT)
-#define DMA_ISR_GIF1                    BIT(DMA_ISR_GIF1_BIT)
-
-/* Interrupt flag clear register */
-
-#define DMA_IFCR_CTEIF7_BIT             27
-#define DMA_IFCR_CHTIF7_BIT             26
-#define DMA_IFCR_CTCIF7_BIT             25
-#define DMA_IFCR_CGIF7_BIT              24
-#define DMA_IFCR_CTEIF6_BIT             23
-#define DMA_IFCR_CHTIF6_BIT             22
-#define DMA_IFCR_CTCIF6_BIT             21
-#define DMA_IFCR_CGIF6_BIT              20
-#define DMA_IFCR_CTEIF5_BIT             19
-#define DMA_IFCR_CHTIF5_BIT             18
-#define DMA_IFCR_CTCIF5_BIT             17
-#define DMA_IFCR_CGIF5_BIT              16
-#define DMA_IFCR_CTEIF4_BIT             15
-#define DMA_IFCR_CHTIF4_BIT             14
-#define DMA_IFCR_CTCIF4_BIT             13
-#define DMA_IFCR_CGIF4_BIT              12
-#define DMA_IFCR_CTEIF3_BIT             11
-#define DMA_IFCR_CHTIF3_BIT             10
-#define DMA_IFCR_CTCIF3_BIT             9
-#define DMA_IFCR_CGIF3_BIT              8
-#define DMA_IFCR_CTEIF2_BIT             7
-#define DMA_IFCR_CHTIF2_BIT             6
-#define DMA_IFCR_CTCIF2_BIT             5
-#define DMA_IFCR_CGIF2_BIT              4
-#define DMA_IFCR_CTEIF1_BIT             3
-#define DMA_IFCR_CHTIF1_BIT             2
-#define DMA_IFCR_CTCIF1_BIT             1
-#define DMA_IFCR_CGIF1_BIT              0
-
-#define DMA_IFCR_CTEIF7                 BIT(DMA_IFCR_CTEIF7_BIT)
-#define DMA_IFCR_CHTIF7                 BIT(DMA_IFCR_CHTIF7_BIT)
-#define DMA_IFCR_CTCIF7                 BIT(DMA_IFCR_CTCIF7_BIT)
-#define DMA_IFCR_CGIF7                  BIT(DMA_IFCR_CGIF7_BIT)
-#define DMA_IFCR_CTEIF6                 BIT(DMA_IFCR_CTEIF6_BIT)
-#define DMA_IFCR_CHTIF6                 BIT(DMA_IFCR_CHTIF6_BIT)
-#define DMA_IFCR_CTCIF6                 BIT(DMA_IFCR_CTCIF6_BIT)
-#define DMA_IFCR_CGIF6                  BIT(DMA_IFCR_CGIF6_BIT)
-#define DMA_IFCR_CTEIF5                 BIT(DMA_IFCR_CTEIF5_BIT)
-#define DMA_IFCR_CHTIF5                 BIT(DMA_IFCR_CHTIF5_BIT)
-#define DMA_IFCR_CTCIF5                 BIT(DMA_IFCR_CTCIF5_BIT)
-#define DMA_IFCR_CGIF5                  BIT(DMA_IFCR_CGIF5_BIT)
-#define DMA_IFCR_CTEIF4                 BIT(DMA_IFCR_CTEIF4_BIT)
-#define DMA_IFCR_CHTIF4                 BIT(DMA_IFCR_CHTIF4_BIT)
-#define DMA_IFCR_CTCIF4                 BIT(DMA_IFCR_CTCIF4_BIT)
-#define DMA_IFCR_CGIF4                  BIT(DMA_IFCR_CGIF4_BIT)
-#define DMA_IFCR_CTEIF3                 BIT(DMA_IFCR_CTEIF3_BIT)
-#define DMA_IFCR_CHTIF3                 BIT(DMA_IFCR_CHTIF3_BIT)
-#define DMA_IFCR_CTCIF3                 BIT(DMA_IFCR_CTCIF3_BIT)
-#define DMA_IFCR_CGIF3                  BIT(DMA_IFCR_CGIF3_BIT)
-#define DMA_IFCR_CTEIF2                 BIT(DMA_IFCR_CTEIF2_BIT)
-#define DMA_IFCR_CHTIF2                 BIT(DMA_IFCR_CHTIF2_BIT)
-#define DMA_IFCR_CTCIF2                 BIT(DMA_IFCR_CTCIF2_BIT)
-#define DMA_IFCR_CGIF2                  BIT(DMA_IFCR_CGIF2_BIT)
-#define DMA_IFCR_CTEIF1                 BIT(DMA_IFCR_CTEIF1_BIT)
-#define DMA_IFCR_CHTIF1                 BIT(DMA_IFCR_CHTIF1_BIT)
-#define DMA_IFCR_CTCIF1                 BIT(DMA_IFCR_CTCIF1_BIT)
-#define DMA_IFCR_CGIF1                  BIT(DMA_IFCR_CGIF1_BIT)
-
-/* Channel configuration register */
-
-#define DMA_CCR_MEM2MEM_BIT             14
-#define DMA_CCR_MINC_BIT                7
-#define DMA_CCR_PINC_BIT                6
-#define DMA_CCR_CIRC_BIT                5
-#define DMA_CCR_DIR_BIT                 4
-#define DMA_CCR_TEIE_BIT                3
-#define DMA_CCR_HTIE_BIT                2
-#define DMA_CCR_TCIE_BIT                1
-#define DMA_CCR_EN_BIT                  0
-
-#define DMA_CCR_MEM2MEM                 BIT(DMA_CCR_MEM2MEM_BIT)
-#define DMA_CCR_PL                      (0x3 << 12)
-#define DMA_CCR_PL_LOW                  (0x0 << 12)
-#define DMA_CCR_PL_MEDIUM               (0x1 << 12)
-#define DMA_CCR_PL_HIGH                 (0x2 << 12)
-#define DMA_CCR_PL_VERY_HIGH            (0x3 << 12)
-#define DMA_CCR_MSIZE                   (0x3 << 10)
-#define DMA_CCR_MSIZE_8BITS             (0x0 << 10)
-#define DMA_CCR_MSIZE_16BITS            (0x1 << 10)
-#define DMA_CCR_MSIZE_32BITS            (0x2 << 10)
-#define DMA_CCR_PSIZE                   (0x3 << 8)
-#define DMA_CCR_PSIZE_8BITS             (0x0 << 8)
-#define DMA_CCR_PSIZE_16BITS            (0x1 << 8)
-#define DMA_CCR_PSIZE_32BITS            (0x2 << 8)
-#define DMA_CCR_MINC                    BIT(DMA_CCR_MINC_BIT)
-#define DMA_CCR_PINC                    BIT(DMA_CCR_PINC_BIT)
-#define DMA_CCR_CIRC                    BIT(DMA_CCR_CIRC_BIT)
-#define DMA_CCR_DIR                     BIT(DMA_CCR_DIR_BIT)
-#define DMA_CCR_TEIE                    BIT(DMA_CCR_TEIE_BIT)
-#define DMA_CCR_HTIE                    BIT(DMA_CCR_HTIE_BIT)
-#define DMA_CCR_TCIE                    BIT(DMA_CCR_TCIE_BIT)
-#define DMA_CCR_EN                      BIT(DMA_CCR_EN_BIT)
-
-/*
- * Devices
- */
-
-/** Encapsulates state related to a DMA channel interrupt. */
-typedef struct dma_handler_config {
-    void (*handler)(void);      /**< User-specified channel interrupt
-                                     handler */
-    nvic_irq_num irq_line;      /**< Channel's NVIC interrupt number */
-} dma_handler_config;
-
-/** DMA device type */
-typedef struct dma_dev {
-    dma_reg_map *regs;             /**< Register map */
-    rcc_clk_id clk_id;             /**< Clock ID */
-    dma_handler_config handlers[]; /**<
-                                    * @brief IRQ handlers and NVIC numbers.
-                                    *
-                                    * @see dma_attach_interrupt()
-                                    * @see dma_detach_interrupt()
-                                    */
-} dma_dev;
-
-extern dma_dev *DMA1;
-#ifdef STM32_HIGH_DENSITY
-extern dma_dev *DMA2;
-#endif
-
-/*
- * Convenience functions
- */
-
-void dma_init(dma_dev *dev);
-
-/** Flags for DMA transfer configuration. */
-typedef enum dma_mode_flags {
-    DMA_MEM_2_MEM  = 1 << 14, /**< Memory to memory mode */
-    DMA_MINC_MODE  = 1 << 7,  /**< Auto-increment memory address */
-    DMA_PINC_MODE  = 1 << 6,  /**< Auto-increment peripheral address */
-    DMA_CIRC_MODE  = 1 << 5,  /**< Circular mode */
-    DMA_FROM_MEM   = 1 << 4,  /**< Read from memory to peripheral */
-    DMA_TRNS_ERR   = 1 << 3,  /**< Interrupt on transfer error */
-    DMA_HALF_TRNS  = 1 << 2,  /**< Interrupt on half-transfer */
-    DMA_TRNS_CMPLT = 1 << 1   /**< Interrupt on transfer completion */
-} dma_mode_flags;
-
-/** Source and destination transfer sizes. */
-typedef enum dma_xfer_size {
-    DMA_SIZE_8BITS  = 0,        /**< 8-bit transfers */
-    DMA_SIZE_16BITS = 1,        /**< 16-bit transfers */
-    DMA_SIZE_32BITS = 2         /**< 32-bit transfers */
-} dma_xfer_size;
-
-/** DMA channel */
-typedef enum dma_channel {
-    DMA_CH1 = 1,                /**< Channel 1 */
-    DMA_CH2 = 2,                /**< Channel 2 */
-    DMA_CH3 = 3,                /**< Channel 3 */
-    DMA_CH4 = 4,                /**< Channel 4 */
-    DMA_CH5 = 5,                /**< Channel 5 */
-    DMA_CH6 = 6,                /**< Channel 6 */
-    DMA_CH7 = 7,                /**< Channel 7 */
-} dma_channel;
-
-void dma_setup_transfer(dma_dev       *dev,
-                        dma_channel    channel,
-                        __io void     *peripheral_address,
-                        dma_xfer_size  peripheral_size,
-                        __io void     *memory_address,
-                        dma_xfer_size  memory_size,
-                        uint32         mode);
-
-void dma_set_num_transfers(dma_dev *dev,
-                           dma_channel channel,
-                           uint16 num_transfers);
-
-/** DMA transfer priority. */
-typedef enum dma_priority {
-    DMA_PRIORITY_LOW       = DMA_CCR_PL_LOW,      /**< Low priority */
-    DMA_PRIORITY_MEDIUM    = DMA_CCR_PL_MEDIUM,   /**< Medium priority */
-    DMA_PRIORITY_HIGH      = DMA_CCR_PL_HIGH,     /**< High priority */
-    DMA_PRIORITY_VERY_HIGH = DMA_CCR_PL_VERY_HIGH /**< Very high priority */
-} dma_priority;
-
-void dma_set_priority(dma_dev *dev,
-                      dma_channel channel,
-                      dma_priority priority);
-
-void dma_attach_interrupt(dma_dev *dev,
-                          dma_channel channel,
-                          void (*handler)(void));
-void dma_detach_interrupt(dma_dev *dev, dma_channel channel);
-
-/**
- * Encodes the reason why a DMA interrupt was called.
- * @see dma_get_irq_cause()
- */
-typedef enum dma_irq_cause {
-    DMA_TRANSFER_COMPLETE,      /**< Transfer is complete. */
-    DMA_TRANSFER_HALF_COMPLETE, /**< Transfer is half complete. */
-    DMA_TRANSFER_ERROR,         /**< Error occurred during transfer. */
-} dma_irq_cause;
-
-dma_irq_cause dma_get_irq_cause(dma_dev *dev, dma_channel channel);
-
-void dma_enable(dma_dev *dev, dma_channel channel);
-void dma_disable(dma_dev *dev, dma_channel channel);
-
-void dma_set_mem_addr(dma_dev *dev, dma_channel channel, __io void *address);
-void dma_set_per_addr(dma_dev *dev, dma_channel channel, __io void *address);
-
-/**
- * @brief DMA channel register map type.
- *
- * Provides access to an individual channel's registers.
- */
-typedef struct dma_channel_reg_map {
-    __io uint32 CCR;           /**< Channel configuration register */
-    __io uint32 CNDTR;         /**< Channel number of data register */
-    __io uint32 CPAR;          /**< Channel peripheral address register */
-    __io uint32 CMAR;          /**< Channel memory address register */
-} dma_channel_reg_map;
-
-#define DMA_CHANNEL_NREGS 5
-
-/**
- * @brief Obtain a pointer to an individual DMA channel's registers.
- *
- * For example, dma_channel_regs(DMA1, DMA_CH1)->CCR is DMA1_BASE->CCR1.
- *
- * @param dev DMA device
- * @param channel DMA channel whose channel register map to obtain.
- */
-static inline dma_channel_reg_map* dma_channel_regs(dma_dev *dev,
-                                                    dma_channel channel) {
-    __io uint32 *ccr1 = &dev->regs->CCR1;
-    return (dma_channel_reg_map*)(ccr1 + DMA_CHANNEL_NREGS * (channel - 1));
-}
-
-/**
- * @brief Check if a DMA channel is enabled
- * @param dev DMA device
- * @param channel Channel whose enabled bit to check.
- */
-static inline uint8 dma_is_channel_enabled(dma_dev *dev, dma_channel channel) {
-    return (uint8)(dma_channel_regs(dev, channel)->CCR & DMA_CCR_EN);
-}
-
-/**
- * @brief Get the ISR status bits for a DMA channel.
- *
- * The bits are returned right-aligned, in the following order:
- * transfer error flag, half-transfer flag, transfer complete flag,
- * global interrupt flag.
- *
- * If you're attempting to figure out why a DMA interrupt fired; you
- * may find dma_get_irq_cause() more convenient.
- *
- * @param dev DMA device
- * @param channel Channel whose ISR bits to return.
- * @see dma_get_irq_cause().
- */
-static inline uint8 dma_get_isr_bits(dma_dev *dev, dma_channel channel) {
-    uint8 shift = (channel - 1) * 4;
-    return (dev->regs->ISR >> shift) & 0xF;
-}
-
-/**
- * @brief Clear the ISR status bits for a given DMA channel.
- *
- * If you're attempting to clean up after yourself in a DMA interrupt,
- * you may find dma_get_irq_cause() more convenient.
- *
- * @param dev DMA device
- * @param channel Channel whose ISR bits to clear.
- * @see dma_get_irq_cause()
- */
-static inline void dma_clear_isr_bits(dma_dev *dev, dma_channel channel) {
-    dev->regs->IFCR = BIT(4 * (channel - 1));
-}
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
-#endif
diff --git a/STM32F4/cores/maple/libmaple/dmaF2.c b/STM32F4/cores/maple/libmaple/dmaF4.c
similarity index 91%
rename from STM32F4/cores/maple/libmaple/dmaF2.c
rename to STM32F4/cores/maple/libmaple/dmaF4.c
index 0911e584a..add3d8e51 100644
--- a/STM32F4/cores/maple/libmaple/dmaF2.c
+++ b/STM32F4/cores/maple/libmaple/dmaF4.c
@@ -24,10 +24,10 @@
  * SOFTWARE.
  *****************************************************************************/
 
- #ifdef STM32F2
+#ifdef STM32F4
  
 /**
- * @file dmaF2.c
+ * @file dmaF4.c
  * @brief Direct Memory Access peripheral support
  */
 
@@ -117,33 +117,16 @@ void dma_detach_interrupt(dma_dev *dev, dma_stream stream) {
     dev->handlers[stream].handler = NULL;
 }
 
+const uint8 dma_isr_bits_shift[] = { 0, 6, 16, 22};
+
+uint8 dma_get_isr_bits(dma_dev *dev, dma_stream stream) {
+	if ( stream&0xFC )	return ((dev->regs->HISR)>>dma_isr_bits_shift[stream&0x03]) & 0x3d;
+	else				return ((dev->regs->LISR)>>dma_isr_bits_shift[stream&0x03]) & 0x3d;
+}
+
 void dma_clear_isr_bits(dma_dev *dev, dma_stream stream) {
-    switch (stream) {
-    case 0:
-        dev->regs->LIFCR|=0x0000003d;
-        break;
-    case 1:
-        dev->regs->LIFCR|=0x00000f40;
-        break;
-    case 2:
-        dev->regs->LIFCR|=0x003d0000;
-        break;
-    case 3:
-        dev->regs->LIFCR|=0x0f400000;
-        break;
-    case 4:
-        dev->regs->HIFCR|=0x0000003d;
-        break;
-    case 5:
-        dev->regs->HIFCR|=0x00000f40;
-        break;
-    case 6:
-        dev->regs->HIFCR|=0x003d0000;
-        break;
-    case 7:
-        dev->regs->HIFCR|=0x0f400000;
-        break;
-    }
+	if ( stream&0xFC )	dev->regs->HIFCR = (uint32)0x0000003d << dma_isr_bits_shift[stream&0x03];
+	else				dev->regs->LIFCR = (uint32)0x0000003d << dma_isr_bits_shift[stream&0x03];
 }
 
 /*
diff --git a/STM32F4/cores/maple/libmaple/dmaF2.h b/STM32F4/cores/maple/libmaple/dmaF4.h
similarity index 74%
rename from STM32F4/cores/maple/libmaple/dmaF2.h
rename to STM32F4/cores/maple/libmaple/dmaF4.h
index 6f7086f36..757906c82 100644
--- a/STM32F4/cores/maple/libmaple/dmaF2.h
+++ b/STM32F4/cores/maple/libmaple/dmaF4.h
@@ -25,7 +25,7 @@
  *****************************************************************************/
 
 /**
- * @file dma.h
+ * @file dmaF4.h
  *
  * @author Marti Bolivar <mbolivar@leaflabs.com>;
  *         Original implementation by Michael Hope
@@ -84,7 +84,7 @@ typedef struct dma_reg_map {
  * Register bit definitions
  */
 
-/* Channel configuration register */
+/* Stream configuration register */
 
 #define DMA_CR_CH0                      (0x0 << 25)
 #define DMA_CR_CH1                      (0x1 << 25)
@@ -136,6 +136,25 @@ typedef struct dma_reg_map {
 #define DMA_CR_DMEIE                    (0x1 << 1)
 #define DMA_CR_EN                       (0x1)
 
+typedef enum dma_channel {
+    DMA_CH0 = DMA_CR_CH0,                /**< Channel 0 */
+    DMA_CH1 = DMA_CR_CH1,                /**< Channel 1 */
+    DMA_CH2 = DMA_CR_CH2,                /**< Channel 2 */
+    DMA_CH3 = DMA_CR_CH3,                /**< Channel 3 */
+    DMA_CH4 = DMA_CR_CH4,                /**< Channel 4 */
+    DMA_CH5 = DMA_CR_CH5,                /**< Channel 5 */
+    DMA_CH6 = DMA_CR_CH6,                /**< Channel 6 */
+    DMA_CH7 = DMA_CR_CH7,                /**< Channel 7 */
+} dma_channel;
+
+/* Device interrupt status register flags */
+
+#define DMA_ISR_TCIF    (1 << 5)
+#define DMA_ISR_HTIF    (1 << 4)
+#define DMA_ISR_TEIF    (1 << 3)
+#define DMA_ISR_DMEIF   (1 << 2)
+#define DMA_ISR_FEIF    (1 << 0)
+
 /*
  * Devices
  */
@@ -166,25 +185,35 @@ extern dma_dev *DMA2;
  * Convenience functions
  */
 
-void dma_init(dma_dev *dev);
+extern void dma_init(dma_dev *dev);
 
 /** Flags for DMA transfer configuration. */
 typedef enum dma_mode_flags {
-    DMA_MEM_2_MEM  = 1 << 14, /**< Memory to memory mode */
-    DMA_MINC_MODE  = 1 << 7,  /**< Auto-increment memory address */
-    DMA_PINC_MODE  = 1 << 6,  /**< Auto-increment peripheral address */
-    DMA_CIRC_MODE  = 1 << 5,  /**< Circular mode */
-    DMA_FROM_MEM   = 1 << 4,  /**< Read from memory to peripheral */
-    DMA_TRNS_ERR   = 1 << 3,  /**< Interrupt on transfer error */
-    DMA_HALF_TRNS  = 1 << 2,  /**< Interrupt on half-transfer */
-    DMA_TRNS_CMPLT = 1 << 1   /**< Interrupt on transfer completion */
+    DMA_MEM_BUF_0 = DMA_CR_CT0, /**< Current memory target buffer 0 */
+    DMA_MEM_BUF_1 = DMA_CR_CT1, /**< Current memory target buffer 1 */
+    DMA_DBL_BUF_MODE = DMA_CR_DBM,  /**< Current memory double buffer mode */
+    DMA_PINC_OFFSET  = DMA_CR_PINCOS,  /**< Peripheral increment offset size */
+    DMA_MINC_MODE  = DMA_CR_MINC,  /**< Memory increment mode */
+    DMA_PINC_MODE  = DMA_CR_PINC,  /**< Peripheral increment mode */
+    DMA_CIRC_MODE  = DMA_CR_CIRC,  /**< Memory Circular mode */
+    DMA_FROM_PER   = DMA_CR_DIR_P2M,  /**< Read from memory to peripheral */
+    DMA_FROM_MEM   = DMA_CR_DIR_M2P,  /**< Read from memory to peripheral */
+    DMA_MEM_TO_MEM = DMA_CR_DIR_M2M,  /**< Read from memory to memory */
+    DMA_PERIF_CTRL   = DMA_CR_PFCTRL,  /**< Peripheral flow controller */
+    DMA_PRIO_MEDIUM    = DMA_CR_PL_MEDIUM,    /**< Medium priority */
+    DMA_PRIO_HIGH      = DMA_CR_PL_HIGH,      /**< High priority */
+    DMA_PRIO_VERY_HIGH = DMA_CR_PL_VERY_HIGH, /**< Very high priority */
+    DMA_TRNS_CMPLT   = DMA_CR_TCIE,   /**< Interrupt on transfer completion */
+    DMA_TRNS_HALF    = DMA_CR_HTIE,  /**< Interrupt on half-transfer */
+    DMA_TRNS_ERR       = DMA_CR_TEIE,  /**< Interrupt on transfer error */
+    DMA_DIR_MODE_ERR   = DMA_CR_DMEIE  /**< Interrupt on direct mode error */
 } dma_mode_flags;
 
 /** Source and destination transfer sizes. */
 typedef enum dma_xfer_size {
-    DMA_SIZE_8BITS  = 0,        /**< 8-bit transfers */
-    DMA_SIZE_16BITS = 1,        /**< 16-bit transfers */
-    DMA_SIZE_32BITS = 2         /**< 32-bit transfers */
+    DMA_SIZE_8BITS  = ( DMA_CR_MSIZE_8BITS|DMA_CR_PSIZE_8BITS ),        /**< 8-bit transfers */
+    DMA_SIZE_16BITS = (DMA_CR_MSIZE_16BITS|DMA_CR_PSIZE_16BITS),        /**< 16-bit transfers */
+    DMA_SIZE_32BITS = (DMA_CR_MSIZE_32BITS|DMA_CR_PSIZE_32BITS)         /**< 32-bit transfers */
 } dma_xfer_size;
 
 /** DMA channel */
@@ -201,17 +230,17 @@ typedef enum dma_stream {
     
 static inline void dma_setup_transfer(dma_dev       *dev,
                                       dma_stream    stream,
+                                      dma_channel   channel,
+                                      dma_xfer_size trx_size,
                                       __io void     *peripheral_address,
                                       __io void     *memory_address0,
                                       __io void     *memory_address1,
-                                      uint32         flags,
-                                      uint32         fifo_flags) {
+                                      uint32        flags) {
     dev->regs->STREAM[stream].CR &= ~DMA_CR_EN; // disable
     dev->regs->STREAM[stream].PAR = (uint32)peripheral_address;
     dev->regs->STREAM[stream].M0AR = (uint32)memory_address0;
     dev->regs->STREAM[stream].M1AR = (uint32)memory_address1;
-    dev->regs->STREAM[stream].FCR = fifo_flags & 0x87; // mask out reserved bits
-    dev->regs->STREAM[stream].CR = flags & 0x0feffffe; // mask out reserved and enable
+    dev->regs->STREAM[stream].CR = ((flags|channel|trx_size) & 0x0feffffe); // mask out reserved and enable
 }
     
 static inline void dma_set_num_transfers(dma_dev *dev,
@@ -220,6 +249,12 @@ static inline void dma_set_num_transfers(dma_dev *dev,
     dev->regs->STREAM[stream].NDTR = num_transfers;
 }
 
+static inline void dma_set_fifo_flags(dma_dev *dev,
+                                      dma_stream stream,
+                                      uint8 fifo_flags) {
+    dev->regs->STREAM[stream].FCR = fifo_flags & 0x87; // mask out reserved bits
+}
+
 void dma_attach_interrupt(dma_dev *dev,
                           dma_stream stream,
                           void (*handler)(void));
@@ -232,6 +267,7 @@ static inline void dma_enable(dma_dev *dev, dma_stream stream) {
 
 static inline void dma_disable(dma_dev *dev, dma_stream stream) {
     dev->regs->STREAM[stream].CR &= ~DMA_CR_EN;
+	while (dev->regs->STREAM[stream].CR & DMA_CR_EN); // wait till EN bit is reset, see AN4031, chapter 4.1
 }    
 
 /**
diff --git a/STM32F4/cores/maple/libmaple/exti.h b/STM32F4/cores/maple/libmaple/exti.h
index bac8adcf4..063f2d7f1 100644
--- a/STM32F4/cores/maple/libmaple/exti.h
+++ b/STM32F4/cores/maple/libmaple/exti.h
@@ -52,11 +52,7 @@ typedef struct exti_reg_map {
 } exti_reg_map;
 
 /** EXTI register map base pointer */
-#ifdef STM32F2
 #define EXTI_BASE                       ((struct exti_reg_map*)0x40013C00)
-#else
-#define EXTI_BASE                       ((struct exti_reg_map*)0x40010400)
-#endif
 
 /** External interrupt trigger mode */
 typedef enum exti_trigger_mode {
diff --git a/STM32F4/cores/maple/libmaple/fsmc.c b/STM32F4/cores/maple/libmaple/fsmc.c
index 06ca7df6a..42b0d77b4 100644
--- a/STM32F4/cores/maple/libmaple/fsmc.c
+++ b/STM32F4/cores/maple/libmaple/fsmc.c
@@ -39,27 +39,28 @@
  */
 void fsmc_sram_init_gpios(void) {
     /* Data lines... */
-    gpio_set_mode(GPIOD,  0, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOD,  1, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOD,  8, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOD,  9, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOD, 10, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOD, 14, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOD, 15, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE,  7, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE,  8, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE,  9, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE, 10, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE, 11, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE, 12, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE, 13, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE, 14, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOE, 15, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD0, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD1, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD8, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD9, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD10, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD14, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD15, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE7, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE8, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE9, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE10, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE11, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE12, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE13, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE14, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PE15, GPIO_AF_OUTPUT_PP);
 
     /* Address lines... */
-    gpio_set_mode(GPIOD, 11, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOD, 12, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOD, 13, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD11, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD12, GPIO_AF_OUTPUT_PP);
+    gpio_set_mode(PD13, GPIO_AF_OUTPUT_PP);
+#if 0 // not available on LQFP package
     gpio_set_mode(GPIOF,  0, GPIO_AF_OUTPUT_PP);
     gpio_set_mode(GPIOF,  1, GPIO_AF_OUTPUT_PP);
     gpio_set_mode(GPIOF,  2, GPIO_AF_OUTPUT_PP);
@@ -76,18 +77,20 @@ void fsmc_sram_init_gpios(void) {
     gpio_set_mode(GPIOG,  3, GPIO_AF_OUTPUT_PP);
     gpio_set_mode(GPIOG,  4, GPIO_AF_OUTPUT_PP);
     gpio_set_mode(GPIOG,  5, GPIO_AF_OUTPUT_PP);
-
+#endif  // not available on LQFP package
     /* And control lines... */
-    gpio_set_mode(GPIOD,  4, GPIO_AF_OUTPUT_PP);   // NOE
-    gpio_set_mode(GPIOD,  5, GPIO_AF_OUTPUT_PP);   // NWE
+    gpio_set_mode(PD4, GPIO_AF_OUTPUT_PP);   // NOE
+    gpio_set_mode(PD5, GPIO_AF_OUTPUT_PP);   // NWE
 
-    gpio_set_mode(GPIOD,  7, GPIO_AF_OUTPUT_PP);   // NE1
+    gpio_set_mode(PD7, GPIO_AF_OUTPUT_PP);   // NE1
+#if 0 // not available on LQFP package
     gpio_set_mode(GPIOG,  9, GPIO_AF_OUTPUT_PP);   // NE2
     gpio_set_mode(GPIOG, 10, GPIO_AF_OUTPUT_PP);   // NE3
     gpio_set_mode(GPIOG, 12, GPIO_AF_OUTPUT_PP);   // NE4
+#endif  // not available on LQFP package
 
-    gpio_set_mode(GPIOE,  0, GPIO_AF_OUTPUT_PP);   // NBL0
-    gpio_set_mode(GPIOE,  1, GPIO_AF_OUTPUT_PP);   // NBL1
+    gpio_set_mode(PE0, GPIO_AF_OUTPUT_PP);   // NBL0
+    gpio_set_mode(PE1, GPIO_AF_OUTPUT_PP);   // NBL1
 }
 
 #endif  /* STM32_HIGH_DENSITY */
diff --git a/STM32F4/cores/maple/libmaple/gpio.h b/STM32F4/cores/maple/libmaple/gpio.h
index 4d42386c1..f1a141fee 100644
--- a/STM32F4/cores/maple/libmaple/gpio.h
+++ b/STM32F4/cores/maple/libmaple/gpio.h
@@ -31,8 +31,102 @@
  *         (AFIO) prototypes, defines, and inlined access functions.
  */
 
-#ifdef STM32F2
-#include "gpioF2.h"
-#else
-#include "gpioF1.h"
+#ifndef _GPIO_H_
+#define _GPIO_H_
+
+#include "libmaple.h"
+#include "boards.h"
+
+#ifdef __cplusplus
+extern "C"{
 #endif
+
+
+/**
+ * @brief Get a GPIO port's corresponding afio_exti_port.
+ * @param dev GPIO device whose afio_exti_port to return.
+ */
+static inline afio_exti_port gpio_exti_port(const gpio_dev *dev) {
+    return dev->exti_port;
+}
+
+/**
+ * Set or reset a GPIO pin.
+ *
+ * Pin must have previously been configured to output mode.
+ *
+ * @param dev GPIO device whose pin to set.
+ * @param pin Pin on to set or reset
+ * @param val If true, set the pin.  If false, reset the pin.
+ */
+static inline void gpio_write_pin(uint8_t pin, uint8 val) {
+    if (val) {
+        (PIN_MAP[pin].gpio_device)->regs->BSRRL = BIT(pin&0x0F);
+    } else {
+        (PIN_MAP[pin].gpio_device)->regs->BSRRH = BIT(pin&0x0F);
+    }
+}
+
+static inline void gpio_set_pin(uint8_t pin) {
+	(PIN_MAP[pin].gpio_device)->regs->BSRRL = BIT(pin&0x0F);
+}
+
+static inline void gpio_clear_pin(uint8_t pin) {
+	(PIN_MAP[pin].gpio_device)->regs->BSRRH = BIT(pin&0x0F);
+}
+
+/**
+ * Determine whether or not a GPIO pin is set.
+ *
+ * Pin must have previously been configured to input mode.
+ *
+ * @param dev GPIO device whose pin to test.
+ * @param pin Pin on dev to test.
+ * @return True if the pin is set, false otherwise.
+ */
+static inline uint32 gpio_read_pin(uint8_t pin) {
+    return (PIN_MAP[pin].gpio_device)->regs->IDR & BIT(pin&0x0F);
+}
+
+/**
+ * Toggle a pin configured as output push-pull.
+ * @param dev GPIO device.
+ * @param pin Pin on dev to toggle.
+ */
+static inline void gpio_toggle_pin(uint8_t pin) {
+    (PIN_MAP[pin].gpio_device)->regs->ODR = (PIN_MAP[pin].gpio_device)->regs->ODR ^ BIT(pin&0x0F);
+}
+
+/*
+ * GPIO Convenience routines
+ */
+
+extern void gpio_init(const gpio_dev *dev);
+extern void gpio_init_all(void);
+extern void gpio_set_mode(uint8_t pin, gpio_pin_mode mode);
+extern void gpio_set_af_mode(uint8_t pin, int mode);
+
+/*
+ * AFIO convenience routines
+ */
+
+extern void afio_init(void);
+extern void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port);
+extern void afio_remap(afio_remap_peripheral p);
+
+/**
+ * @brief Enable or disable the JTAG and SW debug ports.
+ * @param config Desired debug port configuration
+ * @see afio_debug_cfg
+ */
+static inline void afio_cfg_debug_ports(afio_debug_cfg config) {
+    //__io uint32 *mapr = &AFIO_BASE->MAPR;
+    //*mapr = (*mapr & ~AFIO_MAPR_SWJ_CFG) | config;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
+
diff --git a/STM32F4/cores/maple/libmaple/gpioF1.c b/STM32F4/cores/maple/libmaple/gpioF1.c
deleted file mode 100644
index 846b7542a..000000000
--- a/STM32F4/cores/maple/libmaple/gpioF1.c
+++ /dev/null
@@ -1,200 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-#ifdef STM32F1
-
-/**
- * @file gpio.c
- * @brief GPIO initialization routine
- */
-
-#include "gpio.h"
-#include "rcc.h"
-
-/*
- * GPIO devices
- */
-
-gpio_dev gpioa = {
-    .regs      = GPIOA_BASE,
-    .clk_id    = RCC_GPIOA,
-    .exti_port = AFIO_EXTI_PA,
-};
-/** GPIO port A device. */
-gpio_dev* const GPIOA = &gpioa;
-
-gpio_dev gpiob = {
-    .regs      = GPIOB_BASE,
-    .clk_id    = RCC_GPIOB,
-    .exti_port = AFIO_EXTI_PB,
-};
-/** GPIO port B device. */
-gpio_dev* const GPIOB = &gpiob;
-
-gpio_dev gpioc = {
-    .regs      = GPIOC_BASE,
-    .clk_id    = RCC_GPIOC,
-    .exti_port = AFIO_EXTI_PC,
-};
-/** GPIO port C device. */
-gpio_dev* const GPIOC = &gpioc;
-
-gpio_dev gpiod = {
-    .regs      = GPIOD_BASE,
-    .clk_id    = RCC_GPIOD,
-    .exti_port = AFIO_EXTI_PD,
-};
-/** GPIO port D device. */
-gpio_dev* const GPIOD = &gpiod;
-
-#ifdef STM32_HIGH_DENSITY
-gpio_dev gpioe = {
-    .regs      = GPIOE_BASE,
-    .clk_id    = RCC_GPIOE,
-    .exti_port = AFIO_EXTI_PE,
-};
-/** GPIO port E device. */
-gpio_dev* const GPIOE = &gpioe;
-
-gpio_dev gpiof = {
-    .regs      = GPIOF_BASE,
-    .clk_id    = RCC_GPIOF,
-    .exti_port = AFIO_EXTI_PF,
-};
-/** GPIO port F device. */
-gpio_dev* const GPIOF = &gpiof;
-
-gpio_dev gpiog = {
-    .regs      = GPIOG_BASE,
-    .clk_id    = RCC_GPIOG,
-    .exti_port = AFIO_EXTI_PG,
-};
-/** GPIO port G device. */
-gpio_dev* const GPIOG = &gpiog;
-#endif
-
-/*
- * GPIO convenience routines
- */
-
-/**
- * Initialize a GPIO device.
- *
- * Enables the clock for and resets the given device.
- *
- * @param dev GPIO device to initialize.
- */
-void gpio_init(gpio_dev *dev) {
-    rcc_clk_enable(dev->clk_id);
-    rcc_reset_dev(dev->clk_id);
-}
-
-/**
- * Initialize and reset all available GPIO devices.
- */
-void gpio_init_all(void) {
-    gpio_init(GPIOA);
-    gpio_init(GPIOB);
-    gpio_init(GPIOC);
-    gpio_init(GPIOD);
-#ifdef STM32_HIGH_DENSITY
-    gpio_init(GPIOE);
-    gpio_init(GPIOF);
-    gpio_init(GPIOG);
-#endif
-}
-
-/**
- * Set the mode of a GPIO pin.
- *
- * @param dev GPIO device.
- * @param pin Pin on the device whose mode to set, 0--15.
- * @param mode General purpose or alternate function mode to set the pin to.
- * @see gpio_pin_mode
- */
-void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode) {
-    gpio_reg_map *regs = dev->regs;
-    __io uint32 *cr = &regs->CRL + (pin >> 3);
-    uint32 shift = (pin & 0x7) * 4;
-    uint32 tmp = *cr;
-
-    tmp &= ~(0xF << shift);
-    tmp |= (mode == GPIO_INPUT_PU ? GPIO_INPUT_PD : mode) << shift;
-    *cr = tmp;
-
-    if (mode == GPIO_INPUT_PD) {
-        regs->ODR &= ~BIT(pin);
-    } else if (mode == GPIO_INPUT_PU) {
-        regs->ODR |= BIT(pin);
-    }
-}
-
-/*
- * AFIO
- */
-
-/**
- * @brief Initialize the AFIO clock, and reset the AFIO registers.
- */
-void afio_init(void) {
-    rcc_clk_enable(RCC_AFIO);
-    rcc_reset_dev(RCC_AFIO);
-}
-
-#define AFIO_EXTI_SEL_MASK 0xF
-
-/**
- * @brief Select a source input for an external interrupt.
- *
- * @param exti      External interrupt.
- * @param gpio_port Port which contains pin to use as source input.
- * @see afio_exti_num
- * @see afio_exti_port
- */
-void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port) {
-    __io uint32 *exti_cr = &AFIO_BASE->EXTICR1 + exti / 4;
-    uint32 shift = 4 * (exti % 4);
-    uint32 cr = *exti_cr;
-
-    cr &= ~(AFIO_EXTI_SEL_MASK << shift);
-    cr |= gpio_port << shift;
-    *exti_cr = cr;
-}
-
-/**
- * @brief Perform an alternate function remap.
- * @param remapping Remapping to perform.
- */
-void afio_remap(afio_remap_peripheral remapping) {
-    if (remapping & AFIO_REMAP_USE_MAPR2) {
-        remapping &= ~AFIO_REMAP_USE_MAPR2;
-        AFIO_BASE->MAPR2 |= remapping;
-    } else {
-        AFIO_BASE->MAPR |= remapping;
-    }
-}
-
-#endif
diff --git a/STM32F4/cores/maple/libmaple/gpioF1.h b/STM32F4/cores/maple/libmaple/gpioF1.h
deleted file mode 100644
index c69efb417..000000000
--- a/STM32F4/cores/maple/libmaple/gpioF1.h
+++ /dev/null
@@ -1,530 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
-*****************************************************************************/
-
-/**
- *  @file gpio.h
- *
- *  @brief General purpose I/O (GPIO) and Alternate Function I/O
- *         (AFIO) prototypes, defines, and inlined access functions.
- */
-
-#ifndef _GPIO_H_
-#define _GPIO_H_
-
-#include "libmaple.h"
-#include "rcc.h"
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-/*
- * GPIO register maps and devices
- */
-
-/** GPIO register map type */
-typedef struct gpio_reg_map {
-    __io uint32 CRL;      /**< Port configuration register low */
-    __io uint32 CRH;      /**< Port configuration register high */
-    __io uint32 IDR;      /**< Port input data register */
-    __io uint32 ODR;      /**< Port output data register */
-    __io uint32 BSRR;     /**< Port bit set/reset register */
-    __io uint32 BRR;      /**< Port bit reset register */
-    __io uint32 LCKR;     /**< Port configuration lock register */
-} gpio_reg_map;
-
-/**
- * @brief External interrupt line port selector.
- *
- * Used to determine which GPIO port to map an external interrupt line
- * onto. */
-/* (See AFIO sections, below) */
-typedef enum afio_exti_port {
-    AFIO_EXTI_PA,               /**< Use port A (PAx) pin. */
-    AFIO_EXTI_PB,               /**< Use port B (PBx) pin. */
-    AFIO_EXTI_PC,               /**< Use port C (PCx) pin. */
-    AFIO_EXTI_PD,               /**< Use port D (PDx) pin. */
-#ifdef STM32_HIGH_DENSITY
-    AFIO_EXTI_PE,               /**< Use port E (PEx) pin. */
-    AFIO_EXTI_PF,               /**< Use port F (PFx) pin. */
-    AFIO_EXTI_PG,               /**< Use port G (PGx) pin. */
-#endif
-} afio_exti_port;
-
-/** GPIO device type */
-typedef struct gpio_dev {
-    gpio_reg_map *regs;       /**< Register map */
-    rcc_clk_id clk_id;        /**< RCC clock information */
-    afio_exti_port exti_port; /**< AFIO external interrupt port value */
-} gpio_dev;
-
-extern gpio_dev gpioa;
-extern gpio_dev* const GPIOA;
-extern gpio_dev gpiob;
-extern gpio_dev* const GPIOB;
-extern gpio_dev gpioc;
-extern gpio_dev* const GPIOC;
-extern gpio_dev gpiod;
-extern gpio_dev* const GPIOD;
-#ifdef STM32_HIGH_DENSITY
-extern gpio_dev gpioe;
-extern gpio_dev* const GPIOE;
-extern gpio_dev gpiof;
-extern gpio_dev* const GPIOF;
-extern gpio_dev gpiog;
-extern gpio_dev* const GPIOG;
-#endif
-
-/** GPIO port A register map base pointer */
-#define GPIOA_BASE                      ((struct gpio_reg_map*)0x40010800)
-/** GPIO port B register map base pointer */
-#define GPIOB_BASE                      ((struct gpio_reg_map*)0x40010C00)
-/** GPIO port C register map base pointer */
-#define GPIOC_BASE                      ((struct gpio_reg_map*)0x40011000)
-/** GPIO port D register map base pointer */
-#define GPIOD_BASE                      ((struct gpio_reg_map*)0x40011400)
-#ifdef STM32_HIGH_DENSITY
-/** GPIO port E register map base pointer */
-#define GPIOE_BASE                      ((struct gpio_reg_map*)0x40011800)
-/** GPIO port F register map base pointer */
-#define GPIOF_BASE                      ((struct gpio_reg_map*)0x40011C00)
-/** GPIO port G register map base pointer */
-#define GPIOG_BASE                      ((struct gpio_reg_map*)0x40012000)
-#endif
-
-/*
- * GPIO register bit definitions
- */
-
-/* Control registers, low and high */
-
-#define GPIO_CR_CNF                     (0x3 << 2)
-#define GPIO_CR_CNF_INPUT_ANALOG        (0x0 << 2)
-#define GPIO_CR_CNF_INPUT_FLOATING      (0x1 << 2)
-#define GPIO_CR_CNF_INPUT_PU_PD         (0x2 << 2)
-#define GPIO_CR_CNF_OUTPUT_PP           (0x0 << 2)
-#define GPIO_CR_CNF_OUTPUT_OD           (0x1 << 2)
-#define GPIO_CR_CNF_AF_OUTPUT_PP        (0x2 << 2)
-#define GPIO_CR_CNF_AF_OUTPUT_OD        (0x3 << 2)
-#define GPIO_CR_MODE                    0x3
-#define GPIO_CR_MODE_INPUT              0x0
-#define GPIO_CR_MODE_OUTPUT_10MHZ       0x1
-#define GPIO_CR_MODE_OUTPUT_2MHZ        0x2
-#define GPIO_CR_MODE_OUTPUT_50MHZ       0x3
-
-/**
- * @brief GPIO Pin modes.
- *
- * These only allow for 50MHZ max output speeds; if you want slower,
- * use direct register access.
- */
-typedef enum gpio_pin_mode {
-    GPIO_OUTPUT_PP = (GPIO_CR_CNF_OUTPUT_PP |
-                      GPIO_CR_MODE_OUTPUT_50MHZ), /**< Output push-pull. */
-    GPIO_OUTPUT_OD = (GPIO_CR_CNF_OUTPUT_OD |
-                      GPIO_CR_MODE_OUTPUT_50MHZ), /**< Output open-drain. */
-    GPIO_AF_OUTPUT_PP = (GPIO_CR_CNF_AF_OUTPUT_PP |
-                         GPIO_CR_MODE_OUTPUT_50MHZ), /**< Alternate function
-                                                        output push-pull. */
-    GPIO_AF_OUTPUT_OD = (GPIO_CR_CNF_AF_OUTPUT_OD |
-                         GPIO_CR_MODE_OUTPUT_50MHZ), /**< Alternate function
-                                                        output open drain. */
-    GPIO_INPUT_ANALOG = (GPIO_CR_CNF_INPUT_ANALOG |
-                         GPIO_CR_MODE_INPUT), /**< Analog input. */
-    GPIO_INPUT_FLOATING = (GPIO_CR_CNF_INPUT_FLOATING |
-                           GPIO_CR_MODE_INPUT), /**< Input floating. */
-    GPIO_INPUT_PD = (GPIO_CR_CNF_INPUT_PU_PD |
-                     GPIO_CR_MODE_INPUT), /**< Input pull-down. */
-    GPIO_AF_INPUT_PD = (GPIO_INPUT_PD), /**< Input pull-down. */
-    GPIO_INPUT_PU /**< Input pull-up. */
-
-
-    /* GPIO_INPUT_PU treated as a special case, for ODR twiddling */
-} gpio_pin_mode;
-
-/*
- * GPIO Convenience routines
- */
-
-void gpio_init(gpio_dev *dev);
-void gpio_init_all(void);
-void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode);
-
-/**
- * @brief Get a GPIO port's corresponding afio_exti_port.
- * @param dev GPIO device whose afio_exti_port to return.
- */
-static inline afio_exti_port gpio_exti_port(gpio_dev *dev) {
-    return dev->exti_port;
-}
-
-/**
- * Set or reset a GPIO pin.
- *
- * Pin must have previously been configured to output mode.
- *
- * @param dev GPIO device whose pin to set.
- * @param pin Pin on to set or reset
- * @param val If true, set the pin.  If false, reset the pin.
- */
-static inline void gpio_write_bit(gpio_dev *dev, uint8 pin, uint8 val) {
-    if (val) {
-        dev->regs->BSRR = BIT(pin);
-    } else {
-        dev->regs->BRR = BIT(pin);
-    }
-}
-
-/**
- * Determine whether or not a GPIO pin is set.
- *
- * Pin must have previously been configured to input mode.
- *
- * @param dev GPIO device whose pin to test.
- * @param pin Pin on dev to test.
- * @return True if the pin is set, false otherwise.
- */
-static inline uint32 gpio_read_bit(gpio_dev *dev, uint8 pin) {
-    return dev->regs->IDR & BIT(pin);
-}
-
-/**
- * Toggle a pin configured as output push-pull.
- * @param dev GPIO device.
- * @param pin Pin on dev to toggle.
- */
-static inline void gpio_toggle_bit(gpio_dev *dev, uint8 pin) {
-    dev->regs->ODR = dev->regs->ODR ^ BIT(pin);
-}
-
-/*
- * AFIO register map
- */
-
-/** AFIO register map */
-typedef struct afio_reg_map {
-    __io uint32 EVCR;        /**< Event control register.  */
-    __io uint32 MAPR;        /**< AF remap and debug I/O configuration
-                                register. */
-    __io uint32 EXTICR1;     /**< External interrupt configuration
-                                register 1. */
-    __io uint32 EXTICR2;     /**< External interrupt configuration
-                                register 2. */
-    __io uint32 EXTICR3;     /**< External interrupt configuration
-                                register 3. */
-    __io uint32 EXTICR4;     /**< External interrupt configuration
-                                register 4. */
-    __io uint32 MAPR2;       /**< AF remap and debug I/O configuration
-                                register 2. */
-} afio_reg_map;
-
-/** AFIO register map base pointer. */
-#define AFIO_BASE                       ((struct afio_reg_map *)0x40010000)
-
-/*
- * AFIO register bit definitions
- */
-
-/* Event control register */
-
-#define AFIO_EVCR_EVOE                  (0x1 << 7)
-#define AFIO_EVCR_PORT_PA               (0x0 << 4)
-#define AFIO_EVCR_PORT_PB               (0x1 << 4)
-#define AFIO_EVCR_PORT_PC               (0x2 << 4)
-#define AFIO_EVCR_PORT_PD               (0x3 << 4)
-#define AFIO_EVCR_PORT_PE               (0x4 << 4)
-#define AFIO_EVCR_PIN_0                 0x0
-#define AFIO_EVCR_PIN_1                 0x1
-#define AFIO_EVCR_PIN_2                 0x2
-#define AFIO_EVCR_PIN_3                 0x3
-#define AFIO_EVCR_PIN_4                 0x4
-#define AFIO_EVCR_PIN_5                 0x5
-#define AFIO_EVCR_PIN_6                 0x6
-#define AFIO_EVCR_PIN_7                 0x7
-#define AFIO_EVCR_PIN_8                 0x8
-#define AFIO_EVCR_PIN_9                 0x9
-#define AFIO_EVCR_PIN_10                0xA
-#define AFIO_EVCR_PIN_11                0xB
-#define AFIO_EVCR_PIN_12                0xC
-#define AFIO_EVCR_PIN_13                0xD
-#define AFIO_EVCR_PIN_14                0xE
-#define AFIO_EVCR_PIN_15                0xF
-
-/* AF remap and debug I/O configuration register */
-
-#define AFIO_MAPR_SWJ_CFG                      (0x7 << 24)
-#define AFIO_MAPR_SWJ_CFG_FULL_SWJ             (0x0 << 24)
-#define AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST    (0x1 << 24)
-#define AFIO_MAPR_SWJ_CFG_NO_JTAG_SW           (0x2 << 24)
-#define AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW        (0x4 << 24)
-#define AFIO_MAPR_ADC2_ETRGREG_REMAP           BIT(20)
-#define AFIO_MAPR_ADC2_ETRGINJ_REMAP           BIT(19)
-#define AFIO_MAPR_ADC1_ETRGREG_REMAP           BIT(18)
-#define AFIO_MAPR_ADC1_ETRGINJ_REMAP           BIT(17)
-#define AFIO_MAPR_TIM5CH4_IREMAP               BIT(16)
-#define AFIO_MAPR_PD01_REMAP                   BIT(15)
-#define AFIO_MAPR_CAN_REMAP                    (0x3 << 13)
-#define AFIO_MAPR_CAN_REMAP_NONE               (0x0 << 13)
-#define AFIO_MAPR_CAN_REMAP_PB8_PB9            (0x2 << 13)
-#define AFIO_MAPR_CAN_REMAP_PD0_PD1            (0x3 << 13)
-#define AFIO_MAPR_TIM4_REMAP                   BIT(12)
-#define AFIO_MAPR_TIM3_REMAP                   (0x3 << 10)
-#define AFIO_MAPR_TIM3_REMAP_NONE              (0x0 << 10)
-#define AFIO_MAPR_TIM3_REMAP_PARTIAL           (0x2 << 10)
-#define AFIO_MAPR_TIM3_REMAP_FULL              (0x3 << 10)
-#define AFIO_MAPR_TIM2_REMAP                   (0x3 << 8)
-#define AFIO_MAPR_TIM2_REMAP_NONE              (0x0 << 8)
-#define AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3  (0x1 << 8)
-#define AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11 (0x2 << 8)
-#define AFIO_MAPR_TIM2_REMAP_FULL              (0x3 << 8)
-#define AFIO_MAPR_TIM1_REMAP                   (0x3 << 6)
-#define AFIO_MAPR_TIM1_REMAP_NONE              (0x0 << 6)
-#define AFIO_MAPR_TIM1_REMAP_PARTIAL           (0x1 << 6)
-#define AFIO_MAPR_TIM1_REMAP_FULL              (0x3 << 6)
-#define AFIO_MAPR_USART3_REMAP                 (0x3 << 4)
-#define AFIO_MAPR_USART3_REMAP_NONE            (0x0 << 4)
-#define AFIO_MAPR_USART3_REMAP_PARTIAL         (0x1 << 4)
-#define AFIO_MAPR_USART3_REMAP_FULL            (0x3 << 4)
-#define AFIO_MAPR_USART2_REMAP                 BIT(3)
-#define AFIO_MAPR_USART1_REMAP                 BIT(2)
-#define AFIO_MAPR_I2C1_REMAP                   BIT(1)
-#define AFIO_MAPR_SPI1_REMAP                   BIT(0)
-
-/* External interrupt configuration register 1 */
-
-#define AFIO_EXTICR1_EXTI3              (0xF << 12)
-#define AFIO_EXTICR1_EXTI3_PA           (0x0 << 12)
-#define AFIO_EXTICR1_EXTI3_PB           (0x1 << 12)
-#define AFIO_EXTICR1_EXTI3_PC           (0x2 << 12)
-#define AFIO_EXTICR1_EXTI3_PD           (0x3 << 12)
-#define AFIO_EXTICR1_EXTI3_PE           (0x4 << 12)
-#define AFIO_EXTICR1_EXTI3_PF           (0x5 << 12)
-#define AFIO_EXTICR1_EXTI3_PG           (0x6 << 12)
-#define AFIO_EXTICR1_EXTI2              (0xF << 8)
-#define AFIO_EXTICR1_EXTI2_PA           (0x0 << 8)
-#define AFIO_EXTICR1_EXTI2_PB           (0x1 << 8)
-#define AFIO_EXTICR1_EXTI2_PC           (0x2 << 8)
-#define AFIO_EXTICR1_EXTI2_PD           (0x3 << 8)
-#define AFIO_EXTICR1_EXTI2_PE           (0x4 << 8)
-#define AFIO_EXTICR1_EXTI2_PF           (0x5 << 8)
-#define AFIO_EXTICR1_EXTI2_PG           (0x6 << 8)
-#define AFIO_EXTICR1_EXTI1              (0xF << 4)
-#define AFIO_EXTICR1_EXTI1_PA           (0x0 << 4)
-#define AFIO_EXTICR1_EXTI1_PB           (0x1 << 4)
-#define AFIO_EXTICR1_EXTI1_PC           (0x2 << 4)
-#define AFIO_EXTICR1_EXTI1_PD           (0x3 << 4)
-#define AFIO_EXTICR1_EXTI1_PE           (0x4 << 4)
-#define AFIO_EXTICR1_EXTI1_PF           (0x5 << 4)
-#define AFIO_EXTICR1_EXTI1_PG           (0x6 << 4)
-#define AFIO_EXTICR1_EXTI0              0xF
-#define AFIO_EXTICR1_EXTI0_PA           0x0
-#define AFIO_EXTICR1_EXTI0_PB           0x1
-#define AFIO_EXTICR1_EXTI0_PC           0x2
-#define AFIO_EXTICR1_EXTI0_PD           0x3
-#define AFIO_EXTICR1_EXTI0_PE           0x4
-#define AFIO_EXTICR1_EXTI0_PF           0x5
-#define AFIO_EXTICR1_EXTI0_PG           0x6
-
-/* External interrupt configuration register 2 */
-
-#define AFIO_EXTICR2_EXTI7              (0xF << 12)
-#define AFIO_EXTICR2_EXTI7_PA           (0x0 << 12)
-#define AFIO_EXTICR2_EXTI7_PB           (0x1 << 12)
-#define AFIO_EXTICR2_EXTI7_PC           (0x2 << 12)
-#define AFIO_EXTICR2_EXTI7_PD           (0x3 << 12)
-#define AFIO_EXTICR2_EXTI7_PE           (0x4 << 12)
-#define AFIO_EXTICR2_EXTI7_PF           (0x5 << 12)
-#define AFIO_EXTICR2_EXTI7_PG           (0x6 << 12)
-#define AFIO_EXTICR2_EXTI6              (0xF << 8)
-#define AFIO_EXTICR2_EXTI6_PA           (0x0 << 8)
-#define AFIO_EXTICR2_EXTI6_PB           (0x1 << 8)
-#define AFIO_EXTICR2_EXTI6_PC           (0x2 << 8)
-#define AFIO_EXTICR2_EXTI6_PD           (0x3 << 8)
-#define AFIO_EXTICR2_EXTI6_PE           (0x4 << 8)
-#define AFIO_EXTICR2_EXTI6_PF           (0x5 << 8)
-#define AFIO_EXTICR2_EXTI6_PG           (0x6 << 8)
-#define AFIO_EXTICR2_EXTI5              (0xF << 4)
-#define AFIO_EXTICR2_EXTI5_PA           (0x0 << 4)
-#define AFIO_EXTICR2_EXTI5_PB           (0x1 << 4)
-#define AFIO_EXTICR2_EXTI5_PC           (0x2 << 4)
-#define AFIO_EXTICR2_EXTI5_PD           (0x3 << 4)
-#define AFIO_EXTICR2_EXTI5_PE           (0x4 << 4)
-#define AFIO_EXTICR2_EXTI5_PF           (0x5 << 4)
-#define AFIO_EXTICR2_EXTI5_PG           (0x6 << 4)
-#define AFIO_EXTICR2_EXTI4              0xF
-#define AFIO_EXTICR2_EXTI4_PA           0x0
-#define AFIO_EXTICR2_EXTI4_PB           0x1
-#define AFIO_EXTICR2_EXTI4_PC           0x2
-#define AFIO_EXTICR2_EXTI4_PD           0x3
-#define AFIO_EXTICR2_EXTI4_PE           0x4
-#define AFIO_EXTICR2_EXTI4_PF           0x5
-#define AFIO_EXTICR2_EXTI4_PG           0x6
-
-/* AF remap and debug I/O configuration register 2 */
-
-#define AFIO_MAPR2_FSMC_NADV            BIT(10)
-#define AFIO_MAPR2_TIM14_REMAP          BIT(9)
-#define AFIO_MAPR2_TIM13_REMAP          BIT(8)
-#define AFIO_MAPR2_TIM11_REMAP          BIT(7)
-#define AFIO_MAPR2_TIM10_REMAP          BIT(6)
-#define AFIO_MAPR2_TIM9_REMAP           BIT(5)
-
-/*
- * AFIO convenience routines
- */
-
-void afio_init(void);
-
-/**
- * External interrupt line numbers.
- */
-typedef enum afio_exti_num {
-    AFIO_EXTI_0,                /**< External interrupt line 0. */
-    AFIO_EXTI_1,                /**< External interrupt line 1. */
-    AFIO_EXTI_2,                /**< External interrupt line 2. */
-    AFIO_EXTI_3,                /**< External interrupt line 3. */
-    AFIO_EXTI_4,                /**< External interrupt line 4. */
-    AFIO_EXTI_5,                /**< External interrupt line 5. */
-    AFIO_EXTI_6,                /**< External interrupt line 6. */
-    AFIO_EXTI_7,                /**< External interrupt line 7. */
-    AFIO_EXTI_8,                /**< External interrupt line 8. */
-    AFIO_EXTI_9,                /**< External interrupt line 9. */
-    AFIO_EXTI_10,               /**< External interrupt line 10. */
-    AFIO_EXTI_11,               /**< External interrupt line 11. */
-    AFIO_EXTI_12,               /**< External interrupt line 12. */
-    AFIO_EXTI_13,               /**< External interrupt line 13. */
-    AFIO_EXTI_14,               /**< External interrupt line 14. */
-    AFIO_EXTI_15,               /**< External interrupt line 15. */
-} afio_exti_num;
-
-void afio_exti_select(afio_exti_num exti, afio_exti_port gpio_port);
-
-/* HACK: Use upper bit to denote MAPR2, Bit 31 is reserved and
- * not used in either MAPR or MAPR2 */
-#define AFIO_REMAP_USE_MAPR2            (1 << 31)
-
-/**
- * @brief Available peripheral remaps.
- * @see afio_remap()
- */
-typedef enum afio_remap_peripheral {
-    AFIO_REMAP_ADC2_ETRGREG  = AFIO_MAPR_ADC2_ETRGREG_REMAP, /**<
-        ADC 2 external trigger regular conversion remapping */
-    AFIO_REMAP_ADC2_ETRGINJ  = AFIO_MAPR_ADC2_ETRGINJ_REMAP, /**<
-        ADC 2 external trigger injected conversion remapping */
-    AFIO_REMAP_ADC1_ETRGREG  = AFIO_MAPR_ADC1_ETRGREG_REMAP, /**<
-        ADC 1 external trigger regular conversion remapping */
-    AFIO_REMAP_ADC1_ETRGINJ  = AFIO_MAPR_ADC1_ETRGINJ_REMAP, /**<
-        ADC 1 external trigger injected conversion remapping */
-    AFIO_REMAP_TIM5CH4_I     = AFIO_MAPR_TIM5CH4_IREMAP, /**<
-        Timer 5 channel 4 internal remapping */
-    AFIO_REMAP_PD01          = AFIO_MAPR_PD01_REMAP, /**<
-        Port D0/Port D1 mapping on OSC_IN/OSC_OUT */
-    AFIO_REMAP_CAN_1         = AFIO_MAPR_CAN_REMAP_PB8_PB9, /**<
-        CAN alternate function remapping 1 (RX on PB8, TX on PB9) */
-    AFIO_REMAP_CAN_2         = AFIO_MAPR_CAN_REMAP_PD0_PD1, /**<
-        CAN alternate function remapping 2 (RX on PD0, TX on PD1) */
-    AFIO_REMAP_TIM4          = AFIO_MAPR_TIM4_REMAP, /**<
-        Timer 4 remapping */
-    AFIO_REMAP_TIM3_PARTIAL  = AFIO_MAPR_TIM3_REMAP_PARTIAL, /**<
-        Timer 3 partial remapping */
-    AFIO_REMAP_TIM3_FULL      = AFIO_MAPR_TIM3_REMAP_FULL, /**<
-        Timer 3 full remapping */
-    AFIO_REMAP_TIM2_PARTIAL_1 = AFIO_MAPR_TIM2_REMAP_PA15_PB3_PA2_PA3, /**<
-        Timer 2 partial remapping 1 (CH1 and ETR on PA15, CH2 on PB3, CH3
-        on PA2, CH4 on PA3) */
-    AFIO_REMAP_TIM2_PARTIAL_2 = AFIO_MAPR_TIM2_REMAP_PA0_PA1_PB10_PB11, /**<
-        Timer 2 partial remapping 2 (CH1 and ETR on PA0, CH2 on PA1, CH3
-        on PB10, CH4 on PB11) */
-    AFIO_REMAP_TIM2_FULL      = AFIO_MAPR_TIM2_REMAP_FULL, /**<
-        Timer 2 full remapping */
-    AFIO_REMAP_USART2        = AFIO_MAPR_USART2_REMAP, /**<
-        USART 2 remapping */
-    AFIO_REMAP_USART1        = AFIO_MAPR_USART1_REMAP, /**<
-        USART 1 remapping */
-    AFIO_REMAP_I2C1          = AFIO_MAPR_I2C1_REMAP, /**<
-        I2C 1 remapping */
-    AFIO_REMAP_SPI1          = AFIO_MAPR_SPI1_REMAP, /**<
-        SPI 1 remapping */
-    AFIO_REMAP_FSMC_NADV     = (AFIO_MAPR2_FSMC_NADV |
-                                AFIO_REMAP_USE_MAPR2), /**<
-        NADV signal not connected */
-    AFIO_REMAP_TIM14         = (AFIO_MAPR2_TIM14_REMAP |
-                                AFIO_REMAP_USE_MAPR2), /**<
-        Timer 14 remapping */
-    AFIO_REMAP_TIM13         = (AFIO_MAPR2_TIM13_REMAP |
-                                AFIO_REMAP_USE_MAPR2), /**<
-        Timer 13 remapping */
-    AFIO_REMAP_TIM11         = (AFIO_MAPR2_TIM11_REMAP |
-                                AFIO_REMAP_USE_MAPR2), /**<
-        Timer 11 remapping */
-    AFIO_REMAP_TIM10         = (AFIO_MAPR2_TIM10_REMAP |
-                                AFIO_REMAP_USE_MAPR2), /**<
-        Timer 10 remapping */
-    AFIO_REMAP_TIM9          = (AFIO_MAPR2_TIM9_REMAP |
-                                AFIO_REMAP_USE_MAPR2) /**<
-        Timer 9 */
-} afio_remap_peripheral;
-
-void afio_remap(afio_remap_peripheral p);
-
-/**
- * @brief Debug port configuration
- *
- * Used to configure the behavior of JTAG and Serial Wire (SW) debug
- * ports and their associated GPIO pins.
- *
- * @see afio_cfg_debug_ports()
- */
-typedef enum afio_debug_cfg {
-    AFIO_DEBUG_FULL_SWJ = AFIO_MAPR_SWJ_CFG_FULL_SWJ, /**<
-                                   Full Serial Wire and JTAG debug */
-    AFIO_DEBUG_FULL_SWJ_NO_NJRST = AFIO_MAPR_SWJ_CFG_FULL_SWJ_NO_NJRST, /**<
-                                   Full Serial Wire and JTAG, but no NJTRST. */
-    AFIO_DEBUG_SW_ONLY = AFIO_MAPR_SWJ_CFG_NO_JTAG_SW, /**<
-                                   Serial Wire debug only (JTAG-DP disabled,
-                                   SW-DP enabled) */
-    AFIO_DEBUG_NONE = AFIO_MAPR_SWJ_CFG_NO_JTAG_NO_SW /**<
-                                   No debug; all JTAG and SW pins are free
-                                   for use as GPIOs. */
-} afio_debug_cfg;
-
-/**
- * @brief Enable or disable the JTAG and SW debug ports.
- * @param config Desired debug port configuration
- * @see afio_debug_cfg
- */
-static inline void afio_cfg_debug_ports(afio_debug_cfg config) {
-    __io uint32 *mapr = &AFIO_BASE->MAPR;
-    *mapr = (*mapr & ~AFIO_MAPR_SWJ_CFG) | config;
-}
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
-
diff --git a/STM32F4/cores/maple/libmaple/gpioF2.c b/STM32F4/cores/maple/libmaple/gpioF4.c
similarity index 75%
rename from STM32F4/cores/maple/libmaple/gpioF2.c
rename to STM32F4/cores/maple/libmaple/gpioF4.c
index b04c7e9d6..af839ebea 100644
--- a/STM32F4/cores/maple/libmaple/gpioF2.c
+++ b/STM32F4/cores/maple/libmaple/gpioF4.c
@@ -24,8 +24,6 @@
  * SOFTWARE.
  *****************************************************************************/
 
- #ifdef STM32F2
- 
 /**
  * @file gpio.c
  * @brief GPIO initialization routine
@@ -38,62 +36,57 @@
  * GPIO devices
  */
 
-gpio_dev gpioa = {
+/** GPIO port A device. */
+const gpio_dev GPIOA = {
     .regs      = GPIOA_BASE,
     .clk_id    = RCC_GPIOA,
     .exti_port = AFIO_EXTI_PA,
 };
-/** GPIO port A device. */
-gpio_dev* const GPIOA = &gpioa;
 
-gpio_dev gpiob = {
+/** GPIO port B device. */
+const gpio_dev GPIOB = {
     .regs      = GPIOB_BASE,
     .clk_id    = RCC_GPIOB,
     .exti_port = AFIO_EXTI_PB,
 };
-/** GPIO port B device. */
-gpio_dev* const GPIOB = &gpiob;
 
-gpio_dev gpioc = {
+/** GPIO port C device. */
+const gpio_dev GPIOC = {
     .regs      = GPIOC_BASE,
     .clk_id    = RCC_GPIOC,
     .exti_port = AFIO_EXTI_PC,
 };
-/** GPIO port C device. */
-gpio_dev* const GPIOC = &gpioc;
 
-gpio_dev gpiod = {
+/** GPIO port D device. */
+const gpio_dev GPIOD = {
     .regs      = GPIOD_BASE,
     .clk_id    = RCC_GPIOD,
     .exti_port = AFIO_EXTI_PD,
 };
-/** GPIO port D device. */
-gpio_dev* const GPIOD = &gpiod;
 
 #ifdef STM32_HIGH_DENSITY
-gpio_dev gpioe = {
+/** GPIO port E device. */
+const gpio_dev GPIOE = {
     .regs      = GPIOE_BASE,
     .clk_id    = RCC_GPIOE,
     .exti_port = AFIO_EXTI_PE,
 };
-/** GPIO port E device. */
-gpio_dev* const GPIOE = &gpioe;
 
-gpio_dev gpiof = {
+ #if 0 // not available on LQFP 100 package
+/** GPIO port F device. */
+const gpio_dev GPIOF = {
     .regs      = GPIOF_BASE,
     .clk_id    = RCC_GPIOF,
     .exti_port = AFIO_EXTI_PF,
 };
-/** GPIO port F device. */
-gpio_dev* const GPIOF = &gpiof;
 
-gpio_dev gpiog = {
+/** GPIO port G device. */
+const gpio_dev GPIOG = {
     .regs      = GPIOG_BASE,
     .clk_id    = RCC_GPIOG,
     .exti_port = AFIO_EXTI_PG,
 };
-/** GPIO port G device. */
-gpio_dev* const GPIOG = &gpiog;
+#endif
 #endif
 
 /*
@@ -107,7 +100,7 @@ gpio_dev* const GPIOG = &gpiog;
  *
  * @param dev GPIO device to initialize.
  */
-void gpio_init(gpio_dev *dev) {
+void gpio_init(const gpio_dev *dev) {
     rcc_clk_enable(dev->clk_id);
     rcc_reset_dev(dev->clk_id);
 }
@@ -116,27 +109,29 @@ void gpio_init(gpio_dev *dev) {
  * Initialize and reset all available GPIO devices.
  */
 void gpio_init_all(void) {
-    gpio_init(GPIOA);
-    gpio_init(GPIOB);
-    gpio_init(GPIOC);
-    gpio_init(GPIOD);
+    gpio_init(&GPIOA);
+    gpio_init(&GPIOB);
+    gpio_init(&GPIOC);
+    gpio_init(&GPIOD);
 
 #ifdef STM32_HIGH_DENSITY
-    gpio_init(GPIOE);
-    gpio_init(GPIOF);
-    gpio_init(GPIOG);
+	gpio_init(&GPIOE);
+  #if 0 // not available on LQFP 100 package
+	gpio_init(GPIOF);
+	gpio_init(GPIOG);
+  #endif // not available on LQFP 100 package
 #endif
 
 #ifdef ARDUINO_STM32F4_NETDUINO2PLUS
     // PA8 Output the Master Clock MCO1
-    gpio_set_af_mode(GPIOA, 8, 0);
-    gpio_set_mode(GPIOA, 8, GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
+    gpio_set_af_mode(PA8, 0);
+    gpio_set_mode(PA8, GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
     // PB4 as alternate MISO Input
-    gpio_set_af_mode(GPIOB, 4, 5);
+    gpio_set_af_mode(PB4, 5);
     // PA5 as alternate SCK Output
-    gpio_set_af_mode(GPIOA, 5, 5);
+    gpio_set_af_mode(PA5, 5);
     // PA7 as alternate MOSI Output
-    gpio_set_af_mode(GPIOA, 7, 5);
+    gpio_set_af_mode(PA7, 5);
 #endif
 }
 
@@ -148,16 +143,17 @@ void gpio_init_all(void) {
  * @param mode General purpose or alternate function mode to set the pin to.
  * @see gpio_pin_mode
  */
-void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode) {
-    gpio_reg_map *regs = dev->regs;
+void gpio_set_mode(uint8_t io_pin, gpio_pin_mode mode) {
+    gpio_reg_map *regs = (PIN_MAP[io_pin].gpio_device)->regs;
+	uint8_t pin = io_pin&0x0f;
 
 	//regs->AFR[pin/8] = (regs->AFR[pin/8] & ~(15 << (4*(pin&7)))) | (((mode >> 8) & 15) << (4*(pin&7)));
 	//gpio_set_af_mode(dev, pin, mode>>8);
 
-    regs->MODER      = (regs->MODER      & ~( 3 << (2*pin)))     | (((mode >> 0) & 3)  << (2*pin));
-    regs->PUPDR      = (regs->PUPDR      & ~( 3 << (2*pin)))     | (((mode >> 2) & 3)  << (2*pin));
-    regs->OSPEEDR    = (regs->OSPEEDR    & ~( 3 << (2*pin)))     | (((mode >> 4) & 3)  << (2*pin));
-    regs->OTYPER     = (regs->OTYPER     & ~( 1 << (1*pin)))     | (((mode >> 6) & 1)  << (1*pin));
+    regs->MODER      = (regs->MODER      & ~( 3 << (pin<<1)))     | (((mode >> 0) & 3)  << (pin<<1));
+    regs->PUPDR      = (regs->PUPDR      & ~( 3 << (pin<<1)))     | (((mode >> 2) & 3)  << (pin<<1));
+    regs->OSPEEDR    = (regs->OSPEEDR    & ~( 3 << (pin<<1)))     | (((mode >> 4) & 3)  << (pin<<1));
+    regs->OTYPER     = (regs->OTYPER     & ~( 1 << (pin<<0)))     | (((mode >> 6) & 1)  << (pin<<0));
 }
 
 /**
@@ -168,10 +164,11 @@ void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode) {
  * @param mode alternate function mode to set the pin to.
  * @see gpio_pin_mode
  */
-void gpio_set_af_mode(gpio_dev *dev, uint8 pin, int mode) {
-    gpio_reg_map *regs = dev->regs;
+void gpio_set_af_mode(uint8_t io_pin, int mode) {
+    gpio_reg_map *regs = (PIN_MAP[io_pin].gpio_device)->regs;
+	uint8_t pin = io_pin&0x0F;
 
-	regs->AFR[pin/8] = (regs->AFR[pin/8] & ~(15 << (4*(pin&7)))) | (((mode >> 0) & 15) << (4*(pin&7)));
+	regs->AFR[pin>>3] = (regs->AFR[pin>>3] & ~(15 << ((pin&7)<<2))) | (((mode >> 0) & 15) << ((pin&7)<<2));
 }
 
 /*
@@ -220,5 +217,3 @@ void afio_remap(afio_remap_peripheral remapping) {
     }
 }
 #endif
-
-#endif
diff --git a/STM32F4/cores/maple/libmaple/gpioF2.h b/STM32F4/cores/maple/libmaple/gpio_def.h
similarity index 90%
rename from STM32F4/cores/maple/libmaple/gpioF2.h
rename to STM32F4/cores/maple/libmaple/gpio_def.h
index 91bd67be3..cd1fb3843 100644
--- a/STM32F4/cores/maple/libmaple/gpioF2.h
+++ b/STM32F4/cores/maple/libmaple/gpio_def.h
@@ -31,8 +31,8 @@
  *         (AFIO) prototypes, defines, and inlined access functions.
  */
 
-#ifndef _GPIO_H_
-#define _GPIO_H_
+#ifndef _GPIO_DEF_H_
+#define _GPIO_DEF_H_
 
 #include "libmaple.h"
 #include "rcc.h"
@@ -74,11 +74,14 @@ typedef enum afio_exti_port {
     AFIO_EXTI_PD,               /**< Use port D (PDx) pin. */
 #ifdef STM32_HIGH_DENSITY
     AFIO_EXTI_PE,               /**< Use port E (PEx) pin. */
+ #if 0 // not available on LQFP 100 package
     AFIO_EXTI_PF,               /**< Use port F (PFx) pin. */
     AFIO_EXTI_PG,               /**< Use port G (PGx) pin. */
+ #endif // not available on LQFP 100 package
 #endif
 } afio_exti_port;
 
+
 /** GPIO device type */
 typedef struct gpio_dev {
     gpio_reg_map *regs;       /**< Register map */
@@ -86,21 +89,18 @@ typedef struct gpio_dev {
     afio_exti_port exti_port; /**< AFIO external interrupt port value */
 } gpio_dev;
 
-extern gpio_dev gpioa;
-extern gpio_dev* const GPIOA;
-extern gpio_dev gpiob;
-extern gpio_dev* const GPIOB;
-extern gpio_dev gpioc;
-extern gpio_dev* const GPIOC;
-extern gpio_dev gpiod;
-extern gpio_dev* const GPIOD;
+extern const gpio_dev GPIOA;
+extern const gpio_dev GPIOB;
+extern const gpio_dev GPIOC;
+extern const gpio_dev GPIOD;
 #ifdef STM32_HIGH_DENSITY
-extern gpio_dev gpioe;
-extern gpio_dev* const GPIOE;
+extern const gpio_dev GPIOE;
+ #if 0 // not available on LQFP 100 package
 extern gpio_dev gpiof;
 extern gpio_dev* const GPIOF;
 extern gpio_dev gpiog;
 extern gpio_dev* const GPIOG;
+ #endif // not available on LQFP 100 package
 #endif
 
 /** GPIO port register map base pointer */
@@ -110,8 +110,10 @@ extern gpio_dev* const GPIOG;
 #define GPIOD_BASE                      ((struct gpio_reg_map*)0x40020C00)
 #ifdef STM32_HIGH_DENSITY
 #define GPIOE_BASE                      ((struct gpio_reg_map*)0x40021000)
+ #if 0 // not available on LQFP 100 package
 #define GPIOF_BASE                      ((struct gpio_reg_map*)0x40021400)
 #define GPIOG_BASE                      ((struct gpio_reg_map*)0x40021800)
+ #endif // not available on LQFP 100 package
 #endif
 
 /*
@@ -190,61 +192,6 @@ typedef enum gpio_pin_mode {
 	GPIO_BIGNUMBER = 0xfff
 } gpio_pin_mode;
 
-/*
- * GPIO Convenience routines
- */
-
-void gpio_init(gpio_dev *dev);
-void gpio_init_all(void);
-void gpio_set_mode(gpio_dev *dev, uint8 pin, gpio_pin_mode mode);
-void gpio_set_af_mode(gpio_dev *dev, uint8 pin, int mode);
-
-/**
- * @brief Get a GPIO port's corresponding afio_exti_port.
- * @param dev GPIO device whose afio_exti_port to return.
- */
-static inline afio_exti_port gpio_exti_port(gpio_dev *dev) {
-    return dev->exti_port;
-}
-
-/**
- * Set or reset a GPIO pin.
- *
- * Pin must have previously been configured to output mode.
- *
- * @param dev GPIO device whose pin to set.
- * @param pin Pin on to set or reset
- * @param val If true, set the pin.  If false, reset the pin.
- */
-static inline void gpio_write_bit(gpio_dev *dev, uint8 pin, uint8 val) {
-    if (val) {
-        dev->regs->BSRRL = BIT(pin);
-    } else {
-        dev->regs->BSRRH = BIT(pin);
-    }
-}
-
-/**
- * Determine whether or not a GPIO pin is set.
- *
- * Pin must have previously been configured to input mode.
- *
- * @param dev GPIO device whose pin to test.
- * @param pin Pin on dev to test.
- * @return True if the pin is set, false otherwise.
- */
-static inline uint32 gpio_read_bit(gpio_dev *dev, uint8 pin) {
-    return dev->regs->IDR & BIT(pin);
-}
-
-/**
- * Toggle a pin configured as output push-pull.
- * @param dev GPIO device.
- * @param pin Pin on dev to toggle.
- */
-static inline void gpio_toggle_bit(gpio_dev *dev, uint8 pin) {
-    dev->regs->ODR = dev->regs->ODR ^ BIT(pin);
-}
 
 /*
  * AFIO register map
@@ -532,15 +479,6 @@ typedef enum afio_debug_cfg {
                                    for use as GPIOs. */
 } afio_debug_cfg;
 
-/**
- * @brief Enable or disable the JTAG and SW debug ports.
- * @param config Desired debug port configuration
- * @see afio_debug_cfg
- */
-static inline void afio_cfg_debug_ports(afio_debug_cfg config) {
-    //__io uint32 *mapr = &AFIO_BASE->MAPR;
-    //*mapr = (*mapr & ~AFIO_MAPR_SWJ_CFG) | config;
-}
 
 #ifdef __cplusplus
 }
diff --git a/STM32F4/cores/maple/libmaple/i2c.c b/STM32F4/cores/maple/libmaple/i2c.c
index e3f3199bc..a582ed056 100644
--- a/STM32F4/cores/maple/libmaple/i2c.c
+++ b/STM32F4/cores/maple/libmaple/i2c.c
@@ -41,9 +41,9 @@
 
 static i2c_dev i2c_dev1 = {
     .regs         = I2C1_BASE,
-    .gpio_port    = &gpiob,
-    .sda_pin      = 7,
-    .scl_pin      = 6,
+    //.gpio_port    = &gpiob,
+    .sda_pin      = PB7,
+    .scl_pin      = PB6,
     .clk_id       = RCC_I2C1,
     .ev_nvic_line = NVIC_I2C1_EV,
     .er_nvic_line = NVIC_I2C1_ER,
@@ -54,9 +54,9 @@ i2c_dev* const I2C1 = &i2c_dev1;
 
 static i2c_dev i2c_dev2 = {
     .regs         = I2C2_BASE,
-    .gpio_port    = &gpiob,
-    .sda_pin      = 11,
-    .scl_pin      = 10,
+    //.gpio_port    = &gpiob,
+    .sda_pin      = PB11,
+    .scl_pin      = PB10,
     .clk_id       = RCC_I2C2,
     .ev_nvic_line = NVIC_I2C2_EV,
     .er_nvic_line = NVIC_I2C2_ER,
@@ -336,38 +336,38 @@ void __irq_i2c2_er(void) {
  */
 void i2c_bus_reset(const i2c_dev *dev) {
     /* Release both lines */
-    gpio_write_bit(dev->gpio_port, dev->scl_pin, 1);
-    gpio_write_bit(dev->gpio_port, dev->sda_pin, 1);
-    gpio_set_mode(dev->gpio_port, dev->scl_pin, GPIO_OUTPUT_OD);
-    gpio_set_mode(dev->gpio_port, dev->sda_pin, GPIO_OUTPUT_OD);
+    gpio_set_pin(dev->scl_pin);
+    gpio_set_pin(dev->sda_pin);
+    gpio_set_mode(dev->scl_pin, GPIO_OUTPUT_OD);
+    gpio_set_mode(dev->sda_pin, GPIO_OUTPUT_OD);
 
     /*
      * Make sure the bus is free by clocking it until any slaves release the
      * bus.
      */
-    while (!gpio_read_bit(dev->gpio_port, dev->sda_pin)) {
+    while (!gpio_read_pin(dev->sda_pin)) {
         /* Wait for any clock stretching to finish */
-        while (!gpio_read_bit(dev->gpio_port, dev->scl_pin))
+        while (!gpio_read_pin(dev->scl_pin))
             ;
         delay_us(10);
 
         /* Pull low */
-        gpio_write_bit(dev->gpio_port, dev->scl_pin, 0);
+        gpio_clear_pin(dev->scl_pin);
         delay_us(10);
 
         /* Release high again */
-        gpio_write_bit(dev->gpio_port, dev->scl_pin, 1);
+        gpio_set_pin(dev->scl_pin);
         delay_us(10);
     }
 
     /* Generate start then stop condition */
-    gpio_write_bit(dev->gpio_port, dev->sda_pin, 0);
+    gpio_clear_pin(dev->sda_pin);
     delay_us(10);
-    gpio_write_bit(dev->gpio_port, dev->scl_pin, 0);
+    gpio_clear_pin(dev->scl_pin);
     delay_us(10);
-    gpio_write_bit(dev->gpio_port, dev->scl_pin, 1);
+    gpio_set_pin(dev->scl_pin);
     delay_us(10);
-    gpio_write_bit(dev->gpio_port, dev->sda_pin, 1);
+    gpio_set_pin(dev->sda_pin);
 }
 
 /**
@@ -413,8 +413,8 @@ void i2c_master_enable(i2c_dev *dev, uint32 flags) {
 
     /* Turn on clock and set GPIO modes */
     i2c_init(dev);
-    gpio_set_mode(dev->gpio_port, dev->sda_pin, GPIO_AF_OUTPUT_OD);
-    gpio_set_mode(dev->gpio_port, dev->scl_pin, GPIO_AF_OUTPUT_OD);
+    gpio_set_mode(dev->sda_pin, GPIO_AF_OUTPUT_OD);
+    gpio_set_mode(dev->scl_pin, GPIO_AF_OUTPUT_OD);
 
     /* I2C1 and I2C2 are fed from APB1, clocked at 36MHz */
     i2c_set_input_clk(dev, I2C_CLK);
diff --git a/STM32F4/cores/maple/libmaple/i2c.h b/STM32F4/cores/maple/libmaple/i2c.h
index 4c60ad713..28819a35b 100644
--- a/STM32F4/cores/maple/libmaple/i2c.h
+++ b/STM32F4/cores/maple/libmaple/i2c.h
@@ -78,7 +78,7 @@ typedef struct i2c_msg {
  */
 typedef struct i2c_dev {
     i2c_reg_map *regs;          /**< Register map */
-    gpio_dev *gpio_port;        /**< SDA, SCL pins' GPIO port */
+    //gpio_dev *gpio_port;        /**< SDA, SCL pins' GPIO port */
     uint8 sda_pin;              /**< SDA bit on gpio_port */
     uint8 scl_pin;              /**< SCL bit on gpio_port */
     rcc_clk_id clk_id;          /**< RCC clock information */
diff --git a/STM32F4/cores/maple/libmaple/libmaple.h b/STM32F4/cores/maple/libmaple/libmaple.h
index 10c6c0c00..8360ba390 100644
--- a/STM32F4/cores/maple/libmaple/libmaple.h
+++ b/STM32F4/cores/maple/libmaple/libmaple.h
@@ -32,29 +32,31 @@
 #ifndef _LIBMAPLE_H_
 #define _LIBMAPLE_H_
 
-#include "libmaple_types.h"
-#include "stm32.h"
 #include "util.h"
-#include "delay.h"
 
 /*
  * Where to put usercode, based on space reserved for bootloader.
  *
  * FIXME this has no business being here
  */
+/*
 #if defined(MCU_STM32F103VE) || defined(MCU_STM32F205VE) || defined(MCU_STM32F406VG)
-    /* e.g., Aeroquad32 */
-    #define USER_ADDR_ROM 0x08010000    /* ala42 */
+    // e.g., Aeroquad32
+    #define USER_ADDR_ROM 0x08010000    // ala42
     #define USER_ADDR_RAM 0x20000C00
     #define STACK_TOP     0x20000800
 #elif defined(BOARD_freeflight)
+*/
 #define USER_ADDR_ROM 0x08000000
-#define USER_ADDR_RAM 0x20000000
+#define USER_ADDR_RAM 0x20000C00
 #define STACK_TOP     0x20000800
+/*
 #else
 #define USER_ADDR_ROM 0x08005000
 #define USER_ADDR_RAM 0x20000C00
 #define STACK_TOP     0x20000800
 #endif
+*/
+
 #endif
 
diff --git a/STM32F4/cores/maple/libmaple/libmaple_types.h b/STM32F4/cores/maple/libmaple/libmaple_types.h
index 332ded176..8e765b435 100644
--- a/STM32F4/cores/maple/libmaple/libmaple_types.h
+++ b/STM32F4/cores/maple/libmaple/libmaple_types.h
@@ -33,6 +33,8 @@
 #ifndef _LIBMAPLE_TYPES_H_
 #define _LIBMAPLE_TYPES_H_
 
+#include <inttypes.h>
+
 typedef unsigned char uint8;
 typedef unsigned short uint16;
 typedef unsigned int uint32;
@@ -46,12 +48,15 @@ typedef long long int64;
 typedef void (*voidFuncPtr)(void);
 
 #define __io volatile
-#define __attr_flash __attribute__((section (".USER_FLASH")))
-
-#define __always_inline inline __attribute__((always_inline))
-
+#define __IO volatile
+#ifndef __attr_flash
+  #define __attr_flash __attribute__((section (".USER_FLASH")))
+#endif
+#ifndef __always_inline
+  #define __always_inline inline __attribute__((always_inline))
+#endif
 #ifndef NULL
-#define NULL 0
+  #define NULL 0
 #endif
 
 #endif
diff --git a/STM32F4/cores/maple/libmaple/rcc.h b/STM32F4/cores/maple/libmaple/rcc.h
index 6317cbdb8..75e2d3d7a 100644
--- a/STM32F4/cores/maple/libmaple/rcc.h
+++ b/STM32F4/cores/maple/libmaple/rcc.h
@@ -29,8 +29,5 @@
  * @brief reset and clock control definitions and prototypes
  */
 
-#ifdef STM32F2
-#include "rccF2.h"
-#else
-#include "rccF1.h"
-#endif
+
+#include "rccF4.h"
diff --git a/STM32F4/cores/maple/libmaple/rccF1.c b/STM32F4/cores/maple/libmaple/rccF1.c
deleted file mode 100644
index 9eb56b872..000000000
--- a/STM32F4/cores/maple/libmaple/rccF1.c
+++ /dev/null
@@ -1,233 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
- #ifdef STM32F1
- 
-/**
- * @file rcc.c
- * @brief Implements pretty much only the basic clock setup on the
- *        stm32, clock enable/disable and peripheral reset commands.
- */
-
-#include "libmaple.h"
-#include "flash.h"
-#include "rcc.h"
-#include "bitband.h"
-
-#define APB1                            RCC_APB1
-#define APB2                            RCC_APB2
-#define AHB                             RCC_AHB
-
-struct rcc_dev_info {
-    const rcc_clk_domain clk_domain;
-    const uint8 line_num;
-};
-
-/* Device descriptor table, maps rcc_clk_id onto bus and enable/reset
- * register bit numbers. */
-static const struct rcc_dev_info rcc_dev_table[] = {
-    [RCC_GPIOA]  = { .clk_domain = APB2, .line_num = 2 },
-    [RCC_GPIOB]  = { .clk_domain = APB2, .line_num = 3 },
-    [RCC_GPIOC]  = { .clk_domain = APB2, .line_num = 4 },
-    [RCC_GPIOD]  = { .clk_domain = APB2, .line_num = 5 },
-    [RCC_AFIO]   = { .clk_domain = APB2, .line_num = 0 },
-    [RCC_ADC1]   = { .clk_domain = APB2, .line_num = 9 },
-    [RCC_ADC2]   = { .clk_domain = APB2, .line_num = 10 },
-    [RCC_ADC3]   = { .clk_domain = APB2, .line_num = 15 },
-    [RCC_USART1] = { .clk_domain = APB2, .line_num = 14 },
-    [RCC_USART2] = { .clk_domain = APB1, .line_num = 17 },
-    [RCC_USART3] = { .clk_domain = APB1, .line_num = 18 },
-    [RCC_TIMER1] = { .clk_domain = APB2, .line_num = 11 },
-    [RCC_TIMER2] = { .clk_domain = APB1, .line_num = 0 },
-    [RCC_TIMER3] = { .clk_domain = APB1, .line_num = 1 },
-    [RCC_TIMER4] = { .clk_domain = APB1, .line_num = 2 },
-    [RCC_SPI1]   = { .clk_domain = APB2, .line_num = 12 },
-    [RCC_SPI2]   = { .clk_domain = APB1, .line_num = 14 },
-    [RCC_DMA1]   = { .clk_domain = AHB,  .line_num = 0 },
-    [RCC_PWR]    = { .clk_domain = APB1, .line_num = 28},
-    [RCC_BKP]    = { .clk_domain = APB1, .line_num = 27},
-    [RCC_I2C1]   = { .clk_domain = APB1, .line_num = 21 },
-    [RCC_I2C2]   = { .clk_domain = APB1, .line_num = 22 },
-    [RCC_CRC]    = { .clk_domain = AHB,  .line_num = 6},
-    [RCC_FLITF]  = { .clk_domain = AHB,  .line_num = 4},
-    [RCC_SRAM]   = { .clk_domain = AHB,  .line_num = 2},
-#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
-    [RCC_GPIOE]  = { .clk_domain = APB2, .line_num = 6 },
-    [RCC_GPIOF]  = { .clk_domain = APB2, .line_num = 7 },
-    [RCC_GPIOG]  = { .clk_domain = APB2, .line_num = 8 },
-    [RCC_UART4]  = { .clk_domain = APB1, .line_num = 19 },
-    [RCC_UART5]  = { .clk_domain = APB1, .line_num = 20 },
-    [RCC_TIMER5] = { .clk_domain = APB1, .line_num = 3 },
-    [RCC_TIMER6] = { .clk_domain = APB1, .line_num = 4 },
-    [RCC_TIMER7] = { .clk_domain = APB1, .line_num = 5 },
-    [RCC_TIMER8] = { .clk_domain = APB2, .line_num = 13 },
-    [RCC_FSMC]   = { .clk_domain = AHB,  .line_num = 8 },
-    [RCC_DAC]    = { .clk_domain = APB1, .line_num = 29 },
-    [RCC_DMA2]   = { .clk_domain = AHB,  .line_num = 1 },
-    [RCC_SDIO]   = { .clk_domain = AHB,  .line_num = 10 },
-    [RCC_SPI3]   = { .clk_domain = APB1, .line_num = 15 },
-#endif
-#ifdef STM32_XL_DENSITY
-    [RCC_TIMER9]  = { .clk_domain = APB2, .line_num = 19 },
-    [RCC_TIMER10] = { .clk_domain = APB2, .line_num = 20 },
-    [RCC_TIMER11] = { .clk_domain = APB2, .line_num = 21 },
-    [RCC_TIMER12] = { .clk_domain = APB1, .line_num = 6 },
-    [RCC_TIMER13] = { .clk_domain = APB1, .line_num = 7 },
-    [RCC_TIMER14] = { .clk_domain = APB1, .line_num = 8 },
-#endif
-};
-
-/**
- * @brief Initialize the clock control system. Initializes the system
- *        clock source to use the PLL driven by an external oscillator
- * @param sysclk_src system clock source, must be PLL
- * @param pll_src pll clock source, must be HSE
- * @param pll_mul pll multiplier
- */
-void rcc_clk_init(rcc_sysclk_src sysclk_src,
-                  rcc_pllsrc pll_src,
-                  rcc_pll_multiplier pll_mul) {
-    uint32 cfgr = 0;
-    uint32 cr;
-
-    /* Assume that we're going to clock the chip off the PLL, fed by
-     * the HSE */
-    ASSERT(sysclk_src == RCC_CLKSRC_PLL &&
-           pll_src    == RCC_PLLSRC_HSE);
-
-    RCC_BASE->CFGR = pll_src | pll_mul;
-
-    /* Turn on the HSE */
-    cr = RCC_BASE->CR;
-    cr |= RCC_CR_HSEON;
-    RCC_BASE->CR = cr;
-    while (!(RCC_BASE->CR & RCC_CR_HSERDY))
-        ;
-
-    /* Now the PLL */
-    cr |= RCC_CR_PLLON;
-    RCC_BASE->CR = cr;
-    while (!(RCC_BASE->CR & RCC_CR_PLLRDY))
-        ;
-
-    /* Finally, let's switch over to the PLL */
-    cfgr &= ~RCC_CFGR_SW;
-    cfgr |= RCC_CFGR_SW_PLL;
-    RCC_BASE->CFGR = cfgr;
-    while ((RCC_BASE->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL)
-        ;
-}
-
-/**
- * @brief Turn on the clock line on a peripheral
- * @param id Clock ID of the peripheral to turn on.
- */
-void rcc_clk_enable(rcc_clk_id id) {
-    static const __io uint32* enable_regs[] = {
-        [APB1] = &RCC_BASE->APB1ENR,
-        [APB2] = &RCC_BASE->APB2ENR,
-        [AHB] = &RCC_BASE->AHBENR,
-    };
-
-    rcc_clk_domain clk_domain = rcc_dev_clk(id);
-    __io uint32* enr = (__io uint32*)enable_regs[clk_domain];
-    uint8 lnum = rcc_dev_table[id].line_num;
-
-    bb_peri_set_bit(enr, lnum, 1);
-}
-
-/**
- * @brief Reset a peripheral.
- * @param id Clock ID of the peripheral to reset.
- */
-void rcc_reset_dev(rcc_clk_id id) {
-    static const __io uint32* reset_regs[] = {
-        [APB1] = &RCC_BASE->APB1RSTR,
-        [APB2] = &RCC_BASE->APB2RSTR,
-    };
-
-    rcc_clk_domain clk_domain = rcc_dev_clk(id);
-    __io void* addr = (__io void*)reset_regs[clk_domain];
-    uint8 lnum = rcc_dev_table[id].line_num;
-
-    bb_peri_set_bit(addr, lnum, 1);
-    bb_peri_set_bit(addr, lnum, 0);
-}
-
-/**
- * @brief Get a peripheral's clock domain
- * @param id Clock ID of the peripheral whose clock domain to return
- * @return Clock source for the given clock ID
- */
-rcc_clk_domain rcc_dev_clk(rcc_clk_id id) {
-    return rcc_dev_table[id].clk_domain;
-}
-
-/**
- * @brief Get a peripheral's clock domain speed
- * @param id Clock ID of the peripheral whose clock domain speed to return
- * @return Clock speed for the given clock ID
- */
-uint32 rcc_dev_clk_speed(rcc_clk_id id) {
-    static const uint32 rcc_dev_clk_speed_table[] = {
-        [RCC_AHB]  = 72000000,
-        [RCC_APB1] = 36000000,
-        [RCC_APB2] = 72000000
-	  };
-    return rcc_dev_clk_speed_table[rcc_dev_clk(id)];
-}
-
-/**
- * @brief Get a peripheral's timer clock domain speed
- * @param id Clock ID of the peripheral whose clock domain speed to return
- * @return Clock speed for the given clock ID
- */
-uint32 rcc_dev_timer_clk_speed(rcc_clk_id id) {
-    return rcc_dev_clk_speed(RCC_APB2); // 72 MHz for all counter
-}
-
-/**
- * @brief Set the divider on a peripheral prescaler
- * @param prescaler prescaler to set
- * @param divider prescaler divider
- */
-void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider) {
-    static const uint32 masks[] = {
-        [RCC_PRESCALER_AHB] = RCC_CFGR_HPRE,
-        [RCC_PRESCALER_APB1] = RCC_CFGR_PPRE1,
-        [RCC_PRESCALER_APB2] = RCC_CFGR_PPRE2,
-        [RCC_PRESCALER_USB] = RCC_CFGR_USBPRE,
-        [RCC_PRESCALER_ADC] = RCC_CFGR_ADCPRE,
-    };
-
-    uint32 cfgr = RCC_BASE->CFGR;
-    cfgr &= ~masks[prescaler];
-    cfgr |= divider;
-    RCC_BASE->CFGR = cfgr;
-}
-
-
-#endif
diff --git a/STM32F4/cores/maple/libmaple/rccF1.h b/STM32F4/cores/maple/libmaple/rccF1.h
deleted file mode 100644
index dd79704d8..000000000
--- a/STM32F4/cores/maple/libmaple/rccF1.h
+++ /dev/null
@@ -1,572 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file rcc.h
- * @brief reset and clock control definitions and prototypes
- */
-
-#include "libmaple_types.h"
-
-#ifndef _RCC_H_
-#define _RCC_H_
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-/** RCC register map type */
-typedef struct rcc_reg_map {
-    __io uint32 CR;             /**< Clock control register */
-    __io uint32 CFGR;           /**< Clock configuration register */
-    __io uint32 CIR;            /**< Clock interrupt register */
-    __io uint32 APB2RSTR;       /**< APB2 peripheral reset register */
-    __io uint32 APB1RSTR;       /**< APB1 peripheral reset register */
-    __io uint32 AHBENR;         /**< AHB peripheral clock enable register */
-    __io uint32 APB2ENR;        /**< APB2 peripheral clock enable register */
-    __io uint32 APB1ENR;        /**< APB1 peripheral clock enable register */
-    __io uint32 BDCR;           /**< Backup domain control register */
-    __io uint32 CSR;            /**< Control/status register */
-} rcc_reg_map;
-
-/** RCC register map base pointer */
-#define RCC_BASE                        ((struct rcc_reg_map*)0x40021000)
-
-/*
- * Register bit definitions
- */
-
-/* Clock control register */
-
-#define RCC_CR_PLLRDY_BIT               25
-#define RCC_CR_PLLON_BIT                24
-#define RCC_CR_CSSON_BIT                19
-#define RCC_CR_HSEBYP_BIT               18
-#define RCC_CR_HSERDY_BIT               17
-#define RCC_CR_HSEON_BIT                16
-#define RCC_CR_HSIRDY_BIT               1
-#define RCC_CR_HSION_BIT                0
-
-#define RCC_CR_PLLRDY                   BIT(RCC_CR_PLLRDY_BIT)
-#define RCC_CR_PLLON                    BIT(RCC_CR_PLLON_BIT)
-#define RCC_CR_CSSON                    BIT(RCC_CR_CSSON_BIT)
-#define RCC_CR_HSEBYP                   BIT(RCC_CR_HSEBYP_BIT)
-#define RCC_CR_HSERDY                   BIT(RCC_CR_HSERDY_BIT)
-#define RCC_CR_HSEON                    BIT(RCC_CR_HSEON_BIT)
-#define RCC_CR_HSICAL                   (0xFF << 8)
-#define RCC_CR_HSITRIM                  (0x1F << 3)
-#define RCC_CR_HSIRDY                   BIT(RCC_CR_HSIRDY_BIT)
-#define RCC_CR_HSION                    BIT(RCC_CR_HSION_BIT)
-
-/* Clock configuration register */
-
-#define RCC_CFGR_USBPRE_BIT             22
-#define RCC_CFGR_PLLXTPRE_BIT           17
-#define RCC_CFGR_PLLSRC_BIT             16
-
-#define RCC_CFGR_MCO                    (0x3 << 24)
-#define RCC_CFGR_USBPRE                 BIT(RCC_CFGR_USBPRE_BIT)
-#define RCC_CFGR_PLLMUL                 (0xF << 18)
-#define RCC_CFGR_PLLXTPRE               BIT(RCC_CFGR_PLLXTPRE_BIT)
-#define RCC_CFGR_PLLSRC                 BIT(RCC_CFGR_PLLSRC_BIT)
-#define RCC_CFGR_ADCPRE                 (0x3 << 14)
-#define RCC_CFGR_PPRE2                  (0x7 << 11)
-#define RCC_CFGR_PPRE1                  (0x7 << 8)
-#define RCC_CFGR_HPRE                   (0xF << 4)
-#define RCC_CFGR_SWS                    (0x3 << 2)
-#define RCC_CFGR_SWS_PLL                (0x2 << 2)
-#define RCC_CFGR_SWS_HSE                (0x1 << 2)
-#define RCC_CFGR_SW                     0x3
-#define RCC_CFGR_SW_PLL                 0x2
-#define RCC_CFGR_SW_HSE                 0x1
-
-/* Clock interrupt register */
-
-#define RCC_CIR_CSSC_BIT                23
-#define RCC_CIR_PLLRDYC_BIT             20
-#define RCC_CIR_HSERDYC_BIT             19
-#define RCC_CIR_HSIRDYC_BIT             18
-#define RCC_CIR_LSERDYC_BIT             17
-#define RCC_CIR_LSIRDYC_BIT             16
-#define RCC_CIR_PLLRDYIE_BIT            12
-#define RCC_CIR_HSERDYIE_BIT            11
-#define RCC_CIR_HSIRDYIE_BIT            10
-#define RCC_CIR_LSERDYIE_BIT            9
-#define RCC_CIR_LSIRDYIE_BIT            8
-#define RCC_CIR_CSSF_BIT                7
-#define RCC_CIR_PLLRDYF_BIT             4
-#define RCC_CIR_HSERDYF_BIT             3
-#define RCC_CIR_HSIRDYF_BIT             2
-#define RCC_CIR_LSERDYF_BIT             1
-#define RCC_CIR_LSIRDYF_BIT             0
-
-#define RCC_CIR_CSSC                    BIT(RCC_CIR_CSSC_BIT)
-#define RCC_CIR_PLLRDYC                 BIT(RCC_CIR_PLLRDYC_BIT)
-#define RCC_CIR_HSERDYC                 BIT(RCC_CIR_HSERDYC_BIT)
-#define RCC_CIR_HSIRDYC                 BIT(RCC_CIR_HSIRDYC_BIT)
-#define RCC_CIR_LSERDYC                 BIT(RCC_CIR_LSERDYC_BIT)
-#define RCC_CIR_LSIRDYC                 BIT(RCC_CIR_LSIRDYC_BIT)
-#define RCC_CIR_PLLRDYIE                BIT(RCC_CIR_PLLRDYIE_BIT)
-#define RCC_CIR_HSERDYIE                BIT(RCC_CIR_HSERDYIE_BIT)
-#define RCC_CIR_HSIRDYIE                BIT(RCC_CIR_HSIRDYIE_BIT)
-#define RCC_CIR_LSERDYIE                BIT(RCC_CIR_LSERDYIE_BIT)
-#define RCC_CIR_LSIRDYIE                BIT(RCC_CIR_LSIRDYIE_BIT)
-#define RCC_CIR_CSSF                    BIT(RCC_CIR_CSSF_BIT)
-#define RCC_CIR_PLLRDYF                 BIT(RCC_CIR_PLLRDYF_BIT)
-#define RCC_CIR_HSERDYF                 BIT(RCC_CIR_HSERDYF_BIT)
-#define RCC_CIR_HSIRDYF                 BIT(RCC_CIR_HSIRDYF_BIT)
-#define RCC_CIR_LSERDYF                 BIT(RCC_CIR_LSERDYF_BIT)
-#define RCC_CIR_LSIRDYF                 BIT(RCC_CIR_LSIRDYF_BIT)
-
-/* APB2 peripheral reset register */
-
-#define RCC_APB2RSTR_TIM11RST_BIT       21
-#define RCC_APB2RSTR_TIM10RST_BIT       20
-#define RCC_APB2RSTR_TIM9RST_BIT        19
-#define RCC_APB2RSTR_ADC3RST_BIT        15
-#define RCC_APB2RSTR_USART1RST_BIT      14
-#define RCC_APB2RSTR_TIM8RST_BIT        13
-#define RCC_APB2RSTR_SPI1RST_BIT        12
-#define RCC_APB2RSTR_TIM1RST_BIT        11
-#define RCC_APB2RSTR_ADC2RST_BIT        10
-#define RCC_APB2RSTR_ADC1RST_BIT        9
-#define RCC_APB2RSTR_IOPGRST_BIT        8
-#define RCC_APB2RSTR_IOPFRST_BIT        7
-#define RCC_APB2RSTR_IOPERST_BIT        6
-#define RCC_APB2RSTR_IOPDRST_BIT        5
-#define RCC_APB2RSTR_IOPCRST_BIT        4
-#define RCC_APB2RSTR_IOPBRST_BIT        3
-#define RCC_APB2RSTR_IOPARST_BIT        2
-#define RCC_APB2RSTR_AFIORST_BIT        0
-
-#define RCC_APB2RSTR_TIM11RST           BIT(RCC_APB2RSTR_TIM11RST_BIT)
-#define RCC_APB2RSTR_TIM10RST           BIT(RCC_APB2RSTR_TIM10RST_BIT)
-#define RCC_APB2RSTR_TIM9RST            BIT(RCC_APB2RSTR_TIM9RST_BIT)
-#define RCC_APB2RSTR_ADC3RST            BIT(RCC_APB2RSTR_ADC3RST_BIT)
-#define RCC_APB2RSTR_USART1RST          BIT(RCC_APB2RSTR_USART1RST_BIT)
-#define RCC_APB2RSTR_TIM8RST            BIT(RCC_APB2RSTR_TIM8RST_BIT)
-#define RCC_APB2RSTR_SPI1RST            BIT(RCC_APB2RSTR_SPI1RST_BIT)
-#define RCC_APB2RSTR_TIM1RST            BIT(RCC_APB2RSTR_TIM1RST_BIT)
-#define RCC_APB2RSTR_ADC2RST            BIT(RCC_APB2RSTR_ADC2RST_BIT)
-#define RCC_APB2RSTR_ADC1RST            BIT(RCC_APB2RSTR_ADC1RST_BIT)
-#define RCC_APB2RSTR_IOPGRST            BIT(RCC_APB2RSTR_IOPGRST_BIT)
-#define RCC_APB2RSTR_IOPFRST            BIT(RCC_APB2RSTR_IOPFRST_BIT)
-#define RCC_APB2RSTR_IOPERST            BIT(RCC_APB2RSTR_IOPERST_BIT)
-#define RCC_APB2RSTR_IOPDRST            BIT(RCC_APB2RSTR_IOPDRST_BIT)
-#define RCC_APB2RSTR_IOPCRST            BIT(RCC_APB2RSTR_IOPCRST_BIT)
-#define RCC_APB2RSTR_IOPBRST            BIT(RCC_APB2RSTR_IOPBRST_BIT)
-#define RCC_APB2RSTR_IOPARST            BIT(RCC_APB2RSTR_IOPARST_BIT)
-#define RCC_APB2RSTR_AFIORST            BIT(RCC_APB2RSTR_AFIORST_BIT)
-
-/* APB1 peripheral reset register */
-
-#define RCC_APB1RSTR_DACRST_BIT         29
-#define RCC_APB1RSTR_PWRRST_BIT         28
-#define RCC_APB1RSTR_BKPRST_BIT         27
-#define RCC_APB1RSTR_CANRST_BIT         25
-#define RCC_APB1RSTR_USBRST_BIT         23
-#define RCC_APB1RSTR_I2C2RST_BIT        22
-#define RCC_APB1RSTR_I2C1RST_BIT        21
-#define RCC_APB1RSTR_UART5RST_BIT       20
-#define RCC_APB1RSTR_UART4RST_BIT       19
-#define RCC_APB1RSTR_USART3RST_BIT      18
-#define RCC_APB1RSTR_USART2RST_BIT      17
-#define RCC_APB1RSTR_SPI3RST_BIT        15
-#define RCC_APB1RSTR_SPI2RST_BIT        14
-#define RCC_APB1RSTR_WWDRST_BIT         11
-#define RCC_APB1RSTR_TIM14RST_BIT       8
-#define RCC_APB1RSTR_TIM13RST_BIT       7
-#define RCC_APB1RSTR_TIM12RST_BIT       6
-#define RCC_APB1RSTR_TIM7RST_BIT        5
-#define RCC_APB1RSTR_TIM6RST_BIT        4
-#define RCC_APB1RSTR_TIM5RST_BIT        3
-#define RCC_APB1RSTR_TIM4RST_BIT        2
-#define RCC_APB1RSTR_TIM3RST_BIT        1
-#define RCC_APB1RSTR_TIM2RST_BIT        0
-
-#define RCC_APB1RSTR_DACRST             BIT(RCC_APB1RSTR_DACRST_BIT)
-#define RCC_APB1RSTR_PWRRST             BIT(RCC_APB1RSTR_PWRRST_BIT)
-#define RCC_APB1RSTR_BKPRST             BIT(RCC_APB1RSTR_BKPRST_BIT)
-#define RCC_APB1RSTR_CANRST             BIT(RCC_APB1RSTR_CANRST_BIT)
-#define RCC_APB1RSTR_USBRST             BIT(RCC_APB1RSTR_USBRST_BIT)
-#define RCC_APB1RSTR_I2C2RST            BIT(RCC_APB1RSTR_I2C2RST_BIT)
-#define RCC_APB1RSTR_I2C1RST            BIT(RCC_APB1RSTR_I2C1RST_BIT)
-#define RCC_APB1RSTR_UART5RST           BIT(RCC_APB1RSTR_UART5RST_BIT)
-#define RCC_APB1RSTR_UART4RST           BIT(RCC_APB1RSTR_UART4RST_BIT)
-#define RCC_APB1RSTR_USART3RST          BIT(RCC_APB1RSTR_USART3RST_BIT)
-#define RCC_APB1RSTR_USART2RST          BIT(RCC_APB1RSTR_USART2RST_BIT)
-#define RCC_APB1RSTR_SPI3RST            BIT(RCC_APB1RSTR_SPI3RST_BIT)
-#define RCC_APB1RSTR_SPI2RST            BIT(RCC_APB1RSTR_SPI2RST_BIT)
-#define RCC_APB1RSTR_WWDRST             BIT(RCC_APB1RSTR_WWDRST_BIT)
-#define RCC_APB1RSTR_TIM14RST           BIT(RCC_APB1RSTR_TIM14RST_BIT)
-#define RCC_APB1RSTR_TIM13RST           BIT(RCC_APB1RSTR_TIM13RST_BIT)
-#define RCC_APB1RSTR_TIM12RST           BIT(RCC_APB1RSTR_TIM12RST_BIT)
-#define RCC_APB1RSTR_TIM7RST            BIT(RCC_APB1RSTR_TIM7RST_BIT)
-#define RCC_APB1RSTR_TIM6RST            BIT(RCC_APB1RSTR_TIM6RST_BIT)
-#define RCC_APB1RSTR_TIM5RST            BIT(RCC_APB1RSTR_TIM5RST_BIT)
-#define RCC_APB1RSTR_TIM4RST            BIT(RCC_APB1RSTR_TIM4RST_BIT)
-#define RCC_APB1RSTR_TIM3RST            BIT(RCC_APB1RSTR_TIM3RST_BIT)
-#define RCC_APB1RSTR_TIM2RST            BIT(RCC_APB1RSTR_TIM2RST_BIT)
-
-/* AHB peripheral clock enable register */
-
-#define RCC_AHBENR_SDIOEN_BIT           10
-#define RCC_AHBENR_FSMCEN_BIT           8
-#define RCC_AHBENR_CRCEN_BIT            7
-#define RCC_AHBENR_FLITFEN_BIT          4
-#define RCC_AHBENR_SRAMEN_BIT           2
-#define RCC_AHBENR_DMA2EN_BIT           1
-#define RCC_AHBENR_DMA1EN_BIT           0
-
-#define RCC_AHBENR_SDIOEN               BIT(RCC_AHBENR_SDIOEN_BIT)
-#define RCC_AHBENR_FSMCEN               BIT(RCC_AHBENR_FSMCEN_BIT)
-#define RCC_AHBENR_CRCEN                BIT(RCC_AHBENR_CRCEN_BIT)
-#define RCC_AHBENR_FLITFEN              BIT(RCC_AHBENR_FLITFEN_BIT)
-#define RCC_AHBENR_SRAMEN               BIT(RCC_AHBENR_SRAMEN_BIT)
-#define RCC_AHBENR_DMA2EN               BIT(RCC_AHBENR_DMA2EN_BIT)
-#define RCC_AHBENR_DMA1EN               BIT(RCC_AHBENR_DMA1EN_BIT)
-
-/* APB2 peripheral clock enable register */
-
-#define RCC_APB2ENR_TIM11EN_BIT         21
-#define RCC_APB2ENR_TIM10EN_BIT         20
-#define RCC_APB2ENR_TIM9EN_BIT          19
-#define RCC_APB2ENR_ADC3EN_BIT          15
-#define RCC_APB2ENR_USART1EN_BIT        14
-#define RCC_APB2ENR_TIM8EN_BIT          13
-#define RCC_APB2ENR_SPI1EN_BIT          12
-#define RCC_APB2ENR_TIM1EN_BIT          11
-#define RCC_APB2ENR_ADC2EN_BIT          10
-#define RCC_APB2ENR_ADC1EN_BIT          9
-#define RCC_APB2ENR_IOPGEN_BIT          8
-#define RCC_APB2ENR_IOPFEN_BIT          7
-#define RCC_APB2ENR_IOPEEN_BIT          6
-#define RCC_APB2ENR_IOPDEN_BIT          5
-#define RCC_APB2ENR_IOPCEN_BIT          4
-#define RCC_APB2ENR_IOPBEN_BIT          3
-#define RCC_APB2ENR_IOPAEN_BIT          2
-#define RCC_APB2ENR_AFIOEN_BIT          0
-
-#define RCC_APB2ENR_TIM11EN             BIT(RCC_APB2ENR_TIM11EN_BIT)
-#define RCC_APB2ENR_TIM10EN             BIT(RCC_APB2ENR_TIM10EN_BIT)
-#define RCC_APB2ENR_TIM9EN              BIT(RCC_APB2ENR_TIM9EN_BIT)
-#define RCC_APB2ENR_ADC3EN              BIT(RCC_APB2ENR_ADC3EN_BIT)
-#define RCC_APB2ENR_USART1EN            BIT(RCC_APB2ENR_USART1EN_BIT)
-#define RCC_APB2ENR_TIM8EN              BIT(RCC_APB2ENR_TIM8EN_BIT)
-#define RCC_APB2ENR_SPI1EN              BIT(RCC_APB2ENR_SPI1EN_BIT)
-#define RCC_APB2ENR_TIM1EN              BIT(RCC_APB2ENR_TIM1EN_BIT)
-#define RCC_APB2ENR_ADC2EN              BIT(RCC_APB2ENR_ADC2EN_BIT)
-#define RCC_APB2ENR_ADC1EN              BIT(RCC_APB2ENR_ADC1EN_BIT)
-#define RCC_APB2ENR_IOPGEN              BIT(RCC_APB2ENR_IOPGEN_BIT)
-#define RCC_APB2ENR_IOPFEN              BIT(RCC_APB2ENR_IOPFEN_BIT)
-#define RCC_APB2ENR_IOPEEN              BIT(RCC_APB2ENR_IOPEEN_BIT)
-#define RCC_APB2ENR_IOPDEN              BIT(RCC_APB2ENR_IOPDEN_BIT)
-#define RCC_APB2ENR_IOPCEN              BIT(RCC_APB2ENR_IOPCEN_BIT)
-#define RCC_APB2ENR_IOPBEN              BIT(RCC_APB2ENR_IOPBEN_BIT)
-#define RCC_APB2ENR_IOPAEN              BIT(RCC_APB2ENR_IOPAEN_BIT)
-#define RCC_APB2ENR_AFIOEN              BIT(RCC_APB2ENR_AFIOEN_BIT)
-
-/* APB1 peripheral clock enable register */
-
-#define RCC_APB1ENR_DACEN_BIT           29
-#define RCC_APB1ENR_PWREN_BIT           28
-#define RCC_APB1ENR_BKPEN_BIT           27
-#define RCC_APB1ENR_CANEN_BIT           25
-#define RCC_APB1ENR_USBEN_BIT           23
-#define RCC_APB1ENR_I2C2EN_BIT          22
-#define RCC_APB1ENR_I2C1EN_BIT          21
-#define RCC_APB1ENR_UART5EN_BIT         20
-#define RCC_APB1ENR_UART4EN_BIT         19
-#define RCC_APB1ENR_USART3EN_BIT        18
-#define RCC_APB1ENR_USART2EN_BIT        17
-#define RCC_APB1ENR_SPI3EN_BIT          15
-#define RCC_APB1ENR_SPI2EN_BIT          14
-#define RCC_APB1ENR_WWDEN_BIT           11
-#define RCC_APB1ENR_TIM14EN_BIT         8
-#define RCC_APB1ENR_TIM13EN_BIT         7
-#define RCC_APB1ENR_TIM12EN_BIT         6
-#define RCC_APB1ENR_TIM7EN_BIT          5
-#define RCC_APB1ENR_TIM6EN_BIT          4
-#define RCC_APB1ENR_TIM5EN_BIT          3
-#define RCC_APB1ENR_TIM4EN_BIT          2
-#define RCC_APB1ENR_TIM3EN_BIT          1
-#define RCC_APB1ENR_TIM2EN_BIT          0
-
-#define RCC_APB1ENR_DACEN               BIT(RCC_APB1ENR_DACEN_BIT)
-#define RCC_APB1ENR_PWREN               BIT(RCC_APB1ENR_PWREN_BIT)
-#define RCC_APB1ENR_BKPEN               BIT(RCC_APB1ENR_BKPEN_BIT)
-#define RCC_APB1ENR_CANEN               BIT(RCC_APB1ENR_CANEN_BIT)
-#define RCC_APB1ENR_USBEN               BIT(RCC_APB1ENR_USBEN_BIT)
-#define RCC_APB1ENR_I2C2EN              BIT(RCC_APB1ENR_I2C2EN_BIT)
-#define RCC_APB1ENR_I2C1EN              BIT(RCC_APB1ENR_I2C1EN_BIT)
-#define RCC_APB1ENR_UART5EN             BIT(RCC_APB1ENR_UART5EN_BIT)
-#define RCC_APB1ENR_UART4EN             BIT(RCC_APB1ENR_UART4EN_BIT)
-#define RCC_APB1ENR_USART3EN            BIT(RCC_APB1ENR_USART3EN_BIT)
-#define RCC_APB1ENR_USART2EN            BIT(RCC_APB1ENR_USART2EN_BIT)
-#define RCC_APB1ENR_SPI3EN              BIT(RCC_APB1ENR_SPI3EN_BIT)
-#define RCC_APB1ENR_SPI2EN              BIT(RCC_APB1ENR_SPI2EN_BIT)
-#define RCC_APB1ENR_WWDEN               BIT(RCC_APB1ENR_WWDEN_BIT)
-#define RCC_APB1ENR_TIM14EN             BIT(RCC_APB1ENR_TIM14EN_BIT)
-#define RCC_APB1ENR_TIM13EN             BIT(RCC_APB1ENR_TIM13EN_BIT)
-#define RCC_APB1ENR_TIM12EN             BIT(RCC_APB1ENR_TIM12EN_BIT)
-#define RCC_APB1ENR_TIM7EN              BIT(RCC_APB1ENR_TIM7EN_BIT)
-#define RCC_APB1ENR_TIM6EN              BIT(RCC_APB1ENR_TIM6EN_BIT)
-#define RCC_APB1ENR_TIM5EN              BIT(RCC_APB1ENR_TIM5EN_BIT)
-#define RCC_APB1ENR_TIM4EN              BIT(RCC_APB1ENR_TIM4EN_BIT)
-#define RCC_APB1ENR_TIM3EN              BIT(RCC_APB1ENR_TIM3EN_BIT)
-#define RCC_APB1ENR_TIM2EN              BIT(RCC_APB1ENR_TIM2EN_BIT)
-
-/* Backup domain control register */
-
-#define RCC_BDCR_BDRST_BIT              16
-#define RCC_BDCR_RTCEN_BIT              15
-#define RCC_BDCR_LSEBYP_BIT             2
-#define RCC_BDCR_LSERDY_BIT             1
-#define RCC_BDCR_LSEON_BIT              0
-
-#define RCC_BDCR_BDRST                  BIT(RCC_BDCR_BDRST_BIT)
-#define RCC_BDCR_RTCEN                  BIT(RCC_BDCR_RTC_BIT)
-#define RCC_BDCR_RTCSEL                 (0x3 << 8)
-#define RCC_BDCR_RTCSEL_NONE            (0x0 << 8)
-#define RCC_BDCR_RTCSEL_LSE             (0x1 << 8)
-#define RCC_BDCR_RTCSEL_HSE             (0x3 << 8)
-#define RCC_BDCR_LSEBYP                 BIT(RCC_BDCR_LSEBYP_BIT)
-#define RCC_BDCR_LSERDY                 BIT(RCC_BDCR_LSERDY_BIT)
-#define RCC_BDCR_LSEON                  BIT(RCC_BDCR_LSEON_BIT)
-
-/* Control/status register */
-
-#define RCC_CSR_LPWRRSTF_BIT            31
-#define RCC_CSR_WWDGRSTF_BIT            30
-#define RCC_CSR_IWDGRSTF_BIT            29
-#define RCC_CSR_SFTRSTF_BIT             28
-#define RCC_CSR_PORRSTF_BIT             27
-#define RCC_CSR_PINRSTF_BIT             26
-#define RCC_CSR_RMVF_BIT                24
-#define RCC_CSR_LSIRDY_BIT              1
-#define RCC_CSR_LSION_BIT               0
-
-#define RCC_CSR_LPWRRSTF                BIT(RCC_CSR_LPWRRSTF_BIT)
-#define RCC_CSR_WWDGRSTF                BIT(RCC_CSR_WWDGRSTF_BIT)
-#define RCC_CSR_IWDGRSTF                BIT(RCC_CSR_IWDGRSTF_BIT)
-#define RCC_CSR_SFTRSTF                 BIT(RCC_CSR_SFTRSTF_BIT)
-#define RCC_CSR_PORRSTF                 BIT(RCC_CSR_PORRSTF_BIT)
-#define RCC_CSR_PINRSTF                 BIT(RCC_CSR_PINRSTF_BIT)
-#define RCC_CSR_RMVF                    BIT(RCC_CSR_RMVF_BIT)
-#define RCC_CSR_LSIRDY                  BIT(RCC_CSR_LSIRDY_BIT)
-#define RCC_CSR_LSION                   BIT(RCC_CSR_LSION_BIT)
-
-/*
- * Convenience routines
- */
-
-/**
- * SYSCLK sources
- * @see rcc_clk_init()
- */
-typedef enum rcc_sysclk_src {
-    RCC_CLKSRC_HSI = 0x0,
-    RCC_CLKSRC_HSE = 0x1,
-    RCC_CLKSRC_PLL = 0x2,
-} rcc_sysclk_src;
-
-/**
- * PLL entry clock source
- * @see rcc_clk_init()
- */
-typedef enum rcc_pllsrc {
-    RCC_PLLSRC_HSE = (0x1 << 16),
-    RCC_PLLSRC_HSI_DIV_2 = (0x0 << 16)
-} rcc_pllsrc;
-
-/**
- * PLL multipliers
- * @see rcc_clk_init()
- */
-typedef enum rcc_pll_multiplier {
-    RCC_PLLMUL_2 = (0x0 << 18),
-    RCC_PLLMUL_3 = (0x1 << 18),
-    RCC_PLLMUL_4 = (0x2 << 18),
-    RCC_PLLMUL_5 = (0x3 << 18),
-    RCC_PLLMUL_6 = (0x4 << 18),
-    RCC_PLLMUL_7 = (0x5 << 18),
-    RCC_PLLMUL_8 = (0x6 << 18),
-    RCC_PLLMUL_9 = (0x7 << 18),
-    RCC_PLLMUL_10 = (0x8 << 18),
-    RCC_PLLMUL_11 = (0x9 << 18),
-    RCC_PLLMUL_12 = (0xA << 18),
-    RCC_PLLMUL_13 = (0xB << 18),
-    RCC_PLLMUL_14 = (0xC << 18),
-    RCC_PLLMUL_15 = (0xD << 18),
-    RCC_PLLMUL_16 = (0xE << 18),
-} rcc_pll_multiplier;
-
-/**
- * @brief Identifies bus and clock line for a peripheral.
- *
- * Also generally useful as a unique identifier for that peripheral
- * (or its corresponding device struct).
- */
-typedef enum rcc_clk_id {
-    RCC_GPIOA,
-    RCC_GPIOB,
-    RCC_GPIOC,
-    RCC_GPIOD,
-    RCC_AFIO,
-    RCC_ADC1,
-    RCC_ADC2,
-    RCC_ADC3,
-    RCC_USART1,
-    RCC_USART2,
-    RCC_USART3,
-    RCC_TIMER1,
-    RCC_TIMER2,
-    RCC_TIMER3,
-    RCC_TIMER4,
-    RCC_SPI1,
-    RCC_SPI2,
-    RCC_DMA1,
-    RCC_PWR,
-    RCC_BKP,
-    RCC_I2C1,
-    RCC_I2C2,
-    RCC_CRC,
-    RCC_FLITF,
-    RCC_SRAM,
-#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
-    RCC_GPIOE,
-    RCC_GPIOF,
-    RCC_GPIOG,
-    RCC_UART4,
-    RCC_UART5,
-    RCC_TIMER5,
-    RCC_TIMER6,
-    RCC_TIMER7,
-    RCC_TIMER8,
-    RCC_FSMC,
-    RCC_DAC,
-    RCC_DMA2,
-    RCC_SDIO,
-    RCC_SPI3,
-#endif
-#ifdef STM32_XL_DENSITY
-    RCC_TIMER9,
-    RCC_TIMER10,
-    RCC_TIMER11,
-    RCC_TIMER12,
-    RCC_TIMER13,
-    RCC_TIMER14,
-#endif
-} rcc_clk_id;
-
-void rcc_clk_init(rcc_sysclk_src sysclk_src,
-                  rcc_pllsrc pll_src,
-                  rcc_pll_multiplier pll_mul);
-void rcc_clk_enable(rcc_clk_id device);
-void rcc_reset_dev(rcc_clk_id device);
-
-typedef enum rcc_clk_domain {
-    RCC_APB1,
-    RCC_APB2,
-    RCC_AHB
-} rcc_clk_domain;
-
-rcc_clk_domain rcc_dev_clk(rcc_clk_id device);
-
-uint32 rcc_dev_clk_speed(rcc_clk_id id);
-uint32 rcc_dev_timer_clk_speed(rcc_clk_id id);
-
-/**
- * Prescaler identifiers
- * @see rcc_set_prescaler()
- */
-typedef enum rcc_prescaler {
-    RCC_PRESCALER_AHB,
-    RCC_PRESCALER_APB1,
-    RCC_PRESCALER_APB2,
-    RCC_PRESCALER_USB,
-    RCC_PRESCALER_ADC
-} rcc_prescaler;
-
-/**
- * ADC prescaler dividers
- * @see rcc_set_prescaler()
- */
-typedef enum rcc_adc_divider {
-    RCC_ADCPRE_PCLK_DIV_2 = 0x0 << 14,
-    RCC_ADCPRE_PCLK_DIV_4 = 0x1 << 14,
-    RCC_ADCPRE_PCLK_DIV_6 = 0x2 << 14,
-    RCC_ADCPRE_PCLK_DIV_8 = 0x3 << 14,
-} rcc_adc_divider;
-
-/**
- * APB1 prescaler dividers
- * @see rcc_set_prescaler()
- */
-typedef enum rcc_apb1_divider {
-    RCC_APB1_HCLK_DIV_1 = 0x0 << 8,
-    RCC_APB1_HCLK_DIV_2 = 0x4 << 8,
-    RCC_APB1_HCLK_DIV_4 = 0x5 << 8,
-    RCC_APB1_HCLK_DIV_8 = 0x6 << 8,
-    RCC_APB1_HCLK_DIV_16 = 0x7 << 8,
-} rcc_apb1_divider;
-
-/**
- * APB2 prescaler dividers
- * @see rcc_set_prescaler()
- */
-typedef enum rcc_apb2_divider {
-    RCC_APB2_HCLK_DIV_1 = 0x0 << 11,
-    RCC_APB2_HCLK_DIV_2 = 0x4 << 11,
-    RCC_APB2_HCLK_DIV_4 = 0x5 << 11,
-    RCC_APB2_HCLK_DIV_8 = 0x6 << 11,
-    RCC_APB2_HCLK_DIV_16 = 0x7 << 11,
-} rcc_apb2_divider;
-
-/**
- * AHB prescaler dividers
- * @see rcc_set_prescaler()
- */
-typedef enum rcc_ahb_divider {
-    RCC_AHB_SYSCLK_DIV_1 = 0x0 << 4,
-    RCC_AHB_SYSCLK_DIV_2 = 0x8 << 4,
-    RCC_AHB_SYSCLK_DIV_4 = 0x9 << 4,
-    RCC_AHB_SYSCLK_DIV_8 = 0xA << 4,
-    RCC_AHB_SYSCLK_DIV_16 = 0xB << 4,
-    RCC_AHB_SYSCLK_DIV_32 = 0xC << 4,
-    RCC_AHB_SYSCLK_DIV_64 = 0xD << 4,
-    RCC_AHB_SYSCLK_DIV_128 = 0xD << 4,
-    RCC_AHB_SYSCLK_DIV_256 = 0xE << 4,
-    RCC_AHB_SYSCLK_DIV_512 = 0xF << 4,
-} rcc_ahb_divider;
-
-void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider);
-
-#ifdef __cplusplus
-} // extern "C"
-#endif
-
-#endif
diff --git a/STM32F4/cores/maple/libmaple/rccF2.c b/STM32F4/cores/maple/libmaple/rccF4.c
similarity index 99%
rename from STM32F4/cores/maple/libmaple/rccF2.c
rename to STM32F4/cores/maple/libmaple/rccF4.c
index 691393a8d..c4ff30dc4 100644
--- a/STM32F4/cores/maple/libmaple/rccF2.c
+++ b/STM32F4/cores/maple/libmaple/rccF4.c
@@ -24,7 +24,7 @@
  * SOFTWARE.
  *****************************************************************************/
 
- #ifdef STM32F2
+#ifdef STM32F4
  
 /**
  * @file rcc.c
@@ -166,7 +166,6 @@ typedef struct
 #define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
 #define RESET 0
 
-typedef uint32 uint32_t;
 
 void InitMCO1()
 {
@@ -175,8 +174,8 @@ void InitMCO1()
     RCC->CFGR &= RCC_CFGR_MCO1_RESET_MASK;
     RCC->CFGR |= RCC_CFGR_MCO1Source_HSE | RCC_CFGR_MCO1Div_1;
     // PA8 Output the Master Clock MCO1
-    gpio_set_af_mode(GPIOA, 8, 0);
-    gpio_set_mode(GPIOA, 8, GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
+    gpio_set_af_mode(PA8, 0);
+    gpio_set_mode(PA8, GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
 }
 
 
diff --git a/STM32F4/cores/maple/libmaple/rccF2.h b/STM32F4/cores/maple/libmaple/rccF4.h
similarity index 100%
rename from STM32F4/cores/maple/libmaple/rccF2.h
rename to STM32F4/cores/maple/libmaple/rccF4.h
diff --git a/STM32F4/cores/maple/libmaple/rules.mk b/STM32F4/cores/maple/libmaple/rules.mk
index c4924dc86..eb8d96d26 100644
--- a/STM32F4/cores/maple/libmaple/rules.mk
+++ b/STM32F4/cores/maple/libmaple/rules.mk
@@ -3,17 +3,11 @@ sp              := $(sp).x
 dirstack_$(sp)  := $(d)
 d               := $(dir)
 BUILDDIRS       += $(BUILD_PATH)/$(d)
-ifneq ($(MCU_FAMILY), STM32F2)
-BUILDDIRS       += $(BUILD_PATH)/$(d)/usb
-BUILDDIRS       += $(BUILD_PATH)/$(d)/usb/usb_lib
-LIBMAPLE_INCLUDES := -I$(LIBMAPLE_PATH) -I$(LIBMAPLE_PATH)/usb -I$(LIBMAPLE_PATH)/usb/usb_lib
-else
 BUILDDIRS       += $(BUILD_PATH)/$(d)/usbF4/STM32_USB_Device_Library/Core/src
 BUILDDIRS       += $(BUILD_PATH)/$(d)/usbF4/STM32_USB_Device_Library/Class/cdc/src
 BUILDDIRS       += $(BUILD_PATH)/$(d)/usbF4/STM32_USB_OTG_Driver/src
 BUILDDIRS       += $(BUILD_PATH)/$(d)/usbF4/VCP
 LIBMAPLE_INCLUDES := -I$(LIBMAPLE_PATH) -I$(LIBMAPLE_PATH)/usbF4
-endif
 
 
 # Local flags
@@ -42,18 +36,6 @@ cSRCS_$(d) := adc.c                    \
               usart.c                  \
               util.c                   
 
-ifneq ($(MCU_FAMILY), STM32F2)
-	cSRCS_$(d) += \
-              usb/descriptors.c        \
-              usb/usb.c                \
-              usb/usb_callbacks.c      \
-              usb/usb_hardware.c       \
-              usb/usb_lib/usb_core.c   \
-              usb/usb_lib/usb_init.c   \
-              usb/usb_lib/usb_int.c    \
-              usb/usb_lib/usb_mem.c    \
-              usb/usb_lib/usb_regs.c
-else
 	V=1
 	cSRCS_$(d) += \
 		usbF4/STM32_USB_Device_Library/Core/src/usbd_core.c \
@@ -69,11 +51,7 @@ else
 		usbF4/VCP/usbd_usr.c \
 		usbF4/usb.c \
 		usbF4/VCP/misc.c 
-endif
 
-ifneq ($(MCU_FAMILY), STM32F2)
-	cSRCS_$(d) += bkp.c
-endif
 
 sSRCS_$(d) := exc.S
 
diff --git a/STM32F4/cores/maple/libmaple/spi.c b/STM32F4/cores/maple/libmaple/spi.c
index 194a82efe..4b274cb37 100644
--- a/STM32F4/cores/maple/libmaple/spi.c
+++ b/STM32F4/cores/maple/libmaple/spi.c
@@ -83,25 +83,29 @@ void spi_slave_enable(spi_dev *dev, spi_mode mode, uint32 flags) {
 }
 
 /**
- * @brief Nonblocking SPI transmit.
+ * @brief Blocking SPI transmit.
  * @param dev SPI port to use for transmission
  * @param buf Buffer to transmit.  The sizeof buf's elements are
  *            inferred from dev's data frame format (i.e., are
  *            correctly treated as 8-bit or 16-bit quantities).
  * @param len Maximum number of elements to transmit.
- * @return Number of elements transmitted.
  */
-uint32 spi_tx(spi_dev *dev, const void *buf, uint32 len) {
-    uint32 txed = 0;
-    uint8 byte_frame = spi_dff(dev) == SPI_DFF_8_BIT;
-    while (spi_is_tx_empty(dev) && (txed < len)) {
-        if (byte_frame) {
-            dev->regs->DR = ((const uint8*)buf)[txed++];
-        } else {
-            dev->regs->DR = ((const uint16*)buf)[txed++];
-        }
-    }
-    return txed;
+void spi_tx(spi_dev *dev, void *buf, uint32 len)
+{
+	spi_reg_map *regs = dev->regs;
+    if ( spi_dff(dev) == SPI_DFF_8_BIT ) {
+		uint8 * dp8 = (uint8*)buf;
+		while ( len-- ) {
+			while ( (regs->SR & SPI_SR_TXE)==0 ) ; //while ( spi_is_tx_empty(dev)==0 ); // wait Tx to be empty
+			regs->DR = *dp8++;
+		}
+    } else {
+		uint16 * dp16 = (uint16*)buf;
+		while ( len-- ) {
+			while ( (regs->SR & SPI_SR_TXE)==0 ) ; //while ( spi_is_tx_empty(dev)==0 ); // wait Tx to be empty
+			regs->DR = *dp16++;
+		}
+	}
 }
 
 /**
@@ -157,8 +161,9 @@ void spi_rx_dma_disable(spi_dev *dev) {
  */
 
 static void spi_reconfigure(spi_dev *dev, uint32 cr1_config) {
-    spi_irq_disable(dev, SPI_INTERRUPTS_ALL);
-    spi_peripheral_disable(dev);
-    dev->regs->CR1 = cr1_config;
-    spi_peripheral_enable(dev);
+#define MASK (SPI_CR1_CRCEN|SPI_CR1_DFF)
+	spi_irq_disable(dev, SPI_INTERRUPTS_ALL);
+	if ( (dev->regs->CR1&MASK)!=(cr1_config&MASK) )	spi_peripheral_disable(dev);
+	dev->regs->CR1 = cr1_config;
+	spi_peripheral_enable(dev);
 }
diff --git a/STM32F4/cores/maple/libmaple/spi.h b/STM32F4/cores/maple/libmaple/spi.h
index 88739c584..abed68c12 100644
--- a/STM32F4/cores/maple/libmaple/spi.h
+++ b/STM32F4/cores/maple/libmaple/spi.h
@@ -213,31 +213,22 @@ typedef struct spi_dev {
 
 void spi_init(spi_dev *dev);
 
-struct gpio_dev;
 /**
  * @brief Configure GPIO bit modes for use as a SPI port's pins.
  *
  * @param dev SPI device
  * @param as_master If true, configure as bus master; otherwise, as slave.
- * @param nss_dev NSS pin's GPIO device
  * @param nss_bit NSS pin's GPIO bit on nss_dev
- * @param sck_dev SCK pin's GPIO device
  * @param sck_bit SCK pin's GPIO bit on comm_dev
- * @param miso_dev MISO pin's GPIO device
  * @param miso_bit MISO pin's GPIO bit on comm_dev
- * @param mosi_dev MOSI pin's GPIO device
  * @param mosi_bit MOSI pin's GPIO bit on comm_dev
  */
 extern void spi_config_gpios(spi_dev *dev,
                              uint8 as_master,
-                             struct gpio_dev *nss_dev,
-                             uint8 nss_bit,
-                             struct gpio_dev *sck_dev,
-                             uint8 sck_bit,
-                             struct gpio_dev *miso_dev,
-                             uint8 miso_bit,
-                             struct gpio_dev *mosi_dev,
-                             uint8 mosi_bit);
+                             uint8 nss_pin,
+                             uint8 sck_pin,
+                             uint8 miso_pin,
+                             uint8 mosi_pin);
 
 /**
  * @brief SPI mode configuration.
@@ -312,7 +303,7 @@ void spi_slave_enable(spi_dev *dev,
                       spi_mode mode,
                       uint32 flags);
 
-uint32 spi_tx(spi_dev *dev, const void *buf, uint32 len);
+void spi_tx(spi_dev *dev, void *buf, uint32 len);
 
 /**
  * @brief Call a function on each SPI port
diff --git a/STM32F4/cores/maple/libmaple/spiF4.h b/STM32F4/cores/maple/libmaple/spiF4.h
index 3f5116442..cbdc91a73 100644
--- a/STM32F4/cores/maple/libmaple/spiF4.h
+++ b/STM32F4/cores/maple/libmaple/spiF4.h
@@ -31,8 +31,8 @@
  * @brief STM32F1 SPI/I2S series header.
  */
 
-#ifndef _LIBMAPLE_STM32F1_SPI_H_
-#define _LIBMAPLE_STM32F1_SPI_H_
+#ifndef _LIBMAPLE_SPI_F4_H_
+#define _LIBMAPLE_SPI_F4_H_
 
 #include <libmaple/libmaple_types.h>
 
@@ -62,17 +62,6 @@ extern struct spi_dev *SPI2;
 extern struct spi_dev *SPI3;
 #endif
 
-/*
- * Routines
- */
-
-/* spi_gpio_cfg(): Backwards compatibility shim to spi_config_gpios() */
-struct gpio_dev;
-extern void spi_config_gpios(struct spi_dev*, uint8,
-                             struct gpio_dev*, uint8,
-                             struct gpio_dev*, uint8, 
-                             struct gpio_dev*, uint8, 
-                             struct gpio_dev*, uint8); 
 
 #ifdef __cplusplus
 }
diff --git a/STM32F4/cores/maple/libmaple/spi_f4.c b/STM32F4/cores/maple/libmaple/spi_f4.c
index b9beb68d2..43f5092c6 100644
--- a/STM32F4/cores/maple/libmaple/spi_f4.c
+++ b/STM32F4/cores/maple/libmaple/spi_f4.c
@@ -56,25 +56,21 @@ spi_dev *SPI3 = &spi3;
 
 void spi_config_gpios(spi_dev *ignored,
                       uint8 as_master,
-                      gpio_dev *nss_dev,
-                      uint8 nss_bit,
-                      gpio_dev *sck_dev,
-                      uint8 sck_bit,
-                      gpio_dev *miso_dev,
-                      uint8 miso_bit,
-                      gpio_dev *mosi_dev,
-                      uint8 mosi_bit) {
+                      uint8 nss_pin,
+                      uint8 sck_pin,
+                      uint8 miso_pin,
+                      uint8 mosi_pin) {
     if (as_master) {
 //        gpio_set_mode(nss_dev, nss_bit, GPIO_AF_OUTPUT_PP);
-        gpio_set_mode(sck_dev, sck_bit, GPIO_AF_OUTPUT_PP);
+        gpio_set_mode(sck_pin, GPIO_AF_OUTPUT_PP);
 //        gpio_set_mode(comm_dev, miso_bit, GPIO_INPUT_FLOATING);
-        gpio_set_mode(miso_dev, miso_bit, GPIO_AF_INPUT_PD);		
-        gpio_set_mode(mosi_dev, mosi_bit, GPIO_AF_OUTPUT_PP);
+        gpio_set_mode(miso_pin, GPIO_AF_INPUT_PD);		
+        gpio_set_mode(mosi_pin, GPIO_AF_OUTPUT_PP);
     } else {
-        gpio_set_mode(nss_dev, nss_bit, GPIO_INPUT_FLOATING);
-        gpio_set_mode(sck_dev, sck_bit, GPIO_INPUT_FLOATING);
-        gpio_set_mode(miso_dev, miso_bit, GPIO_AF_OUTPUT_PP);
-        gpio_set_mode(mosi_dev, mosi_bit, GPIO_INPUT_FLOATING);
+        gpio_set_mode(nss_pin, GPIO_INPUT_FLOATING);
+        gpio_set_mode(sck_pin, GPIO_INPUT_FLOATING);
+        gpio_set_mode(miso_pin, GPIO_AF_OUTPUT_PP);
+        gpio_set_mode(mosi_pin, GPIO_INPUT_FLOATING);
     }
 }
 
diff --git a/STM32F4/cores/maple/libmaple/stm32.h b/STM32F4/cores/maple/libmaple/stm32.h
index 0d4deaa41..3921788e7 100644
--- a/STM32F4/cores/maple/libmaple/stm32.h
+++ b/STM32F4/cores/maple/libmaple/stm32.h
@@ -138,69 +138,8 @@
 
 #endif
 
-#if defined(MCU_STM32F103RB)
-    /* e.g., LeafLabs Maple */
 
-    #define STM32_NR_GPIO_PORTS          4
-    #define STM32_DELAY_US_MULT         12
-    #define STM32_SRAM_END              ((void*)0x20005000)
-
-    #define NR_GPIO_PORTS               STM32_NR_GPIO_PORTS
-    #define DELAY_US_MULT               STM32_DELAY_US_MULT
-
-#elif defined(MCU_STM32F103ZE)
-    /* e.g., LeafLabs Maple Native */
-
-    #define STM32_NR_GPIO_PORTS          7
-    #define STM32_DELAY_US_MULT         12
-    #define STM32_SRAM_END              ((void*)0x20010000)
-
-    #define NR_GPIO_PORTS               STM32_NR_GPIO_PORTS
-    #define DELAY_US_MULT               STM32_DELAY_US_MULT
-
-#elif defined(MCU_STM32F103CB)
-    /* e.g., LeafLabs Maple Mini */
-
-    /* This STM32_NR_GPIO_PORTS value is not, strictly speaking, true.
-     * But only pins 0 and 1 exist, and they're used for OSC on the
-     * Mini, so we'll live with this for now. */
-    #define STM32_NR_GPIO_PORTS          3
-    #define STM32_DELAY_US_MULT         12
-    #define STM32_SRAM_END              ((void*)0x20005000)
-
-    #define NR_GPIO_PORTS               STM32_NR_GPIO_PORTS
-    #define DELAY_US_MULT               STM32_DELAY_US_MULT
-
-#elif defined(MCU_STM32F103RE)
-    /* e.g., LeafLabs Maple RET6 edition */
-
-    #define STM32_NR_GPIO_PORTS          4
-    #define STM32_DELAY_US_MULT         12
-    #define STM32_SRAM_END              ((void*)0x20010000)
-
-    #define NR_GPIO_PORTS               STM32_NR_GPIO_PORTS
-    #define DELAY_US_MULT               STM32_DELAY_US_MULT
-
-#elif defined(MCU_STM32F103VE)
-    /* e.g., LeafLabs Maple Native */
-
-    #define STM32_NR_GPIO_PORTS          5
-    #define STM32_DELAY_US_MULT         12
-    #define STM32_SRAM_END              ((void*)0x20010000)
-
-    #define NR_GPIO_PORTS               STM32_NR_GPIO_PORTS
-    #define DELAY_US_MULT               STM32_DELAY_US_MULT
-
-#elif defined(MCU_STM32F205VE)
-	#define STM32_TICKS_PER_US          120
-    #define STM32_NR_GPIO_PORTS          5
-    #define STM32_DELAY_US_MULT         (STM32_TICKS_PER_US/3)
-    #define STM32_SRAM_END              ((void*)0x20010000)
-
-    #define NR_GPIO_PORTS               STM32_NR_GPIO_PORTS
-    #define DELAY_US_MULT               STM32_DELAY_US_MULT
-
-#elif defined(MCU_STM32F406VG)
+#if defined( STM32F4 )
 	#define STM32_TICKS_PER_US          168
     #define STM32_NR_GPIO_PORTS          5
     #define STM32_DELAY_US_MULT         (STM32_TICKS_PER_US/3)
diff --git a/STM32F4/cores/maple/libmaple/timer.c b/STM32F4/cores/maple/libmaple/timer.c
index 83e9ace33..f8e55a185 100644
--- a/STM32F4/cores/maple/libmaple/timer.c
+++ b/STM32F4/cores/maple/libmaple/timer.c
@@ -44,7 +44,7 @@
 /* Update only. */
 #define NR_BAS_HANDLERS                 1
 
-static timer_dev timer1 = {
+timer_dev timer1 = {
     .regs         = { .adv = TIMER1_BASE },
     .clk_id       = RCC_TIMER1,
     .type         = TIMER_ADVANCED,
@@ -53,7 +53,7 @@ static timer_dev timer1 = {
 /** Timer 1 device (advanced) */
 timer_dev *TIMER1 = &timer1;
 
-static timer_dev timer2 = {
+timer_dev timer2 = {
     .regs         = { .gen = TIMER2_BASE },
     .clk_id       = RCC_TIMER2,
     .type         = TIMER_GENERAL,
@@ -62,7 +62,7 @@ static timer_dev timer2 = {
 /** Timer 2 device (general-purpose) */
 timer_dev *TIMER2 = &timer2;
 
-static timer_dev timer3 = {
+timer_dev timer3 = {
     .regs         = { .gen = TIMER3_BASE },
     .clk_id       = RCC_TIMER3,
     .type         = TIMER_GENERAL,
@@ -71,7 +71,7 @@ static timer_dev timer3 = {
 /** Timer 3 device (general-purpose) */
 timer_dev *TIMER3 = &timer3;
 
-static timer_dev timer4 = {
+timer_dev timer4 = {
     .regs         = { .gen = TIMER4_BASE },
     .clk_id       = RCC_TIMER4,
     .type         = TIMER_GENERAL,
@@ -81,7 +81,7 @@ static timer_dev timer4 = {
 timer_dev *TIMER4 = &timer4;
 
 #ifdef STM32_HIGH_DENSITY
-static timer_dev timer5 = {
+timer_dev timer5 = {
     .regs         = { .gen = TIMER5_BASE },
     .clk_id       = RCC_TIMER5,
     .type         = TIMER_GENERAL,
@@ -90,7 +90,7 @@ static timer_dev timer5 = {
 /** Timer 5 device (general-purpose) */
 timer_dev *TIMER5 = &timer5;
 
-static timer_dev timer6 = {
+timer_dev timer6 = {
     .regs         = { .bas = TIMER6_BASE },
     .clk_id       = RCC_TIMER6,
     .type         = TIMER_BASIC,
@@ -99,7 +99,7 @@ static timer_dev timer6 = {
 /** Timer 6 device (basic) */
 timer_dev *TIMER6 = &timer6;
 
-static timer_dev timer7 = {
+timer_dev timer7 = {
     .regs         = { .bas = TIMER7_BASE },
     .clk_id       = RCC_TIMER7,
     .type         = TIMER_BASIC,
@@ -108,7 +108,7 @@ static timer_dev timer7 = {
 /** Timer 7 device (basic) */
 timer_dev *TIMER7 = &timer7;
 
-static timer_dev timer8 = {
+timer_dev timer8 = {
     .regs         = { .adv = TIMER8_BASE },
     .clk_id       = RCC_TIMER8,
     .type         = TIMER_ADVANCED,
diff --git a/STM32F4/cores/maple/libmaple/timer.h b/STM32F4/cores/maple/libmaple/timer.h
index fce6345b2..79b7d2996 100644
--- a/STM32F4/cores/maple/libmaple/timer.h
+++ b/STM32F4/cores/maple/libmaple/timer.h
@@ -113,13 +113,8 @@ typedef struct timer_bas_reg_map {
 } timer_bas_reg_map;
 
 
-#ifdef STM32F2
-  /** Timer 1 register map base pointer */
-  #define TIMER1_BASE        ((struct timer_adv_reg_map*)0x40010000)
-#else
-  /** Timer 1 register map base pointer */
-  #define TIMER1_BASE        ((struct timer_adv_reg_map*)0x40012C00)
-#endif
+/** Timer 1 register map base pointer */
+#define TIMER1_BASE        ((struct timer_adv_reg_map*)0x40010000)
 /** Timer 2 register map base pointer */
 #define TIMER2_BASE        ((struct timer_gen_reg_map*)0x40000000)
 /** Timer 3 register map base pointer */
@@ -133,14 +128,8 @@ typedef struct timer_bas_reg_map {
 #define TIMER6_BASE        ((struct timer_bas_reg_map*)0x40001000)
 /** Timer 7 register map base pointer */
 #define TIMER7_BASE        ((struct timer_bas_reg_map*)0x40001400)
-
-#ifdef STM32F2
-  /** Timer 8 register map base pointer */
-  #define TIMER8_BASE        ((struct timer_adv_reg_map*)0x40010400)
-#else
-  /** Timer 8 register map base pointer */
-  #define TIMER8_BASE        ((struct timer_adv_reg_map*)0x40013400)
-#endif
+/** Timer 8 register map base pointer */
+#define TIMER8_BASE        ((struct timer_adv_reg_map*)0x40010400)
 #endif
 
 /*
diff --git a/STM32F4/cores/maple/libmaple/usart.h b/STM32F4/cores/maple/libmaple/usart.h
index 3f7c88590..282293a17 100644
--- a/STM32F4/cores/maple/libmaple/usart.h
+++ b/STM32F4/cores/maple/libmaple/usart.h
@@ -62,11 +62,7 @@ typedef struct usart_reg_map {
 } usart_reg_map;
 
 /** USART1 register map base pointer */
-#ifdef STM32F2
-  #define USART1_BASE                   ((struct usart_reg_map*)0x40011000)
-#else
-  #define USART1_BASE                   ((struct usart_reg_map*)0x40013800)
-#endif
+#define USART1_BASE                   ((struct usart_reg_map*)0x40011000)
 /** USART2 register map base pointer */
 #define USART2_BASE                     ((struct usart_reg_map*)0x40004400)
 /** USART3 register map base pointer */
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_core.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_core.h
index f58ff0601..7ac987dcb 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_core.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_core.h
@@ -26,7 +26,7 @@
 
 #include "usbd_ioreq.h"
 #include "usbd_req.h"
-#include "usbd_desc.h"
+#include <VCP\usbd_desc.h>
 
 
 
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h
index 926f42e13..b1c8cc117 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h
@@ -24,7 +24,8 @@
 #ifndef __USB_CDC_CORE_H_
 #define __USB_CDC_CORE_H_
 
-#include  "usbd_ioreq.h"
+#include <STM32_USB_Device_Library\Core\inc/usbd_ioreq.h>
+#include <STM32_USB_OTG_Driver\inc\usb_core.h>
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_core.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_core.c
index aac6776cd..8f97c5176 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_core.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_core.c
@@ -58,9 +58,10 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include "usbd_cdc_core.h"
-#include "usbd_desc.h"
-#include "usbd_req.h"
+#include <VCP\usb_conf.h>
+#include <STM32_USB_Device_Library\Class\cdc\inc\usbd_cdc_core.h>
+#include <VCP\usbd_desc.h>
+#include <STM32_USB_Device_Library\Core\inc\usbd_req.h>
 
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_core.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_core.h
index b876856a3..063a30e69 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_core.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_core.h
@@ -24,9 +24,9 @@
 #define __USBD_CORE_H
 
 /* Includes ------------------------------------------------------------------*/
-#include "usb_dcd.h"
+#include <STM32_USB_OTG_Driver/inc/usb_dcd.h>
 #include "usbd_def.h"
-#include "usbd_conf.h"
+#include <VCP\usbd_conf.h>
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_def.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_def.h
index a8c86710d..f2a31153a 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_def.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_def.h
@@ -24,7 +24,7 @@
 #ifndef __USBD_DEF_H
 #define __USBD_DEF_H
 /* Includes ------------------------------------------------------------------*/
-#include "usbd_conf.h"
+#include <VCP\usbd_conf.h>
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_req.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_req.h
index 9aa9e44a3..f9849c6f9 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_req.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_req.h
@@ -27,7 +27,7 @@
 /* Includes ------------------------------------------------------------------*/
 #include  "usbd_def.h"
 #include  "usbd_core.h"
-#include  "usbd_conf.h"
+#include  <VCP\usbd_conf.h>
 
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_core.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_core.c
index af758427d..00bb25140 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_core.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_core.c
@@ -20,11 +20,11 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include "usbd_core.h"
-#include "usbd_req.h"
-#include "usbd_ioreq.h"
-#include "usb_dcd_int.h"
-#include "usb_bsp.h"
+#include <STM32_USB_Device_Library\Core\inc\usbd_core.h>
+#include <STM32_USB_Device_Library\Core\inc\usbd_req.h>
+#include <STM32_USB_Device_Library\Core\inc\usbd_ioreq.h>
+#include <STM32_USB_OTG_Driver\inc\usb_dcd_int.h>
+#include <STM32_USB_OTG_Driver\inc\usb_bsp.h>
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
 * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_ioreq.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_ioreq.c
index 6964766bd..20ee5a0f1 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_ioreq.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_ioreq.c
@@ -20,7 +20,7 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include "usbd_ioreq.h"
+#include <STM32_USB_Device_Library\Core\inc\usbd_ioreq.h>
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
   * @{
   */
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_req.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_req.c
index f08d26c6c..5fc2e036c 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_req.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_req.c
@@ -20,9 +20,9 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include "usbd_req.h"
-#include "usbd_ioreq.h"
-#include "usbd_desc.h"
+#include <STM32_USB_Device_Library\Core\inc\usbd_req.h>
+#include <STM32_USB_Device_Library\Core\inc\usbd_ioreq.h>
+#include <VCP\usbd_desc.h>
 
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_core.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_core.h
index 82a09e15c..43c478126 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_core.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_core.h
@@ -24,7 +24,7 @@
 #define __USB_CORE_H__
 
 /* Includes ------------------------------------------------------------------*/
-#include "usb_conf.h"
+#include <VCP\usbd_conf.h>
 #include "usb_regs.h"
 #include "usb_defines.h"
 
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_defines.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_defines.h
index 8c23d72d9..ee2c1a009 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_defines.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_defines.h
@@ -24,7 +24,7 @@
 #define __USB_DEF_H__
 
 /* Includes ------------------------------------------------------------------*/
-#include  "usb_conf.h"
+#include  <VCP\usbd_conf.h>
 
 /** @addtogroup USB_OTG_DRIVER
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_otg.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_otg.h
index 54d61b827..1347f315d 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_otg.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_otg.h
@@ -23,6 +23,7 @@
 #ifndef __USB_OTG__
 #define __USB_OTG__
 
+#include "usb_core.h"
 
 /** @addtogroup USB_OTG_DRIVER
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_regs.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_regs.h
index cd71ddfaf..99f844e58 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_regs.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_regs.h
@@ -24,8 +24,8 @@
 #define __USB_OTG_REGS_H__
 
 /* Includes ------------------------------------------------------------------*/
-#include "usb_conf.h"
-
+#include <VCP\usbd_conf.h>
+#include <libmaple\libmaple_types.h>
 
 /** @addtogroup USB_OTG_DRIVER
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_core.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_core.c
index cb9eabc8c..1687afa7c 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_core.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_core.c
@@ -20,8 +20,8 @@
   */
 
 /* Includes ------------------------------------------------------------------*/
-#include "usb_bsp.h"
-#include "usb_core.h"
+#include <STM32_USB_OTG_Driver\inc\usb_bsp.h>
+#include <STM32_USB_OTG_Driver\inc\usb_core.h>
 
 
 /** @addtogroup USB_OTG_DRIVER
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd.c
index c3336cb84..dc9e53839 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd.c
@@ -20,8 +20,8 @@
   */
 
 /* Includes ------------------------------------------------------------------*/
-#include "usb_dcd.h"
-#include "usb_bsp.h"
+#include <STM32_USB_OTG_Driver\inc\usb_dcd.h>
+#include <STM32_USB_OTG_Driver\inc\usb_bsp.h>
 
 
 /** @addtogroup USB_OTG_DRIVER
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd_int.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd_int.c
index 3a49ede25..f9e561f14 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd_int.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd_int.c
@@ -20,12 +20,12 @@
   */
 
 /* Includes ------------------------------------------------------------------*/
-#include "usb_dcd_int.h"
+#include <STM32_USB_OTG_Driver\inc\usb_dcd_int.h>
 
 typedef int IRQn_Type;
 #define __NVIC_PRIO_BITS          4
 #define __Vendor_SysTickConfig    1
-#include <core_cm4.h>
+#include <VCP\core_cm4.h>
 
 
 /** @addtogroup USB_OTG_DRIVER
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/core_cm4.h b/STM32F4/cores/maple/libmaple/usbF4/VCP/core_cm4.h
index 443665c70..ff5e9a6d4 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/core_cm4.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/core_cm4.h
@@ -141,7 +141,7 @@
 #endif
 
 #include <stdint.h>                      /*!< standard types definitions                      */
-#include <core_cmInstr.h>                /*!< Core Instruction Access                         */
+#include "core_cmInstr.h"                /*!< Core Instruction Access                         */
 //#include <core_cmFunc.h>                 /*!< Core Function Access                            */
 //#include <core_cm4_simd.h>               /*!< Compiler specific SIMD Intrinsics               */
 
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/misc.c b/STM32F4/cores/maple/libmaple/usbF4/VCP/misc.c
index 9f33150cf..15a715e87 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/misc.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/misc.c
@@ -80,7 +80,7 @@ typedef unsigned char		u8;
 typedef int IRQn_Type;
 #define __NVIC_PRIO_BITS          4
 #define __Vendor_SysTickConfig    1
-#include <core_cm4.h>
+#include "core_cm4.h"
 
 /** @addtogroup STM32F4xx_StdPeriph_Driver
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_bsp.c b/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_bsp.c
index df23ccbd7..e794cb144 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_bsp.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_bsp.c
@@ -21,13 +21,13 @@
   */
 
 /* Includes ------------------------------------------------------------------*/
-#include "usb_bsp.h"
+#include <STM32_USB_OTG_Driver\inc\usb_bsp.h>
 #include "usbd_conf.h"
-#include <gpio.h>
+#include <libmaple/gpio.h>
 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
 #define OTG_FS_IRQn 67
 //typedef unsigned char uint8_t;
-#include <misc.h>
+#include "misc.h"
 
 //#include "stm32f4_discovery.h"
 
@@ -97,10 +97,10 @@ void USB_OTG_BSP_Init(USB_OTG_CORE_HANDLE *pdev)
 {
 	// ala42
 #define GPIO_AF_OTG1_FS         ((uint8_t)0xA)  /* OTG_FS Alternate Function mapping */
-	gpio_set_mode(GPIOA,11,GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
-	gpio_set_mode(GPIOA,12,GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
-	gpio_set_af_mode(GPIOA,11,GPIO_AF_OTG1_FS) ;	// OTG_FS_DM
-	gpio_set_af_mode(GPIOA,12,GPIO_AF_OTG1_FS) ;	// OTG_FS_DP
+	gpio_set_mode(BOARD_USB_DM_PIN,GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
+	gpio_set_mode(BOARD_USB_DP_PIN,GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
+	gpio_set_af_mode(BOARD_USB_DM_PIN,GPIO_AF_OTG1_FS) ;	// OTG_FS_DM
+	gpio_set_af_mode(BOARD_USB_DP_PIN,GPIO_AF_OTG1_FS) ;	// OTG_FS_DP
 #ifdef USB_OTG_FS_SOF_OUTPUT_ENABLED
 	gpio_set_mode(GPIOA, 8,GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_OSPEED_100MHZ);
 	gpio_set_af_mode(GPIOA, 8,GPIO_AF_OTG1_FS) ;		// OTG_FS_SOF
@@ -122,10 +122,10 @@ void USB_OTG_BSP_DeInit(USB_OTG_CORE_HANDLE *pdev)
 {
 	// ala42
 #define GPIO_AF0         ((uint8_t)0)  /* OTG_FS Alternate Function mapping */
-	gpio_set_mode(GPIOA,11, GPIO_MODE_INPUT);
-	gpio_set_mode(GPIOA,12, GPIO_MODE_INPUT);
-	gpio_set_af_mode(GPIOA,11,GPIO_AF0) ;	// OTG_FS_DM
-	gpio_set_af_mode(GPIOA,12,GPIO_AF0) ;	// OTG_FS_DP
+	gpio_set_mode(BOARD_USB_DM_PIN, GPIO_MODE_INPUT);
+	gpio_set_mode(BOARD_USB_DP_PIN, GPIO_MODE_INPUT);
+	gpio_set_af_mode(BOARD_USB_DM_PIN,GPIO_AF0) ;	// OTG_FS_DM
+	gpio_set_af_mode(BOARD_USB_DP_PIN,GPIO_AF0) ;	// OTG_FS_DP
 #ifdef USB_OTG_FS_SOF_OUTPUT_ENABLED
 	gpio_set_mode(GPIOA, 8,GPIO_MODE_INPUT);
 	gpio_set_af_mode(GPIOA, 8,GPIO_AF0) ;		// OTG_FS_SOF
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_conf.h b/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_conf.h
index 61b0ac50c..fd45f4db3 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_conf.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_conf.h
@@ -173,7 +173,9 @@ typedef unsigned char		u8;
 #elif defined (__ICCARM__)     /* IAR Compiler */
   #define __packed    __packed
 #elif defined   ( __GNUC__ )   /* GNU Compiler */
+ #ifndef __packed
   #define __packed    __attribute__ ((__packed__))
+ #endif
 #elif defined   (__TASKING__)  /* TASKING Compiler */
   #define __packed    __unaligned
 #endif /* __CC_ARM */
@@ -206,7 +208,9 @@ typedef unsigned char		u8;
 #elif defined (__ICCARM__)     /* IAR Compiler */
   #define __packed    __packed
 #elif defined   ( __GNUC__ )   /* GNU Compiler */
+ #ifndef __packed
   #define __packed    __attribute__ ((__packed__))
+ #endif
 #elif defined   (__TASKING__)  /* TASKING Compiler */
   #define __packed    __unaligned
 #endif /* __CC_ARM */
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.c b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.c
index b13260ee5..28a2d1ff2 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.c
@@ -255,7 +255,7 @@ typedef struct {
 
 void systemHardReset(void) {
     SCB_TypeDef* rSCB = (SCB_TypeDef *) SCB_BASE;
-    typedef void (*funcPtr)(void);
+    //typedef void (*funcPtr)(void); // not used
 
     /* Reset */
     rSCB->AIRCR = (u32)AIRCR_RESET_REQ;
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.h b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.h
index 67475e7a4..8398dbdbb 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.h
@@ -26,7 +26,7 @@
 /* Includes ------------------------------------------------------------------*/
 //#include "stm32f4xx.h"
 
-#include "usbd_cdc_core.h"
+#include <STM32_USB_Device_Library\Class\cdc\inc\usbd_cdc_core.h>
 #include "usbd_conf.h"
 
 
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_conf.h b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_conf.h
index 516a2fbb3..62a40c27c 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_conf.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_conf.h
@@ -25,6 +25,7 @@
 
 /* Includes ------------------------------------------------------------------*/
 //#include   "stm32f4_discovery.h"
+#include "usb_conf.h"
 
 /** @defgroup USB_CONF_Exported_Defines
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.c b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.c
index 537f2665c..0153858fc 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.c
@@ -20,11 +20,11 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include "usbd_core.h"
+#include <STM32_USB_Device_Library\Core\inc\usbd_core.h>
 #include "usbd_desc.h"
-#include "usbd_req.h"
+#include <STM32_USB_Device_Library\Core\inc\usbd_req.h>
 #include "usbd_conf.h"
-#include "usb_regs.h"
+#include <STM32_USB_OTG_Driver\inc\usb_regs.h>
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.h b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.h
index ed999dc62..4ae998cee 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.h
@@ -25,7 +25,7 @@
 #define __USB_DESC_H
 
 /* Includes ------------------------------------------------------------------*/
-#include "usbd_def.h"
+#include <STM32_USB_Device_Library\Core\inc\usbd_def.h>
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_usr.c b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_usr.c
index 84e8d6a54..a16ce40c5 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_usr.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_usr.c
@@ -20,8 +20,8 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include "usbd_usr.h"
-#include "usbd_ioreq.h"
+#include <STM32_USB_Device_Library\Core\inc\usbd_usr.h>
+#include <STM32_USB_Device_Library\Core\inc\usbd_ioreq.h>
 
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
diff --git a/STM32F4/cores/maple/libmaple/usbF4/usb.c b/STM32F4/cores/maple/libmaple/usbF4/usb.c
index 2c0672f6a..385071982 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/usb.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/usb.c
@@ -1,27 +1,30 @@
-#include "usbd_cdc_core.h"
-#include "usbd_usr.h"
-#include "usbd_desc.h"
+#ifndef _USBF4_USB_H_
+#define _USBF4_USB_H_
+
+
+#include <STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h>
+#include <STM32_USB_Device_Library/Core/inc/usbd_usr.h>
+#include <VCP\usbd_desc.h>
 #include "usb.h"
-#include <gpio.h>
-#include <rccF2.h>
-#include <usbd_cdc_vcp.h>
+#include <libmaple/gpio.h>
+#include <libmaple/rccF4.h>
+#include <VCP\usbd_cdc_vcp.h>
+#include <boards.h>
 
 USB_OTG_CORE_HANDLE  USB_OTG_dev;
 
 
 
-void setupUSB (void) {
-    #define USB_DISC_DEV         GPIOD
-    #define USB_DISC_PIN         11
-
-	gpio_set_mode(USB_DISC_DEV, USB_DISC_PIN, GPIO_OUTPUT_OD); // ala42
+void setupUSB (void)
+{
+	gpio_set_mode(BOARD_USB_DP_PIN, GPIO_OUTPUT_OD); // ala42
 #ifdef USB_DISC_OD
   //gpio_set_mode(USB_DISC_DEV, USB_DISC_PIN, GPIO_OUTPUT_OD); // ala42
 #else
   //gpio_set_mode(USB_DISC_DEV, USB_DISC_PIN, GPIO_OUTPUT_PP); // ala42 for active pull-up on disconnect pin
 #endif
 
-  gpio_write_bit(USB_DISC_DEV, USB_DISC_PIN,0); // ala42
+  gpio_clear_pin(BOARD_USB_DP_PIN); // ala42
   delay_us(200000);
 
   /* setup the apb1 clock for USB */
@@ -29,7 +32,7 @@ void setupUSB (void) {
   //pRCC->APB1ENR |= RCC_APB1ENR_USBEN;
 
   /* initialize the usb application */
-  gpio_write_bit(USB_DISC_DEV, USB_DISC_PIN, 1); // ala42 // presents us to the host
+  gpio_set_pin(BOARD_USB_DP_PIN); // ala42 // presents us to the host
   USBD_Init(&USB_OTG_dev,
             USB_OTG_FS_CORE_ID,
             &USR_desc,
@@ -93,7 +96,7 @@ RESULT usbPowerOff(void) {
 
 void usbDsbISR(void) {};
 
-#include "usb_dcd_int.h"
+#include <STM32_USB_OTG_Driver\inc\usb_dcd_int.h>
 void __irq_OTG_FS_IRQHandler(void)
 {
   USBD_OTG_ISR_Handler (&USB_OTG_dev);
@@ -102,3 +105,5 @@ void __irq_OTG_FS_IRQHandler(void)
 void x__irq_usbwakeup(void)
 {
 }
+
+#endif
diff --git a/STM32F4/cores/maple/libmaple/usbF4/usb.h b/STM32F4/cores/maple/libmaple/usbF4/usb.h
index f09f2bd0c..ce1a5585f 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/usb.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/usb.h
@@ -5,7 +5,7 @@
 extern "C" {
 #endif
 
-#include "usb_conf.h"
+#include <VCP\usb_conf.h>
 
 typedef enum _RESULT
 {
diff --git a/STM32F4/cores/maple/libmaple/util.c b/STM32F4/cores/maple/libmaple/util.c
index 8c03e1865..8a745e87d 100644
--- a/STM32F4/cores/maple/libmaple/util.c
+++ b/STM32F4/cores/maple/libmaple/util.c
@@ -128,7 +128,7 @@ void throb(void) {
     uint32 TOP_CNT = 0x0800;
     uint32 i       = 0;
 
-    gpio_set_mode(ERROR_LED_PORT, ERROR_LED_PIN, GPIO_OUTPUT_PP);
+    gpio_set_mode(ERROR_LED_PIN, GPIO_OUTPUT_PP);
     /* Error fade. */
     while (1) {
         if (CC == TOP_CNT)  {
@@ -143,9 +143,9 @@ void throb(void) {
         }
 
         if (i < CC) {
-            gpio_write_bit(ERROR_LED_PORT, ERROR_LED_PIN, 1);
+            gpio_set_pin(ERROR_LED_PIN);
         } else {
-            gpio_write_bit(ERROR_LED_PORT, ERROR_LED_PIN, 0);
+            gpio_clear_pin(ERROR_LED_PIN);
         }
         i++;
     }
diff --git a/STM32F4/cores/maple/libmaple/util.h b/STM32F4/cores/maple/libmaple/util.h
index 62ad8af37..c5ed2de07 100644
--- a/STM32F4/cores/maple/libmaple/util.h
+++ b/STM32F4/cores/maple/libmaple/util.h
@@ -29,11 +29,12 @@
  * @brief Miscellaneous utility macros and procedures.
  */
 
-#include "libmaple_types.h"
-
 #ifndef _UTIL_H_
 #define _UTIL_H_
 
+#include "libmaple_types.h"
+#include "delay.h"
+
 #ifdef __cplusplus
 extern "C"{
 #endif
diff --git a/STM32F4/cores/maple/pwm.cpp b/STM32F4/cores/maple/pwm.cpp
index 1806348c2..c5f2ccbc6 100644
--- a/STM32F4/cores/maple/pwm.cpp
+++ b/STM32F4/cores/maple/pwm.cpp
@@ -28,8 +28,8 @@
  *  @brief Arduino-style PWM implementation.
  */
 
-#include "libmaple_types.h"
-#include "timer.h"
+#include <libmaple/libmaple_types.h>
+#include <libmaple/timer.h>
 
 #include "boards.h"
 #include "pwm.h"
diff --git a/STM32F4/cores/maple/usb_serial.cpp b/STM32F4/cores/maple/usb_serial.cpp
index cc726c2e2..fadcb91af 100644
--- a/STM32F4/cores/maple/usb_serial.cpp
+++ b/STM32F4/cores/maple/usb_serial.cpp
@@ -33,6 +33,8 @@
 #include "wirish.h"
 #include "usb.h"
 
+#ifdef SERIAL_USB
+
 #define USB_TIMEOUT 50
 
 USBSerial::USBSerial(void) {
@@ -132,7 +134,7 @@ uint8 USBSerial::pending(void) {
     return usbGetPending();
 }
 
-uint8 USBSerial::isConnected(void) {
+USBSerial::operator bool() {
     return usbIsConnected() && usbIsConfigured();
 }
 
@@ -153,3 +155,5 @@ void USBSerial::disableBlockingTx(void) {
 }
 
 USBSerial SerialUSB;
+
+#endif
diff --git a/STM32F4/cores/maple/usb_serial.h b/STM32F4/cores/maple/usb_serial.h
index a551e9d4b..8eeed966a 100644
--- a/STM32F4/cores/maple/usb_serial.h
+++ b/STM32F4/cores/maple/usb_serial.h
@@ -33,6 +33,8 @@
 
 #include "Stream.h"
 
+#ifdef SERIAL_USB
+
 /**
  * @brief Virtual serial terminal.
  */
@@ -57,7 +59,8 @@ class USBSerial : public Stream {
 
     uint8 getRTS();
     uint8 getDTR();
-    uint8 isConnected();
+	operator bool();
+	uint8 isConnected() { return (bool) *this; }
     uint8 pending();
 
     void enableBlockingTx(void);
@@ -65,6 +68,14 @@ class USBSerial : public Stream {
 };
 
 extern USBSerial SerialUSB;
+#define Serial SerialUSB
+
+#else //  _USB_SERIAL_H_
+
+#define Serial Serial1
+
+#endif //  SERIAL_USB
+
 
-#endif
+#endif //  _USB_SERIAL_H_
 
diff --git a/STM32F4/cores/maple/wirish.h b/STM32F4/cores/maple/wirish.h
index 4aca74c0b..945e8fb94 100644
--- a/STM32F4/cores/maple/wirish.h
+++ b/STM32F4/cores/maple/wirish.h
@@ -34,9 +34,9 @@
 #define _WIRISH_H_
 
 #include <stdlib.h>
-#include "libmaple.h"
+#include <stdio.h>
+#include <stdint.h>
 
-#include "wirish_types.h"
 #include "boards.h"
 #include "io.h"
 #include "bits.h"
@@ -44,10 +44,8 @@
 #include "ext_interrupts.h"
 #include "wirish_debug.h"
 #include "wirish_math.h"
-#include "wirish_time.h"
 #include <wirish_constants.h>
-#include "HardwareSPI.h"
-#include "HardwareSerial.h"
+#include <libmaple/HardwareSerial.h>
 #include "HardwareTimer.h"
 #include "usb_serial.h"
 
@@ -55,9 +53,10 @@
 #define HIGH 0x1
 #define LOW  0x0
 
-#define true 0x1
-#define false 0x0
-
+#ifndef true
+  #define true 0x1
+  #define false 0x0
+#endif
 
 #define lowByte(w)                     ((w) & 0xFF)
 #define highByte(w)                    (((w) >> 8) & 0xFF)
diff --git a/STM32F4/cores/maple/wirish_analog.cpp b/STM32F4/cores/maple/wirish_analog.cpp
index 63b5eb2d0..4e920e7c7 100644
--- a/STM32F4/cores/maple/wirish_analog.cpp
+++ b/STM32F4/cores/maple/wirish_analog.cpp
@@ -28,9 +28,7 @@
  *  @brief Arduino-compatible ADC implementation.
  */
 
-#include "libmaple.h"
 #include "wirish.h"
-#include "io.h"
 
 /* Assumes that the ADC has been initialized and that the pin is set
  * to INPUT_ANALOG */
diff --git a/STM32F4/cores/maple/wirish_constants.h b/STM32F4/cores/maple/wirish_constants.h
index 06a85ae8c..f39c0777e 100644
--- a/STM32F4/cores/maple/wirish_constants.h
+++ b/STM32F4/cores/maple/wirish_constants.h
@@ -1,5 +1,5 @@
-#ifndef _WIRING_CONSTANTS_
-#define _WIRING_CONSTANTS_
+#ifndef _WIRISH_CONSTANTS_H_
+#define _WIRISH_CONSTANTS_H_
 
 #ifdef __cplusplus
 extern "C"{
diff --git a/STM32F4/cores/maple/wirish_debug.h b/STM32F4/cores/maple/wirish_debug.h
index d4c0bab4d..d7dea2391 100644
--- a/STM32F4/cores/maple/wirish_debug.h
+++ b/STM32F4/cores/maple/wirish_debug.h
@@ -24,6 +24,9 @@
  * SOFTWARE.
  *****************************************************************************/
 
+#ifndef _WIRISH_DEBUG_H_
+#define _WIRISH_DEBUG_H_
+
 /**
  * @file wirish_debug.h
  * @brief High level debug port configuration
@@ -50,5 +53,7 @@ static inline void disableDebugPorts(void) {
  * @see disableDebugPorts()
  */
 static inline void enableDebugPorts(void) {
-    afio_cfg_debug_ports(AFIO_DEBUG_FULL_SWJ);
+    afio_cfg_debug_ports(AFIO_DEBUG_SW_ONLY); //AFIO_DEBUG_FULL_SWJ);
 }
+
+#endif
diff --git a/STM32F4/cores/maple/wirish_digital.cpp b/STM32F4/cores/maple/wirish_digital.cpp
index a8b3ad811..4a656199b 100644
--- a/STM32F4/cores/maple/wirish_digital.cpp
+++ b/STM32F4/cores/maple/wirish_digital.cpp
@@ -29,7 +29,7 @@
  */
 
 #include "wirish.h"
-#include "io.h"
+
 
 void pinMode(uint8 pin, WiringPinMode mode) {
     gpio_pin_mode outputMode;
@@ -72,7 +72,7 @@ void pinMode(uint8 pin, WiringPinMode mode) {
         return;
     }
 
-    gpio_set_mode(PIN_MAP[pin].gpio_device, PIN_MAP[pin].gpio_bit, outputMode);
+    gpio_set_mode(pin, outputMode);
 
     if (PIN_MAP[pin].timer_device != NULL) {
         /* Enable/disable timer channels if we're switching into or
@@ -84,48 +84,51 @@ void pinMode(uint8 pin, WiringPinMode mode) {
 }
 
 
-uint32 digitalRead(uint8 pin) {
+uint32 digitalRead(uint8 pin)
+{
     if (pin >= BOARD_NR_GPIO_PINS) {
         return 0;
     }
 
-    return gpio_read_bit(PIN_MAP[pin].gpio_device, PIN_MAP[pin].gpio_bit) ?
+    return gpio_read_pin(pin) ?
         HIGH : LOW;
 }
 
-void digitalWrite(uint8 pin, uint8 val) {
+void digitalWrite(uint8 pin, uint8 val)
+{
     if (pin >= BOARD_NR_GPIO_PINS) {
         return;
     }
 
-    gpio_write_bit(PIN_MAP[pin].gpio_device, PIN_MAP[pin].gpio_bit, val);
+    gpio_write_pin(pin, val);
 }
 
-void togglePin(uint8 pin) {
+void togglePin(uint8 pin)
+{
     if (pin >= BOARD_NR_GPIO_PINS) {
         return;
     }
 
-    gpio_toggle_bit(PIN_MAP[pin].gpio_device, PIN_MAP[pin].gpio_bit);
+    gpio_toggle_pin(pin);
 }
 
 #define BUTTON_DEBOUNCE_DELAY 1
 
-uint8 isButtonPressed() {
-    if (digitalRead(BOARD_BUTTON_PIN)) {
+uint8 isButtonPressed(uint8_t button) {
+    if (digitalRead(button)) {
         delay(BUTTON_DEBOUNCE_DELAY);
-        while (digitalRead(BOARD_BUTTON_PIN))
+        while (digitalRead(button))
             ;
         return true;
     }
     return false;
 }
 
-uint8 waitForButtonPress(uint32 timeout) {
+uint8 waitForButtonPress(uint8_t button, uint32 timeout) {
     uint32 start = millis();
     uint32 time;
     if (timeout == 0) {
-        while (!isButtonPressed())
+        while (!isButtonPressed(button))
             ;
         return true;
     }
@@ -136,6 +139,6 @@ uint8 waitForButtonPress(uint32 timeout) {
             time - start > timeout) {
             return false;
         }
-    } while (!isButtonPressed());
+    } while (!isButtonPressed(button));
     return true;
 }
diff --git a/STM32F4/cores/maple/wirish_math.h b/STM32F4/cores/maple/wirish_math.h
index a85b30ada..0b8b22260 100644
--- a/STM32F4/cores/maple/wirish_math.h
+++ b/STM32F4/cores/maple/wirish_math.h
@@ -29,8 +29,8 @@
  * @brief Includes <math.h>; provides Arduino-compatible math routines.
  */
 
-#ifndef _WIRING_MATH_H_
-#define _WIRING_MATH_H_
+#ifndef _WIRISH_MATH_H_
+#define _WIRISH_MATH_H_
 
 #include <math.h>
 
diff --git a/STM32F4/cores/maple/wirish_time.cpp b/STM32F4/cores/maple/wirish_time.cpp
index 270da28ac..654c1a2d2 100644
--- a/STM32F4/cores/maple/wirish_time.cpp
+++ b/STM32F4/cores/maple/wirish_time.cpp
@@ -28,10 +28,10 @@
  *  @brief Delay implementation.
  */
 
-#include "libmaple.h"
-#include "systick.h"
+#include <libmaple/libmaple.h>
+#include <libmaple/systick.h>
 #include "wirish_time.h"
-#include "delay.h"
+#include <libmaple/delay.h>
 
 void delay(unsigned long ms) {
     uint32 i;
diff --git a/STM32F4/cores/maple/wirish_time.h b/STM32F4/cores/maple/wirish_time.h
index 20a2fbfc4..3a117863c 100644
--- a/STM32F4/cores/maple/wirish_time.h
+++ b/STM32F4/cores/maple/wirish_time.h
@@ -32,10 +32,9 @@
 #ifndef __WIRISH_TIME_H_
 #define __WIRISH_TIME_H_
 
-#include "libmaple.h"
-#include "nvic.h"
-#include "systick.h"
 #include "boards.h"
+#include <libmaple/nvic.h>
+#include <libmaple/systick.h>
 
 #define US_PER_MS               1000
 
diff --git a/STM32F4/cores/maple/wirish_types.h b/STM32F4/cores/maple/wirish_types.h
index a3c260a73..de685bf9f 100644
--- a/STM32F4/cores/maple/wirish_types.h
+++ b/STM32F4/cores/maple/wirish_types.h
@@ -30,14 +30,13 @@
  * @brief  Wirish library type definitions.
  */
 
-#include "libmaple_types.h"
-#include "gpio.h"
-#include "timer.h"
-#include "adc.h"
-
 #ifndef _WIRISH_TYPES_H_
 #define _WIRISH_TYPES_H_
 
+#include <libmaple/gpio_def.h>
+#include <libmaple/timer.h>
+#include <libmaple/adc.h>
+
 /**
  * Invalid stm32_pin_info adc_channel value.
  * @see stm32_pin_info
@@ -48,16 +47,28 @@
  * @brief Stores STM32-specific information related to a given Maple pin.
  * @see PIN_MAP
  */
+#ifdef BOARD_generic_f407v
+// restructure members to build consecutive pairs
 typedef struct stm32_pin_info {
-    gpio_dev *gpio_device;      /**< Maple pin's GPIO device */
+    const gpio_dev * gpio_device;      /**< Maple pin's GPIO device */
+    timer_dev * timer_device;    /**< Pin's timer device, if any. */
+    uint8 timer_channel;        /**< Timer channel, or 0 if none. */
+    uint8 adc_channel;          /**< Pin ADC channel, or ADCx if none. */
+    const adc_dev *adc_device;  /**< ADC device, if any. */
+} stm32_pin_info;
+
+#else
+
+typedef struct stm32_pin_info {
+    const gpio_dev *gpio_device;      /**< Maple pin's GPIO device */
     timer_dev *timer_device;    /**< Pin's timer device, if any. */
     const adc_dev *adc_device;  /**< ADC device, if any. */
-    uint8 gpio_bit;             /**< Pin's GPIO port bit. */
     uint8 timer_channel;        /**< Timer channel, or 0 if none. */
     uint8 adc_channel;          /**< Pin ADC channel, or ADCx if none. */
-    uint8 filler;
 } stm32_pin_info;
 
+#endif
+
 /**
  * Variable attribute, instructs the linker to place the marked
  * variable in Flash instead of RAM. */
diff --git a/STM32F4/libraries/SPI/library.properties b/STM32F4/libraries/SPI/library.properties
index 6f20f0185..ba3a57704 100644
--- a/STM32F4/libraries/SPI/library.properties
+++ b/STM32F4/libraries/SPI/library.properties
@@ -7,3 +7,4 @@ paragraph=SPI for STM32F4
 category=Communication
 url=
 architectures=STM32F4
+maintainer=
\ No newline at end of file
diff --git a/STM32F4/libraries/SPI/src/SPI.cpp b/STM32F4/libraries/SPI/src/SPI.cpp
index 08fbbd5d7..cb8f561c9 100644
--- a/STM32F4/libraries/SPI/src/SPI.cpp
+++ b/STM32F4/libraries/SPI/src/SPI.cpp
@@ -40,9 +40,9 @@
 #include "wirish.h"
 #include "boards.h"
 
-//#include "HardwareSerial.h"
+#define DMA_TIMEOUT 100
 
-#if CYCLES_PER_MICROSECOND != 72
+#if CYCLES_PER_MICROSECOND != 168
 /* TODO [0.2.0?] something smarter than this */
 #warning "Unexpected clock speed; SPI frequency calculation will be incorrect"
 #endif
@@ -91,77 +91,115 @@ static const spi_pins board_spi_pins[] __FLASH__ = {
  */
 
 SPIClass::SPIClass(uint32 spi_num) {
+
+	_currentSetting=&_settings[spi_num-1];// SPI channels are called 1 2 and 3 but the array is zero indexed
+
+	
     switch (spi_num) {
 #if BOARD_NR_SPI >= 1
     case 1:
-        this->spi_d = SPI1;
+        _currentSetting->spi_d = SPI1;
         break;
 #endif
 #if BOARD_NR_SPI >= 2
     case 2:
-        this->spi_d = SPI2;
+        _currentSetting->spi_d = SPI2;
         break;
 #endif
 #if BOARD_NR_SPI >= 3
     case 3:
-        this->spi_d = SPI3;
+        _currentSetting->spi_d = SPI3;
         break;
 #endif
     default:
         ASSERT(0);
     }
 	
-    //pinMode(BOARD_SPI_DEFAULT_SS,OUTPUT);
-    
-    clockDivider = SPI_BAUD_PCLK_DIV_16;
-    dataMode = SPI_MODE0;
+	// Init things specific to each SPI device
+	// clock divider setup is a bit of hack, and needs to be improved at a later date.
+/*****************************************************************************/
+//           DMA / Channel / Stream 
+//            Rx             Tx
+// SPI1:  2 / 3 / 0 (2) - 2 / 3 / 3 (5)
+// SPI2:  1 / 0 / 3     - 1 / 0 / 4
+// SPI3:  1 / 0 / 0 (2) - 1 / 0 / 5 (7)
+/*****************************************************************************/
+	_settings[0].spi_d = SPI1;
+	_settings[0].clockDivider = determine_baud_rate(_settings[0].spi_d, _settings[0].clock);
+#ifdef SPI_DMA
+	_settings[0].spiDmaDev = DMA2;
+	_settings[0].spiDmaChannel = DMA_CH3;
+	_settings[0].spiRxDmaStream  = DMA_STREAM0; // alternative: DMA_STREAM2
+	_settings[0].spiTxDmaStream  = DMA_STREAM3; // alternative: DMA_STREAM5
+#endif
+	_settings[1].spi_d = SPI2;
+	_settings[1].clockDivider = determine_baud_rate(_settings[1].spi_d, _settings[1].clock);
+#ifdef SPI_DMA
+	_settings[1].spiDmaDev = DMA1;
+	_settings[1].spiDmaChannel = DMA_CH0;
+	_settings[1].spiRxDmaStream  = DMA_STREAM3; // alternative: -
+	_settings[1].spiTxDmaStream  = DMA_STREAM4; // alternative: -
+#endif
+#if BOARD_NR_SPI >= 3
+	_settings[2].spi_d = SPI3;
+	_settings[2].clockDivider = determine_baud_rate(_settings[2].spi_d, _settings[2].clock);
+#ifdef SPI_DMA
+	_settings[2].spiDmaDev = DMA1;
+	_settings[2].spiDmaChannel = DMA_CH0;
+	_settings[2].spiRxDmaStream  = DMA_STREAM0; // alternative: DMA_STREAM2
+	_settings[2].spiTxDmaStream  = DMA_STREAM5; // alternative: DMA_STREAM7
+#endif
+#endif
+
 }
 
 /*
  * Set up/tear down
  */
-
-void SPIClass::begin(void) {
-
-    uint32 flags = ((bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | SPI_DFF_8_BIT | SPI_SW_SLAVE | SPI_SOFT_SS);
-    spi_init(spi_d);
-    configure_gpios(spi_d, 1);
+void SPIClass::updateSettings(void) {
+	uint32 flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | _currentSetting->dataSize | SPI_SW_SLAVE | SPI_SOFT_SS);
 	#ifdef SPI_DEBUG
-	Serial.print("spi_master_enable("); Serial.print(clockDivider); Serial.print(","); Serial.print(dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
+	Serial.print("spi_master_enable("); Serial.print(_currentSetting->clockDivider); Serial.print(","); Serial.print(_currentSetting->dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
 	#endif
-    spi_master_enable(spi_d, (spi_baud_rate)clockDivider, (spi_mode)dataMode, flags);
+	spi_master_enable(_currentSetting->spi_d, (spi_baud_rate)_currentSetting->clockDivider, (spi_mode)_currentSetting->dataMode, flags);
+}
+
+void SPIClass::begin(void) {
+    spi_init(_currentSetting->spi_d);
+    configure_gpios(_currentSetting->spi_d, 1);
+    updateSettings();
+#ifdef SPI_USE_DMA_BUFFER
+	dmaSendBufferInit();
+#endif
+//Serial.println("SPI class begin - end");
 }
 
 void SPIClass::beginSlave(void) {
-    if (dataMode >= 4) {
-        ASSERT(0);
-        return;
-    }
-    uint32 flags = ((bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | SPI_DFF_8_BIT | SPI_SW_SLAVE);
-    spi_init(spi_d);
-    configure_gpios(spi_d, 0);
+    spi_init(_currentSetting->spi_d);
+    configure_gpios(_currentSetting->spi_d, 0);
+    uint32 flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | _currentSetting->dataSize | SPI_RX_ONLY);
 	#ifdef SPI_DEBUG
-	Serial.print("spi_slave_enable("); Serial.print(dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
+	Serial.print("spi_slave_enable("); Serial.print(_currentSetting->dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
 	#endif
-    spi_slave_enable(spi_d, (spi_mode)dataMode, flags);
+    spi_slave_enable(_currentSetting->spi_d, (spi_mode)_currentSetting->dataMode, flags);
 }
 
 void SPIClass::end(void) {
-    if (!spi_is_enabled(this->spi_d)) {
+    if (!spi_is_enabled(_currentSetting->spi_d)) {
         return;
     }
 
     // Follows RM0008's sequence for disabling a SPI in master/slave
     // full duplex mode.
-    while (spi_is_rx_nonempty(this->spi_d)) {
+    while (spi_is_rx_nonempty(_currentSetting->spi_d)) {
         // FIXME [0.1.0] remove this once you have an interrupt based driver
-        volatile uint16 rx __attribute__((unused)) = spi_rx_reg(this->spi_d);
+        volatile uint16 rx __attribute__((unused)) = spi_rx_reg(_currentSetting->spi_d);
     }
-    while (!spi_is_tx_empty(this->spi_d))
+    while (!spi_is_tx_empty(_currentSetting->spi_d))
         ;
-    while (spi_is_busy(this->spi_d))
+    while (spi_is_busy(_currentSetting->spi_d))
         ;
-    spi_peripheral_disable(this->spi_d);
+    spi_peripheral_disable(_currentSetting->spi_d);
 }
 
 /* Roger Clark added  3 functions */
@@ -170,8 +208,9 @@ void SPIClass::setClockDivider(uint32_t clockDivider)
 	#ifdef SPI_DEBUG
 	Serial.print("Clock divider set to "); Serial.println(clockDivider);
 	#endif
-	this->clockDivider = clockDivider;
-	this->begin();
+	_currentSetting->clockDivider = clockDivider;
+	uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_BR);
+	_currentSetting->spi_d->regs->CR1 = cr1 | (clockDivider & SPI_CR1_BR);
 }
 
 void SPIClass::setBitOrder(BitOrder bitOrder)
@@ -179,8 +218,10 @@ void SPIClass::setBitOrder(BitOrder bitOrder)
 	#ifdef SPI_DEBUG
 	Serial.print("Bit order set to "); Serial.println(bitOrder);
 	#endif
-	this->bitOrder = bitOrder;
-	this->begin();
+	_currentSetting->bitOrder = bitOrder;
+	uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_LSBFIRST);
+	if ( bitOrder==LSBFIRST )	cr1 |= SPI_CR1_LSBFIRST;
+	_currentSetting->spi_d->regs->CR1 = cr1;
 }
 
 /*	Victor Perez. Added to test changing datasize from 8 to 16 bit modes on the fly.
@@ -189,11 +230,11 @@ void SPIClass::setBitOrder(BitOrder bitOrder)
 */
 void SPIClass::setDataSize(uint32 datasize)
 {
-		uint32 cr1 = this->spi_d->regs->CR1; 
-		datasize &= SPI_CR1_DFF;
-		cr1 &= ~(SPI_CR1_DFF); 
-		cr1 |= datasize;  
-		this->spi_d->regs->CR1 = cr1; 
+	_currentSetting->dataSize = datasize;
+	uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_DFF);
+	uint8 en = spi_is_enabled(_currentSetting->spi_d);
+	spi_peripheral_disable(_currentSetting->spi_d);
+	_currentSetting->spi_d->regs->CR1 = cr1 | (datasize & SPI_CR1_DFF) | en;
 }
 
 void SPIClass::setDataMode(uint8_t dataMode)
@@ -212,13 +253,11 @@ SPI Mode 	CPOL 	CPHA 	Shift SCK-edge 	Capture SCK-edge
 On the STM32 it appears to be
 
 bit 1 - CPOL : Clock polarity
-
     (This bit should not be changed when communication is ongoing)
     0 : CLK to 0 when idle
     1 : CLK to 1 when idle
  
 bit 0 - CPHA : Clock phase
-
     (This bit should not be changed when communication is ongoing)
     0 : The first clock transition is the first data capture edge
     1 : The second clock transition is the first data capture edge
@@ -228,44 +267,32 @@ If someone finds this is not the case or sees a logic error with this let me kno
 	#ifdef SPI_DEBUG
 	Serial.print("Data mode set to "); Serial.println(dataMode);
 	#endif
-	this->dataMode = dataMode;
-	this->begin();
-}	
-
+	_currentSetting->dataMode = dataMode;
+	uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_CPOL|SPI_CR1_CPHA);
+	_currentSetting->spi_d->regs->CR1 = cr1 | (dataMode & (SPI_CR1_CPOL|SPI_CR1_CPHA));
+}
 
 void SPIClass::beginTransaction(uint8_t pin, SPISettings settings)
 {
 	#ifdef SPI_DEBUG
 	Serial.println("SPIClass::beginTransaction");
 	#endif
-	//_SSPin=pin;
-	//pinMode(_SSPin,OUTPUT);
-	//digitalWrite(_SSPin,LOW);
 	setBitOrder(settings.bitOrder);
 	setDataMode(settings.dataMode);
-	setClockDivider(determine_baud_rate(spi_d, settings.clock));
+	setDataSize(settings.dataSize);
+	setClockDivider(determine_baud_rate(_currentSetting->spi_d, settings.clock));
 	begin();
-#if 0
-// code from SAM core	
-	uint8_t mode = interruptMode;
-	if (mode > 0) {
-		if (mode < 16) {
-			if (mode & 1) PIOA->PIO_IDR = interruptMask[0];
-			if (mode & 2) PIOB->PIO_IDR = interruptMask[1];
-			if (mode & 4) PIOC->PIO_IDR = interruptMask[2];
-			if (mode & 8) PIOD->PIO_IDR = interruptMask[3];
-		} else {
-			interruptSave = interruptsStatus();
-			noInterrupts();
-		}
-	}
-	uint32_t ch = BOARD_PIN_TO_SPI_CHANNEL(pin);
-	bitOrder[ch] = settings.border;
-	SPI_ConfigureNPCS(spi, ch, settings.config);
-	//setBitOrder(pin, settings.border);
-	//setDataMode(pin, settings.datamode);
-	//setClockDivider(pin, settings.clockdiv);
-#endif
+}
+
+void SPIClass::beginTransactionSlave(SPISettings settings)
+{
+	#ifdef SPI_DEBUG
+	Serial.println(F("SPIClass::beginTransactionSlave"));
+	#endif
+	setBitOrder(settings.bitOrder);
+	setDataMode(settings.dataMode);
+	setDataSize(settings.dataSize);
+	beginSlave();
 }
 
 void SPIClass::endTransaction(void)
@@ -295,131 +322,154 @@ void SPIClass::endTransaction(void)
  * I/O
  */
 
-uint8 SPIClass::read(void) {
-    uint8 buf[1];
-    this->read(buf, 1);
-    return buf[0];
+uint16 SPIClass::read(void)
+{
+	while ( spi_is_rx_nonempty(_currentSetting->spi_d)==0 ) ;
+	return (uint16)spi_rx_reg(_currentSetting->spi_d);
 }
 
-void SPIClass::read(uint8 *buf, uint32 len) {
-    uint32 rxed = 0;
-    while (rxed < len) {
-        while (!spi_is_rx_nonempty(this->spi_d))
-            ;
-        buf[rxed++] = (uint8)spi_rx_reg(this->spi_d);
-    }
+void SPIClass::read(uint8 *buf, uint32 len)
+{
+	if ( len == 0 ) return;
+	spi_rx_reg(_currentSetting->spi_d);		// clear the RX buffer in case a byte is waiting on it.
+	spi_reg_map * regs = _currentSetting->spi_d->regs;
+	// start sequence: write byte 0
+	regs->DR = 0x00FF;						// write the first byte
+	// main loop
+	while ( (--len) ) {
+		while( !(regs->SR & SPI_SR_TXE) );		// wait for TXE flag
+		noInterrupts();							// go atomic level - avoid interrupts to surely get the previously received data
+		regs->DR = 0x00FF;						// write the next data item to be transmitted into the SPI_DR register. This clears the TXE flag.
+		while ( !(regs->SR & SPI_SR_RXNE) );	// wait till data is available in the DR register
+		*buf++ = (uint8)(regs->DR);				// read and store the received byte. This clears the RXNE flag.
+		interrupts();							// let systick do its job
+	}
+	// read remaining last byte
+	while ( !(regs->SR & SPI_SR_RXNE) );	// wait till data is available in the Rx register
+	*buf++ = (uint8)(regs->DR);				// read and store the received byte
 }
 
-void SPIClass::write(uint16 data) {
-	#ifdef SPI_DEBUG
-//	Serial.print("SPIClass::write("); Serial.print(data); Serial.println(")");
-	#endif
-	//  this->write(&data, 1);
-
+void SPIClass::write(uint16 data)
+{
 	/* Added for 16bit data Victor Perez. Roger Clark 
-	 * Improved speed by just directly writing the single byte to the SPI data reg and wait for completion,	 * by taking the Tx code from transfer(byte)
-	 * The original method, of calling write(*data, length) .
+	 * Improved speed by just directly writing the single byte to the SPI data reg and wait for completion,
+	 * by taking the Tx code from transfer(byte)
 	 * This almost doubles the speed of this function.
 	 */
-  
-	spi_tx_reg(this->spi_d, data); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-	while (spi_is_tx_empty(this->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(this->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
+	spi_tx_reg(_currentSetting->spi_d, data); // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
+	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
 }
 
-//void SPIClass::write(uint8 byte) {
-  //  this->write(&byte, 1);
+void SPIClass::write(uint16 data, uint32 n)
+{
+	// Added by stevstrong: Repeatedly send same data by the specified number of times
+	spi_reg_map * regs = _currentSetting->spi_d->regs;
+	while ( (n--)>0 ) {
+		regs->DR = data; // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
+		while ( (regs->SR & SPI_SR_TXE)==0 ) ; // wait till Tx empty
+	}
+	while ( (regs->SR & SPI_SR_BSY) != 0); // wait until BSY=0 before returning 
+}
 
-	/* Roger Clark 
-	 * Improved speed by just directly writing the single byte to the SPI data reg and wait for completion,	 * by taking the Tx code from transfer(byte)
-	 * The original method, of calling write(*data, length) .
-	 * This almost doubles the speed of this function.
-	 */
-  
-//	spi_tx_reg(this->spi_d, byte); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-//	while (spi_is_tx_empty(this->spi_d) == 0); // "5. Wait until TXE=1 ..."
-//	while (spi_is_busy(this->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
-//}
+void SPIClass::write(void *data, uint32 length)
+{
+	spi_dev * spi_d = _currentSetting->spi_d;
+	spi_tx(spi_d, (void*)data, length); // data can be array of bytes or words
+	while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
+}
 
-void SPIClass::write(const uint8 *data, uint32 length) {
-	#ifdef SPI_DEBUG
-	Serial.print("SPIClass::write(data, "); Serial.print(length); Serial.println(")");
-	#endif
-    uint32 txed = 0;
-    while (txed < length) {
-        txed += spi_tx(this->spi_d, data + txed, length - txed);
-    }
-	while (spi_is_tx_empty(this->spi_d) == 0); // "4. After writing the last data item into the SPI_DR register, wait until TXE=1 ..."
-	while (spi_is_busy(this->spi_d) != 0); // "... then wait until BSY=0, this indicates that the transmission of the last data is complete."
+uint8 SPIClass::transfer(uint8 byte) const
+{
+	spi_dev * spi_d = _currentSetting->spi_d;
+	spi_rx_reg(spi_d); // read any previous data
+	spi_tx_reg(spi_d, byte); // Write the data item to be transmitted into the SPI_DR register
+	while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
+	return (uint8)spi_rx_reg(spi_d); // "... and read the last received data."
 }
 
-uint8 SPIClass::transfer(uint8 byte) const {
-	#ifdef SPI_DEBUG
-//	Serial.print("SPIClass::transfer("); Serial.print(byte); Serial.println(")");
-	#endif
-	uint8 b;
-	spi_tx_reg(this->spi_d, byte); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-  	while (spi_is_rx_nonempty(this->spi_d) == 0); // "4. Wait until RXNE=1 ..."
-  	b = spi_rx_reg(this->spi_d); // "... and read the last received data."
-  	while (spi_is_tx_empty(this->spi_d) == 0); // "5. Wait until TXE=1 ..."
-  	while (spi_is_busy(this->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
-    return b;
+uint16_t SPIClass::transfer16(uint16_t wr_data) const
+{
+	spi_dev * spi_d = _currentSetting->spi_d;
+	spi_rx_reg(spi_d); // read any previous data
+	spi_tx_reg(spi_d, wr_data); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
+	while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
+	return (uint16)spi_rx_reg(spi_d); // "... and read the last received data."
 }
+
+#ifdef SPI_DMA
 /*  Roger Clark and Victor Perez, 2015
 *	Performs a DMA SPI transfer with at least a receive buffer.
-*	If a TX buffer is not provided, FF is sent over and over for the lenght of the transfer. 
-*	On exit TX buffer is not modified, and RX buffer cotains the received data.
+*	If a TX buffer is not provided, FF is sent over and over for the length of the transfer. 
+*	On exit TX buffer is not modified, and RX buffer contains the received data.
 *	Still in progress.
 */
-uint8 SPIClass::dmaTransfer(uint8 *transmitBuf, uint8 *receiveBuf, uint16 length) {
+uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length)
+{
 	if (length == 0) return 0;
-	uint8 b;
-	if (spi_is_rx_nonempty(this->spi_d) == 1) b = spi_rx_reg(this->spi_d); //Clear the RX buffer in case a byte is waiting on it.
-	dma1_ch3_Active=true;
-    dma_init(DMA1);
-	dma_attach_interrupt(DMA1, DMA_CH3, &SPIClass::DMA1_CH3_Event);
-	
+
+	uint8 b = 0;
+
+    dma_init(_currentSetting->spiDmaDev);
+//	dma_attach_interrupt(DMA1, DMA_CH3, &SPIClass::DMA1_CH3_Event);
 	// RX
-	spi_rx_dma_enable(SPI1);
-	dma_setup_transfer(DMA1, DMA_CH2, &SPI1->regs->DR, DMA_SIZE_8BITS,
-                     receiveBuf, DMA_SIZE_8BITS, (DMA_MINC_MODE | DMA_TRNS_CMPLT));// receive buffer DMA
-	dma_set_num_transfers(DMA1, DMA_CH2, length);
-	
+	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==SPI_DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
+	dma_setup_transfer(	_currentSetting->spiDmaDev,
+						_currentSetting->spiRxDmaStream,
+						_currentSetting->spiDmaChannel,
+						dma_bit_size,
+						&_currentSetting->spi_d->regs->DR,	// peripheral address
+						receiveBuf,							// memory bank 0 address
+						NULL,								// memory bank 1 address
+						(DMA_MINC_MODE | DMA_FROM_PER | DMA_PRIO_VERY_HIGH)		// flags
+	);
+	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaStream, length);
+	dma_set_fifo_flags(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaStream, 0);
+	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaStream);
+
 	// TX
-	spi_tx_dma_enable(SPI1);	
-	if (!transmitBuf) {
-	static uint8_t ff = 0XFF;
-	transmitBuf = &ff;
-	dma_setup_transfer(DMA1, DMA_CH3, &SPI1->regs->DR, DMA_SIZE_8BITS,
-                       transmitBuf, DMA_SIZE_8BITS, (DMA_FROM_MEM | DMA_TRNS_CMPLT));// Transmit FF repeatedly
+	uint32 flags = (DMA_MINC_MODE | DMA_FROM_MEM); // | DMA_TRNS_CMPLT);
+	if ( transmitBuf==0 ) {
+		static uint8_t ff = 0XFF;
+		transmitBuf = &ff;
+		flags &= ~((uint32)DMA_MINC_MODE); // remove increment mode
 	}
-	else {
-    dma_setup_transfer(DMA1, DMA_CH3, &SPI1->regs->DR, DMA_SIZE_8BITS,
-                       transmitBuf, DMA_SIZE_8BITS, (DMA_MINC_MODE |  DMA_FROM_MEM | DMA_TRNS_CMPLT));// Transmit buffer DMA 
-	}
-	dma_set_num_transfers(DMA1, DMA_CH3, length);
-
-	dma_enable(DMA1, DMA_CH2);// enable receive
-	dma_enable(DMA1, DMA_CH3);// enable transmit
+	dma_setup_transfer(	_currentSetting->spiDmaDev,
+						_currentSetting->spiTxDmaStream,
+						_currentSetting->spiDmaChannel,
+						dma_bit_size,
+						&_currentSetting->spi_d->regs->DR,	// peripheral address
+						transmitBuf,						// memory bank 0 address
+						NULL,								// memory bank 1 address
+						flags
+	);
+	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream, length);
+	dma_set_fifo_flags(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream, 0);
+	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream);
+	// software enable sequence, see AN4031, chapter 4.3
+	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaStream);// enable receive
+	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream);// enable transmit
+	spi_rx_reg(_currentSetting->spi_d); //Clear the RX buffer in case a byte is waiting on it.
+	spi_rx_dma_enable(_currentSetting->spi_d);
+	spi_tx_dma_enable(_currentSetting->spi_d);	// must be the last enable to avoid DMA error flag
 	
-//	while (dma1_ch3_Active);
-//	if (receiveBuf) {
     uint32_t m = millis();
-    while (dma1_ch3_Active) {
-      if ((millis() - m) > 100)  {
-        dma1_ch3_Active = 0;
-		b = 2;
-		break;
-      }
+	while ((b = dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream) & DMA_ISR_TCIF)==0 ) {// wait for completion flag to be set
+		if ( b&(DMA_ISR_TEIF|DMA_ISR_DMEIF|DMA_ISR_FEIF) ) { b = 1; break; } // break on any error flag
+		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
     }
-
-//	}
-	while (spi_is_tx_empty(this->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(this->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
-    dma_disable(DMA1, DMA_CH3);
-	dma_disable(DMA1, DMA_CH2);
-	spi_rx_dma_disable(SPI1);
-	spi_tx_dma_disable(SPI1);
+	if (b & DMA_ISR_TCIF) b = 0;
+
+	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
+	// software disable sequence, see AN4031, chapter 4.1
+	spi_tx_dma_disable(_currentSetting->spi_d);
+	spi_rx_dma_disable(_currentSetting->spi_d);
+	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaStream);
+    dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream);
     return b;
 }
 
@@ -427,56 +477,45 @@ uint8 SPIClass::dmaTransfer(uint8 *transmitBuf, uint8 *receiveBuf, uint16 length
 *	Performs a DMA SPI send using a TX buffer.
 *	On exit TX buffer is not modified.
 *	Still in progress.
+*	2016 - stevstrong - reworked to automatically detect bit size from SPI setting
 */
-uint8 SPIClass::dmaSend(uint8 *transmitBuf, uint16 length, bool minc) {
+uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length, bool minc)
+{
 	if (length == 0) return 0;
-	uint32 flags = ((DMA_MINC_MODE * minc) |  DMA_FROM_MEM | DMA_TRNS_CMPLT);
-	uint8 b;
-	dma1_ch3_Active=true;
-    dma_init(DMA1);
-	dma_attach_interrupt(DMA1, DMA_CH3, &SPIClass::DMA1_CH3_Event);
-
+	uint8 b = 0;
+	dma_init(_currentSetting->spiDmaDev);
 	// TX
-	spi_tx_dma_enable(SPI1);	
-    dma_setup_transfer(DMA1, DMA_CH3, &SPI1->regs->DR, DMA_SIZE_8BITS,
-                       transmitBuf, DMA_SIZE_8BITS, flags);// Transmit buffer DMA 
-	dma_set_num_transfers(DMA1, DMA_CH3, length);
-	dma_enable(DMA1, DMA_CH3);// enable transmit
-	
-    while (dma1_ch3_Active);
-	while (spi_is_rx_nonempty(this->spi_d) == 0); // "4. Wait until RXNE=1 ..."
-  	b = spi_rx_reg(this->spi_d); // "... and read the last received data."
-	while (spi_is_tx_empty(this->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(this->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
-	dma_disable(DMA1, DMA_CH3);
-	spi_tx_dma_disable(SPI1);
-    return b;
-}
-
-uint8 SPIClass::dmaSend(uint16 *transmitBuf, uint16 length, bool minc) {
-	if (length == 0) return 0;
-	uint32 flags = ((DMA_MINC_MODE * minc) |  DMA_FROM_MEM | DMA_TRNS_CMPLT);
-	uint8 b;
-	dma1_ch3_Active=true;
-    dma_init(DMA1);
-	dma_attach_interrupt(DMA1, DMA_CH3, &SPIClass::DMA1_CH3_Event);
+	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==SPI_DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
+	dma_setup_transfer(	_currentSetting->spiDmaDev,
+						_currentSetting->spiTxDmaStream,
+						_currentSetting->spiDmaChannel,
+						dma_bit_size,
+						&_currentSetting->spi_d->regs->DR,	// peripheral address
+						transmitBuf,						// memory bank 0 address
+						NULL,								// memory bank 1 address
+						( (DMA_MINC_MODE*minc) | DMA_FROM_MEM ) //| DMA_TRNS_CMPLT ) // flags
+	);// Transmit buffer DMA 
+	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream, length);
+	dma_set_fifo_flags(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream, 0);
+	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream);
+	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream);// enable transmit
+	spi_tx_dma_enable(_currentSetting->spi_d);
+
+	uint32_t m = millis();
+	while ((b = dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream) & DMA_ISR_TCIF)==0 ) {// wait for completion flag to be set
+		if ( b&(DMA_ISR_TEIF|DMA_ISR_DMEIF|DMA_ISR_FEIF) ) { b = 1; break; } // break on any error flag
+		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
+    }
+	if (b & DMA_ISR_TCIF) b = 0;
 
-	// TX
-	spi_tx_dma_enable(SPI1);	
-    dma_setup_transfer(DMA1, DMA_CH3, &SPI1->regs->DR, DMA_SIZE_16BITS,
-                       transmitBuf, DMA_SIZE_16BITS, flags);// Transmit buffer DMA 
-	dma_set_num_transfers(DMA1, DMA_CH3, length);
-	dma_enable(DMA1, DMA_CH3);// enable transmit
-	
-    while (dma1_ch3_Active);
-	while (spi_is_rx_nonempty(this->spi_d) == 0); // "4. Wait until RXNE=1 ..."
-  	b = spi_rx_reg(this->spi_d); // "... and read the last received data."
-	while (spi_is_tx_empty(this->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(this->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
-	dma_disable(DMA1, DMA_CH3);
-	spi_tx_dma_disable(SPI1);
-    return b;
+	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
+	spi_tx_dma_disable(_currentSetting->spi_d);
+	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream);
+	return b;
 }
+#endif
+
 
 
 void SPIClass::attachInterrupt(void) {
@@ -492,19 +531,19 @@ void SPIClass::detachInterrupt(void) {
  */
 
 uint8 SPIClass::misoPin(void) {
-    return dev_to_spi_pins(this->spi_d)->miso;
+    return dev_to_spi_pins(_currentSetting->spi_d)->miso;
 }
 
 uint8 SPIClass::mosiPin(void) {
-    return dev_to_spi_pins(this->spi_d)->mosi;
+    return dev_to_spi_pins(_currentSetting->spi_d)->mosi;
 }
 
 uint8 SPIClass::sckPin(void) {
-    return dev_to_spi_pins(this->spi_d)->sck;
+    return dev_to_spi_pins(_currentSetting->spi_d)->sck;
 }
 
 uint8 SPIClass::nssPin(void) {
-    return dev_to_spi_pins(this->spi_d)->nss;
+    return dev_to_spi_pins(_currentSetting->spi_d)->nss;
 }
 
 /*
@@ -512,18 +551,13 @@ uint8 SPIClass::nssPin(void) {
  */
 
 uint8 SPIClass::send(uint8 data) {
-    uint8 buf[] = {data};
-    return this->send(buf, 1);
+    this->write(data);
+    return 1;
 }
 
 uint8 SPIClass::send(uint8 *buf, uint32 len) {
-    uint32 txed = 0;
-    uint8 ret = 0;
-    while (txed < len) {
-        this->write(buf[txed++]);
-        ret = this->read();
-    }
-    return ret;
+    this->write(buf, len);
+    return len;
 }
 
 uint8 SPIClass::recv(void) {
@@ -585,29 +619,26 @@ static void configure_gpios(spi_dev *dev, bool as_master) {
 	if(dev->clk_id <= RCC_SPI2) {
 		if(nssi) {
 			if(!as_master) {
-				gpio_set_af_mode(nssi->gpio_device,  scki->gpio_bit, 5);
+				gpio_set_af_mode(pins->nss, 5);
 			}
 		}
-		gpio_set_af_mode(scki->gpio_device,  scki->gpio_bit, 5);
-		gpio_set_af_mode(misoi->gpio_device, misoi->gpio_bit, 5);
-		gpio_set_af_mode(mosii->gpio_device, mosii->gpio_bit, 5);
+		gpio_set_af_mode(pins->sck, 5);
+		gpio_set_af_mode(pins->miso, 5);
+		gpio_set_af_mode(pins->mosi, 5);
 	} else {
 		if(nssi) {
 			if(!as_master) {
-				gpio_set_af_mode(nssi->gpio_device,  scki->gpio_bit, 6);
+				gpio_set_af_mode(pins->nss, 6);
 			}
 		}
-		gpio_set_af_mode(scki->gpio_device,  scki->gpio_bit, 6);
-		gpio_set_af_mode(misoi->gpio_device, misoi->gpio_bit, 6);
-		gpio_set_af_mode(mosii->gpio_device, mosii->gpio_bit, 6);
+		gpio_set_af_mode(pins->sck, 6);
+		gpio_set_af_mode(pins->miso, 6);
+		gpio_set_af_mode(pins->mosi, 6);
 	}
 	
 #endif
 
-    spi_config_gpios(dev, as_master, nssi->gpio_device, nssi->gpio_bit,
-                     scki->gpio_device, scki->gpio_bit, 
-                     misoi->gpio_device, misoi->gpio_bit,
-                     mosii->gpio_device, mosii->gpio_bit);
+    spi_config_gpios(dev, as_master, pins->nss, pins->sck, pins->miso, pins->mosi);
 }
 
 static const spi_baud_rate baud_rates[8] __FLASH__ = {
@@ -634,6 +665,8 @@ static spi_baud_rate determine_baud_rate(spi_dev *dev, uint32_t freq) {
     {
     	case RCC_APB2: clock = STM32_PCLK2; break; // 72 Mhz
     	case RCC_APB1: clock = STM32_PCLK1; break; // 36 Mhz
+		case RCC_AHB1: break;
+		default: break;
     }
     clock /= 2;
     i = 0;
@@ -646,4 +679,3 @@ static spi_baud_rate determine_baud_rate(spi_dev *dev, uint32_t freq) {
 
 
 //SPIClass SPI(3);
-
diff --git a/STM32F4/libraries/SPI/src/SPI.h b/STM32F4/libraries/SPI/src/SPI.h
index 490d58b2e..cabc0c260 100644
--- a/STM32F4/libraries/SPI/src/SPI.h
+++ b/STM32F4/libraries/SPI/src/SPI.h
@@ -34,18 +34,16 @@
 /* TODO [0.1.0] Remove deprecated methods. */
 
 
-
-#ifndef _SPI_H_INCLUDED
-#define _SPI_H_INCLUDED
+#ifndef _LIB_SPI_H_
+#define _LIB_SPI_H_
 
 #include <libmaple/libmaple_types.h>
 #include <libmaple/spi.h>
 #include <libmaple/dma.h>
-
-#include <boards.h>
-#include <stdint.h>
 #include <wirish.h>
 
+#define SPI_DMA
+
 // SPI_HAS_TRANSACTION means SPI has
 //   - beginTransaction()
 //   - endTransaction()
@@ -96,34 +94,61 @@
 #define SPI_MODE2 SPI_MODE_2
 #define SPI_MODE3 SPI_MODE_3
 
+#define SPI_DATA_SIZE_8BIT SPI_CR1_DFF_8_BIT
+#define SPI_DATA_SIZE_16BIT SPI_CR1_DFF_16_BIT
+
 class SPISettings {
 public:
 	SPISettings(uint32_t clock, BitOrder bitOrder, uint8_t dataMode) {
 		if (__builtin_constant_p(clock)) {
-			init_AlwaysInline(clock, bitOrder, dataMode);
+			init_AlwaysInline(clock, bitOrder, dataMode, SPI_DATA_SIZE_8BIT);
+		} else {
+			init_MightInline(clock, bitOrder, dataMode, SPI_DATA_SIZE_8BIT);
+		}
+	}
+	SPISettings(uint32_t clock, BitOrder bitOrder, uint8_t dataMode, uint32_t dataSize) {
+		if (__builtin_constant_p(clock)) {
+			init_AlwaysInline(clock, bitOrder, dataMode, dataSize);
 		} else {
-			init_MightInline(clock, bitOrder, dataMode);
+			init_MightInline(clock, bitOrder, dataMode, dataSize);
 		}
 	}
-	SPISettings() { init_AlwaysInline(4000000, MSBFIRST, SPI_MODE0); }
+	SPISettings(uint32_t clock) {
+		if (__builtin_constant_p(clock)) {
+			init_AlwaysInline(clock, MSBFIRST, SPI_MODE0, SPI_DATA_SIZE_8BIT);
+		} else {
+			init_MightInline(clock, MSBFIRST, SPI_MODE0, SPI_DATA_SIZE_8BIT);
+		}
+	}
+	SPISettings() { init_AlwaysInline(4000000, MSBFIRST, SPI_MODE0, SPI_DATA_SIZE_8BIT); }
 private:
-	void init_MightInline(uint32_t clock, BitOrder bitOrder, uint8_t dataMode) {
-		init_AlwaysInline(clock, bitOrder, dataMode);
+	void init_MightInline(uint32_t clock, BitOrder bitOrder, uint8_t dataMode, uint32_t dataSize) {
+		init_AlwaysInline(clock, bitOrder, dataMode, dataSize);
 	}
-	void init_AlwaysInline(uint32_t clock, BitOrder bitOrder, uint8_t dataMode) __attribute__((__always_inline__)) {
+	void init_AlwaysInline(uint32_t clock, BitOrder bitOrder, uint8_t dataMode, uint32_t dataSize) __attribute__((__always_inline__)) {
 		this->clock = clock;
 		this->bitOrder = bitOrder;
 		this->dataMode = dataMode;
+		this->dataSize = dataSize;
 	}
 	uint32_t clock;
 	BitOrder bitOrder;
 	uint8_t dataMode;
+	uint32_t dataSize;
+	
+	spi_dev *spi_d;
+	uint32_t clockDivider;
+
+#ifdef SPI_DMA
+	dma_dev* spiDmaDev;
+	dma_channel spiDmaChannel;
+	dma_stream spiRxDmaStream, spiTxDmaStream;
+#endif
+
 	friend class SPIClass;
 };
 
 
-volatile static bool dma1_ch3_Active;
-
 /**
  * @brief Wirish SPI interface.
  *
@@ -133,18 +158,11 @@ volatile static bool dma1_ch3_Active;
 class SPIClass {
 public:
 
-
-
     /**
      * @param spiPortNumber Number of the SPI port to manage.
      */
     SPIClass(uint32 spiPortNumber);
 
-    /*
-     * Set up/tear down
-     */
-
-
 
     /**
      * @brief Equivalent to begin(SPI_1_125MHZ, MSBFIRST, 0).
@@ -175,6 +193,8 @@ class SPIClass {
 	void beginTransaction(uint8_t pin, SPISettings settings);
 	void endTransaction(void);
 
+	void beginTransactionSlave(SPISettings settings);
+
 	void setClockDivider(uint32_t clockDivider);
 	void setBitOrder(BitOrder bitOrder);	
 	void setDataMode(uint8_t dataMode);		
@@ -195,40 +215,40 @@ class SPIClass {
      */
 
     /**
-     * @brief Return the next unread byte.
+     * @brief Return the next unread byte/word.
      *
-     * If there is no unread byte waiting, this function will block
+     * If there is no unread byte/word waiting, this function will block
      * until one is received.
      */
-    uint8 read(void);
+    uint16 read(void);
 
     /**
      * @brief Read length bytes, storing them into buffer.
      * @param buffer Buffer to store received bytes into.
-     * @param length Number of bytes to store in buffer.  This
+     * @param length Number of bytes to store in buffer. This
      *               function will block until the desired number of
      *               bytes have been read.
      */
     void read(uint8 *buffer, uint32 length);
 
     /**
-     * @brief Transmit a byte.
-     * @param data Byte to transmit.
+     * @brief Transmit one byte/word.
+     * @param data to transmit.
      */
-//    void write(uint8 data);
-
+    void write(uint16 data);	
+	
     /**
-     * @brief Transmit a half word.
+     * @brief Transmit one byte/word a specified number of times.
      * @param data to transmit.
      */
-    void write(uint16 data);	
+    void write(uint16 data, uint32 n);	
 	
     /**
-     * @brief Transmit multiple bytes.
-     * @param buffer Bytes to transmit.
-     * @param length Number of bytes in buffer to transmit.
+     * @brief Transmit multiple bytes/words.
+     * @param buffer Bytes/words to transmit.
+     * @param length Number of bytes/words in buffer to transmit.
      */
-    void write(const uint8 *buffer, uint32 length);
+    void write(void * buffer, uint32 length);
 
     /**
      * @brief Transmit a byte, then return the next unread byte.
@@ -239,9 +259,12 @@ class SPIClass {
      * @return Next unread byte.
      */
     uint8 transfer(uint8 data) const;
+    uint16_t transfer16(uint16_t data) const;
 	
+#ifdef SPI_DMA
 	/**
      * @brief Sets up a DMA Transfer for "length" bytes.
+	 * The transfer mode (8 or 16 bit mode) is evaluated from the SPI peripheral setting.
      *
      * This function transmits and receives to buffers.
      *
@@ -249,30 +272,19 @@ class SPIClass {
      * @param receiveBuf buffer Bytes to save received data. 
      * @param length Number of bytes in buffer to transmit.
 	 */
-	uint8 dmaTransfer(uint8 *transmitBuf, uint8 *receiveBuf, uint16 length);
+	uint8 dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length);
 
 	/**
-     * @brief Sets up a DMA Transmit for bytes.
-     *
-     * This function transmits and does not care about the RX fifo.
+     * @brief Sets up a DMA Transmit for SPI 8 or 16 bit transfer mode.
+	 * The transfer mode (8 or 16 bit mode) is evaluated from the SPI peripheral setting.
      *
-     * @param transmitBuf buffer Bytes to transmit,
-     * @param length Number of bytes in buffer to transmit.
-	 * @param minc Set to use Memory Increment mode, clear to use Circular mode.
-     */
-	uint8 dmaSend(uint8 *transmitBuf, uint16 length, bool minc = 1);
-	
-	/**
-     * @brief Sets up a DMA Transmit for half words.
-	 * SPI PERFIPHERAL MUST BE SET TO 16 BIT MODE BEFORE
-     *
-     * This function transmits and does not care about the RX fifo.
+     * This function only transmits and does not care about the RX fifo.
      *
      * @param data buffer half words to transmit,
      * @param length Number of bytes in buffer to transmit.
-     * @param minc Set to use Memory Increment mode (default if blank), clear to use Circular mode.
      */
-	uint8 dmaSend(uint16 *transmitBuf, uint16 length, bool minc = 1);
+	uint8 dmaSend(void * transmitBuf, uint16 length, bool minc = 1);
+#endif
 
     /*
      * Pin accessors
@@ -304,7 +316,24 @@ class SPIClass {
      * @brief Get a pointer to the underlying libmaple spi_dev for
      *        this HardwareSPI instance.
      */
-    spi_dev* c_dev(void) { return this->spi_d; }
+    spi_dev* c_dev(void) { return _currentSetting->spi_d; }
+	
+		
+	spi_dev *dev(){ return _currentSetting->spi_d;}
+	
+	 /**
+     * @brief Sets the number of the SPI peripheral to be used by
+     *        this HardwareSPI instance.
+	 *
+	 * @param spi_num Number of the SPI port. 1-2 in low density devices
+	 *			or 1-3 in high density devices.
+     */
+	
+	void setModule(int spi_num)
+	{
+		_currentSetting=&_settings[spi_num-1];// SPI channels are called 1 2 and 3 but the array is zero indexed
+	}
+
 
     /* -- The following methods are deprecated --------------------------- */
 
@@ -338,26 +367,13 @@ class SPIClass {
      */
     uint8 recv(void);
 	
-	spi_dev *dev(){ return spi_d;}
-	
-	
-	
 private:
-
-	static inline void DMA1_CH3_Event() {
-		dma1_ch3_Active = 0;
-//		dma_disable(DMA1, DMA_CH3);
-//		dma_disable(DMA1, DMA_CH2);
-		
-		// To Do. Need to wait for 
-	}
-	spi_dev *spi_d;
-	uint8_t _SSPin;
-	uint32_t clockDivider;
-	uint8_t dataMode;
-	BitOrder bitOrder;
+	SPISettings _settings[BOARD_NR_SPI];
+	SPISettings *_currentSetting;
+	
+	void updateSettings(void);
 };
 
+extern SPIClass SPI; // needed bx SdFat(EX) lib
 
-extern SPIClass SPI;//(1);// dummy params
 #endif
diff --git a/STM32F4/platform.txt b/STM32F4/platform.txt
index 99ae55549..2bb1946b0 100755
--- a/STM32F4/platform.txt
+++ b/STM32F4/platform.txt
@@ -8,17 +8,15 @@ version=0.1.0
 
 # compiler variables
 # ----------------------
-#build.gcc_ver=gcc-arm-none-eabi-4.8.3-2014q1
-
 compiler.path={runtime.tools.arm-none-eabi-gcc.path}/bin/
 compiler.c.cmd=arm-none-eabi-gcc
-compiler.c.flags=-c -g -Os -w -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
+compiler.c.flags=-c -g -Os -Wall -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
 compiler.c.elf.cmd=arm-none-eabi-g++
 compiler.c.elf.flags=-Os -Wl,--gc-sections
 compiler.S.cmd=arm-none-eabi-gcc
 compiler.S.flags=-c -g -x assembler-with-cpp -MMD
 compiler.cpp.cmd=arm-none-eabi-g++
-compiler.cpp.flags=-c -g -Os -w -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
+compiler.cpp.flags=-c -g -Os -Wall -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
 compiler.ar.cmd=arm-none-eabi-ar
 compiler.ar.flags=rcs
 compiler.objcopy.cmd=arm-none-eabi-objcopy
@@ -30,6 +28,8 @@ compiler.size.cmd=arm-none-eabi-size
 compiler.define=-DARDUINO=                            
 
 # this can be overriden in boards.txt
+build.f_cpu=168000000L
+build.mcu=cortex-m4
 build.cpu_flags=
 build.hs_flag=
 build.common_flags=-mthumb -D__STM32F4__
@@ -44,12 +44,10 @@ compiler.ar.extra_flags=
 compiler.elf2hex.extra_flags=
 
 
+##compiler.libs.c.flags="-I{build.system.path}/libmaple" "-I{build.system.path}/libmaple/include" "-I{build.system.path}/libmaple/stm32f1/include"                                                           "-I{build.system.path}/libmaple/usb/stm32f1" "-I{build.system.path}/libmaple/usb/usb_lib" 
+#compiler.libs.c.flags="-I{build.core.path}" "-I{build.core.path}/libmaple" "-I{build.core.path}/libmaple/usbF4" "-I{build.core.path}/libmaple/usbF4/STM32_USB_Device_Library/Core/inc" "-I{build.core.path}/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/inc" "-I{build.core.path}/libmaple/usbF4/STM32_USB_OTG_Driver/inc" "-I{build.core.path}/libmaple/usbF4/VCP" 
+compiler.libs.c.flags="-I{build.system.path}/libmaple" "-I{build.core.path}/libmaple/usbF4"
 
-##compiler.libs.c.flags="-I{build.system.path}/libmaple" "-I{build.system.path}/libmaple/include" "-I{build.system.path}/libmaple/stm32f1/include" "-I{build.system.path}/libmaple/stm32f1/include/series" "-I{build.system.path}/libmaple/usb/stm32f1" "-I{build.system.path}/libmaple/usb/usb_lib" 
-#compiler.libs.c.flags="-I{build.system.path}/libmaple" "-I{build.system.path}/libmaple/include" "-I{build.system.path}/libmaple/stm32f1/include"                                                           "-I{build.system.path}/libmaple/usb/stm32f1" "-I{build.system.path}/libmaple/usb/usb_lib" 
-
-
-compiler.libs.c.flags="-I{build.core.path}/libmaple" -I{build.core.path}/libmaple/usbF4 -I{build.core.path}/libmaple/usbF4/STM32_USB_Device_Library/Core/inc -I{build.core.path}/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/inc -I{build.core.path}/libmaple/usbF4/STM32_USB_OTG_Driver/inc -I{build.core.path}/libmaple/usbF4/VCP 
 
 
 
@@ -66,14 +64,13 @@ compiler.libs.c.flags="-I{build.core.path}/libmaple" -I{build.core.path}/libmapl
 # ---------------------
 
 ## Compile c files
-recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.c.flags} -mcpu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.c.extra_flags} {build.extra_flags} {compiler.libs.c.flags} {includes} "{source_file}" -o "{object_file}"
+recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.c.flags} -mcpu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.c.extra_flags} {build.extra_flags} {build.cpu_flags} {compiler.libs.c.flags} {includes} "{source_file}" -o "{object_file}"
 
 ## Compile c++ files
 recipe.cpp.o.pattern="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.flags} -mcpu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {build.cpu_flags} {build.hs_flag} {build.common_flags} {compiler.libs.c.flags} {includes} "{source_file}" -o "{object_file}"
 
 ## Compile S files
 recipe.S.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.S.flags} -mcpu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.S.extra_flags} {build.extra_flags} {build.cpu_flags} {build.hs_flag} {build.common_flags} {compiler.libs.c.flags} {includes} "{source_file}" -o "{object_file}"
-#recipe.S.o.pattern="{compiler.path}{compiler.c.cmd}" "{source_file}" -o "{object_file}"
 
 ## Create archives
 recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} {compiler.ar.extra_flags} "{archive_file_path}" "{object_file}"
@@ -92,7 +89,6 @@ recipe.objcopy.hex.pattern="{compiler.path}{compiler.elf2hex.cmd}" {compiler.elf
 
 ## Compute size
 recipe.size.pattern="{compiler.path}{compiler.size.cmd}" -A "{build.path}/{build.project_name}.elf"
-#recipe.size.regex=\.text\s+([0-9]+).*
 recipe.size.regex=^(?:\.text|\.rodata|\.ARM.exidx)\s+([0-9]+).*
 recipe.size.regex.data=^(?:\.data|\.bss|\.noinit)\s+([0-9]+).*
 
diff --git a/STM32F4/cores/maple/libmaple/gpio.c b/STM32F4/system/libmaple/Arduino.h
similarity index 79%
rename from STM32F4/cores/maple/libmaple/gpio.c
rename to STM32F4/system/libmaple/Arduino.h
index 3792220e3..cef8f089f 100644
--- a/STM32F4/cores/maple/libmaple/gpio.c
+++ b/STM32F4/system/libmaple/Arduino.h
@@ -1,7 +1,7 @@
 /******************************************************************************
  * The MIT License
  *
- * Copyright (c) 2010 Perry Hung.
+ * Copyright (c) 2010 LeafLabs LLC.
  *
  * Permission is hereby granted, free of charge, to any person
  * obtaining a copy of this software and associated documentation
@@ -24,13 +24,23 @@
  * SOFTWARE.
  *****************************************************************************/
 
-/**
- * @file gpio.c
- * @brief GPIO initialization routine
- */
+#ifndef _WIRISH_ARDUINO_H_
+#define _WIRISH_ARDUINO_H_
 
-// #ifdef STM32F2
-// #include "gpioF2.c"
-// #else
-// #include "gpioF1.c"
-// #endif
+//#warning Include Arduino.h from system\libmaple
+
+#include "wirish.h"
+
+void setup();
+void loop();
+#ifdef __cplusplus
+extern "C"{
+#endif // __cplusplus
+void yield(void);
+#ifdef __cplusplus
+}
+#endif // __cplusplus
+
+#include "variant.h"
+
+#endif
diff --git a/STM32F4/variants/generic_f407v/generic_f407v.cpp b/STM32F4/variants/generic_f407v/generic_f407v.cpp
new file mode 100644
index 000000000..c51ff9b55
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/generic_f407v.cpp
@@ -0,0 +1,81 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file   generic_f407v.cpp
+ * @author ala42
+ * @brief  generic_f407v board file.
+ */
+
+#ifdef BOARD_generic_f407v
+
+#include "generic_f407v.h"
+
+#include "wirish_types.h"
+
+//static void initSRAMChip(void);
+/*****************************************************************************/
+//  Alternate functions, see DocID022152 Rev 8, Table 9. 
+/*****************************************************************************/
+void boardInit(void) {
+/*	// remap TIMER8 to PC6-9
+	gpio_set_af_mode(GPIOC, 6, 3);
+	gpio_set_af_mode(GPIOC, 7, 3);
+	gpio_set_af_mode(GPIOC, 8, 3);
+	gpio_set_af_mode(GPIOC, 9, 3);
+
+	// remap TIMER1 to PE9,11,13,14
+	gpio_set_af_mode(GPIOE,  9, 1);
+	gpio_set_af_mode(GPIOE, 11, 1);
+	gpio_set_af_mode(GPIOE, 13, 1);
+	gpio_set_af_mode(GPIOE, 14, 1);
+
+	// remap TIMER3 to PB4,5,0,1
+	gpio_set_af_mode(GPIOB,  4, 2);
+	gpio_set_af_mode(GPIOB,  5, 2);
+	gpio_set_af_mode(GPIOB,  0, 2);
+	gpio_set_af_mode(GPIOB,  1, 2);
+
+	//gpio_set_af_mode(GPIOA, 2, 7);
+	//gpio_set_af_mode(GPIOA, 3, 7);
+*/
+	return;
+}
+
+/*
+static void initSRAMChip(void) {
+    fsmc_nor_psram_reg_map *regs = FSMC_NOR_PSRAM1_BASE;
+
+    fsmc_sram_init_gpios();
+    rcc_clk_enable(RCC_FSMC);
+
+    regs->BCR = (FSMC_BCR_WREN | FSMC_BCR_MWID_16BITS | FSMC_BCR_MTYP_SRAM |
+                 FSMC_BCR_MBKEN);
+    fsmc_nor_psram_set_addset(regs, 0);
+    fsmc_nor_psram_set_datast(regs, 3);
+}
+*/
+#endif
diff --git a/STM32F4/variants/generic_f407v/generic_f407v.h b/STM32F4/variants/generic_f407v/generic_f407v.h
new file mode 100644
index 000000000..927f9cd9c
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/generic_f407v.h
@@ -0,0 +1,163 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file   generic_f407v.h
+ * @author Marti Bolivar <mbolivar@leaflabs.com>
+ * @brief  Private include file for Maple Native in boards.h
+ *
+ * See maple.h for more information on these definitions.
+ */
+
+#ifndef _BOARD_GENERIC_F407V_H_
+#define _BOARD_GENERIC_F407V_H_
+
+#define Port2Pin(port, bit) ((port-'A')*16+bit)
+
+#define CYCLES_PER_MICROSECOND  168
+
+
+#undef  STM32_PCLK1
+#undef  STM32_PCLK2
+#define STM32_PCLK1   (CYCLES_PER_MICROSECOND*1000000/4)
+#define STM32_PCLK2   (CYCLES_PER_MICROSECOND*1000000/2)
+
+#define SYSTICK_RELOAD_VAL      (CYCLES_PER_MICROSECOND*1000-1)
+
+/*****************************************************************************/
+// Board pin definitions
+#define BOARD_USB_DM_PIN		PA11
+#define BOARD_USB_DP_PIN		PA12
+
+#define BOARD_LED_PIN           PA6 //Port2Pin('A', 6)
+#define BOARD_LED2_PIN          PA7 //Port2Pin('A', 7)
+#define BOARD_BUTTON1_PIN       PA0 //Port2Pin('A', 0)
+#define BOARD_BUTTON2_PIN       PE4 //Port2Pin('E', 4)
+#define BOARD_BUTTON3_PIN       PE3 //Port2Pin('E', 3)
+
+#define BOARD_NR_USARTS         5
+#define BOARD_USART1_TX_PIN     PA9  //Port2Pin('A', 9)
+#define BOARD_USART1_RX_PIN     PA10 //Port2Pin('A',10)
+#define BOARD_USART2_TX_PIN     PA2  //Port2Pin('A', 2)
+#define BOARD_USART2_RX_PIN     PA3  //Port2Pin('A', 3)
+#define BOARD_USART3_TX_PIN     PB10 //Port2Pin('B',10)
+#define BOARD_USART3_RX_PIN     PB11 //Port2Pin('B',11)
+#define BOARD_UART4_TX_PIN      PA0  //Port2Pin('A', 0)
+#define BOARD_UART4_RX_PIN      PA1  //Port2Pin('A', 1)
+#define BOARD_UART5_TX_PIN      PC12 //Port2Pin('C',12)
+#define BOARD_UART5_RX_PIN      PD2  //Port2Pin('D', 2)
+
+#define BOARD_NR_SPI            3
+#define BOARD_SPI1_NSS_PIN      PA4  //Port2Pin('A', 4)
+#define BOARD_SPI1_SCK_PIN      PA5  //Port2Pin('A', 5)
+#define BOARD_SPI1_MISO_PIN     PA6  //Port2Pin('A', 6)
+#define BOARD_SPI1_MOSI_PIN     PA7  //Port2Pin('A', 7)
+#define BOARD_SPI1A_NSS_PIN     PA15 //Port2Pin('A',15)
+#define BOARD_SPI1A_SCK_PIN     PB3  //Port2Pin('B', 3)
+#define BOARD_SPI1A_MISO_PIN    PB4  //Port2Pin('B', 4)
+#define BOARD_SPI1A_MOSI_PIN    PB5  //Port2Pin('B', 5)
+
+#define BOARD_SPI2_NSS_PIN      PB12 //Port2Pin('B',12)
+#define BOARD_SPI2_SCK_PIN      PB13 //Port2Pin('B',13)
+#define BOARD_SPI2_MISO_PIN     PB14 //Port2Pin('B',14)
+#define BOARD_SPI2_MOSI_PIN     PB15 //Port2Pin('B',15)
+#define BOARD_SPI2A_NSS_PIN     PB9  //Port2Pin('B', 9)
+#define BOARD_SPI2A_SCK_PIN     PB10 //Port2Pin('B',10)
+#define BOARD_SPI2A_MISO_PIN    PC2  //Port2Pin('C', 2)
+#define BOARD_SPI2A_MOSI_PIN    pc3  //Port2Pin('C', 3)
+
+#define BOARD_SPI3_NSS_PIN      PA15 //Port2Pin('A',15)
+#define BOARD_SPI3_SCK_PIN      PB3  //Port2Pin('B', 3)
+#define BOARD_SPI3_MISO_PIN     PB4  //Port2Pin('B', 4)
+#define BOARD_SPI3_MOSI_PIN     PB5  //Port2Pin('B', 5)
+/* overlap with the SDIO interface for SD card
+#define BOARD_SPI3A_NSS_PIN     PA4  //Port2Pin('A', 4)
+#define BOARD_SPI3A_SCK_PIN     PC10 //Port2Pin('C',10)
+#define BOARD_SPI3A_MISO_PIN    PC11 //Port2Pin('C',11)
+#define BOARD_SPI3A_MOSI_PIN    PC12 //Port2Pin('C',12)
+*/
+#define BOARD_SDIO_D0           PC8  //Port2Pin('C', 8)
+#define BOARD_SDIO_D1           PC9  //Port2Pin('C', 9)
+#define BOARD_SDIO_D2           PC10 //Port2Pin('C',10)
+#define BOARD_SDIO_D3           PC11 //Port2Pin('C',11)
+#define BOARD_SDIO_CK           PC12 //Port2Pin('C',12)
+#define BOARD_SDIO_CMD          PD2  //Port2Pin('D', 2)
+
+#define BOARD_NR_GPIO_PINS      80
+#define BOARD_NR_PWM_PINS       22
+#define BOARD_NR_ADC_PINS       16
+#define BOARD_NR_USED_PINS      22
+#define BOARD_JTMS_SWDIO_PIN    PA13 //Port2Pin('A',13)
+#define BOARD_JTCK_SWCLK_PIN    PA14 //Port2Pin('A',14)
+#define BOARD_JTDI_PIN          PA15 //Port2Pin('A',15)
+#define BOARD_JTDO_PIN          PB3  //Port2Pin('B', 3)
+#define BOARD_NJTRST_PIN        PB4  //Port2Pin('B', 4)
+
+/*****************************************************************************/
+// Pins reserved for the on-board hardware
+#define USB_DM_PIN		BOARD_USB_DM_PIN // PA11
+#define USB_DP_PIN		BOARD_USB_DP_PIN // PA12
+
+#define FLASH_CS_PIN	PB0
+#define FLASH_CLK_PIN	BOARD_SPI3_SCK_PIN	// PB3
+#define FLASH_DO_PIN	BOARD_SPI3_MISO_PIN	// PB4
+#define FLASH_DI_PIN	BOARD_SPI3_MOSI_PIN	// PB5
+
+#define NRF24_CLK_PIN	BOARD_SPI3_SCK_PIN	// PB3
+#define NRF24_DO_PIN	BOARD_SPI3_MISO_PIN	// PB4
+#define NRF24_DI_PIN	BOARD_SPI3_MOSI_PIN	// PB5
+#define NRF24_CE_PIN	PB6
+#define NRF24_CS_PIN	PB7
+#define NRF24_IRQ_PIN	PB8
+
+// SD card, SDIO mode
+#define SD_DAT0         BOARD_SDIO_D0	// PC8
+#define SD_DAT1         BOARD_SDIO_D1	// PC9
+#define SD_DAT2         BOARD_SDIO_D2	// PC10
+#define SD_DAT3         BOARD_SDIO_D3	// PC11
+#define SD_CLK          BOARD_SDIO_CK	// PC12
+#define SD_CMD          BOARD_SDIO_CMD	// PD2
+// SD card, SPI mode, only usable with software SPI
+#define SD_DI           BOARD_SDIO_CMD	// PD2
+#define SD_DO           BOARD_SDIO_D0	// PC8
+#define SD_CS           BOARD_SDIO_D3	// PC11
+#define SD_SCLK         BOARD_SDIO_CK	// PC12
+
+/*****************************************************************************/
+
+enum {
+PA0,PA1,PA2,PA3,PA4,PA5,PA6,PA7,PA8,PA9,PA10,PA11,PA12,PA13,PA14,PA15,
+PB0,PB1,PB2,PB3,PB4,PB5,PB6,PB7,PB8,PB9,PB10,PB11,PB12,PB13,PB14,PB15,
+PC0,PC1,PC2,PC3,PC4,PC5,PC6,PC7,PC8,PC9,PC10,PC11,PC12,PC13,PC14,PC15,
+PD0,PD1,PD2,PD3,PD4,PD5,PD6,PD7,PD8,PD9,PD10,PD11,PD12,PD13,PD14,PD15,
+PE0,PE1,PE2,PE3,PE4,PE5,PE6,PE7,PE8,PE9,PE10,PE11,PE12,PE13,PE14,PE15,
+#if 0 // not available on LQFP100 package
+PF0,PF1,PF2,PF3,PF4,PF5,PF6,PF7,PF8,PF9,PF10,PF11,PF12,PF13,PF14,PF15,
+PG0,PG1,PG2,PG3,PG4,PG5,PG6,PG7,PG8,PG9,PG10,PG11,PG12,PG13,PG14,PG15
+#endif // not available on LQFP100 package
+};
+
+#endif
diff --git a/STM32F4/variants/generic_f407v/ld/common.inc b/STM32F4/variants/generic_f407v/ld/common.inc
new file mode 100644
index 000000000..f5a0f5b6e
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/ld/common.inc
@@ -0,0 +1,219 @@
+/*
+ * Linker script for libmaple.
+ *
+ * Original author "lanchon" from ST forums, with modifications by LeafLabs.
+ */
+
+OUTPUT_FORMAT ("elf32-littlearm", "elf32-bigarm", "elf32-littlearm")
+
+/*
+ * Configure other libraries we want in the link.
+ *
+ * libgcc, libc, and libm are common across supported toolchains.
+ * However, some toolchains require additional archives which aren't
+ * present everywhere (e.g. ARM's gcc-arm-embedded releases).
+ *
+ * To hack around this, we let the build system specify additional
+ * archives by putting the right extra_libs.inc (in a directory under
+ * toolchains/) in our search path.
+ */
+GROUP(libgcc.a libc.a libm.a)
+INCLUDE extra_libs.inc
+
+/*
+ * These force the linker to search for vector table symbols.
+ *
+ * These symbols vary by STM32 family (and also within families).
+ * It's up to the build system to configure the link's search path
+ * properly for the target MCU.
+ */
+INCLUDE vector_symbols.inc
+
+/* STM32 vector table. */
+EXTERN(__stm32_vector_table)
+
+/* C runtime initialization function. */
+EXTERN(start_c)
+
+/* main entry point */
+EXTERN(main)
+
+/* Initial stack pointer value. */
+EXTERN(__msp_init)
+PROVIDE(__msp_init = ORIGIN(ram) + LENGTH(ram));
+
+/* Reset vector and chip reset entry point */
+EXTERN(__start__)
+ENTRY(__start__)
+PROVIDE(__exc_reset = __start__);
+
+/* Heap boundaries, for libmaple */
+EXTERN(_lm_heap_start);
+EXTERN(_lm_heap_end);
+
+SECTIONS
+{
+    .text :
+      {
+        __text_start__ = .;
+        /*
+         * STM32 vector table.  Leave this here.  Yes, really.
+         */
+        *(.stm32.interrupt_vector)
+
+        /*
+         * Program code and vague linking
+         */
+        *(.text .text.* .gnu.linkonce.t.*)
+        *(.plt)
+        *(.gnu.warning)
+        *(.glue_7t) *(.glue_7) *(.vfp11_veneer)
+
+        *(.ARM.extab* .gnu.linkonce.armextab.*)
+        *(.gcc_except_table)
+        *(.eh_frame_hdr)
+        *(.eh_frame)
+
+        . = ALIGN(4);
+        KEEP(*(.init))
+
+        . = ALIGN(4);
+        __preinit_array_start = .;
+        KEEP (*(.preinit_array))
+        __preinit_array_end = .;
+
+        . = ALIGN(4);
+        __init_array_start = .;
+        KEEP (*(SORT(.init_array.*)))
+        KEEP (*(.init_array))
+        __init_array_end = .;
+
+        . = ALIGN(0x4);
+        KEEP (*crtbegin.o(.ctors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .ctors))
+        KEEP (*(SORT(.ctors.*)))
+        KEEP (*crtend.o(.ctors))
+
+        . = ALIGN(4);
+        KEEP(*(.fini))
+
+        . = ALIGN(4);
+        __fini_array_start = .;
+        KEEP (*(.fini_array))
+        KEEP (*(SORT(.fini_array.*)))
+        __fini_array_end = .;
+
+        KEEP (*crtbegin.o(.dtors))
+        KEEP (*(EXCLUDE_FILE (*crtend.o) .dtors))
+        KEEP (*(SORT(.dtors.*)))
+        KEEP (*crtend.o(.dtors))
+      } > REGION_TEXT
+
+    /*
+     * End of text
+     */
+    .text.align :
+      {
+        . = ALIGN(8);
+        __text_end__ = .;
+      } > REGION_TEXT
+
+    /*
+     * .ARM.exidx exception unwinding; mandated by ARM's C++ ABI
+     */
+    __exidx_start = .;
+    .ARM.exidx :
+      {
+        *(.ARM.exidx* .gnu.linkonce.armexidx.*)
+      } > REGION_RODATA
+    __exidx_end = .;
+
+    /*
+     * .data
+     */
+    .data :
+      {
+        . = ALIGN(8);
+        __data_start__ = .;
+
+        *(.got.plt) *(.got)
+        *(.data .data.* .gnu.linkonce.d.*)
+
+        . = ALIGN(8);
+        __data_end__ = .;
+      } > REGION_DATA AT> REGION_RODATA
+
+    /*
+     * Read-only data
+     */
+    .rodata :
+      {
+        *(.rodata .rodata.* .gnu.linkonce.r.*)
+        /* .USER_FLASH: We allow users to allocate into Flash here */
+        *(.USER_FLASH)
+        /* ROM image configuration; for C startup */
+        . = ALIGN(4);
+        _lm_rom_img_cfgp = .;
+        LONG(LOADADDR(.data));
+        /*
+         * Heap: Linker scripts may choose a custom heap by overriding
+         * _lm_heap_start and _lm_heap_end. Otherwise, the heap is in
+         * internal SRAM, beginning after .bss, and growing towards
+         * the stack.
+         *
+         * I'm shoving these here naively; there's probably a cleaner way
+         * to go about this. [mbolivar]
+         */
+        _lm_heap_start = DEFINED(_lm_heap_start) ? _lm_heap_start : _end;
+        _lm_heap_end   = DEFINED(_lm_heap_end) ? _lm_heap_end : __msp_init;
+      } > REGION_RODATA
+
+    /*
+     * .bss
+     */
+    .bss :
+      {
+        . = ALIGN(8);
+        __bss_start__ = .;
+        *(.bss .bss.* .gnu.linkonce.b.*)
+        *(COMMON)
+        . = ALIGN (8);
+        __bss_end__ = .;
+        _end = __bss_end__;
+      } > REGION_BSS
+
+    /*
+     * Debugging sections
+     */
+    .stab 0 (NOLOAD) : { *(.stab) }
+    .stabstr 0 (NOLOAD) : { *(.stabstr) }
+    /* DWARF debug sections.
+     * Symbols in the DWARF debugging sections are relative to the beginning
+     * of the section so we begin them at 0.  */
+    /* DWARF 1 */
+    .debug          0 : { *(.debug) }
+    .line           0 : { *(.line) }
+    /* GNU DWARF 1 extensions */
+    .debug_srcinfo  0 : { *(.debug_srcinfo) }
+    .debug_sfnames  0 : { *(.debug_sfnames) }
+    /* DWARF 1.1 and DWARF 2 */
+    .debug_aranges  0 : { *(.debug_aranges) }
+    .debug_pubnames 0 : { *(.debug_pubnames) }
+    /* DWARF 2 */
+    .debug_info     0 : { *(.debug_info .gnu.linkonce.wi.*) }
+    .debug_abbrev   0 : { *(.debug_abbrev) }
+    .debug_line     0 : { *(.debug_line) }
+    .debug_frame    0 : { *(.debug_frame) }
+    .debug_str      0 : { *(.debug_str) }
+    .debug_loc      0 : { *(.debug_loc) }
+    .debug_macinfo  0 : { *(.debug_macinfo) }
+    /* SGI/MIPS DWARF 2 extensions */
+    .debug_weaknames 0 : { *(.debug_weaknames) }
+    .debug_funcnames 0 : { *(.debug_funcnames) }
+    .debug_typenames 0 : { *(.debug_typenames) }
+    .debug_varnames  0 : { *(.debug_varnames) }
+
+    .note.gnu.arm.ident 0 : { KEEP (*(.note.gnu.arm.ident)) }
+    .ARM.attributes 0 : { KEEP (*(.ARM.attributes)) }
+    /DISCARD/ : { *(.note.GNU-stack) }
+}
diff --git a/STM32F4/variants/generic_f407v/ld/extra_libs.inc b/STM32F4/variants/generic_f407v/ld/extra_libs.inc
new file mode 100644
index 000000000..dd2c84fa4
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/ld/extra_libs.inc
@@ -0,0 +1,7 @@
+/*
+ * Extra archives needed by ARM's GCC ARM Embedded arm-none-eabi-
+ * releases (https://launchpad.net/gcc-arm-embedded/).
+ */
+
+/* This is for the provided newlib. */
+GROUP(libnosys.a)
diff --git a/STM32F4/variants/generic_f407v/ld/flash.ld b/STM32F4/variants/generic_f407v/ld/flash.ld
new file mode 100644
index 000000000..c753a786c
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/ld/flash.ld
@@ -0,0 +1,20 @@
+/*
+ * Discovery F4 (STM32F407VGT6, high density) linker script for
+ * Flash builds.
+ */
+
+MEMORY
+{
+  ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 125K
+  rom (rx)  : ORIGIN = 0x08010000, LENGTH = 960K  /* ala42 */
+}
+
+/* GROUP(libcs4_stm32_high_density.a) */
+
+REGION_ALIAS("REGION_TEXT", rom);
+REGION_ALIAS("REGION_DATA", ram);
+REGION_ALIAS("REGION_BSS", ram);
+REGION_ALIAS("REGION_RODATA", rom);
+
+_FLASH_BUILD = 1;
+INCLUDE common.inc
diff --git a/STM32F4/variants/generic_f407v/ld/jtag.ld b/STM32F4/variants/generic_f407v/ld/jtag.ld
new file mode 100644
index 000000000..1001db518
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/ld/jtag.ld
@@ -0,0 +1,20 @@
+/*
+ * STM32F4xx high density linker script for
+ * JTAG (bare metal, no bootloader) builds.
+ */
+
+MEMORY
+{
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
+  rom (rx)  : ORIGIN = 0x08000000, LENGTH = 512K
+}
+
+/* GROUP(libcs3_stm32_high_density.a) */
+
+REGION_ALIAS("REGION_TEXT", rom);
+REGION_ALIAS("REGION_DATA", ram);
+REGION_ALIAS("REGION_BSS", ram);
+REGION_ALIAS("REGION_RODATA", rom);
+
+_FLASH_BUILD = 1;
+INCLUDE common.inc
diff --git a/STM32F4/variants/generic_f407v/ld/names.inc b/STM32F4/variants/generic_f407v/ld/names.inc
new file mode 100644
index 000000000..6d7ff6e94
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/ld/names.inc
@@ -0,0 +1,78 @@
+EXTERN(__cs3_stack)
+EXTERN(__cs3_reset)
+EXTERN(__exc_nmi)
+EXTERN(__exc_hardfault)
+EXTERN(__exc_memmanage)
+EXTERN(__exc_busfault)
+EXTERN(__exc_usagefault)
+EXTERN(__stm32reservedexception7)
+EXTERN(__stm32reservedexception8)
+EXTERN(__stm32reservedexception9)
+EXTERN(__stm32reservedexception10)
+EXTERN(__exc_svc)
+EXTERN(__exc_debug_monitor)
+EXTERN(__stm32reservedexception13)
+EXTERN(__exc_pendsv)
+EXTERN(__exc_systick)
+
+EXTERN(__irq_wwdg)
+EXTERN(__irq_pvd)
+EXTERN(__irq_tamper)
+EXTERN(__irq_rtc)
+EXTERN(__irq_flash)
+EXTERN(__irq_rcc)
+EXTERN(__irq_exti0)
+EXTERN(__irq_exti1)
+EXTERN(__irq_exti2)
+EXTERN(__irq_exti3)
+EXTERN(__irq_exti4)
+EXTERN(__irq_dma1_channel1)
+EXTERN(__irq_dma1_channel2)
+EXTERN(__irq_dma1_channel3)
+EXTERN(__irq_dma1_channel4)
+EXTERN(__irq_dma1_channel5)
+EXTERN(__irq_dma1_channel6)
+EXTERN(__irq_dma1_channel7)
+EXTERN(__irq_adc)
+EXTERN(__irq_usb_hp_can_tx)
+EXTERN(__irq_usb_lp_can_rx0)
+EXTERN(__irq_can_rx1)
+EXTERN(__irq_can_sce)
+EXTERN(__irq_exti9_5)
+EXTERN(__irq_tim1_brk)
+EXTERN(__irq_tim1_up)
+EXTERN(__irq_tim1_trg_com)
+EXTERN(__irq_tim1_cc)
+EXTERN(__irq_tim2)
+EXTERN(__irq_tim3)
+EXTERN(__irq_tim4)
+EXTERN(__irq_i2c1_ev)
+EXTERN(__irq_i2c1_er)
+EXTERN(__irq_i2c2_ev)
+EXTERN(__irq_i2c2_er)
+EXTERN(__irq_spi1)
+EXTERN(__irq_spi2)
+EXTERN(__irq_usart1)
+EXTERN(__irq_usart2)
+EXTERN(__irq_usart3)
+EXTERN(__irq_exti15_10)
+EXTERN(__irq_rtcalarm)
+EXTERN(__irq_usbwakeup)
+
+EXTERN(__irq_tim8_brk)
+EXTERN(__irq_tim8_up)
+EXTERN(__irq_tim8_trg_com)
+EXTERN(__irq_tim8_cc)
+EXTERN(__irq_adc3)
+EXTERN(__irq_fsmc)
+EXTERN(__irq_sdio)
+EXTERN(__irq_tim5)
+EXTERN(__irq_spi3)
+EXTERN(__irq_uart4)
+EXTERN(__irq_uart5)
+EXTERN(__irq_tim6)
+EXTERN(__irq_tim7)
+EXTERN(__irq_dma2_channel1)
+EXTERN(__irq_dma2_channel2)
+EXTERN(__irq_dma2_channel3)
+EXTERN(__irq_dma2_channel4_5)
diff --git a/STM32F4/variants/generic_f407v/ld/ram.ld b/STM32F4/variants/generic_f407v/ld/ram.ld
new file mode 100644
index 000000000..b57060c92
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/ld/ram.ld
@@ -0,0 +1,19 @@
+/*
+ * aeroquad32 (STM32F103VET6, high density) linker script for
+ * RAM builds.
+ */
+
+MEMORY
+{
+  ram (rwx) : ORIGIN = 0x20000C00, LENGTH = 61K
+  rom (rx)  : ORIGIN = 0x08010000, LENGTH = 0K  /* ala42 */
+}
+
+GROUP(libcs3_stm32_high_density.a)
+
+REGION_ALIAS("REGION_TEXT", ram);
+REGION_ALIAS("REGION_DATA", ram);
+REGION_ALIAS("REGION_BSS", ram);
+REGION_ALIAS("REGION_RODATA", ram);
+
+INCLUDE common.inc
diff --git a/STM32F4/variants/generic_f407v/ld/vector_symbols.inc b/STM32F4/variants/generic_f407v/ld/vector_symbols.inc
new file mode 100644
index 000000000..f8519bba4
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/ld/vector_symbols.inc
@@ -0,0 +1,78 @@
+EXTERN(__msp_init)
+EXTERN(__exc_reset)
+EXTERN(__exc_nmi)
+EXTERN(__exc_hardfault)
+EXTERN(__exc_memmanage)
+EXTERN(__exc_busfault)
+EXTERN(__exc_usagefault)
+EXTERN(__stm32reservedexception7)
+EXTERN(__stm32reservedexception8)
+EXTERN(__stm32reservedexception9)
+EXTERN(__stm32reservedexception10)
+EXTERN(__exc_svc)
+EXTERN(__exc_debug_monitor)
+EXTERN(__stm32reservedexception13)
+EXTERN(__exc_pendsv)
+EXTERN(__exc_systick)
+
+EXTERN(__irq_wwdg)
+EXTERN(__irq_pvd)
+EXTERN(__irq_tamper)
+EXTERN(__irq_rtc)
+EXTERN(__irq_flash)
+EXTERN(__irq_rcc)
+EXTERN(__irq_exti0)
+EXTERN(__irq_exti1)
+EXTERN(__irq_exti2)
+EXTERN(__irq_exti3)
+EXTERN(__irq_exti4)
+EXTERN(__irq_dma1_channel1)
+EXTERN(__irq_dma1_channel2)
+EXTERN(__irq_dma1_channel3)
+EXTERN(__irq_dma1_channel4)
+EXTERN(__irq_dma1_channel5)
+EXTERN(__irq_dma1_channel6)
+EXTERN(__irq_dma1_channel7)
+EXTERN(__irq_adc)
+EXTERN(__irq_usb_hp_can_tx)
+EXTERN(__irq_usb_lp_can_rx0)
+EXTERN(__irq_can_rx1)
+EXTERN(__irq_can_sce)
+EXTERN(__irq_exti9_5)
+EXTERN(__irq_tim1_brk)
+EXTERN(__irq_tim1_up)
+EXTERN(__irq_tim1_trg_com)
+EXTERN(__irq_tim1_cc)
+EXTERN(__irq_tim2)
+EXTERN(__irq_tim3)
+EXTERN(__irq_tim4)
+EXTERN(__irq_i2c1_ev)
+EXTERN(__irq_i2c1_er)
+EXTERN(__irq_i2c2_ev)
+EXTERN(__irq_i2c2_er)
+EXTERN(__irq_spi1)
+EXTERN(__irq_spi2)
+EXTERN(__irq_usart1)
+EXTERN(__irq_usart2)
+EXTERN(__irq_usart3)
+EXTERN(__irq_exti15_10)
+EXTERN(__irq_rtcalarm)
+EXTERN(__irq_usbwakeup)
+
+EXTERN(__irq_tim8_brk)
+EXTERN(__irq_tim8_up)
+EXTERN(__irq_tim8_trg_com)
+EXTERN(__irq_tim8_cc)
+EXTERN(__irq_adc3)
+EXTERN(__irq_fsmc)
+EXTERN(__irq_sdio)
+EXTERN(__irq_tim5)
+EXTERN(__irq_spi3)
+EXTERN(__irq_uart4)
+EXTERN(__irq_uart5)
+EXTERN(__irq_tim6)
+EXTERN(__irq_tim7)
+EXTERN(__irq_dma2_channel1)
+EXTERN(__irq_dma2_channel2)
+EXTERN(__irq_dma2_channel3)
+EXTERN(__irq_dma2_channel4_5)
diff --git a/STM32F4/variants/generic_f407v/pin_map.c b/STM32F4/variants/generic_f407v/pin_map.c
new file mode 100644
index 000000000..2189902d6
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/pin_map.c
@@ -0,0 +1,210 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file   generic_f407v.cpp
+ * @author ala42
+ * @brief  generic_f407v board file.
+ */
+
+#ifdef BOARD_generic_f407v
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+//#include "generic_f407v.h"
+
+//#include "fsmc.h"
+#include <libmaple\gpio.h>
+#include <libmaple\rcc.h>
+#include <libmaple\timer.h>
+
+#include <wirish_types.h>
+
+extern timer_dev timer1;
+extern timer_dev timer2;
+extern timer_dev timer3;
+extern timer_dev timer4;
+extern timer_dev timer5;
+extern timer_dev timer6;
+extern timer_dev timer7;
+extern timer_dev timer8;
+
+/*
+typedef struct stm32_pin_info {
+    gpio_dev *gpio_device;      // Maple pin's GPIO device
+    timer_dev *timer_device;    // Pin's timer device, if any.
+    uint8 timer_channel;        // Timer channel, or 0 if none.
+    uint8 adc_channel;          // Pin ADC channel, or ADCx if none.
+    const adc_dev *adc_device;  // ADC device, if any.
+} stm32_pin_info;
+*/
+const stm32_pin_info PIN_MAP[] = { // LQFP100 package pin
+    {&GPIOA, &timer5, 1,    0, &ADC1}, // D00/PA0  | 23 | USART2_CTS | UART4_TX       | ETH_MII_CRS      | TIM2_CH1_ETR   | TIM5_CH1       | TIM8_ETR                      | ADC123_IN0/WKUP
+    {&GPIOA, &timer5, 2,    1, &ADC1}, // D01/PA1  | 24 | USART2_RTS | UART4_RX       | ETH_RMII_REF_CLK | ETH_MII_RX_CLK | TIM5_CH2       | TIM2_CH2                      | ADC123_IN1
+    {&GPIOA, &timer5, 3,    2, &ADC1}, // D02/PA2  | 25 | USART2_TX  | TIM5_CH3       | TIM9_CH1         | TIM2_CH3       | ETH_MDIO                                       | ADC123_IN2
+    {&GPIOA, &timer5, 4,    3, &ADC1}, // D03/PA3  | 26 | USART2_RX  | TIM5_CH4       | TIM9_CH2         | TIM2_CH4       | OTG_HS_ULPI_D0 | ETH_MII_COL                   | ADC123_IN3
+    {&GPIOA,    NULL, 0,    4, &ADC1}, // D04/PA4  | 29 | SPI1_NSS   | SPI3_NSS       | USART2_CK        | DCMI_HSYNC     | OTG_HS_SOF     | I2S3_WS                       | ADC12_IN4 / DAC_OUT1
+    {&GPIOA,    NULL, 0,    5, &ADC1}, // D05/PA5  | 30 | SPI1_SCK   | OTG_HS_ULPI_CK | TIM2_CH1_ETR     | TIM8_CH1N                                                       | ADC12_IN5 / DAC_OUT2
+    {&GPIOA,    NULL, 1,    6, &ADC1}, // D06/PA6  | 31 | SPI1_MISO  | TIM8_BKIN      | TIM13_CH1        | DCMI_PIXCLK    | TIM3_CH1       | TIM1_BKIN                     | ADC12_IN6
+    {&GPIOA,    NULL, 0,    7, &ADC1}, // D07/PA7  | 32 | SPI1_MOSI  | TIM8_CH1N      | TIM14_CH1        | TIM3_CH2       | ETH_MII_RX_DV  | TIM1_CH1N   / ETH_RMII_CRS_DV | ADC12_IN7
+    {&GPIOA,    NULL, 0, ADCx,  NULL}, // D08/PA8  | 67 | MCO1       | USART1_CK      | TIM1_CH1         | I2C3_SCL       | OTG_FS_SOF
+    {&GPIOA,    NULL, 0, ADCx,  NULL}, // D09/PA9  | 68 | USART1_TX  | TIM1_CH2       | I2C3_SMBA        | DCMI_D0
+    {&GPIOA,    NULL, 0, ADCx,  NULL}, // D10/PA10 | 69 | USART1_RX  | TIM1_CH3       | OTG_FS_ID        | DCMI_D1
+    {&GPIOA,    NULL, 0, ADCx,  NULL}, // D11/PA11 | 70 | USART1_CTS | CAN1_RX        | TIM1_CH4         | OTG_FS_DM
+    {&GPIOA,    NULL, 0, ADCx,  NULL}, // D12/PA12 | 71 | USART1_RTS | CAN1_TX        | TIM1_ETR         | OTG_FS_DP
+    {&GPIOA,    NULL, 0, ADCx,  NULL}, // D13/PA13 | 72 | JTMS-SWDIO
+    {&GPIOA,    NULL, 0, ADCx,  NULL}, // D14/PA14 | 76 | JTCK-SWCLK
+    {&GPIOA, &timer2, 1, ADCx,  NULL}, // D15/PA15 | 77 | JTDI       | SPI3_NSS       | I2S3_WS          | TIM2_CH1_ETR   | SPI1_NSS
+
+    {&GPIOB, &timer3, 3,    8, &ADC1}, // D16/PB0  | 35 | TIM3_CH3   | TIM8_CH2N | OTG_HS_ULPI_D1 | ETH_MII_RXD2   | TIM1_CH2N      | ADC12_IN8
+    {&GPIOB, &timer3, 4,    9, &ADC1}, // D17/PB1  | 36 | TIM3_CH4   | TIM8_CH3N | OTG_HS_ULPI_D2 | ETH_MII_RXD3   | TIM1_CH3N      | ADC12_IN9
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D18/PB2  | 37 | BOOT1    
+    {&GPIOB, &timer2, 2, ADCx,  NULL}, // D19/PB3  | 89 | JTDO       | TRACESWO  | SPI3_SCK       | I2S3_CK        | TIM2_CH2       | SPI1_SCK
+    {&GPIOB, &timer3, 1, ADCx,  NULL}, // D20/PB4  | 90 | NJTRST     | SPI3_MISO | TIM3_CH1       | SPI1_MISO      | I2S3ext_SD
+    {&GPIOB, &timer3, 2, ADCx,  NULL}, // D21/PB5  | 91 | I2C1_SMBA  | CAN2_RX   | OTG_HS_ULPI_D7 | ETH_PPS_OUT    | TIM3_CH2       | SPI1_MOSI      | SPI3_MOSI      | DCMI_D10      | I2S3_SD
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D22/PB6  | 92 | I2C1_SCL   | TIM4_CH1  | CAN2_TX        | DCMI_D5        | USART1_TX
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D23/PB7  | 93 | I2C1_SDA   | FSMC_NL   | DCMI_VSYNC     | USART1_RX      | TIM4_CH2
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D24/PB8  | 95 | TIM4_CH3   | SDIO_D4   | TIM10_CH1      | DCMI_D6        | ETH_MII_TXD3   | I2C1_SCL       | CAN1_RX
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D25/PB9  | 96 | SPI2_NSS   | I2S2_WS   | TIM4_CH4       | TIM11_CH1      | SDIO_D5        | DCMI_D7        | I2C1_SDA       | CAN1_TX
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D26/PB10 | 47 | SPI2_SCK   | I2S2_CK   | I2C2_SCL       | USART3_TX      | OTG_HS_ULPI_D3 | ETH_MII_RX_ER  | TIM2_CH3
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D27/PB11 | 48 | I2C2_SDA   | USART3_RX | OTG_HS_ULPI_D4 | ETH_RMII_TX_EN | ETH_MII_TX_EN  | TIM2_CH4
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D28/PB12 | 51 | SPI2_NSS   | I2S2_WS   | I2C2_SMBA      | USART3_CK      | TIM1_BKIN      | CAN2_RX        | OTG_HS_ULPI_D5 | ETH_RMII_TXD0 | ETH_MII_TXD0 | OTG_HS_ID
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D29/PB13 | 52 | SPI2_SCK   | I2S2_CK   | USART3_CTS     | TIM1_CH1N      | CAN2_TX        | OTG_HS_ULPI_D6 | ETH_RMII_TXD1  | ETH_MII_TXD1
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D30/PB14 | 53 | SPI2_MISO  | TIM1_CH2N | TIM12_CH1      | OTG_HS_DM      | USART3_RTS     | TIM8_CH2N      | I2S2ext_SD
+    {&GPIOB,    NULL, 0, ADCx,  NULL}, // D31/PB15 | 54 | SPI2_MOSI  | I2S2_SD   | TIM1_CH3N      | TIM8_CH3N      | TIM12_CH2      | OTG_HS_DP
+                             
+    {&GPIOC,    NULL, 0,   10, &ADC1}, // D32/PC0  | 15 | OTG_HS_ULPI_STP                                                  | ADC123_IN10
+    {&GPIOC,    NULL, 0,   11, &ADC1}, // D33/PC1  | 16 | ETH_MDC                                                          | ADC123_IN11
+    {&GPIOC,    NULL, 0,   12, &ADC1}, // D34/PC2  | 17 | SPI2_MISO  | OTG_HS_ULPI_DIR  | ETH_MII_TXD2    | I2S2ext_SD     | ADC123_IN12
+    {&GPIOC,    NULL, 0,   13, &ADC1}, // D35/PC3  | 18 | SPI2_MOSI  | I2S2_SD          | OTG_HS_ULPI_NXT | ETH_MII_TX_CLK | ADC123_IN13
+    {&GPIOC,    NULL, 0,   14, &ADC1}, // D36/PC4  | 33 | ETH_RMII_RX_D0                | ETH_MII_RX_D0                    | ADC12_IN14
+    {&GPIOC,    NULL, 0,   15, &ADC1}, // D37/PC5  | 34 | ETH_RMII_RX_D1                | ETH_MII_RX_D1                    | ADC12_IN15
+    {&GPIOC, &timer8, 1, ADCx,  NULL}, // D38/PC6  | 63 | I2S2_MCK   | TIM8_CH1/SDIO_D6 | USART6_TX       | DCMI_D0/TIM3_CH1 
+    {&GPIOC, &timer8, 2, ADCx,  NULL}, // D39/PC7  | 64 | I2S3_MCK   | TIM8_CH2/SDIO_D7 | USART6_RX       | DCMI_D1/TIM3_CH2
+    {&GPIOC, &timer8, 3, ADCx,  NULL}, // D40/PC8  | 65 | TIM8_CH3   | SDIO_D0          | TIM3_CH3        | USART6_CK      | DCMI_D2
+    {&GPIOC, &timer8, 4, ADCx,  NULL}, // D41/PC9  | 66 | I2S_CKIN   | MCO2             | TIM8_CH4        | SDIO_D1        | I2C3_SDA  | DCMI_D3    | TIM3_CH4
+    {&GPIOC,    NULL, 0, ADCx,  NULL}, // D42/PC10 | 78 | SPI3_SCK   | I2S3_CK          | UART4_TX        | SDIO_D2        | DCMI_D8   | USART3_TX
+    {&GPIOC,    NULL, 0, ADCx,  NULL}, // D43/PC11 | 79 | UART4_RX   | SPI3_MISO        | SDIO_D3         | DCMI_D4        | USART3_RX | I2S3ext_SD
+    {&GPIOC,    NULL, 0, ADCx,  NULL}, // D44/PC12 | 80 | UART5_TX   | SDIO_CK          | DCMI_D9         | SPI3_MOSI      | I2S3_SD   | USART3_CK
+    {&GPIOC,    NULL, 0, ADCx,  NULL}, // D45/PC13 |  7 | RTC_OUT, RTC_TAMP1, RTC_TS
+    {&GPIOC,    NULL, 0, ADCx,  NULL}, // D46/PC14 |  8 | OSC32_IN
+    {&GPIOC,    NULL, 0, ADCx,  NULL}, // D47/PC15 |  9 | OSC32_OUT
+                             
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D48/PD0  | 81 | FSMC_D2    | CAN1_RX
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D49/PD1  | 82 | FSMC_D3    | CAN1_TX
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D50/PD2  | 83 | TIM3_ETR   | UART5_RX   | SDIO_CMD | DCMI_D11
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D51/PD3  | 84 | FSMC_CLK   | USART2_CTS
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D52/PD4  | 85 | FSMC_NOE   | USART2_RTS
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D53/PD5  | 86 | FSMC_NWE   | USART2_TX
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D54/PD6  | 87 | FSMC_NWAIT | USART2_RX
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D55/PD7  | 88 | USART2_CK  | FSMC_NE1   | FSMC_NCE2
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D56/PD8  | 55 | FSMC_D13   | USART3_TX
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D57/PD9  | 56 | FSMC_D14   | USART3_RX
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D58/PD10 | 57 | FSMC_D15   | USART3_CK
+    {&GPIOD,    NULL, 0, ADCx,  NULL}, // D59/PD11 | 58 | FSMC_CLE   | FSMC_A16   | USART3_CTS
+    {&GPIOD, &timer4, 1, ADCx,  NULL}, // D60/PD12 | 59 | FSMC_ALE   | FSMC_A17   | TIM4_CH1   | USART3_RTS // remap in
+    {&GPIOD, &timer4, 2, ADCx,  NULL}, // D61/PD13 | 60 | FSMC_A18                | TIM4_CH2                // remap in
+    {&GPIOD, &timer4, 3, ADCx,  NULL}, // D62/PD14 | 61 | FSMC_D0                 | TIM4_CH3                // remap in
+    {&GPIOD, &timer4, 4, ADCx,  NULL}, // D63/PD15 | 62 | FSMC_D1                 | TIM4_CH4                // remap in
+
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D64/PE0  | 97 | TIM4_ETR  | FSMC_NBL0 | DCMI_D2
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D65/PE1  | 98 | FSMC_NBL1 | DCMI_D3
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D66/PE2  |  1 | TRACECLK  | FSMC_A23  | ETH_MII_TXD3
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D67/PE3  |  2 | TRACED0   | FSMC_A19
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D68/PE4  |  3 | TRACED1   | FSMC_A20  | DCMI_D4
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D69/PE5  |  4 | TRACED2   | FSMC_A21  | TIM9_CH1     / DCMI_D6
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D70/PE6  |  5 | TRACED3   | FSMC_A22  | TIM9_CH2     / DCMI_D7
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D71/PE7  | 38 | FSMC_D4   | TIM1_ETR
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D72/PE8  | 39 | FSMC_D5   | TIM1_CH1N
+    {&GPIOE, &timer1, 1, ADCx,  NULL}, // D73/PE9  | 40 | FSMC_D6   | TIM1_CH1   // remap in
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D74/PE10 | 41 | FSMC_D7   | TIM1_CH2N
+    {&GPIOE, &timer1, 2, ADCx,  NULL}, // D75/PE11 | 42 | FSMC_D8   | TIM1_CH2   // remap in
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D76/PE12 | 43 | FSMC_D9   | TIM1_CH3N
+    {&GPIOE, &timer1, 3, ADCx,  NULL}, // D77/PE13 | 44 | FSMC_D10  | TIM1_CH3   // remap in
+    {&GPIOE, &timer1, 4, ADCx,  NULL}, // D78/PE14 | 45 | FSMC_D11  | TIM1_CH4   // remap in
+    {&GPIOE,    NULL, 0, ADCx,  NULL}, // D79/PE15 | 46 | FSMC_D12  | TIM1_BKIN
+#if 0
+    {GPIOF,  0,   NULL, 0, NULL, ADCx}, // D80/PF0
+    {GPIOF,  1,   NULL, 0, NULL, ADCx}, // D81/PF1
+    {GPIOF,  2,   NULL, 0, NULL, ADCx}, // D82/PF2
+    {GPIOF,  3,   NULL, 0, NULL, ADCx}, // D83/PF3
+    {GPIOF,  4,   NULL, 0, NULL, ADCx}, // D84/PF4
+    {GPIOF,  5,   NULL, 0, NULL, ADCx}, // D85/PF5
+    {GPIOF,  6,   NULL, 0, NULL, ADCx}, // D86/PF6
+    {GPIOF,  7,   NULL, 0, NULL, ADCx}, // D87/PF7
+    {GPIOF,  8,   NULL, 0, NULL, ADCx}, // D88/PF8
+    {GPIOF,  9,   NULL, 0, NULL, ADCx}, // D89/PF9
+    {GPIOF, 10,   NULL, 0, NULL, ADCx}, // D90/PF10
+    {GPIOF, 11,   NULL, 0, NULL, ADCx}, // D91/PF11
+    {GPIOF, 12,   NULL, 0, NULL, ADCx}, // D92/PF12
+    {GPIOF, 13,   NULL, 0, NULL, ADCx}, // D93/PF13
+    {GPIOF, 14,   NULL, 0, NULL, ADCx}, // D94/PF14
+    {GPIOF, 15,   NULL, 0, NULL, ADCx}, // D95/PF15
+
+    {GPIOG,  0,   NULL, 0, NULL, ADCx}, // D96/PG0
+    {GPIOG,  1,   NULL, 0, NULL, ADCx}, // D97/PG1
+    {GPIOG,  2,   NULL, 0, NULL, ADCx}, // D98/PG2
+    {GPIOG,  3,   NULL, 0, NULL, ADCx}, // D99/PG3
+    {GPIOG,  4,   NULL, 0, NULL, ADCx}, // D100/PG4
+    {GPIOG,  5,   NULL, 0, NULL, ADCx}, // D101/PG5
+    {GPIOG,  6,   NULL, 0, NULL, ADCx}, // D102/PG6
+    {GPIOG,  7,   NULL, 0, NULL, ADCx}, // D103/PG7 
+    {GPIOG,  8,   NULL, 0, NULL, ADCx}, // D104/PG8
+    {GPIOG,  9,   NULL, 0, NULL, ADCx}, // D105/PG9
+    {GPIOG, 10,   NULL, 0, NULL, ADCx}, // D106/PG10
+    {GPIOG, 11,   NULL, 0, NULL, ADCx}, // D107/PG11
+    {GPIOG, 12,   NULL, 0, NULL, ADCx}, // D108/PG12
+    {GPIOG, 13,   NULL, 0, NULL, ADCx}, // D109/PG13
+    {GPIOG, 14,   NULL, 0, NULL, ADCx}, // D110/PG14
+    {GPIOG, 15,   NULL, 0, NULL, ADCx}  // D111/PG15
+#endif
+};
+/* to be defined
+extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
+    0, 1, 2, 3, 15, 16, 17, 19, 20, 21, 38, 39, 49, 41, 60, 61, 62, 63, 73, 75, 77, 78
+};
+*/
+const uint8 boardADCPins[BOARD_NR_ADC_PINS] = {
+    PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PB0, PB1, PC0, PC1, PC2, PC3, PC4, PC5
+};
+
+const uint8 boardUsedPins[BOARD_NR_USED_PINS] = {
+    BOARD_LED_PIN, BOARD_LED2_PIN, BOARD_BUTTON1_PIN, BOARD_BUTTON2_PIN, BOARD_BUTTON2_PIN,
+	BOARD_JTMS_SWDIO_PIN, BOARD_JTCK_SWCLK_PIN,
+	FLASH_CS_PIN, FLASH_CLK_PIN, FLASH_DO_PIN, FLASH_DI_PIN,
+	NRF24_CE_PIN, NRF24_CS_PIN, NRF24_IRQ_PIN,
+	BOARD_SDIO_D0, BOARD_SDIO_D1, BOARD_SDIO_D2, BOARD_SDIO_D3, BOARD_SDIO_CK, BOARD_SDIO_CMD,
+	USB_DM_PIN, USB_DP_PIN
+};
+
+#ifdef __cplusplus
+}
+#endif
+
+
+#endif // BOARD_generic_f407v
diff --git a/STM32F4/variants/generic_f407v/pins_arduino.h b/STM32F4/variants/generic_f407v/pins_arduino.h
new file mode 100644
index 000000000..3052f2eb2
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/pins_arduino.h
@@ -0,0 +1,6 @@
+
+
+
+
+// API compatibility
+#include "variant.h"
\ No newline at end of file
diff --git a/STM32F4/variants/generic_f407v/stm32_isrs.S b/STM32F4/variants/generic_f407v/stm32_isrs.S
new file mode 100644
index 000000000..34e515c08
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/stm32_isrs.S
@@ -0,0 +1,323 @@
+/* STM32 ISR weak declarations */
+
+	.thumb
+
+/* Default handler for all non-overridden interrupts and exceptions */
+	.globl	__default_handler
+	.type	__default_handler, %function
+
+__default_handler:
+	b .
+
+	.weak	__exc_nmi
+	.globl	__exc_nmi
+	.set	__exc_nmi, __default_handler
+	.weak	__exc_hardfault
+	.globl	__exc_hardfault
+	.set	__exc_hardfault, __default_handler
+	.weak	__exc_memmanage
+	.globl	__exc_memmanage
+	.set	__exc_memmanage, __default_handler
+	.weak	__exc_busfault
+	.globl	__exc_busfault
+	.set	__exc_busfault, __default_handler
+	.weak	__exc_usagefault
+	.globl	__exc_usagefault
+	.set	__exc_usagefault, __default_handler
+	.weak	__stm32reservedexception7
+	.globl	__stm32reservedexception7
+	.set	__stm32reservedexception7, __default_handler
+	.weak	__stm32reservedexception8
+	.globl	__stm32reservedexception8
+	.set	__stm32reservedexception8, __default_handler
+	.weak	__stm32reservedexception9
+	.globl	__stm32reservedexception9
+	.set	__stm32reservedexception9, __default_handler
+	.weak	__stm32reservedexception10
+	.globl	__stm32reservedexception10
+	.set	__stm32reservedexception10, __default_handler
+	.weak	__exc_svc
+	.globl	__exc_svc
+	.set	__exc_svc, __default_handler
+	.weak	__exc_debug_monitor
+	.globl	__exc_debug_monitor
+	.set	__exc_debug_monitor, __default_handler
+	.weak	__stm32reservedexception13
+	.globl	__stm32reservedexception13
+	.set	__stm32reservedexception13, __default_handler
+	.weak	__exc_pendsv
+	.globl	__exc_pendsv
+	.set	__exc_pendsv, __default_handler
+	.weak	__exc_systick
+	.globl	__exc_systick
+	.set	__exc_systick, __default_handler
+	.weak	__irq_wwdg
+	.globl	__irq_wwdg
+	.set	__irq_wwdg, __default_handler
+	.weak	__irq_pvd
+	.globl	__irq_pvd
+	.set	__irq_pvd, __default_handler
+	.weak	__irq_tamper
+	.globl	__irq_tamper
+	.set	__irq_tamper, __default_handler
+	.weak	__irq_rtc
+	.globl	__irq_rtc
+	.set	__irq_rtc, __default_handler
+	.weak	__irq_flash
+	.globl	__irq_flash
+	.set	__irq_flash, __default_handler
+	.weak	__irq_rcc
+	.globl	__irq_rcc
+	.set	__irq_rcc, __default_handler
+	.weak	__irq_exti0
+	.globl	__irq_exti0
+	.set	__irq_exti0, __default_handler
+	.weak	__irq_exti1
+	.globl	__irq_exti1
+	.set	__irq_exti1, __default_handler
+	.weak	__irq_exti2
+	.globl	__irq_exti2
+	.set	__irq_exti2, __default_handler
+	.weak	__irq_exti3
+	.globl	__irq_exti3
+	.set	__irq_exti3, __default_handler
+	.weak	__irq_exti4
+	.globl	__irq_exti4
+	.set	__irq_exti4, __default_handler
+	.weak	__irq_dma1_channel1
+	.globl	__irq_dma1_channel1
+	.set	__irq_dma1_channel1, __default_handler
+	.weak	__irq_dma1_channel2
+	.globl	__irq_dma1_channel2
+	.set	__irq_dma1_channel2, __default_handler
+	.weak	__irq_dma1_channel3
+	.globl	__irq_dma1_channel3
+	.set	__irq_dma1_channel3, __default_handler
+	.weak	__irq_dma1_channel4
+	.globl	__irq_dma1_channel4
+	.set	__irq_dma1_channel4, __default_handler
+	.weak	__irq_dma1_channel5
+	.globl	__irq_dma1_channel5
+	.set	__irq_dma1_channel5, __default_handler
+	.weak	__irq_dma1_channel6
+	.globl	__irq_dma1_channel6
+	.set	__irq_dma1_channel6, __default_handler
+	.weak	__irq_dma1_channel7
+	.globl	__irq_dma1_channel7
+	.set	__irq_dma1_channel7, __default_handler
+	.weak	__irq_adc
+	.globl	__irq_adc
+	.set	__irq_adc, __default_handler
+	.weak	__irq_usb_hp_can_tx
+	.globl	__irq_usb_hp_can_tx
+	.set	__irq_usb_hp_can_tx, __default_handler
+	.weak	__irq_usb_lp_can_rx0
+	.globl	__irq_usb_lp_can_rx0
+	.set	__irq_usb_lp_can_rx0, __default_handler
+	.weak	__irq_can_rx1
+	.globl	__irq_can_rx1
+	.set	__irq_can_rx1, __default_handler
+	.weak	__irq_can_sce
+	.globl	__irq_can_sce
+	.set	__irq_can_sce, __default_handler
+	.weak	__irq_exti9_5
+	.globl	__irq_exti9_5
+	.set	__irq_exti9_5, __default_handler
+	.weak	__irq_tim1_brk
+	.globl	__irq_tim1_brk
+	.set	__irq_tim1_brk, __default_handler
+	.weak	__irq_tim1_up
+	.globl	__irq_tim1_up
+	.set	__irq_tim1_up, __default_handler
+	.weak	__irq_tim1_trg_com
+	.globl	__irq_tim1_trg_com
+	.set	__irq_tim1_trg_com, __default_handler
+	.weak	__irq_tim1_cc
+	.globl	__irq_tim1_cc
+	.set	__irq_tim1_cc, __default_handler
+	.weak	__irq_tim2
+	.globl	__irq_tim2
+	.set	__irq_tim2, __default_handler
+	.weak	__irq_tim3
+	.globl	__irq_tim3
+	.set	__irq_tim3, __default_handler
+	.weak	__irq_tim4
+	.globl	__irq_tim4
+	.set	__irq_tim4, __default_handler
+	.weak	__irq_i2c1_ev
+	.globl	__irq_i2c1_ev
+	.set	__irq_i2c1_ev, __default_handler
+	.weak	__irq_i2c1_er
+	.globl	__irq_i2c1_er
+	.set	__irq_i2c1_er, __default_handler
+	.weak	__irq_i2c2_ev
+	.globl	__irq_i2c2_ev
+	.set	__irq_i2c2_ev, __default_handler
+	.weak	__irq_i2c2_er
+	.globl	__irq_i2c2_er
+	.set	__irq_i2c2_er, __default_handler
+	.weak	__irq_spi1
+	.globl	__irq_spi1
+	.set	__irq_spi1, __default_handler
+	.weak	__irq_spi2
+	.globl	__irq_spi2
+	.set	__irq_spi2, __default_handler
+	.weak	__irq_usart1
+	.globl	__irq_usart1
+	.set	__irq_usart1, __default_handler
+	.weak	__irq_usart2
+	.globl	__irq_usart2
+	.set	__irq_usart2, __default_handler
+	.weak	__irq_usart3
+	.globl	__irq_usart3
+	.set	__irq_usart3, __default_handler
+	.weak	__irq_exti15_10
+	.globl	__irq_exti15_10
+	.set	__irq_exti15_10, __default_handler
+	.weak	__irq_rtcalarm
+	.globl	__irq_rtcalarm
+	.set	__irq_rtcalarm, __default_handler
+	.weak	__irq_usbwakeup
+	.globl	__irq_usbwakeup
+	.set	__irq_usbwakeup, __default_handler
+#if defined (STM32_HIGH_DENSITY)
+	.weak	__irq_tim8_brk
+	.globl	__irq_tim8_brk
+	.set	__irq_tim8_brk, __default_handler
+	.weak	__irq_tim8_up
+	.globl	__irq_tim8_up
+	.set	__irq_tim8_up, __default_handler
+	.weak	__irq_tim8_trg_com
+	.globl	__irq_tim8_trg_com
+	.set	__irq_tim8_trg_com, __default_handler
+	.weak	__irq_tim8_cc
+	.globl	__irq_tim8_cc
+	.set	__irq_tim8_cc, __default_handler
+	.weak	__irq_adc3
+	.globl	__irq_adc3
+	.set	__irq_adc3, __default_handler
+	.weak	__irq_fsmc
+	.globl	__irq_fsmc
+	.set	__irq_fsmc, __default_handler
+	.weak	__irq_sdio
+	.globl	__irq_sdio
+	.set	__irq_sdio, __default_handler
+	.weak	__irq_tim5
+	.globl	__irq_tim5
+	.set	__irq_tim5, __default_handler
+	.weak	__irq_spi3
+	.globl	__irq_spi3
+	.set	__irq_spi3, __default_handler
+	.weak	__irq_uart4
+	.globl	__irq_uart4
+	.set	__irq_uart4, __default_handler
+	.weak	__irq_uart5
+	.globl	__irq_uart5
+	.set	__irq_uart5, __default_handler
+	.weak	__irq_tim6
+	.globl	__irq_tim6
+	.set	__irq_tim6, __default_handler
+	.weak	__irq_tim7
+	.globl	__irq_tim7
+	.set	__irq_tim7, __default_handler
+	.weak	__irq_dma2_channel1
+	.globl	__irq_dma2_channel1
+	.set	__irq_dma2_channel1, __default_handler
+	.weak	__irq_dma2_channel2
+	.globl	__irq_dma2_channel2
+	.set	__irq_dma2_channel2, __default_handler
+	.weak	__irq_dma2_channel3
+	.globl	__irq_dma2_channel3
+	.set	__irq_dma2_channel3, __default_handler
+	.weak	__irq_dma2_channel4_5
+	.globl	__irq_dma2_channel4_5
+	.set	__irq_dma2_channel4_5, __default_handler
+#endif /* STM32_HIGH_DENSITY */
+
+	.weak	__irq_DMA2_Stream4_IRQHandler              
+	.globl	__irq_DMA2_Stream4_IRQHandler              
+	.set	__irq_DMA2_Stream4_IRQHandler, __default_handler
+
+  .weak	__irq_ETH_IRQHandler                       
+  .globl	__irq_ETH_IRQHandler                       
+  .set	__irq_ETH_IRQHandler, __default_handler
+
+  .weak	__irq_ETH_WKUP_IRQHandler                         
+  .globl	__irq_ETH_WKUP_IRQHandler                         
+  .set	__irq_ETH_WKUP_IRQHandler, __default_handler  
+
+  .weak	__irq_CAN2_TX_IRQHandler                          
+  .globl	__irq_CAN2_TX_IRQHandler                          
+  .set	__irq_CAN2_TX_IRQHandler, __default_handler    
+
+  .weak	__irq_CAN2_RX0_IRQHandler                         
+  .globl	__irq_CAN2_RX0_IRQHandler                         
+  .set	__irq_CAN2_RX0_IRQHandler, __default_handler      
+
+  .weak	__irq_CAN2_RX1_IRQHandler                         
+  .globl	__irq_CAN2_RX1_IRQHandler                         
+  .set	__irq_CAN2_RX1_IRQHandler, __default_handler        
+
+  .weak	__irq_CAN2_SCE_IRQHandler                         
+  .globl	__irq_CAN2_SCE_IRQHandler                         
+  .set	__irq_CAN2_SCE_IRQHandler, __default_handler          
+
+  .weak	__irq_OTG_FS_IRQHandler                    
+  .globl	__irq_OTG_FS_IRQHandler                    
+  .set	__irq_OTG_FS_IRQHandler, __default_handler            
+
+  .weak	__irq_DMA2_Stream5_IRQHandler              
+  .globl	__irq_DMA2_Stream5_IRQHandler              
+  .set	__irq_DMA2_Stream5_IRQHandler, __default_handler              
+
+  .weak	__irq_DMA2_Stream6_IRQHandler              
+  .globl	__irq_DMA2_Stream6_IRQHandler              
+  .set	__irq_DMA2_Stream6_IRQHandler, __default_handler                
+
+  .weak	__irq_DMA2_Stream7_IRQHandler              
+  .globl	__irq_DMA2_Stream7_IRQHandler              
+  .set	__irq_DMA2_Stream7_IRQHandler, __default_handler                  
+
+  .weak	__irq_USART6_IRQHandler                     
+  .globl	__irq_USART6_IRQHandler                     
+  .set	__irq_USART6_IRQHandler, __default_handler                    
+
+  .weak	__irq_I2C3_EV_IRQHandler                          
+  .globl	__irq_I2C3_EV_IRQHandler                          
+  .set	__irq_I2C3_EV_IRQHandler, __default_handler                      
+
+  .weak	__irq_I2C3_ER_IRQHandler                          
+  .globl	__irq_I2C3_ER_IRQHandler                          
+  .set	__irq_I2C3_ER_IRQHandler, __default_handler                        
+
+  .weak	__irq_OTG_HS_EP1_OUT_IRQHandler              
+  .globl	__irq_OTG_HS_EP1_OUT_IRQHandler              
+  .set	__irq_OTG_HS_EP1_OUT_IRQHandler, __default_handler                          
+
+  .weak	__irq_OTG_HS_EP1_IN_IRQHandler              
+  .globl	__irq_OTG_HS_EP1_IN_IRQHandler              
+  .set	__irq_OTG_HS_EP1_IN_IRQHandler, __default_handler                            
+
+  .weak	__irq_OTG_HS_WKUP_IRQHandler                       
+  .globl	__irq_OTG_HS_WKUP_IRQHandler                       
+  .set	__irq_OTG_HS_WKUP_IRQHandler, __default_handler                              
+
+  .weak	__irq_OTG_HS_IRQHandler                    
+  .globl	__irq_OTG_HS_IRQHandler                    
+  .set	__irq_OTG_HS_IRQHandler, __default_handler                                
+
+  .weak	__irq_DCMI_IRQHandler                      
+  .globl	__irq_DCMI_IRQHandler                      
+  .set	__irq_DCMI_IRQHandler, __default_handler                                  
+
+  .weak	__irq_CRYP_IRQHandler                      
+  .globl	__irq_CRYP_IRQHandler                      
+  .set	__irq_CRYP_IRQHandler, __default_handler                                    
+
+  .weak	__irq_HASH_RNG_IRQHandler    
+  .globl	__irq_HASH_RNG_IRQHandler    
+  .set	__irq_HASH_RNG_IRQHandler, __default_handler                                      
+
+  .weak	__irq_FPU_IRQHandler         
+  .globl	__irq_FPU_IRQHandler         
+  .set	__irq_FPU_IRQHandler, __default_handler                                        
diff --git a/STM32F4/variants/generic_f407v/stm32_vector_table.S b/STM32F4/variants/generic_f407v/stm32_vector_table.S
new file mode 100644
index 000000000..9f08d6669
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/stm32_vector_table.S
@@ -0,0 +1,113 @@
+/* STM32 vector table */
+
+	.section	".stm32.interrupt_vector"
+
+	.globl	__stm32_vector_table
+	.type	__stm32_vector_table, %object
+
+__stm32_vector_table:
+/* CM3 core interrupts */
+	.long	__msp_init
+	.long	__exc_reset
+	.long	__exc_nmi
+	.long	__exc_hardfault
+	.long	__exc_memmanage
+	.long	__exc_busfault
+	.long	__exc_usagefault
+	.long	__stm32reservedexception7
+	.long	__stm32reservedexception8
+	.long	__stm32reservedexception9
+	.long	__stm32reservedexception10
+	.long	__exc_svc
+	.long	__exc_debug_monitor
+	.long	__stm32reservedexception13
+	.long	__exc_pendsv
+	.long	__exc_systick
+/* Peripheral interrupts */
+	.long	__irq_wwdg
+	.long	__irq_pvd
+	.long	__irq_tamper
+	.long	__irq_rtc
+	.long	__irq_flash
+	.long	__irq_rcc
+	.long	__irq_exti0
+	.long	__irq_exti1
+	.long	__irq_exti2
+	.long	__irq_exti3
+	.long	__irq_exti4
+	.long	__irq_dma1_channel1
+	.long	__irq_dma1_channel2
+	.long	__irq_dma1_channel3
+	.long	__irq_dma1_channel4
+	.long	__irq_dma1_channel5
+	.long	__irq_dma1_channel6
+	.long	__irq_dma1_channel7
+	.long	__irq_adc
+	.long	__irq_usb_hp_can_tx
+	.long	__irq_usb_lp_can_rx0
+	.long	__irq_can_rx1
+	.long	__irq_can_sce
+	.long	__irq_exti9_5
+	.long	__irq_tim1_brk
+	.long	__irq_tim1_up
+	.long	__irq_tim1_trg_com
+	.long	__irq_tim1_cc
+	.long	__irq_tim2
+	.long	__irq_tim3
+	.long	__irq_tim4
+	.long	__irq_i2c1_ev
+	.long	__irq_i2c1_er
+	.long	__irq_i2c2_ev
+	.long	__irq_i2c2_er
+	.long	__irq_spi1
+	.long	__irq_spi2
+	.long	__irq_usart1
+	.long	__irq_usart2
+	.long	__irq_usart3
+	.long	__irq_exti15_10
+	.long	__irq_rtcalarm
+	.long	__irq_usbwakeup
+#if defined (STM32_HIGH_DENSITY)
+	.long	__irq_tim8_brk
+	.long	__irq_tim8_up
+	.long	__irq_tim8_trg_com
+	.long	__irq_tim8_cc
+	.long	__irq_adc3
+	.long	__irq_fsmc
+	.long	__irq_sdio
+	.long	__irq_tim5
+	.long	__irq_spi3
+	.long	__irq_uart4
+	.long	__irq_uart5
+	.long	__irq_tim6
+	.long	__irq_tim7
+	.long	__irq_dma2_channel1
+	.long	__irq_dma2_channel2
+	.long	__irq_dma2_channel3
+	.long	__irq_dma2_channel4_5
+#endif /* STM32_HIGH_DENSITY */
+
+  .long	__irq_DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */                   
+  .long	__irq_ETH_IRQHandler                    /* Ethernet                     */                   
+  .long	__irq_ETH_WKUP_IRQHandler               /* Ethernet Wakeup through EXTI line */                     
+  .long	__irq_CAN2_TX_IRQHandler                /* CAN2 TX                      */                          
+  .long	__irq_CAN2_RX0_IRQHandler               /* CAN2 RX0                     */                          
+  .long	__irq_CAN2_RX1_IRQHandler               /* CAN2 RX1                     */                          
+  .long	__irq_CAN2_SCE_IRQHandler               /* CAN2 SCE                     */                          
+  .long	__irq_OTG_FS_IRQHandler                 /* USB OTG FS                   */                   
+  .long	__irq_DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */                   
+  .long	__irq_DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */                   
+  .long	__irq_DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */                   
+  .long	__irq_USART6_IRQHandler                 /* USART6                       */                    
+  .long	__irq_I2C3_EV_IRQHandler                /* I2C3 event                   */                          
+  .long	__irq_I2C3_ER_IRQHandler                /* I2C3 error                   */                          
+  .long	__irq_OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */                   
+  .long	__irq_OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */                   
+  .long	__irq_OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */                         
+  .long	__irq_OTG_HS_IRQHandler                 /* USB OTG HS                   */                   
+  .long	__irq_DCMI_IRQHandler                   /* DCMI                         */                   
+  .long	__irq_CRYP_IRQHandler                   /* CRYP crypto                  */                   
+  .long	__irq_HASH_RNG_IRQHandler               /* Hash and Rng                 */
+  .long	__irq_FPU_IRQHandler                    /* FPU                          */
+
+	.size	__stm32_vector_table, . - __stm32_vector_table
diff --git a/STM32F4/variants/generic_f407v/variant.h b/STM32F4/variants/generic_f407v/variant.h
new file mode 100644
index 000000000..cd0a96de4
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/variant.h
@@ -0,0 +1,21 @@
+#ifndef _VARIANT_ARDUINO_STM32_
+#define _VARIANT_ARDUINO_STM32_
+
+
+#define digitalPinToPort(P)        ( PIN_MAP[P].gpio_device )
+#define digitalPinToBitMask(P)     ( BIT(PIN_MAP[P].gpio_bit) )
+#define portOutputRegister(port)   ( &(port->regs->ODR) )
+#define portInputRegister(port)    ( &(port->regs->IDR) )
+
+#define portSetRegister(pin)		( &(PIN_MAP[pin].gpio_device->regs->BSRR) )
+#define portClearRegister(pin)		( &(PIN_MAP[pin].gpio_device->regs->BRR) )
+
+#define portConfigRegister(pin)		( &(PIN_MAP[pin].gpio_device->regs->CRL) )
+
+static const uint8_t SS   = BOARD_SPI1_NSS_PIN;
+static const uint8_t SS1  = BOARD_SPI2_NSS_PIN;
+static const uint8_t MOSI = BOARD_SPI1_MOSI_PIN;
+static const uint8_t MISO = BOARD_SPI1_MISO_PIN;
+static const uint8_t SCK  = BOARD_SPI1_SCK_PIN;
+
+#endif /* _VARIANT_ARDUINO_STM32_ */
\ No newline at end of file
diff --git a/STM32F4/cores/maple/libmaple/rcc.c b/STM32F4/variants/generic_f407v/wirish/start.S
similarity index 54%
rename from STM32F4/cores/maple/libmaple/rcc.c
rename to STM32F4/variants/generic_f407v/wirish/start.S
index b3cb9c5d1..8b181aa99 100644
--- a/STM32F4/cores/maple/libmaple/rcc.c
+++ b/STM32F4/variants/generic_f407v/wirish/start.S
@@ -1,7 +1,7 @@
 /******************************************************************************
  * The MIT License
  *
- * Copyright (c) 2010 Perry Hung.
+ * Copyright (c) 2011 LeafLabs, LLC.
  *
  * Permission is hereby granted, free of charge, to any person
  * obtaining a copy of this software and associated documentation
@@ -24,14 +24,34 @@
  * SOFTWARE.
  *****************************************************************************/
 
-/**
- * @file rcc.c
- * @brief Implements pretty much only the basic clock setup on the
- *        stm32, clock enable/disable and peripheral reset commands.
+/*
+ * This file is a modified version of a file obtained from
+ * CodeSourcery Inc. (now part of Mentor Graphics Corp.), in which the
+ * following text appeared:
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
  */
 
-// #ifdef STM32F2
-// #include "rccF2.c"
-// #else
-// #include "rccF1.c"
-// #endif
+        .text
+        .code 16
+        .thumb_func
+
+        .globl __start__
+        .type __start__, %function
+__start__:
+        .fnstart
+        ldr r1,=__msp_init
+        mov sp,r1
+        ldr r1,=start_c
+        bx r1
+        .pool
+        .cantunwind
+        .fnend
diff --git a/STM32F4/variants/generic_f407v/wirish/start_c.c b/STM32F4/variants/generic_f407v/wirish/start_c.c
new file mode 100644
index 000000000..655fefb88
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/wirish/start_c.c
@@ -0,0 +1,95 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/*
+ * This file is a modified version of a file obtained from
+ * CodeSourcery Inc. (now part of Mentor Graphics Corp.), in which the
+ * following text appeared:
+ *
+ * Copyright (c) 2006, 2007 CodeSourcery Inc
+ *
+ * The authors hereby grant permission to use, copy, modify, distribute,
+ * and license this software and its documentation for any purpose, provided
+ * that existing copyright notices are retained in all copies and that this
+ * notice is included verbatim in any distributions. No written agreement,
+ * license, or royalty fee is required for any of the authorized uses.
+ * Modifications to this software may be copyrighted by their authors
+ * and need not follow the licensing terms described here, provided that
+ * the new terms are clearly indicated on the first page of each file where
+ * they apply.
+ */
+
+#include <stddef.h>
+
+extern void __libc_init_array(void);
+
+extern int main(int, char**, char**);
+
+extern void exit(int) __attribute__((noreturn, weak));
+
+/* The linker must ensure that these are at least 4-byte aligned. */
+extern char __data_start__, __data_end__;
+extern char __bss_start__, __bss_end__;
+
+struct rom_img_cfg {
+    int *img_start;
+};
+
+extern char _lm_rom_img_cfgp;
+
+void __attribute__((noreturn)) start_c(void) {
+    struct rom_img_cfg *img_cfg = (struct rom_img_cfg*)&_lm_rom_img_cfgp;
+    int *src = img_cfg->img_start;
+    int *dst = (int*)&__data_start__;
+    int exit_code;
+
+    /* Initialize .data, if necessary. */
+    if (src != dst) {
+        int *end = (int*)&__data_end__;
+        while (dst < end) {
+            *dst++ = *src++;
+        }
+    }
+
+    /* Zero .bss. */
+    dst = (int*)&__bss_start__;
+    while (dst < (int*)&__bss_end__) {
+        *dst++ = 0;
+    }
+
+    /* Run initializers. */
+    __libc_init_array();
+
+    /* Jump to main. */
+    exit_code = main(0, 0, 0);
+    if (exit) {
+        exit(exit_code);
+    }
+
+    /* If exit is NULL, make sure we don't return. */
+    for (;;)
+        continue;
+}

From 8ba463a68ceeafa08674a7643ff967172525bea3 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Sat, 13 May 2017 14:30:24 +0200
Subject: [PATCH 075/307] improved SPI non-DMA block read routine, taken over
 from F4

---
 STM32F1/libraries/SPI/src/SPI.cpp | 109 ++++++++++++++++--------------
 STM32F1/libraries/SPI/src/SPI.h   |   2 +-
 2 files changed, 58 insertions(+), 53 deletions(-)

diff --git a/STM32F1/libraries/SPI/src/SPI.cpp b/STM32F1/libraries/SPI/src/SPI.cpp
index 34c810234..11080148f 100644
--- a/STM32F1/libraries/SPI/src/SPI.cpp
+++ b/STM32F1/libraries/SPI/src/SPI.cpp
@@ -135,9 +135,8 @@ SPIClass::SPIClass(uint32 spi_num) {
 	_settings[2].spiDmaDev = DMA2;
 	_settings[2].spiTxDmaChannel = DMA_CH2;
 	_settings[2].spiRxDmaChannel = DMA_CH1;
-#endif	
-	
-	//pinMode(BOARD_SPI_DEFAULT_SS,OUTPUT);
+#endif
+
 }
 
 /*
@@ -260,9 +259,6 @@ void SPIClass::beginTransaction(uint8_t pin, SPISettings settings)
 	#ifdef SPI_DEBUG
 	Serial.println("SPIClass::beginTransaction");
 	#endif
-	//_SSPin=pin;
-	//pinMode(_SSPin,OUTPUT);
-	//digitalWrite(_SSPin,LOW);
 	setBitOrder(settings.bitOrder);
 	setDataMode(settings.dataMode);
 	setDataSize(settings.dataSize);
@@ -316,14 +312,23 @@ uint16 SPIClass::read(void)
 
 void SPIClass::read(uint8 *buf, uint32 len)
 {
+	if ( len == 0 ) return;
+	spi_rx_reg(_currentSetting->spi_d);		// clear the RX buffer in case a byte is waiting on it.
 	spi_reg_map * regs = _currentSetting->spi_d->regs;
-	uint8 b = (regs->DR); // clear the RX buffer in case a byte is waiting on it.
-	// start sequence
-    while ( (len--)>0) {
-		regs->DR = 0x00FF; // " write the data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-        while ( (regs->SR & SPI_SR_RXNE)==0 ) ; // wait till data is available in the Rx register
-        *buf++ = (uint8)(regs->DR); // read and store the received byte
-    }
+	// start sequence: write byte 0
+	regs->DR = 0x00FF;						// write the first byte
+	// main loop
+	while ( (--len) ) {
+		while( !(regs->SR & SPI_SR_TXE) );		// wait for TXE flag
+		noInterrupts();							// go atomic level - avoid interrupts to surely get the previously received data
+		regs->DR = 0x00FF;						// write the next data item to be transmitted into the SPI_DR register. This clears the TXE flag.
+		while ( !(regs->SR & SPI_SR_RXNE) );	// wait till data is available in the DR register
+		*buf++ = (uint8)(regs->DR);				// read and store the received byte. This clears the RXNE flag.
+		interrupts();							// let systick do its job
+	}
+	// read remaining last byte
+	while ( !(regs->SR & SPI_SR_RXNE) );	// wait till data is available in the Rx register
+	*buf++ = (uint8)(regs->DR);				// read and store the received byte
 }
 
 void SPIClass::write(uint16 data)
@@ -344,32 +349,37 @@ void SPIClass::write(uint16 data, uint32 n)
 	spi_reg_map * regs = _currentSetting->spi_d->regs;
 	while ( (n--)>0 ) {
 		regs->DR = data; // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
-        while ( (regs->SR & SPI_SR_TXE)==0 ) ; // wait till Tx empty
+		while ( (regs->SR & SPI_SR_TXE)==0 ) ; // wait till Tx empty
 	}
 	while ( (regs->SR & SPI_SR_BSY) != 0); // wait until BSY=0 before returning 
 }
 
-void SPIClass::write(const void *data, uint32 length)
+void SPIClass::write(void *data, uint32 length)
 {
-    spi_tx(_currentSetting->spi_d, data, length); // data can be array of bytes or words
-	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
-	// taken from SdSpiSTM32F1.cpp - Victor's lib, and adapted to support device selection
-	uint16 b = spi_rx_reg(_currentSetting->spi_d); // dummy read, needed, don't remove!
+	spi_dev * spi_d = _currentSetting->spi_d;
+	spi_tx(spi_d, (void*)data, length); // data can be array of bytes or words
+	while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
 }
 
-uint8 SPIClass::transfer(uint8 byte) const {
-	spi_tx_reg(_currentSetting->spi_d, byte); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
-	return (uint8)spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
+uint8 SPIClass::transfer(uint8 byte) const
+{
+	spi_dev * spi_d = _currentSetting->spi_d;
+	spi_rx_reg(spi_d); // read any previous data
+	spi_tx_reg(spi_d, byte); // Write the data item to be transmitted into the SPI_DR register
+	while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
+	return (uint8)spi_rx_reg(spi_d); // "... and read the last received data."
 }
 
-uint16_t SPIClass::transfer16(uint16_t wr_data) const {
-	spi_tx_reg(_currentSetting->spi_d, wr_data); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
-	return (uint16)spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
+uint16_t SPIClass::transfer16(uint16_t wr_data) const
+{
+	spi_dev * spi_d = _currentSetting->spi_d;
+	spi_rx_reg(spi_d); // read any previous data
+	spi_tx_reg(spi_d, wr_data); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
+	while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
+	return (uint16)spi_rx_reg(spi_d); // "... and read the last received data."
 }
 
 /*  Roger Clark and Victor Perez, 2015
@@ -382,21 +392,19 @@ uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length
 {
 	if (length == 0) return 0;
 	uint8 b = 0;
-	spi_rx_reg(_currentSetting->spi_d); //Clear the RX buffer in case a byte is waiting on it.
 //	dma1_ch3_Active=true;
     dma_init(_currentSetting->spiDmaDev);
 //	dma_attach_interrupt(DMA1, DMA_CH3, &SPIClass::DMA1_CH3_Event);
 
 	// RX
-	spi_rx_dma_enable(_currentSetting->spi_d);
 	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
 	dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
                      receiveBuf, dma_bit_size, (DMA_MINC_MODE));// receive buffer DMA
 	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, length);
+	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);// enable receive
 
 	// TX
 	uint32 flags = (DMA_MINC_MODE | DMA_FROM_MEM);
-	spi_tx_dma_enable(_currentSetting->spi_d);	
 	if ( transmitBuf==0 ) {
 		static uint8_t ff = 0XFF;
 		transmitBuf = &ff;
@@ -405,23 +413,25 @@ uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length
     dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
                        transmitBuf, dma_bit_size, flags);// Transmit buffer DMA 
 	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
-
-	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);// enable receive
 	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
+
+	spi_rx_reg(_currentSetting->spi_d); //Clear the RX buffer in case a byte is waiting on it.
+	spi_rx_dma_enable(_currentSetting->spi_d);
+	spi_tx_dma_enable(_currentSetting->spi_d);	// must be the last enable to avoid DMA error flag
 	
     uint32_t m = millis();
 	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
+		//delayMicroseconds(10);
 		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
     }
 
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
-    dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
-	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
-	spi_rx_dma_disable(_currentSetting->spi_d); // And disable generation of DMA request from the SPI port so other peripherals can use the channels
 	spi_tx_dma_disable(_currentSetting->spi_d);
-	uint16 x = spi_rx_reg(_currentSetting->spi_d); // dummy read, needed, don't remove!
+	spi_rx_dma_disable(_currentSetting->spi_d); // And disable generation of DMA request from the SPI port so other peripherals can use the channels
+	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
     return b;
 }
 
@@ -438,25 +448,25 @@ uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length, bool minc)
 	uint8 b = 0;
     dma_init(_currentSetting->spiDmaDev);
 	// TX
-	spi_tx_dma_enable(_currentSetting->spi_d);	
 	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
     dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
                        transmitBuf, dma_bit_size, flags);// Transmit buffer DMA 
 	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
 	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
+	spi_tx_dma_enable(_currentSetting->spi_d);	
 
     uint32_t m = millis();
 	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
+		//delayMicroseconds(10);
 		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
     }
 
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
-	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 	spi_tx_dma_disable(_currentSetting->spi_d);
-	uint16 x = spi_rx_reg(_currentSetting->spi_d); // dummy read, needed, don't remove!
-    return b;
+	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+	return b;
 }
 
 void SPIClass::attachInterrupt(void) {
@@ -492,18 +502,13 @@ uint8 SPIClass::nssPin(void) {
  */
 
 uint8 SPIClass::send(uint8 data) {
-    uint8 buf[] = {data};
-    return this->send(buf, 1);
+    this->write(data);
+    return 1;
 }
 
 uint8 SPIClass::send(uint8 *buf, uint32 len) {
-    uint32 txed = 0;
-    uint8 ret = 0;
-    while (txed < len) {
-        this->write(buf[txed++]);
-        ret = this->read();
-    }
-    return ret;
+    this->write(buf, len);
+    return len;
 }
 
 uint8 SPIClass::recv(void) {
diff --git a/STM32F1/libraries/SPI/src/SPI.h b/STM32F1/libraries/SPI/src/SPI.h
index 717a2e90c..b66238426 100644
--- a/STM32F1/libraries/SPI/src/SPI.h
+++ b/STM32F1/libraries/SPI/src/SPI.h
@@ -256,7 +256,7 @@ class SPIClass {
      * @param buffer Bytes/words to transmit.
      * @param length Number of bytes/words in buffer to transmit.
      */
-    void write(const void * buffer, uint32 length);
+    void write(void * buffer, uint32 length);
 
     /**
      * @brief Transmit a byte, then return the next unread byte.

From fbd6927d56f333510f045de10a4bd1ad4a983a43 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Sun, 14 May 2017 16:27:43 +0200
Subject: [PATCH 076/307] resolve Invalid library version number

---
 STM32F4/libraries/arduino_uip/library.properties | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F4/libraries/arduino_uip/library.properties b/STM32F4/libraries/arduino_uip/library.properties
index d707a448d..ce2c43b5d 100644
--- a/STM32F4/libraries/arduino_uip/library.properties
+++ b/STM32F4/libraries/arduino_uip/library.properties
@@ -6,6 +6,6 @@ paragraph=implements the same API as stock Ethernet-lib. Just replace the includ
 category=Communication
 url=https://github.com/ntruchsess/arduino_uip
 architectures=STM32F4
-version=1.04
+version=1.0.4
 dependencies=
 core-dependencies=arduino (>=1.5.0)

From b8afde026a89ad63fc7e3faf4910381c6169ba7a Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Sun, 14 May 2017 16:31:11 +0200
Subject: [PATCH 077/307] increase digitalWrite() value parameter width to 16
 bit

- this useful for the 16 bit parallel TFT lib
---
 STM32F4/cores/maple/libmaple/gpio.h    | 2 +-
 STM32F4/cores/maple/wirish_digital.cpp | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/STM32F4/cores/maple/libmaple/gpio.h b/STM32F4/cores/maple/libmaple/gpio.h
index f1a141fee..dcf1151c1 100644
--- a/STM32F4/cores/maple/libmaple/gpio.h
+++ b/STM32F4/cores/maple/libmaple/gpio.h
@@ -59,7 +59,7 @@ static inline afio_exti_port gpio_exti_port(const gpio_dev *dev) {
  * @param pin Pin on to set or reset
  * @param val If true, set the pin.  If false, reset the pin.
  */
-static inline void gpio_write_pin(uint8_t pin, uint8 val) {
+static inline void gpio_write_pin(uint8_t pin, uint16 val) {
     if (val) {
         (PIN_MAP[pin].gpio_device)->regs->BSRRL = BIT(pin&0x0F);
     } else {
diff --git a/STM32F4/cores/maple/wirish_digital.cpp b/STM32F4/cores/maple/wirish_digital.cpp
index 4a656199b..47690515a 100644
--- a/STM32F4/cores/maple/wirish_digital.cpp
+++ b/STM32F4/cores/maple/wirish_digital.cpp
@@ -94,7 +94,7 @@ uint32 digitalRead(uint8 pin)
         HIGH : LOW;
 }
 
-void digitalWrite(uint8 pin, uint8 val)
+void digitalWrite(uint8 pin, uint16 val)
 {
     if (pin >= BOARD_NR_GPIO_PINS) {
         return;

From 20fbc3613dc11b75c2763defcc3592855ea07ed1 Mon Sep 17 00:00:00 2001
From: MicroBahner <fpm@mnet-online.de>
Date: Sun, 14 May 2017 21:21:03 +0200
Subject: [PATCH 078/307] donot disable Timer in pinMode

---
 STM32F1/cores/maple/stm32f1/wirish_digital_f1.cpp | 7 +++----
 1 file changed, 3 insertions(+), 4 deletions(-)

diff --git a/STM32F1/cores/maple/stm32f1/wirish_digital_f1.cpp b/STM32F1/cores/maple/stm32f1/wirish_digital_f1.cpp
index f16181dd1..74c6dc377 100644
--- a/STM32F1/cores/maple/stm32f1/wirish_digital_f1.cpp
+++ b/STM32F1/cores/maple/stm32f1/wirish_digital_f1.cpp
@@ -79,11 +79,10 @@ void pinMode(uint8 pin, WiringPinMode mode) {
 
     gpio_set_mode(PIN_MAP[pin].gpio_device, PIN_MAP[pin].gpio_bit, outputMode);
 
-    if (PIN_MAP[pin].timer_device != NULL) {
-        /* Enable/disable timer channels if we're switching into or
-         * out of PWM. */
+    if (pwm && PIN_MAP[pin].timer_device != NULL) {
+        /* Enable/disable timer channels if we're switching into PWM. */
         timer_set_mode(PIN_MAP[pin].timer_device,
                        PIN_MAP[pin].timer_channel,
-                       pwm ? TIMER_PWM : TIMER_DISABLED);
+                       TIMER_PWM );
     }
 }

From 3d5c54e344ee8d8f769c318d034dd567da6ba25f Mon Sep 17 00:00:00 2001
From: edogaldo <edogaldo@gmail.com>
Date: Tue, 16 May 2017 00:00:59 +0200
Subject: [PATCH 079/307] Make HardwareSerial.flush() compatible with Arduino
 1.0 api

---
 STM32F1/cores/maple/HardwareSerial.cpp                 | 5 +++--
 STM32F1/system/libmaple/include/libmaple/ring_buffer.h | 6 +++---
 2 files changed, 6 insertions(+), 5 deletions(-)

diff --git a/STM32F1/cores/maple/HardwareSerial.cpp b/STM32F1/cores/maple/HardwareSerial.cpp
index c993bdfff..024efbc7d 100644
--- a/STM32F1/cores/maple/HardwareSerial.cpp
+++ b/STM32F1/cores/maple/HardwareSerial.cpp
@@ -193,7 +193,8 @@ size_t HardwareSerial::write(unsigned char ch) {
 	return 1;
 }
 
+/* edogaldo: Waits for the transmission of outgoing serial data to complete (Arduino 1.0 api specs) */
 void HardwareSerial::flush(void) {
-    usart_reset_rx(this->usart_device);
-    usart_reset_tx(this->usart_device);
+    while(!rb_is_empty(this->usart_device->wb)); // wait for TX buffer empty
+    while(!((this->usart_device->regs->SR) & (1<<USART_SR_TC_BIT))); // wait for TC (Transmission Complete) flag set 
 }
diff --git a/STM32F1/system/libmaple/include/libmaple/ring_buffer.h b/STM32F1/system/libmaple/include/libmaple/ring_buffer.h
index eb3863479..e99fe6266 100644
--- a/STM32F1/system/libmaple/include/libmaple/ring_buffer.h
+++ b/STM32F1/system/libmaple/include/libmaple/ring_buffer.h
@@ -52,9 +52,9 @@ extern "C"{
  * One byte is left free to distinguish empty from full. */
 typedef struct ring_buffer {
     volatile uint8 *buf; /**< Buffer items are stored into */
-    uint16 head;         /**< Index of the next item to remove */
-    uint16 tail;         /**< Index where the next item will get inserted */
-    uint16 size;         /**< Buffer capacity minus one */
+    volatile uint16 head;         /**< Index of the next item to remove */
+    volatile uint16 tail;         /**< Index where the next item will get inserted */
+    volatile uint16 size;         /**< Buffer capacity minus one */
 } ring_buffer;
 
 /**

From 04cf037a1dce2898598674f3f54ad4bcf6948902 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Fri, 19 May 2017 17:24:26 +0200
Subject: [PATCH 080/307] digital IO write optimizations for 16bit parallel
 display types

- digitalWrite value increased to 16 bit width
- added IO device bit access functions
- removed PWM enable/disable from pinMode()
---
 STM32F4/cores/maple/io.h               |  2 +-
 STM32F4/cores/maple/libmaple/gpio.h    | 14 ++++++++++++--
 STM32F4/cores/maple/wirish_digital.cpp |  6 +++---
 3 files changed, 16 insertions(+), 6 deletions(-)

diff --git a/STM32F4/cores/maple/io.h b/STM32F4/cores/maple/io.h
index aeaf0fd3a..14546b83d 100644
--- a/STM32F4/cores/maple/io.h
+++ b/STM32F4/cores/maple/io.h
@@ -121,7 +121,7 @@ void pinMode(uint8 pin, WiringPinMode mode);
  * @param value Either LOW (write a 0) or HIGH (write a 1).
  * @see pinMode()
  */
-void digitalWrite(uint8 pin, uint8 value);
+void digitalWrite(uint8 pin, uint16 value);
 
 /**
  * Read a digital value from a pin.  The pin must have its mode set to
diff --git a/STM32F4/cores/maple/libmaple/gpio.h b/STM32F4/cores/maple/libmaple/gpio.h
index dcf1151c1..308324754 100644
--- a/STM32F4/cores/maple/libmaple/gpio.h
+++ b/STM32F4/cores/maple/libmaple/gpio.h
@@ -60,10 +60,12 @@ static inline afio_exti_port gpio_exti_port(const gpio_dev *dev) {
  * @param val If true, set the pin.  If false, reset the pin.
  */
 static inline void gpio_write_pin(uint8_t pin, uint16 val) {
+	uint16_t bit = BIT(pin&0x0F);
+	gpio_reg_map *regs = (PIN_MAP[pin].gpio_device)->regs;
     if (val) {
-        (PIN_MAP[pin].gpio_device)->regs->BSRRL = BIT(pin&0x0F);
+        regs->BSRRL = bit;
     } else {
-        (PIN_MAP[pin].gpio_device)->regs->BSRRH = BIT(pin&0x0F);
+        regs->BSRRH = bit;
     }
 }
 
@@ -71,10 +73,18 @@ static inline void gpio_set_pin(uint8_t pin) {
 	(PIN_MAP[pin].gpio_device)->regs->BSRRL = BIT(pin&0x0F);
 }
 
+static inline void gpio_set_dev_bit(const gpio_dev * dev, uint8_t bit) {
+	dev->regs->BSRRL = BIT(bit);
+}
+
 static inline void gpio_clear_pin(uint8_t pin) {
 	(PIN_MAP[pin].gpio_device)->regs->BSRRH = BIT(pin&0x0F);
 }
 
+static inline void gpio_clear_dev_bit(const gpio_dev * dev, uint8_t bit) {
+	dev->regs->BSRRH = BIT(bit);
+}
+
 /**
  * Determine whether or not a GPIO pin is set.
  *
diff --git a/STM32F4/cores/maple/wirish_digital.cpp b/STM32F4/cores/maple/wirish_digital.cpp
index 47690515a..4630da7bf 100644
--- a/STM32F4/cores/maple/wirish_digital.cpp
+++ b/STM32F4/cores/maple/wirish_digital.cpp
@@ -73,14 +73,14 @@ void pinMode(uint8 pin, WiringPinMode mode) {
     }
 
     gpio_set_mode(pin, outputMode);
-
+/*
     if (PIN_MAP[pin].timer_device != NULL) {
-        /* Enable/disable timer channels if we're switching into or
-         * out of PWM. */
+        // Enable/disable timer channels if we're switching into or out of PWM.
         timer_set_mode(PIN_MAP[pin].timer_device,
                        PIN_MAP[pin].timer_channel,
                        pwm ? TIMER_PWM : TIMER_DISABLED);
     }
+*/
 }
 
 

From c294b0d0dcad974e66b85295933a16807d3a0637 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Fri, 19 May 2017 17:25:51 +0200
Subject: [PATCH 081/307] SPI DMA cleanup

---
 STM32F4/libraries/SPI/src/SPI.cpp | 18 +++++++-----------
 1 file changed, 7 insertions(+), 11 deletions(-)

diff --git a/STM32F4/libraries/SPI/src/SPI.cpp b/STM32F4/libraries/SPI/src/SPI.cpp
index cb8f561c9..18c54cb2b 100644
--- a/STM32F4/libraries/SPI/src/SPI.cpp
+++ b/STM32F4/libraries/SPI/src/SPI.cpp
@@ -428,14 +428,13 @@ uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length
 	);
 	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaStream, length);
 	dma_set_fifo_flags(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaStream, 0);
-	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaStream);
 
 	// TX
-	uint32 flags = (DMA_MINC_MODE | DMA_FROM_MEM); // | DMA_TRNS_CMPLT);
+	uint32 flags = (DMA_MINC_MODE | DMA_FROM_MEM);
 	if ( transmitBuf==0 ) {
-		static uint8_t ff = 0XFF;
+		static uint16_t ff = 0XFFFF;
 		transmitBuf = &ff;
-		flags &= ~((uint32)DMA_MINC_MODE); // remove increment mode
+		flags ^= DMA_MINC_MODE; // remove increment mode
 	}
 	dma_setup_transfer(	_currentSetting->spiDmaDev,
 						_currentSetting->spiTxDmaStream,
@@ -457,19 +456,18 @@ uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length
 	spi_tx_dma_enable(_currentSetting->spi_d);	// must be the last enable to avoid DMA error flag
 	
     uint32_t m = millis();
-	while ((b = dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream) & DMA_ISR_TCIF)==0 ) {// wait for completion flag to be set
-		if ( b&(DMA_ISR_TEIF|DMA_ISR_DMEIF|DMA_ISR_FEIF) ) { b = 1; break; } // break on any error flag
+	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream) & DMA_ISR_TCIF)==0 ) {// wait for completion flag to be set
 		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
     }
-	if (b & DMA_ISR_TCIF) b = 0;
 
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
 	// software disable sequence, see AN4031, chapter 4.1
 	spi_tx_dma_disable(_currentSetting->spi_d);
 	spi_rx_dma_disable(_currentSetting->spi_d);
+	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream);
 	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaStream);
-    dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream);
+
     return b;
 }
 
@@ -502,11 +500,9 @@ uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length, bool minc)
 	spi_tx_dma_enable(_currentSetting->spi_d);
 
 	uint32_t m = millis();
-	while ((b = dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream) & DMA_ISR_TCIF)==0 ) {// wait for completion flag to be set
-		if ( b&(DMA_ISR_TEIF|DMA_ISR_DMEIF|DMA_ISR_FEIF) ) { b = 1; break; } // break on any error flag
+	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream) & DMA_ISR_TCIF)==0 ) {// wait for completion flag to be set
 		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
     }
-	if (b & DMA_ISR_TCIF) b = 0;
 
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 

From a84b8b209ab4a143816c5221f94240551e4221ff Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Fri, 19 May 2017 17:26:16 +0200
Subject: [PATCH 082/307] cosmetics

---
 STM32F4/variants/generic_f407v/generic_f407v.h | 2 +-
 STM32F4/variants/generic_f407v/pin_map.c       | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/STM32F4/variants/generic_f407v/generic_f407v.h b/STM32F4/variants/generic_f407v/generic_f407v.h
index 927f9cd9c..f8a747f3d 100644
--- a/STM32F4/variants/generic_f407v/generic_f407v.h
+++ b/STM32F4/variants/generic_f407v/generic_f407v.h
@@ -87,7 +87,7 @@
 #define BOARD_SPI2A_NSS_PIN     PB9  //Port2Pin('B', 9)
 #define BOARD_SPI2A_SCK_PIN     PB10 //Port2Pin('B',10)
 #define BOARD_SPI2A_MISO_PIN    PC2  //Port2Pin('C', 2)
-#define BOARD_SPI2A_MOSI_PIN    pc3  //Port2Pin('C', 3)
+#define BOARD_SPI2A_MOSI_PIN    PC3  //Port2Pin('C', 3)
 
 #define BOARD_SPI3_NSS_PIN      PA15 //Port2Pin('A',15)
 #define BOARD_SPI3_SCK_PIN      PB3  //Port2Pin('B', 3)
diff --git a/STM32F4/variants/generic_f407v/pin_map.c b/STM32F4/variants/generic_f407v/pin_map.c
index 2189902d6..b21fac885 100644
--- a/STM32F4/variants/generic_f407v/pin_map.c
+++ b/STM32F4/variants/generic_f407v/pin_map.c
@@ -56,7 +56,7 @@ extern timer_dev timer8;
 
 /*
 typedef struct stm32_pin_info {
-    gpio_dev *gpio_device;      // Maple pin's GPIO device
+    const gpio_dev * gpio_device;      // Maple pin's GPIO device
     timer_dev *timer_device;    // Pin's timer device, if any.
     uint8 timer_channel;        // Timer channel, or 0 if none.
     uint8 adc_channel;          // Pin ADC channel, or ADCx if none.

From ba4f3808c2799ecbc53c78cb1514b195188b70d4 Mon Sep 17 00:00:00 2001
From: MicroBahner <fpm@mnet-online.de>
Date: Sat, 20 May 2017 16:11:00 +0200
Subject: [PATCH 083/307] channel output disabled in non pwm-mode

pwmMode disables the channel output in non pwm modes.
Attached ISRs are left unchanged
---
 STM32F1/cores/maple/stm32f1/wirish_digital_f1.cpp | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/STM32F1/cores/maple/stm32f1/wirish_digital_f1.cpp b/STM32F1/cores/maple/stm32f1/wirish_digital_f1.cpp
index 74c6dc377..3ea5ed00a 100644
--- a/STM32F1/cores/maple/stm32f1/wirish_digital_f1.cpp
+++ b/STM32F1/cores/maple/stm32f1/wirish_digital_f1.cpp
@@ -79,10 +79,14 @@ void pinMode(uint8 pin, WiringPinMode mode) {
 
     gpio_set_mode(PIN_MAP[pin].gpio_device, PIN_MAP[pin].gpio_bit, outputMode);
 
-    if (pwm && PIN_MAP[pin].timer_device != NULL) {
-        /* Enable/disable timer channels if we're switching into PWM. */
+    if (PIN_MAP[pin].timer_device != NULL) {
+        if ( pwm ) { // we're switching into PWM, enable timer channels
         timer_set_mode(PIN_MAP[pin].timer_device,
                        PIN_MAP[pin].timer_channel,
                        TIMER_PWM );
+        } else {  // disable channel output in non pwm-Mode             
+            timer_cc_disable(PIN_MAP[pin].timer_device, 
+                            PIN_MAP[pin].timer_channel); 
+        }
     }
 }

From f7a444b9ef0a269febcf1ebab50177690fa18c45 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Sun, 21 May 2017 11:01:22 +0200
Subject: [PATCH 084/307] implemented FSMC for driving an LCD on 16 bit
 parallel data bus

---
 STM32F4/cores/maple/libmaple/fsmc.c           | 97 +++++++++----------
 STM32F4/cores/maple/libmaple/fsmc.h           | 44 +++++++--
 STM32F4/cores/maple/libmaple/gpio.h           | 16 +--
 STM32F4/cores/maple/wirish_digital.cpp        |  6 +-
 .../variants/generic_f407v/generic_f407v.h    | 29 ++++++
 5 files changed, 119 insertions(+), 73 deletions(-)

diff --git a/STM32F4/cores/maple/libmaple/fsmc.c b/STM32F4/cores/maple/libmaple/fsmc.c
index 42b0d77b4..04c75555b 100644
--- a/STM32F4/cores/maple/libmaple/fsmc.c
+++ b/STM32F4/cores/maple/libmaple/fsmc.c
@@ -35,62 +35,53 @@
 #ifdef STM32_HIGH_DENSITY
 
 /**
- * Configure FSMC GPIOs for use with SRAM.
- */
-void fsmc_sram_init_gpios(void) {
-    /* Data lines... */
-    gpio_set_mode(PD0, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PD1, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PD8, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PD9, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PD10, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PD14, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PD15, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE7, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE8, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE9, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE10, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE11, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE12, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE13, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE14, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE15, GPIO_AF_OUTPUT_PP);
+ * Configure FSMC GPIOs for use with LCDs.
+ */ 
 
-    /* Address lines... */
-    gpio_set_mode(PD11, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PD12, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PD13, GPIO_AF_OUTPUT_PP);
-#if 0 // not available on LQFP package
-    gpio_set_mode(GPIOF,  0, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF,  1, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF,  2, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF,  3, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF,  4, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF,  5, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF, 12, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF, 13, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF, 14, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF, 15, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOG,  0, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOG,  1, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOG,  2, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOG,  3, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOG,  4, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOG,  5, GPIO_AF_OUTPUT_PP);
-#endif  // not available on LQFP package
-    /* And control lines... */
-    gpio_set_mode(PD4, GPIO_AF_OUTPUT_PP);   // NOE
-    gpio_set_mode(PD5, GPIO_AF_OUTPUT_PP);   // NWE
+void fsmc_init(void) {
+    rcc_clk_enable(RCC_FSMC);
+    rcc_reset_dev(RCC_FSMC);
+}
 
-    gpio_set_mode(PD7, GPIO_AF_OUTPUT_PP);   // NE1
-#if 0 // not available on LQFP package
-    gpio_set_mode(GPIOG,  9, GPIO_AF_OUTPUT_PP);   // NE2
-    gpio_set_mode(GPIOG, 10, GPIO_AF_OUTPUT_PP);   // NE3
-    gpio_set_mode(GPIOG, 12, GPIO_AF_OUTPUT_PP);   // NE4
-#endif  // not available on LQFP package
+// used control, address and data lines
+// NOE -> RD, NWE -> WR, A18 -> RS, NE1 -> CS
+const uint8_t fsmc_pins[]= {FSMC_NOE, FSMC_NWE, FSMC_NE1, FSMC_A18,
+							FSMC_D0, FSMC_D1, FSMC_D2, FSMC_D3,
+							FSMC_D4, FSMC_D5, FSMC_D6, FSMC_D7,
+							FSMC_D8, FSMC_D9, FSMC_D10, FSMC_D11,
+							FSMC_D12, FSMC_D13, FSMC_D14, FSMC_D15};
 
-    gpio_set_mode(PE0, GPIO_AF_OUTPUT_PP);   // NBL0
-    gpio_set_mode(PE1, GPIO_AF_OUTPUT_PP);   // NBL1
+void fsmc_lcd_init_gpios(void) {
+	uint8_t i;
+	for (i=0; i<sizeof(fsmc_pins); i++) {
+		uint8_t pin = fsmc_pins[i];
+		gpio_set_mode(pin, GPIO_AF_OUTPUT_PP);
+		gpio_set_af_mode(pin, 12);
+	}
 }
 
+volatile uint16_t * fsmcCommand;
+volatile uint16_t * fsmcData;
+
+void fsmc_lcd_init(void)
+{
+    fsmcCommand    =  FSMC_BANK1; // clears A18
+    fsmcData       =  (fsmcCommand+(1<<18)); // sets A18
+
+	fsmc_init();
+	fsmc_lcd_init_gpios();
+	// set access for asynchronous SRAM type, 16 bit wide data bus
+	// see RM0090, 36.5.4, pages 1552-1554
+	uint32_t val = (FSMC_BCR_MTYP_SRAM | FSMC_BCR_MWID_16BITS | FSMC_BCR_WREN);
+	//Serial.print("BCR: "); Serial.println(val, HEX);
+	fsmc_nor_psram_set_BCR(FSMC_NOR_PSRAM1_BASE, val);
+	// set timing data Mode 1. Adjust DATAST according to the WR low period timing from the LCD specification
+	val = (FSMC_BTR_ACCMOD_A | FSMC_BTR_DATLAT_(0) | FSMC_BTR_CLKDIV_(0) | FSMC_BTR_BUSTURN_(0) | FSMC_BTR_DATAST_(6) | FSMC_BTR_ADDHLD_(0) | FSMC_BTR_ADDSET_(2));
+	//Serial.print("BTR: "); Serial.println(val, HEX);
+	fsmc_nor_psram_set_BTR(FSMC_NOR_PSRAM1_BASE, val);
+	// enable FSCM
+	fsmc_nor_psram_bank_enable(FSMC_NOR_PSRAM1_BASE);
+}
+
+
 #endif  /* STM32_HIGH_DENSITY */
diff --git a/STM32F4/cores/maple/libmaple/fsmc.h b/STM32F4/cores/maple/libmaple/fsmc.h
index ef82b08a9..e9754927a 100644
--- a/STM32F4/cores/maple/libmaple/fsmc.h
+++ b/STM32F4/cores/maple/libmaple/fsmc.h
@@ -33,8 +33,6 @@
  * See ../notes/fsmc.txt for more info
  */
 
-#include "libmaple_types.h"
-
 /**
  * @file fsmc.h
  */
@@ -42,6 +40,9 @@
 #ifndef _FSMC_H_
 #define _FSMC_H_
 
+#include <libmaple\util.h>
+#include "libmaple_types.h"
+
 #ifdef __cplusplus
 extern "C"{
 #endif
@@ -62,27 +63,27 @@ typedef struct fsmc_reg_map {
     __io uint32 BTR3; /**< SRAM/NOR-Flash chip-select timing register 3 */
     __io uint32 BCR4; /**< SRAM/NOR-Flash chip-select control register 4 */
     __io uint32 BTR4; /**< SRAM/NOR-Flash chip-select timing register 4 */
-    const uint8 RESERVED1[64];  /**< Reserved */
+    const uint32 RESERVED1[16];  /**< Reserved */
     __io uint32 PCR2;  /**< PC Card/NAND Flash control register 2 */
     __io uint32 SR2;   /**< FIFO status and interrupt register 2 */
     __io uint32 PMEM2; /**< Common memory space timing register 2 */
     __io uint32 PATT2; /**< Attribute memory space timing register 2 */
-    const uint8 RESERVED2[4];   /**< Reserved */
+    const uint32 RESERVED2;   /**< Reserved */
     __io uint32 ECCR2; /**< ECC result register 2 */
-    const uint8 RESERVED3[2];
+    const uint32 RESERVED3[2];   /**< Reserved */
     __io uint32 PCR3;  /**< PC Card/NAND Flash control register 3 */
     __io uint32 SR3;   /**< FIFO status and interrupt register 3 */
     __io uint32 PMEM3; /**< Common memory space timing register 3 */
     __io uint32 PATT3; /**< Attribute memory space timing register 3 */
     const uint32 RESERVED4;     /**< Reserved */
     __io uint32 ECCR3; /**< ECC result register 3 */
-    const uint8 RESERVED5[8];   /**< Reserved */
+    const uint32 RESERVED5[2];   /**< Reserved */
     __io uint32 PCR4;  /**< PC Card/NAND Flash control register 4 */
     __io uint32 SR4;   /**< FIFO status and interrupt register 4 */
     __io uint32 PMEM4; /**< Common memory space timing register 4 */
     __io uint32 PATT4; /**< Attribute memory space timing register 4 */
     __io uint32 PIO4;  /**< I/O space timing register 4 */
-    const uint8 RESERVED6[80];  /**< Reserved */
+    const uint32 RESERVED6[20];  /**< Reserved */
     __io uint32 BWTR1; /**< SRAM/NOR-Flash write timing register 1 */
     const uint32 RESERVED7;     /**< Reserved */
     __io uint32 BWTR2; /**< SRAM/NOR-Flash write timing register 2 */
@@ -101,7 +102,7 @@ typedef struct fsmc_reg_map {
 typedef struct fsmc_nor_psram_reg_map {
     __io uint32 BCR;            /**< Chip-select control register */
     __io uint32 BTR;            /**< Chip-select timing register */
-    const uint8 RESERVED[252];  /**< Reserved */
+    const uint32 RESERVED[64];  /**< Reserved */
     __io uint32 BWTR;           /**< Write timing register */
 } fsmc_nor_psram_reg_map;
 
@@ -170,6 +171,13 @@ typedef struct fsmc_nor_psram_reg_map {
 #define FSMC_BTR_ADDHLD                 (0xF << 4)
 #define FSMC_BTR_ADDSET                 0xF
 
+#define FSMC_BTR_DATLAT_(x)		((x<<24)&FSMC_BTR_DATLAT)
+#define FSMC_BTR_CLKDIV_(x)		((x<<20)&FSMC_BTR_CLKDIV)
+#define FSMC_BTR_BUSTURN_(x)	((x<<16)&FSMC_BTR_BUSTURN)
+#define FSMC_BTR_DATAST_(x)		((x<<8)&FSMC_BTR_DATAST)
+#define FSMC_BTR_ADDHLD_(x)		((x<<4)&FSMC_BTR_ADDHLD)
+#define FSMC_BTR_ADDSET_(x)		((x<<0)&FSMC_BTR_ADDSET)
+
 /* SRAM/NOR-Flash write timing registers */
 
 #define FSMC_BWTR_ACCMOD                 (0x3 << 28)
@@ -280,8 +288,26 @@ typedef struct fsmc_nor_psram_reg_map {
 /*
  * SRAM/NOR Flash routines
  */
+extern volatile uint16_t * fsmcData;
+extern volatile uint16_t * fsmcCommand;
+
+void fsmc_lcd_init(void);
 
-void fsmc_sram_init_gpios(void);
+static inline void fsmc_nor_psram_set_BCR(fsmc_nor_psram_reg_map *regs, uint32_t bcr) {
+    regs->BCR = bcr;
+}
+
+static inline void fsmc_nor_psram_set_BTR(fsmc_nor_psram_reg_map *regs, uint32_t btr) {
+    regs->BTR = btr;
+}
+
+static inline void fsmc_nor_psram_bank_enable(fsmc_nor_psram_reg_map *regs) {
+    regs->BCR |= FSMC_BCR_MBKEN;
+}
+
+static inline void fsmc_nor_psram_bank_disable(fsmc_nor_psram_reg_map *regs) {
+    regs->BCR ^= FSMC_BCR_MBKEN;
+}
 
 /**
  * Set the DATAST bits in the given NOR/PSRAM register map's
diff --git a/STM32F4/cores/maple/libmaple/gpio.h b/STM32F4/cores/maple/libmaple/gpio.h
index 308324754..7f2e7f522 100644
--- a/STM32F4/cores/maple/libmaple/gpio.h
+++ b/STM32F4/cores/maple/libmaple/gpio.h
@@ -69,22 +69,22 @@ static inline void gpio_write_pin(uint8_t pin, uint16 val) {
     }
 }
 
-static inline void gpio_set_pin(uint8_t pin) {
-	(PIN_MAP[pin].gpio_device)->regs->BSRRL = BIT(pin&0x0F);
-}
-
 static inline void gpio_set_dev_bit(const gpio_dev * dev, uint8_t bit) {
 	dev->regs->BSRRL = BIT(bit);
 }
 
-static inline void gpio_clear_pin(uint8_t pin) {
-	(PIN_MAP[pin].gpio_device)->regs->BSRRH = BIT(pin&0x0F);
-}
-
 static inline void gpio_clear_dev_bit(const gpio_dev * dev, uint8_t bit) {
 	dev->regs->BSRRH = BIT(bit);
 }
 
+static inline void gpio_set_pin(uint8_t pin) {
+	gpio_set_dev_bit(PIN_MAP[pin].gpio_device, (pin&0x0F));
+}
+
+static inline void gpio_clear_pin(uint8_t pin) {
+	gpio_clear_dev_bit(PIN_MAP[pin].gpio_device, (pin&0x0F));
+}
+
 /**
  * Determine whether or not a GPIO pin is set.
  *
diff --git a/STM32F4/cores/maple/wirish_digital.cpp b/STM32F4/cores/maple/wirish_digital.cpp
index 4630da7bf..c976fbf1a 100644
--- a/STM32F4/cores/maple/wirish_digital.cpp
+++ b/STM32F4/cores/maple/wirish_digital.cpp
@@ -33,7 +33,7 @@
 
 void pinMode(uint8 pin, WiringPinMode mode) {
     gpio_pin_mode outputMode;
-    boolean pwm = false;
+//    boolean pwm = false;
 
     if (pin >= BOARD_NR_GPIO_PINS) {
         return;
@@ -61,11 +61,11 @@ void pinMode(uint8 pin, WiringPinMode mode) {
         break;
     case PWM:
         outputMode = GPIO_AF_OUTPUT_PP;
-        pwm = true;
+//        pwm = true;
         break;
     case PWM_OPEN_DRAIN:
         outputMode = GPIO_AF_OUTPUT_OD;
-        pwm = true;
+//        pwm = true;
         break;
     default:
         ASSERT(0);
diff --git a/STM32F4/variants/generic_f407v/generic_f407v.h b/STM32F4/variants/generic_f407v/generic_f407v.h
index f8a747f3d..24fae506c 100644
--- a/STM32F4/variants/generic_f407v/generic_f407v.h
+++ b/STM32F4/variants/generic_f407v/generic_f407v.h
@@ -106,6 +106,35 @@
 #define BOARD_SDIO_CK           PC12 //Port2Pin('C',12)
 #define BOARD_SDIO_CMD          PD2  //Port2Pin('D', 2)
 
+#define FSMC_NOE			PD4
+#define FSMC_NWE			PD5
+#define FSMC_NE1			PD7
+#define FSMC_A18			PD13
+#define FSMC_A17			PD12
+#define FSMC_A16			PD11
+#define FSMC_D0				PD14
+#define FSMC_D1				PD15
+#define FSMC_D2				PD0
+#define FSMC_D3				PD1
+#define FSMC_D4				PE7
+#define FSMC_D5				PE8
+#define FSMC_D6				PE9
+#define FSMC_D7				PE10
+#define FSMC_D8				PE11
+#define FSMC_D9				PE12
+#define FSMC_D10			PE13
+#define FSMC_D11			PE14
+#define FSMC_D12			PE15
+#define FSMC_D13			PD8
+#define FSMC_D14			PD9
+#define FSMC_D15			PD10
+
+#define BOARD_T_CS			BOARD_SPI2_NSS_PIN
+#define BOARD_T_SCK			BOARD_SPI2_SCK_PIN
+#define BOARD_T_MISO		BOARD_SPI2_MISO_PIN
+#define BOARD_T_MOSI		BOARD_SPI2_MOSI_PIN
+#define BOARD_T_PEN			PC5
+
 #define BOARD_NR_GPIO_PINS      80
 #define BOARD_NR_PWM_PINS       22
 #define BOARD_NR_ADC_PINS       16

From 8574d238e8ebd1700c98bb099f6da847046269b2 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Mon, 22 May 2017 17:36:50 +0200
Subject: [PATCH 085/307] added FSMC + SPI brought in line with F1

---
 STM32F4/cores/maple/libmaple/fsmc.c           | 97 +++++++++----------
 STM32F4/cores/maple/libmaple/fsmc.h           | 44 +++++++--
 STM32F4/libraries/SPI/src/SPI.cpp             | 10 +-
 .../variants/generic_f407v/generic_f407v.h    | 31 +++++-
 4 files changed, 112 insertions(+), 70 deletions(-)

diff --git a/STM32F4/cores/maple/libmaple/fsmc.c b/STM32F4/cores/maple/libmaple/fsmc.c
index 42b0d77b4..04c75555b 100644
--- a/STM32F4/cores/maple/libmaple/fsmc.c
+++ b/STM32F4/cores/maple/libmaple/fsmc.c
@@ -35,62 +35,53 @@
 #ifdef STM32_HIGH_DENSITY
 
 /**
- * Configure FSMC GPIOs for use with SRAM.
- */
-void fsmc_sram_init_gpios(void) {
-    /* Data lines... */
-    gpio_set_mode(PD0, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PD1, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PD8, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PD9, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PD10, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PD14, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PD15, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE7, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE8, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE9, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE10, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE11, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE12, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE13, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE14, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE15, GPIO_AF_OUTPUT_PP);
+ * Configure FSMC GPIOs for use with LCDs.
+ */ 
 
-    /* Address lines... */
-    gpio_set_mode(PD11, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PD12, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PD13, GPIO_AF_OUTPUT_PP);
-#if 0 // not available on LQFP package
-    gpio_set_mode(GPIOF,  0, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF,  1, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF,  2, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF,  3, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF,  4, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF,  5, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF, 12, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF, 13, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF, 14, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF, 15, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOG,  0, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOG,  1, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOG,  2, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOG,  3, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOG,  4, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOG,  5, GPIO_AF_OUTPUT_PP);
-#endif  // not available on LQFP package
-    /* And control lines... */
-    gpio_set_mode(PD4, GPIO_AF_OUTPUT_PP);   // NOE
-    gpio_set_mode(PD5, GPIO_AF_OUTPUT_PP);   // NWE
+void fsmc_init(void) {
+    rcc_clk_enable(RCC_FSMC);
+    rcc_reset_dev(RCC_FSMC);
+}
 
-    gpio_set_mode(PD7, GPIO_AF_OUTPUT_PP);   // NE1
-#if 0 // not available on LQFP package
-    gpio_set_mode(GPIOG,  9, GPIO_AF_OUTPUT_PP);   // NE2
-    gpio_set_mode(GPIOG, 10, GPIO_AF_OUTPUT_PP);   // NE3
-    gpio_set_mode(GPIOG, 12, GPIO_AF_OUTPUT_PP);   // NE4
-#endif  // not available on LQFP package
+// used control, address and data lines
+// NOE -> RD, NWE -> WR, A18 -> RS, NE1 -> CS
+const uint8_t fsmc_pins[]= {FSMC_NOE, FSMC_NWE, FSMC_NE1, FSMC_A18,
+							FSMC_D0, FSMC_D1, FSMC_D2, FSMC_D3,
+							FSMC_D4, FSMC_D5, FSMC_D6, FSMC_D7,
+							FSMC_D8, FSMC_D9, FSMC_D10, FSMC_D11,
+							FSMC_D12, FSMC_D13, FSMC_D14, FSMC_D15};
 
-    gpio_set_mode(PE0, GPIO_AF_OUTPUT_PP);   // NBL0
-    gpio_set_mode(PE1, GPIO_AF_OUTPUT_PP);   // NBL1
+void fsmc_lcd_init_gpios(void) {
+	uint8_t i;
+	for (i=0; i<sizeof(fsmc_pins); i++) {
+		uint8_t pin = fsmc_pins[i];
+		gpio_set_mode(pin, GPIO_AF_OUTPUT_PP);
+		gpio_set_af_mode(pin, 12);
+	}
 }
 
+volatile uint16_t * fsmcCommand;
+volatile uint16_t * fsmcData;
+
+void fsmc_lcd_init(void)
+{
+    fsmcCommand    =  FSMC_BANK1; // clears A18
+    fsmcData       =  (fsmcCommand+(1<<18)); // sets A18
+
+	fsmc_init();
+	fsmc_lcd_init_gpios();
+	// set access for asynchronous SRAM type, 16 bit wide data bus
+	// see RM0090, 36.5.4, pages 1552-1554
+	uint32_t val = (FSMC_BCR_MTYP_SRAM | FSMC_BCR_MWID_16BITS | FSMC_BCR_WREN);
+	//Serial.print("BCR: "); Serial.println(val, HEX);
+	fsmc_nor_psram_set_BCR(FSMC_NOR_PSRAM1_BASE, val);
+	// set timing data Mode 1. Adjust DATAST according to the WR low period timing from the LCD specification
+	val = (FSMC_BTR_ACCMOD_A | FSMC_BTR_DATLAT_(0) | FSMC_BTR_CLKDIV_(0) | FSMC_BTR_BUSTURN_(0) | FSMC_BTR_DATAST_(6) | FSMC_BTR_ADDHLD_(0) | FSMC_BTR_ADDSET_(2));
+	//Serial.print("BTR: "); Serial.println(val, HEX);
+	fsmc_nor_psram_set_BTR(FSMC_NOR_PSRAM1_BASE, val);
+	// enable FSCM
+	fsmc_nor_psram_bank_enable(FSMC_NOR_PSRAM1_BASE);
+}
+
+
 #endif  /* STM32_HIGH_DENSITY */
diff --git a/STM32F4/cores/maple/libmaple/fsmc.h b/STM32F4/cores/maple/libmaple/fsmc.h
index ef82b08a9..3501583b4 100644
--- a/STM32F4/cores/maple/libmaple/fsmc.h
+++ b/STM32F4/cores/maple/libmaple/fsmc.h
@@ -33,8 +33,6 @@
  * See ../notes/fsmc.txt for more info
  */
 
-#include "libmaple_types.h"
-
 /**
  * @file fsmc.h
  */
@@ -42,6 +40,9 @@
 #ifndef _FSMC_H_
 #define _FSMC_H_
 
+#include <libmaple\util.h>
+#include "libmaple_types.h"
+
 #ifdef __cplusplus
 extern "C"{
 #endif
@@ -62,27 +63,27 @@ typedef struct fsmc_reg_map {
     __io uint32 BTR3; /**< SRAM/NOR-Flash chip-select timing register 3 */
     __io uint32 BCR4; /**< SRAM/NOR-Flash chip-select control register 4 */
     __io uint32 BTR4; /**< SRAM/NOR-Flash chip-select timing register 4 */
-    const uint8 RESERVED1[64];  /**< Reserved */
+    const uint32 RESERVED1[16];  /**< Reserved */
     __io uint32 PCR2;  /**< PC Card/NAND Flash control register 2 */
     __io uint32 SR2;   /**< FIFO status and interrupt register 2 */
     __io uint32 PMEM2; /**< Common memory space timing register 2 */
     __io uint32 PATT2; /**< Attribute memory space timing register 2 */
-    const uint8 RESERVED2[4];   /**< Reserved */
+    const uint32 RESERVED2;   /**< Reserved */
     __io uint32 ECCR2; /**< ECC result register 2 */
-    const uint8 RESERVED3[2];
+    const uint32 RESERVED3[2];   /**< Reserved */
     __io uint32 PCR3;  /**< PC Card/NAND Flash control register 3 */
     __io uint32 SR3;   /**< FIFO status and interrupt register 3 */
     __io uint32 PMEM3; /**< Common memory space timing register 3 */
     __io uint32 PATT3; /**< Attribute memory space timing register 3 */
     const uint32 RESERVED4;     /**< Reserved */
     __io uint32 ECCR3; /**< ECC result register 3 */
-    const uint8 RESERVED5[8];   /**< Reserved */
+    const uint32 RESERVED5[2];   /**< Reserved */
     __io uint32 PCR4;  /**< PC Card/NAND Flash control register 4 */
     __io uint32 SR4;   /**< FIFO status and interrupt register 4 */
     __io uint32 PMEM4; /**< Common memory space timing register 4 */
     __io uint32 PATT4; /**< Attribute memory space timing register 4 */
     __io uint32 PIO4;  /**< I/O space timing register 4 */
-    const uint8 RESERVED6[80];  /**< Reserved */
+    const uint32 RESERVED6[20];  /**< Reserved */
     __io uint32 BWTR1; /**< SRAM/NOR-Flash write timing register 1 */
     const uint32 RESERVED7;     /**< Reserved */
     __io uint32 BWTR2; /**< SRAM/NOR-Flash write timing register 2 */
@@ -101,7 +102,7 @@ typedef struct fsmc_reg_map {
 typedef struct fsmc_nor_psram_reg_map {
     __io uint32 BCR;            /**< Chip-select control register */
     __io uint32 BTR;            /**< Chip-select timing register */
-    const uint8 RESERVED[252];  /**< Reserved */
+    const uint32 RESERVED[63];  /**< Reserved */
     __io uint32 BWTR;           /**< Write timing register */
 } fsmc_nor_psram_reg_map;
 
@@ -170,6 +171,13 @@ typedef struct fsmc_nor_psram_reg_map {
 #define FSMC_BTR_ADDHLD                 (0xF << 4)
 #define FSMC_BTR_ADDSET                 0xF
 
+#define FSMC_BTR_DATLAT_(x)		((x<<24)&FSMC_BTR_DATLAT)
+#define FSMC_BTR_CLKDIV_(x)		((x<<20)&FSMC_BTR_CLKDIV)
+#define FSMC_BTR_BUSTURN_(x)	((x<<16)&FSMC_BTR_BUSTURN)
+#define FSMC_BTR_DATAST_(x)		((x<<8)&FSMC_BTR_DATAST)
+#define FSMC_BTR_ADDHLD_(x)		((x<<4)&FSMC_BTR_ADDHLD)
+#define FSMC_BTR_ADDSET_(x)		((x<<0)&FSMC_BTR_ADDSET)
+
 /* SRAM/NOR-Flash write timing registers */
 
 #define FSMC_BWTR_ACCMOD                 (0x3 << 28)
@@ -280,8 +288,26 @@ typedef struct fsmc_nor_psram_reg_map {
 /*
  * SRAM/NOR Flash routines
  */
+extern volatile uint16_t * fsmcData;
+extern volatile uint16_t * fsmcCommand;
+
+void fsmc_lcd_init(void);
 
-void fsmc_sram_init_gpios(void);
+static inline void fsmc_nor_psram_set_BCR(fsmc_nor_psram_reg_map *regs, uint32_t bcr) {
+    regs->BCR = bcr;
+}
+
+static inline void fsmc_nor_psram_set_BTR(fsmc_nor_psram_reg_map *regs, uint32_t btr) {
+    regs->BTR = btr;
+}
+
+static inline void fsmc_nor_psram_bank_enable(fsmc_nor_psram_reg_map *regs) {
+    regs->BCR |= FSMC_BCR_MBKEN;
+}
+
+static inline void fsmc_nor_psram_bank_disable(fsmc_nor_psram_reg_map *regs) {
+    regs->BCR ^= FSMC_BCR_MBKEN;
+}
 
 /**
  * Set the DATAST bits in the given NOR/PSRAM register map's
diff --git a/STM32F4/libraries/SPI/src/SPI.cpp b/STM32F4/libraries/SPI/src/SPI.cpp
index cb8f561c9..c4ad5f298 100644
--- a/STM32F4/libraries/SPI/src/SPI.cpp
+++ b/STM32F4/libraries/SPI/src/SPI.cpp
@@ -457,19 +457,17 @@ uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length
 	spi_tx_dma_enable(_currentSetting->spi_d);	// must be the last enable to avoid DMA error flag
 	
     uint32_t m = millis();
-	while ((b = dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream) & DMA_ISR_TCIF)==0 ) {// wait for completion flag to be set
-		if ( b&(DMA_ISR_TEIF|DMA_ISR_DMEIF|DMA_ISR_FEIF) ) { b = 1; break; } // break on any error flag
+	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream) & DMA_ISR_TCIF)==0 ) {// wait for completion flag to be set
 		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
     }
-	if (b & DMA_ISR_TCIF) b = 0;
 
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
 	// software disable sequence, see AN4031, chapter 4.1
 	spi_tx_dma_disable(_currentSetting->spi_d);
 	spi_rx_dma_disable(_currentSetting->spi_d);
+	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream);
 	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaStream);
-    dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream);
     return b;
 }
 
@@ -502,11 +500,9 @@ uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length, bool minc)
 	spi_tx_dma_enable(_currentSetting->spi_d);
 
 	uint32_t m = millis();
-	while ((b = dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream) & DMA_ISR_TCIF)==0 ) {// wait for completion flag to be set
-		if ( b&(DMA_ISR_TEIF|DMA_ISR_DMEIF|DMA_ISR_FEIF) ) { b = 1; break; } // break on any error flag
+	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream) & DMA_ISR_TCIF)==0 ) {// wait for completion flag to be set
 		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
     }
-	if (b & DMA_ISR_TCIF) b = 0;
 
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
diff --git a/STM32F4/variants/generic_f407v/generic_f407v.h b/STM32F4/variants/generic_f407v/generic_f407v.h
index 927f9cd9c..24fae506c 100644
--- a/STM32F4/variants/generic_f407v/generic_f407v.h
+++ b/STM32F4/variants/generic_f407v/generic_f407v.h
@@ -87,7 +87,7 @@
 #define BOARD_SPI2A_NSS_PIN     PB9  //Port2Pin('B', 9)
 #define BOARD_SPI2A_SCK_PIN     PB10 //Port2Pin('B',10)
 #define BOARD_SPI2A_MISO_PIN    PC2  //Port2Pin('C', 2)
-#define BOARD_SPI2A_MOSI_PIN    pc3  //Port2Pin('C', 3)
+#define BOARD_SPI2A_MOSI_PIN    PC3  //Port2Pin('C', 3)
 
 #define BOARD_SPI3_NSS_PIN      PA15 //Port2Pin('A',15)
 #define BOARD_SPI3_SCK_PIN      PB3  //Port2Pin('B', 3)
@@ -106,6 +106,35 @@
 #define BOARD_SDIO_CK           PC12 //Port2Pin('C',12)
 #define BOARD_SDIO_CMD          PD2  //Port2Pin('D', 2)
 
+#define FSMC_NOE			PD4
+#define FSMC_NWE			PD5
+#define FSMC_NE1			PD7
+#define FSMC_A18			PD13
+#define FSMC_A17			PD12
+#define FSMC_A16			PD11
+#define FSMC_D0				PD14
+#define FSMC_D1				PD15
+#define FSMC_D2				PD0
+#define FSMC_D3				PD1
+#define FSMC_D4				PE7
+#define FSMC_D5				PE8
+#define FSMC_D6				PE9
+#define FSMC_D7				PE10
+#define FSMC_D8				PE11
+#define FSMC_D9				PE12
+#define FSMC_D10			PE13
+#define FSMC_D11			PE14
+#define FSMC_D12			PE15
+#define FSMC_D13			PD8
+#define FSMC_D14			PD9
+#define FSMC_D15			PD10
+
+#define BOARD_T_CS			BOARD_SPI2_NSS_PIN
+#define BOARD_T_SCK			BOARD_SPI2_SCK_PIN
+#define BOARD_T_MISO		BOARD_SPI2_MISO_PIN
+#define BOARD_T_MOSI		BOARD_SPI2_MOSI_PIN
+#define BOARD_T_PEN			PC5
+
 #define BOARD_NR_GPIO_PINS      80
 #define BOARD_NR_PWM_PINS       22
 #define BOARD_NR_ADC_PINS       16

From 70aa720e34afcb7f3278a5c368b91ba26cfde2f4 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Mon, 22 May 2017 17:53:17 +0200
Subject: [PATCH 086/307] corrected RESERVED size in fsmc_nor_psram_reg_map

---
 STM32F4/cores/maple/libmaple/fsmc.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F4/cores/maple/libmaple/fsmc.h b/STM32F4/cores/maple/libmaple/fsmc.h
index e9754927a..3501583b4 100644
--- a/STM32F4/cores/maple/libmaple/fsmc.h
+++ b/STM32F4/cores/maple/libmaple/fsmc.h
@@ -102,7 +102,7 @@ typedef struct fsmc_reg_map {
 typedef struct fsmc_nor_psram_reg_map {
     __io uint32 BCR;            /**< Chip-select control register */
     __io uint32 BTR;            /**< Chip-select timing register */
-    const uint32 RESERVED[64];  /**< Reserved */
+    const uint32 RESERVED[63];  /**< Reserved */
     __io uint32 BWTR;           /**< Write timing register */
 } fsmc_nor_psram_reg_map;
 

From f1608abe0b8e250d22999a804fc105f391974305 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Mon, 22 May 2017 21:09:12 +0200
Subject: [PATCH 087/307] SPI update

- cleaned up commented out lines
- run-time optimized write and transfer functions
- run-time optimized non-DMA block read routine
- function call order within DMA routines tied to F4 structure - in line
with AN4031, chapter 4.3
- reworked send functions (currently not used, deprecated, but still)
---
 STM32F1/libraries/SPI/src/SPI.cpp | 118 +++++++++++++++---------------
 STM32F1/libraries/SPI/src/SPI.h   |   2 +-
 2 files changed, 62 insertions(+), 58 deletions(-)

diff --git a/STM32F1/libraries/SPI/src/SPI.cpp b/STM32F1/libraries/SPI/src/SPI.cpp
index 45ee25ab4..11080148f 100644
--- a/STM32F1/libraries/SPI/src/SPI.cpp
+++ b/STM32F1/libraries/SPI/src/SPI.cpp
@@ -135,9 +135,8 @@ SPIClass::SPIClass(uint32 spi_num) {
 	_settings[2].spiDmaDev = DMA2;
 	_settings[2].spiTxDmaChannel = DMA_CH2;
 	_settings[2].spiRxDmaChannel = DMA_CH1;
-#endif	
-	
-	//pinMode(BOARD_SPI_DEFAULT_SS,OUTPUT);
+#endif
+
 }
 
 /*
@@ -260,9 +259,6 @@ void SPIClass::beginTransaction(uint8_t pin, SPISettings settings)
 	#ifdef SPI_DEBUG
 	Serial.println("SPIClass::beginTransaction");
 	#endif
-	//_SSPin=pin;
-	//pinMode(_SSPin,OUTPUT);
-	//digitalWrite(_SSPin,LOW);
 	setBitOrder(settings.bitOrder);
 	setDataMode(settings.dataMode);
 	setDataSize(settings.dataSize);
@@ -316,14 +312,23 @@ uint16 SPIClass::read(void)
 
 void SPIClass::read(uint8 *buf, uint32 len)
 {
+	if ( len == 0 ) return;
+	spi_rx_reg(_currentSetting->spi_d);		// clear the RX buffer in case a byte is waiting on it.
 	spi_reg_map * regs = _currentSetting->spi_d->regs;
-	uint8 b = (regs->DR); // clear the RX buffer in case a byte is waiting on it.
-	// start sequence
-    while ( (len--)>0) {
-		regs->DR = 0x00FF; // " write the data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-        while ( (regs->SR & SPI_SR_RXNE)==0 ) ; // wait till data is available in the Rx register
-        *buf++ = (uint8)(regs->DR); // read and store the received byte
-    }
+	// start sequence: write byte 0
+	regs->DR = 0x00FF;						// write the first byte
+	// main loop
+	while ( (--len) ) {
+		while( !(regs->SR & SPI_SR_TXE) );		// wait for TXE flag
+		noInterrupts();							// go atomic level - avoid interrupts to surely get the previously received data
+		regs->DR = 0x00FF;						// write the next data item to be transmitted into the SPI_DR register. This clears the TXE flag.
+		while ( !(regs->SR & SPI_SR_RXNE) );	// wait till data is available in the DR register
+		*buf++ = (uint8)(regs->DR);				// read and store the received byte. This clears the RXNE flag.
+		interrupts();							// let systick do its job
+	}
+	// read remaining last byte
+	while ( !(regs->SR & SPI_SR_RXNE) );	// wait till data is available in the Rx register
+	*buf++ = (uint8)(regs->DR);				// read and store the received byte
 }
 
 void SPIClass::write(uint16 data)
@@ -344,32 +349,37 @@ void SPIClass::write(uint16 data, uint32 n)
 	spi_reg_map * regs = _currentSetting->spi_d->regs;
 	while ( (n--)>0 ) {
 		regs->DR = data; // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
-        while ( (regs->SR & SPI_SR_TXE)==0 ) ; // wait till Tx empty
+		while ( (regs->SR & SPI_SR_TXE)==0 ) ; // wait till Tx empty
 	}
 	while ( (regs->SR & SPI_SR_BSY) != 0); // wait until BSY=0 before returning 
 }
 
-void SPIClass::write(const void *data, uint32 length)
+void SPIClass::write(void *data, uint32 length)
 {
-    spi_tx(_currentSetting->spi_d, data, length); // data can be array of bytes or words
-	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
-	// taken from SdSpiSTM32F1.cpp - Victor's lib, and adapted to support device selection
-	uint16 b = spi_rx_reg(_currentSetting->spi_d); // dummy read, needed, don't remove!
+	spi_dev * spi_d = _currentSetting->spi_d;
+	spi_tx(spi_d, (void*)data, length); // data can be array of bytes or words
+	while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
 }
 
-uint8 SPIClass::transfer(uint8 byte) const {
-	spi_tx_reg(_currentSetting->spi_d, byte); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
-	return (uint8)spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
+uint8 SPIClass::transfer(uint8 byte) const
+{
+	spi_dev * spi_d = _currentSetting->spi_d;
+	spi_rx_reg(spi_d); // read any previous data
+	spi_tx_reg(spi_d, byte); // Write the data item to be transmitted into the SPI_DR register
+	while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
+	return (uint8)spi_rx_reg(spi_d); // "... and read the last received data."
 }
 
-uint16_t SPIClass::transfer16(uint16_t wr_data) const {
-	spi_tx_reg(_currentSetting->spi_d, wr_data); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
-	return (uint16)spi_rx_reg(_currentSetting->spi_d); // "... and read the last received data."
+uint16_t SPIClass::transfer16(uint16_t wr_data) const
+{
+	spi_dev * spi_d = _currentSetting->spi_d;
+	spi_rx_reg(spi_d); // read any previous data
+	spi_tx_reg(spi_d, wr_data); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
+	while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
+	return (uint16)spi_rx_reg(spi_d); // "... and read the last received data."
 }
 
 /*  Roger Clark and Victor Perez, 2015
@@ -382,21 +392,19 @@ uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length
 {
 	if (length == 0) return 0;
 	uint8 b = 0;
-	spi_rx_reg(_currentSetting->spi_d); //Clear the RX buffer in case a byte is waiting on it.
 //	dma1_ch3_Active=true;
     dma_init(_currentSetting->spiDmaDev);
 //	dma_attach_interrupt(DMA1, DMA_CH3, &SPIClass::DMA1_CH3_Event);
 
 	// RX
-	spi_rx_dma_enable(_currentSetting->spi_d);
 	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
 	dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
-                     receiveBuf, dma_bit_size, (DMA_MINC_MODE | DMA_TRNS_CMPLT));// receive buffer DMA
+                     receiveBuf, dma_bit_size, (DMA_MINC_MODE));// receive buffer DMA
 	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, length);
+	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);// enable receive
 
 	// TX
-	uint32 flags = (DMA_MINC_MODE | DMA_FROM_MEM | DMA_TRNS_CMPLT);
-	spi_tx_dma_enable(_currentSetting->spi_d);	
+	uint32 flags = (DMA_MINC_MODE | DMA_FROM_MEM);
 	if ( transmitBuf==0 ) {
 		static uint8_t ff = 0XFF;
 		transmitBuf = &ff;
@@ -405,23 +413,25 @@ uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length
     dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
                        transmitBuf, dma_bit_size, flags);// Transmit buffer DMA 
 	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
-
-	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);// enable receive
+	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
+
+	spi_rx_reg(_currentSetting->spi_d); //Clear the RX buffer in case a byte is waiting on it.
+	spi_rx_dma_enable(_currentSetting->spi_d);
+	spi_tx_dma_enable(_currentSetting->spi_d);	// must be the last enable to avoid DMA error flag
 	
     uint32_t m = millis();
 	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
+		//delayMicroseconds(10);
 		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
     }
-	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
-    dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
-	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
-	spi_rx_dma_disable(_currentSetting->spi_d); // And disable generation of DMA request from the SPI port so other peripherals can use the channels
 	spi_tx_dma_disable(_currentSetting->spi_d);
-	uint16 x = spi_rx_reg(_currentSetting->spi_d); // dummy read, needed, don't remove!
+	spi_rx_dma_disable(_currentSetting->spi_d); // And disable generation of DMA request from the SPI port so other peripherals can use the channels
+	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
     return b;
 }
 
@@ -438,26 +448,25 @@ uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length, bool minc)
 	uint8 b = 0;
     dma_init(_currentSetting->spiDmaDev);
 	// TX
-	spi_tx_dma_enable(_currentSetting->spi_d);	
 	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
     dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
                        transmitBuf, dma_bit_size, flags);// Transmit buffer DMA 
 	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
+	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
+	spi_tx_dma_enable(_currentSetting->spi_d);	
 
-//    while (dma1_ch3_Active);
     uint32_t m = millis();
 	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
+		//delayMicroseconds(10);
 		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
     }
-	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
-	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 	spi_tx_dma_disable(_currentSetting->spi_d);
-	uint16 x = spi_rx_reg(_currentSetting->spi_d); // dummy read, needed, don't remove!
-    return b;
+	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+	return b;
 }
 
 void SPIClass::attachInterrupt(void) {
@@ -493,18 +502,13 @@ uint8 SPIClass::nssPin(void) {
  */
 
 uint8 SPIClass::send(uint8 data) {
-    uint8 buf[] = {data};
-    return this->send(buf, 1);
+    this->write(data);
+    return 1;
 }
 
 uint8 SPIClass::send(uint8 *buf, uint32 len) {
-    uint32 txed = 0;
-    uint8 ret = 0;
-    while (txed < len) {
-        this->write(buf[txed++]);
-        ret = this->read();
-    }
-    return ret;
+    this->write(buf, len);
+    return len;
 }
 
 uint8 SPIClass::recv(void) {
diff --git a/STM32F1/libraries/SPI/src/SPI.h b/STM32F1/libraries/SPI/src/SPI.h
index 717a2e90c..b66238426 100644
--- a/STM32F1/libraries/SPI/src/SPI.h
+++ b/STM32F1/libraries/SPI/src/SPI.h
@@ -256,7 +256,7 @@ class SPIClass {
      * @param buffer Bytes/words to transmit.
      * @param length Number of bytes/words in buffer to transmit.
      */
-    void write(const void * buffer, uint32 length);
+    void write(void * buffer, uint32 length);
 
     /**
      * @brief Transmit a byte, then return the next unread byte.

From aa79ea1d6e5838bba1041f333c20f0758536452c Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Wed, 24 May 2017 18:40:41 +0200
Subject: [PATCH 088/307] Adafruit_ILI9341_STM - reworked for 16 bit SPI
 register accesses

---
 .../Adafruit_ILI9341_STM.cpp                  | 24 ++++---------------
 .../Adafruit_ILI9341_STM.h                    |  8 +++++--
 2 files changed, 11 insertions(+), 21 deletions(-)

diff --git a/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.cpp b/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.cpp
index e21f33cbd..db57b3e56 100644
--- a/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.cpp
+++ b/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.cpp
@@ -36,7 +36,7 @@ Adafruit_ILI9341_STM::Adafruit_ILI9341_STM(int8_t cs, int8_t dc, int8_t rst) : A
 }
 
 
-void Adafruit_ILI9341_STM::spiwrite(uint8_t c) {
+void Adafruit_ILI9341_STM::spiwrite(uint16_t c) {
 
   //Serial.print("0x"); Serial.print(c, HEX); Serial.print(", ");
 
@@ -178,10 +178,7 @@ void Adafruit_ILI9341_STM::begin(void) {
     SPI.setBitOrder(MSBFIRST);
     SPI.setDataMode(SPI_MODE0);
 #elif defined (__STM32F1__)
-    SPI.begin();
-    SPI.setClockDivider(SPI_CLOCK_DIV2);
-    SPI.setBitOrder(MSBFIRST);
-    SPI.setDataMode(SPI_MODE0);
+    SPI.beginTransaction(SPISettings(36000000));
 
 #elif defined (__arm__)
     SPI.begin();
@@ -335,6 +332,7 @@ void Adafruit_ILI9341_STM::begin(void) {
   if (hwSPI) spi_begin();
   writecommand(ILI9341_DISPON);    //Display on
   if (hwSPI) spi_end();
+  if (hwSPI) SPI.setDataSize(SPI_CR1_DFF);
 
 }
 
@@ -345,18 +343,14 @@ void Adafruit_ILI9341_STM::setAddrWindow(uint16_t x0, uint16_t y0, uint16_t x1,
   writecommand(ILI9341_CASET); // Column addr set
   *dcport |=  dcpinmask;
   *csport &= ~cspinmask;
-  SPI.setDataSize (SPI_CR1_DFF);
   SPI.write(x0);
   SPI.write(x1);
-//  SPI.setDataSize (0);
   
   writecommand(ILI9341_PASET); // Row addr set
   *dcport |=  dcpinmask;
   *csport &= ~cspinmask;
-//  SPI.setDataSize (SPI_CR1_DFF);
   SPI.write(y0);
   SPI.write(y1);
-  SPI.setDataSize (0);
 
   writecommand(ILI9341_RAMWR); // write to RAM
 
@@ -385,7 +379,6 @@ void Adafruit_ILI9341_STM::pushColor(uint16_t color) {
   //digitalWrite(_cs, LOW);
   *csport &= ~cspinmask;
 
-  spiwrite(color >> 8);
   spiwrite(color);
 
   *csport |= cspinmask;
@@ -403,7 +396,6 @@ void Adafruit_ILI9341_STM::drawPixel(int16_t x, int16_t y, uint16_t color) {
   *dcport |=  dcpinmask;
   *csport &= ~cspinmask;
 
-  spiwrite(color >> 8);
   spiwrite(color);
 
   *csport |= cspinmask;
@@ -431,10 +423,8 @@ void Adafruit_ILI9341_STM::drawFastVLine(int16_t x, int16_t y, int16_t h,
   *csport &= ~cspinmask;
   
 #if defined (__STM32F1__)
-  SPI.setDataSize (SPI_CR1_DFF); // Set SPI 16bit mode
   lineBuffer[0] = color;
   SPI.dmaSend(lineBuffer, h, 0);
-  SPI.setDataSize (0);
  #else
   uint8_t hi = color >> 8, lo = color;
   while (h--) {
@@ -464,10 +454,8 @@ void Adafruit_ILI9341_STM::drawFastHLine(int16_t x, int16_t y, int16_t w,
   *csport &= ~cspinmask;
 
 #if defined (__STM32F1__)
-  SPI.setDataSize (SPI_CR1_DFF); // Set spi 16bit mode
   lineBuffer[0] = color;
   SPI.dmaSend(lineBuffer, w, 0);
-  SPI.setDataSize (0);
 #else
 	uint8_t hi = color >> 8, lo = color;
     while (w--) {
@@ -485,11 +473,9 @@ void Adafruit_ILI9341_STM::fillScreen(uint16_t color) {
   setAddrWindow(0, 0, _width - 1, _height - 1);
   *dcport |=  dcpinmask;
   *csport &= ~cspinmask;
-  SPI.setDataSize (SPI_CR1_DFF); // Set spi 16bit mode
   lineBuffer[0] = color;
   SPI.dmaSend(lineBuffer, (65535), 0);
   SPI.dmaSend(lineBuffer, ((_width * _height) - 65535), 0);
-  SPI.setDataSize (0);
 
 #else
   fillRect(0, 0,  _width, _height, color);
@@ -515,7 +501,6 @@ void Adafruit_ILI9341_STM::fillRect(int16_t x, int16_t y, int16_t w, int16_t h,
   *dcport |=  dcpinmask;
   *csport &= ~cspinmask;
 #if defined (__STM32F1__)
-  SPI.setDataSize (SPI_CR1_DFF); // Set spi 16bit mode
   lineBuffer[0] = color;
   if (w*h <= 65535) {
   SPI.dmaSend(lineBuffer, (w*h), 0);
@@ -524,7 +509,6 @@ void Adafruit_ILI9341_STM::fillRect(int16_t x, int16_t y, int16_t w, int16_t h,
   SPI.dmaSend(lineBuffer, (65535), 0);
   SPI.dmaSend(lineBuffer, ((w*h) - 65535), 0);
   }
-  SPI.setDataSize (0);
 #else
   uint8_t hi = color >> 8, lo = color;
   for(y=h; y>0; y--) 
@@ -672,6 +656,7 @@ uint16_t Adafruit_ILI9341_STM::color565(uint8_t r, uint8_t g, uint8_t b) {
 void Adafruit_ILI9341_STM::setRotation(uint8_t m) {
 
   if (hwSPI) spi_begin();
+  if (hwSPI) SPI.setDataSize(0);
   writecommand(ILI9341_MADCTL);
   rotation = m % 4; // can't be higher than 3
   switch (rotation) {
@@ -696,6 +681,7 @@ void Adafruit_ILI9341_STM::setRotation(uint8_t m) {
       _height = ILI9341_TFTWIDTH;
       break;
   }
+  if (hwSPI) SPI.setDataSize(SPI_CR1_DFF);
   if (hwSPI) spi_end();
 }
 
diff --git a/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.h b/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.h
index a716c2769..6554bc046 100644
--- a/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.h
+++ b/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.h
@@ -8,9 +8,13 @@ This library has been modified for the Maple Mini
 
 #include "Arduino.h"
 #include "Print.h"
-#include <Adafruit_GFX_AS.h>
+#include <Adafruit_GFX.h>
 #include <avr/pgmspace.h>
 
+#ifndef swap
+  #define swap(a, b) { int16_t t = a; a = b; b = t; }
+#endif
+
 #define ILI9341_TFTWIDTH  240
 #define ILI9341_TFTHEIGHT 320
 
@@ -125,7 +129,7 @@ class Adafruit_ILI9341_STM : public Adafruit_GFX {
   void     dummyclock(void);
   */  
 
-  void     spiwrite(uint8_t),
+  void     spiwrite(uint16_t),
     writecommand(uint8_t c),
     writedata(uint8_t d),
     commandList(uint8_t *addr);

From c6fe342d0f46256a5ccf581237f4b42c5c7b163c Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Thu, 25 May 2017 17:59:48 +1000
Subject: [PATCH 089/307] Add prototype for systick_attach_callback (thanks to
 @ag123)

---
 STM32F1/system/libmaple/include/libmaple/systick.h | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/STM32F1/system/libmaple/include/libmaple/systick.h b/STM32F1/system/libmaple/include/libmaple/systick.h
index 551f8000a..51d0c567f 100644
--- a/STM32F1/system/libmaple/include/libmaple/systick.h
+++ b/STM32F1/system/libmaple/include/libmaple/systick.h
@@ -108,6 +108,12 @@ static inline uint32 systick_check_underflow(void) {
     return SYSTICK_BASE->CSR & SYSTICK_CSR_COUNTFLAG;
 }
 
+/**
+ * @brief prototype for systick_attach_callback
+ *
+ */
+extern void systick_attach_callback(void (*callback)(void));
+
 #ifdef __cplusplus
 } // extern "C"
 #endif

From c3d9d1bc1e36b44a3d5f1c39bb145194df8d8b1f Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Thu, 25 May 2017 18:16:47 +1000
Subject: [PATCH 090/307] Added define for LED_BUILTIN to Maple mini and
 generic STM32F103C (on PC13 to suit the BluePill)

---
 STM32F1/variants/generic_stm32f103c/board/board.h | 2 ++
 STM32F1/variants/maple_mini/board/board.h         | 2 ++
 2 files changed, 4 insertions(+)

diff --git a/STM32F1/variants/generic_stm32f103c/board/board.h b/STM32F1/variants/generic_stm32f103c/board/board.h
index d2a4fd659..97231e09f 100644
--- a/STM32F1/variants/generic_stm32f103c/board/board.h
+++ b/STM32F1/variants/generic_stm32f103c/board/board.h
@@ -73,6 +73,8 @@
 #define BOARD_USB_DISC_DEV        GPIOB
 #define BOARD_USB_DISC_BIT        10
 
+#define LED_BUILTIN PC13
+
 // Note this needs to match with the PIN_MAP array in board.cpp
 enum {
     PA0, PA1, PA2, PA3, PA4, PA5, PA6, PA7, PA8, PA9, PA10, PA11, PA12, PA13,PA14,PA15,
diff --git a/STM32F1/variants/maple_mini/board/board.h b/STM32F1/variants/maple_mini/board/board.h
index b7a54a8b1..10bcb5a69 100644
--- a/STM32F1/variants/maple_mini/board/board.h
+++ b/STM32F1/variants/maple_mini/board/board.h
@@ -71,6 +71,8 @@
 #define BOARD_USB_DISC_DEV        GPIOB
 #define BOARD_USB_DISC_BIT        9
 
+#define LED_BUILTIN PB1
+
 enum {
     PB11, PB10, PB2, PB0, PA7, PA6, PA5, PA4, PA3, PA2, PA1, PA0, PC15, PC14,
     PC13, PB7, PB6, PB5, PB4, PB3, PA15, PA14, PA13, PA12, PA11, PA10, PA9,

From 782b53119d7ee0c8dec605421c5bf5be60f622a4 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Thu, 25 May 2017 10:18:27 +0200
Subject: [PATCH 091/307] used GFX library changed back to GFX_AS

---
 STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.h b/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.h
index 6554bc046..137b7a4b5 100644
--- a/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.h
+++ b/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.h
@@ -8,7 +8,7 @@ This library has been modified for the Maple Mini
 
 #include "Arduino.h"
 #include "Print.h"
-#include <Adafruit_GFX.h>
+#include <Adafruit_GFX_AS.h>
 #include <avr/pgmspace.h>
 
 #ifndef swap

From 437834a91fafc15bac2f24b9e889ddd259e86a72 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Thu, 25 May 2017 20:06:37 +1000
Subject: [PATCH 092/307] Added code by @danieleff to delay leaving the
 maple_upload script (in all platforms) until the Serial device has
 reconnected - this helps resolve the problem of needing to close the Arduino
 Serial Monitor prior to upload

---
 tools/linux/maple_upload   |  9 +++++++++
 tools/linux64/maple_upload |  9 +++++++++
 tools/macosx/maple_upload  |  9 +++++++++
 tools/win/maple_upload.bat | 10 ++++++++++
 4 files changed, 37 insertions(+)

diff --git a/tools/linux/maple_upload b/tools/linux/maple_upload
index e799f3a90..195317468 100755
--- a/tools/linux/maple_upload
+++ b/tools/linux/maple_upload
@@ -38,3 +38,12 @@ if [ ! -x "${DFU_UTIL}" ]; then
 fi
 
 "${DFU_UTIL}" -d ${usbID} -a ${altID} -D ${binfile} ${dfuse_addr} -R
+
+echo -n Waiting for ${dummy_port_fullpath} serial...
+
+COUNTER=0
+while [ ! -c ${dummy_port_fullpath} ] && ((COUNTER++ < 40)); do
+    sleep 0.1
+done
+
+echo Done
diff --git a/tools/linux64/maple_upload b/tools/linux64/maple_upload
index e799f3a90..27e006c22 100755
--- a/tools/linux64/maple_upload
+++ b/tools/linux64/maple_upload
@@ -38,3 +38,12 @@ if [ ! -x "${DFU_UTIL}" ]; then
 fi
 
 "${DFU_UTIL}" -d ${usbID} -a ${altID} -D ${binfile} ${dfuse_addr} -R
+
+echo -n Waiting for ${dummy_port_fullpath} serial...
+
+COUNTER=0
+while [ ! -c ${dummy_port_fullpath} ] && ((COUNTER++ < 40)); do
+    sleep 0.1
+done
+
+echo Done
\ No newline at end of file
diff --git a/tools/macosx/maple_upload b/tools/macosx/maple_upload
index 8d15eff8f..3521aa1ef 100755
--- a/tools/macosx/maple_upload
+++ b/tools/macosx/maple_upload
@@ -51,3 +51,12 @@ if [ ! -x ${DFU_UTIL} ]; then
 fi
 
 ${DFU_UTIL} -d ${usbID} -a ${altID} -D ${binfile} -R ${dfuse_addr} -R
+
+echo -n Waiting for ${dummy_port_fullpath} serial...
+
+COUNTER=0
+while [ ! -c ${dummy_port_fullpath} ] && ((COUNTER++ < 40)); do
+    sleep 0.1
+done
+
+echo Done
diff --git a/tools/win/maple_upload.bat b/tools/win/maple_upload.bat
index 678969c56..7d59bf53b 100644
--- a/tools/win/maple_upload.bat
+++ b/tools/win/maple_upload.bat
@@ -6,3 +6,13 @@ set driverLetter=%driverLetter:~0,2%
 %driverLetter%
 cd %~dp0
 java -jar maple_loader.jar %1 %2 %3 %4 %5 %6 %7 %8 %9
+
+for /l %%x in (1, 1, 40) do (
+  ping -w 50 -n 1 192.0.2.1 > nul
+  mode %1 > nul
+  if ERRORLEVEL 0 goto comPortFound
+)
+
+echo timeout waiting for %1 serial
+
+:comPortFound

From d3058d39f077daceea2573fd1fbe6255b5cc1497 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Thu, 25 May 2017 20:29:01 +1000
Subject: [PATCH 093/307] Fixed F4 ADC typo as noted by @stevstrong in reply to
 issue #265

---
 STM32F4/cores/maple/libmaple/adc.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/STM32F4/cores/maple/libmaple/adc.h b/STM32F4/cores/maple/libmaple/adc.h
index 3a40d4c58..bff18d904 100644
--- a/STM32F4/cores/maple/libmaple/adc.h
+++ b/STM32F4/cores/maple/libmaple/adc.h
@@ -166,7 +166,7 @@ extern const adc_dev *ADC3;
 #define ADC_CR2_ALIGN_BIT               11
 #define ADC_CR2_JEXTTRIG_BIT            15
 #define ADC_CR2_EXTTRIG_BIT             20
-#define ADC_CR2_TSEREFE_BIT             23
+#define ADC_CR2_TSVREFE_BIT             23
 #ifdef STM32F2
 #define ADC_CR2_JSWSTART_BIT            22
 #define ADC_CR2_SWSTART_BIT             30
@@ -191,7 +191,7 @@ extern const adc_dev *ADC3;
 #define ADC_CR2_EXTTRIG                 BIT(ADC_CR2_EXTTRIG_BIT)
 #define ADC_CR2_JSWSTART                BIT(ADC_CR2_JSWSTART_BIT)
 #define ADC_CR2_SWSTART                 BIT(ADC_CR2_SWSTART_BIT)
-#define ADC_CR2_TSEREFE                 BIT(ADC_CR2_TSEREFE_BIT)
+#define ADC_CR2_TSVREFE                 BIT(ADC_CR2_TSVREFE_BIT)
 
 /* Sample time register 1 */
 

From 84dd9162304a21c3b0799cb113d87b014662706c Mon Sep 17 00:00:00 2001
From: Tom Vijlbrief <tvijlbrief@gmail.com>
Date: Thu, 25 May 2017 20:53:24 +0200
Subject: [PATCH 094/307] Fix documentation for usart_putc()

---
 STM32F1/system/libmaple/include/libmaple/usart.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/STM32F1/system/libmaple/include/libmaple/usart.h b/STM32F1/system/libmaple/include/libmaple/usart.h
index fa7c7fbdb..245ddab16 100644
--- a/STM32F1/system/libmaple/include/libmaple/usart.h
+++ b/STM32F1/system/libmaple/include/libmaple/usart.h
@@ -439,8 +439,8 @@ static inline void usart_disable_all(void) {
 /**
  * @brief Transmit one character on a serial port.
  *
- * This function blocks until the character has been successfully
- * transmitted.
+ * This function blocks until the character has been queued
+ * for transmission.
  *
  * @param dev Serial port to send on.
  * @param byte Byte to transmit.

From 66579ef8ef822fd188c11efd4e682d75b95126d8 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Fri, 26 May 2017 16:03:49 +1000
Subject: [PATCH 095/307] Added -std=gnu++11 and -std=gnu11 compile flags to F1
 and F4 platform.txt compile recipes

---
 STM32F1/platform.txt | 4 ++--
 STM32F4/platform.txt | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/STM32F1/platform.txt b/STM32F1/platform.txt
index 3ffde2e45..3da3070c9 100644
--- a/STM32F1/platform.txt
+++ b/STM32F1/platform.txt
@@ -16,13 +16,13 @@ compiler.warning_flags.all=-Wall -Wextra -DDEBUG_LEVEL=DEBUG_ALL
 # ----------------------
 compiler.path={runtime.tools.arm-none-eabi-gcc.path}/bin/
 compiler.c.cmd=arm-none-eabi-gcc
-compiler.c.flags=-c -g -Os {compiler.warning_flags} -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin} 
+compiler.c.flags=-c -g -Os {compiler.warning_flags} -std=gnu11 -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin} 
 compiler.c.elf.cmd=arm-none-eabi-g++
 compiler.c.elf.flags=-Os -Wl,--gc-sections
 compiler.S.cmd=arm-none-eabi-gcc
 compiler.S.flags=-c -g -x assembler-with-cpp -MMD
 compiler.cpp.cmd=arm-none-eabi-g++
-compiler.cpp.flags=-c -g -Os {compiler.warning_flags} -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin} 
+compiler.cpp.flags=-c -g -Os {compiler.warning_flags} -std=gnu++11 -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin} 
 compiler.ar.cmd=arm-none-eabi-ar
 compiler.ar.flags=rcs
 compiler.objcopy.cmd=arm-none-eabi-objcopy
diff --git a/STM32F4/platform.txt b/STM32F4/platform.txt
index 99ae55549..c43a061a3 100755
--- a/STM32F4/platform.txt
+++ b/STM32F4/platform.txt
@@ -12,13 +12,13 @@ version=0.1.0
 
 compiler.path={runtime.tools.arm-none-eabi-gcc.path}/bin/
 compiler.c.cmd=arm-none-eabi-gcc
-compiler.c.flags=-c -g -Os -w -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
+compiler.c.flags=-c -g -Os -w -MMD -std=gnu11 -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
 compiler.c.elf.cmd=arm-none-eabi-g++
 compiler.c.elf.flags=-Os -Wl,--gc-sections
 compiler.S.cmd=arm-none-eabi-gcc
 compiler.S.flags=-c -g -x assembler-with-cpp -MMD
 compiler.cpp.cmd=arm-none-eabi-g++
-compiler.cpp.flags=-c -g -Os -w -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
+compiler.cpp.flags=-c -g -Os -w -MMD -std=gnu++11 -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
 compiler.ar.cmd=arm-none-eabi-ar
 compiler.ar.flags=rcs
 compiler.objcopy.cmd=arm-none-eabi-objcopy

From f2c2323afde16917b5ba7059c677c54ef9ee0e8c Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Fri, 26 May 2017 16:22:16 +1000
Subject: [PATCH 096/307] Changed board variants to use calculate value from
 F_CPU for CYCLES_PER_MICROSECOND

---
 STM32F1/variants/STM32VLD/board/board.h            | 3 ++-
 STM32F1/variants/generic_gd32f103c/board/board.h   | 2 +-
 STM32F1/variants/generic_stm32f103c/board/board.h  | 2 +-
 STM32F1/variants/generic_stm32f103r8/board/board.h | 2 +-
 STM32F1/variants/generic_stm32f103t/board/board.h  | 2 +-
 STM32F1/variants/generic_stm32f103v/board/board.h  | 2 +-
 STM32F1/variants/hytiny_stm32f103t/board/board.h   | 2 +-
 STM32F1/variants/maple/board/board.h               | 2 +-
 STM32F1/variants/maple_mini/board/board.h          | 2 +-
 STM32F1/variants/microduino/board/board.h          | 2 +-
 STM32F1/variants/nucleo_f103rb/board/board.h       | 2 +-
 STM32F3/variants/discovery_f3/board/board.h        | 4 ++--
 12 files changed, 14 insertions(+), 13 deletions(-)

diff --git a/STM32F1/variants/STM32VLD/board/board.h b/STM32F1/variants/STM32VLD/board/board.h
index ba8d556c8..be2f19e7f 100644
--- a/STM32F1/variants/STM32VLD/board/board.h
+++ b/STM32F1/variants/STM32VLD/board/board.h
@@ -38,7 +38,8 @@
 
 
 
-#define CYCLES_PER_MICROSECOND    24
+//#define CYCLES_PER_MICROSECOND    24
+#define CYCLES_PER_MICROSECOND	(F_CPU / 1000000U)
 //#define SYSTICK_RELOAD_VAL     (F_CPU/1000) - 1 /* takes a cycle to reload */
 #define SYSTICK_RELOAD_VAL      23999  /* takes a cycle to reload */
 
diff --git a/STM32F1/variants/generic_gd32f103c/board/board.h b/STM32F1/variants/generic_gd32f103c/board/board.h
index 209bc3637..50dd98904 100644
--- a/STM32F1/variants/generic_gd32f103c/board/board.h
+++ b/STM32F1/variants/generic_gd32f103c/board/board.h
@@ -36,7 +36,7 @@
 #ifndef _BOARD_GENERIC_STM32F103C_H_
 #define _BOARD_GENERIC_STM32F103C_H_
 
-#define CYCLES_PER_MICROSECOND    72
+#define CYCLES_PER_MICROSECOND	(F_CPU / 1000000U)
 #define SYSTICK_RELOAD_VAL     (F_CPU/1000) - 1 /* takes a cycle to reload */
 
 #define BOARD_NR_USARTS           3
diff --git a/STM32F1/variants/generic_stm32f103c/board/board.h b/STM32F1/variants/generic_stm32f103c/board/board.h
index 97231e09f..09351a61a 100644
--- a/STM32F1/variants/generic_stm32f103c/board/board.h
+++ b/STM32F1/variants/generic_stm32f103c/board/board.h
@@ -36,7 +36,7 @@
 #ifndef _BOARD_GENERIC_STM32F103C_H_
 #define _BOARD_GENERIC_STM32F103C_H_
 
-#define CYCLES_PER_MICROSECOND    72
+#define CYCLES_PER_MICROSECOND	(F_CPU / 1000000U)
 #define SYSTICK_RELOAD_VAL     (F_CPU/1000) - 1 /* takes a cycle to reload */
 
 #define BOARD_NR_USARTS           3
diff --git a/STM32F1/variants/generic_stm32f103r8/board/board.h b/STM32F1/variants/generic_stm32f103r8/board/board.h
index 5f6855dca..c274d64a7 100644
--- a/STM32F1/variants/generic_stm32f103r8/board/board.h
+++ b/STM32F1/variants/generic_stm32f103r8/board/board.h
@@ -36,7 +36,7 @@
 #ifndef _BOARD_GENERIC_STM32F103R8_H_
 #define _BOARD_GENERIC_STM32F103R8_H_
 
-#define CYCLES_PER_MICROSECOND    72
+#define CYCLES_PER_MICROSECOND	(F_CPU / 1000000U)
 #define SYSTICK_RELOAD_VAL     (F_CPU/1000) - 1 /* takes a cycle to reload */
 
 #define BOARD_NR_USARTS           3
diff --git a/STM32F1/variants/generic_stm32f103t/board/board.h b/STM32F1/variants/generic_stm32f103t/board/board.h
index 5454958ee..9b261f6d5 100644
--- a/STM32F1/variants/generic_stm32f103t/board/board.h
+++ b/STM32F1/variants/generic_stm32f103t/board/board.h
@@ -36,7 +36,7 @@
 #ifndef _BOARD_GENERIC_STM32F103T_H_
 #define _BOARD_GENERIC_STM32F103T_H_
 
-#define CYCLES_PER_MICROSECOND    72
+#define CYCLES_PER_MICROSECOND	(F_CPU / 1000000U)
 #define SYSTICK_RELOAD_VAL     (F_CPU/1000) - 1 /* takes a cycle to reload */
 
 #define BOARD_NR_USARTS           2
diff --git a/STM32F1/variants/generic_stm32f103v/board/board.h b/STM32F1/variants/generic_stm32f103v/board/board.h
index 210dbf888..92f2bf8a1 100644
--- a/STM32F1/variants/generic_stm32f103v/board/board.h
+++ b/STM32F1/variants/generic_stm32f103v/board/board.h
@@ -38,7 +38,7 @@
 /* A few of these values will seem strange given that it's a
  * high-density board. */
 
-#define CYCLES_PER_MICROSECOND  72
+#define CYCLES_PER_MICROSECOND	(F_CPU / 1000000U)
 #define SYSTICK_RELOAD_VAL     (F_CPU/1000) - 1 /* takes a cycle to reload */
 
 #define BOARD_BUTTON_PIN        PC0
diff --git a/STM32F1/variants/hytiny_stm32f103t/board/board.h b/STM32F1/variants/hytiny_stm32f103t/board/board.h
index 194b2e581..179e5e5aa 100644
--- a/STM32F1/variants/hytiny_stm32f103t/board/board.h
+++ b/STM32F1/variants/hytiny_stm32f103t/board/board.h
@@ -36,7 +36,7 @@
 #ifndef _BOARD_GENERIC_STM32F103C_H_
 #define _BOARD_GENERIC_STM32F103C_H_
 
-#define CYCLES_PER_MICROSECOND    72
+#define CYCLES_PER_MICROSECOND	(F_CPU / 1000000U)
 #define SYSTICK_RELOAD_VAL     (F_CPU/1000) - 1 /* takes a cycle to reload */
 
 #define BOARD_NR_USARTS           2
diff --git a/STM32F1/variants/maple/board/board.h b/STM32F1/variants/maple/board/board.h
index caebcc78d..5a092861b 100644
--- a/STM32F1/variants/maple/board/board.h
+++ b/STM32F1/variants/maple/board/board.h
@@ -34,7 +34,7 @@
 #define _BOARD_MAPLE_H_
 
 /* 72 MHz -> 72 cycles per microsecond. */
-#define CYCLES_PER_MICROSECOND  72
+#define CYCLES_PER_MICROSECOND	(F_CPU / 1000000U)
 
 /* Roger clark
 
diff --git a/STM32F1/variants/maple_mini/board/board.h b/STM32F1/variants/maple_mini/board/board.h
index 10bcb5a69..9064807c7 100644
--- a/STM32F1/variants/maple_mini/board/board.h
+++ b/STM32F1/variants/maple_mini/board/board.h
@@ -36,7 +36,7 @@
 #ifndef _BOARD_MAPLE_MINI_H_
 #define _BOARD_MAPLE_MINI_H_
 
-#define CYCLES_PER_MICROSECOND    72
+#define CYCLES_PER_MICROSECOND	(F_CPU / 1000000U)
 #define SYSTICK_RELOAD_VAL     (F_CPU/1000) - 1 /* takes a cycle to reload */
 
 #define BOARD_NR_USARTS           3
diff --git a/STM32F1/variants/microduino/board/board.h b/STM32F1/variants/microduino/board/board.h
index 2a1295fa6..0c06363d1 100644
--- a/STM32F1/variants/microduino/board/board.h
+++ b/STM32F1/variants/microduino/board/board.h
@@ -37,7 +37,7 @@
 #ifndef _BOARD_MICRODUINO_STM32_H_
 #define _BOARD_MICRODUINO_STM32_H_
 
-#define CYCLES_PER_MICROSECOND    72
+#define CYCLES_PER_MICROSECOND	(F_CPU / 1000000U)
 #define SYSTICK_RELOAD_VAL     (F_CPU/1000) - 1 /* takes a cycle to reload */
 
 /* Roger Clark. 
diff --git a/STM32F1/variants/nucleo_f103rb/board/board.h b/STM32F1/variants/nucleo_f103rb/board/board.h
index 02f46d9c3..b27862dc3 100644
--- a/STM32F1/variants/nucleo_f103rb/board/board.h
+++ b/STM32F1/variants/nucleo_f103rb/board/board.h
@@ -33,7 +33,7 @@
 #ifndef _BOARD_MAPLE_H_
 #define _BOARD_MAPLE_H_
 #define _BOARD_NUCLEOF103RB_ 1 // hack for HardwareSerial.cpp for a new order of serials
-#define CYCLES_PER_MICROSECOND  72
+#define CYCLES_PER_MICROSECOND	(F_CPU / 1000000U)
 #define SYSTICK_RELOAD_VAL     (F_CPU/1000) - 1 /* takes a cycle to reload */
 
 /* Roger clark. Removed defines for LED pin and Button pin as they are not Arduino API defines */
diff --git a/STM32F3/variants/discovery_f3/board/board.h b/STM32F3/variants/discovery_f3/board/board.h
index 179dede0b..6b04a8be1 100644
--- a/STM32F3/variants/discovery_f3/board/board.h
+++ b/STM32F3/variants/discovery_f3/board/board.h
@@ -38,8 +38,8 @@
 
 #include <libmaple/stm32.h>
 
-#define CYCLES_PER_MICROSECOND    72
-#define SYSTICK_RELOAD_VAL     71999 /* takes a cycle to reload */
+#define CYCLES_PER_MICROSECOND	(F_CPU / 1000000U)
+#define SYSTICK_RELOAD_VAL     (F_CPU/1000) - 1 /* takes a cycle to reload */
 
 enum {
 		PC13, PC14, PC15,

From b19fc38e5e8e57f5df399e972edbc5968b5b16b3 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Fri, 26 May 2017 17:00:47 +1000
Subject: [PATCH 097/307] Applied change to fix issue in itoa.c and itoa.h with
 newer versions of GCC (using the changes from STM's fix,  in
 Arduino_Core_STM32)

---
 STM32F1/cores/maple/itoa.c | 6 +++++-
 STM32F1/cores/maple/itoa.h | 5 +++++
 STM32F4/cores/maple/itoa.c | 6 +++++-
 STM32F4/cores/maple/itoa.h | 5 +++++
 4 files changed, 20 insertions(+), 2 deletions(-)

diff --git a/STM32F1/cores/maple/itoa.c b/STM32F1/cores/maple/itoa.c
index fc3576602..ee74f829f 100644
--- a/STM32F1/cores/maple/itoa.c
+++ b/STM32F1/cores/maple/itoa.c
@@ -120,8 +120,12 @@ extern char* ltoa( long value, char *string, int radix )
 
   return string;
 }
-
+#if __GNUC__ > 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ > 9 || \
+   (__GNUC_MINOR__ == 9 && __GNUC_PATCHLEVEL__ > 2)))
+extern char* utoa( unsigned value, char *string, int radix )
+#else
 extern char* utoa( unsigned long value, char *string, int radix )
+#endif
 {
   return ultoa( value, string, radix ) ;
 }
diff --git a/STM32F1/cores/maple/itoa.h b/STM32F1/cores/maple/itoa.h
index 59af10947..b88204c0e 100644
--- a/STM32F1/cores/maple/itoa.h
+++ b/STM32F1/cores/maple/itoa.h
@@ -31,7 +31,12 @@ extern void itoa( int n, char s[] ) ;
 
 extern char* itoa( int value, char *string, int radix ) ;
 extern char* ltoa( long value, char *string, int radix ) ;
+#if __GNUC__ > 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ > 9 || \
+   (__GNUC_MINOR__ == 9 && __GNUC_PATCHLEVEL__ > 2)))
+extern char* utoa( unsigned value, char *string, int radix ) ;
+#else
 extern char* utoa( unsigned long value, char *string, int radix ) ;
+#endif
 extern char* ultoa( unsigned long value, char *string, int radix ) ;
 #endif /* 0 */
 
diff --git a/STM32F4/cores/maple/itoa.c b/STM32F4/cores/maple/itoa.c
index fc3576602..ee74f829f 100644
--- a/STM32F4/cores/maple/itoa.c
+++ b/STM32F4/cores/maple/itoa.c
@@ -120,8 +120,12 @@ extern char* ltoa( long value, char *string, int radix )
 
   return string;
 }
-
+#if __GNUC__ > 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ > 9 || \
+   (__GNUC_MINOR__ == 9 && __GNUC_PATCHLEVEL__ > 2)))
+extern char* utoa( unsigned value, char *string, int radix )
+#else
 extern char* utoa( unsigned long value, char *string, int radix )
+#endif
 {
   return ultoa( value, string, radix ) ;
 }
diff --git a/STM32F4/cores/maple/itoa.h b/STM32F4/cores/maple/itoa.h
index 59af10947..b88204c0e 100644
--- a/STM32F4/cores/maple/itoa.h
+++ b/STM32F4/cores/maple/itoa.h
@@ -31,7 +31,12 @@ extern void itoa( int n, char s[] ) ;
 
 extern char* itoa( int value, char *string, int radix ) ;
 extern char* ltoa( long value, char *string, int radix ) ;
+#if __GNUC__ > 4 || (__GNUC__ == 4 && (__GNUC_MINOR__ > 9 || \
+   (__GNUC_MINOR__ == 9 && __GNUC_PATCHLEVEL__ > 2)))
+extern char* utoa( unsigned value, char *string, int radix ) ;
+#else
 extern char* utoa( unsigned long value, char *string, int radix ) ;
+#endif
 extern char* ultoa( unsigned long value, char *string, int radix ) ;
 #endif /* 0 */
 

From 54a23097839088747206b363bf477bc53fdba01c Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Fri, 2 Jun 2017 17:25:32 +0200
Subject: [PATCH 098/307] corrected digitalPinToBitMask(P)

---
 STM32F4/variants/generic_f407v/variant.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F4/variants/generic_f407v/variant.h b/STM32F4/variants/generic_f407v/variant.h
index cd0a96de4..95a7f3928 100644
--- a/STM32F4/variants/generic_f407v/variant.h
+++ b/STM32F4/variants/generic_f407v/variant.h
@@ -3,7 +3,7 @@
 
 
 #define digitalPinToPort(P)        ( PIN_MAP[P].gpio_device )
-#define digitalPinToBitMask(P)     ( BIT(PIN_MAP[P].gpio_bit) )
+#define digitalPinToBitMask(P)     ( BIT(P&0x0F) )
 #define portOutputRegister(port)   ( &(port->regs->ODR) )
 #define portInputRegister(port)    ( &(port->regs->IDR) )
 

From 9e4b05289cff9067289bb32873c02c108a21b63d Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Fri, 2 Jun 2017 19:28:50 +0200
Subject: [PATCH 099/307] corrected digitalPinToBitMask(P)

---
 STM32F4/variants/generic_f407v/variant.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F4/variants/generic_f407v/variant.h b/STM32F4/variants/generic_f407v/variant.h
index cd0a96de4..95a7f3928 100644
--- a/STM32F4/variants/generic_f407v/variant.h
+++ b/STM32F4/variants/generic_f407v/variant.h
@@ -3,7 +3,7 @@
 
 
 #define digitalPinToPort(P)        ( PIN_MAP[P].gpio_device )
-#define digitalPinToBitMask(P)     ( BIT(PIN_MAP[P].gpio_bit) )
+#define digitalPinToBitMask(P)     ( BIT(P&0x0F) )
 #define portOutputRegister(port)   ( &(port->regs->ODR) )
 #define portInputRegister(port)    ( &(port->regs->IDR) )
 

From 1c097cc8c3bfa2eb15dd92794aa9cc3d828d18ce Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Fri, 2 Jun 2017 19:32:34 +0200
Subject: [PATCH 100/307] added pin modes: GPIO_AF_OUTPUT_PP_PU (for SDIO)

and GPIO_AF_INPUT_PU/PD
---
 .../cores/maple/libmaple/HardwareSerial.cpp   |  4 ++--
 STM32F4/cores/maple/libmaple/gpio_def.h       | 21 ++++++++++---------
 2 files changed, 13 insertions(+), 12 deletions(-)

diff --git a/STM32F4/cores/maple/libmaple/HardwareSerial.cpp b/STM32F4/cores/maple/libmaple/HardwareSerial.cpp
index f9387d15a..7f3d281a9 100644
--- a/STM32F4/cores/maple/libmaple/HardwareSerial.cpp
+++ b/STM32F4/cores/maple/libmaple/HardwareSerial.cpp
@@ -100,8 +100,8 @@ void HardwareSerial::begin(uint32 baud) {
         gpio_set_af_mode(tx_pin, 7);
         gpio_set_af_mode(rx_pin, 7);
     }
-    gpio_set_mode(tx_pin, (gpio_pin_mode)(GPIO_AF_OUTPUT_PP | GPIO_PUPD_INPUT_PU | 0x700));
-    gpio_set_mode(rx_pin, (gpio_pin_mode)(GPIO_MODE_AF      | GPIO_PUPD_INPUT_PU | 0x700));
+    gpio_set_mode(tx_pin, (gpio_pin_mode)(GPIO_AF_OUTPUT_PP_PU | 0x700));
+    gpio_set_mode(rx_pin, (gpio_pin_mode)(GPIO_AF_INPUT_PU | 0x700));
     //gpio_set_mode(txi->gpio_device, txi->gpio_bit, (gpio_pin_mode)(GPIO_PUPD_INPUT_PU));
     //gpio_set_mode(rxi->gpio_device, rxi->gpio_bit, (gpio_pin_mode)(GPIO_PUPD_INPUT_PU));
 #else
diff --git a/STM32F4/cores/maple/libmaple/gpio_def.h b/STM32F4/cores/maple/libmaple/gpio_def.h
index cd1fb3843..4a8e61e26 100644
--- a/STM32F4/cores/maple/libmaple/gpio_def.h
+++ b/STM32F4/cores/maple/libmaple/gpio_def.h
@@ -125,9 +125,9 @@ extern gpio_dev* const GPIOG;
 #define GPIO_MODE_AF                    2
 #define GPIO_MODE_ANALOG                3
 
-#define GPIO_PUPD_INPUT_FLOATING        (0 << 2)
-#define GPIO_PUPD_INPUT_PU              (1 << 2)
-#define GPIO_PUPD_INPUT_PD              (2 << 2)
+#define GPIO_PUPD_NONE            (0 << 2)
+#define GPIO_PUPD_PU              (1 << 2)
+#define GPIO_PUPD_PD              (2 << 2)
 
 #define GPIO_OSPEED_2MHZ                (0 << 4)
 #define GPIO_OSPEED_25MHZ               (1 << 4)
@@ -177,18 +177,19 @@ typedef enum gpio_pin_mode {
     GPIO_AF_OUTPUT_PP = (GPIO_MODE_AF | GPIO_OTYPE_PP |
                          GPIO_OSPEED_50MHZ), /**< Alternate function
                                                         output push-pull. */
+    GPIO_AF_OUTPUT_PP_PU = (GPIO_MODE_AF | GPIO_OTYPE_PP | GPIO_PUPD_PU |
+                         GPIO_OSPEED_50MHZ), /**< Alternate function
+                                                        output push-pull. */
     GPIO_AF_OUTPUT_OD = (GPIO_MODE_AF | GPIO_OTYPE_OD |
                          GPIO_OSPEED_50MHZ), /**< Alternate function
                                                         output open drain. */
     GPIO_INPUT_ANALOG = (GPIO_MODE_ANALOG), /**< Analog input. */
     GPIO_INPUT_FLOATING = (GPIO_MODE_INPUT |
-                           GPIO_PUPD_INPUT_FLOATING), /**< Input floating. */
-    GPIO_INPUT_PD = (GPIO_MODE_INPUT |
-                     GPIO_PUPD_INPUT_PD), /**< Input pull-down. */
-    GPIO_INPUT_PU = (GPIO_MODE_INPUT |
-                     GPIO_PUPD_INPUT_PU), /**< Input pull-up. */
-    GPIO_AF_INPUT_PD = (GPIO_MODE_AF |
-                     GPIO_PUPD_INPUT_PD), /**< Input pull-down. */
+                           GPIO_PUPD_NONE), /**< Input floating. */
+    GPIO_INPUT_PU = (GPIO_MODE_INPUT | GPIO_PUPD_PU), /**< Input pull-up. */
+    GPIO_INPUT_PD = (GPIO_MODE_INPUT | GPIO_PUPD_PD), /**< Input pull-down. */
+    GPIO_AF_INPUT_PU = (GPIO_MODE_AF | GPIO_PUPD_PU), /**< Alternate input pull-up. */
+    GPIO_AF_INPUT_PD = (GPIO_MODE_AF | GPIO_PUPD_PD), /**< Alternate input pull-down. */
 	GPIO_BIGNUMBER = 0xfff
 } gpio_pin_mode;
 

From cbd20e93844fac77258e635b9cf208ca1178b5b2 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Fri, 2 Jun 2017 19:35:32 +0200
Subject: [PATCH 101/307] corrected digitalPinToBitMask(P) for disco F4, too

---
 STM32F4/variants/discovery_f407/variant.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F4/variants/discovery_f407/variant.h b/STM32F4/variants/discovery_f407/variant.h
index 8a88623e7..8782ccc71 100644
--- a/STM32F4/variants/discovery_f407/variant.h
+++ b/STM32F4/variants/discovery_f407/variant.h
@@ -2,7 +2,7 @@
 #define _VARIANT_ARDUINO_STM32_
 
 #define digitalPinToPort(P)        ( PIN_MAP[P].gpio_device )
-#define digitalPinToBitMask(P)     ( BIT(PIN_MAP[P].gpio_bit) )
+#define digitalPinToBitMask(P)     ( BIT(P&0x0F) )
 #define portOutputRegister(port)   ( &(port->regs->ODR) )
 #define portInputRegister(port)    ( &(port->regs->IDR) )
 

From 642495bec9cbb4b8176bfa4ff208b78c7f84c48c Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Fri, 2 Jun 2017 19:37:36 +0200
Subject: [PATCH 102/307] corrected typo for BOARD_SDIO_CLK (generic F4)

---
 STM32F4/variants/generic_f407v/generic_f407v.h | 2 +-
 STM32F4/variants/generic_f407v/pin_map.c       | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/STM32F4/variants/generic_f407v/generic_f407v.h b/STM32F4/variants/generic_f407v/generic_f407v.h
index 24fae506c..bc3b77b69 100644
--- a/STM32F4/variants/generic_f407v/generic_f407v.h
+++ b/STM32F4/variants/generic_f407v/generic_f407v.h
@@ -103,7 +103,7 @@
 #define BOARD_SDIO_D1           PC9  //Port2Pin('C', 9)
 #define BOARD_SDIO_D2           PC10 //Port2Pin('C',10)
 #define BOARD_SDIO_D3           PC11 //Port2Pin('C',11)
-#define BOARD_SDIO_CK           PC12 //Port2Pin('C',12)
+#define BOARD_SDIO_CLK          PC12 //Port2Pin('C',12)
 #define BOARD_SDIO_CMD          PD2  //Port2Pin('D', 2)
 
 #define FSMC_NOE			PD4
diff --git a/STM32F4/variants/generic_f407v/pin_map.c b/STM32F4/variants/generic_f407v/pin_map.c
index 2189902d6..5ecde5367 100644
--- a/STM32F4/variants/generic_f407v/pin_map.c
+++ b/STM32F4/variants/generic_f407v/pin_map.c
@@ -198,7 +198,7 @@ const uint8 boardUsedPins[BOARD_NR_USED_PINS] = {
 	BOARD_JTMS_SWDIO_PIN, BOARD_JTCK_SWCLK_PIN,
 	FLASH_CS_PIN, FLASH_CLK_PIN, FLASH_DO_PIN, FLASH_DI_PIN,
 	NRF24_CE_PIN, NRF24_CS_PIN, NRF24_IRQ_PIN,
-	BOARD_SDIO_D0, BOARD_SDIO_D1, BOARD_SDIO_D2, BOARD_SDIO_D3, BOARD_SDIO_CK, BOARD_SDIO_CMD,
+	BOARD_SDIO_D0, BOARD_SDIO_D1, BOARD_SDIO_D2, BOARD_SDIO_D3, BOARD_SDIO_CLK, BOARD_SDIO_CMD,
 	USB_DM_PIN, USB_DP_PIN
 };
 

From 6dde3d39b401b01695c2844635331df1a1226b4e Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Fri, 2 Jun 2017 20:26:55 +0200
Subject: [PATCH 103/307] added serial bool operator for "if(!Serial)"

---
 STM32F4/cores/maple/libmaple/HardwareSerial.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/STM32F4/cores/maple/libmaple/HardwareSerial.h b/STM32F4/cores/maple/libmaple/HardwareSerial.h
index d7e8a3d1f..b49c4cfca 100644
--- a/STM32F4/cores/maple/libmaple/HardwareSerial.h
+++ b/STM32F4/cores/maple/libmaple/HardwareSerial.h
@@ -57,6 +57,7 @@ class HardwareSerial : public Stream {
     void begin(uint32 baud);
     void end(void);
 
+	operator bool() { return true; } // This is needed because of "if (!Serial)"
     /* I/O */
     virtual int available(void);
     virtual int peek(void);

From 9ae2f6fa78bc258d61a11fc3f0157fd3537780d0 Mon Sep 17 00:00:00 2001
From: Zou Hanya <hanyazou@gmail.com>
Date: Sat, 3 Jun 2017 08:27:33 +0900
Subject: [PATCH 104/307] Avoid initializing USB serial twice

---
 STM32F1/cores/maple/usb_serial.cpp | 5 +++++
 STM32F1/cores/maple/usb_serial.h   | 3 +++
 2 files changed, 8 insertions(+)

diff --git a/STM32F1/cores/maple/usb_serial.cpp b/STM32F1/cores/maple/usb_serial.cpp
index 5eaf70efb..32fe47191 100644
--- a/STM32F1/cores/maple/usb_serial.cpp
+++ b/STM32F1/cores/maple/usb_serial.cpp
@@ -55,6 +55,7 @@ static void ifaceSetupHook(unsigned, void*);
 
 #define USB_TIMEOUT 50
 
+bool USBSerial::_hasBegun = false;
 USBSerial::USBSerial(void) {
 #if !BOARD_HAVE_SERIALUSB
     ASSERT(0);
@@ -62,6 +63,9 @@ USBSerial::USBSerial(void) {
 }
 
 void USBSerial::begin(void) {
+    if (_hasBegun)
+        return;
+    _hasBegun = true;
 #if BOARD_HAVE_SERIALUSB
     usb_cdcacm_enable(BOARD_USB_DISC_DEV, BOARD_USB_DISC_BIT);
     usb_cdcacm_set_hooks(USB_CDCACM_HOOK_RX, rxHook);
@@ -90,6 +94,7 @@ void USBSerial::end(void) {
     usb_cdcacm_disable(BOARD_USB_DISC_DEV, BOARD_USB_DISC_BIT);
     usb_cdcacm_remove_hooks(USB_CDCACM_HOOK_RX | USB_CDCACM_HOOK_IFACE_SETUP);
 #endif
+    _hasBegun = false;
 }
 
 size_t USBSerial::write(uint8 ch) {
diff --git a/STM32F1/cores/maple/usb_serial.h b/STM32F1/cores/maple/usb_serial.h
index 96bbefc25..3146a3ca4 100644
--- a/STM32F1/cores/maple/usb_serial.h
+++ b/STM32F1/cores/maple/usb_serial.h
@@ -71,6 +71,9 @@ class USBSerial : public Stream {
     uint8 getDTR();
     uint8 isConnected();
     uint8 pending();
+
+protected:
+    static bool _hasBegun;
 };
 
 #ifdef SERIAL_USB 

From df78777e98a411036036388cb0ab809f35c6741a Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Tue, 6 Jun 2017 20:45:50 +1000
Subject: [PATCH 105/307] Add yield() call in delay() to support the Arduino
 Scheduler library. Ref issue #299

---
 STM32F1/cores/maple/wirish_time.cpp | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/STM32F1/cores/maple/wirish_time.cpp b/STM32F1/cores/maple/wirish_time.cpp
index 08fd2d189..6404bec15 100644
--- a/STM32F1/cores/maple/wirish_time.cpp
+++ b/STM32F1/cores/maple/wirish_time.cpp
@@ -32,11 +32,15 @@
 
 #include <libmaple/libmaple_types.h>
 #include <libmaple/delay.h>
+#include "Arduino.h"
 
 void delay(unsigned long ms) {
     uint32 start = millis();
-    while (millis() - start < ms)
-        ;
+	do
+	{
+		yield();
+	}
+    while (millis() - start < ms);
 }
 
 void delayMicroseconds(uint32 us) {

From 3c4307ebac3102bf95bc6fd7b637449860bef053 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Wed, 7 Jun 2017 14:00:24 +1000
Subject: [PATCH 106/307] Fix issue where USB Serial begin(xx) begin(xx,yy) did
 nothing, when they should ahave called begin()

---
 STM32F1/cores/maple/usb_serial.cpp | 13 ++++++++++---
 1 file changed, 10 insertions(+), 3 deletions(-)

diff --git a/STM32F1/cores/maple/usb_serial.cpp b/STM32F1/cores/maple/usb_serial.cpp
index 32fe47191..1fe2bf48e 100644
--- a/STM32F1/cores/maple/usb_serial.cpp
+++ b/STM32F1/cores/maple/usb_serial.cpp
@@ -54,8 +54,10 @@ static void ifaceSetupHook(unsigned, void*);
  */
 
 #define USB_TIMEOUT 50
-
+#if BOARD_HAVE_SERIALUSB
 bool USBSerial::_hasBegun = false;
+#endif
+
 USBSerial::USBSerial(void) {
 #if !BOARD_HAVE_SERIALUSB
     ASSERT(0);
@@ -63,10 +65,12 @@ USBSerial::USBSerial(void) {
 }
 
 void USBSerial::begin(void) {
+	
+#if BOARD_HAVE_SERIALUSB
     if (_hasBegun)
         return;
     _hasBegun = true;
-#if BOARD_HAVE_SERIALUSB
+
     usb_cdcacm_enable(BOARD_USB_DISC_DEV, BOARD_USB_DISC_BIT);
     usb_cdcacm_set_hooks(USB_CDCACM_HOOK_RX, rxHook);
     usb_cdcacm_set_hooks(USB_CDCACM_HOOK_IFACE_SETUP, ifaceSetupHook);
@@ -79,6 +83,7 @@ void USBSerial::begin(unsigned long ignoreBaud)
 volatile unsigned long removeCompilerWarningsIgnoreBaud=ignoreBaud;
 
 	ignoreBaud=removeCompilerWarningsIgnoreBaud;
+	begin();
 }
 void USBSerial::begin(unsigned long ignoreBaud, uint8_t ignore)
 {
@@ -87,14 +92,16 @@ volatile uint8_t removeCompilerWarningsIgnore=ignore;
 
 	ignoreBaud=removeCompilerWarningsIgnoreBaud;
 	ignore=removeCompilerWarningsIgnore;
+	begin();
 }
 
 void USBSerial::end(void) {
 #if BOARD_HAVE_SERIALUSB
     usb_cdcacm_disable(BOARD_USB_DISC_DEV, BOARD_USB_DISC_BIT);
     usb_cdcacm_remove_hooks(USB_CDCACM_HOOK_RX | USB_CDCACM_HOOK_IFACE_SETUP);
+	_hasBegun = false;
 #endif
-    _hasBegun = false;
+
 }
 
 size_t USBSerial::write(uint8 ch) {

From bf138eb389c50f68de28d708033442f8d4584c2b Mon Sep 17 00:00:00 2001
From: SukkoPera <software@sukkology.net>
Date: Fri, 9 Jun 2017 22:07:05 +0200
Subject: [PATCH 107/307] Remove isConnected() usage from examples

---
 .../examples/General/BlinkNcount/BlinkNcount.ino            | 2 +-
 .../examples/General/IntegerInput/IntegerInput.ino          | 2 +-
 .../IntegerInput_FloatOutput/IntegerInput_FloatOutput.ino   | 2 +-
 .../General/InternalTempSensor/InternalTempSensor.ino       | 6 +++---
 .../A_STM32_Examples/examples/General/PrimeNos/PrimeNos.ino | 2 +-
 .../examples/General/PrimeNos2/PrimeNos2.ino                | 2 +-
 .../examples/General/PrimeNos3/PrimeNos3.ino                | 2 +-
 .../examples/General/Print_Binary/Print_Binary.ino          | 2 +-
 .../examples/General/Print_Float/Print_Float.ino            | 2 +-
 .../examples/General/Print_HEX/Print_HEX.ino                | 2 +-
 .../examples/General/SerialReadUntil/SerialReadUntil.ino    | 2 +-
 .../examples/General/USB_ASCII/USB_ASCII.ino                | 2 +-
 .../General/strtol_DecEquivalents/strtol_DecEquivalents.ino | 2 +-
 13 files changed, 15 insertions(+), 15 deletions(-)

diff --git a/STM32F1/libraries/A_STM32_Examples/examples/General/BlinkNcount/BlinkNcount.ino b/STM32F1/libraries/A_STM32_Examples/examples/General/BlinkNcount/BlinkNcount.ino
index 7cabfde09..1b1f58a9f 100644
--- a/STM32F1/libraries/A_STM32_Examples/examples/General/BlinkNcount/BlinkNcount.ino
+++ b/STM32F1/libraries/A_STM32_Examples/examples/General/BlinkNcount/BlinkNcount.ino
@@ -15,7 +15,7 @@ void setup() {
   // Initialize virtual COM over USB on Maple Mini
   Serial.begin(9600);  // BAUD has no effect on USB serial: placeholder for physical UART
   // wait for serial monitor to be connected.
-  while (!(Serial.isConnected() && (Serial.getDTR() || Serial.getRTS())))
+  while (!Serial)
   {
     digitalWrite(33,!digitalRead(33));// Turn the LED from off to on, or on to off
     delay(100);         // fast blink
diff --git a/STM32F1/libraries/A_STM32_Examples/examples/General/IntegerInput/IntegerInput.ino b/STM32F1/libraries/A_STM32_Examples/examples/General/IntegerInput/IntegerInput.ino
index 55a68e8c8..4a1d16acb 100644
--- a/STM32F1/libraries/A_STM32_Examples/examples/General/IntegerInput/IntegerInput.ino
+++ b/STM32F1/libraries/A_STM32_Examples/examples/General/IntegerInput/IntegerInput.ino
@@ -18,7 +18,7 @@ void setup()
   Serial.begin(BAUD);  // BAUD has no effect on USB serial: placeholder for physical UART
   Serial.setTimeout(timeoutPeriod); // default is 1 second
   // wait for serial monitor to be connected.
-  while (!(Serial.isConnected() && (Serial.getDTR() || Serial.getRTS())))
+  while (!Serial)
   {
     digitalWrite(33,!digitalRead(33));// Turn the LED from off to on, or on to off
     delay(100);         // fast blink
diff --git a/STM32F1/libraries/A_STM32_Examples/examples/General/IntegerInput_FloatOutput/IntegerInput_FloatOutput.ino b/STM32F1/libraries/A_STM32_Examples/examples/General/IntegerInput_FloatOutput/IntegerInput_FloatOutput.ino
index 6f0484022..b82394ec8 100644
--- a/STM32F1/libraries/A_STM32_Examples/examples/General/IntegerInput_FloatOutput/IntegerInput_FloatOutput.ino
+++ b/STM32F1/libraries/A_STM32_Examples/examples/General/IntegerInput_FloatOutput/IntegerInput_FloatOutput.ino
@@ -19,7 +19,7 @@ void setup()
   Serial.begin(BAUD);  // BAUD has no effect on USB serial: placeholder for physical UART
   Serial.setTimeout(timeoutPeriod); // default is 1 second
   // wait for serial monitor to be connected.
-  while (!(Serial.isConnected() && (Serial.getDTR() || Serial.getRTS())))
+  while (!Serial)
   {
     digitalWrite(33,!digitalRead(33));// Turn the LED from off to on, or on to off
     delay(100);         // fast blink
diff --git a/STM32F1/libraries/A_STM32_Examples/examples/General/InternalTempSensor/InternalTempSensor.ino b/STM32F1/libraries/A_STM32_Examples/examples/General/InternalTempSensor/InternalTempSensor.ino
index d6000cdf8..871ae254d 100644
--- a/STM32F1/libraries/A_STM32_Examples/examples/General/InternalTempSensor/InternalTempSensor.ino
+++ b/STM32F1/libraries/A_STM32_Examples/examples/General/InternalTempSensor/InternalTempSensor.ino
@@ -38,7 +38,7 @@ void setup(void)
   pinMode(A_RANDOM_ANALOG_PIN, INPUT_ANALOG);
 
 // wait for serial monitor to be connected.
-  while (!(Serial.isConnected() && (Serial.getDTR() || Serial.getRTS())))
+  while (!Serial)
   {
     digitalWrite(33,!digitalRead(33));// Turn the LED from off to on, or on to off
     delay(100);         // fast blink
@@ -48,7 +48,7 @@ void setup(void)
   setup_temperature_sensor();
   
 // announce start up
-  if(Serial.isConnected() && (Serial.getDTR() || Serial.getRTS()))
+  if(Serial)
     Serial.println("Temp mon startup");
 }
 
@@ -69,7 +69,7 @@ void loop(void)
   t2 = micros();
   vsense = adc_read(ADC1, 16);
   t3 = micros();
-  if(Serial.isConnected() && (Serial.getDTR() || Serial.getRTS())) {
+  if(Serial) {
     sprintf(buf,"%04x %08x  %04x %08x" , vsense, t3-t2, alogpin, t2-t1);
     Serial.println(buf);
   }
diff --git a/STM32F1/libraries/A_STM32_Examples/examples/General/PrimeNos/PrimeNos.ino b/STM32F1/libraries/A_STM32_Examples/examples/General/PrimeNos/PrimeNos.ino
index 09a7a3fbe..c744219d4 100644
--- a/STM32F1/libraries/A_STM32_Examples/examples/General/PrimeNos/PrimeNos.ino
+++ b/STM32F1/libraries/A_STM32_Examples/examples/General/PrimeNos/PrimeNos.ino
@@ -29,7 +29,7 @@ void setup()
   pinMode(33, OUTPUT);
   Serial.begin(BAUD);  // BAUD has no effect on USB serial: placeholder for physical UART
   // wait for serial monitor to be connected.
-  while (!(Serial.isConnected() && (Serial.getDTR() || Serial.getRTS())))
+  while (!Serial)
   {
     digitalWrite(33,!digitalRead(33));// Turn the LED from off to on, or on to off
     delay(100);         // fast blink
diff --git a/STM32F1/libraries/A_STM32_Examples/examples/General/PrimeNos2/PrimeNos2.ino b/STM32F1/libraries/A_STM32_Examples/examples/General/PrimeNos2/PrimeNos2.ino
index 51fe33216..a2fd1c99e 100644
--- a/STM32F1/libraries/A_STM32_Examples/examples/General/PrimeNos2/PrimeNos2.ino
+++ b/STM32F1/libraries/A_STM32_Examples/examples/General/PrimeNos2/PrimeNos2.ino
@@ -18,7 +18,7 @@ void setup() {
   pinMode(33, OUTPUT);
   Serial.begin(BAUD);  // BAUD has no effect on USB serial: placeholder for physical UART
   // wait for serial monitor to be connected.
-  while (!(Serial.isConnected() && (Serial.getDTR() || Serial.getRTS())))
+  while (!Serial)
   {
     digitalWrite(33,!digitalRead(33));// Turn the LED from off to on, or on to off
     delay(100);         // fast blink
diff --git a/STM32F1/libraries/A_STM32_Examples/examples/General/PrimeNos3/PrimeNos3.ino b/STM32F1/libraries/A_STM32_Examples/examples/General/PrimeNos3/PrimeNos3.ino
index eec3dc0f3..8e8fe88d7 100644
--- a/STM32F1/libraries/A_STM32_Examples/examples/General/PrimeNos3/PrimeNos3.ino
+++ b/STM32F1/libraries/A_STM32_Examples/examples/General/PrimeNos3/PrimeNos3.ino
@@ -18,7 +18,7 @@ void setup() {
   pinMode(33, OUTPUT);
   Serial.begin(BAUD);  // BAUD has no effect on USB serial: placeholder for physical UART
   // wait for serial monitor to be connected.
-  while (!(Serial.isConnected() && (Serial.getDTR() || Serial.getRTS())))
+  while (!Serial)
   {
     digitalWrite(33,!digitalRead(33));// Turn the LED from off to on, or on to off
     delay(100);         // fast blink
diff --git a/STM32F1/libraries/A_STM32_Examples/examples/General/Print_Binary/Print_Binary.ino b/STM32F1/libraries/A_STM32_Examples/examples/General/Print_Binary/Print_Binary.ino
index c9c4b883a..7409ba5fb 100644
--- a/STM32F1/libraries/A_STM32_Examples/examples/General/Print_Binary/Print_Binary.ino
+++ b/STM32F1/libraries/A_STM32_Examples/examples/General/Print_Binary/Print_Binary.ino
@@ -15,7 +15,7 @@ void setup()
   pinMode(33, OUTPUT);
   Serial.begin(BAUD);  // BAUD has no effect on USB serial: placeholder for physical UART
   // wait for serial monitor to be connected.
-  while (!(Serial.isConnected() && (Serial.getDTR() || Serial.getRTS())))
+  while (!Serial)
   {
     digitalWrite(33,!digitalRead(33));// Turn the LED from off to on, or on to off
     delay(100);         // fast blink
diff --git a/STM32F1/libraries/A_STM32_Examples/examples/General/Print_Float/Print_Float.ino b/STM32F1/libraries/A_STM32_Examples/examples/General/Print_Float/Print_Float.ino
index 289db9e58..4351d3189 100644
--- a/STM32F1/libraries/A_STM32_Examples/examples/General/Print_Float/Print_Float.ino
+++ b/STM32F1/libraries/A_STM32_Examples/examples/General/Print_Float/Print_Float.ino
@@ -17,7 +17,7 @@ void setup()                    // run once, when the sketch starts
   pinMode(33, OUTPUT);
   Serial.begin(BAUD);  // BAUD has no effect on USB serial: placeholder for physical UART
   // wait for serial monitor to be connected.
-  while (!(Serial.isConnected() && (Serial.getDTR() || Serial.getRTS())))
+  while (!Serial)
   {
     digitalWrite(33,!digitalRead(33));// Turn the LED from off to on, or on to off
     delay(100);         // fast blink
diff --git a/STM32F1/libraries/A_STM32_Examples/examples/General/Print_HEX/Print_HEX.ino b/STM32F1/libraries/A_STM32_Examples/examples/General/Print_HEX/Print_HEX.ino
index cfdb977b8..2dc41fe53 100644
--- a/STM32F1/libraries/A_STM32_Examples/examples/General/Print_HEX/Print_HEX.ino
+++ b/STM32F1/libraries/A_STM32_Examples/examples/General/Print_HEX/Print_HEX.ino
@@ -16,7 +16,7 @@ void setup()                    // run once, when the sketch starts
   pinMode(33, OUTPUT);
   Serial.begin(BAUD);  // BAUD has no effect on USB serial: placeholder for physical UART
   // wait for serial monitor to be connected.
-  while (!(Serial.isConnected() && (Serial.getDTR() || Serial.getRTS())))
+  while (!Serial)
   {
     digitalWrite(33,!digitalRead(33));// Turn the LED from off to on, or on to off
     delay(100);         // fast blink
diff --git a/STM32F1/libraries/A_STM32_Examples/examples/General/SerialReadUntil/SerialReadUntil.ino b/STM32F1/libraries/A_STM32_Examples/examples/General/SerialReadUntil/SerialReadUntil.ino
index 1e7d400be..80d3b3bea 100644
--- a/STM32F1/libraries/A_STM32_Examples/examples/General/SerialReadUntil/SerialReadUntil.ino
+++ b/STM32F1/libraries/A_STM32_Examples/examples/General/SerialReadUntil/SerialReadUntil.ino
@@ -13,7 +13,7 @@ void setup() {
   pinMode(33, OUTPUT);
   Serial.begin(BAUD);  // BAUD has no effect on USB serial: placeholder for physical UAR
     // wait for serial monitor to be connected.
-  while (!(Serial.isConnected() && (Serial.getDTR() || Serial.getRTS())))
+  while (!Serial)
   {
     digitalWrite(33,!digitalRead(33));// Turn the LED from off to on, or on to off
     delay(100);         // fast blink
diff --git a/STM32F1/libraries/A_STM32_Examples/examples/General/USB_ASCII/USB_ASCII.ino b/STM32F1/libraries/A_STM32_Examples/examples/General/USB_ASCII/USB_ASCII.ino
index e38b17602..a884978dc 100644
--- a/STM32F1/libraries/A_STM32_Examples/examples/General/USB_ASCII/USB_ASCII.ino
+++ b/STM32F1/libraries/A_STM32_Examples/examples/General/USB_ASCII/USB_ASCII.ino
@@ -34,7 +34,7 @@ void setup() {
   pinMode(33, OUTPUT);
   Serial.begin();  // USB does not require BAUD
   // wait for serial monitor to be connected.
-  while (!(Serial.isConnected() && (Serial.getDTR() || Serial.getRTS())))
+  while (!Serial)
   {
     digitalWrite(33,!digitalRead(33));// Turn the LED from off to on, or on to off
     delay(100);         // fast blink
diff --git a/STM32F1/libraries/A_STM32_Examples/examples/General/strtol_DecEquivalents/strtol_DecEquivalents.ino b/STM32F1/libraries/A_STM32_Examples/examples/General/strtol_DecEquivalents/strtol_DecEquivalents.ino
index 7d799af8d..f75947112 100644
--- a/STM32F1/libraries/A_STM32_Examples/examples/General/strtol_DecEquivalents/strtol_DecEquivalents.ino
+++ b/STM32F1/libraries/A_STM32_Examples/examples/General/strtol_DecEquivalents/strtol_DecEquivalents.ino
@@ -19,7 +19,7 @@ void setup() {
   pinMode(33, OUTPUT);
   Serial.begin(9600);
   // wait for serial monitor to be connected.
-  while (!(Serial.isConnected() && (Serial.getDTR() || Serial.getRTS())))
+  while (!Serial)
   {
     digitalWrite(33,!digitalRead(33));// Turn the LED from off to on, or on to off
     delay(100);         // fast blink

From c4643b265ec344365d9d547ac4f8859d2e20083c Mon Sep 17 00:00:00 2001
From: SukkoPera <software@sukkology.net>
Date: Fri, 9 Jun 2017 22:07:33 +0200
Subject: [PATCH 108/307] Remove isConnected() usage and binary zeros from
 StringEx_Parsinge xample

---
 .../StringEx_Parsing/StringEx_Parsing.ino     | Bin 3285 -> 3217 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)

diff --git a/STM32F1/libraries/A_STM32_Examples/examples/General/StringEx_Parsing/StringEx_Parsing.ino b/STM32F1/libraries/A_STM32_Examples/examples/General/StringEx_Parsing/StringEx_Parsing.ino
index d98193c351739023a243a659979419438b658719..fd30b4ca30fcbbae814efffd42c6611eba5a2119 100644
GIT binary patch
delta 69
zcmV-L0J{Ix8Ic*Vcmb1n0apWBL@blq0d$j30(G;+0yYB%Q)O~#VQjNG24V%1oeTX5
bTrfH?crs&LFq5GS7y$~CuL~6f3MwxOLQEB=

delta 157
zcmbOzc~x>l1tX)v<O;@cu15`XqFf#|%+*nte2K9HDCovi%BZk;H<KB&oknnKQD$O}
zUS_d#eqLT`a!G26hNgm=ngUEBJ+;IoBnT*0Q=<S?3ls_p3D(fm)ZF}?HHno;L1A(v
q_g{7fD}xH7WQNJ{JQ6YrTnbts;F_1Bke{YdRGJ6oa%t)FasdGN=r2S7


From 0444a3652709b2ed98de2fc708535859fa182727 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sun, 11 Jun 2017 15:35:14 +1000
Subject: [PATCH 109/307] Added an additional SPI API function dmaSendAsync
 which will start the a DMA send of a buffer and return immediately. The next
 time dmaSendAsync is called it waits if the previous transfer is not
 complete. Note the buffer is not copied, so ddouble buffering is needed to
 use this function

---
 STM32F1/libraries/SPI/src/SPI.cpp | 42 +++++++++++++++++++++++++++++++
 STM32F1/libraries/SPI/src/SPI.h   |  2 +-
 2 files changed, 43 insertions(+), 1 deletion(-)

diff --git a/STM32F1/libraries/SPI/src/SPI.cpp b/STM32F1/libraries/SPI/src/SPI.cpp
index 11080148f..f0d9f7f57 100644
--- a/STM32F1/libraries/SPI/src/SPI.cpp
+++ b/STM32F1/libraries/SPI/src/SPI.cpp
@@ -469,6 +469,48 @@ uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length, bool minc)
 	return b;
 }
 
+
+uint8 SPIClass::dmaSendAsync(void * transmitBuf, uint16 length, bool minc)
+{
+	static bool isRunning=false;
+	uint8 b = 0;	
+
+	if (isRunning)
+	{
+
+		uint32_t m = millis();
+		while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
+			//delayMicroseconds(10);
+			if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
+		}		
+		
+		while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+		while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
+		spi_tx_dma_disable(_currentSetting->spi_d);
+		dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+		isRunning=false;
+	}
+
+	
+	if (length == 0) return 0;
+	uint32 flags = ( (DMA_MINC_MODE*minc) | DMA_FROM_MEM | DMA_TRNS_CMPLT);
+
+    dma_init(_currentSetting->spiDmaDev);
+	// TX
+	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
+    dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
+                       transmitBuf, dma_bit_size, flags);// Transmit buffer DMA 
+	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
+	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
+	spi_tx_dma_enable(_currentSetting->spi_d);	
+
+	isRunning=true;
+
+	return b;
+}
+
+
 void SPIClass::attachInterrupt(void) {
 	// Should be enableInterrupt()
 }
diff --git a/STM32F1/libraries/SPI/src/SPI.h b/STM32F1/libraries/SPI/src/SPI.h
index b66238426..4d9b563ed 100644
--- a/STM32F1/libraries/SPI/src/SPI.h
+++ b/STM32F1/libraries/SPI/src/SPI.h
@@ -291,7 +291,7 @@ class SPIClass {
      * @param length Number of bytes in buffer to transmit.
      */
 	uint8 dmaSend(void * transmitBuf, uint16 length, bool minc = 1);
-
+	uint8 dmaSendAsync(void * transmitBuf, uint16 length, bool minc = 1);
     /*
      * Pin accessors
      */

From f47846662db1c7aa61430ca5ffcde8ce9d6b9579 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sun, 11 Jun 2017 15:42:05 +1000
Subject: [PATCH 110/307] Added Wire.end() for bit banged version (TwoWire.cpp)

---
 STM32F1/libraries/Wire/Wire.cpp | 12 ++++++++++++
 STM32F1/libraries/Wire/Wire.h   |  9 +++++++++
 2 files changed, 21 insertions(+)

diff --git a/STM32F1/libraries/Wire/Wire.cpp b/STM32F1/libraries/Wire/Wire.cpp
index abc57f8fb..01ee72fd3 100644
--- a/STM32F1/libraries/Wire/Wire.cpp
+++ b/STM32F1/libraries/Wire/Wire.cpp
@@ -184,6 +184,18 @@ void TwoWire::begin(uint8 self_addr) {
     set_sda(HIGH);
 }
 
+void TwoWire::end()
+{
+	if (this->scl_pin)
+	{
+		pinMode(this->scl_pin, INPUT);
+	}
+	if (this->sda_pin)
+	{
+		pinMode(this->sda_pin, INPUT);
+	}
+}
+
 TwoWire::~TwoWire() {
     this->scl_pin=0;
     this->sda_pin=0;
diff --git a/STM32F1/libraries/Wire/Wire.h b/STM32F1/libraries/Wire/Wire.h
index add0ac972..c7edfefa6 100644
--- a/STM32F1/libraries/Wire/Wire.h
+++ b/STM32F1/libraries/Wire/Wire.h
@@ -111,6 +111,10 @@ class TwoWire : public WireBase {
      * Shifts out the data through SDA and clocks SCL for the slave device
      */
     void i2c_shift_out(uint8);
+	
+	
+
+	
  protected:
     /*
      * Processes the incoming I2C message defined by WireBase
@@ -130,6 +134,11 @@ class TwoWire : public WireBase {
      */
     void begin(uint8 = 0x00);
 
+    /*
+     * Sets pins SDA and SCL to INPUT
+     */
+	void end();	
+	
     /*
      * If object is destroyed, set pin numbers to 0.
      */

From 953aa8b88e0c9479e591c693a03b6fa37a64a73a Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sun, 11 Jun 2017 15:55:08 +1000
Subject: [PATCH 111/307] Added end() to HardWire (I2C)

---
 STM32F1/libraries/Wire/HardWire.cpp | 5 +++++
 STM32F1/libraries/Wire/HardWire.h   | 5 +++++
 2 files changed, 10 insertions(+)

diff --git a/STM32F1/libraries/Wire/HardWire.cpp b/STM32F1/libraries/Wire/HardWire.cpp
index 8a6318379..b3c1850df 100644
--- a/STM32F1/libraries/Wire/HardWire.cpp
+++ b/STM32F1/libraries/Wire/HardWire.cpp
@@ -75,3 +75,8 @@ HardWire::~HardWire() {
 void HardWire::begin(uint8 self_addr) {
     i2c_master_enable(sel_hard, dev_flags);
 }
+
+void HardWire:end() {
+    i2c_disable(sel_hard);
+    sel_hard = 0;
+}
diff --git a/STM32F1/libraries/Wire/HardWire.h b/STM32F1/libraries/Wire/HardWire.h
index 6f137b850..6f30cb331 100644
--- a/STM32F1/libraries/Wire/HardWire.h
+++ b/STM32F1/libraries/Wire/HardWire.h
@@ -59,6 +59,11 @@ class HardWire : public WireBase {
      * passed flags
      */
     HardWire(uint8, uint8 = 0);
+	
+	/*
+	 * Shuts down (disables) the hardware I2C
+	 */
+	void end();
 
     /*
      * Disables the I2C device and remove the device address.

From cc355255ac9b6358a4cd6e32b1d8216a49364764 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Mon, 12 Jun 2017 16:42:49 +1000
Subject: [PATCH 112/307] Added WS2812B (aka Neopixel) library using SPI DMA
 asynchronous transfers and double buffering

---
 STM32F1/libraries/WS2812B | 1 +
 1 file changed, 1 insertion(+)
 create mode 160000 STM32F1/libraries/WS2812B

diff --git a/STM32F1/libraries/WS2812B b/STM32F1/libraries/WS2812B
new file mode 160000
index 000000000..b7f1e2709
--- /dev/null
+++ b/STM32F1/libraries/WS2812B
@@ -0,0 +1 @@
+Subproject commit b7f1e2709e48f533e4d43aec3d36f8c48337bc31

From 7487d96f70ba3f78c00623556267cff6fb3a223c Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Tue, 13 Jun 2017 08:32:56 +1000
Subject: [PATCH 113/307] Fix typo in Hardware end()

---
 STM32F1/libraries/Wire/HardWire.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/libraries/Wire/HardWire.cpp b/STM32F1/libraries/Wire/HardWire.cpp
index b3c1850df..1f3ebf25e 100644
--- a/STM32F1/libraries/Wire/HardWire.cpp
+++ b/STM32F1/libraries/Wire/HardWire.cpp
@@ -76,7 +76,7 @@ void HardWire::begin(uint8 self_addr) {
     i2c_master_enable(sel_hard, dev_flags);
 }
 
-void HardWire:end() {
+void HardWire::end() {
     i2c_disable(sel_hard);
     sel_hard = 0;
 }

From 40dd7c6fe1a3f48a9657f54516737e80a78291a3 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Tue, 13 Jun 2017 10:37:16 +1000
Subject: [PATCH 114/307] Removed WS2812B lib as it had a .git folder in it
 which was causing problems

---
 STM32F1/libraries/WS2812B | 1 -
 1 file changed, 1 deletion(-)
 delete mode 160000 STM32F1/libraries/WS2812B

diff --git a/STM32F1/libraries/WS2812B b/STM32F1/libraries/WS2812B
deleted file mode 160000
index b7f1e2709..000000000
--- a/STM32F1/libraries/WS2812B
+++ /dev/null
@@ -1 +0,0 @@
-Subproject commit b7f1e2709e48f533e4d43aec3d36f8c48337bc31

From ca484b4fdd2efcc1338381021ac267a211751639 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Tue, 13 Jun 2017 10:38:05 +1000
Subject: [PATCH 115/307] Add WS2812B library again, but this time without the
 .git folder in it

---
 STM32F1/libraries/WS2812B/README.md           |  78 +++++
 .../examples/WS2812B_test/WS2812B_test.ino    | 303 ++++++++++++++++++
 STM32F1/libraries/WS2812B/keywords.txt        |  27 ++
 STM32F1/libraries/WS2812B/library.properties  |  10 +
 STM32F1/libraries/WS2812B/src/WS2812B.cpp     | 238 ++++++++++++++
 STM32F1/libraries/WS2812B/src/WS2812B.h       |  81 +++++
 6 files changed, 737 insertions(+)
 create mode 100644 STM32F1/libraries/WS2812B/README.md
 create mode 100644 STM32F1/libraries/WS2812B/examples/WS2812B_test/WS2812B_test.ino
 create mode 100644 STM32F1/libraries/WS2812B/keywords.txt
 create mode 100644 STM32F1/libraries/WS2812B/library.properties
 create mode 100644 STM32F1/libraries/WS2812B/src/WS2812B.cpp
 create mode 100644 STM32F1/libraries/WS2812B/src/WS2812B.h

diff --git a/STM32F1/libraries/WS2812B/README.md b/STM32F1/libraries/WS2812B/README.md
new file mode 100644
index 000000000..3f101445d
--- /dev/null
+++ b/STM32F1/libraries/WS2812B/README.md
@@ -0,0 +1,78 @@
+# WS2812B_STM32_Libmaple
+WS2812B (Neopixel) library for Arduino STM32 (Libmaple core)
+
+Written by Roger Clark www.rogerclark.net, from first principals
+
+This library uses SPI DMA to control a strip of WS2812B (NeoPixel) LEDS
+
+It should be generally compatible with the Adafruit NeoPixel library, 
+except I have not had chance to implement one or two of the lesser used functions
+
+Connect  Data In of the strip to SPI1 MOSI
+
+This library has only been tested on the WS2812B LED. It may not work with the older WS2812 or
+other types of addressable RGB LED, becuase it relies on a division multiple of the 72Mhz clock 
+frequence on the STM32 SPI to generate the correct width T0H pulse, of 400ns +/- 150nS
+SPI DIV32 gives a pulse width of 444nS which is well within spec for the WS2812B but
+is probably too long for the WS2812 which needs a 350ns pulse for T0H
+
+##Technical details
+
+The library uses SPI to send the mark/space encoded data to the LED's
+
+Each mark/space squarewave is generated by 3 bits of data
+A pixel 0 value is achieved by sending the bit pattern 100
+A pixel 1 value is achieved by sending the bit pattern 110
+
+Where the duration of each bit is 444nS
+Hence 100 generates a mark space value of 444/888nS
+and 110 generates a mark space value of 888/444nS
+
+This method results in the smallest storage requirement and the fastest send times,
+however because the 8 bit pixel channel data is encoded in 24 bits, (3 bytes) the values required in each of the 3 bytes to represent 
+a specific value is not easy to generate.
+
+The bit pattern in the 3 bytes is 
+88877766   65554443    33222111
+
+For speed of operation the values reqired for each byte for each of the 256 possible values is held in 3 separate 256 byte LUTS
+which were pre-computed by this function (which generates the full 24 bit pattern for a given input value (0-255)
+
+```
+uint32_t convert(uint8_t data)
+{
+  uint32_t out=0;
+  for(uint8_t mask = 0x80; mask; mask >>= 1)  
+  {
+    out=out<<3;
+    if (data & mask)
+    {
+      out = out | 0B110;//Bit high
+    }
+    else
+    {
+      out = out | 0B100;// bit low
+    }
+  }
+  return out;
+}
+```
+
+The STM32F103 has plenty of flash space (either 64 or 128k), so I used 256 byte LUTs even though the number of unique values in each LUT is 
+only 8,4 and 8 bytes respectively.
+However to use small LUTS requires shifting and masking of the input data, and the code was written with a preference for speed over binary size
+
+The encoded pixel buffer is 2 bytes longer than the actual encoded data.
+The first and last encoded bytes are all zeros. This is because the SPI hardware seems to preload MOSI with its output value before the start
+of the DMA transfer, which causes the first encoded pulse to be around 50ns longer than the subsequent bits, (around 490 or 500ns)
+This had the effect of causing the first LED to always think the MS bit of the green channel was set to High.
+
+So having the first encoded byte of zeros, is a work-around , as although the first encoded bit is still 490nS wide its a logic zero and is therefore
+not visible, becuase the default state is of the SPI when not transmitting data is logic zero
+The last byte was also set to all zeros, as occasionally MOSI seemed to be left set to logic high on completion of the SPI DMA send
+
+Adding these 2 bytes does slightly slow down the transfer, as it add 444ns * 8 = just over 3.5uS to both end.
+But the WS2812B theoretically requires a reset time of more than 50uS between transmissions, so 3.5uS can be part of that time.
+In reality the WS2812B seems to only need around 6uS of reset time, so for all practical purposes, there no delays are needed at all in the
+library to enforce the reset time, as the overead of the function call and the SPI DMA setup plus the 3.5uS gives the enough reset time.
+
diff --git a/STM32F1/libraries/WS2812B/examples/WS2812B_test/WS2812B_test.ino b/STM32F1/libraries/WS2812B/examples/WS2812B_test/WS2812B_test.ino
new file mode 100644
index 000000000..bf4934f88
--- /dev/null
+++ b/STM32F1/libraries/WS2812B/examples/WS2812B_test/WS2812B_test.ino
@@ -0,0 +1,303 @@
+#include <WS2812B.h>
+
+#define NUM_LEDS 30
+/*
+ * Note. Library uses SPI1
+ * Connect the WS2812B data input to MOSI on your board.
+ * 
+ */
+WS2812B strip = WS2812B(NUM_LEDS);
+// Note. Gamma is not really supported in the library, its only included as some functions used in this example require Gamma
+uint8_t LEDGamma[] = {
+    0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,
+    0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  0,  1,  1,  1,  1,
+    1,  1,  1,  1,  1,  1,  1,  1,  1,  2,  2,  2,  2,  2,  2,  2,
+    2,  3,  3,  3,  3,  3,  3,  3,  4,  4,  4,  4,  4,  5,  5,  5,
+    5,  6,  6,  6,  6,  7,  7,  7,  7,  8,  8,  8,  9,  9,  9, 10,
+   10, 10, 11, 11, 11, 12, 12, 13, 13, 13, 14, 14, 15, 15, 16, 16,
+   17, 17, 18, 18, 19, 19, 20, 20, 21, 21, 22, 22, 23, 24, 24, 25,
+   25, 26, 27, 27, 28, 29, 29, 30, 31, 32, 32, 33, 34, 35, 35, 36,
+   37, 38, 39, 39, 40, 41, 42, 43, 44, 45, 46, 47, 48, 49, 50, 50,
+   51, 52, 54, 55, 56, 57, 58, 59, 60, 61, 62, 63, 64, 66, 67, 68,
+   69, 70, 72, 73, 74, 75, 77, 78, 79, 81, 82, 83, 85, 86, 87, 89,
+   90, 92, 93, 95, 96, 98, 99,101,102,104,105,107,109,110,112,114,
+  115,117,119,120,122,124,126,127,129,131,133,135,137,138,140,142,
+  144,146,148,150,152,154,156,158,160,162,164,167,169,171,173,175,
+  177,180,182,184,186,189,191,193,196,198,200,203,205,208,210,213,
+215,218,220,223,225,228,231,233,236,239,241,244,247,249,252,255 };
+
+void setup() 
+{
+  strip.begin();// Sets up the SPI
+  strip.show();// Clears the strip, as by default the strip data is set to all LED's off.
+ // strip.setBrightness(8);
+}
+
+void loop() 
+{ 
+  colorWipe(strip.Color(0, 255, 0), 20); // Green
+  colorWipe(strip.Color(255, 0, 0), 20); // Red
+  colorWipe(strip.Color(0, 0, 255), 20); // Blue
+  rainbow(10);
+  rainbowCycle(10);
+  theaterChase(strip.Color(255, 0, 0), 20); // Red
+  theaterChase(strip.Color(0, 255, 0), 20); // Green
+  theaterChase(strip.Color(0, 0, 255), 20); // Blue
+  theaterChaseRainbow(10);
+  whiteOverRainbow(20,75,5);  
+  pulseWhite(5); 
+  delay(250);
+  fullWhite();
+  delay(250);
+  rainbowFade2White(3,3,1);
+}
+
+// Fill the dots one after the other with a color
+void colorWipe(uint32_t c, uint8_t wait) 
+{
+  for(uint16_t i=0; i<strip.numPixels(); i++) 
+  {
+      strip.setPixelColor(i, c);
+      strip.show();
+      delay(wait);
+  }
+}
+
+void rainbow(uint8_t wait) {
+  uint16_t i, j;
+
+  for(j=0; j<256; j++) {
+    for(i=0; i<strip.numPixels(); i++) 
+  {
+      strip.setPixelColor(i, Wheel((i+j) & 255));
+    }
+    strip.show();
+    delay(wait);
+  }
+}
+
+
+
+// Slightly different, this makes the rainbow equally distributed throughout
+void rainbowCycle(uint8_t wait) 
+{
+  uint16_t i, j;
+
+  for(j=0; j<256*5; j++) 
+  { // 5 cycles of all colors on wheel
+    for(i=0; i< strip.numPixels(); i++) 
+  {
+      strip.setPixelColor(i, Wheel(((i * 256 / strip.numPixels()) + j) & 255));
+    }
+    strip.show();
+    delay(wait);
+  }
+}
+
+// Input a value 0 to 255 to get a color value.
+// The colours are a transition r - g - b - back to r.
+uint32_t Wheel(byte WheelPos) 
+{
+  if(WheelPos < 85) 
+  {
+    return strip.Color(WheelPos * 3, 255 - WheelPos * 3, 0);
+  } 
+  else 
+  {
+    if(WheelPos < 170) 
+    {
+     WheelPos -= 85;
+     return strip.Color(255 - WheelPos * 3, 0, WheelPos * 3);
+    } 
+    else 
+    {
+     WheelPos -= 170;
+     return strip.Color(0, WheelPos * 3, 255 - WheelPos * 3);
+    }
+  }
+}
+
+//Theatre-style crawling lights.
+void theaterChase(uint32_t c, uint8_t wait) {
+  for (int j=0; j<10; j++) {  //do 10 cycles of chasing
+    for (int q=0; q < 3; q++) {
+      for (uint16_t i=0; i < strip.numPixels(); i=i+3) {
+        strip.setPixelColor(i+q, c);    //turn every third pixel on
+      }
+      strip.show();
+
+      delay(wait);
+
+      for (uint16_t i=0; i < strip.numPixels(); i=i+3) {
+        strip.setPixelColor(i+q, 0);        //turn every third pixel off
+      }
+    }
+  }
+}
+
+//Theatre-style crawling lights with rainbow effect
+void theaterChaseRainbow(uint8_t wait) {
+  for (int j=0; j < 256; j++) {     // cycle all 256 colors in the wheel
+    for (int q=0; q < 3; q++) {
+      for (uint16_t i=0; i < strip.numPixels(); i=i+3) {
+        strip.setPixelColor(i+q, Wheel( (i+j) % 255));    //turn every third pixel on
+      }
+      strip.show();
+
+      delay(wait);
+
+      for (uint16_t i=0; i < strip.numPixels(); i=i+3) {
+        strip.setPixelColor(i+q, 0);        //turn every third pixel off
+      }
+    }
+  }
+}
+
+void pulseWhite(uint8_t wait) {
+  for(int j = 0; j < 256 ; j++){
+      for(uint16_t i=0; i<strip.numPixels(); i++) {
+          strip.setPixelColor(i, strip.Color(0,0,0, LEDGamma[j] ) );
+        }
+        delay(wait);
+        strip.show();
+      }
+
+  for(int j = 255; j >= 0 ; j--){
+      for(uint16_t i=0; i<strip.numPixels(); i++) {
+          strip.setPixelColor(i, strip.Color(0,0,0, LEDGamma[j] ) );
+        }
+        delay(wait);
+        strip.show();
+      }
+}
+
+
+void rainbowFade2White(uint8_t wait, int rainbowLoops, int whiteLoops) {
+  float fadeMax = 100.0;
+  int fadeVal = 0;
+  uint32_t wheelVal;
+  int redVal, greenVal, blueVal;
+
+  for(int k = 0 ; k < rainbowLoops ; k ++){
+    
+    for(int j=0; j<256; j++) { // 5 cycles of all colors on wheel
+
+      for(int i=0; i< strip.numPixels(); i++) {
+
+        wheelVal = Wheel(((i * 256 / strip.numPixels()) + j) & 255);
+
+        redVal = red(wheelVal) * float(fadeVal/fadeMax);
+        greenVal = green(wheelVal) * float(fadeVal/fadeMax);
+        blueVal = blue(wheelVal) * float(fadeVal/fadeMax);
+
+        strip.setPixelColor( i, strip.Color( redVal, greenVal, blueVal ) );
+
+      }
+
+      //First loop, fade in!
+      if(k == 0 && fadeVal < fadeMax-1) {
+          fadeVal++;
+      }
+
+      //Last loop, fade out!
+      else if(k == rainbowLoops - 1 && j > 255 - fadeMax ){
+          fadeVal--;
+      }
+
+        strip.show();
+        delay(wait);
+    }
+  
+  }
+
+
+
+  delay(500);
+
+
+  for(int k = 0 ; k < whiteLoops ; k ++){
+
+    for(int j = 0; j < 256 ; j++){
+
+        for(uint16_t i=0; i < strip.numPixels(); i++) {
+            strip.setPixelColor(i, strip.Color(0,0,0, LEDGamma[j] ) );
+          }
+          strip.show();
+        }
+
+        delay(2000);
+    for(int j = 255; j >= 0 ; j--){
+
+        for(uint16_t i=0; i < strip.numPixels(); i++) {
+            strip.setPixelColor(i, strip.Color(0,0,0, LEDGamma[j] ) );
+          }
+          strip.show();
+        }
+  }
+
+  delay(500);
+
+
+}
+
+void whiteOverRainbow(uint8_t wait, uint8_t whiteSpeed, uint8_t whiteLength ) {
+  
+  if(whiteLength >= strip.numPixels()) whiteLength = strip.numPixels() - 1;
+
+  int head = whiteLength - 1;
+  int tail = 0;
+
+  int loops = 3;
+  int loopNum = 0;
+
+  static unsigned long lastTime = 0;
+
+
+  while(true){
+    for(int j=0; j<256; j++) {
+      for(uint16_t i=0; i<strip.numPixels(); i++) {
+        if((i >= tail && i <= head) || (tail > head && i >= tail) || (tail > head && i <= head) ){
+          strip.setPixelColor(i, strip.Color(0,0,0, 255 ) );
+        }
+        else{
+          strip.setPixelColor(i, Wheel(((i * 256 / strip.numPixels()) + j) & 255));
+        }
+        
+      }
+
+      if(millis() - lastTime > whiteSpeed) {
+        head++;
+        tail++;
+        if(head == strip.numPixels()){
+          loopNum++;
+        }
+        lastTime = millis();
+      }
+
+      if(loopNum == loops) return;
+    
+      head%=strip.numPixels();
+      tail%=strip.numPixels();
+        strip.show();
+        delay(wait);
+    }
+  }
+  
+}
+void fullWhite() {
+  
+    for(uint16_t i=0; i<strip.numPixels(); i++) {
+        strip.setPixelColor(i, strip.Color(0,0,0, 255 ) );
+    }
+      strip.show();
+}
+
+uint8_t red(uint32_t c) {
+  return (c >> 16);
+}
+uint8_t green(uint32_t c) {
+  return (c >> 8);
+}
+uint8_t blue(uint32_t c) {
+  return (c);
+}
diff --git a/STM32F1/libraries/WS2812B/keywords.txt b/STM32F1/libraries/WS2812B/keywords.txt
new file mode 100644
index 000000000..2d8b83a59
--- /dev/null
+++ b/STM32F1/libraries/WS2812B/keywords.txt
@@ -0,0 +1,27 @@
+#######################################
+# Syntax Coloring Map For WS2812B
+# Class
+#######################################
+
+WS2812B	KEYWORD1
+
+#######################################
+# Methods and Functions 
+#######################################	
+
+setPixelColor	KEYWORD2
+numPixels		KEYWORD2
+Color			KEYWORD2
+show			KEYWORD2
+
+clear			KEYWORD2
+updateLength			KEYWORD2
+
+canShow			KEYWORD2
+
+
+#######################################
+# Constants
+#######################################
+
+
diff --git a/STM32F1/libraries/WS2812B/library.properties b/STM32F1/libraries/WS2812B/library.properties
new file mode 100644
index 000000000..936976ddf
--- /dev/null
+++ b/STM32F1/libraries/WS2812B/library.properties
@@ -0,0 +1,10 @@
+name=WS2812B
+version=1.0
+author=Roger Clark, based on the Adafruit Neopixel library API
+email=
+sentence=WS2812B (Neopixel) library
+paragraph=WS2812B (Neopixel) library for STM32F1 LibMaple
+url=
+architectures=STM32F1
+maintainer=Roger Clark
+category=Uncategorized
\ No newline at end of file
diff --git a/STM32F1/libraries/WS2812B/src/WS2812B.cpp b/STM32F1/libraries/WS2812B/src/WS2812B.cpp
new file mode 100644
index 000000000..36483fccd
--- /dev/null
+++ b/STM32F1/libraries/WS2812B/src/WS2812B.cpp
@@ -0,0 +1,238 @@
+/*-----------------------------------------------------------------------------------------------
+  Arduino library to control WS2812B RGB Led strips using the Arduino STM32 LibMaple core
+  -----------------------------------------------------------------------------------------------
+ 
+  Note. 
+  This library has only been tested on the WS2812B LED. It may not work with the older WS2812 or
+  other types of addressable RGB LED, becuase it relies on a division multiple of the 72Mhz clock 
+  frequence on the STM32 SPI to generate the correct width T0H pulse, of 400ns +/- 150nS
+  SPI DIV32 gives a pulse width of 444nS which is well within spec for the WS2812B but
+  is probably too long for the WS2812 which needs a 350ns pulse for T0H
+ 
+  This WS2811B library is free software: you can redistribute it and/or modify
+  it under the terms of the GNU Lesser General Public License as
+  published by the Free Software Foundation, either version 3 of
+  the License, or (at your option) any later version.
+
+  It is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU Lesser General Public License for more details.
+
+  See   <http://www.gnu.org/licenses/>.
+  -----------------------------------------------------------------------------------------------*/
+
+#include "WS2812B.h"
+#include "pins_arduino.h"
+#include "wiring_private.h"
+#include <SPI.h>
+
+
+// Constructor when n is the number of LEDs in the strip
+WS2812B::WS2812B(uint16_t number_of_leds) :
+  brightness(0), pixels(NULL)
+{
+  updateLength(number_of_leds);
+}
+
+
+WS2812B::~WS2812B() 
+{
+  if(pixels)   
+  {
+	  free(pixels);
+  }
+  SPI.end();
+}
+
+void WS2812B::begin(void) {
+
+if (!begun)
+{
+  SPI.setClockDivider(SPI_CLOCK_DIV32);// need bit rate of 400nS but closest we can do @ 72Mhz is 444ns (which is within spec)
+  SPI.begin();
+  begun = true;
+}
+}
+
+void WS2812B::updateLength(uint16_t n)
+{
+  if(doubleBuffer) 
+  {
+	  free(doubleBuffer); 
+  }
+
+  numBytes = (n<<3) + n + 2; // 9 encoded bytes per pixel. 1 byte empty peamble to fix issue with SPI MOSI and on byte at the end to clear down MOSI 
+							// Note. (n<<3) +n is a fast way of doing n*9
+  if((doubleBuffer = (uint8_t *)malloc(numBytes*2)))
+  {
+    numLEDs = n;	 
+	pixels = doubleBuffer;
+	// Only need to init the part of the double buffer which will be interacted with by the API e.g. setPixelColor
+	*pixels=0;//clear the preamble byte
+	*(pixels+numBytes-1)=0;// clear the post send cleardown byte.
+	clear();// Set the encoded data to all encoded zeros 
+  } 
+  else 
+  {
+    numLEDs = numBytes = 0;
+  }
+}
+
+// Sends the current buffer to the leds
+void WS2812B::show(void) 
+{
+  SPI.dmaSendAsync(pixels,numBytes);// Start the DMA transfer of the current pixel buffer to the LEDs and return immediately.
+
+  // Need to copy the last / current buffer to the other half of the double buffer as most API code does not rebuild the entire contents
+  // from scratch. Often just a few pixels are changed e.g in a chaser effect
+  
+  if (pixels==doubleBuffer)
+  {
+	// pixels was using the first buffer
+	pixels	= doubleBuffer+numBytes;  // set pixels to second buffer
+	memcpy(pixels,doubleBuffer,numBytes);// copy first buffer to second buffer
+  }
+  else
+  {
+	// pixels was using the second buffer	  
+	pixels	= doubleBuffer;  // set pixels to first buffer
+	memcpy(pixels,doubleBuffer+numBytes,numBytes);	 // copy second buffer to first buffer 
+  }	
+}
+
+/*Sets a specific pixel to a specific r,g,b colour 
+* Because the pixels buffer contains the encoded bitstream, which is in triplets
+* the lookup table need to be used to find the correct pattern for each byte in the 3 byte sequence.
+*/
+void WS2812B::setPixelColor(uint16_t n, uint8_t r, uint8_t g, uint8_t b)
+ {
+   uint8_t *bptr = pixels + (n<<3) + n +1;
+   uint8_t *tPtr = (uint8_t *)encoderLookup + g*2 + g;// need to index 3 x g into the lookup
+   
+   *bptr++ = *tPtr++;
+   *bptr++ = *tPtr++;
+   *bptr++ = *tPtr++;
+
+   tPtr = (uint8_t *)encoderLookup + r*2 + r;
+   *bptr++ = *tPtr++;
+   *bptr++ = *tPtr++;
+   *bptr++ = *tPtr++;   
+   
+   tPtr = (uint8_t *)encoderLookup + b*2 + b;
+   *bptr++ = *tPtr++;
+   *bptr++ = *tPtr++;
+   *bptr++ = *tPtr++;
+ }
+
+void WS2812B::setPixelColor(uint16_t n, uint32_t c)
+  {
+     uint8_t r,g,b;
+   
+    if(brightness) 
+	{ 
+      r = ((int)((uint8_t)(c >> 16)) * (int)brightness) >> 8;
+      g = ((int)((uint8_t)(c >>  8)) * (int)brightness) >> 8;
+      b = ((int)((uint8_t)c) * (int)brightness) >> 8;
+	}
+	else
+	{
+      r = (uint8_t)(c >> 16),
+      g = (uint8_t)(c >>  8),
+	  b = (uint8_t)c;		
+	}
+	
+   uint8_t *bptr = pixels + (n<<3) + n +1;
+   uint8_t *tPtr = (uint8_t *)encoderLookup + g*2 + g;// need to index 3 x g into the lookup
+   
+   *bptr++ = *tPtr++;
+   *bptr++ = *tPtr++;
+   *bptr++ = *tPtr++;
+
+   tPtr = (uint8_t *)encoderLookup + r*2 + r;
+   *bptr++ = *tPtr++;
+   *bptr++ = *tPtr++;
+   *bptr++ = *tPtr++;   
+   
+   tPtr = (uint8_t *)encoderLookup + b*2 + b;
+   *bptr++ = *tPtr++;
+   *bptr++ = *tPtr++;
+   *bptr++ = *tPtr++;
+}
+
+// Convert separate R,G,B into packed 32-bit RGB color.
+// Packed format is always RGB, regardless of LED strand color order.
+uint32_t WS2812B::Color(uint8_t r, uint8_t g, uint8_t b) {
+  return ((uint32_t)r << 16) | ((uint32_t)g <<  8) | b;
+}
+
+// Convert separate R,G,B,W into packed 32-bit WRGB color.
+// Packed format is always WRGB, regardless of LED strand color order.
+uint32_t WS2812B::Color(uint8_t r, uint8_t g, uint8_t b, uint8_t w) {
+  return ((uint32_t)w << 24) | ((uint32_t)r << 16) | ((uint32_t)g <<  8) | b;
+}
+
+
+uint16_t WS2812B::numPixels(void) const {
+  return numLEDs;
+}
+
+// Adjust output brightness; 0=darkest (off), 255=brightest.  This does
+// NOT immediately affect what's currently displayed on the LEDs.  The
+// next call to show() will refresh the LEDs at this level.  However,
+// this process is potentially "lossy," especially when increasing
+// brightness.  The tight timing in the WS2811/WS2812 code means there
+// aren't enough free cycles to perform this scaling on the fly as data
+// is issued.  So we make a pass through the existing color data in RAM
+// and scale it (subsequent graphics commands also work at this
+// brightness level).  If there's a significant step up in brightness,
+// the limited number of steps (quantization) in the old data will be
+// quite visible in the re-scaled version.  For a non-destructive
+// change, you'll need to re-render the full strip data.  C'est la vie.
+void WS2812B::setBrightness(uint8_t b) {
+  // Stored brightness value is different than what's passed.
+  // This simplifies the actual scaling math later, allowing a fast
+  // 8x8-bit multiply and taking the MSB.  'brightness' is a uint8_t,
+  // adding 1 here may (intentionally) roll over...so 0 = max brightness
+  // (color values are interpreted literally; no scaling), 1 = min
+  // brightness (off), 255 = just below max brightness.
+  uint8_t newBrightness = b + 1;
+  if(newBrightness != brightness) { // Compare against prior value
+    // Brightness has changed -- re-scale existing data in RAM
+    uint8_t  c,
+            *ptr           = pixels,
+             oldBrightness = brightness - 1; // De-wrap old brightness value
+    uint16_t scale;
+    if(oldBrightness == 0) scale = 0; // Avoid /0
+    else if(b == 255) scale = 65535 / oldBrightness;
+    else scale = (((uint16_t)newBrightness << 8) - 1) / oldBrightness;
+    for(uint16_t i=0; i<numBytes; i++) 
+	{
+      c      = *ptr;
+      *ptr++ = (c * scale) >> 8;
+    }
+    brightness = newBrightness;
+  }
+}
+
+//Return the brightness value
+uint8_t WS2812B::getBrightness(void) const {
+  return brightness - 1;
+}
+
+/*
+*	Sets the encoded pixel data to turn all the LEDs off.
+*/
+void WS2812B::clear() 
+{
+	uint8_t * bptr= pixels+1;// Note first byte in the buffer is a preable and is always zero. hence the +1
+	uint8_t *tPtr;
+
+	for(int i=0;i< (numLEDs *3);i++)
+	{
+	   tPtr = (uint8_t *)encoderLookup;
+   	   *bptr++ = *tPtr++;
+	   *bptr++ = *tPtr++;
+	   *bptr++ = *tPtr++;	
+	}
+}
diff --git a/STM32F1/libraries/WS2812B/src/WS2812B.h b/STM32F1/libraries/WS2812B/src/WS2812B.h
new file mode 100644
index 000000000..30bc8753a
--- /dev/null
+++ b/STM32F1/libraries/WS2812B/src/WS2812B.h
@@ -0,0 +1,81 @@
+/*--------------------------------------------------------------------
+  The WS2812B library is free software: you can redistribute it and/or modify
+  it under the terms of the GNU Lesser General Public License as
+  published by the Free Software Foundation, either version 3 of
+  the License, or (at your option) any later version.
+
+  It is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+  GNU Lesser General Public License for more details.
+
+  See <http://www.gnu.org/licenses/>.
+  --------------------------------------------------------------------*/
+
+#ifndef WS2812B_H
+#define WS2812B_H
+
+#include <Arduino.h>
+/*
+ * old version used 3 separate tables, one per byte of the 24 bit encoded data
+ *
+static const uint8_t byte0Lookup[256]={0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x92,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x93,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9A,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0x9B,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD2,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xD3,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDA,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB,0xDB};
+static const uint8_t byte1Lookup[256]={0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x4D,0x4D,0x4D,0x4D,0x4D,0x4D,0x4D,0x4D,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x6D,0x6D,0x6D,0x6D,0x6D,0x6D,0x6D,0x6D,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x4D,0x4D,0x4D,0x4D,0x4D,0x4D,0x4D,0x4D,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x6D,0x6D,0x6D,0x6D,0x6D,0x6D,0x6D,0x6D,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x4D,0x4D,0x4D,0x4D,0x4D,0x4D,0x4D,0x4D,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x6D,0x6D,0x6D,0x6D,0x6D,0x6D,0x6D,0x6D,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x4D,0x4D,0x4D,0x4D,0x4D,0x4D,0x4D,0x4D,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x6D,0x6D,0x6D,0x6D,0x6D,0x6D,0x6D,0x6D,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x4D,0x4D,0x4D,0x4D,0x4D,0x4D,0x4D,0x4D,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x6D,0x6D,0x6D,0x6D,0x6D,0x6D,0x6D,0x6D,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x4D,0x4D,0x4D,0x4D,0x4D,0x4D,0x4D,0x4D,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x6D,0x6D,0x6D,0x6D,0x6D,0x6D,0x6D,0x6D,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x4D,0x4D,0x4D,0x4D,0x4D,0x4D,0x4D,0x4D,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x6D,0x6D,0x6D,0x6D,0x6D,0x6D,0x6D,0x6D,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x4D,0x4D,0x4D,0x4D,0x4D,0x4D,0x4D,0x4D,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x69,0x6D,0x6D,0x6D,0x6D,0x6D,0x6D,0x6D,0x6D};
+static const uint8_t byte2Lookup[256]={0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6};
+*/
+
+// New version uses one large LUT as its faster index into sequential bytes for the GRB pattern
+static const uint8_t encoderLookup[256*3]={	0x92,0x49,0x24,0x92,0x49,0x26,0x92,0x49,0x34,0x92,0x49,0x36,0x92,0x49,0xA4,0x92,0x49,0xA6,0x92,0x49,0xB4,0x92,0x49,0xB6,0x92,0x4D,0x24,0x92,0x4D,0x26,0x92,0x4D,0x34,0x92,0x4D,0x36,0x92,0x4D,0xA4,0x92,0x4D,0xA6,0x92,0x4D,0xB4,0x92,0x4D,0xB6,0x92,0x69,0x24,0x92,0x69,0x26,0x92,0x69,0x34,0x92,0x69,0x36,0x92,0x69,0xA4,0x92,0x69,0xA6,0x92,0x69,0xB4,0x92,0x69,0xB6,0x92,0x6D,0x24,0x92,0x6D,0x26,0x92,0x6D,0x34,0x92,0x6D,0x36,0x92,0x6D,0xA4,0x92,0x6D,0xA6,0x92,0x6D,0xB4,0x92,0x6D,0xB6,0x93,0x49,0x24,0x93,0x49,0x26,0x93,0x49,0x34,0x93,0x49,0x36,0x93,0x49,0xA4,0x93,0x49,0xA6,0x93,0x49,0xB4,0x93,0x49,0xB6,0x93,0x4D,0x24,0x93,0x4D,0x26,0x93,0x4D,0x34,0x93,0x4D,0x36,0x93,0x4D,0xA4,0x93,0x4D,0xA6,0x93,0x4D,0xB4,0x93,0x4D,0xB6,0x93,0x69,0x24,0x93,0x69,0x26,0x93,0x69,0x34,0x93,0x69,0x36,0x93,0x69,0xA4,0x93,0x69,0xA6,0x93,0x69,0xB4,0x93,0x69,0xB6,0x93,0x6D,0x24,0x93,0x6D,0x26,0x93,0x6D,0x34,0x93,0x6D,0x36,0x93,0x6D,0xA4,0x93,0x6D,0xA6,0x93,0x6D,0xB4,0x93,0x6D,0xB6,0x9A,0x49,0x24,0x9A,0x49,0x26,0x9A,0x49,0x34,0x9A,0x49,0x36,0x9A,0x49,0xA4,0x9A,0x49,0xA6,0x9A,0x49,0xB4,0x9A,0x49,0xB6,0x9A,0x4D,0x24,0x9A,0x4D,0x26,0x9A,0x4D,0x34,0x9A,0x4D,0x36,0x9A,0x4D,0xA4,0x9A,0x4D,0xA6,0x9A,0x4D,0xB4,0x9A,0x4D,0xB6,0x9A,0x69,0x24,0x9A,0x69,0x26,0x9A,0x69,0x34,0x9A,0x69,0x36,0x9A,0x69,0xA4,0x9A,0x69,\
+											0xA6,0x9A,0x69,0xB4,0x9A,0x69,0xB6,0x9A,0x6D,0x24,0x9A,0x6D,0x26,0x9A,0x6D,0x34,0x9A,0x6D,0x36,0x9A,0x6D,0xA4,0x9A,0x6D,0xA6,0x9A,0x6D,0xB4,0x9A,0x6D,0xB6,0x9B,0x49,0x24,0x9B,0x49,0x26,0x9B,0x49,0x34,0x9B,0x49,0x36,0x9B,0x49,0xA4,0x9B,0x49,0xA6,0x9B,0x49,0xB4,0x9B,0x49,0xB6,0x9B,0x4D,0x24,0x9B,0x4D,0x26,0x9B,0x4D,0x34,0x9B,0x4D,0x36,0x9B,0x4D,0xA4,0x9B,0x4D,0xA6,0x9B,0x4D,0xB4,0x9B,0x4D,0xB6,0x9B,0x69,0x24,0x9B,0x69,0x26,0x9B,0x69,0x34,0x9B,0x69,0x36,0x9B,0x69,0xA4,0x9B,0x69,0xA6,0x9B,0x69,0xB4,0x9B,0x69,0xB6,0x9B,0x6D,0x24,0x9B,0x6D,0x26,0x9B,0x6D,0x34,0x9B,0x6D,0x36,0x9B,0x6D,0xA4,0x9B,0x6D,0xA6,0x9B,0x6D,0xB4,0x9B,0x6D,0xB6,0xD2,0x49,0x24,0xD2,0x49,0x26,0xD2,0x49,0x34,0xD2,0x49,0x36,0xD2,0x49,0xA4,0xD2,0x49,0xA6,0xD2,0x49,0xB4,0xD2,0x49,0xB6,0xD2,0x4D,0x24,0xD2,0x4D,0x26,0xD2,0x4D,0x34,0xD2,0x4D,0x36,0xD2,0x4D,0xA4,0xD2,0x4D,0xA6,0xD2,0x4D,0xB4,0xD2,0x4D,0xB6,0xD2,0x69,0x24,0xD2,0x69,0x26,0xD2,0x69,0x34,0xD2,0x69,0x36,0xD2,0x69,0xA4,0xD2,0x69,0xA6,0xD2,0x69,0xB4,0xD2,0x69,0xB6,0xD2,0x6D,0x24,0xD2,0x6D,0x26,0xD2,0x6D,0x34,0xD2,0x6D,0x36,0xD2,0x6D,0xA4,0xD2,0x6D,0xA6,0xD2,0x6D,0xB4,0xD2,0x6D,0xB6,0xD3,0x49,0x24,0xD3,0x49,0x26,0xD3,0x49,0x34,0xD3,0x49,0x36,0xD3,0x49,0xA4,0xD3,0x49,0xA6,0xD3,0x49,0xB4,0xD3,0x49,0xB6,0xD3,0x4D,0x24,0xD3,0x4D,0x26,0xD3,0x4D,0x34,0xD3,\
+											0x4D,0x36,0xD3,0x4D,0xA4,0xD3,0x4D,0xA6,0xD3,0x4D,0xB4,0xD3,0x4D,0xB6,0xD3,0x69,0x24,0xD3,0x69,0x26,0xD3,0x69,0x34,0xD3,0x69,0x36,0xD3,0x69,0xA4,0xD3,0x69,0xA6,0xD3,0x69,0xB4,0xD3,0x69,0xB6,0xD3,0x6D,0x24,0xD3,0x6D,0x26,0xD3,0x6D,0x34,0xD3,0x6D,0x36,0xD3,0x6D,0xA4,0xD3,0x6D,0xA6,0xD3,0x6D,0xB4,0xD3,0x6D,0xB6,0xDA,0x49,0x24,0xDA,0x49,0x26,0xDA,0x49,0x34,0xDA,0x49,0x36,0xDA,0x49,0xA4,0xDA,0x49,0xA6,0xDA,0x49,0xB4,0xDA,0x49,0xB6,0xDA,0x4D,0x24,0xDA,0x4D,0x26,0xDA,0x4D,0x34,0xDA,0x4D,0x36,0xDA,0x4D,0xA4,0xDA,0x4D,0xA6,0xDA,0x4D,0xB4,0xDA,0x4D,0xB6,0xDA,0x69,0x24,0xDA,0x69,0x26,0xDA,0x69,0x34,0xDA,0x69,0x36,0xDA,0x69,0xA4,0xDA,0x69,0xA6,0xDA,0x69,0xB4,0xDA,0x69,0xB6,0xDA,0x6D,0x24,0xDA,0x6D,0x26,0xDA,0x6D,0x34,0xDA,0x6D,0x36,0xDA,0x6D,0xA4,0xDA,0x6D,0xA6,0xDA,0x6D,0xB4,0xDA,0x6D,0xB6,0xDB,0x49,0x24,0xDB,0x49,0x26,0xDB,0x49,0x34,0xDB,0x49,0x36,0xDB,0x49,0xA4,0xDB,0x49,0xA6,0xDB,0x49,0xB4,0xDB,0x49,0xB6,0xDB,0x4D,0x24,0xDB,0x4D,0x26,0xDB,0x4D,0x34,0xDB,0x4D,0x36,0xDB,0x4D,0xA4,0xDB,0x4D,0xA6,0xDB,0x4D,0xB4,0xDB,0x4D,0xB6,0xDB,0x69,0x24,0xDB,0x69,0x26,0xDB,0x69,0x34,0xDB,0x69,0x36,0xDB,0x69,0xA4,0xDB,0x69,0xA6,0xDB,0x69,0xB4,0xDB,0x69,0xB6,0xDB,0x6D,0x24,0xDB,0x6D,0x26,0xDB,0x6D,0x34,0xDB,0x6D,0x36,0xDB,0x6D,0xA4,0xDB,0x6D,0xA6,0xDB,0x6D,0xB4,0xDB,0x6D,0xB6};
+
+class WS2812B {
+ public:
+
+  // Constructor: number of LEDs
+  WS2812B (uint16_t number_of_leds);// Constuctor 
+    ~WS2812B();
+  void
+    begin(void),
+    show(void),
+    setPixelColor(uint16_t n, uint8_t r, uint8_t g, uint8_t b),
+ //   setPixelColor(uint16_t n, uint8_t r, uint8_t g, uint8_t b, uint8_t w),
+    setPixelColor(uint16_t n, uint32_t c),
+    setBrightness(uint8_t),
+    clear(),
+	updateLength(uint16_t n);
+  uint8_t
+//   *getPixels(void) const,
+    getBrightness(void) const;
+  uint16_t
+    numPixels(void) const;
+  static uint32_t
+    Color(uint8_t r, uint8_t g, uint8_t b),
+    Color(uint8_t r, uint8_t g, uint8_t b, uint8_t w);
+ // uint32_t
+ //   getPixelColor(uint16_t n) const;
+  inline bool
+    canShow(void) { return (micros() - endTime) >= 300L; }
+
+	private:
+
+  boolean
+    begun;         // true if begin() previously called
+  uint16_t
+    numLEDs,       // Number of RGB LEDs in strip
+    numBytes;      // Size of 'pixels' buffer
+	
+  uint8_t
+    brightness,
+   *pixels,        // Holds the current LED color values, which the external API calls interact with 9 bytes per pixel + start + end empty bytes
+   *doubleBuffer,	// Holds the start of the double buffer (1 buffer for async DMA transfer and one for the API interaction.
+    rOffset,       // Index of red byte within each 3- or 4-byte pixel
+    gOffset,       // Index of green byte
+    bOffset,       // Index of blue byte
+    wOffset;       // Index of white byte (same as rOffset if no white)
+  uint32_t
+    endTime;       // Latch timing reference
+};
+
+
+#endif // WS2812B_H

From aef93f74cde8f1127eb9b4c571d9f8fe910854b8 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Tue, 13 Jun 2017 10:39:42 +1000
Subject: [PATCH 116/307] Moved encoderLookup LUT from flash to RAM to give 30%
 speed increase of setPixelColor() - at the expense of 768 bytes of RAM

---
 STM32F1/libraries/WS2812B/src/WS2812B.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/libraries/WS2812B/src/WS2812B.h b/STM32F1/libraries/WS2812B/src/WS2812B.h
index 30bc8753a..3a6bcb60c 100644
--- a/STM32F1/libraries/WS2812B/src/WS2812B.h
+++ b/STM32F1/libraries/WS2812B/src/WS2812B.h
@@ -25,7 +25,7 @@ static const uint8_t byte2Lookup[256]={0x24,0x26,0x34,0x36,0xA4,0xA6,0xB4,0xB6,0
 */
 
 // New version uses one large LUT as its faster index into sequential bytes for the GRB pattern
-static const uint8_t encoderLookup[256*3]={	0x92,0x49,0x24,0x92,0x49,0x26,0x92,0x49,0x34,0x92,0x49,0x36,0x92,0x49,0xA4,0x92,0x49,0xA6,0x92,0x49,0xB4,0x92,0x49,0xB6,0x92,0x4D,0x24,0x92,0x4D,0x26,0x92,0x4D,0x34,0x92,0x4D,0x36,0x92,0x4D,0xA4,0x92,0x4D,0xA6,0x92,0x4D,0xB4,0x92,0x4D,0xB6,0x92,0x69,0x24,0x92,0x69,0x26,0x92,0x69,0x34,0x92,0x69,0x36,0x92,0x69,0xA4,0x92,0x69,0xA6,0x92,0x69,0xB4,0x92,0x69,0xB6,0x92,0x6D,0x24,0x92,0x6D,0x26,0x92,0x6D,0x34,0x92,0x6D,0x36,0x92,0x6D,0xA4,0x92,0x6D,0xA6,0x92,0x6D,0xB4,0x92,0x6D,0xB6,0x93,0x49,0x24,0x93,0x49,0x26,0x93,0x49,0x34,0x93,0x49,0x36,0x93,0x49,0xA4,0x93,0x49,0xA6,0x93,0x49,0xB4,0x93,0x49,0xB6,0x93,0x4D,0x24,0x93,0x4D,0x26,0x93,0x4D,0x34,0x93,0x4D,0x36,0x93,0x4D,0xA4,0x93,0x4D,0xA6,0x93,0x4D,0xB4,0x93,0x4D,0xB6,0x93,0x69,0x24,0x93,0x69,0x26,0x93,0x69,0x34,0x93,0x69,0x36,0x93,0x69,0xA4,0x93,0x69,0xA6,0x93,0x69,0xB4,0x93,0x69,0xB6,0x93,0x6D,0x24,0x93,0x6D,0x26,0x93,0x6D,0x34,0x93,0x6D,0x36,0x93,0x6D,0xA4,0x93,0x6D,0xA6,0x93,0x6D,0xB4,0x93,0x6D,0xB6,0x9A,0x49,0x24,0x9A,0x49,0x26,0x9A,0x49,0x34,0x9A,0x49,0x36,0x9A,0x49,0xA4,0x9A,0x49,0xA6,0x9A,0x49,0xB4,0x9A,0x49,0xB6,0x9A,0x4D,0x24,0x9A,0x4D,0x26,0x9A,0x4D,0x34,0x9A,0x4D,0x36,0x9A,0x4D,0xA4,0x9A,0x4D,0xA6,0x9A,0x4D,0xB4,0x9A,0x4D,0xB6,0x9A,0x69,0x24,0x9A,0x69,0x26,0x9A,0x69,0x34,0x9A,0x69,0x36,0x9A,0x69,0xA4,0x9A,0x69,\
+static uint8_t encoderLookup[256*3]={	0x92,0x49,0x24,0x92,0x49,0x26,0x92,0x49,0x34,0x92,0x49,0x36,0x92,0x49,0xA4,0x92,0x49,0xA6,0x92,0x49,0xB4,0x92,0x49,0xB6,0x92,0x4D,0x24,0x92,0x4D,0x26,0x92,0x4D,0x34,0x92,0x4D,0x36,0x92,0x4D,0xA4,0x92,0x4D,0xA6,0x92,0x4D,0xB4,0x92,0x4D,0xB6,0x92,0x69,0x24,0x92,0x69,0x26,0x92,0x69,0x34,0x92,0x69,0x36,0x92,0x69,0xA4,0x92,0x69,0xA6,0x92,0x69,0xB4,0x92,0x69,0xB6,0x92,0x6D,0x24,0x92,0x6D,0x26,0x92,0x6D,0x34,0x92,0x6D,0x36,0x92,0x6D,0xA4,0x92,0x6D,0xA6,0x92,0x6D,0xB4,0x92,0x6D,0xB6,0x93,0x49,0x24,0x93,0x49,0x26,0x93,0x49,0x34,0x93,0x49,0x36,0x93,0x49,0xA4,0x93,0x49,0xA6,0x93,0x49,0xB4,0x93,0x49,0xB6,0x93,0x4D,0x24,0x93,0x4D,0x26,0x93,0x4D,0x34,0x93,0x4D,0x36,0x93,0x4D,0xA4,0x93,0x4D,0xA6,0x93,0x4D,0xB4,0x93,0x4D,0xB6,0x93,0x69,0x24,0x93,0x69,0x26,0x93,0x69,0x34,0x93,0x69,0x36,0x93,0x69,0xA4,0x93,0x69,0xA6,0x93,0x69,0xB4,0x93,0x69,0xB6,0x93,0x6D,0x24,0x93,0x6D,0x26,0x93,0x6D,0x34,0x93,0x6D,0x36,0x93,0x6D,0xA4,0x93,0x6D,0xA6,0x93,0x6D,0xB4,0x93,0x6D,0xB6,0x9A,0x49,0x24,0x9A,0x49,0x26,0x9A,0x49,0x34,0x9A,0x49,0x36,0x9A,0x49,0xA4,0x9A,0x49,0xA6,0x9A,0x49,0xB4,0x9A,0x49,0xB6,0x9A,0x4D,0x24,0x9A,0x4D,0x26,0x9A,0x4D,0x34,0x9A,0x4D,0x36,0x9A,0x4D,0xA4,0x9A,0x4D,0xA6,0x9A,0x4D,0xB4,0x9A,0x4D,0xB6,0x9A,0x69,0x24,0x9A,0x69,0x26,0x9A,0x69,0x34,0x9A,0x69,0x36,0x9A,0x69,0xA4,0x9A,0x69,\
 											0xA6,0x9A,0x69,0xB4,0x9A,0x69,0xB6,0x9A,0x6D,0x24,0x9A,0x6D,0x26,0x9A,0x6D,0x34,0x9A,0x6D,0x36,0x9A,0x6D,0xA4,0x9A,0x6D,0xA6,0x9A,0x6D,0xB4,0x9A,0x6D,0xB6,0x9B,0x49,0x24,0x9B,0x49,0x26,0x9B,0x49,0x34,0x9B,0x49,0x36,0x9B,0x49,0xA4,0x9B,0x49,0xA6,0x9B,0x49,0xB4,0x9B,0x49,0xB6,0x9B,0x4D,0x24,0x9B,0x4D,0x26,0x9B,0x4D,0x34,0x9B,0x4D,0x36,0x9B,0x4D,0xA4,0x9B,0x4D,0xA6,0x9B,0x4D,0xB4,0x9B,0x4D,0xB6,0x9B,0x69,0x24,0x9B,0x69,0x26,0x9B,0x69,0x34,0x9B,0x69,0x36,0x9B,0x69,0xA4,0x9B,0x69,0xA6,0x9B,0x69,0xB4,0x9B,0x69,0xB6,0x9B,0x6D,0x24,0x9B,0x6D,0x26,0x9B,0x6D,0x34,0x9B,0x6D,0x36,0x9B,0x6D,0xA4,0x9B,0x6D,0xA6,0x9B,0x6D,0xB4,0x9B,0x6D,0xB6,0xD2,0x49,0x24,0xD2,0x49,0x26,0xD2,0x49,0x34,0xD2,0x49,0x36,0xD2,0x49,0xA4,0xD2,0x49,0xA6,0xD2,0x49,0xB4,0xD2,0x49,0xB6,0xD2,0x4D,0x24,0xD2,0x4D,0x26,0xD2,0x4D,0x34,0xD2,0x4D,0x36,0xD2,0x4D,0xA4,0xD2,0x4D,0xA6,0xD2,0x4D,0xB4,0xD2,0x4D,0xB6,0xD2,0x69,0x24,0xD2,0x69,0x26,0xD2,0x69,0x34,0xD2,0x69,0x36,0xD2,0x69,0xA4,0xD2,0x69,0xA6,0xD2,0x69,0xB4,0xD2,0x69,0xB6,0xD2,0x6D,0x24,0xD2,0x6D,0x26,0xD2,0x6D,0x34,0xD2,0x6D,0x36,0xD2,0x6D,0xA4,0xD2,0x6D,0xA6,0xD2,0x6D,0xB4,0xD2,0x6D,0xB6,0xD3,0x49,0x24,0xD3,0x49,0x26,0xD3,0x49,0x34,0xD3,0x49,0x36,0xD3,0x49,0xA4,0xD3,0x49,0xA6,0xD3,0x49,0xB4,0xD3,0x49,0xB6,0xD3,0x4D,0x24,0xD3,0x4D,0x26,0xD3,0x4D,0x34,0xD3,\
 											0x4D,0x36,0xD3,0x4D,0xA4,0xD3,0x4D,0xA6,0xD3,0x4D,0xB4,0xD3,0x4D,0xB6,0xD3,0x69,0x24,0xD3,0x69,0x26,0xD3,0x69,0x34,0xD3,0x69,0x36,0xD3,0x69,0xA4,0xD3,0x69,0xA6,0xD3,0x69,0xB4,0xD3,0x69,0xB6,0xD3,0x6D,0x24,0xD3,0x6D,0x26,0xD3,0x6D,0x34,0xD3,0x6D,0x36,0xD3,0x6D,0xA4,0xD3,0x6D,0xA6,0xD3,0x6D,0xB4,0xD3,0x6D,0xB6,0xDA,0x49,0x24,0xDA,0x49,0x26,0xDA,0x49,0x34,0xDA,0x49,0x36,0xDA,0x49,0xA4,0xDA,0x49,0xA6,0xDA,0x49,0xB4,0xDA,0x49,0xB6,0xDA,0x4D,0x24,0xDA,0x4D,0x26,0xDA,0x4D,0x34,0xDA,0x4D,0x36,0xDA,0x4D,0xA4,0xDA,0x4D,0xA6,0xDA,0x4D,0xB4,0xDA,0x4D,0xB6,0xDA,0x69,0x24,0xDA,0x69,0x26,0xDA,0x69,0x34,0xDA,0x69,0x36,0xDA,0x69,0xA4,0xDA,0x69,0xA6,0xDA,0x69,0xB4,0xDA,0x69,0xB6,0xDA,0x6D,0x24,0xDA,0x6D,0x26,0xDA,0x6D,0x34,0xDA,0x6D,0x36,0xDA,0x6D,0xA4,0xDA,0x6D,0xA6,0xDA,0x6D,0xB4,0xDA,0x6D,0xB6,0xDB,0x49,0x24,0xDB,0x49,0x26,0xDB,0x49,0x34,0xDB,0x49,0x36,0xDB,0x49,0xA4,0xDB,0x49,0xA6,0xDB,0x49,0xB4,0xDB,0x49,0xB6,0xDB,0x4D,0x24,0xDB,0x4D,0x26,0xDB,0x4D,0x34,0xDB,0x4D,0x36,0xDB,0x4D,0xA4,0xDB,0x4D,0xA6,0xDB,0x4D,0xB4,0xDB,0x4D,0xB6,0xDB,0x69,0x24,0xDB,0x69,0x26,0xDB,0x69,0x34,0xDB,0x69,0x36,0xDB,0x69,0xA4,0xDB,0x69,0xA6,0xDB,0x69,0xB4,0xDB,0x69,0xB6,0xDB,0x6D,0x24,0xDB,0x6D,0x26,0xDB,0x6D,0x34,0xDB,0x6D,0x36,0xDB,0x6D,0xA4,0xDB,0x6D,0xA6,0xDB,0x6D,0xB4,0xDB,0x6D,0xB6};
 

From f58a96e0f62aaa1415a3816fa0fb2d2bc5742950 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Sun, 18 Jun 2017 17:27:02 +0200
Subject: [PATCH 117/307] implemented SDIO

+ small changes in DMA - reworked get and clear ISR bits
+ wirish_time compatible with "C"
---
 .gitignore                           |   1 +
 STM32F4/cores/maple/libmaple/dmaF4.c |  12 +-
 STM32F4/cores/maple/libmaple/dmaF4.h | 159 ++++++++++-------
 STM32F4/cores/maple/libmaple/sdio.c  | 194 +++++++++++++++++++++
 STM32F4/cores/maple/libmaple/sdio.h  | 250 +++++++++++++++++++++++++++
 STM32F4/cores/maple/wirish_time.h    |   8 +
 6 files changed, 555 insertions(+), 69 deletions(-)
 create mode 100644 STM32F4/cores/maple/libmaple/sdio.c
 create mode 100644 STM32F4/cores/maple/libmaple/sdio.h

diff --git a/.gitignore b/.gitignore
index 05bb0a597..b538f89ed 100644
--- a/.gitignore
+++ b/.gitignore
@@ -7,3 +7,4 @@ other/maple-bootloader/build
 other/maple-bootloader/*~
 *.o
 tools/src/stm32flash_serial/src/parsers/parsers.a
+*.bak
diff --git a/STM32F4/cores/maple/libmaple/dmaF4.c b/STM32F4/cores/maple/libmaple/dmaF4.c
index add3d8e51..173f3a222 100644
--- a/STM32F4/cores/maple/libmaple/dmaF4.c
+++ b/STM32F4/cores/maple/libmaple/dmaF4.c
@@ -119,14 +119,14 @@ void dma_detach_interrupt(dma_dev *dev, dma_stream stream) {
 
 const uint8 dma_isr_bits_shift[] = { 0, 6, 16, 22};
 
-uint8 dma_get_isr_bits(dma_dev *dev, dma_stream stream) {
-	if ( stream&0xFC )	return ((dev->regs->HISR)>>dma_isr_bits_shift[stream&0x03]) & 0x3d;
-	else				return ((dev->regs->LISR)>>dma_isr_bits_shift[stream&0x03]) & 0x3d;
+uint8 dma_get_isr_bit(dma_dev *dev, dma_stream stream, uint8_t mask) {
+	if ( stream&0xFC )	return ((dev->regs->HISR)>>dma_isr_bits_shift[stream&0x03]) & mask;
+	else				return ((dev->regs->LISR)>>dma_isr_bits_shift[stream&0x03]) & mask;
 }
 
-void dma_clear_isr_bits(dma_dev *dev, dma_stream stream) {
-	if ( stream&0xFC )	dev->regs->HIFCR = (uint32)0x0000003d << dma_isr_bits_shift[stream&0x03];
-	else				dev->regs->LIFCR = (uint32)0x0000003d << dma_isr_bits_shift[stream&0x03];
+void dma_clear_isr_bit(dma_dev *dev, dma_stream stream, uint8_t mask) {
+	if ( stream&0xFC )	dev->regs->HIFCR = (uint32)mask << dma_isr_bits_shift[stream&0x03];
+	else				dev->regs->LIFCR = (uint32)mask << dma_isr_bits_shift[stream&0x03];
 }
 
 /*
diff --git a/STM32F4/cores/maple/libmaple/dmaF4.h b/STM32F4/cores/maple/libmaple/dmaF4.h
index 757906c82..cb2376069 100644
--- a/STM32F4/cores/maple/libmaple/dmaF4.h
+++ b/STM32F4/cores/maple/libmaple/dmaF4.h
@@ -62,30 +62,30 @@ typedef struct dma_stream_t {
     __io uint32 PAR;          /**< Stream peripheral address register */
     __io uint32 M0AR;         /**< Stream memory address register 0 */
     __io uint32 M1AR;         /**< Stream memory address register 1 */
-    __io uint32 FCR;           /**< Stream FIFO configuration register */
+    __io uint32 FCR;          /**< Stream FIFO configuration register */
 } dma_stream_t;
 /**
  * @brief DMA register map type.
  *
  */
 typedef struct dma_reg_map {
-    __io uint32 LISR;           /**< Low interrupt status register */
-    __io uint32 HISR;           /**< High interrupt status register */
-    __io uint32 LIFCR;          /**< Low interrupt flag clear register */
-    __io uint32 HIFCR;          /**< High interrupt flag clear register */
-    dma_stream_t  STREAM[8];
+    __io uint32  LISR;         /**< Low interrupt status register */
+    __io uint32  HISR;         /**< High interrupt status register */
+    __io uint32  LIFCR;        /**< Low interrupt flag clear register */
+    __io uint32  HIFCR;        /**< High interrupt flag clear register */
+    dma_stream_t STREAM[8];
 } dma_reg_map;
 
 /** DMA controller register map base pointers */
 #define DMA1_BASE                       ((struct dma_reg_map*)0x40026000)
 #define DMA2_BASE                       ((struct dma_reg_map*)0x40026400)
 
+
 /*
  * Register bit definitions
  */
 
-/* Stream configuration register */
-
+// Stream configuration register
 #define DMA_CR_CH0                      (0x0 << 25)
 #define DMA_CR_CH1                      (0x1 << 25)
 #define DMA_CR_CH2                      (0x2 << 25)
@@ -134,7 +134,34 @@ typedef struct dma_reg_map {
 #define DMA_CR_HTIE                     (0x1 << 3)
 #define DMA_CR_TEIE                     (0x1 << 2)
 #define DMA_CR_DMEIE                    (0x1 << 1)
-#define DMA_CR_EN                       (0x1)
+#define DMA_CR_EN                       (0x1 << 0)
+
+// Device interrupt status register flags
+#define DMA_ISR_TCIF    (1 << 5)
+#define DMA_ISR_HTIF    (1 << 4)
+#define DMA_ISR_TEIF    (1 << 3)
+#define DMA_ISR_DMEIF   (1 << 2)
+#define DMA_ISR_FEIF    (1 << 0)
+
+#define DMA_ISR_ERROR_BITS (DMA_ISR_TEIF | DMA_ISR_DMEIF | DMA_ISR_FEIF)
+#define DMA_ISR_BIT_MASK 0x3D
+
+// FIFO control register flags
+#define DMA_FCR_FEIE                   (0x1 << 7) // FIFO error interrupt enable
+#define DMA_FCR_FS                     (0x7 << 3) // FIFO status (READ_ONLY):
+#define DMA_FCR_FS_LEVEL_1             (0x0 << 3) //  000: 0 < fifo_level < 1/4
+#define DMA_FCR_FS_LEVEL_2             (0x1 << 3) //  001: 1/4 ≤ fifo_level < 1/2
+#define DMA_FCR_FS_LEVEL_3             (0x2 << 3) //  010: 1/2 ≤ fifo_level < 3/4
+#define DMA_FCR_FS_LEVEL_4             (0x3 << 3) //  011: 3/4 ≤ fifo_level < full
+#define DMA_FCR_FS_EMPTY               (0x4 << 3) //  100: FIFO is empty
+#define DMA_FCR_FS_FULL                (0x5 << 3) //  101: FIFO is full
+#define DMA_FCR_DMDIS                  (0x1 << 2) // Direct mode disable
+#define DMA_FCR_FTH                    (0x3 << 0) // FIFO threshold selection
+#define DMA_FCR_FTH_1_4                (0x0 << 0) //  1/4 full FIFO
+#define DMA_FCR_FTH_2_4                (0x1 << 0) //  2/4 full FIFO
+#define DMA_FCR_FTH_3_4                (0x2 << 0) //  3/4 full FIFO
+#define DMA_FCR_FTH_FULL               (0x3 << 0) //  full FIFO
+
 
 typedef enum dma_channel {
     DMA_CH0 = DMA_CR_CH0,                /**< Channel 0 */
@@ -147,18 +174,6 @@ typedef enum dma_channel {
     DMA_CH7 = DMA_CR_CH7,                /**< Channel 7 */
 } dma_channel;
 
-/* Device interrupt status register flags */
-
-#define DMA_ISR_TCIF    (1 << 5)
-#define DMA_ISR_HTIF    (1 << 4)
-#define DMA_ISR_TEIF    (1 << 3)
-#define DMA_ISR_DMEIF   (1 << 2)
-#define DMA_ISR_FEIF    (1 << 0)
-
-/*
- * Devices
- */
-
 /** Encapsulates state related to a DMA channel interrupt. */
 typedef struct dma_handler_config {
     void (*handler)(void);      /**< User-specified channel interrupt
@@ -172,50 +187,53 @@ typedef struct dma_dev {
     rcc_clk_id clk_id;             /**< Clock ID */
     dma_handler_config handlers[]; /**<
                                     * @brief IRQ handlers and NVIC numbers.
-                                    *
-                                    * @see dma_attach_interrupt()
                                     * @see dma_detach_interrupt()
                                     */
 } dma_dev;
 
-extern dma_dev *DMA1;
-extern dma_dev *DMA2;
-
 /*
- * Convenience functions
+ * Devices
  */
-
-extern void dma_init(dma_dev *dev);
+extern dma_dev *DMA1;
+extern dma_dev *DMA2;
 
 /** Flags for DMA transfer configuration. */
 typedef enum dma_mode_flags {
-    DMA_MEM_BUF_0 = DMA_CR_CT0, /**< Current memory target buffer 0 */
-    DMA_MEM_BUF_1 = DMA_CR_CT1, /**< Current memory target buffer 1 */
-    DMA_DBL_BUF_MODE = DMA_CR_DBM,  /**< Current memory double buffer mode */
-    DMA_PINC_OFFSET  = DMA_CR_PINCOS,  /**< Peripheral increment offset size */
-    DMA_MINC_MODE  = DMA_CR_MINC,  /**< Memory increment mode */
-    DMA_PINC_MODE  = DMA_CR_PINC,  /**< Peripheral increment mode */
-    DMA_CIRC_MODE  = DMA_CR_CIRC,  /**< Memory Circular mode */
-    DMA_FROM_PER   = DMA_CR_DIR_P2M,  /**< Read from memory to peripheral */
-    DMA_FROM_MEM   = DMA_CR_DIR_M2P,  /**< Read from memory to peripheral */
-    DMA_MEM_TO_MEM = DMA_CR_DIR_M2M,  /**< Read from memory to memory */
-    DMA_PERIF_CTRL   = DMA_CR_PFCTRL,  /**< Peripheral flow controller */
+    DMA_MEM_BUF_0      = DMA_CR_CT0, /**< Current memory target buffer 0 */
+    DMA_MEM_BUF_1      = DMA_CR_CT1, /**< Current memory target buffer 1 */
+    DMA_DBL_BUF_MODE   = DMA_CR_DBM,  /**< Current memory double buffer mode */
+    DMA_PINC_OFFSET    = DMA_CR_PINCOS,  /**< Peripheral increment offset size */
+    DMA_MINC_MODE      = DMA_CR_MINC,  /**< Memory increment mode */
+    DMA_PINC_MODE      = DMA_CR_PINC,  /**< Peripheral increment mode */
+    DMA_CIRC_MODE      = DMA_CR_CIRC,  /**< Memory Circular mode */
+    DMA_FROM_PER       = DMA_CR_DIR_P2M,  /**< Read from memory to peripheral */
+    DMA_FROM_MEM       = DMA_CR_DIR_M2P,  /**< Read from memory to peripheral */
+    DMA_MEM_TO_MEM     = DMA_CR_DIR_M2M,  /**< Read from memory to memory */
+    DMA_PERIF_CTRL     = DMA_CR_PFCTRL,  /**< Peripheral flow controller */
     DMA_PRIO_MEDIUM    = DMA_CR_PL_MEDIUM,    /**< Medium priority */
     DMA_PRIO_HIGH      = DMA_CR_PL_HIGH,      /**< High priority */
     DMA_PRIO_VERY_HIGH = DMA_CR_PL_VERY_HIGH, /**< Very high priority */
-    DMA_TRNS_CMPLT   = DMA_CR_TCIE,   /**< Interrupt on transfer completion */
-    DMA_TRNS_HALF    = DMA_CR_HTIE,  /**< Interrupt on half-transfer */
+    DMA_TRNS_CMPLT     = DMA_CR_TCIE,   /**< Interrupt on transfer completion */
+    DMA_TRNS_HALF      = DMA_CR_HTIE,  /**< Interrupt on half-transfer */
     DMA_TRNS_ERR       = DMA_CR_TEIE,  /**< Interrupt on transfer error */
     DMA_DIR_MODE_ERR   = DMA_CR_DMEIE  /**< Interrupt on direct mode error */
 } dma_mode_flags;
 
-/** Source and destination transfer sizes. */
+// Source and destination transfer sizes.
 typedef enum dma_xfer_size {
-    DMA_SIZE_8BITS  = ( DMA_CR_MSIZE_8BITS|DMA_CR_PSIZE_8BITS ),        /**< 8-bit transfers */
-    DMA_SIZE_16BITS = (DMA_CR_MSIZE_16BITS|DMA_CR_PSIZE_16BITS),        /**< 16-bit transfers */
-    DMA_SIZE_32BITS = (DMA_CR_MSIZE_32BITS|DMA_CR_PSIZE_32BITS)         /**< 32-bit transfers */
+    DMA_SIZE_8BITS  = ( DMA_CR_MSIZE_8BITS|DMA_CR_PSIZE_8BITS ),  // 8-bit transfers
+    DMA_SIZE_16BITS = (DMA_CR_MSIZE_16BITS|DMA_CR_PSIZE_16BITS),  // 16-bit transfers
+    DMA_SIZE_32BITS = (DMA_CR_MSIZE_32BITS|DMA_CR_PSIZE_32BITS)   // 32-bit transfers
 } dma_xfer_size;
 
+// Source and destination burst sizes.
+typedef enum dma_burst_size {
+    DMA_BURST_INCR0  = ( DMA_CR_MBURST0|DMA_CR_PBURST0 ),  // single transfer
+    DMA_BURST_INCR4  = ( DMA_CR_MBURST4|DMA_CR_PBURST4 ),  // incremental burst of 4 beats
+    DMA_BURST_INCR8  = ( DMA_CR_MBURST8|DMA_CR_PBURST8 ),  // incremental burst of 8 beats
+    DMA_BURST_INCR16 = (DMA_CR_MBURST16|DMA_CR_PBURST16)   // incremental burst of 16 beats
+} dma_burst_size;
+
 /** DMA channel */
 typedef enum dma_stream {
     DMA_STREAM0 = 0,                /**< Stream 0 */
@@ -227,7 +245,12 @@ typedef enum dma_stream {
     DMA_STREAM6 = 6,                /**< Stream 6 */
     DMA_STREAM7 = 7,                /**< Stream 7 */
 } dma_stream;
-    
+
+/*
+ * Convenience functions
+ */
+extern void dma_init(dma_dev *dev);
+
 static inline void dma_setup_transfer(dma_dev       *dev,
                                       dma_stream    stream,
                                       dma_channel   channel,
@@ -235,24 +258,24 @@ static inline void dma_setup_transfer(dma_dev       *dev,
                                       __io void     *peripheral_address,
                                       __io void     *memory_address0,
                                       __io void     *memory_address1,
-                                      uint32        flags) {
+                                      uint32        flags)
+{
     dev->regs->STREAM[stream].CR &= ~DMA_CR_EN; // disable
+	while( (dev->regs->STREAM[stream].CR)&DMA_CR_EN ); // wait till enable bit is cleared
     dev->regs->STREAM[stream].PAR = (uint32)peripheral_address;
     dev->regs->STREAM[stream].M0AR = (uint32)memory_address0;
     dev->regs->STREAM[stream].M1AR = (uint32)memory_address1;
-    dev->regs->STREAM[stream].CR = ((flags|channel|trx_size) & 0x0feffffe); // mask out reserved and enable
+    dev->regs->STREAM[stream].CR = (uint32)((flags|channel|trx_size) & 0x0feffffe); // mask out reserved and enable
 }
     
-static inline void dma_set_num_transfers(dma_dev *dev,
-                                         dma_stream stream,
-                                         uint16 num_transfers) {
-    dev->regs->STREAM[stream].NDTR = num_transfers;
+static inline void dma_set_num_transfers(dma_dev *dev, dma_stream stream, uint16 num_transfers)
+{
+    dev->regs->STREAM[stream].NDTR = (uint32)num_transfers;
 }
 
-static inline void dma_set_fifo_flags(dma_dev *dev,
-                                      dma_stream stream,
-                                      uint8 fifo_flags) {
-    dev->regs->STREAM[stream].FCR = fifo_flags & 0x87; // mask out reserved bits
+static inline void dma_set_fifo_flags(dma_dev *dev, dma_stream stream, uint8 fifo_flags)
+{
+    dev->regs->STREAM[stream].FCR = (uint32)(fifo_flags & 0x87); // mask out reserved bits
 }
 
 void dma_attach_interrupt(dma_dev *dev,
@@ -261,12 +284,14 @@ void dma_attach_interrupt(dma_dev *dev,
 
 void dma_detach_interrupt(dma_dev *dev, dma_stream stream);
 
-static inline void dma_enable(dma_dev *dev, dma_stream stream) {
-    dev->regs->STREAM[stream].CR |= DMA_CR_EN;
+static inline void dma_enable(dma_dev *dev, dma_stream stream)
+{
+    dev->regs->STREAM[stream].CR |= (uint32)DMA_CR_EN;
 }    
 
-static inline void dma_disable(dma_dev *dev, dma_stream stream) {
-    dev->regs->STREAM[stream].CR &= ~DMA_CR_EN;
+static inline void dma_disable(dma_dev *dev, dma_stream stream)
+{
+    dev->regs->STREAM[stream].CR &= (uint32)(~DMA_CR_EN);
 	while (dev->regs->STREAM[stream].CR & DMA_CR_EN); // wait till EN bit is reset, see AN4031, chapter 4.1
 }    
 
@@ -289,7 +314,11 @@ static inline uint8 dma_is_stream_enabled(dma_dev *dev, dma_stream stream) {
  * @param dev DMA device
  * @param stream Stream whose ISR bits to return.
  */
-uint8 dma_get_isr_bits(dma_dev *dev, dma_stream stream);
+uint8 dma_get_isr_bit(dma_dev *dev, dma_stream stream, uint8_t mask);
+
+static inline uint8 dma_get_isr_bits(dma_dev *dev, dma_stream stream) {
+	return dma_get_isr_bit(dev, stream, DMA_ISR_BIT_MASK);
+}
 
 /**
  * @brief Clear the ISR status bits for a given DMA stream.
@@ -297,7 +326,11 @@ uint8 dma_get_isr_bits(dma_dev *dev, dma_stream stream);
  * @param dev DMA device
  * @param stream Stream whose ISR bits to clear.
  */
-void dma_clear_isr_bits(dma_dev *dev, dma_stream stream);
+void dma_clear_isr_bit(dma_dev *dev, dma_stream stream, uint8_t mask);
+
+static inline void dma_clear_isr_bits(dma_dev *dev, dma_stream stream) {
+	dma_clear_isr_bit(dev, stream, DMA_ISR_BIT_MASK);
+}
 
 #ifdef __cplusplus
 } // extern "C"
diff --git a/STM32F4/cores/maple/libmaple/sdio.c b/STM32F4/cores/maple/libmaple/sdio.c
new file mode 100644
index 000000000..1a9113a7c
--- /dev/null
+++ b/STM32F4/cores/maple/libmaple/sdio.c
@@ -0,0 +1,194 @@
+/******************************************************************************
+  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/sdio.c
+ * @author stevstrong
+ * @brief Secure digital input/output interface.
+ */
+
+#include "sdio.h"
+#include "gpio.h"
+#include "wirish_time.h"
+
+#if defined(BOARD_generic_f407v)
+
+sdio_dev * SDIO = SDIO_BASE;
+
+#define DELAY_LONG 10
+#define DELAY_SHORT 1
+
+uint8_t dly = DELAY_LONG; // microseconds delay after accessing registers
+
+/*
+ * SDIO convenience routines
+ */
+static void sdio_gpios_init(void)
+{
+	gpio_set_mode(BOARD_SDIO_D0, GPIO_AF_OUTPUT_PP_PU);
+	gpio_set_mode(BOARD_SDIO_D1, GPIO_AF_OUTPUT_PP_PU);
+	gpio_set_mode(BOARD_SDIO_D2, GPIO_AF_OUTPUT_PP_PU);
+	gpio_set_mode(BOARD_SDIO_D3, GPIO_AF_OUTPUT_PP_PU);
+	gpio_set_mode(BOARD_SDIO_CLK, GPIO_AF_OUTPUT_PP);
+	gpio_set_mode(BOARD_SDIO_CMD, GPIO_AF_OUTPUT_PP_PU);
+	//
+	gpio_set_af_mode(BOARD_SDIO_D0, 12);
+	gpio_set_af_mode(BOARD_SDIO_D1, 12);
+	gpio_set_af_mode(BOARD_SDIO_D2, 12);
+	gpio_set_af_mode(BOARD_SDIO_D3, 12);
+	gpio_set_af_mode(BOARD_SDIO_CLK, 12);
+	gpio_set_af_mode(BOARD_SDIO_CMD, 12);
+}
+
+static void sdio_gpios_deinit(void)
+{
+	gpio_set_mode(BOARD_SDIO_D0, GPIO_INPUT_FLOATING);
+	gpio_set_mode(BOARD_SDIO_D1, GPIO_INPUT_FLOATING);
+	gpio_set_mode(BOARD_SDIO_D2, GPIO_INPUT_FLOATING);
+	gpio_set_mode(BOARD_SDIO_D3, GPIO_INPUT_FLOATING);
+	gpio_set_mode(BOARD_SDIO_CLK, GPIO_INPUT_FLOATING);
+	gpio_set_mode(BOARD_SDIO_CMD, GPIO_INPUT_FLOATING);
+	//
+	gpio_set_af_mode(BOARD_SDIO_D0, 0);
+	gpio_set_af_mode(BOARD_SDIO_D1, 0);
+	gpio_set_af_mode(BOARD_SDIO_D2, 0);
+	gpio_set_af_mode(BOARD_SDIO_D3, 0);
+	gpio_set_af_mode(BOARD_SDIO_CLK, 0);
+	gpio_set_af_mode(BOARD_SDIO_CMD, 0);
+}
+
+/**
+ * @brief Initialize and reset the SDIO device.
+ */
+void sdio_init(void)
+{
+    rcc_clk_enable(RCC_SDIO);
+    rcc_reset_dev(RCC_SDIO);
+}
+
+void sdio_power_on(void)
+{
+    SDIO->POWER = SDIO_POWER_PWRCTRL_ON;
+// After a data write, data cannot be written to this register for three SDIOCLK clock periods
+// plus two PCLK2 clock periods.
+	delayMicroseconds(DELAY_LONG);
+}
+
+void sdio_power_off(void)
+{
+    SDIO->POWER = SDIO_POWER_PWRCTRL_OFF;
+// After a data write, data cannot be written to this register for three SDIOCLK clock periods
+// plus two PCLK2 clock periods.
+	delayMicroseconds(DELAY_LONG);
+}
+
+/**
+ * @brief Enable the SDIO peripheral
+
+void sdio_peripheral_enable(void) {
+    bb_peri_set_bit(SDIO->CR1, SPI_CR1_SPE_BIT, 1);
+}
+ */
+/**
+ * @brief Disable a SPI peripheral
+
+void sdio_peripheral_disable(spi_dev *dev) {
+    bb_peri_set_bit(&dev->regs->CR1, SPI_CR1_SPE_BIT, 0);
+}
+ */
+void sdio_set_clock(uint32_t clk)
+{
+	if (clk>24000000UL) clk = 24000000UL; // limit the SDIO master clock to 24MHz
+
+	if (clk<1000000) dly = DELAY_LONG;
+	else dly = DELAY_SHORT;
+
+	sdio_disable();
+	SDIO->CLKCR = (SDIO->CLKCR & (~(SDIO_CLKCR_CLKDIV|SDIO_CLKCR_BYPASS))) | SDIO_CLKCR_CLKEN | (((SDIOCLK/clk)-2)&SDIO_CLKCR_CLKDIV);
+	delayMicroseconds(dly);
+}
+
+void sdio_set_dbus_width(uint16_t bus_w)
+{
+	SDIO->CLKCR = (SDIO->CLKCR & (~SDIO_CLKCR_WIDBUS)) | bus_w;
+	delayMicroseconds(dly);
+}
+
+void sdio_set_dblock_size(uint8_t dbsize)
+{
+	SDIO->DCTRL = (SDIO->DCTRL&(~SDIO_DCTRL_DBLOCKSIZE)) | ((dbsize&0xF)<<4);
+	delayMicroseconds(dly);
+}
+
+void sdio_enable(void)
+{
+	SDIO->CLKCR |= SDIO_CLKCR_CLKEN;
+	delayMicroseconds(dly);
+}
+
+void sdio_disable(void)
+{
+	SDIO->CLKCR ^= SDIO_CLKCR_CLKEN;
+	delayMicroseconds(dly);
+}
+
+/**
+ * @brief Configure and enable the SDIO device.
+ */
+void sdio_begin(void)
+{
+	sdio_gpios_init();
+	sdio_init();
+	sdio_power_on();
+	// Set initial SCK rate.
+	sdio_set_clock(400000);
+	delayMicroseconds(200); // generate 80 pulses at 400kHz
+}
+
+/**
+ * @brief Disables the SDIO device.
+ */
+void sdio_end(void)
+{
+	sdio_disable();
+	while ( sdio_cmd_xfer_ongoing() );
+	sdio_power_off();
+    rcc_clk_disable(RCC_SDIO);
+	sdio_gpios_deinit();
+}
+
+/**
+ * @brief Send command by the SDIO device.
+ */
+uint8_t sdio_cmd_send(uint16_t cmd_index_resp_type, uint32_t arg)
+{
+	uint8_t retries = 10; // in case of errors
+	do { // retry command if errors detected
+		// clear interrupt flags - IMPORTANT!!!
+		SDIO->ICR = SDIO_ICR_CMD_FLAGS;
+		// write command
+		SDIO->ARG = arg;
+		SDIO->CMD = (uint32_t)(SDIO_CMD_CPSMEN | cmd_index_resp_type );
+		while ( (SDIO->STA&SDIO_STA_CMDACT) ) ; // wait for actual command transfer to finish
+		// wait for response, if the case
+		if ( cmd_index_resp_type&(SDIO_CMD_WAIT_SHORT_RESP|SDIO_CMD_WAIT_LONG_RESP) ) {
+			while ( !(SDIO->STA&(SDIO_STA_CMDREND|SDIO_STA_CMD_ERROR_FLAGS)) ) ;
+		} else break; // no response required
+		if ( SDIO->STA&(SDIO_STA_CMDREND|SDIO_STA_CTIMEOUT) )
+			break; // response received or timeout
+		// ignore CRC error for CMD5 and ACMD41
+		if ( ((cmd_index_resp_type&SDIO_CMD_CMDINDEX)==5) || ((cmd_index_resp_type&SDIO_CMD_CMDINDEX)==41) )
+			break;
+	} while ( (--retries) );
+	return (uint8_t)retries;
+}
+
+#endif // BOARD_generic_f407v
diff --git a/STM32F4/cores/maple/libmaple/sdio.h b/STM32F4/cores/maple/libmaple/sdio.h
new file mode 100644
index 000000000..f0afaa163
--- /dev/null
+++ b/STM32F4/cores/maple/libmaple/sdio.h
@@ -0,0 +1,250 @@
+/******************************************************************************
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file sdio.h
+ * @brief Secure digital input/output interface.
+ */
+
+#ifndef _SDIO_H_
+#define _SDIO_H_
+
+
+#include "libmaple_types.h"
+
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#ifdef STM32_HIGH_DENSITY
+
+/*
+ * Register maps and devices
+ */
+
+// SDIO register map type
+typedef struct sdio_reg_map {
+    __io uint32 POWER;    // 0x00
+    __io uint32 CLKCR;    // 0x04
+    __io uint32 ARG;      // 0x08
+    __io uint32 CMD;      // 0x0C
+    __io uint32 RESPCMD;  // 0x10 (0x3F)
+    const uint32 RESP[4]; // 0x14 - contain the card status, which is part of the received response.
+    __io uint32 DTIMER;   // 0x24 - contains the data timeout period, in card bus clock periods.
+    __io uint32 DLEN;     // 0x28 (0x01FF FFFF) - contains the number of data bytes to be transferred
+    __io uint32 DCTRL;    // 0x2C
+    __io uint32 DCOUNT;   // 0x30 (0x01FF FFFF)
+    __io uint32 STA;      // 0x34
+    __io uint32 ICR;      // 0x38
+    __io uint32 MASK;     // 0x3C
+    const uint32 RESERVED1[2];
+    __io uint32 FIFOCNT;  // 0x48 (0x01FF FFFF)
+    const uint32 RESERVED2[13];
+    __io uint32 FIFO;     // 0x80
+} sdio_reg_map;
+#define sdio_dev sdio_reg_map
+
+/** SDIO register map base pointer */
+#define SDIO_BASE                       ((struct sdio_reg_map*)0x40012C00)
+
+extern sdio_dev * SDIO;
+
+/*
+ * Register bit definitions
+ */
+
+/* NOR/PSRAM chip-select control registers */
+
+// SDIO_POWER register bits
+// At least seven HCLK clock periods are needed between two write accesses to this register.
+// After a data write, data cannot be written to this register for three SDIOCLK clock periods
+// plus two PCLK2 clock periods.
+#define SDIO_POWER_PWRCTRL_OFF         0x00
+#define SDIO_POWER_PWRCTRL_ON          0x03
+
+// SDIO_CLKCR register bits
+// Controls the SDIO_CK output clock.
+// After a data write, data cannot be written to this register for three SDIOCLK clock periods
+// plus two PCLK2 clock periods. SDIO_CK can also be stopped during the read wait interval
+// for SD I/O cards: in this case the SDIO_CLKCR register does not control SDIO_CK.
+#define SDIO_CLKCR_HWFC_EN          (1<<14) // HW Flow Control enable - DON'T USE!!! (see errata sheet 2.12.1)
+                                            // Overrun errors (Rx mode) and FIFO underrun (Tx mode)
+											// should be managed by the application software.
+#define SDIO_CLKCR_NEGEDGE          (1<<13) // SDIO_CK de-phasing selection bit - DON'T USE!!! (see errata sheet 2.12.4)
+#define SDIO_CLKCR_WIDBUS           (3<<11) // Data bus width
+#define SDIO_CLKCR_WIDBUS_1BIT      (0<<11) // 1 bit (SDIO_D0 used)
+#define SDIO_CLKCR_WIDBUS_4BIT      (1<<11) // 4-bit (SDIO_D[3:0] used)
+#define SDIO_CLKCR_BYPASS           (1<<10) // Clock divider bypass enable bit - SDIO_CK = SDIOCLK, CLKDIV not relevant.
+#define SDIO_CLKCR_PWRSAV           (1<<9)  // 0: SDIO_CK clock is always enabled, 1: SDIO_CK is only enabled when the bus is active
+#define SDIO_CLKCR_CLKEN            (1<<8)  // Clock enable
+#define SDIO_CLKCR_CLKDIV           (0xFF)  // SDIO_CK = SDIOCLK / [CLKDIV + 2]
+#define SDIOCLK 48000000UL // SDIO master clock frequency
+
+// SDIO_CMD register bits
+// After a data write, data cannot be written to this register for three SDIOCLK clock periods
+// plus two PCLK2 clock periods.
+// MultiMediaCards can send two kinds of response: short responses, 48 bits long, or long
+// responses,136 bits long. SD card and SD I/O card can send only short responses, the
+// argument can vary according to the type of response: the software will distinguish the type
+// of response according to the sent command. CE-ATA devices send only short responses.
+#define SDIO_CMD_ATACMD          (1<<14)
+#define SDIO_CMD_NIEN            (1<<13)
+#define SDIO_CMD_ENCMDCOMPL      (1<<12)
+#define SDIO_CMD_SDIOSUSPEND     (1<<11)
+#define SDIO_CMD_CPSMEN          (1<<10)
+#define SDIO_CMD_WAITPEND        (1<<9)
+#define SDIO_CMD_WAITINT         (1<<8)
+#define SDIO_CMD_WAITRESP        (3<<6)
+#define SDIO_CMD_WAIT_NO_RESP    (0<<6)
+#define SDIO_CMD_WAIT_SHORT_RESP (1<<6)
+#define SDIO_CMD_WAIT_LONG_RESP  (3<<6)
+#define SDIO_CMD_CMDINDEX        (0x3F)
+
+// SDIO_DLEN register bits
+// For a block data transfer, the value in the data length register must be a multiple of the block
+// size (see SDIO_DCTRL). A data transfer must be written to the data timer register and the
+// data length register before being written to the data control register.
+// For an SDIO multibyte transfer the value in the data length register must be between 1 and 512.
+#define SDIO_DLEN_DATALENGTH     (0x01FFFFFF)
+
+// SDIO_DCTRL register bits
+// Controls the data path state machine (DPSM).
+// After a data write, data cannot be written to this register for three SDIOCLK clock periods
+// plus two PCLK2 clock periods.
+#define SDIO_DCTRL_SDIOEN        (1<<11)  // the DPSM performs an SD I/O-card-specific operation.
+#define SDIO_DCTRL_RWMODE        (1<<10)  // 0: Read Wait control stopping SDIO_D2, 1:Read Wait control using SDIO_CK
+#define SDIO_DCTRL_RWSTOP        (1<<9)   // 0: Read wait in progress if RWSTART bit is set, 1: Enable for read wait stop if RWSTART bit is set
+#define SDIO_DCTRL_RWSTART       (1<<8)   // read wait operation starts
+#define SDIO_DCTRL_DBLOCKSIZE    (0xF<<4) // Define the data block length when the block data transfer mode is selected: 2^N bytes
+#define SDIO_BLOCKSIZE_64        (6<<4)
+#define SDIO_BLOCKSIZE_512       (9<<4)
+#define SDIO_DCTRL_DMAEN         (1<<3)   // DMA enable
+#define SDIO_DCTRL_DTMODE        (1<<2)   // Data transfer mode selection: 0: Block data transfer, 1: Stream or SDIO multi-byte data transfer
+#define SDIO_DCTRL_DTDIR         (1<<1)   // Data transfer direction selection: 0: From controller to card, 1: From card to controller.
+#define SDIO_DIR_TX              (0<<1)
+#define SDIO_DIR_RX              (1<<1)
+#define SDIO_DCTRL_DTEN          (1<<0)   // Start data transfer. Depending on the direction bit, DTDIR,
+                                          // the DPSM moves to the Wait_S, Wait_R state or Readwait if RW Start is set immediately at
+										  // the beginning of the transfer. It is not necessary to clear the enable bit after the end of a data
+										  // transfer but the SDIO_DCTRL must be updated to enable a new data transfer
+// The meaning of the DTMODE bit changes according to the value of the SDIOEN bit:
+// When DTEN=0 and DTMODE=1, the MultiMediaCard stream mode is enabled.
+// When DTEN=1 and DTMODE=1, the peripheral enables an SDIO multi-byte transfer.
+
+// SDIO_STA register bits
+#define SDIO_STA_CEATAEND        (1<<23) // CE-ATA command completion signal received for CMD61
+#define SDIO_STA_SDIOIT          (1<<22) // SDIO interrupt received
+#define SDIO_STA_RXDAVL          (1<<21) // Data available in receive FIFO
+#define SDIO_STA_TXDAVL          (1<<20) // Data available in transmit FIFO
+#define SDIO_STA_RXFIFOE         (1<<19) // Receive FIFO empty
+#define SDIO_STA_TXFIFOE         (1<<18) // Transmit FIFO empty (2 words)
+#define SDIO_STA_RXFIFOF         (1<<17) // Receive FIFO full (2 words before the FIFO is full.)
+#define SDIO_STA_TXFIFOF         (1<<16) // Transmit FIFO full
+#define SDIO_STA_RXFIFOHF        (1<<15) // Receive FIFO half full: there are at least 8 words in the FIFO
+#define SDIO_STA_TXFIFOHE        (1<<14) // Transmit FIFO half empty: at least 8 words can be written into the FIFO
+#define SDIO_STA_RXACT           (1<<13) // Data receive in progress
+#define SDIO_STA_TXACT           (1<<12) // Data transmit in progress
+#define SDIO_STA_CMDACT          (1<<11) // Command transfer in progress
+#define SDIO_STA_DBCKEND         (1<<10) // Data block sent/received (CRC check passed)
+#define SDIO_STA_STBITERR        (1<<9)  // Start bit not detected on all data signals in wide bus mode
+#define SDIO_STA_DATAEND         (1<<8)  // Data end (data counter SDIOCOUNT is zero)
+#define SDIO_STA_CMDSENT         (1<<7)  // Command sent (no response required)
+#define SDIO_STA_CMDREND         (1<<6)  // Command response received (CRC check passed)
+#define SDIO_STA_RXOVERR         (1<<5)  // Received FIFO overrun error
+#define SDIO_STA_TXUNDERR        (1<<4)  // Transmit FIFO underrun error
+#define SDIO_STA_DTIMEOUT        (1<<3)  // Data timeout
+#define SDIO_STA_CTIMEOUT        (1<<2)  // Command response timeout. The Command TimeOut period has a fixed value of 64 SDIO_CK clock periods.
+#define SDIO_STA_DCRCFAIL        (1<<1)  // Data block sent/received (CRC check failed)
+#define SDIO_STA_CCRCFAIL        (1<<0)  // Command response received (CRC check failed)
+
+#define SDIO_STA_CMD_ERROR_FLAGS (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL)
+#define SDIO_STA_TRX_ERROR_FLAGS (SDIO_STA_STBITERR | SDIO_STA_RXOVERR | SDIO_STA_TXUNDERR | SDIO_STA_DTIMEOUT | SDIO_STA_DCRCFAIL)
+#define SDIO_STA_TRX_ACT_FLAGS   (SDIO_STA_RXACT|SDIO_STA_TXACT)
+
+// SDIO_ICR register bits (WO - write only)
+#define SDIO_ICR_CEATAENDC       (1<<23) // clear CEATAEND  flag
+#define SDIO_ICR_SDIOITC         (1<<22) // clear SDIOIT    flag
+#define SDIO_ICR_DBCKENDC        (1<<10) // clear DBCKENDC  flag
+#define SDIO_ICR_STBITERRC       (1<<9)  // clear STBITERRC flag
+#define SDIO_ICR_DATAENDC        (1<<8)  // clear DATAENDC  flag
+#define SDIO_ICR_CMDSENTC        (1<<7)  // clear CMDSENTC  flag
+#define SDIO_ICR_CMDRENDC        (1<<6)  // clear CMDREND   flag
+#define SDIO_ICR_RXOVERRC        (1<<5)  // clear RXOVERR   flag
+#define SDIO_ICR_TXUNDERRC       (1<<4)  // clear TXUNDERR  flag
+#define SDIO_ICR_DTIMEOUTC       (1<<3)  // clear DTIMEOUT  flag
+#define SDIO_ICR_CTIMEOUTC       (1<<2)  // clear CTIMEOUT  flag
+#define SDIO_ICR_DCRCFAILC       (1<<1)  // clear DCRCFAIL  flag
+#define SDIO_ICR_CCRCFAILC       (1<<0)  // clear CCRCFAIL  flag
+
+#define SDIO_ICR_CMD_FLAGS   (SDIO_ICR_CEATAENDC | SDIO_ICR_SDIOITC | SDIO_ICR_CMDSENTC | SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC)
+#define SDIO_ICR_DATA_FLAGS  (SDIO_ICR_DBCKENDC | SDIO_ICR_STBITERRC | SDIO_ICR_DATAENDC | SDIO_ICR_RXOVERRC | SDIO_ICR_TXUNDERRC | SDIO_ICR_DTIMEOUTC | SDIO_ICR_DCRCFAILC)
+
+// SDIO_MASK register bits
+// Determines which status flags generate an interrupt request by setting the corresponding bit to 1b.
+#define SDIO_MASK_CEATAENDIE        (1<<23) // enable CEATAEND interrupt 
+#define SDIO_MASK_SDIOITIE          (1<<22) // enable SDIOIT   interrupt
+#define SDIO_MASK_RXDAVLIE          (1<<21) // enable RXDAVL   interrupt
+#define SDIO_MASK_TXDAVLIE          (1<<20) // enable TXDAVL   interrupt
+#define SDIO_MASK_RXFIFOEIE         (1<<19) // enable RXFIFOE  interrupt
+#define SDIO_MASK_TXFIFOEIE         (1<<18) // enable TXFIFOE  interrupt
+#define SDIO_MASK_RXFIFOFIE         (1<<17) // enable RXFIFOF  interrupt
+#define SDIO_MASK_TXFIFOFIE         (1<<16) // enable TXFIFOF  interrupt
+#define SDIO_MASK_RXFIFOHFIE        (1<<15) // enable RXFIFOHF interrupt
+#define SDIO_MASK_TXFIFOHEIE        (1<<14) // enable TXFIFOHE interrupt
+#define SDIO_MASK_RXACTIE           (1<<13) // enable RXACT    interrupt
+#define SDIO_MASK_TXACTIE           (1<<12) // enable TXACT    interrupt
+#define SDIO_MASK_CMDACTIE          (1<<11) // enable CMDACT   interrupt
+#define SDIO_MASK_DBCKENDIE         (1<<10) // enable DBCKENDC interrupt
+#define SDIO_MASK_STBITERRIE        (1<<9)  // enable STBITERR interrupt
+#define SDIO_MASK_DATAENDIE         (1<<8)  // enable DATAENDC interrupt
+#define SDIO_MASK_CMDSENTIE         (1<<7)  // enable CMDSENTC interrupt
+#define SDIO_MASK_CMDRENDIE         (1<<6)  // enable CMDREND  interrupt
+#define SDIO_MASK_RXOVERRIE         (1<<5)  // enable RXOVERR  interrupt
+#define SDIO_MASK_TXUNDERRIE        (1<<4)  // enable TXUNDERR interrupt
+#define SDIO_MASK_DTIMEOUTIE        (1<<3)  // enable DTIMEOUT interrupt
+#define SDIO_MASK_CTIMEOUTIE        (1<<2)  // enable CTIMEOUT interrupt
+#define SDIO_MASK_DCRCFAILIE        (1<<1)  // enable DCRCFAIL interrupt
+#define SDIO_MASK_CCRCFAILIE        (1<<0)  // enable CCRCFAIL interrupt
+
+
+void sdio_enable(void);
+void sdio_disable(void);
+void sdio_begin(void);
+uint8_t sdio_cmd_send(uint16_t cmd_index_resp_type, uint32_t arg);
+void sdio_set_clock(uint32_t clk);
+void sdio_set_dbus_width(uint16_t bus_w);
+void sdio_set_dblock_size(uint8_t dbsize);
+//void sdio_trx_enable(uint8_t dir);
+inline void sdio_trx_enable(void)
+{
+	SDIO->DCTRL |= SDIO_DCTRL_DTEN; // enable data transfer
+}
+
+inline uint32_t sdio_cmd_xfer_ongoing(void) { return (SDIO->STA&SDIO_STA_CMDACT); }
+inline uint32_t sdio_cmd_complete(void) { return (SDIO->STA&SDIO_STA_CMDSENT); }
+
+inline void sdio_setup_transfer(uint32_t dtimer, uint32_t dlen, uint16_t flags)
+{
+	SDIO->ICR = SDIO_ICR_DATA_FLAGS; // clear data access relevant flags
+	SDIO->DTIMER = dtimer;
+	SDIO->DLEN = dlen;
+	SDIO->DCTRL = flags;// | SDIO_DCTRL_DTEN; // enable data transfer
+}
+
+#endif /* STM32_HIGH_DENSITY */
+
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
+#endif
diff --git a/STM32F4/cores/maple/wirish_time.h b/STM32F4/cores/maple/wirish_time.h
index 3a117863c..87091a307 100644
--- a/STM32F4/cores/maple/wirish_time.h
+++ b/STM32F4/cores/maple/wirish_time.h
@@ -36,6 +36,10 @@
 #include <libmaple/nvic.h>
 #include <libmaple/systick.h>
 
+#ifdef __cplusplus
+extern "C"{
+#endif
+
 #define US_PER_MS               1000
 
 /**
@@ -101,4 +105,8 @@ void delay(unsigned long ms);
  */
 void delayMicroseconds(uint32 us);
 
+#ifdef __cplusplus
+} /* extern "C" */
+#endif
+
 #endif

From 4aa44ee0e0eb99707a0aa8d407444eb8c539a694 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Sun, 18 Jun 2017 18:40:40 +0200
Subject: [PATCH 118/307] added SDIO lib files

---
 STM32F4/libraries/SDIO/SdioF4.cpp | 801 ++++++++++++++++++++++++++++++
 STM32F4/libraries/SDIO/SdioF4.h   |   7 +
 2 files changed, 808 insertions(+)
 create mode 100644 STM32F4/libraries/SDIO/SdioF4.cpp
 create mode 100644 STM32F4/libraries/SDIO/SdioF4.h

diff --git a/STM32F4/libraries/SDIO/SdioF4.cpp b/STM32F4/libraries/SDIO/SdioF4.cpp
new file mode 100644
index 000000000..1d533a0a3
--- /dev/null
+++ b/STM32F4/libraries/SDIO/SdioF4.cpp
@@ -0,0 +1,801 @@
+/* Arduino SdCard Library
+ * Copyright (C) 2016 by William Greiman
+ *
+ * This file is part of the Arduino SdSpiCard Library
+ *
+ * This Library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This Library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with the Arduino SdSpiCard Library.  If not, see
+ * <http://www.gnu.org/licenses/>.
+ */
+
+#include "SdioF4.h"
+#include <libmaple\sdio.h>
+#include <libmaple\dma.h>
+#include <boards.h>
+
+#define USE_DEBUG_MODE 0
+
+//==============================================================================
+//#define SDHC_PROCTL_DTW_4BIT 0x01
+#define CMD8_RETRIES 10
+#define BUSY_TIMEOUT_MILLIS 500
+//==============================================================================
+#define CMD_RESP_NONE SDIO_CMD_WAIT_NO_RESP
+#define CMD_RESP_R1   SDIO_CMD_WAIT_SHORT_RESP // normal response
+#define CMD_RESP_R1b  SDIO_CMD_WAIT_SHORT_RESP // normal response + busy data line (optional)
+#define CMD_RESP_R2   SDIO_CMD_WAIT_LONG_RESP  // CID, CSD
+#define CMD_RESP_R3   SDIO_CMD_WAIT_SHORT_RESP // OCR register, response to ACMD41
+#define CMD_RESP_R6   SDIO_CMD_WAIT_SHORT_RESP // published RCA response, response to CMD3
+#define CMD_RESP_R7   SDIO_CMD_WAIT_SHORT_RESP // response to CMD8
+
+#define CMD0_XFERTYP    (uint16_t)( CMD0   | CMD_RESP_NONE )
+#define CMD2_XFERTYP    (uint16_t)( CMD2   | CMD_RESP_R2   )
+#define CMD3_XFERTYP    (uint16_t)( CMD3   | CMD_RESP_R6   )
+#define CMD6_XFERTYP    (uint16_t)( CMD6   | CMD_RESP_R1   )
+#define ACMD6_XFERTYP   (uint16_t)( ACMD6  | CMD_RESP_R1   )
+#define CMD7_XFERTYP    (uint16_t)( CMD7   | CMD_RESP_R1b  )
+#define CMD8_XFERTYP    (uint16_t)( CMD8   | CMD_RESP_R7   )
+#define CMD9_XFERTYP    (uint16_t)( CMD9   | CMD_RESP_R2   )
+#define CMD10_XFERTYP   (uint16_t)( CMD10  | CMD_RESP_R2   )
+#define CMD12_XFERTYP   (uint16_t)( CMD12  | CMD_RESP_R1b  )
+#define CMD13_XFERTYP   (uint16_t)( CMD13  | CMD_RESP_R1   )
+#define CMD17_XFERTYP   (uint16_t)( CMD17  | CMD_RESP_R1   )
+#define CMD18_XFERTYP   (uint16_t)( CMD18  | CMD_RESP_R1   )
+#define ACMD23_XFERTYP  (uint16_t)( ACMD23 | CMD_RESP_R1   )
+#define CMD24_XFERTYP   (uint16_t)( CMD24  | CMD_RESP_R1   )
+#define CMD25_XFERTYP   (uint16_t)( CMD25  | CMD_RESP_R1   )
+#define CMD32_XFERTYP   (uint16_t)( CMD32  | CMD_RESP_R1   )
+#define CMD33_XFERTYP   (uint16_t)( CMD32  | CMD_RESP_R1   )
+#define CMD38_XFERTYP   (uint16_t)( CMD38  | CMD_RESP_R1b  )
+#define ACMD41_XFERTYP  (uint16_t)( ACMD41 | CMD_RESP_R3   )
+
+#define CMD55_XFERTYP   (uint16_t)( CMD55  | CMD_RESP_R1   )
+
+//=============================================================================
+//static void enableGPIO(bool enable);
+//static void enableDmaIrs();
+static void initSDHC(void);
+static bool isBusyCMD13(void);
+static bool isBusyTransferComplete(void);
+//static bool isBusyCommandComplete();
+//static bool isBusyCommandInhibit();
+static bool readReg16(uint32_t xfertyp, void* data);
+//static void setSdclk(uint32_t kHzMax);
+static bool yieldTimeout(bool (*fcn)(void));
+static bool waitDmaStatus(void);
+static bool waitTimeout(bool (*fcn)(void));
+//-----------------------------------------------------------------------------
+#define TRX_RD 0
+#define TRX_WR 1
+static uint8_t m_dir = TRX_RD;
+static bool (*m_busyFcn)() = 0;
+static bool m_initDone = false;
+static uint32_t m_lba; // for raw non-DMA read(write)Start, read(write)Data, read(write)Stop
+static uint32_t m_cnt; // for raw non-DMA read(write)Start, read(write)Data, read(write)Stop
+static bool m_version2;
+static bool m_highCapacity;
+static uint8_t m_errorCode = SD_CARD_ERROR_INIT_NOT_CALLED;
+static uint32_t m_errorLine = 0;
+static uint32_t m_rca;
+//static volatile bool m_dmaBusy = false;
+static volatile uint32_t m_irqstat;
+static uint32_t m_sdClkKhz = 0;
+static uint32_t m_ocr;
+static cid_t m_cid;
+static csd_t m_csd;
+static uint32_t t = 0;
+//=============================================================================
+#if USE_DEBUG_MODE
+#define DBG_PRINT() { \
+	Serial.write('_'); Serial.print(__FUNCTION__); Serial.write('_'); Serial.print(__LINE__); Serial.print(": "); \
+	Serial.print("DMA->LISR: "); Serial.print(DMA2->regs->LISR, HEX); \
+	/*Serial.print("DMA->HISR: "); Serial.println(DMA2->regs->HISR, HEX);*/ \
+	Serial.print(", DMA->CR: "); Serial.print(DMA2->regs->STREAM[DMA_STREAM3].CR, HEX); \
+	Serial.print(", DMA->NDTR: "); Serial.print(DMA2->regs->STREAM[DMA_STREAM3].NDTR, HEX); \
+	/**/Serial.print(", DMA->PAR: "); Serial.print(DMA2->regs->STREAM[DMA_STREAM3].PAR, HEX); \
+	/**/Serial.print(", DMA->M0AR: "); Serial.print(DMA2->regs->STREAM[DMA_STREAM3].M0AR, HEX); \
+	Serial.print(", DMA->FCR: "); Serial.print(DMA2->regs->STREAM[DMA_STREAM3].FCR, HEX); \
+ \
+	/*Serial.print(" SDIO->POWER: "); Serial.println(SDIO->POWER, HEX);*/ \
+	Serial.print(", SDIO->CLKCR: "); Serial.print(SDIO->CLKCR, HEX); \
+	Serial.print(", SDIO->DTIMER: "); Serial.print(SDIO->DTIMER, HEX); \
+	Serial.print(", SDIO->DCTRL: "); Serial.print(SDIO->DCTRL, HEX); \
+	/**/Serial.print(", SDIO->DLEN: "); Serial.print(SDIO->DLEN); \
+	Serial.print(", SDIO->DCOUNT: "); Serial.print(SDIO->DCOUNT); \
+	Serial.print(", SDIO->STA: "); Serial.println(SDIO->STA, HEX); \
+	/*delay(1);*/ \
+}
+#define DBG_PIN PD0
+
+#else  // USE_DEBUG_MODE
+#define DBG_PRINT()
+#endif  // USE_DEBUG_MODE
+
+/*****************************************************************************/
+static void _panic(const char *message, uint32_t code)
+{
+	Serial.print(message); Serial.println(code, HEX);
+	//Block the execution with blinky leds
+	pinMode(BOARD_LED_PIN, OUTPUT);
+	pinMode(BOARD_LED2_PIN, OUTPUT);
+	while (1) {
+		digitalWrite(BOARD_LED_PIN, HIGH);
+		digitalWrite(BOARD_LED2_PIN, LOW);
+		delay(250);
+		digitalWrite(BOARD_LED_PIN, LOW);
+		digitalWrite(BOARD_LED2_PIN, HIGH);
+		delay(250);
+	}
+}
+/*===========================================================================
+void yield(void)
+{
+	uint32_t val = SDIO->STA;
+	if ( val & SDIO_STA_TRX_ERROR_FLAGS ) {
+		Serial.print("SDIO ERROR:: SDIO->CLKCR: "); Serial.print(SDIO->CLKCR, HEX); \
+		Serial.print(", SDIO->DTIMER: "); Serial.print(SDIO->DTIMER, HEX); \
+		Serial.print(", SDIO->DCTRL: "); Serial.print(SDIO->DCTRL, HEX); \
+		Serial.print(", SDIO->DLEN: "); Serial.print(SDIO->DLEN); \
+		Serial.print(", SDIO->DCOUNT: "); Serial.print(SDIO->DCOUNT); \
+		Serial.print(", SDIO->STA: "); Serial.print(SDIO->STA, HEX); \
+		Serial.print(", SDIO->RESP0: "); Serial.println(SDIO->RESP[0], HEX); \
+		if (val & SDIO_STA_STBITERR) Serial.print(" STBITERR");
+		if (val & SDIO_STA_RXOVERR) Serial.print(" RXOVERR");
+		if (val & SDIO_STA_TXUNDERR) Serial.print(" TXUNDERR");
+		if (val & SDIO_STA_DTIMEOUT) Serial.print(" DTIMEOUT");
+		if (val & SDIO_STA_DCRCFAIL) Serial.print(" DCRCFAIL");
+		_panic(" - SDIO: Data Transmission Error ", val);
+	}
+
+	val = dma_get_isr_bit(DMA2, DMA_STREAM3, DMA_ISR_ERROR_BITS);
+	if ( val & DMA_ISR_FEIF ) {
+		val ^= DMA_ISR_FEIF;
+		dma_clear_isr_bit(DMA2, DMA_STREAM3, DMA_ISR_FEIF);
+	}
+	if ( val ) {
+		if (val & DMA_ISR_TEIF) Serial.print(" TEIF");
+		if (val & DMA_ISR_DMEIF) Serial.print(" DMEIF");
+		//if (val & DMA_ISR_FEIF) Serial.print(" FEIF");
+		_panic(" - DMA: Data Transmission Error ", val);
+	}
+	//Serial.write('.');
+}*/
+//=============================================================================
+// Error function and macro.
+inline bool setSdErrorCode(uint8_t code, uint32_t line) {
+  m_errorCode = code;
+  m_errorLine = line;
+  return false;  // setSdErrorCode
+}
+#define sdError(code) setSdErrorCode(code, __LINE__)
+//=============================================================================
+/* ISR
+void sdhc_isr() {
+  SDHC_IRQSIGEN = 0;
+  m_irqstat = SDHC_IRQSTAT;
+  SDHC_IRQSTAT = m_irqstat;
+  m_dmaBusy = false;
+}*/
+//=============================================================================
+// Static functions.
+//-----------------------------------------------------------------------------
+static bool cardCommand(uint16_t xfertyp, uint32_t arg)
+{
+#if USE_DEBUG_MODE
+	Serial.print("cardCommand: "); Serial.print(xfertyp&SDIO_CMD_CMDINDEX); Serial.print(", arg: "); Serial.print(arg, HEX);
+#endif
+	uint8_t resp = sdio_cmd_send(xfertyp, arg); // returns non-zero if fails, zero if OK
+#if USE_DEBUG_MODE
+	Serial.print(", resp: "); Serial.print(resp, HEX);
+	Serial.print(", SDIO->STA: "); Serial.print(SDIO->STA, HEX); Serial.print(", cmd_resp: "); Serial.print(SDIO->RESP[0], HEX);
+	if ( (xfertyp&SDIO_CMD_WAIT_LONG_RESP)==SDIO_CMD_WAIT_LONG_RESP ) {
+		Serial.print(", "); Serial.print(SDIO->RESP[1], HEX); Serial.print(", "); Serial.print(SDIO->RESP[2], HEX); Serial.print(", "); Serial.println(SDIO->RESP[3], HEX);
+	} else Serial.println();
+#endif
+	return resp; // return non-zero when OK
+}
+//-----------------------------------------------------------------------------
+static bool cardAcmd(uint32_t rca, uint32_t xfertyp, uint32_t arg) {
+  return cardCommand(CMD55_XFERTYP, rca) && cardCommand((uint16_t)xfertyp, arg);
+}
+/*---------------------------------------------------------------------------*/
+static bool cardCMD6(uint32_t arg, uint8_t* status) {
+  // CMD6 returns 64 bytes.
+  // use polling only for the moment
+	if (waitTimeout(isBusyCMD13)) {
+		return sdError(SD_CARD_ERROR_CMD13);
+	}
+	// get the 64 bytes over data lines
+	sdio_setup_transfer(80000, 64, (SDIO_BLOCKSIZE_64 | SDIO_DIR_RX | SDIO_DCTRL_DTEN));
+
+	cardCommand(CMD6_XFERTYP, arg);
+
+	// wait data Rx response
+	if (waitTimeout(isBusyTransferComplete)) {
+		return sdError(SD_CARD_ERROR_CMD6);
+	}
+DBG_PRINT();
+	// copy 64 bytes as 16 words from FIFO to buffer
+	for (uint8_t i=0; i<16; i++) {
+		*(uint32_t*)(&status[i<<2]) = SDIO->FIFO;
+	}
+	//SDIO->DCTRL = 0; // disable data controller
+
+#if USE_DEBUG_MODE
+	Serial.print("read data: "); for (uint8_t i=0; i<17; i++) { Serial.print(status[i], HEX); Serial.print(", "); } Serial.println();
+#endif
+return true;
+}
+//-----------------------------------------------------------------------------
+static void initSDHC(void)
+{
+	sdio_begin();
+	DBG_PRINT();
+}
+/*---------------------------------------------------------------------------*/
+static bool isBusyCMD13(void) {
+  if (!cardCommand(CMD13_XFERTYP, m_rca)) { // SEND_STATUS
+    // Caller will timeout.
+    return true;
+  }
+  return !(SDIO->RESP[0] & CARD_STATUS_READY_FOR_DATA);
+}
+/*---------------------------------------------------------------------------*/
+static bool isBusyDMA(void)
+{
+	uint8_t isr = dma_get_isr_bit(DMA2, DMA_STREAM3, (DMA_ISR_TCIF | DMA_ISR_ERROR_BITS));
+	//if (isr&DMA_ISR_TCIF) dma_disable(DMA2, DMA_STREAM3);
+	return !(isr^DMA_ISR_FEIF); // ignore transfer error flag
+}
+/*---------------------------------------------------------------------------*/
+static bool isBusyTransferComplete(void)
+{
+	uint32_t mask = SDIO->STA &(SDIO_STA_DATAEND | SDIO_STA_TRX_ERROR_FLAGS);
+#if USE_DEBUG_MODE
+	if ( mask & SDIO_STA_TRX_ERROR_FLAGS ) {
+		Serial.print("XFER ERROR: SDIO->STA: "); Serial.print(SDIO->STA, HEX);
+		if (mask & SDIO_STA_STBITERR) Serial.print(" STBITERR");
+		if (mask & SDIO_STA_RXOVERR)  Serial.print(" RXOVERR");
+		if (mask & SDIO_STA_TXUNDERR) Serial.print(" TXUNDERR");
+		if (mask & SDIO_STA_DTIMEOUT) Serial.print(" DTIMEOUT");
+		if (mask & SDIO_STA_DCRCFAIL) Serial.print(" DCRCFAIL");
+		Serial.println();
+	}
+#endif
+	if (mask) {
+		dma_disable(DMA2, DMA_STREAM3);
+		return false;
+	}
+	return true;
+}
+/*---------------------------------------------------------------------------*/
+static void trxStart(uint8_t* buf, uint32_t n, uint8_t dir)
+{
+	m_dir = dir;
+	uint32_t flags = (SDIO_BLOCKSIZE_512 | SDIO_DCTRL_DTEN);
+	if (dir==TRX_RD) flags |= SDIO_DIR_RX;
+	// setup SDIO to transfer n blocks of 512 bytes
+	sdio_setup_transfer(0x00FFFFFF, n, flags);
+}
+/*---------------------------------------------------------------------------*/
+static bool trxStop()
+{
+	if (!cardCommand(CMD12_XFERTYP, 0)) {
+		return sdError(SD_CARD_ERROR_CMD12);
+	}
+	if ( t ) {
+		Serial.print(", in "); Serial.println(millis()-t);
+		t = 0;
+	}
+	return true;
+}
+/*---------------------------------------------------------------------------*/
+static bool dmaTrxStart(uint8_t* buf, uint32_t n, uint8_t dir)
+{
+	m_dir = dir;
+	if ((3 & (uint32_t)buf) || n == 0) { // check alignment
+		_panic("- transferStart: unaligned buffer address ", (uint32_t)buf);
+		return sdError(SD_CARD_ERROR_DMA);
+	}
+	if (dir==TRX_RD && yieldTimeout(isBusyCMD13)) {
+		return sdError(SD_CARD_ERROR_CMD13);
+	}
+	uint32_t flags = (SDIO_BLOCKSIZE_512 | SDIO_DCTRL_DMAEN | SDIO_DCTRL_DTEN);
+	if (dir==TRX_RD) flags |= SDIO_DIR_RX;
+	// setup SDIO to transfer n blocks of 512 bytes
+	sdio_setup_transfer(0x00FFFFFF, n, flags);
+	// setup DMA2 stream 3 channel 4
+	dma_init(DMA2);
+	flags = (DMA_PERIF_CTRL | DMA_BURST_INCR4 | DMA_MINC_MODE | DMA_PRIO_VERY_HIGH);
+	if (dir==TRX_RD) flags |= DMA_FROM_PER; // read
+	else             flags |= DMA_FROM_MEM; // write
+	dma_setup_transfer(DMA2, DMA_STREAM3, DMA_CH4, DMA_SIZE_32BITS, &SDIO->FIFO, buf, NULL, flags);
+	dma_set_num_transfers(DMA2, DMA_STREAM3, n);
+	dma_set_fifo_flags(DMA2, DMA_STREAM3, (DMA_FCR_DMDIS | DMA_FCR_FTH_FULL)); // disable direct mode | threshold FULL
+	dma_clear_isr_bits(DMA2, DMA_STREAM3);
+	dma_enable(DMA2, DMA_STREAM3);
+	return true;
+}
+/*---------------------------------------------------------------------------*/
+static bool dmaTrxEnd(bool multi_block)
+{
+	if ( !waitDmaStatus() ) {
+		return sdError(SD_CARD_ERROR_DMA);
+	}
+	if ( waitTimeout(isBusyTransferComplete) ) {
+		if (m_dir==TRX_RD)
+			return sdError(SD_CARD_ERROR_READ_TIMEOUT);
+		else
+			return sdError(SD_CARD_ERROR_WRITE_TIMEOUT);
+	}
+	if (multi_block) {
+		return trxStop();
+	} else {
+		if ( t ) {
+			Serial.print(", in "); Serial.println(millis()-t);
+			t = 0;
+		}
+		return true;
+	}
+}
+//-----------------------------------------------------------------------------
+// Read 16 byte CID or CSD register.
+static bool readReg16(uint32_t xfertyp, void* data)
+{
+  uint8_t* d = reinterpret_cast<uint8_t*>(data);
+  if (!cardCommand(xfertyp, m_rca)) {
+    return false;  // Caller will set errorCode.
+  }
+  *(uint32_t*)(&d[0])  = __builtin_bswap32(SDIO->RESP[0]);
+  *(uint32_t*)(&d[4])  = __builtin_bswap32(SDIO->RESP[1]);
+  *(uint32_t*)(&d[8])  = __builtin_bswap32(SDIO->RESP[2]);
+  *(uint32_t*)(&d[12]) = __builtin_bswap32(SDIO->RESP[3]);
+  d[15] = 0;
+  return true;
+}
+/*---------------------------------------------------------------------------*/
+// Return true if timeout occurs.
+static bool yieldTimeout(bool (*fcn)()) {
+  uint32_t m = millis();
+  while (fcn()) {
+    if ((millis() - m) > BUSY_TIMEOUT_MILLIS) {
+      return true;
+    }
+    yield();
+  }
+  return false;  // Caller will set errorCode.
+}
+/*---------------------------------------------------------------------------*/
+static bool waitDmaStatus(void)
+{
+  if (yieldTimeout(isBusyDMA)) {
+    return false;  // Caller will set errorCode.
+  }
+  return true;
+}
+/*---------------------------------------------------------------------------*/
+// Return true if timeout occurs.
+static bool waitTimeout(bool (*fcn)(void)) {
+  uint32_t m = millis();
+  while (fcn()) {
+    if ((millis() - m) > BUSY_TIMEOUT_MILLIS) {
+      return true;
+    }
+	delayMicroseconds(1);
+  }
+  return false;  // Caller will set errorCode.
+}
+
+uint32_t aligned[128]; // temporary buffer for misaligned buffers
+//=============================================================================
+bool SdioCard::begin(void)
+{
+  m_initDone = false;
+  m_errorCode = SD_CARD_ERROR_NONE;
+  m_highCapacity = false;
+  m_version2 = false;
+
+#if USE_DEBUG_MODE
+pinMode(DBG_PIN, OUTPUT);
+digitalWrite(DBG_PIN, HIGH);
+delay(100);
+#endif
+  // initialize controller.
+  initSDHC();
+
+  if (!cardCommand(CMD0_XFERTYP, 0)) {
+    return sdError(SD_CARD_ERROR_CMD0);
+  }
+  // Try several times for case of reset delay.
+  for (uint32_t i = 0; i < CMD8_RETRIES; i++) {
+    if (cardCommand(CMD8_XFERTYP, 0X1AA)) {
+      if (SDIO->RESP[0] != 0X1AA) {
+        return sdError(SD_CARD_ERROR_CMD8);
+      }
+      m_version2 = true;
+      break;
+    }
+  }
+  uint32_t arg = m_version2 ? 0X40300000 : 0x00300000;
+  uint32_t m = millis();
+  do {
+    if (!cardAcmd(0, ACMD41_XFERTYP, arg) ||
+       ((millis() - m) > BUSY_TIMEOUT_MILLIS)) {
+      return sdError(SD_CARD_ERROR_ACMD41);
+    }
+  } while ((SDIO->RESP[0] & 0x80000000) == 0);
+
+  m_ocr = SDIO->RESP[0];
+  if (m_ocr & 0x40000000) {
+    // Is high capacity.
+    m_highCapacity = true;
+  }
+  if (!cardCommand(CMD2_XFERTYP, 0)) {
+    return sdError(SD_CARD_ERROR_CMD2);
+  }
+  if (!cardCommand(CMD3_XFERTYP, 0)) {
+    return sdError(SD_CARD_ERROR_CMD3);
+  }
+  m_rca = SDIO->RESP[0] & 0xFFFF0000;
+  if (!readReg16(CMD9_XFERTYP, &m_csd)) {
+    return sdError(SD_CARD_ERROR_CMD9);
+  }
+  if (!readReg16(CMD10_XFERTYP, &m_cid)) {
+    return sdError(SD_CARD_ERROR_CMD10);
+  }
+  if (!cardCommand(CMD7_XFERTYP, m_rca)) {
+    return sdError(SD_CARD_ERROR_CMD7);
+  }
+  // Set card to bus width four.
+  if (!cardAcmd(m_rca, ACMD6_XFERTYP, 2)) {
+    return sdError(SD_CARD_ERROR_ACMD6);
+  }
+  sdio_set_dbus_width(SDIO_CLKCR_WIDBUS_4BIT);
+
+  // Determine if High Speed mode is supported and set frequency.
+  uint8_t status[64];
+  // see "Physical Layer Simplified Specification Version 6.00", chapter 4.3.10, Table 4-13.
+  // Support Bits of Functions in Function Group 1: bits 415:400, which are bytes [12][13]
+  // Function Selection of Function Group 1: bits 379:376, which is low nibble of byte [16]
+  if (cardCMD6(0X00FFFFFF, status) && (2 & status[13]) &&
+      cardCMD6(0X80FFFFF1, status) && (status[16] & 0XF) == 1) {
+	//Serial.println("\n*** 50MHz clock supported ***");
+  } else {
+	_panic("*** Only 25MHz clock supported! ***", 0);
+  }
+
+  m_sdClkKhz = 24000;
+  sdio_set_clock(m_sdClkKhz*1000); // set clock to 24MHz
+
+  m_initDone = true;
+  return true;
+}
+//-----------------------------------------------------------------------------
+uint32_t SdioCard::cardSize(void) {
+  return sdCardCapacity(&m_csd);
+}
+/*---------------------------------------------------------------------------*/
+bool SdioCard::erase(uint32_t firstBlock, uint32_t lastBlock) {
+  // check for single block erase
+  if (!m_csd.v1.erase_blk_en) {
+    // erase size mask
+    uint8_t m = (m_csd.v1.sector_size_high << 1) | m_csd.v1.sector_size_low;
+    if ((firstBlock & m) != 0 || ((lastBlock + 1) & m) != 0) {
+      // error card can't erase specified area
+      return sdError(SD_CARD_ERROR_ERASE_SINGLE_BLOCK);
+    }
+  }
+  if (!m_highCapacity) {
+    firstBlock <<= 9;
+    lastBlock <<= 9;
+  }
+  if (!cardCommand(CMD32_XFERTYP, firstBlock)) {
+    return sdError(SD_CARD_ERROR_CMD32);
+  }
+  if (!cardCommand(CMD33_XFERTYP, lastBlock)) {
+     return sdError(SD_CARD_ERROR_CMD33);
+  }
+  if (!cardCommand(CMD38_XFERTYP, 0)) {
+    return sdError(SD_CARD_ERROR_CMD38);
+  }
+  if (waitTimeout(isBusyCMD13)) {
+    return sdError(SD_CARD_ERROR_ERASE_TIMEOUT);
+  }
+  return true;
+}
+//-----------------------------------------------------------------------------
+uint8_t SdioCard::errorCode() {
+  return m_errorCode;
+}
+//-----------------------------------------------------------------------------
+uint32_t SdioCard::errorData() {
+  return m_irqstat;
+}
+//-----------------------------------------------------------------------------
+uint32_t SdioCard::errorLine() {
+  return m_errorLine;
+}
+//-----------------------------------------------------------------------------
+bool SdioCard::isBusy() {
+  return m_busyFcn ? m_busyFcn() : m_initDone && isBusyCMD13();
+}
+//-----------------------------------------------------------------------------
+uint32_t SdioCard::kHzSdClk() {
+  return m_sdClkKhz;
+}
+/*---------------------------------------------------------------------------*/
+bool SdioCard::readBlock(uint32_t lba, uint8_t* buf)
+{
+	// prepare SDIO and DMA for data read transfer
+	dmaTrxStart((uint32_t)buf & 3 ? (uint8_t*)aligned : buf, 512, TRX_RD);
+	// send command to start data transfer
+	if ( !cardCommand(CMD17_XFERTYP, (m_highCapacity ? lba : 512*lba)) ) {
+		return sdError(SD_CARD_ERROR_CMD17);
+	}
+	if ( dmaTrxEnd(0)) {
+		if ( (uint32_t)buf & 3 ) {
+			//memcpy(buf, aligned, 512);
+			register uint8_t * dst = buf;
+			register uint8_t * src = (uint8_t *)aligned;
+			register uint16_t i = 64;
+			while ( i-- ) { // do 8 byte copies, is much faster than single byte copy
+				*dst++ = *src++; *dst++ = *src++; *dst++ = *src++; *dst++ = *src++;
+				*dst++ = *src++; *dst++ = *src++; *dst++ = *src++; *dst++ = *src++;
+			}
+		}
+		return true;
+	}
+	return false;
+}
+/*---------------------------------------------------------------------------*/
+bool SdioCard::readBlocks(uint32_t lba, uint8_t* buf, size_t n)
+{
+	if ((uint32_t)buf & 3) {
+		for (size_t i = 0; i < n; i++, lba++, buf += 512) {
+			if (!readBlock(lba, buf)) {
+				return false;  // readBlock will set errorCode.
+			}
+		}
+		return true;
+	}
+	// prepare SDIO and DMA for data read transfer
+	dmaTrxStart(buf, 512*n, TRX_RD);
+	// send command to start data transfer
+	if ( !cardCommand(CMD18_XFERTYP, (m_highCapacity ? lba : 512*lba)) ) {
+		return sdError(SD_CARD_ERROR_CMD18);
+	}
+	return dmaTrxEnd(1);
+}
+//-----------------------------------------------------------------------------
+bool SdioCard::readCID(void* cid) {
+  memcpy(cid, &m_cid, 16);
+  return true;
+}
+//-----------------------------------------------------------------------------
+bool SdioCard::readCSD(void* csd) {
+  memcpy(csd, &m_csd, 16);
+  return true;
+}
+/*---------------------------------------------------------------------------*/
+bool SdioCard::readData(uint8_t *dst)
+{
+	//Serial.print("readData: "); Serial.print(m_lba); Serial.print(", m_cnt: "); Serial.println(m_cnt);
+	if ( m_cnt==0 ) return false;
+	if (yieldTimeout(isBusyCMD13)) { // wait for previous transmission end
+		return sdError(SD_CARD_ERROR_CMD13);
+	}
+	// non-DMA block read
+	trxStart(dst, 512, TRX_RD);
+	// send command to start data transfer
+	if ( !cardCommand(CMD17_XFERTYP, (m_highCapacity ? m_lba : 512*m_lba)) ) {
+		return sdError(SD_CARD_ERROR_CMD17);
+	}
+	// Receive a data block from the SDIO
+	register uint32_t STA; // to speed up SDIO flags checking
+	register uint16_t cnt = 512;
+	register uint32_t * ptr = (uint32_t *)dst;
+	// ----> TIME CRITICAL SECTION BEGIN <----
+	do {
+		STA = SDIO->STA;
+		if (STA & SDIO_STA_RXFIFOHF) {
+			// Receive FIFO half full, there are at least 8 words in it
+			noInterrupts();
+			*ptr++ = SDIO->FIFO; *ptr++ = SDIO->FIFO; *ptr++ = SDIO->FIFO; *ptr++ = SDIO->FIFO;
+			*ptr++ = SDIO->FIFO; *ptr++ = SDIO->FIFO; *ptr++ = SDIO->FIFO; *ptr++ = SDIO->FIFO;
+			interrupts();
+			cnt -= 8;
+		}
+	} while ( !(STA & (SDIO_STA_DATAEND | SDIO_STA_TRX_ERROR_FLAGS)) );
+	// <---- TIME CRITICAL SECTION END ---->
+
+	// read data still available in FIFO
+	while ( (SDIO->STA & SDIO_STA_RXDAVL) && (cnt--) ) {
+		*ptr++ = SDIO->FIFO;
+	}
+	// check error, temporary stuff, remove for final version
+	if ( SDIO->STA & SDIO_STA_TRX_ERROR_FLAGS ) {
+		_panic("ERROR: non-DMA read error ", SDIO->STA);
+		return false;
+	}
+	m_lba++;
+	m_cnt--;
+	return !(SDIO->STA&SDIO_STA_TRX_ERROR_FLAGS);
+}
+//-----------------------------------------------------------------------------
+bool SdioCard::readOCR(uint32_t* ocr) {
+  *ocr = m_ocr;
+  return true;
+}
+//-----------------------------------------------------------------------------
+bool SdioCard::readStart(uint32_t lba)
+{
+  m_lba = lba;
+  m_cnt = 1024;
+  return true;
+}
+/*---------------------------------------------------------------------------*/
+// SDHC will do Auto CMD12 after count blocks.
+bool SdioCard::readStart(uint32_t lba, uint32_t count)
+{
+	//Serial.print("readStart: "); Serial.print(lba); Serial.print(", cnt: "); Serial.println(count);
+  m_lba = lba;
+  m_cnt = count;
+  return true;
+}
+/*---------------------------------------------------------------------------*/
+bool SdioCard::readStop()
+{
+	//Serial.println("readStop.");
+  m_lba = 0;
+  m_cnt = 0;
+  return true;
+}
+//-----------------------------------------------------------------------------
+bool SdioCard::syncBlocks() {
+  return true;
+}
+//-----------------------------------------------------------------------------
+uint8_t SdioCard::type() {
+  return  m_version2 ? m_highCapacity ?
+          SD_CARD_TYPE_SDHC : SD_CARD_TYPE_SD2 : SD_CARD_TYPE_SD1;
+}
+/*---------------------------------------------------------------------------*/
+bool SdioCard::writeBlock(uint32_t lba, const uint8_t* buf)
+{
+	uint8_t * ptr = (uint8_t *)buf;
+	if (3 & (uint32_t)ptr) {
+		//Serial.print("writeBlock: "); Serial.print(lba);
+		Serial.print(", buf: "); Serial.print((uint32_t)ptr, HEX);
+		//memcpy(aligned, buf, 512);
+		register uint8_t * src = (uint8_t *)ptr;
+		ptr = (uint8_t *)aligned;
+		register uint8_t * dst = ptr;
+		register uint16_t i = 64;
+		while ( i-- ) { // do 8 byte copies, is much faster than single byte copy
+			*dst++ = *src++; *dst++ = *src++; *dst++ = *src++; *dst++ = *src++;
+			*dst++ = *src++; *dst++ = *src++; *dst++ = *src++; *dst++ = *src++;
+		}
+	}
+	if (yieldTimeout(isBusyCMD13)) { // wait for previous transmission end
+		return sdError(SD_CARD_ERROR_CMD13);
+	}
+	// send command to start data transfer
+	if ( !cardCommand(CMD24_XFERTYP, (m_highCapacity ? lba : 512*lba)) ) {
+		return sdError(SD_CARD_ERROR_CMD24);
+	}
+	// prepare SDIO and DMA for data transfer
+	dmaTrxStart(ptr, 512, TRX_WR); // 1 block, write transfer
+
+	return dmaTrxEnd(0);
+}
+/*---------------------------------------------------------------------------*/
+bool SdioCard::writeBlocks(uint32_t lba, const uint8_t* buf, size_t n)
+{
+	if (3 & (uint32_t)buf) { // misaligned buffer address, write single blocks
+		for (size_t i = 0; i < n; i++, lba++, buf += 512) {
+			if (!writeBlock(lba, buf)) {
+				return false;  // writeBlock will set errorCode.
+			}
+		}
+		return true;
+	}
+	//Serial.print("writeBlocks: ");  Serial.print(lba); Serial.print(", "); Serial.print(n);
+	if (yieldTimeout(isBusyCMD13)) {
+		return sdError(SD_CARD_ERROR_CMD13);
+	}
+#if 0
+	// set number of blocks to write - this can speed up block write
+	if ( !cardAcmd(m_rca, ACMD23_XFERTYP, n) ) {
+		return sdError(SD_CARD_ERROR_ACMD23);
+	}
+#endif
+	// send command to start data transfer
+	if ( !cardCommand(CMD25_XFERTYP, (m_highCapacity ? lba : 512*lba)) ) {
+		return sdError(SD_CARD_ERROR_CMD25);
+	}
+	// prepare SDIO and DMA for data transfer
+	dmaTrxStart((uint8_t *)buf, 512*n, TRX_WR); // n blocks, write transfer
+
+	return dmaTrxEnd(1);
+}
+/*---------------------------------------------------------------------------*/
+bool SdioCard::writeData(const uint8_t* src)
+{
+	//Serial.print("writeData: "); Serial.print(m_lba); Serial.print(", cnt: "); Serial.println(m_cnt);
+	if ( !m_cnt ) return false;
+	if (yieldTimeout(isBusyCMD13)) { // wait for previous transmission end
+		return sdError(SD_CARD_ERROR_CMD13);
+	}
+	// send command to start block data transfer
+	if ( !cardCommand(CMD24_XFERTYP, (m_highCapacity ? m_lba : 512*m_lba)) ) {
+		return sdError(SD_CARD_ERROR_CMD24);
+	}
+	// non-DMA block write
+	trxStart((uint8_t*)src, 512, TRX_WR);
+	// Receive a data block from the SDIO
+	register uint32_t STA; // to speed up SDIO flags checking
+	register uint16_t cnt = 512;
+	register uint32_t * ptr = (uint32_t*)src;
+	// pre-fill up the FIFO with 32 words
+	noInterrupts();
+	while ( (cnt--)>(512-32) ) SDIO->FIFO = *ptr++;
+	interrupts();
+	// ----> TIME CRITICAL SECTION BEGIN <----
+	do {
+		STA = SDIO->STA;
+		if (STA & SDIO_STA_TXFIFOHE) {
+			// Transmit FIFO half empty, fill up the remaining 16 words
+			noInterrupts();
+			SDIO->FIFO = *ptr++; SDIO->FIFO = *ptr++; SDIO->FIFO = *ptr++; SDIO->FIFO = *ptr++;
+			SDIO->FIFO = *ptr++; SDIO->FIFO = *ptr++; SDIO->FIFO = *ptr++; SDIO->FIFO = *ptr++;
+			SDIO->FIFO = *ptr++; SDIO->FIFO = *ptr++; SDIO->FIFO = *ptr++; SDIO->FIFO = *ptr++;
+			SDIO->FIFO = *ptr++; SDIO->FIFO = *ptr++; SDIO->FIFO = *ptr++; SDIO->FIFO = *ptr++;
+			interrupts();
+			cnt -= 16;
+		}
+	} while ( !(STA & (SDIO_STA_DATAEND | SDIO_STA_TRX_ERROR_FLAGS)) && cnt);
+	// <---- TIME CRITICAL SECTION END ---->
+	if ( waitTimeout(isBusyTransferComplete) ) {
+		return sdError(SD_CARD_ERROR_WRITE_TIMEOUT);
+	}
+	m_lba++;
+	m_cnt--;
+	if (SDIO->STA&SDIO_STA_TRX_ERROR_FLAGS) {
+		_panic("writeData error: ", SDIO->STA);
+	}
+	return !(SDIO->STA&SDIO_STA_TRX_ERROR_FLAGS);
+}
+//-----------------------------------------------------------------------------
+bool SdioCard::writeStart(uint32_t lba)
+{
+  m_lba = lba;
+  m_cnt = 1024;
+  return true;
+}
+/*---------------------------------------------------------------------------*/
+// SDHC will do Auto CMD12 after count blocks.
+bool SdioCard::writeStart(uint32_t lba, uint32_t count)
+{
+	//Serial.print("writeStart: "); Serial.print(lba); Serial.print(", cnt: "); Serial.println(count);
+  m_lba = lba;
+  m_cnt = count;
+  return true;
+}
+/*---------------------------------------------------------------------------*/
+bool SdioCard::writeStop()
+{
+	//Serial.println("writeStop.");
+  m_lba = 0;
+  m_cnt = 0;
+  return true;
+}
diff --git a/STM32F4/libraries/SDIO/SdioF4.h b/STM32F4/libraries/SDIO/SdioF4.h
new file mode 100644
index 000000000..c995b1c5c
--- /dev/null
+++ b/STM32F4/libraries/SDIO/SdioF4.h
@@ -0,0 +1,7 @@
+
+#ifndef _SDIOF4_H_
+#define _SDIOF4_H_
+
+#include <SdFat.h>
+
+#endif

From 8af6002812e15379ac75e1494558a894ed24970b Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Mon, 19 Jun 2017 17:11:04 +1000
Subject: [PATCH 119/307] Added link to gitter chat room in the readme

---
 README.md | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/README.md b/README.md
index 019cb2b26..b6c60f686 100644
--- a/README.md
+++ b/README.md
@@ -13,6 +13,8 @@ This repo contains, the "Hardware" files to support STM32 based boards on Arduin
 
 ***PRIMARY SUPPORT FORUM: http://www.stm32duino.com/***
 
+*** We are also on Gitter https://gitter.im/stm32duino/Lobby ***
+
 ##Background & Support:  
 * Based on https://github.com/bobc/maple-asp, which is in turn based on LibMaple by Leaflabs  
 * **Please read the wiki (https://github.com/rogerclarkmelbourne/Arduino_STM32/wiki) for full details**

From 6fa060c05a702f5d68c4c63752cdb2911b0764b1 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Mon, 19 Jun 2017 17:11:31 +1000
Subject: [PATCH 120/307] Updated readme for gitter (again)

---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index b6c60f686..b77db0128 100644
--- a/README.md
+++ b/README.md
@@ -13,7 +13,7 @@ This repo contains, the "Hardware" files to support STM32 based boards on Arduin
 
 ***PRIMARY SUPPORT FORUM: http://www.stm32duino.com/***
 
-*** We are also on Gitter https://gitter.im/stm32duino/Lobby ***
+***We are also on Gitter https://gitter.im/stm32duino/Lobby/***
 
 ##Background & Support:  
 * Based on https://github.com/bobc/maple-asp, which is in turn based on LibMaple by Leaflabs  

From b7fb21aa0ca9a3a679233ee403d4ae2e88ccc300 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Tue, 20 Jun 2017 18:33:00 +0200
Subject: [PATCH 121/307] make USB serial Tx blocking (bugfix for lost TX
 characters)

---
 STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.c | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.c b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.c
index 28a2d1ff2..bc4374795 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.c
@@ -25,7 +25,6 @@
 
 /* Includes ------------------------------------------------------------------*/
 #include "usbd_cdc_vcp.h"
-//#include  "stm32f4_discovery.h"
 
 /* Private typedef -----------------------------------------------------------*/
 /* Private define ------------------------------------------------------------*/
@@ -57,7 +56,7 @@ uint8_t UsbRecBuffer[UsbRecBufferSize];
 volatile int UsbRecRead = 0;
 volatile int UsbRecWrite = 0;
 volatile int VCP_DTRHIGH = 0;
-uint8_t UsbTXBlock = 0;
+uint8_t UsbTXBlock = 1;
 
 uint32_t VCPBytesAvailable(void) {
 	return (UsbRecWrite - UsbRecRead + UsbRecBufferSize) % UsbRecBufferSize;

From d872cb1963b39384c7344a1229179f59a09a2c17 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Tue, 20 Jun 2017 18:50:23 +0200
Subject: [PATCH 122/307] avoid multiple USB serial begin (taken from F1)

---
 STM32F4/cores/maple/usb_serial.cpp | 7 ++++++-
 STM32F4/cores/maple/usb_serial.h   | 3 +++
 2 files changed, 9 insertions(+), 1 deletion(-)

diff --git a/STM32F4/cores/maple/usb_serial.cpp b/STM32F4/cores/maple/usb_serial.cpp
index fadcb91af..1764e86fd 100644
--- a/STM32F4/cores/maple/usb_serial.cpp
+++ b/STM32F4/cores/maple/usb_serial.cpp
@@ -36,20 +36,25 @@
 #ifdef SERIAL_USB
 
 #define USB_TIMEOUT 50
+bool USBSerial::_hasBegun = false;
 
 USBSerial::USBSerial(void) {
 }
 
 void USBSerial::begin(void) {
+    if (_hasBegun)
+        return;
+    _hasBegun = true;
     setupUSB();
 }
 
 void USBSerial::begin(int) {
-    setupUSB();
+    this->begin();
 }
 
 void USBSerial::end(void) {
     disableUSB();
+	_hasBegun = false;
 }
 
 size_t USBSerial::write(uint8 ch) {
diff --git a/STM32F4/cores/maple/usb_serial.h b/STM32F4/cores/maple/usb_serial.h
index 8eeed966a..228802566 100644
--- a/STM32F4/cores/maple/usb_serial.h
+++ b/STM32F4/cores/maple/usb_serial.h
@@ -65,6 +65,9 @@ class USBSerial : public Stream {
 
     void enableBlockingTx(void);
     void disableBlockingTx(void);
+
+protected:
+    static bool _hasBegun;
 };
 
 extern USBSerial SerialUSB;

From f6dea1e50efa6694b9ccc577fb6b4103a7fa9272 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Tue, 20 Jun 2017 21:03:18 +0200
Subject: [PATCH 123/307] added CCMRAM definitions

---
 STM32F4/variants/generic_f407v/ld/common.inc | 9 +++++++++
 STM32F4/variants/generic_f407v/ld/jtag.ld    | 5 +++--
 2 files changed, 12 insertions(+), 2 deletions(-)

diff --git a/STM32F4/variants/generic_f407v/ld/common.inc b/STM32F4/variants/generic_f407v/ld/common.inc
index f5a0f5b6e..30c49c2d0 100644
--- a/STM32F4/variants/generic_f407v/ld/common.inc
+++ b/STM32F4/variants/generic_f407v/ld/common.inc
@@ -183,6 +183,15 @@ SECTIONS
       } > REGION_BSS
 
     /*
+     * .ccmram
+     */
+	.ccmram (NOLOAD):
+		{
+			. = ALIGN(8);
+			*(.ccmram .ccmram.*)
+		} > ccmram
+
+	/*
      * Debugging sections
      */
     .stab 0 (NOLOAD) : { *(.stab) }
diff --git a/STM32F4/variants/generic_f407v/ld/jtag.ld b/STM32F4/variants/generic_f407v/ld/jtag.ld
index 1001db518..2156f15c1 100644
--- a/STM32F4/variants/generic_f407v/ld/jtag.ld
+++ b/STM32F4/variants/generic_f407v/ld/jtag.ld
@@ -5,8 +5,9 @@
 
 MEMORY
 {
-  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 128K
-  rom (rx)  : ORIGIN = 0x08000000, LENGTH = 512K
+  ccmram (rw): ORIGIN = 0x10000000, LENGTH = 64K
+  ram (rwx)  : ORIGIN = 0x20000000, LENGTH = 128K
+  rom (rx)   : ORIGIN = 0x08000000, LENGTH = 512K
 }
 
 /* GROUP(libcs3_stm32_high_density.a) */

From 747634a31acd6b1aca33a8fdd9160e5a557dd6c6 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sat, 24 Jun 2017 17:23:54 +1000
Subject: [PATCH 124/307] Update README.md

---
 README.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/README.md b/README.md
index b77db0128..7e13786a2 100644
--- a/README.md
+++ b/README.md
@@ -14,6 +14,7 @@ This repo contains, the "Hardware" files to support STM32 based boards on Arduin
 ***PRIMARY SUPPORT FORUM: http://www.stm32duino.com/***
 
 ***We are also on Gitter https://gitter.im/stm32duino/Lobby/***
+[![Gitter](https://badges.gitter.im/Join%20Chat.svg)](https://gitter.im/stm32duino/Lobby?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
 
 ##Background & Support:  
 * Based on https://github.com/bobc/maple-asp, which is in turn based on LibMaple by Leaflabs  

From f7a576f2e0efcee958bdfd737d9af7a2f6c76051 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sun, 25 Jun 2017 13:08:30 +1000
Subject: [PATCH 125/307] Fixed issue with PB10 being set to OUTPUT for use as
 a USB Disconnect control on boards which do not have the additional USB
 disconnect hardware e.g. the Blue Pill. Note. Some variants seem to have the
 disconnect control on another pin, so I did not change those in case they
 were actually used

---
 .../cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c | 15 +++++++++++----
 STM32F1/variants/generic_gd32f103c/board/board.h  |  4 ++--
 STM32F1/variants/generic_stm32f103c/board/board.h |  4 ++--
 .../variants/generic_stm32f103r8/board/board.h    |  4 ++--
 STM32F1/variants/nucleo_f103rb/board/board.h      |  7 ++-----
 5 files changed, 19 insertions(+), 15 deletions(-)

diff --git a/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c b/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c
index 7a5a772af..774be42cb 100644
--- a/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c
+++ b/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c
@@ -384,9 +384,13 @@ void usb_cdcacm_enable(gpio_dev *disc_dev, uint8 disc_bit) {
     /* Present ourselves to the host. Writing 0 to "disc" pin must
      * pull USB_DP pin up while leaving USB_DM pulled down by the
      * transceiver. See USB 2.0 spec, section 7.1.7.3. */
-    gpio_set_mode(disc_dev, disc_bit, GPIO_OUTPUT_PP);
-    gpio_write_bit(disc_dev, disc_bit, 0);
-
+	 
+	if (disc_dev!=NULL)
+	{	 
+		gpio_set_mode(disc_dev, disc_bit, GPIO_OUTPUT_PP);
+		gpio_write_bit(disc_dev, disc_bit, 0);
+	}
+	
     /* Initialize the USB peripheral. */
     usb_init_usblib(USBLIB, ep_int_in, ep_int_out);
 }
@@ -395,7 +399,10 @@ void usb_cdcacm_disable(gpio_dev *disc_dev, uint8 disc_bit) {
     /* Turn off the interrupt and signal disconnect (see e.g. USB 2.0
      * spec, section 7.1.7.3). */
     nvic_irq_disable(NVIC_USB_LP_CAN_RX0);
-    gpio_write_bit(disc_dev, disc_bit, 1);
+	if (disc_dev!=NULL)
+	{
+		gpio_write_bit(disc_dev, disc_bit, 1);
+	}
 }
 
 void usb_cdcacm_putc(char ch) {
diff --git a/STM32F1/variants/generic_gd32f103c/board/board.h b/STM32F1/variants/generic_gd32f103c/board/board.h
index 50dd98904..16295a11a 100644
--- a/STM32F1/variants/generic_gd32f103c/board/board.h
+++ b/STM32F1/variants/generic_gd32f103c/board/board.h
@@ -70,8 +70,8 @@
 #define BOARD_JTDO_PIN            19
 #define BOARD_NJTRST_PIN          18
 
-#define BOARD_USB_DISC_DEV        GPIOB
-#define BOARD_USB_DISC_BIT        10
+#define BOARD_USB_DISC_DEV        NULL
+#define BOARD_USB_DISC_BIT        NULL
 
 // Note this needs to match with the PIN_MAP array in board.cpp
 enum {
diff --git a/STM32F1/variants/generic_stm32f103c/board/board.h b/STM32F1/variants/generic_stm32f103c/board/board.h
index 09351a61a..4736dc9ff 100644
--- a/STM32F1/variants/generic_stm32f103c/board/board.h
+++ b/STM32F1/variants/generic_stm32f103c/board/board.h
@@ -70,8 +70,8 @@
 #define BOARD_JTDO_PIN            19
 #define BOARD_NJTRST_PIN          18
 
-#define BOARD_USB_DISC_DEV        GPIOB
-#define BOARD_USB_DISC_BIT        10
+#define BOARD_USB_DISC_DEV        NULL
+#define BOARD_USB_DISC_BIT        NULL
 
 #define LED_BUILTIN PC13
 
diff --git a/STM32F1/variants/generic_stm32f103r8/board/board.h b/STM32F1/variants/generic_stm32f103r8/board/board.h
index c274d64a7..36c224112 100644
--- a/STM32F1/variants/generic_stm32f103r8/board/board.h
+++ b/STM32F1/variants/generic_stm32f103r8/board/board.h
@@ -70,8 +70,8 @@
 #define BOARD_JTDO_PIN            19
 #define BOARD_NJTRST_PIN          18
 
-#define BOARD_USB_DISC_DEV        GPIOB
-#define BOARD_USB_DISC_BIT        10
+#define BOARD_USB_DISC_DEV        NULL
+#define BOARD_USB_DISC_BIT        NULL
 
 // Note this needs to match with the PIN_MAP array in board.cpp
 enum {
diff --git a/STM32F1/variants/nucleo_f103rb/board/board.h b/STM32F1/variants/nucleo_f103rb/board/board.h
index b27862dc3..5c7ece719 100644
--- a/STM32F1/variants/nucleo_f103rb/board/board.h
+++ b/STM32F1/variants/nucleo_f103rb/board/board.h
@@ -102,11 +102,8 @@
 /**
  * Note: there is no USB in this board.
  */
- // Roger Clark. These USB disconnect pin definitions have been added as a temporary fix in order that the this board compiles
- // following changes to add usb serial to other boards
- // I will remove them when the code in the core usb_serial.cpp has been tidied up so that they are no longer needed.
-#define BOARD_USB_DISC_DEV        GPIOB
-#define BOARD_USB_DISC_BIT        10
+#define BOARD_USB_DISC_DEV        NULL
+#define BOARD_USB_DISC_BIT        NULL
 
 /* Pin aliases: these give the GPIO port/bit for each pin as an
  * enum. These are optional, but recommended. They make it easier to

From 80339e6073d25b58ce0c8dbc0d7c5bbabb8a441f Mon Sep 17 00:00:00 2001
From: "U-MarquisSeven\\Brandon" <bmmgreen@gmail.com>
Date: Mon, 26 Jun 2017 18:57:49 -0500
Subject: [PATCH 126/307] checking out work from master

---
 STM32F1/libraries/Wire/HardWire.cpp |  6 +++++-
 STM32F1/libraries/Wire/HardWire.h   |  1 +
 STM32F1/libraries/Wire/Wire.cpp     | 22 ++++++++++++++++++++--
 STM32F1/libraries/Wire/Wire.h       |  8 +++++++-
 STM32F1/libraries/Wire/WireBase.cpp |  8 ++++++--
 STM32F1/libraries/Wire/WireBase.h   |  2 ++
 6 files changed, 41 insertions(+), 6 deletions(-)

diff --git a/STM32F1/libraries/Wire/HardWire.cpp b/STM32F1/libraries/Wire/HardWire.cpp
index 1f3ebf25e..d81f584ae 100644
--- a/STM32F1/libraries/Wire/HardWire.cpp
+++ b/STM32F1/libraries/Wire/HardWire.cpp
@@ -38,7 +38,7 @@
 
 #include "HardWire.h"
 
-uint8 HardWire::process() {
+uint8 HardWire::process(uint8 stop) {
     int8 res = i2c_master_xfer(sel_hard, &itc_msg, 1, 0);
     if (res == I2C_ERROR_PROTOCOL) {
         if (sel_hard->error_flags & I2C_SR1_AF) { /* NACK */
@@ -55,6 +55,10 @@ uint8 HardWire::process() {
     return res;
 }
 
+uint8 HardWire::process(){
+	return process(true);
+}
+
 // TODO: Add in Error Handling if devsel is out of range for other Maples
 HardWire::HardWire(uint8 dev_sel, uint8 flags) {
     if (dev_sel == 1) {
diff --git a/STM32F1/libraries/Wire/HardWire.h b/STM32F1/libraries/Wire/HardWire.h
index 6f30cb331..bf59a2f24 100644
--- a/STM32F1/libraries/Wire/HardWire.h
+++ b/STM32F1/libraries/Wire/HardWire.h
@@ -52,6 +52,7 @@ class HardWire : public WireBase {
      * Processes the incoming I2C message defined by WireBase to the
      * hardware. If an error occured, restart the I2C device.
      */
+    uint8 process(uint8);
     uint8 process();
 public:
     /*
diff --git a/STM32F1/libraries/Wire/Wire.cpp b/STM32F1/libraries/Wire/Wire.cpp
index 01ee72fd3..8e8d3e5c7 100644
--- a/STM32F1/libraries/Wire/Wire.cpp
+++ b/STM32F1/libraries/Wire/Wire.cpp
@@ -40,6 +40,9 @@
   * Updated by Roger Clark. 20141111. Fixed issue when process() returned because of missing ACK (often caused by invalid device address being used), caused SCL to be left
   * LOW so that in the next call to process() , the first clock pulse was not sent, because SCL was LOW when it should have been high.
   */
+ /*
+  * Updated by Brandon Green. 20172306. Implementing the repeated stop functionality.
+  */
 
 #include "Wire.h"
 
@@ -76,6 +79,12 @@ void TwoWire::i2c_stop() {
     set_sda(HIGH);
 }
 
+void TwoWire::i2c_repeated_start() {
+    set_sda(HIGH);
+    set_scl(HIGH);
+    set_sda(LOW);
+}
+
 bool TwoWire::i2c_get_ack() {
     set_scl(LOW);
     set_sda(HIGH);
@@ -121,7 +130,8 @@ void TwoWire::i2c_shift_out(uint8 val) {
     }
 }
 
-uint8 TwoWire::process() {
+//process needs to be updated for repeated start.
+uint8 TwoWire::process(uint8 stop) {
     itc_msg.xferred = 0;
 
     uint8 sla_addr = (itc_msg.addr << 1);
@@ -162,10 +172,18 @@ uint8 TwoWire::process() {
             itc_msg.xferred++;
         }
     }
-    i2c_stop();
+    if(stop == true)
+		i2c_stop();
+    else i2c_repeated_start();
+	
     return SUCCESS;
 }
 
+// For compatibility with legacy code
+uint8 TwoWire::process(){
+	return process(true);
+}
+
 // TODO: Add in Error Handling if pins is out of range for other Maples
 // TODO: Make delays more capable
 TwoWire::TwoWire(uint8 scl, uint8 sda, uint8 delay) : i2c_delay(delay) {
diff --git a/STM32F1/libraries/Wire/Wire.h b/STM32F1/libraries/Wire/Wire.h
index c7edfefa6..df474da7c 100644
--- a/STM32F1/libraries/Wire/Wire.h
+++ b/STM32F1/libraries/Wire/Wire.h
@@ -86,7 +86,12 @@ class TwoWire : public WireBase {
      * Creates a Stop condition on the bus
      */
     void  i2c_stop();
-
+    
+    /*
+     * Created a Repeated Start condition on the bus
+     */
+    void i2c_repeated_start();
+    
     /*
      * Gets an ACK condition from a slave device on the bus
      */
@@ -119,6 +124,7 @@ class TwoWire : public WireBase {
     /*
      * Processes the incoming I2C message defined by WireBase
      */
+    uint8 process(uint8);
     uint8 process();
  public:
     /*
diff --git a/STM32F1/libraries/Wire/WireBase.cpp b/STM32F1/libraries/Wire/WireBase.cpp
index ff0dae361..73d039836 100644
--- a/STM32F1/libraries/Wire/WireBase.cpp
+++ b/STM32F1/libraries/Wire/WireBase.cpp
@@ -59,17 +59,21 @@ void WireBase::beginTransmission(int slave_address) {
     beginTransmission((uint8)slave_address);
 }
 
-uint8 WireBase::endTransmission(void) {
+uint8 WireBase::endTransmission(uint8 stop) {
     uint8 retVal;
     if (tx_buf_overflow) {
         return EDATA;
     }
-    retVal = process();// Changed so that the return value from process is returned by this function see also the return line below
+    retVal = process(stop);// Changed so that the return value from process is returned by this function see also the return line below
     tx_buf_idx = 0;
     tx_buf_overflow = false;
     return retVal;//SUCCESS;
 }
 
+uint8 WireBase::endTransmission(){
+    endTransmission(true);
+}
+
 //TODO: Add the ability to queue messages (adding a boolean to end of function
 // call, allows for the Arduino style to stay while also giving the flexibility
 // to bulk send
diff --git a/STM32F1/libraries/Wire/WireBase.h b/STM32F1/libraries/Wire/WireBase.h
index 4e51c0deb..4038428d5 100644
--- a/STM32F1/libraries/Wire/WireBase.h
+++ b/STM32F1/libraries/Wire/WireBase.h
@@ -65,6 +65,7 @@ class WireBase { // Abstraction is awesome!
     boolean tx_buf_overflow;
 
     // Force derived classes to define process function
+    virtual uint8 process(uint8) = 0;
     virtual uint8 process() = 0;
 public:
     WireBase() {}
@@ -90,6 +91,7 @@ class WireBase { // Abstraction is awesome!
      * Call the process function to process the message if the TX
      * buffer has not overflowed.
      */
+    uint8 endTransmission(uint8);
     uint8 endTransmission(void);
 
     /*

From 54044592fb4a05149c6694d429a26b4d3a014626 Mon Sep 17 00:00:00 2001
From: "U-MarquisSeven\\Brandon" <bmmgreen@gmail.com>
Date: Mon, 26 Jun 2017 18:59:33 -0500
Subject: [PATCH 127/307] changing comment

---
 STM32F1/libraries/Wire/Wire.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/libraries/Wire/Wire.cpp b/STM32F1/libraries/Wire/Wire.cpp
index 8e8d3e5c7..fff850be8 100644
--- a/STM32F1/libraries/Wire/Wire.cpp
+++ b/STM32F1/libraries/Wire/Wire.cpp
@@ -41,7 +41,7 @@
   * LOW so that in the next call to process() , the first clock pulse was not sent, because SCL was LOW when it should have been high.
   */
  /*
-  * Updated by Brandon Green. 20172306. Implementing the repeated stop functionality.
+  * Updated by Brandon Green. 20172306. Implementing the repeated start functionality.
   */
 
 #include "Wire.h"

From f7440485833c83405dd9396f034f21a53d9ba5a7 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Sun, 2 Jul 2017 15:02:55 +0200
Subject: [PATCH 128/307] include backslashes replaced by slashes

---
 STM32F4/libraries/SDIO/SdioF4.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/STM32F4/libraries/SDIO/SdioF4.cpp b/STM32F4/libraries/SDIO/SdioF4.cpp
index 1d533a0a3..e32e9f2d6 100644
--- a/STM32F4/libraries/SDIO/SdioF4.cpp
+++ b/STM32F4/libraries/SDIO/SdioF4.cpp
@@ -19,8 +19,8 @@
  */
 
 #include "SdioF4.h"
-#include <libmaple\sdio.h>
-#include <libmaple\dma.h>
+#include <libmaple/sdio.h>
+#include <libmaple/dma.h>
 #include <boards.h>
 
 #define USE_DEBUG_MODE 0

From 753d92977ddfec1dba4344ff750c87b207f43210 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Mon, 3 Jul 2017 20:47:25 +0200
Subject: [PATCH 129/307] remove duplicated generic variant

---
 STM32F4/boards.txt | 37 -------------------------------------
 1 file changed, 37 deletions(-)

diff --git a/STM32F4/boards.txt b/STM32F4/boards.txt
index 035acc952..8fc143071 100644
--- a/STM32F4/boards.txt
+++ b/STM32F4/boards.txt
@@ -74,43 +74,6 @@ generic_f407v.menu.usb_cfg.usb_serial.build.cpu_flags=-DSERIAL_USB
 generic_f407v.menu.usb_cfg.usb_msc=USB Mass Storage (MSC)
 generic_f407v.menu.usb_cfg.usb_msc.build.cpu_flags=-DUSB_MSC
 
-##############################################################
-generic_f407v.name=Generic STM32F407V series
-
-generic_f407v.upload.tool=stlink_upload
-generic_f407v.upload.protocol=stlink
-
-generic_f407v.upload.file_type=bin
-generic_f407v.upload.ram.maximum_size=131072
-generic_f407v.upload.flash.maximum_size=514288
-generic_f407v.upload.maximum_size=514288
-
-#generic_f407v.upload.usbID=0483:3748
-#generic_f407v.upload.altID=1
-#generic_f407v.upload.auto_reset=true
-
-generic_f407v.build.mcu=cortex-m4
-generic_f407v.build.f_cpu=168000000L
-generic_f407v.build.core=maple
-generic_f407v.build.extra_flags=-mthumb -DSTM32_HIGH_DENSITY -DSTM32F4 -DBOARD_generic_f407v
-generic_f407v.build.ldscript=ld/jtag.ld
-generic_f407v.build.variant=generic_f407v
-generic_f407v.build.variant_system_lib=lib_f407.a
-generic_f407v.build.vect=VECT_TAB_BASE
-generic_f407v.build.density=STM32_HIGH_DENSITY
-generic_f407v.build.error_led_port=GPIOA
-generic_f407v.build.error_led_pin=7
-generic_f407v.build.board=STM32GenericF407VET6
-
-generic_f407v.menu.usb_cfg.usb_nc=USB inactive
-generic_f407v.menu.usb_cfg.usb_nc.build.cpu_flags=-DUSB_NC
-
-generic_f407v.menu.usb_cfg.usb_serial=USB serial (CDC)
-generic_f407v.menu.usb_cfg.usb_serial.build.cpu_flags=-DSERIAL_USB
-
-generic_f407v.menu.usb_cfg.usb_msc=USB Mass Storage (MSC)
-generic_f407v.menu.usb_cfg.usb_msc.build.cpu_flags=-DUSB_MSC
-
 ##############################################################
 stm32f4stamp.name=STM32F4Stamp F405
 

From 832f10209075e4ff4f283281a636cd2a263f3f31 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Mon, 3 Jul 2017 20:50:53 +0200
Subject: [PATCH 130/307] bring up in sync with master

---
 STM32F4/cores/maple/libmaple/dmaF4.h          | 73 -------------------
 STM32F4/cores/maple/libmaple/fsmc.c           | 57 ---------------
 STM32F4/libraries/SPI/src/SPI.cpp             |  1 +
 STM32F4/system/libmaple/Arduino.h~HEAD        | 46 ------------
 .../Arduino.h~refs_remotes_origin_master      | 46 ------------
 5 files changed, 1 insertion(+), 222 deletions(-)
 delete mode 100644 STM32F4/system/libmaple/Arduino.h~HEAD
 delete mode 100644 STM32F4/system/libmaple/Arduino.h~refs_remotes_origin_master

diff --git a/STM32F4/cores/maple/libmaple/dmaF4.h b/STM32F4/cores/maple/libmaple/dmaF4.h
index 5815f1c05..cb2376069 100644
--- a/STM32F4/cores/maple/libmaple/dmaF4.h
+++ b/STM32F4/cores/maple/libmaple/dmaF4.h
@@ -85,12 +85,7 @@ typedef struct dma_reg_map {
  * Register bit definitions
  */
 
-<<<<<<< HEAD:STM32F4/cores/maple/libmaple/dmaF4.h
-/* Stream configuration register */
-
-=======
 // Stream configuration register
->>>>>>> refs/remotes/origin/master:STM32F4/cores/maple/libmaple/dmaF4.h
 #define DMA_CR_CH0                      (0x0 << 25)
 #define DMA_CR_CH1                      (0x1 << 25)
 #define DMA_CR_CH2                      (0x2 << 25)
@@ -139,9 +134,6 @@ typedef struct dma_reg_map {
 #define DMA_CR_HTIE                     (0x1 << 3)
 #define DMA_CR_TEIE                     (0x1 << 2)
 #define DMA_CR_DMEIE                    (0x1 << 1)
-<<<<<<< HEAD:STM32F4/cores/maple/libmaple/dmaF4.h
-#define DMA_CR_EN                       (0x1)
-=======
 #define DMA_CR_EN                       (0x1 << 0)
 
 // Device interrupt status register flags
@@ -170,7 +162,6 @@ typedef struct dma_reg_map {
 #define DMA_FCR_FTH_3_4                (0x2 << 0) //  3/4 full FIFO
 #define DMA_FCR_FTH_FULL               (0x3 << 0) //  full FIFO
 
->>>>>>> refs/remotes/origin/master:STM32F4/cores/maple/libmaple/dmaF4.h
 
 typedef enum dma_channel {
     DMA_CH0 = DMA_CR_CH0,                /**< Channel 0 */
@@ -182,21 +173,6 @@ typedef enum dma_channel {
     DMA_CH6 = DMA_CR_CH6,                /**< Channel 6 */
     DMA_CH7 = DMA_CR_CH7,                /**< Channel 7 */
 } dma_channel;
-<<<<<<< HEAD:STM32F4/cores/maple/libmaple/dmaF4.h
-
-/* Device interrupt status register flags */
-
-#define DMA_ISR_TCIF    (1 << 5)
-#define DMA_ISR_HTIF    (1 << 4)
-#define DMA_ISR_TEIF    (1 << 3)
-#define DMA_ISR_DMEIF   (1 << 2)
-#define DMA_ISR_FEIF    (1 << 0)
-
-/*
- * Devices
- */
-=======
->>>>>>> refs/remotes/origin/master:STM32F4/cores/maple/libmaple/dmaF4.h
 
 /** Encapsulates state related to a DMA channel interrupt. */
 typedef struct dma_handler_config {
@@ -218,29 +194,6 @@ typedef struct dma_dev {
 /*
  * Devices
  */
-<<<<<<< HEAD:STM32F4/cores/maple/libmaple/dmaF4.h
-
-extern void dma_init(dma_dev *dev);
-
-/** Flags for DMA transfer configuration. */
-typedef enum dma_mode_flags {
-    DMA_MEM_BUF_0 = DMA_CR_CT0, /**< Current memory target buffer 0 */
-    DMA_MEM_BUF_1 = DMA_CR_CT1, /**< Current memory target buffer 1 */
-    DMA_DBL_BUF_MODE = DMA_CR_DBM,  /**< Current memory double buffer mode */
-    DMA_PINC_OFFSET  = DMA_CR_PINCOS,  /**< Peripheral increment offset size */
-    DMA_MINC_MODE  = DMA_CR_MINC,  /**< Memory increment mode */
-    DMA_PINC_MODE  = DMA_CR_PINC,  /**< Peripheral increment mode */
-    DMA_CIRC_MODE  = DMA_CR_CIRC,  /**< Memory Circular mode */
-    DMA_FROM_PER   = DMA_CR_DIR_P2M,  /**< Read from memory to peripheral */
-    DMA_FROM_MEM   = DMA_CR_DIR_M2P,  /**< Read from memory to peripheral */
-    DMA_MEM_TO_MEM = DMA_CR_DIR_M2M,  /**< Read from memory to memory */
-    DMA_PERIF_CTRL   = DMA_CR_PFCTRL,  /**< Peripheral flow controller */
-    DMA_PRIO_MEDIUM    = DMA_CR_PL_MEDIUM,    /**< Medium priority */
-    DMA_PRIO_HIGH      = DMA_CR_PL_HIGH,      /**< High priority */
-    DMA_PRIO_VERY_HIGH = DMA_CR_PL_VERY_HIGH, /**< Very high priority */
-    DMA_TRNS_CMPLT   = DMA_CR_TCIE,   /**< Interrupt on transfer completion */
-    DMA_TRNS_HALF    = DMA_CR_HTIE,  /**< Interrupt on half-transfer */
-=======
 extern dma_dev *DMA1;
 extern dma_dev *DMA2;
 
@@ -262,22 +215,15 @@ typedef enum dma_mode_flags {
     DMA_PRIO_VERY_HIGH = DMA_CR_PL_VERY_HIGH, /**< Very high priority */
     DMA_TRNS_CMPLT     = DMA_CR_TCIE,   /**< Interrupt on transfer completion */
     DMA_TRNS_HALF      = DMA_CR_HTIE,  /**< Interrupt on half-transfer */
->>>>>>> refs/remotes/origin/master:STM32F4/cores/maple/libmaple/dmaF4.h
     DMA_TRNS_ERR       = DMA_CR_TEIE,  /**< Interrupt on transfer error */
     DMA_DIR_MODE_ERR   = DMA_CR_DMEIE  /**< Interrupt on direct mode error */
 } dma_mode_flags;
 
 // Source and destination transfer sizes.
 typedef enum dma_xfer_size {
-<<<<<<< HEAD:STM32F4/cores/maple/libmaple/dmaF4.h
-    DMA_SIZE_8BITS  = ( DMA_CR_MSIZE_8BITS|DMA_CR_PSIZE_8BITS ),        /**< 8-bit transfers */
-    DMA_SIZE_16BITS = (DMA_CR_MSIZE_16BITS|DMA_CR_PSIZE_16BITS),        /**< 16-bit transfers */
-    DMA_SIZE_32BITS = (DMA_CR_MSIZE_32BITS|DMA_CR_PSIZE_32BITS)         /**< 32-bit transfers */
-=======
     DMA_SIZE_8BITS  = ( DMA_CR_MSIZE_8BITS|DMA_CR_PSIZE_8BITS ),  // 8-bit transfers
     DMA_SIZE_16BITS = (DMA_CR_MSIZE_16BITS|DMA_CR_PSIZE_16BITS),  // 16-bit transfers
     DMA_SIZE_32BITS = (DMA_CR_MSIZE_32BITS|DMA_CR_PSIZE_32BITS)   // 32-bit transfers
->>>>>>> refs/remotes/origin/master:STM32F4/cores/maple/libmaple/dmaF4.h
 } dma_xfer_size;
 
 // Source and destination burst sizes.
@@ -312,22 +258,14 @@ static inline void dma_setup_transfer(dma_dev       *dev,
                                       __io void     *peripheral_address,
                                       __io void     *memory_address0,
                                       __io void     *memory_address1,
-<<<<<<< HEAD:STM32F4/cores/maple/libmaple/dmaF4.h
-                                      uint32        flags) {
-=======
                                       uint32        flags)
 {
->>>>>>> refs/remotes/origin/master:STM32F4/cores/maple/libmaple/dmaF4.h
     dev->regs->STREAM[stream].CR &= ~DMA_CR_EN; // disable
 	while( (dev->regs->STREAM[stream].CR)&DMA_CR_EN ); // wait till enable bit is cleared
     dev->regs->STREAM[stream].PAR = (uint32)peripheral_address;
     dev->regs->STREAM[stream].M0AR = (uint32)memory_address0;
     dev->regs->STREAM[stream].M1AR = (uint32)memory_address1;
-<<<<<<< HEAD:STM32F4/cores/maple/libmaple/dmaF4.h
-    dev->regs->STREAM[stream].CR = ((flags|channel|trx_size) & 0x0feffffe); // mask out reserved and enable
-=======
     dev->regs->STREAM[stream].CR = (uint32)((flags|channel|trx_size) & 0x0feffffe); // mask out reserved and enable
->>>>>>> refs/remotes/origin/master:STM32F4/cores/maple/libmaple/dmaF4.h
 }
     
 static inline void dma_set_num_transfers(dma_dev *dev, dma_stream stream, uint16 num_transfers)
@@ -340,12 +278,6 @@ static inline void dma_set_fifo_flags(dma_dev *dev, dma_stream stream, uint8 fif
     dev->regs->STREAM[stream].FCR = (uint32)(fifo_flags & 0x87); // mask out reserved bits
 }
 
-static inline void dma_set_fifo_flags(dma_dev *dev,
-                                      dma_stream stream,
-                                      uint8 fifo_flags) {
-    dev->regs->STREAM[stream].FCR = fifo_flags & 0x87; // mask out reserved bits
-}
-
 void dma_attach_interrupt(dma_dev *dev,
                           dma_stream stream,
                           void (*handler)(void));
@@ -357,14 +289,9 @@ static inline void dma_enable(dma_dev *dev, dma_stream stream)
     dev->regs->STREAM[stream].CR |= (uint32)DMA_CR_EN;
 }    
 
-<<<<<<< HEAD:STM32F4/cores/maple/libmaple/dmaF4.h
-static inline void dma_disable(dma_dev *dev, dma_stream stream) {
-    dev->regs->STREAM[stream].CR &= ~DMA_CR_EN;
-=======
 static inline void dma_disable(dma_dev *dev, dma_stream stream)
 {
     dev->regs->STREAM[stream].CR &= (uint32)(~DMA_CR_EN);
->>>>>>> refs/remotes/origin/master:STM32F4/cores/maple/libmaple/dmaF4.h
 	while (dev->regs->STREAM[stream].CR & DMA_CR_EN); // wait till EN bit is reset, see AN4031, chapter 4.1
 }    
 
diff --git a/STM32F4/cores/maple/libmaple/fsmc.c b/STM32F4/cores/maple/libmaple/fsmc.c
index 301a855c4..1e3691adf 100644
--- a/STM32F4/cores/maple/libmaple/fsmc.c
+++ b/STM32F4/cores/maple/libmaple/fsmc.c
@@ -37,62 +37,6 @@
 /**
  * Configure FSMC GPIOs for use with LCDs.
  */
-<<<<<<< HEAD
-void fsmc_sram_init_gpios(void) {
-    /* Data lines... */
-    gpio_set_mode(PD0, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PD1, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PD8, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PD9, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PD10, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PD14, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PD15, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE7, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE8, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE9, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE10, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE11, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE12, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE13, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE14, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PE15, GPIO_AF_OUTPUT_PP);
-
-    /* Address lines... */
-    gpio_set_mode(PD11, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PD12, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(PD13, GPIO_AF_OUTPUT_PP);
-#if 0 // not available on LQFP package
-    gpio_set_mode(GPIOF,  0, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF,  1, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF,  2, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF,  3, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF,  4, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF,  5, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF, 12, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF, 13, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF, 14, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOF, 15, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOG,  0, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOG,  1, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOG,  2, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOG,  3, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOG,  4, GPIO_AF_OUTPUT_PP);
-    gpio_set_mode(GPIOG,  5, GPIO_AF_OUTPUT_PP);
-#endif  // not available on LQFP package
-    /* And control lines... */
-    gpio_set_mode(PD4, GPIO_AF_OUTPUT_PP);   // NOE
-    gpio_set_mode(PD5, GPIO_AF_OUTPUT_PP);   // NWE
-
-    gpio_set_mode(PD7, GPIO_AF_OUTPUT_PP);   // NE1
-#if 0 // not available on LQFP package
-    gpio_set_mode(GPIOG,  9, GPIO_AF_OUTPUT_PP);   // NE2
-    gpio_set_mode(GPIOG, 10, GPIO_AF_OUTPUT_PP);   // NE3
-    gpio_set_mode(GPIOG, 12, GPIO_AF_OUTPUT_PP);   // NE4
-#endif  // not available on LQFP package
-
-    gpio_set_mode(PE0, GPIO_AF_OUTPUT_PP);   // NBL0
-    gpio_set_mode(PE1, GPIO_AF_OUTPUT_PP);   // NBL1
-=======
 
 void fsmc_init(void) {
     rcc_clk_enable(RCC_FSMC);
@@ -137,7 +81,6 @@ void fsmc_lcd_init(void)
 	fsmc_nor_psram_set_BTR(FSMC_NOR_PSRAM1_BASE, val);
 	// enable FSCM
 	fsmc_nor_psram_bank_enable(FSMC_NOR_PSRAM1_BASE);
->>>>>>> refs/remotes/origin/master
 }
 
 
diff --git a/STM32F4/libraries/SPI/src/SPI.cpp b/STM32F4/libraries/SPI/src/SPI.cpp
index eb07c8f1e..63ed4db65 100644
--- a/STM32F4/libraries/SPI/src/SPI.cpp
+++ b/STM32F4/libraries/SPI/src/SPI.cpp
@@ -460,6 +460,7 @@ uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length
 	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaStream) & DMA_ISR_TCIF)==0 ) {// wait for completion flag to be set
 		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
     }
+
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
 	// software disable sequence, see AN4031, chapter 4.1
diff --git a/STM32F4/system/libmaple/Arduino.h~HEAD b/STM32F4/system/libmaple/Arduino.h~HEAD
deleted file mode 100644
index cef8f089f..000000000
--- a/STM32F4/system/libmaple/Arduino.h~HEAD
+++ /dev/null
@@ -1,46 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 LeafLabs LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-#ifndef _WIRISH_ARDUINO_H_
-#define _WIRISH_ARDUINO_H_
-
-//#warning Include Arduino.h from system\libmaple
-
-#include "wirish.h"
-
-void setup();
-void loop();
-#ifdef __cplusplus
-extern "C"{
-#endif // __cplusplus
-void yield(void);
-#ifdef __cplusplus
-}
-#endif // __cplusplus
-
-#include "variant.h"
-
-#endif
diff --git a/STM32F4/system/libmaple/Arduino.h~refs_remotes_origin_master b/STM32F4/system/libmaple/Arduino.h~refs_remotes_origin_master
deleted file mode 100644
index cef8f089f..000000000
--- a/STM32F4/system/libmaple/Arduino.h~refs_remotes_origin_master
+++ /dev/null
@@ -1,46 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 LeafLabs LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-#ifndef _WIRISH_ARDUINO_H_
-#define _WIRISH_ARDUINO_H_
-
-//#warning Include Arduino.h from system\libmaple
-
-#include "wirish.h"
-
-void setup();
-void loop();
-#ifdef __cplusplus
-extern "C"{
-#endif // __cplusplus
-void yield(void);
-#ifdef __cplusplus
-}
-#endif // __cplusplus
-
-#include "variant.h"
-
-#endif

From 66df08b6bb1c6c5559531b5af4994a1b567faf00 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Mon, 3 Jul 2017 20:59:56 +0200
Subject: [PATCH 131/307] update .gitignore

---
 .gitignore | 2 --
 1 file changed, 2 deletions(-)

diff --git a/.gitignore b/.gitignore
index 6ef98005c..078faf600 100644
--- a/.gitignore
+++ b/.gitignore
@@ -6,7 +6,5 @@ other/maple-bootloader/cscope.out
 other/maple-bootloader/build
 other/maple-bootloader/*~
 *.o
-tools/src/stm32flash_serial/src/parsers/parsers.a
 *.bak
 *.1
-STM32F4/cores/maple/libmaple/adc.h

From 85f8b8237af7f580fbcd823e42d4ba4e9c530b58 Mon Sep 17 00:00:00 2001
From: Testato <Testato@users.noreply.github.com>
Date: Tue, 4 Jul 2017 10:05:01 +0200
Subject: [PATCH 132/307] Update boards.txt

- Exluded CCM Ram
---
 STM32F4/boards.txt | 9 ++++-----
 1 file changed, 4 insertions(+), 5 deletions(-)

diff --git a/STM32F4/boards.txt b/STM32F4/boards.txt
index 0df9990dd..60d4fc473 100644
--- a/STM32F4/boards.txt
+++ b/STM32F4/boards.txt
@@ -11,7 +11,7 @@ discovery_f407.upload.protocol=stlink
 #discovery_f407.upload.use_1200bps_touch=false
 discovery_f407.upload.file_type=bin
 discovery_f407.upload.maximum_size=1048576
-discovery_f407.upload.maximum_data_size=196608
+discovery_f407.upload.maximum_data_size=131072
 
 #discovery_f407.upload.usbID=1EAF:0003
 #discovery_f407.upload.altID=1
@@ -43,9 +43,8 @@ generic_f407v.upload.tool=stlink_upload
 generic_f407v.upload.protocol=stlink
 
 generic_f407v.upload.file_type=bin
-generic_f407v.upload.ram.maximum_size=131072
-generic_f407v.upload.flash.maximum_size=514288
 generic_f407v.upload.maximum_size=514288
+generic_f407v.upload.ram.maximum_size=131072
 
 #generic_f407v.upload.usbID=0483:3748
 #generic_f407v.upload.altID=1
@@ -82,7 +81,7 @@ stm32f4stamp.upload.protocol=maple_dfu
 #stm32f4stamp.upload.use_1200bps_touch=false
 stm32f4stamp.upload.file_type=bin
 stm32f4stamp.upload.maximum_size=1048576
-stm32f4stamp.upload.maximum_data_size=196608
+stm32f4stamp.upload.maximum_data_size=131072
 
 stm32f4stamp.upload.usbID=0483:df11
 stm32f4stamp.upload.altID=0
@@ -117,7 +116,7 @@ netduino2plus.upload.protocol=maple_dfu
 #netduino2plus.upload.use_1200bps_touch=false
 netduino2plus.upload.file_type=bin
 netduino2plus.upload.maximum_size=1048576
-netduino2plus.upload.maximum_data_size=196608
+netduino2plus.upload.maximum_data_size=131072
 
 netduino2plus.upload.usbID=0483:df11
 netduino2plus.upload.altID=0

From 4467592149551b87e2c31f82658feb6f20c108e8 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Tue, 4 Jul 2017 19:11:48 +0200
Subject: [PATCH 133/307] adapt flash and RAM maximum sizes for Arduino

---
 STM32F4/boards.txt | 9 +++------
 1 file changed, 3 insertions(+), 6 deletions(-)

diff --git a/STM32F4/boards.txt b/STM32F4/boards.txt
index 8fc143071..514c8a564 100644
--- a/STM32F4/boards.txt
+++ b/STM32F4/boards.txt
@@ -10,9 +10,8 @@ discovery_f407.upload.protocol=stlink
 
 #discovery_f407.upload.use_1200bps_touch=false
 discovery_f407.upload.file_type=bin
-discovery_f407.upload.ram.maximum_size=17000
-discovery_f407.upload.flash.maximum_size=1048576
 discovery_f407.upload.maximum_size=1048576
+discovery_f407.upload.maximum_data_size=131072
 
 #discovery_f407.upload.usbID=1EAF:0003
 #discovery_f407.upload.altID=1
@@ -44,9 +43,8 @@ generic_f407v.upload.tool=stlink_upload
 generic_f407v.upload.protocol=stlink
 
 generic_f407v.upload.file_type=bin
-generic_f407v.upload.ram.maximum_size=131072
-generic_f407v.upload.flash.maximum_size=514288
 generic_f407v.upload.maximum_size=514288
+generic_f407v.upload.maximum_data_size=131072
 
 #generic_f407v.upload.usbID=0483:3748
 #generic_f407v.upload.altID=1
@@ -82,9 +80,8 @@ stm32f4stamp.upload.protocol=maple_dfu
 
 #stm32f4stamp.upload.use_1200bps_touch=false
 stm32f4stamp.upload.file_type=bin
-stm32f4stamp.upload.ram.maximum_size=196608
-stm32f4stamp.upload.flash.maximum_size=1048576
 stm32f4stamp.upload.maximum_size=1048576
+stm32f4stamp.upload.maximum_data_size=131072
 
 stm32f4stamp.upload.usbID=0483:df11
 stm32f4stamp.upload.altID=0

From 9b30346bfa379df4fd41c4985650a14c674a9c76 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Tue, 4 Jul 2017 19:13:20 +0200
Subject: [PATCH 134/307] default activated SPI class - needed by external libs

---
 STM32F4/libraries/SPI/src/SPI.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F4/libraries/SPI/src/SPI.cpp b/STM32F4/libraries/SPI/src/SPI.cpp
index 63ed4db65..45aa366b2 100644
--- a/STM32F4/libraries/SPI/src/SPI.cpp
+++ b/STM32F4/libraries/SPI/src/SPI.cpp
@@ -651,4 +651,4 @@ static spi_baud_rate determine_baud_rate(spi_dev *dev, uint32_t freq) {
 }
 
 
-//SPIClass SPI(3);
+SPIClass SPI(3); // needed for external libs

From 597f77ac1d2824ebe369fc33b500cd9358d5d6db Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Tue, 4 Jul 2017 19:28:50 +0200
Subject: [PATCH 135/307] replace all backslaches by slashes in include paths

---
 STM32F4/cores/maple/libmaple/fsmc.h                    |  2 +-
 .../Class/audio/inc/usbd_audio_core.h                  |  2 +-
 .../Class/cdc/inc/usbd_cdc_core.h                      |  4 ++--
 .../Class/cdc/src/usbd_cdc_core.c                      |  8 ++++----
 .../STM32_USB_Device_Library/Core/inc/usbd_core.h      |  2 +-
 .../usbF4/STM32_USB_Device_Library/Core/inc/usbd_def.h |  2 +-
 .../usbF4/STM32_USB_Device_Library/Core/inc/usbd_req.h |  2 +-
 .../STM32_USB_Device_Library/Core/src/usbd_core.c      | 10 +++++-----
 .../STM32_USB_Device_Library/Core/src/usbd_ioreq.c     |  2 +-
 .../usbF4/STM32_USB_Device_Library/Core/src/usbd_req.c |  6 +++---
 .../libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_core.h |  2 +-
 .../usbF4/STM32_USB_OTG_Driver/inc/usb_defines.h       |  2 +-
 .../libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_regs.h |  4 ++--
 .../libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_core.c |  4 ++--
 .../libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd.c  |  4 ++--
 .../usbF4/STM32_USB_OTG_Driver/src/usb_dcd_int.c       |  4 ++--
 STM32F4/cores/maple/libmaple/usbF4/VCP/usb_bsp.c       |  2 +-
 STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.h  |  2 +-
 STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.c     |  6 +++---
 STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.h     |  2 +-
 STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_usr.c      |  4 ++--
 STM32F4/cores/maple/libmaple/usbF4/usb.c               |  6 +++---
 STM32F4/cores/maple/libmaple/usbF4/usb.h               |  2 +-
 STM32F4/system/libmaple/Arduino.h                      |  1 -
 STM32F4/variants/discovery_f407/discovery_f4.cpp       |  4 ++--
 STM32F4/variants/generic_f407v/pin_map.c               |  6 +++---
 26 files changed, 47 insertions(+), 48 deletions(-)

diff --git a/STM32F4/cores/maple/libmaple/fsmc.h b/STM32F4/cores/maple/libmaple/fsmc.h
index 3501583b4..03a6acfce 100644
--- a/STM32F4/cores/maple/libmaple/fsmc.h
+++ b/STM32F4/cores/maple/libmaple/fsmc.h
@@ -40,7 +40,7 @@
 #ifndef _FSMC_H_
 #define _FSMC_H_
 
-#include <libmaple\util.h>
+#include <libmaple/util.h>
 #include "libmaple_types.h"
 
 #ifdef __cplusplus
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_core.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_core.h
index 7ac987dcb..69f7ffaaa 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_core.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/audio/inc/usbd_audio_core.h
@@ -26,7 +26,7 @@
 
 #include "usbd_ioreq.h"
 #include "usbd_req.h"
-#include <VCP\usbd_desc.h>
+#include <VCP/usbd_desc.h>
 
 
 
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h
index b1c8cc117..29a38e96d 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h
@@ -24,8 +24,8 @@
 #ifndef __USB_CDC_CORE_H_
 #define __USB_CDC_CORE_H_
 
-#include <STM32_USB_Device_Library\Core\inc/usbd_ioreq.h>
-#include <STM32_USB_OTG_Driver\inc\usb_core.h>
+#include <STM32_USB_Device_Library/Core/inc/usbd_ioreq.h>
+#include <STM32_USB_OTG_Driver/inc/usb_core.h>
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_core.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_core.c
index 8f97c5176..8963a8a2a 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_core.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Class/cdc/src/usbd_cdc_core.c
@@ -58,10 +58,10 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include <VCP\usb_conf.h>
-#include <STM32_USB_Device_Library\Class\cdc\inc\usbd_cdc_core.h>
-#include <VCP\usbd_desc.h>
-#include <STM32_USB_Device_Library\Core\inc\usbd_req.h>
+#include <VCP/usb_conf.h>
+#include <STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h>
+#include <VCP/usbd_desc.h>
+#include <STM32_USB_Device_Library/Core/inc/usbd_req.h>
 
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_core.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_core.h
index 063a30e69..3e4db9b33 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_core.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_core.h
@@ -26,7 +26,7 @@
 /* Includes ------------------------------------------------------------------*/
 #include <STM32_USB_OTG_Driver/inc/usb_dcd.h>
 #include "usbd_def.h"
-#include <VCP\usbd_conf.h>
+#include <VCP/usbd_conf.h>
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_def.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_def.h
index f2a31153a..03a8afc9d 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_def.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_def.h
@@ -24,7 +24,7 @@
 #ifndef __USBD_DEF_H
 #define __USBD_DEF_H
 /* Includes ------------------------------------------------------------------*/
-#include <VCP\usbd_conf.h>
+#include <VCP/usbd_conf.h>
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_req.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_req.h
index f9849c6f9..fd3c05561 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_req.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/inc/usbd_req.h
@@ -27,7 +27,7 @@
 /* Includes ------------------------------------------------------------------*/
 #include  "usbd_def.h"
 #include  "usbd_core.h"
-#include  <VCP\usbd_conf.h>
+#include  <VCP/usbd_conf.h>
 
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_core.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_core.c
index 00bb25140..2c5e82206 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_core.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_core.c
@@ -20,11 +20,11 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include <STM32_USB_Device_Library\Core\inc\usbd_core.h>
-#include <STM32_USB_Device_Library\Core\inc\usbd_req.h>
-#include <STM32_USB_Device_Library\Core\inc\usbd_ioreq.h>
-#include <STM32_USB_OTG_Driver\inc\usb_dcd_int.h>
-#include <STM32_USB_OTG_Driver\inc\usb_bsp.h>
+#include <STM32_USB_Device_Library/Core/inc/usbd_core.h>
+#include <STM32_USB_Device_Library/Core/inc/usbd_req.h>
+#include <STM32_USB_Device_Library/Core/inc/usbd_ioreq.h>
+#include <STM32_USB_OTG_Driver/inc/usb_dcd_int.h>
+#include <STM32_USB_OTG_Driver/inc/usb_bsp.h>
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
 * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_ioreq.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_ioreq.c
index 20ee5a0f1..620b9e5cf 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_ioreq.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_ioreq.c
@@ -20,7 +20,7 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include <STM32_USB_Device_Library\Core\inc\usbd_ioreq.h>
+#include <STM32_USB_Device_Library/Core/inc/usbd_ioreq.h>
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
   * @{
   */
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_req.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_req.c
index 5fc2e036c..2233d1504 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_req.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_Device_Library/Core/src/usbd_req.c
@@ -20,9 +20,9 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include <STM32_USB_Device_Library\Core\inc\usbd_req.h>
-#include <STM32_USB_Device_Library\Core\inc\usbd_ioreq.h>
-#include <VCP\usbd_desc.h>
+#include <STM32_USB_Device_Library/Core/inc/usbd_req.h>
+#include <STM32_USB_Device_Library/Core/inc/usbd_ioreq.h>
+#include <VCP/usbd_desc.h>
 
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_core.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_core.h
index 43c478126..dd6a86ad2 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_core.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_core.h
@@ -24,7 +24,7 @@
 #define __USB_CORE_H__
 
 /* Includes ------------------------------------------------------------------*/
-#include <VCP\usbd_conf.h>
+#include <VCP/usbd_conf.h>
 #include "usb_regs.h"
 #include "usb_defines.h"
 
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_defines.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_defines.h
index ee2c1a009..546f5ab8b 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_defines.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_defines.h
@@ -24,7 +24,7 @@
 #define __USB_DEF_H__
 
 /* Includes ------------------------------------------------------------------*/
-#include  <VCP\usbd_conf.h>
+#include  <VCP/usbd_conf.h>
 
 /** @addtogroup USB_OTG_DRIVER
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_regs.h b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_regs.h
index 99f844e58..3038f0d86 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_regs.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/inc/usb_regs.h
@@ -24,8 +24,8 @@
 #define __USB_OTG_REGS_H__
 
 /* Includes ------------------------------------------------------------------*/
-#include <VCP\usbd_conf.h>
-#include <libmaple\libmaple_types.h>
+#include <VCP/usbd_conf.h>
+#include <libmaple/libmaple_types.h>
 
 /** @addtogroup USB_OTG_DRIVER
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_core.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_core.c
index 1687afa7c..dd3856f12 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_core.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_core.c
@@ -20,8 +20,8 @@
   */
 
 /* Includes ------------------------------------------------------------------*/
-#include <STM32_USB_OTG_Driver\inc\usb_bsp.h>
-#include <STM32_USB_OTG_Driver\inc\usb_core.h>
+#include <STM32_USB_OTG_Driver/inc/usb_bsp.h>
+#include <STM32_USB_OTG_Driver/inc/usb_core.h>
 
 
 /** @addtogroup USB_OTG_DRIVER
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd.c
index dc9e53839..0d23a9769 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd.c
@@ -20,8 +20,8 @@
   */
 
 /* Includes ------------------------------------------------------------------*/
-#include <STM32_USB_OTG_Driver\inc\usb_dcd.h>
-#include <STM32_USB_OTG_Driver\inc\usb_bsp.h>
+#include <STM32_USB_OTG_Driver/inc/usb_dcd.h>
+#include <STM32_USB_OTG_Driver/inc/usb_bsp.h>
 
 
 /** @addtogroup USB_OTG_DRIVER
diff --git a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd_int.c b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd_int.c
index f9e561f14..fb3bb9d44 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd_int.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/STM32_USB_OTG_Driver/src/usb_dcd_int.c
@@ -20,12 +20,12 @@
   */
 
 /* Includes ------------------------------------------------------------------*/
-#include <STM32_USB_OTG_Driver\inc\usb_dcd_int.h>
+#include <STM32_USB_OTG_Driver/inc/usb_dcd_int.h>
 
 typedef int IRQn_Type;
 #define __NVIC_PRIO_BITS          4
 #define __Vendor_SysTickConfig    1
-#include <VCP\core_cm4.h>
+#include <VCP/core_cm4.h>
 
 
 /** @addtogroup USB_OTG_DRIVER
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_bsp.c b/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_bsp.c
index e794cb144..c3650384c 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_bsp.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usb_bsp.c
@@ -21,7 +21,7 @@
   */
 
 /* Includes ------------------------------------------------------------------*/
-#include <STM32_USB_OTG_Driver\inc\usb_bsp.h>
+#include <STM32_USB_OTG_Driver/inc/usb_bsp.h>
 #include "usbd_conf.h"
 #include <libmaple/gpio.h>
 typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.h b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.h
index 8398dbdbb..1ac6c2fb3 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_cdc_vcp.h
@@ -26,7 +26,7 @@
 /* Includes ------------------------------------------------------------------*/
 //#include "stm32f4xx.h"
 
-#include <STM32_USB_Device_Library\Class\cdc\inc\usbd_cdc_core.h>
+#include <STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h>
 #include "usbd_conf.h"
 
 
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.c b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.c
index 0153858fc..e37e28c72 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.c
@@ -20,11 +20,11 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include <STM32_USB_Device_Library\Core\inc\usbd_core.h>
+#include <STM32_USB_Device_Library/Core/inc/usbd_core.h>
 #include "usbd_desc.h"
-#include <STM32_USB_Device_Library\Core\inc\usbd_req.h>
+#include <STM32_USB_Device_Library/Core/inc/usbd_req.h>
 #include "usbd_conf.h"
-#include <STM32_USB_OTG_Driver\inc\usb_regs.h>
+#include <STM32_USB_OTG_Driver/inc/usb_regs.h>
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.h b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.h
index 4ae998cee..987767ff2 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_desc.h
@@ -25,7 +25,7 @@
 #define __USB_DESC_H
 
 /* Includes ------------------------------------------------------------------*/
-#include <STM32_USB_Device_Library\Core\inc\usbd_def.h>
+#include <STM32_USB_Device_Library/Core/inc/usbd_def.h>
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
   * @{
diff --git a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_usr.c b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_usr.c
index a16ce40c5..44eef15e1 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_usr.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/VCP/usbd_usr.c
@@ -20,8 +20,8 @@
   */ 
 
 /* Includes ------------------------------------------------------------------*/
-#include <STM32_USB_Device_Library\Core\inc\usbd_usr.h>
-#include <STM32_USB_Device_Library\Core\inc\usbd_ioreq.h>
+#include <STM32_USB_Device_Library/Core/inc/usbd_usr.h>
+#include <STM32_USB_Device_Library/Core/inc/usbd_ioreq.h>
 
 
 /** @addtogroup STM32_USB_OTG_DEVICE_LIBRARY
diff --git a/STM32F4/cores/maple/libmaple/usbF4/usb.c b/STM32F4/cores/maple/libmaple/usbF4/usb.c
index 385071982..3e9218609 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/usb.c
+++ b/STM32F4/cores/maple/libmaple/usbF4/usb.c
@@ -4,11 +4,11 @@
 
 #include <STM32_USB_Device_Library/Class/cdc/inc/usbd_cdc_core.h>
 #include <STM32_USB_Device_Library/Core/inc/usbd_usr.h>
-#include <VCP\usbd_desc.h>
+#include <VCP/usbd_desc.h>
 #include "usb.h"
 #include <libmaple/gpio.h>
 #include <libmaple/rccF4.h>
-#include <VCP\usbd_cdc_vcp.h>
+#include <VCP/usbd_cdc_vcp.h>
 #include <boards.h>
 
 USB_OTG_CORE_HANDLE  USB_OTG_dev;
@@ -96,7 +96,7 @@ RESULT usbPowerOff(void) {
 
 void usbDsbISR(void) {};
 
-#include <STM32_USB_OTG_Driver\inc\usb_dcd_int.h>
+#include <STM32_USB_OTG_Driver/inc/usb_dcd_int.h>
 void __irq_OTG_FS_IRQHandler(void)
 {
   USBD_OTG_ISR_Handler (&USB_OTG_dev);
diff --git a/STM32F4/cores/maple/libmaple/usbF4/usb.h b/STM32F4/cores/maple/libmaple/usbF4/usb.h
index ce1a5585f..7f0b2aa7e 100644
--- a/STM32F4/cores/maple/libmaple/usbF4/usb.h
+++ b/STM32F4/cores/maple/libmaple/usbF4/usb.h
@@ -5,7 +5,7 @@
 extern "C" {
 #endif
 
-#include <VCP\usb_conf.h>
+#include <VCP/usb_conf.h>
 
 typedef enum _RESULT
 {
diff --git a/STM32F4/system/libmaple/Arduino.h b/STM32F4/system/libmaple/Arduino.h
index cef8f089f..d445126b0 100644
--- a/STM32F4/system/libmaple/Arduino.h
+++ b/STM32F4/system/libmaple/Arduino.h
@@ -27,7 +27,6 @@
 #ifndef _WIRISH_ARDUINO_H_
 #define _WIRISH_ARDUINO_H_
 
-//#warning Include Arduino.h from system\libmaple
 
 #include "wirish.h"
 
diff --git a/STM32F4/variants/discovery_f407/discovery_f4.cpp b/STM32F4/variants/discovery_f407/discovery_f4.cpp
index 74660f0b9..7d288d583 100644
--- a/STM32F4/variants/discovery_f407/discovery_f4.cpp
+++ b/STM32F4/variants/discovery_f407/discovery_f4.cpp
@@ -34,8 +34,8 @@
 
 #include "discovery_f4.h"
 
-#include <libmaple\gpio.h>
-#include <libmaple\rcc.h>
+#include <libmaple/gpio.h>
+#include <libmaple/rcc.h>
 
 #include "wirish_types.h"
 
diff --git a/STM32F4/variants/generic_f407v/pin_map.c b/STM32F4/variants/generic_f407v/pin_map.c
index 5ecde5367..db5247b02 100644
--- a/STM32F4/variants/generic_f407v/pin_map.c
+++ b/STM32F4/variants/generic_f407v/pin_map.c
@@ -39,9 +39,9 @@ extern "C"{
 //#include "generic_f407v.h"
 
 //#include "fsmc.h"
-#include <libmaple\gpio.h>
-#include <libmaple\rcc.h>
-#include <libmaple\timer.h>
+#include <libmaple/gpio.h>
+#include <libmaple/rcc.h>
+#include <libmaple/timer.h>
 
 #include <wirish_types.h>
 

From 8f46bf3c9e3a5c575eb9850ad0285d4189514664 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Tue, 4 Jul 2017 20:09:11 +0200
Subject: [PATCH 136/307] remove leaflasb USB CDC ACM warning

---
 STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c b/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c
index 774be42cb..cba050f54 100644
--- a/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c
+++ b/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c
@@ -62,8 +62,8 @@
 
 #if !(defined(BOARD_maple) || defined(BOARD_maple_RET6) ||      \
       defined(BOARD_maple_mini) || defined(BOARD_maple_native))
-#warning USB CDC ACM relies on LeafLabs board-specific configuration.\
-    You may have problems on non-LeafLabs boards.
+//#warning USB CDC ACM relies on LeafLabs board-specific configuration.\
+//    You may have problems on non-LeafLabs boards.
 #endif
 
 static void vcomDataTxCb(void);

From 6fcecec2b02f96791041257850a18fa20d1400c8 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Tue, 4 Jul 2017 20:20:14 +0200
Subject: [PATCH 137/307] remove compiler warning about passing NULL to
 non-pointer argument

---
 STM32F1/cores/maple/usb_serial.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/STM32F1/cores/maple/usb_serial.cpp b/STM32F1/cores/maple/usb_serial.cpp
index 1fe2bf48e..6cffbf573 100644
--- a/STM32F1/cores/maple/usb_serial.cpp
+++ b/STM32F1/cores/maple/usb_serial.cpp
@@ -71,7 +71,7 @@ void USBSerial::begin(void) {
         return;
     _hasBegun = true;
 
-    usb_cdcacm_enable(BOARD_USB_DISC_DEV, BOARD_USB_DISC_BIT);
+    usb_cdcacm_enable(BOARD_USB_DISC_DEV, (uint8_t)BOARD_USB_DISC_BIT);
     usb_cdcacm_set_hooks(USB_CDCACM_HOOK_RX, rxHook);
     usb_cdcacm_set_hooks(USB_CDCACM_HOOK_IFACE_SETUP, ifaceSetupHook);
 #endif
@@ -97,7 +97,7 @@ volatile uint8_t removeCompilerWarningsIgnore=ignore;
 
 void USBSerial::end(void) {
 #if BOARD_HAVE_SERIALUSB
-    usb_cdcacm_disable(BOARD_USB_DISC_DEV, BOARD_USB_DISC_BIT);
+    usb_cdcacm_disable(BOARD_USB_DISC_DEV, (uint8_t)BOARD_USB_DISC_BIT);
     usb_cdcacm_remove_hooks(USB_CDCACM_HOOK_RX | USB_CDCACM_HOOK_IFACE_SETUP);
 	_hasBegun = false;
 #endif

From 6f2effadac3d703b45fe4c4cbacba79df544ebfb Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Thu, 6 Jul 2017 00:29:45 +0200
Subject: [PATCH 138/307] update SdioF4.cpp - fix for CL4 cards

---
 STM32F4/libraries/SDIO/SdioF4.cpp | 33 ++++++++++++++++++++++++-------
 1 file changed, 26 insertions(+), 7 deletions(-)

diff --git a/STM32F4/libraries/SDIO/SdioF4.cpp b/STM32F4/libraries/SDIO/SdioF4.cpp
index e32e9f2d6..63c928a80 100644
--- a/STM32F4/libraries/SDIO/SdioF4.cpp
+++ b/STM32F4/libraries/SDIO/SdioF4.cpp
@@ -24,11 +24,12 @@
 #include <boards.h>
 
 #define USE_DEBUG_MODE 0
+#define USE_YIELD 0
 
 //==============================================================================
 //#define SDHC_PROCTL_DTW_4BIT 0x01
 #define CMD8_RETRIES 10
-#define BUSY_TIMEOUT_MILLIS 500
+#define BUSY_TIMEOUT_MILLIS 750
 //==============================================================================
 #define CMD_RESP_NONE SDIO_CMD_WAIT_NO_RESP
 #define CMD_RESP_R1   SDIO_CMD_WAIT_SHORT_RESP // normal response
@@ -137,7 +138,8 @@ static void _panic(const char *message, uint32_t code)
 		delay(250);
 	}
 }
-/*===========================================================================
+/*===========================================================================*/
+#if USE_YIELD
 void yield(void)
 {
 	uint32_t val = SDIO->STA;
@@ -169,7 +171,8 @@ void yield(void)
 		_panic(" - DMA: Data Transmission Error ", val);
 	}
 	//Serial.write('.');
-}*/
+}
+#endif
 //=============================================================================
 // Error function and macro.
 inline bool setSdErrorCode(uint8_t code, uint32_t line) {
@@ -191,11 +194,11 @@ void sdhc_isr() {
 //-----------------------------------------------------------------------------
 static bool cardCommand(uint16_t xfertyp, uint32_t arg)
 {
-#if USE_DEBUG_MODE
+#if USE_DEBUG_MODE==2
 	Serial.print("cardCommand: "); Serial.print(xfertyp&SDIO_CMD_CMDINDEX); Serial.print(", arg: "); Serial.print(arg, HEX);
 #endif
 	uint8_t resp = sdio_cmd_send(xfertyp, arg); // returns non-zero if fails, zero if OK
-#if USE_DEBUG_MODE
+#if USE_DEBUG_MODE==2
 	Serial.print(", resp: "); Serial.print(resp, HEX);
 	Serial.print(", SDIO->STA: "); Serial.print(SDIO->STA, HEX); Serial.print(", cmd_resp: "); Serial.print(SDIO->RESP[0], HEX);
 	if ( (xfertyp&SDIO_CMD_WAIT_LONG_RESP)==SDIO_CMD_WAIT_LONG_RESP ) {
@@ -330,6 +333,7 @@ static bool dmaTrxStart(uint8_t* buf, uint32_t n, uint8_t dir)
 static bool dmaTrxEnd(bool multi_block)
 {
 	if ( !waitDmaStatus() ) {
+		DBG_PRINT();
 		return sdError(SD_CARD_ERROR_DMA);
 	}
 	if ( waitTimeout(isBusyTransferComplete) ) {
@@ -536,6 +540,9 @@ uint32_t SdioCard::kHzSdClk() {
 /*---------------------------------------------------------------------------*/
 bool SdioCard::readBlock(uint32_t lba, uint8_t* buf)
 {
+#if USE_DEBUG_MODE
+	Serial.print("readBlock: ");  Serial.println(lba); //Serial.print(", buf: "); Serial.println((uint32_t)buf, HEX);
+#endif
 	// prepare SDIO and DMA for data read transfer
 	dmaTrxStart((uint32_t)buf & 3 ? (uint8_t*)aligned : buf, 512, TRX_RD);
 	// send command to start data transfer
@@ -560,6 +567,11 @@ bool SdioCard::readBlock(uint32_t lba, uint8_t* buf)
 /*---------------------------------------------------------------------------*/
 bool SdioCard::readBlocks(uint32_t lba, uint8_t* buf, size_t n)
 {
+#if USE_DEBUG_MODE
+	Serial.print("readBlocks: ");  Serial.print(lba);
+	//Serial.print(", buf: "); Serial.print((uint32_t)buf, HEX);
+	Serial.print(", "); Serial.println(n);
+#endif
 	if ((uint32_t)buf & 3) {
 		for (size_t i = 0; i < n; i++, lba++, buf += 512) {
 			if (!readBlock(lba, buf)) {
@@ -672,9 +684,12 @@ uint8_t SdioCard::type() {
 /*---------------------------------------------------------------------------*/
 bool SdioCard::writeBlock(uint32_t lba, const uint8_t* buf)
 {
+#if USE_DEBUG_MODE
+	Serial.print("writeBlock: ");  Serial.println(lba); //Serial.print(", buf: "); Serial.println((uint32_t)buf, HEX);
+#endif
 	uint8_t * ptr = (uint8_t *)buf;
 	if (3 & (uint32_t)ptr) {
-		//Serial.print("writeBlock: "); Serial.print(lba);
+		Serial.print("writeBlock: "); Serial.print(lba);
 		Serial.print(", buf: "); Serial.print((uint32_t)ptr, HEX);
 		//memcpy(aligned, buf, 512);
 		register uint8_t * src = (uint8_t *)ptr;
@@ -701,6 +716,11 @@ bool SdioCard::writeBlock(uint32_t lba, const uint8_t* buf)
 /*---------------------------------------------------------------------------*/
 bool SdioCard::writeBlocks(uint32_t lba, const uint8_t* buf, size_t n)
 {
+#if USE_DEBUG_MODE
+	Serial.print("writeBlocks: ");  Serial.print(lba);
+	//Serial.print(", buf: "); Serial.print((uint32_t)buf, HEX);
+	Serial.print(", "); Serial.println(n);
+#endif
 	if (3 & (uint32_t)buf) { // misaligned buffer address, write single blocks
 		for (size_t i = 0; i < n; i++, lba++, buf += 512) {
 			if (!writeBlock(lba, buf)) {
@@ -709,7 +729,6 @@ bool SdioCard::writeBlocks(uint32_t lba, const uint8_t* buf, size_t n)
 		}
 		return true;
 	}
-	//Serial.print("writeBlocks: ");  Serial.print(lba); Serial.print(", "); Serial.print(n);
 	if (yieldTimeout(isBusyCMD13)) {
 		return sdError(SD_CARD_ERROR_CMD13);
 	}

From 54dd788f2b223869854532d2df64ee9ab9e6d507 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Thu, 6 Jul 2017 10:57:20 +1000
Subject: [PATCH 139/307] Fix warning caused by commit
 #f7a576f2e0efcee958bdfd737d9af7a2f6c76051

---
 STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c | 4 ++--
 STM32F1/cores/maple/usb_serial.cpp                    | 4 ++--
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c b/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c
index 774be42cb..cba050f54 100644
--- a/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c
+++ b/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c
@@ -62,8 +62,8 @@
 
 #if !(defined(BOARD_maple) || defined(BOARD_maple_RET6) ||      \
       defined(BOARD_maple_mini) || defined(BOARD_maple_native))
-#warning USB CDC ACM relies on LeafLabs board-specific configuration.\
-    You may have problems on non-LeafLabs boards.
+//#warning USB CDC ACM relies on LeafLabs board-specific configuration.\
+//    You may have problems on non-LeafLabs boards.
 #endif
 
 static void vcomDataTxCb(void);
diff --git a/STM32F1/cores/maple/usb_serial.cpp b/STM32F1/cores/maple/usb_serial.cpp
index 1fe2bf48e..6cffbf573 100644
--- a/STM32F1/cores/maple/usb_serial.cpp
+++ b/STM32F1/cores/maple/usb_serial.cpp
@@ -71,7 +71,7 @@ void USBSerial::begin(void) {
         return;
     _hasBegun = true;
 
-    usb_cdcacm_enable(BOARD_USB_DISC_DEV, BOARD_USB_DISC_BIT);
+    usb_cdcacm_enable(BOARD_USB_DISC_DEV, (uint8_t)BOARD_USB_DISC_BIT);
     usb_cdcacm_set_hooks(USB_CDCACM_HOOK_RX, rxHook);
     usb_cdcacm_set_hooks(USB_CDCACM_HOOK_IFACE_SETUP, ifaceSetupHook);
 #endif
@@ -97,7 +97,7 @@ volatile uint8_t removeCompilerWarningsIgnore=ignore;
 
 void USBSerial::end(void) {
 #if BOARD_HAVE_SERIALUSB
-    usb_cdcacm_disable(BOARD_USB_DISC_DEV, BOARD_USB_DISC_BIT);
+    usb_cdcacm_disable(BOARD_USB_DISC_DEV, (uint8_t)BOARD_USB_DISC_BIT);
     usb_cdcacm_remove_hooks(USB_CDCACM_HOOK_RX | USB_CDCACM_HOOK_IFACE_SETUP);
 	_hasBegun = false;
 #endif

From 8683035cb7f95127b18b386be24b0fac537bb1f8 Mon Sep 17 00:00:00 2001
From: victorpv <victor_pv@hotmail.com>
Date: Sat, 8 Jul 2017 10:46:49 -0500
Subject: [PATCH 140/307] Update usb_serial.h

---
 STM32F1/cores/maple/usb_serial.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/STM32F1/cores/maple/usb_serial.h b/STM32F1/cores/maple/usb_serial.h
index d6c3e026f..153eb8ef8 100644
--- a/STM32F1/cores/maple/usb_serial.h
+++ b/STM32F1/cores/maple/usb_serial.h
@@ -51,6 +51,7 @@ class USBSerial : public Stream {
 
     virtual int available(void);// Changed to virtual
 
+    size_t usb_serial_class::readBytes(char *buf, const size_t& len);
     uint32 read(uint8 * buf, uint32 len);
     // uint8  read(void);
 

From 1c07e25bd71f4e823aa9d61e2194731a9d9aee8a Mon Sep 17 00:00:00 2001
From: victorpv <victor_pv@hotmail.com>
Date: Sat, 8 Jul 2017 10:49:14 -0500
Subject: [PATCH 141/307] Update usb_serial.h

---
 STM32F1/cores/maple/usb_serial.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/cores/maple/usb_serial.h b/STM32F1/cores/maple/usb_serial.h
index 153eb8ef8..835159370 100644
--- a/STM32F1/cores/maple/usb_serial.h
+++ b/STM32F1/cores/maple/usb_serial.h
@@ -51,7 +51,7 @@ class USBSerial : public Stream {
 
     virtual int available(void);// Changed to virtual
 
-    size_t usb_serial_class::readBytes(char *buf, const size_t& len);
+    size_t readBytes(char *buf, const size_t& len);
     uint32 read(uint8 * buf, uint32 len);
     // uint8  read(void);
 

From fd95b999146be0ffbb607551370bf4cd0d7bfaff Mon Sep 17 00:00:00 2001
From: victorpv <victor_pv@hotmail.com>
Date: Sat, 8 Jul 2017 10:52:50 -0500
Subject: [PATCH 142/307] Added readBytes function to usbSerial

Add Arduino USB implementation of Arduino Stream class readBytes, which reads bytes in blocks with a timeout.
Increases the speed from 300KB/s to 500KB/s over the Stream class readBytes function.
---
 STM32F1/cores/maple/usb_serial.cpp | 13 +++++++++++++
 1 file changed, 13 insertions(+)

diff --git a/STM32F1/cores/maple/usb_serial.cpp b/STM32F1/cores/maple/usb_serial.cpp
index 994cd7a62..0902c50e6 100644
--- a/STM32F1/cores/maple/usb_serial.cpp
+++ b/STM32F1/cores/maple/usb_serial.cpp
@@ -168,6 +168,19 @@ uint32 USBSerial::read(uint8 * buf, uint32 len) {
     return rxed;
 }
 
+size_t USBSerial::readBytes(char *buf, const size_t& len)
+{
+    size_t rxed=0;
+    unsigned long startMillis;
+    startMillis = millis();
+    if (len <= 0) return 0;
+    do {
+        rxed += usb_cdcacm_rx((uint8 *)buf + rxed, len - rxed);
+        if (rxed == len) return rxed;
+    } while(millis() - startMillis < _timeout);
+    return rxed;
+}
+
 /* Blocks forever until 1 byte is received */
 int USBSerial::read(void) {
     uint8 b;

From b892004cc236553618c29c7afb43663f00af9016 Mon Sep 17 00:00:00 2001
From: victorpv <victor_pv@hotmail.com>
Date: Mon, 10 Jul 2017 12:00:29 -0500
Subject: [PATCH 143/307] Add files via upload

---
 STM32F1/libraries/SPI/src/SPI.cpp | 358 +++++++++++++++++++++---------
 STM32F1/libraries/SPI/src/SPI.h   |  81 +++++--
 2 files changed, 311 insertions(+), 128 deletions(-)

diff --git a/STM32F1/libraries/SPI/src/SPI.cpp b/STM32F1/libraries/SPI/src/SPI.cpp
index f0d9f7f57..998f9b0f2 100644
--- a/STM32F1/libraries/SPI/src/SPI.cpp
+++ b/STM32F1/libraries/SPI/src/SPI.cpp
@@ -101,16 +101,19 @@ SPIClass::SPIClass(uint32 spi_num) {
 #if BOARD_NR_SPI >= 1
     case 1:
         _currentSetting->spi_d = SPI1;
+		_spi1_this = (void*) this;						  
         break;
 #endif
 #if BOARD_NR_SPI >= 2
     case 2:
         _currentSetting->spi_d = SPI2;
+        _spi2_this = (void*) this;								  
         break;
 #endif
 #if BOARD_NR_SPI >= 3
     case 3:
         _currentSetting->spi_d = SPI3;
+        _spi3_this = (void*) this;								  
         break;
 #endif
     default:
@@ -137,6 +140,8 @@ SPIClass::SPIClass(uint32 spi_num) {
 	_settings[2].spiRxDmaChannel = DMA_CH1;
 #endif
 
+    // added for DMA callbacks.
+    _currentSetting->state = SPI_STATE_IDLE;
 }
 
 /*
@@ -154,6 +159,8 @@ void SPIClass::begin(void) {
     spi_init(_currentSetting->spi_d);
     configure_gpios(_currentSetting->spi_d, 1);
     updateSettings();
+    // added for DMA callbacks.
+    _currentSetting->state = SPI_STATE_READY;
 }
 
 void SPIClass::beginSlave(void) {
@@ -164,6 +171,8 @@ void SPIClass::beginSlave(void) {
 	Serial.print("spi_slave_enable("); Serial.print(_currentSetting->dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
 	#endif
     spi_slave_enable(_currentSetting->spi_d, (spi_mode)_currentSetting->dataMode, flags);
+    // added for DMA callbacks.
+    _currentSetting->state = SPI_STATE_READY;
 }
 
 void SPIClass::end(void) {
@@ -182,6 +191,9 @@ void SPIClass::end(void) {
     while (spi_is_busy(_currentSetting->spi_d))
         ;
     spi_peripheral_disable(_currentSetting->spi_d);
+    // added for DMA callbacks.
+    // Need to add unsetting the callbacks for the DMA channels.
+    _currentSetting->state = SPI_STATE_IDLE;
 }
 
 /* Roger Clark added  3 functions */
@@ -384,98 +396,126 @@ uint16_t SPIClass::transfer16(uint16_t wr_data) const
 
 /*  Roger Clark and Victor Perez, 2015
 *	Performs a DMA SPI transfer with at least a receive buffer.
-*	If a TX buffer is not provided, FF is sent over and over for the length of the transfer. 
-*	On exit TX buffer is not modified, and RX buffer contains the received data.
+*	If a TX buffer is not provided, FF is sent over and over for the lenght of the transfer. 
+*	On exit TX buffer is not modified, and RX buffer cotains the received data.
 *	Still in progress.
 */
-uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length)
-{
-	if (length == 0) return 0;
-	uint8 b = 0;
-//	dma1_ch3_Active=true;
+void SPIClass::dmaTransferSet(void *transmitBuf, void *receiveBuf) {
     dma_init(_currentSetting->spiDmaDev);
-//	dma_attach_interrupt(DMA1, DMA_CH3, &SPIClass::DMA1_CH3_Event);
-
-	// RX
+	//spi_rx_dma_enable(_currentSetting->spi_d);
+	//spi_tx_dma_enable(_currentSetting->spi_d);
 	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
 	dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
-                     receiveBuf, dma_bit_size, (DMA_MINC_MODE));// receive buffer DMA
-	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, length);
-	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);// enable receive
-
-	// TX
-	uint32 flags = (DMA_MINC_MODE | DMA_FROM_MEM);
-	if ( transmitBuf==0 ) {
-		static uint8_t ff = 0XFF;
-		transmitBuf = &ff;
-		flags ^= DMA_MINC_MODE; // remove increment mode
+                     receiveBuf, dma_bit_size, (DMA_MINC_MODE | DMA_TRNS_CMPLT ));// receive buffer DMA
+	if (!transmitBuf) {
+	transmitBuf = &ff;
+	dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
+                       transmitBuf, dma_bit_size, (DMA_FROM_MEM));// Transmit FF repeatedly
 	}
+	else {
     dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
-                       transmitBuf, dma_bit_size, flags);// Transmit buffer DMA 
+                       transmitBuf, dma_bit_size, (DMA_MINC_MODE |  DMA_FROM_MEM ));// Transmit buffer DMA
+	}
+	dma_set_priority(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, DMA_PRIORITY_LOW);
+	dma_set_priority(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, DMA_PRIORITY_VERY_HIGH);
+}
+
+uint8 SPIClass::dmaTransferRepeat(uint16 length) {
+	if (length == 0) return 0;
+	if (spi_is_rx_nonempty(_currentSetting->spi_d) == 1) spi_rx_reg(_currentSetting->spi_d);
+	_currentSetting->state = SPI_STATE_TRANSFER;
+	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, length);
 	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
-	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);// enable receive
 	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
-
-	spi_rx_reg(_currentSetting->spi_d); //Clear the RX buffer in case a byte is waiting on it.
 	spi_rx_dma_enable(_currentSetting->spi_d);
-	spi_tx_dma_enable(_currentSetting->spi_d);	// must be the last enable to avoid DMA error flag
-	
+	spi_tx_dma_enable(_currentSetting->spi_d);
+    if (_currentSetting->receiveCallback){
+        return 0;
+    }
+    //uint32_t m = millis();
+    uint8 b = 0;
     uint32_t m = millis();
-	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
-		//delayMicroseconds(10);
+	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {
+		//Avoid interrupts and just loop waiting for the flag to be set.
 		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
     }
 
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
+	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
 	spi_tx_dma_disable(_currentSetting->spi_d);
-	spi_rx_dma_disable(_currentSetting->spi_d); // And disable generation of DMA request from the SPI port so other peripherals can use the channels
-	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+	spi_rx_dma_disable(_currentSetting->spi_d);
+    dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
+	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
+	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+	_currentSetting->state = SPI_STATE_READY;
     return b;
 }
 
+/*  Roger Clark and Victor Perez, 2015
+*	Performs a DMA SPI transfer with at least a receive buffer.
+*	If a TX buffer is not provided, FF is sent over and over for the length of the transfer. 
+*	On exit TX buffer is not modified, and RX buffer contains the received data.
+*	Still in progress.
+*/
+
+uint8 SPIClass::dmaTransfer(void *transmitBuf, void *receiveBuf, uint16 length) {
+	dmaTransferSet(transmitBuf, receiveBuf);
+	return dmaTransferRepeat(length);
+}
+
 /*  Roger Clark and Victor Perez, 2015
 *	Performs a DMA SPI send using a TX buffer.
 *	On exit TX buffer is not modified.
 *	Still in progress.
 *	2016 - stevstrong - reworked to automatically detect bit size from SPI setting
 */
-uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length, bool minc)
-{
+
+void SPIClass::dmaSendSet(void * transmitBuf, bool minc) {
+   uint32 flags = ( (DMA_MINC_MODE*minc) | DMA_FROM_MEM | DMA_TRNS_CMPLT);
+   dma_init(_currentSetting->spiDmaDev);
+   dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
+   dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
+                       transmitBuf, dma_bit_size, flags);// Transmit buffer DMA
+   dma_set_priority(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, DMA_PRIORITY_LOW);
+}
+
+uint8 SPIClass::dmaSendRepeat(uint16 length) {
 	if (length == 0) return 0;
-	uint32 flags = ( (DMA_MINC_MODE*minc) | DMA_FROM_MEM | DMA_TRNS_CMPLT);
-	uint8 b = 0;
-    dma_init(_currentSetting->spiDmaDev);
-	// TX
-	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
-    dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
-                       transmitBuf, dma_bit_size, flags);// Transmit buffer DMA 
-	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
 	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
+	_currentSetting->state = SPI_STATE_TRANSMIT;
 	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
-	spi_tx_dma_enable(_currentSetting->spi_d);	
-
-    uint32_t m = millis();
-	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
-		//delayMicroseconds(10);
+	spi_tx_dma_enable(_currentSetting->spi_d);				  
+	if (_currentSetting->transmitCallback)
+	{
+		return 0;
+	}
+	uint32_t m = millis();
+	uint8 b = 0;
+	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {
+		//Avoid interrupts and just loop waiting for the flag to be set.
 		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
-    }
-
+	}
 	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
 	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
 	spi_tx_dma_disable(_currentSetting->spi_d);
 	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+	_currentSetting->state = SPI_STATE_READY;
 	return b;
 }
 
+uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length, bool minc) {
+    dmaSendSet(transmitBuf, minc);
+    return dmaSendRepeat(length);
+}
 
-uint8 SPIClass::dmaSendAsync(void * transmitBuf, uint16 length, bool minc)
-{
-	static bool isRunning=false;
+uint8 SPIClass::dmaSendAsync(void * transmitBuf, uint16 length, bool minc) {
 	uint8 b = 0;	
 
-	if (isRunning)
+	if (_currentSetting->state != SPI_STATE_READY)
 	{
 
 		uint32_t m = millis();
@@ -488,29 +528,121 @@ uint8 SPIClass::dmaSendAsync(void * transmitBuf, uint16 length, bool minc)
 		while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
 		spi_tx_dma_disable(_currentSetting->spi_d);
 		dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
-		isRunning=false;
+		_currentSetting->state = SPI_STATE_READY;
 	}
 
 	
 	if (length == 0) return 0;
 	uint32 flags = ( (DMA_MINC_MODE*minc) | DMA_FROM_MEM | DMA_TRNS_CMPLT);
 
-    dma_init(_currentSetting->spiDmaDev);
+	
+	dma_init(_currentSetting->spiDmaDev);
 	// TX
 	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
-    dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
-                       transmitBuf, dma_bit_size, flags);// Transmit buffer DMA 
+	dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
+	transmitBuf, dma_bit_size, flags);// Transmit buffer DMA 
 	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
 	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
 	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
 	spi_tx_dma_enable(_currentSetting->spi_d);	
 
-	isRunning=true;
+	_currentSetting->state = SPI_STATE_TRANSMIT;
 
 	return b;
 }
 
 
+/*
+    New functions added to manage callbacks.
+    Victor Perez 2017
+*/
+
+void SPIClass::onReceive(void(*callback)(void)) {
+	_currentSetting->receiveCallback = callback;
+	if (callback){
+		switch (_currentSetting->spi_d->clk_id) {
+		case RCC_SPI1:
+			dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &SPIClass::_spi1EventCallback);
+			break;
+		case RCC_SPI2:
+			dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &SPIClass::_spi2EventCallback);
+			break;
+			#if BOARD_NR_SPI >= 3
+		case RCC_SPI3:
+			dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &SPIClass::_spi3EventCallback);
+			break;
+			#endif
+		default:
+			ASSERT(0);
+		}
+	}
+	else {
+		dma_detach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
+	}
+}
+
+void SPIClass::onTransmit(void(*callback)(void)) {
+	_currentSetting->transmitCallback = callback;
+	if (callback){
+		switch (_currentSetting->spi_d->clk_id) {
+		case RCC_SPI1:
+			dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &SPIClass::_spi1EventCallback);
+			break;
+		case RCC_SPI2:
+			dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &SPIClass::_spi2EventCallback);
+			break;
+			#if BOARD_NR_SPI >= 3
+		case RCC_SPI3:
+			dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &SPIClass::_spi3EventCallback);
+			break;
+			#endif
+		default:
+			ASSERT(0);
+		}
+	}
+	else {
+		dma_detach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+	}
+}
+
+/*
+    TODO: check if better to first call the customer code, next disable the DMA requests.
+    Also see if we need to check whether callbacks are set or not, may be better to be checked during the initial setup and only set the callback to EventCallback if they are set.
+*/
+
+void SPIClass::EventCallback() {
+	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0"
+	switch (_currentSetting->state) {
+	case SPI_STATE_TRANSFER:
+		while (spi_is_rx_nonempty(_currentSetting->spi_d));
+		_currentSetting->state = SPI_STATE_READY;
+		spi_tx_dma_disable(_currentSetting->spi_d);
+		spi_rx_dma_disable(_currentSetting->spi_d);
+		//dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+		//dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
+
+		if (_currentSetting->receiveCallback)
+		{
+			_currentSetting->receiveCallback();
+		}
+		break;
+	case SPI_STATE_TRANSMIT:
+		_currentSetting->state = SPI_STATE_READY;
+		spi_tx_dma_disable(_currentSetting->spi_d);
+		//dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+		if (_currentSetting->transmitCallback)
+		{
+			_currentSetting->transmitCallback();
+		}
+
+		break;
+	default:
+		// we shouldn't get here, so better to add an assert and fail.
+		return;
+	}
+}
+
 void SPIClass::attachInterrupt(void) {
 	// Should be enableInterrupt()
 }
@@ -557,85 +689,101 @@ uint8 SPIClass::recv(void) {
     return this->read();
 }
 
+/*
+    DMA call back functions, one per port.
+*/
+
+void SPIClass::_spi1EventCallback()
+{
+    reinterpret_cast<class SPIClass*>(_spi1_this)->EventCallback();
+}
 
+void SPIClass::_spi2EventCallback() {
+	reinterpret_cast<class SPIClass*>(_spi2_this)->EventCallback();
+}
+#if BOARD_NR_SPI >= 3
+void SPIClass::_spi3EventCallback() {
+	reinterpret_cast<class SPIClass*>(_spi3_this)->EventCallback();
+}
+#endif
 /*
- * Auxiliary functions
- */
+* Auxiliary functions
+*/
 
 static const spi_pins* dev_to_spi_pins(spi_dev *dev) {
-    switch (dev->clk_id) {
+	switch (dev->clk_id) {
 #if BOARD_NR_SPI >= 1
-    case RCC_SPI1: return board_spi_pins;
+	case RCC_SPI1: return board_spi_pins;
 #endif
 #if BOARD_NR_SPI >= 2
-    case RCC_SPI2: return board_spi_pins + 1;
+	case RCC_SPI2: return board_spi_pins + 1;
 #endif
 #if BOARD_NR_SPI >= 3
-    case RCC_SPI3: return board_spi_pins + 2;
+	case RCC_SPI3: return board_spi_pins + 2;
 #endif
-    default:       return NULL;
-    }
+	default:       return NULL;
+	}
 }
 
 static void disable_pwm(const stm32_pin_info *i) {
-    if (i->timer_device) {
-        timer_set_mode(i->timer_device, i->timer_channel, TIMER_DISABLED);
-    }
+	if (i->timer_device) {
+		timer_set_mode(i->timer_device, i->timer_channel, TIMER_DISABLED);
+	}
 }
 
 static void configure_gpios(spi_dev *dev, bool as_master) {
-    const spi_pins *pins = dev_to_spi_pins(dev);
+	const spi_pins *pins = dev_to_spi_pins(dev);
 
-    if (!pins) {
-        return;
-    }
+	if (!pins) {
+		return;
+	}
 
-    const stm32_pin_info *nssi = &PIN_MAP[pins->nss];
-    const stm32_pin_info *scki = &PIN_MAP[pins->sck];
-    const stm32_pin_info *misoi = &PIN_MAP[pins->miso];
-    const stm32_pin_info *mosii = &PIN_MAP[pins->mosi];
+	const stm32_pin_info *nssi = &PIN_MAP[pins->nss];
+	const stm32_pin_info *scki = &PIN_MAP[pins->sck];
+	const stm32_pin_info *misoi = &PIN_MAP[pins->miso];
+	const stm32_pin_info *mosii = &PIN_MAP[pins->mosi];
 
-    disable_pwm(nssi);
-    disable_pwm(scki);
-    disable_pwm(misoi);
-    disable_pwm(mosii);
+	disable_pwm(nssi);
+	disable_pwm(scki);
+	disable_pwm(misoi);
+	disable_pwm(mosii);
 
-    spi_config_gpios(dev, as_master, nssi->gpio_device, nssi->gpio_bit,
-                     scki->gpio_device, scki->gpio_bit, misoi->gpio_bit,
-                     mosii->gpio_bit);
+	spi_config_gpios(dev, as_master, nssi->gpio_device, nssi->gpio_bit,
+	scki->gpio_device, scki->gpio_bit, misoi->gpio_bit,
+	mosii->gpio_bit);
 }
 
 static const spi_baud_rate baud_rates[8] __FLASH__ = {
-    SPI_BAUD_PCLK_DIV_2,
-    SPI_BAUD_PCLK_DIV_4,
-    SPI_BAUD_PCLK_DIV_8,
-    SPI_BAUD_PCLK_DIV_16,
-    SPI_BAUD_PCLK_DIV_32,
-    SPI_BAUD_PCLK_DIV_64,
-    SPI_BAUD_PCLK_DIV_128,
-    SPI_BAUD_PCLK_DIV_256,
+	SPI_BAUD_PCLK_DIV_2,
+	SPI_BAUD_PCLK_DIV_4,
+	SPI_BAUD_PCLK_DIV_8,
+	SPI_BAUD_PCLK_DIV_16,
+	SPI_BAUD_PCLK_DIV_32,
+	SPI_BAUD_PCLK_DIV_64,
+	SPI_BAUD_PCLK_DIV_128,
+	SPI_BAUD_PCLK_DIV_256,
 };
 
 /*
- * Note: This assumes you're on a LeafLabs-style board
- * (CYCLES_PER_MICROSECOND == 72, APB2 at 72MHz, APB1 at 36MHz).
- */
+* Note: This assumes you're on a LeafLabs-style board
+* (CYCLES_PER_MICROSECOND == 72, APB2 at 72MHz, APB1 at 36MHz).
+*/
 static spi_baud_rate determine_baud_rate(spi_dev *dev, uint32_t freq) {
 	uint32_t clock = 0, i;
 	#ifdef SPI_DEBUG
 	Serial.print("determine_baud_rate("); Serial.print(freq); Serial.println(")");
 	#endif
-    switch (rcc_dev_clk(dev->clk_id))
-    {
-    	case RCC_APB2: clock = STM32_PCLK2; break; // 72 Mhz
-    	case RCC_APB1: clock = STM32_PCLK1; break; // 36 Mhz
-    }
-    clock /= 2;
-    i = 0;
-    while (i < 7 && freq < clock) {
-      clock /= 2;
-      i++;
-    }
+	switch (rcc_dev_clk(dev->clk_id))
+	{
+	case RCC_APB2: clock = STM32_PCLK2; break; // 72 Mhz
+	case RCC_APB1: clock = STM32_PCLK1; break; // 36 Mhz
+	}
+	clock /= 2;
+	i = 0;
+	while (i < 7 && freq < clock) {
+		clock /= 2;
+		i++;
+	}
 	return baud_rates[i];
 }
 
diff --git a/STM32F1/libraries/SPI/src/SPI.h b/STM32F1/libraries/SPI/src/SPI.h
index 4d9b563ed..2160d2696 100644
--- a/STM32F1/libraries/SPI/src/SPI.h
+++ b/STM32F1/libraries/SPI/src/SPI.h
@@ -99,6 +99,13 @@
 #define DATA_SIZE_8BIT SPI_CR1_DFF_8_BIT
 #define DATA_SIZE_16BIT SPI_CR1_DFF_16_BIT
 
+typedef enum {
+		SPI_STATE_IDLE,
+		SPI_STATE_READY,
+		SPI_STATE_RECEIVE,
+		SPI_STATE_TRANSMIT,
+        SPI_STATE_TRANSFER
+	} spi_mode_t;
 class SPISettings {
 public:
 	SPISettings(uint32_t clock, BitOrder bitOrder, uint8_t dataMode) {
@@ -134,21 +141,31 @@ class SPISettings {
 		this->dataSize = dataSize;
 	}
 	uint32_t clock;
+  uint32_t dataSize;
+  uint32_t clockDivider;
 	BitOrder bitOrder;
 	uint8_t dataMode;
-	uint32_t dataSize;
-	
+  uint8_t _SSPin;
+	volatile spi_mode_t state;
 	spi_dev *spi_d;
-	uint8_t _SSPin;
-	uint32_t clockDivider;
 	dma_channel spiRxDmaChannel, spiTxDmaChannel;
 	dma_dev* spiDmaDev;
+  void (*receiveCallback)(void) = NULL;
+  void (*transmitCallback)(void) = NULL;
 	
 	friend class SPIClass;
 };
 
 
-volatile static bool dma1_ch3_Active;
+/*
+    Should move this to within the class once tested out, just for tidyness
+*/
+static uint8_t ff = 0XFF;
+static void (*_spi1_this);
+static void (*_spi2_this);
+#if BOARD_NR_SPI >= 3
+static void (*_spi3_this);
+#endif
 
 /**
  * @brief Wirish SPI interface.
@@ -217,7 +234,15 @@ class SPIClass {
 	*/
     void setDataSize(uint32 ds);
 	
-	
+    /*  Victor Perez 2017. Added to set and clear callback functions for callback
+	* on DMA transfer completion.
+	* onReceive used to set the callback in case of dmaTransfer (tx/rx), once rx is completed
+	* onTransmit used to set the callback in case of dmaSend (tx only). That function
+	* will NOT be called in case of TX/RX
+    */
+    void onReceive(void(*)(void));
+    void onTransmit(void(*)(void));
+
     /*
      * I/O
      */
@@ -279,7 +304,9 @@ class SPIClass {
      * @param receiveBuf buffer Bytes to save received data. 
      * @param length Number of bytes in buffer to transmit.
 	 */
-	uint8 dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length);
+    uint8 dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length);
+    void dmaTransferSet(void *transmitBuf, void *receiveBuf);
+    uint8 dmaTransferRepeat(uint16 length);
 
 	/**
      * @brief Sets up a DMA Transmit for SPI 8 or 16 bit transfer mode.
@@ -289,9 +316,13 @@ class SPIClass {
      *
      * @param data buffer half words to transmit,
      * @param length Number of bytes in buffer to transmit.
+	 * @param minc Set to use Memory Increment mode, clear to use Circular mode.
      */
-	uint8 dmaSend(void * transmitBuf, uint16 length, bool minc = 1);
-	uint8 dmaSendAsync(void * transmitBuf, uint16 length, bool minc = 1);
+    uint8 dmaSend(void * transmitBuf, uint16 length, bool minc = 1);
+    void dmaSendSet(void * transmitBuf, bool minc);
+    uint8 dmaSendRepeat(uint16 length);
+	
+    uint8 dmaSendAsync(void * transmitBuf, uint16 length, bool minc = 1);
     /*
      * Pin accessors
      */
@@ -325,7 +356,7 @@ class SPIClass {
     spi_dev* c_dev(void) { return _currentSetting->spi_d; }
 	
 		
-	spi_dev *dev(){ return _currentSetting->spi_d;}
+    spi_dev *dev(){ return _currentSetting->spi_d;}
 	
 	 /**
      * @brief Sets the number of the SPI peripheral to be used by
@@ -335,10 +366,10 @@ class SPIClass {
 	 *			or 1-3 in high density devices.
      */
 	
-	void setModule(int spi_num)
-	{
-		_currentSetting=&_settings[spi_num-1];// SPI channels are called 1 2 and 3 but the array is zero indexed
-	}
+    void setModule(int spi_num)
+    {
+        _currentSetting=&_settings[spi_num-1];// SPI channels are called 1 2 and 3 but the array is zero indexed
+    }
 
 
     /* -- The following methods are deprecated --------------------------- */
@@ -374,19 +405,23 @@ class SPIClass {
     uint8 recv(void);
 	
 private:
-/*
-	static inline void DMA1_CH3_Event() {
-		dma1_ch3_Active = 0;
-//		dma_disable(DMA1, DMA_CH3);
-//		dma_disable(DMA1, DMA_CH2);
-		
-		// To Do. Need to wait for 
-	}
-*/	
+
 	SPISettings _settings[BOARD_NR_SPI];
 	SPISettings *_currentSetting;
 	
 	void updateSettings(void);
+    /*
+	* Functions added for DMA transfers with Callback. 
+	* Experimental.
+	*/
+	
+    void EventCallback(void);
+    
+    static void _spi1EventCallback(void);
+    static void _spi2EventCallback(void);
+    #if BOARD_NR_SPI >= 3
+    static void _spi3EventCallback(void);
+    #endif
 	/*
 	spi_dev *spi_d;
 	uint8_t _SSPin;

From 910072c7db2c0f81452589cc8fdf965457824aa1 Mon Sep 17 00:00:00 2001
From: victorpv <victor_pv@hotmail.com>
Date: Mon, 10 Jul 2017 12:08:59 -0500
Subject: [PATCH 144/307] Changes tabs for spaces.

---
 STM32F1/libraries/SPI/src/SPI.cpp | 692 +++++++++++++++---------------
 1 file changed, 346 insertions(+), 346 deletions(-)

diff --git a/STM32F1/libraries/SPI/src/SPI.cpp b/STM32F1/libraries/SPI/src/SPI.cpp
index 998f9b0f2..94e5031c8 100644
--- a/STM32F1/libraries/SPI/src/SPI.cpp
+++ b/STM32F1/libraries/SPI/src/SPI.cpp
@@ -94,14 +94,14 @@ static const spi_pins board_spi_pins[] __FLASH__ = {
 
 SPIClass::SPIClass(uint32 spi_num) {
 
-	_currentSetting=&_settings[spi_num-1];// SPI channels are called 1 2 and 3 but the array is zero indexed
+    _currentSetting=&_settings[spi_num-1];// SPI channels are called 1 2 and 3 but the array is zero indexed
 
-	
+    
     switch (spi_num) {
 #if BOARD_NR_SPI >= 1
     case 1:
         _currentSetting->spi_d = SPI1;
-		_spi1_this = (void*) this;						  
+        _spi1_this = (void*) this;						  
         break;
 #endif
 #if BOARD_NR_SPI >= 2
@@ -119,25 +119,25 @@ SPIClass::SPIClass(uint32 spi_num) {
     default:
         ASSERT(0);
     }
-	
-	// Init things specific to each SPI device
-	// clock divider setup is a bit of hack, and needs to be improved at a later date.
-	_settings[0].spi_d = SPI1;
-	_settings[0].clockDivider = determine_baud_rate(_settings[0].spi_d, _settings[0].clock);
-	_settings[0].spiDmaDev = DMA1;
-	_settings[0].spiTxDmaChannel = DMA_CH3;
-	_settings[0].spiRxDmaChannel = DMA_CH2;
-	_settings[1].spi_d = SPI2;
-	_settings[1].clockDivider = determine_baud_rate(_settings[1].spi_d, _settings[1].clock);
-	_settings[1].spiDmaDev = DMA1;
-	_settings[1].spiTxDmaChannel = DMA_CH5;
-	_settings[1].spiRxDmaChannel = DMA_CH4;
+    
+    // Init things specific to each SPI device
+    // clock divider setup is a bit of hack, and needs to be improved at a later date.
+    _settings[0].spi_d = SPI1;
+    _settings[0].clockDivider = determine_baud_rate(_settings[0].spi_d, _settings[0].clock);
+    _settings[0].spiDmaDev = DMA1;
+    _settings[0].spiTxDmaChannel = DMA_CH3;
+    _settings[0].spiRxDmaChannel = DMA_CH2;
+    _settings[1].spi_d = SPI2;
+    _settings[1].clockDivider = determine_baud_rate(_settings[1].spi_d, _settings[1].clock);
+    _settings[1].spiDmaDev = DMA1;
+    _settings[1].spiTxDmaChannel = DMA_CH5;
+    _settings[1].spiRxDmaChannel = DMA_CH4;
 #if BOARD_NR_SPI >= 3
-	_settings[2].spi_d = SPI3;
-	_settings[2].clockDivider = determine_baud_rate(_settings[2].spi_d, _settings[2].clock);
-	_settings[2].spiDmaDev = DMA2;
-	_settings[2].spiTxDmaChannel = DMA_CH2;
-	_settings[2].spiRxDmaChannel = DMA_CH1;
+    _settings[2].spi_d = SPI3;
+    _settings[2].clockDivider = determine_baud_rate(_settings[2].spi_d, _settings[2].clock);
+    _settings[2].spiDmaDev = DMA2;
+    _settings[2].spiTxDmaChannel = DMA_CH2;
+    _settings[2].spiRxDmaChannel = DMA_CH1;
 #endif
 
     // added for DMA callbacks.
@@ -148,11 +148,11 @@ SPIClass::SPIClass(uint32 spi_num) {
  * Set up/tear down
  */
 void SPIClass::updateSettings(void) {
-	uint32 flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | _currentSetting->dataSize | SPI_SW_SLAVE | SPI_SOFT_SS);
-	#ifdef SPI_DEBUG
-	Serial.print("spi_master_enable("); Serial.print(_currentSetting->clockDivider); Serial.print(","); Serial.print(_currentSetting->dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
-	#endif
-	spi_master_enable(_currentSetting->spi_d, (spi_baud_rate)_currentSetting->clockDivider, (spi_mode)_currentSetting->dataMode, flags);
+    uint32 flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | _currentSetting->dataSize | SPI_SW_SLAVE | SPI_SOFT_SS);
+    #ifdef SPI_DEBUG
+    Serial.print("spi_master_enable("); Serial.print(_currentSetting->clockDivider); Serial.print(","); Serial.print(_currentSetting->dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
+    #endif
+    spi_master_enable(_currentSetting->spi_d, (spi_baud_rate)_currentSetting->clockDivider, (spi_mode)_currentSetting->dataMode, flags);
 }
 
 void SPIClass::begin(void) {
@@ -167,9 +167,9 @@ void SPIClass::beginSlave(void) {
     spi_init(_currentSetting->spi_d);
     configure_gpios(_currentSetting->spi_d, 0);
     uint32 flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | _currentSetting->dataSize | SPI_RX_ONLY);
-	#ifdef SPI_DEBUG
-	Serial.print("spi_slave_enable("); Serial.print(_currentSetting->dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
-	#endif
+    #ifdef SPI_DEBUG
+    Serial.print("spi_slave_enable("); Serial.print(_currentSetting->dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
+    #endif
     spi_slave_enable(_currentSetting->spi_d, (spi_mode)_currentSetting->dataMode, flags);
     // added for DMA callbacks.
     _currentSetting->state = SPI_STATE_READY;
@@ -199,23 +199,23 @@ void SPIClass::end(void) {
 /* Roger Clark added  3 functions */
 void SPIClass::setClockDivider(uint32_t clockDivider)
 {
-	#ifdef SPI_DEBUG
-	Serial.print("Clock divider set to "); Serial.println(clockDivider);
-	#endif
-	_currentSetting->clockDivider = clockDivider;
-	uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_BR);
-	_currentSetting->spi_d->regs->CR1 = cr1 | (clockDivider & SPI_CR1_BR);
+    #ifdef SPI_DEBUG
+    Serial.print("Clock divider set to "); Serial.println(clockDivider);
+    #endif
+    _currentSetting->clockDivider = clockDivider;
+    uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_BR);
+    _currentSetting->spi_d->regs->CR1 = cr1 | (clockDivider & SPI_CR1_BR);
 }
 
 void SPIClass::setBitOrder(BitOrder bitOrder)
 {
-	#ifdef SPI_DEBUG
-	Serial.print("Bit order set to "); Serial.println(bitOrder);
-	#endif
-	_currentSetting->bitOrder = bitOrder;
-	uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_LSBFIRST);
-	if ( bitOrder==LSBFIRST )	cr1 |= SPI_CR1_LSBFIRST;
-	_currentSetting->spi_d->regs->CR1 = cr1;
+    #ifdef SPI_DEBUG
+    Serial.print("Bit order set to "); Serial.println(bitOrder);
+    #endif
+    _currentSetting->bitOrder = bitOrder;
+    uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_LSBFIRST);
+    if ( bitOrder==LSBFIRST )	cr1 |= SPI_CR1_LSBFIRST;
+    _currentSetting->spi_d->regs->CR1 = cr1;
 }
 
 /*	Victor Perez. Added to test changing datasize from 8 to 16 bit modes on the fly.
@@ -224,11 +224,11 @@ void SPIClass::setBitOrder(BitOrder bitOrder)
 */
 void SPIClass::setDataSize(uint32 datasize)
 {
-	_currentSetting->dataSize = datasize;
-	uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_DFF);
-	uint8 en = spi_is_enabled(_currentSetting->spi_d);
-	spi_peripheral_disable(_currentSetting->spi_d);
-	_currentSetting->spi_d->regs->CR1 = cr1 | (datasize & SPI_CR1_DFF) | en;
+    _currentSetting->dataSize = datasize;
+    uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_DFF);
+    uint8 en = spi_is_enabled(_currentSetting->spi_d);
+    spi_peripheral_disable(_currentSetting->spi_d);
+    _currentSetting->spi_d->regs->CR1 = cr1 | (datasize & SPI_CR1_DFF) | en;
 }
 
 void SPIClass::setDataMode(uint8_t dataMode)
@@ -258,56 +258,56 @@ bit 0 - CPHA : Clock phase
  
 If someone finds this is not the case or sees a logic error with this let me know ;-) 
  */
-	#ifdef SPI_DEBUG
-	Serial.print("Data mode set to "); Serial.println(dataMode);
-	#endif
-	_currentSetting->dataMode = dataMode;
-	uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_CPOL|SPI_CR1_CPHA);
-	_currentSetting->spi_d->regs->CR1 = cr1 | (dataMode & (SPI_CR1_CPOL|SPI_CR1_CPHA));
+    #ifdef SPI_DEBUG
+    Serial.print("Data mode set to "); Serial.println(dataMode);
+    #endif
+    _currentSetting->dataMode = dataMode;
+    uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_CPOL|SPI_CR1_CPHA);
+    _currentSetting->spi_d->regs->CR1 = cr1 | (dataMode & (SPI_CR1_CPOL|SPI_CR1_CPHA));
 }
 
 void SPIClass::beginTransaction(uint8_t pin, SPISettings settings)
 {
-	#ifdef SPI_DEBUG
-	Serial.println("SPIClass::beginTransaction");
-	#endif
-	setBitOrder(settings.bitOrder);
-	setDataMode(settings.dataMode);
-	setDataSize(settings.dataSize);
-	setClockDivider(determine_baud_rate(_currentSetting->spi_d, settings.clock));
-	begin();
+    #ifdef SPI_DEBUG
+    Serial.println("SPIClass::beginTransaction");
+    #endif
+    setBitOrder(settings.bitOrder);
+    setDataMode(settings.dataMode);
+    setDataSize(settings.dataSize);
+    setClockDivider(determine_baud_rate(_currentSetting->spi_d, settings.clock));
+    begin();
 }
 
 void SPIClass::beginTransactionSlave(SPISettings settings)
 {
-	#ifdef SPI_DEBUG
-	Serial.println(F("SPIClass::beginTransactionSlave"));
-	#endif
-	setBitOrder(settings.bitOrder);
-	setDataMode(settings.dataMode);
-	setDataSize(settings.dataSize);
-	beginSlave();
+    #ifdef SPI_DEBUG
+    Serial.println(F("SPIClass::beginTransactionSlave"));
+    #endif
+    setBitOrder(settings.bitOrder);
+    setDataMode(settings.dataMode);
+    setDataSize(settings.dataSize);
+    beginSlave();
 }
 
 void SPIClass::endTransaction(void)
 {
-	#ifdef SPI_DEBUG
-	Serial.println("SPIClass::endTransaction");
-	#endif
-	//digitalWrite(_SSPin,HIGH);
+    #ifdef SPI_DEBUG
+    Serial.println("SPIClass::endTransaction");
+    #endif
+    //digitalWrite(_SSPin,HIGH);
 #if false
 // code from SAM core
-	uint8_t mode = interruptMode;
-	if (mode > 0) {
-		if (mode < 16) {
-			if (mode & 1) PIOA->PIO_IER = interruptMask[0];
-			if (mode & 2) PIOB->PIO_IER = interruptMask[1];
-			if (mode & 4) PIOC->PIO_IER = interruptMask[2];
-			if (mode & 8) PIOD->PIO_IER = interruptMask[3];
-		} else {
-			if (interruptSave) interrupts();
-		}
-	}
+    uint8_t mode = interruptMode;
+    if (mode > 0) {
+        if (mode < 16) {
+            if (mode & 1) PIOA->PIO_IER = interruptMask[0];
+            if (mode & 2) PIOB->PIO_IER = interruptMask[1];
+            if (mode & 4) PIOC->PIO_IER = interruptMask[2];
+            if (mode & 8) PIOD->PIO_IER = interruptMask[3];
+        } else {
+            if (interruptSave) interrupts();
+        }
+    }
 #endif
 }
 
@@ -318,80 +318,80 @@ void SPIClass::endTransaction(void)
 
 uint16 SPIClass::read(void)
 {
-	while ( spi_is_rx_nonempty(_currentSetting->spi_d)==0 ) ;
-	return (uint16)spi_rx_reg(_currentSetting->spi_d);
+    while ( spi_is_rx_nonempty(_currentSetting->spi_d)==0 ) ;
+    return (uint16)spi_rx_reg(_currentSetting->spi_d);
 }
 
 void SPIClass::read(uint8 *buf, uint32 len)
 {
-	if ( len == 0 ) return;
-	spi_rx_reg(_currentSetting->spi_d);		// clear the RX buffer in case a byte is waiting on it.
-	spi_reg_map * regs = _currentSetting->spi_d->regs;
-	// start sequence: write byte 0
-	regs->DR = 0x00FF;						// write the first byte
-	// main loop
-	while ( (--len) ) {
-		while( !(regs->SR & SPI_SR_TXE) );		// wait for TXE flag
-		noInterrupts();							// go atomic level - avoid interrupts to surely get the previously received data
-		regs->DR = 0x00FF;						// write the next data item to be transmitted into the SPI_DR register. This clears the TXE flag.
-		while ( !(regs->SR & SPI_SR_RXNE) );	// wait till data is available in the DR register
-		*buf++ = (uint8)(regs->DR);				// read and store the received byte. This clears the RXNE flag.
-		interrupts();							// let systick do its job
-	}
-	// read remaining last byte
-	while ( !(regs->SR & SPI_SR_RXNE) );	// wait till data is available in the Rx register
-	*buf++ = (uint8)(regs->DR);				// read and store the received byte
+    if ( len == 0 ) return;
+    spi_rx_reg(_currentSetting->spi_d);		// clear the RX buffer in case a byte is waiting on it.
+    spi_reg_map * regs = _currentSetting->spi_d->regs;
+    // start sequence: write byte 0
+    regs->DR = 0x00FF;						// write the first byte
+    // main loop
+    while ( (--len) ) {
+        while( !(regs->SR & SPI_SR_TXE) );		// wait for TXE flag
+        noInterrupts();							// go atomic level - avoid interrupts to surely get the previously received data
+        regs->DR = 0x00FF;						// write the next data item to be transmitted into the SPI_DR register. This clears the TXE flag.
+        while ( !(regs->SR & SPI_SR_RXNE) );	// wait till data is available in the DR register
+        *buf++ = (uint8)(regs->DR);				// read and store the received byte. This clears the RXNE flag.
+        interrupts();							// let systick do its job
+    }
+    // read remaining last byte
+    while ( !(regs->SR & SPI_SR_RXNE) );	// wait till data is available in the Rx register
+    *buf++ = (uint8)(regs->DR);				// read and store the received byte
 }
 
 void SPIClass::write(uint16 data)
 {
-	/* Added for 16bit data Victor Perez. Roger Clark 
-	 * Improved speed by just directly writing the single byte to the SPI data reg and wait for completion,
-	 * by taking the Tx code from transfer(byte)
-	 * This almost doubles the speed of this function.
-	 */
-	spi_tx_reg(_currentSetting->spi_d, data); // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
-	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
+    /* Added for 16bit data Victor Perez. Roger Clark 
+     * Improved speed by just directly writing the single byte to the SPI data reg and wait for completion,
+     * by taking the Tx code from transfer(byte)
+     * This almost doubles the speed of this function.
+     */
+    spi_tx_reg(_currentSetting->spi_d, data); // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
+    while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+    while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
 }
 
 void SPIClass::write(uint16 data, uint32 n)
 {
-	// Added by stevstrong: Repeatedly send same data by the specified number of times
-	spi_reg_map * regs = _currentSetting->spi_d->regs;
-	while ( (n--)>0 ) {
-		regs->DR = data; // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
-		while ( (regs->SR & SPI_SR_TXE)==0 ) ; // wait till Tx empty
-	}
-	while ( (regs->SR & SPI_SR_BSY) != 0); // wait until BSY=0 before returning 
+    // Added by stevstrong: Repeatedly send same data by the specified number of times
+    spi_reg_map * regs = _currentSetting->spi_d->regs;
+    while ( (n--)>0 ) {
+        regs->DR = data; // write the data to be transmitted into the SPI_DR register (this clears the TXE flag)
+        while ( (regs->SR & SPI_SR_TXE)==0 ) ; // wait till Tx empty
+    }
+    while ( (regs->SR & SPI_SR_BSY) != 0); // wait until BSY=0 before returning 
 }
 
 void SPIClass::write(void *data, uint32 length)
 {
-	spi_dev * spi_d = _currentSetting->spi_d;
-	spi_tx(spi_d, (void*)data, length); // data can be array of bytes or words
-	while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
+    spi_dev * spi_d = _currentSetting->spi_d;
+    spi_tx(spi_d, (void*)data, length); // data can be array of bytes or words
+    while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
+    while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
 }
 
 uint8 SPIClass::transfer(uint8 byte) const
 {
-	spi_dev * spi_d = _currentSetting->spi_d;
-	spi_rx_reg(spi_d); // read any previous data
-	spi_tx_reg(spi_d, byte); // Write the data item to be transmitted into the SPI_DR register
-	while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
-	return (uint8)spi_rx_reg(spi_d); // "... and read the last received data."
+    spi_dev * spi_d = _currentSetting->spi_d;
+    spi_rx_reg(spi_d); // read any previous data
+    spi_tx_reg(spi_d, byte); // Write the data item to be transmitted into the SPI_DR register
+    while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
+    while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
+    return (uint8)spi_rx_reg(spi_d); // "... and read the last received data."
 }
 
 uint16_t SPIClass::transfer16(uint16_t wr_data) const
 {
-	spi_dev * spi_d = _currentSetting->spi_d;
-	spi_rx_reg(spi_d); // read any previous data
-	spi_tx_reg(spi_d, wr_data); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-	while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
-	return (uint16)spi_rx_reg(spi_d); // "... and read the last received data."
+    spi_dev * spi_d = _currentSetting->spi_d;
+    spi_rx_reg(spi_d); // read any previous data
+    spi_tx_reg(spi_d, wr_data); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
+    while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
+    while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
+    return (uint16)spi_rx_reg(spi_d); // "... and read the last received data."
 }
 
 /*  Roger Clark and Victor Perez, 2015
@@ -402,54 +402,54 @@ uint16_t SPIClass::transfer16(uint16_t wr_data) const
 */
 void SPIClass::dmaTransferSet(void *transmitBuf, void *receiveBuf) {
     dma_init(_currentSetting->spiDmaDev);
-	//spi_rx_dma_enable(_currentSetting->spi_d);
-	//spi_tx_dma_enable(_currentSetting->spi_d);
-	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
-	dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
+    //spi_rx_dma_enable(_currentSetting->spi_d);
+    //spi_tx_dma_enable(_currentSetting->spi_d);
+    dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
+    dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
                      receiveBuf, dma_bit_size, (DMA_MINC_MODE | DMA_TRNS_CMPLT ));// receive buffer DMA
-	if (!transmitBuf) {
-	transmitBuf = &ff;
-	dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
+    if (!transmitBuf) {
+    transmitBuf = &ff;
+    dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
                        transmitBuf, dma_bit_size, (DMA_FROM_MEM));// Transmit FF repeatedly
-	}
-	else {
+    }
+    else {
     dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
                        transmitBuf, dma_bit_size, (DMA_MINC_MODE |  DMA_FROM_MEM ));// Transmit buffer DMA
-	}
-	dma_set_priority(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, DMA_PRIORITY_LOW);
-	dma_set_priority(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, DMA_PRIORITY_VERY_HIGH);
+    }
+    dma_set_priority(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, DMA_PRIORITY_LOW);
+    dma_set_priority(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, DMA_PRIORITY_VERY_HIGH);
 }
 
 uint8 SPIClass::dmaTransferRepeat(uint16 length) {
-	if (length == 0) return 0;
-	if (spi_is_rx_nonempty(_currentSetting->spi_d) == 1) spi_rx_reg(_currentSetting->spi_d);
-	_currentSetting->state = SPI_STATE_TRANSFER;
-	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, length);
-	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
-	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);// enable receive
-	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
-	spi_rx_dma_enable(_currentSetting->spi_d);
-	spi_tx_dma_enable(_currentSetting->spi_d);
+    if (length == 0) return 0;
+    if (spi_is_rx_nonempty(_currentSetting->spi_d) == 1) spi_rx_reg(_currentSetting->spi_d);
+    _currentSetting->state = SPI_STATE_TRANSFER;
+    dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, length);
+    dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
+    dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);// enable receive
+    dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
+    spi_rx_dma_enable(_currentSetting->spi_d);
+    spi_tx_dma_enable(_currentSetting->spi_d);
     if (_currentSetting->receiveCallback){
         return 0;
     }
     //uint32_t m = millis();
     uint8 b = 0;
     uint32_t m = millis();
-	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {
-		//Avoid interrupts and just loop waiting for the flag to be set.
-		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
+    while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {
+        //Avoid interrupts and just loop waiting for the flag to be set.
+        if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
     }
 
-	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
-	spi_tx_dma_disable(_currentSetting->spi_d);
-	spi_rx_dma_disable(_currentSetting->spi_d);
+    while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+    while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
+    spi_tx_dma_disable(_currentSetting->spi_d);
+    spi_rx_dma_disable(_currentSetting->spi_d);
     dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
-	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
-	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
-	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
-	_currentSetting->state = SPI_STATE_READY;
+    dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
+    dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
+    dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+    _currentSetting->state = SPI_STATE_READY;
     return b;
 }
 
@@ -461,8 +461,8 @@ uint8 SPIClass::dmaTransferRepeat(uint16 length) {
 */
 
 uint8 SPIClass::dmaTransfer(void *transmitBuf, void *receiveBuf, uint16 length) {
-	dmaTransferSet(transmitBuf, receiveBuf);
-	return dmaTransferRepeat(length);
+    dmaTransferSet(transmitBuf, receiveBuf);
+    return dmaTransferRepeat(length);
 }
 
 /*  Roger Clark and Victor Perez, 2015
@@ -482,29 +482,29 @@ void SPIClass::dmaSendSet(void * transmitBuf, bool minc) {
 }
 
 uint8 SPIClass::dmaSendRepeat(uint16 length) {
-	if (length == 0) return 0;
-	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
-	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
-	_currentSetting->state = SPI_STATE_TRANSMIT;
-	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
-	spi_tx_dma_enable(_currentSetting->spi_d);				  
-	if (_currentSetting->transmitCallback)
-	{
-		return 0;
-	}
-	uint32_t m = millis();
-	uint8 b = 0;
-	while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {
-		//Avoid interrupts and just loop waiting for the flag to be set.
-		if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
-	}
-	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
-	spi_tx_dma_disable(_currentSetting->spi_d);
-	dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
-	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
-	_currentSetting->state = SPI_STATE_READY;
-	return b;
+    if (length == 0) return 0;
+    dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+    dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
+    _currentSetting->state = SPI_STATE_TRANSMIT;
+    dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
+    spi_tx_dma_enable(_currentSetting->spi_d);				  
+    if (_currentSetting->transmitCallback)
+    {
+        return 0;
+    }
+    uint32_t m = millis();
+    uint8 b = 0;
+    while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {
+        //Avoid interrupts and just loop waiting for the flag to be set.
+        if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
+    }
+    while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+    while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
+    spi_tx_dma_disable(_currentSetting->spi_d);
+    dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+    dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+    _currentSetting->state = SPI_STATE_READY;
+    return b;
 }
 
 uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length, bool minc) {
@@ -513,42 +513,42 @@ uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length, bool minc) {
 }
 
 uint8 SPIClass::dmaSendAsync(void * transmitBuf, uint16 length, bool minc) {
-	uint8 b = 0;	
-
-	if (_currentSetting->state != SPI_STATE_READY)
-	{
-
-		uint32_t m = millis();
-		while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
-			//delayMicroseconds(10);
-			if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
-		}		
-		
-		while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
-		while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
-		spi_tx_dma_disable(_currentSetting->spi_d);
-		dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
-		_currentSetting->state = SPI_STATE_READY;
-	}
+    uint8 b = 0;	
+
+    if (_currentSetting->state != SPI_STATE_READY)
+    {
+
+        uint32_t m = millis();
+        while ((dma_get_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel) & DMA_ISR_TCIF1)==0) {//Avoid interrupts and just loop waiting for the flag to be set.
+            //delayMicroseconds(10);
+            if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
+        }		
+        
+        while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+        while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
+        spi_tx_dma_disable(_currentSetting->spi_d);
+        dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+        _currentSetting->state = SPI_STATE_READY;
+    }
 
-	
-	if (length == 0) return 0;
-	uint32 flags = ( (DMA_MINC_MODE*minc) | DMA_FROM_MEM | DMA_TRNS_CMPLT);
+    
+    if (length == 0) return 0;
+    uint32 flags = ( (DMA_MINC_MODE*minc) | DMA_FROM_MEM | DMA_TRNS_CMPLT);
 
-	
-	dma_init(_currentSetting->spiDmaDev);
-	// TX
-	dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
-	dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
-	transmitBuf, dma_bit_size, flags);// Transmit buffer DMA 
-	dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
-	dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
-	dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
-	spi_tx_dma_enable(_currentSetting->spi_d);	
+    
+    dma_init(_currentSetting->spiDmaDev);
+    // TX
+    dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
+    dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
+    transmitBuf, dma_bit_size, flags);// Transmit buffer DMA 
+    dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
+    dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+    dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
+    spi_tx_dma_enable(_currentSetting->spi_d);	
 
-	_currentSetting->state = SPI_STATE_TRANSMIT;
+    _currentSetting->state = SPI_STATE_TRANSMIT;
 
-	return b;
+    return b;
 }
 
 
@@ -558,51 +558,51 @@ uint8 SPIClass::dmaSendAsync(void * transmitBuf, uint16 length, bool minc) {
 */
 
 void SPIClass::onReceive(void(*callback)(void)) {
-	_currentSetting->receiveCallback = callback;
-	if (callback){
-		switch (_currentSetting->spi_d->clk_id) {
-		case RCC_SPI1:
-			dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &SPIClass::_spi1EventCallback);
-			break;
-		case RCC_SPI2:
-			dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &SPIClass::_spi2EventCallback);
-			break;
-			#if BOARD_NR_SPI >= 3
-		case RCC_SPI3:
-			dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &SPIClass::_spi3EventCallback);
-			break;
-			#endif
-		default:
-			ASSERT(0);
-		}
-	}
-	else {
-		dma_detach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
-	}
+    _currentSetting->receiveCallback = callback;
+    if (callback){
+        switch (_currentSetting->spi_d->clk_id) {
+        case RCC_SPI1:
+            dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &SPIClass::_spi1EventCallback);
+            break;
+        case RCC_SPI2:
+            dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &SPIClass::_spi2EventCallback);
+            break;
+            #if BOARD_NR_SPI >= 3
+        case RCC_SPI3:
+            dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, &SPIClass::_spi3EventCallback);
+            break;
+            #endif
+        default:
+            ASSERT(0);
+        }
+    }
+    else {
+        dma_detach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
+    }
 }
 
 void SPIClass::onTransmit(void(*callback)(void)) {
-	_currentSetting->transmitCallback = callback;
-	if (callback){
-		switch (_currentSetting->spi_d->clk_id) {
-		case RCC_SPI1:
-			dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &SPIClass::_spi1EventCallback);
-			break;
-		case RCC_SPI2:
-			dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &SPIClass::_spi2EventCallback);
-			break;
-			#if BOARD_NR_SPI >= 3
-		case RCC_SPI3:
-			dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &SPIClass::_spi3EventCallback);
-			break;
-			#endif
-		default:
-			ASSERT(0);
-		}
-	}
-	else {
-		dma_detach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
-	}
+    _currentSetting->transmitCallback = callback;
+    if (callback){
+        switch (_currentSetting->spi_d->clk_id) {
+        case RCC_SPI1:
+            dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &SPIClass::_spi1EventCallback);
+            break;
+        case RCC_SPI2:
+            dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &SPIClass::_spi2EventCallback);
+            break;
+            #if BOARD_NR_SPI >= 3
+        case RCC_SPI3:
+            dma_attach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &SPIClass::_spi3EventCallback);
+            break;
+            #endif
+        default:
+            ASSERT(0);
+        }
+    }
+    else {
+        dma_detach_interrupt(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+    }
 }
 
 /*
@@ -611,44 +611,44 @@ void SPIClass::onTransmit(void(*callback)(void)) {
 */
 
 void SPIClass::EventCallback() {
-	while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
-	while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0"
-	switch (_currentSetting->state) {
-	case SPI_STATE_TRANSFER:
-		while (spi_is_rx_nonempty(_currentSetting->spi_d));
-		_currentSetting->state = SPI_STATE_READY;
-		spi_tx_dma_disable(_currentSetting->spi_d);
-		spi_rx_dma_disable(_currentSetting->spi_d);
-		//dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
-		//dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
-
-		if (_currentSetting->receiveCallback)
-		{
-			_currentSetting->receiveCallback();
-		}
-		break;
-	case SPI_STATE_TRANSMIT:
-		_currentSetting->state = SPI_STATE_READY;
-		spi_tx_dma_disable(_currentSetting->spi_d);
-		//dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
-		if (_currentSetting->transmitCallback)
-		{
-			_currentSetting->transmitCallback();
-		}
-
-		break;
-	default:
-		// we shouldn't get here, so better to add an assert and fail.
-		return;
-	}
+    while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
+    while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0"
+    switch (_currentSetting->state) {
+    case SPI_STATE_TRANSFER:
+        while (spi_is_rx_nonempty(_currentSetting->spi_d));
+        _currentSetting->state = SPI_STATE_READY;
+        spi_tx_dma_disable(_currentSetting->spi_d);
+        spi_rx_dma_disable(_currentSetting->spi_d);
+        //dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+        //dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel);
+
+        if (_currentSetting->receiveCallback)
+        {
+            _currentSetting->receiveCallback();
+        }
+        break;
+    case SPI_STATE_TRANSMIT:
+        _currentSetting->state = SPI_STATE_READY;
+        spi_tx_dma_disable(_currentSetting->spi_d);
+        //dma_disable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
+        if (_currentSetting->transmitCallback)
+        {
+            _currentSetting->transmitCallback();
+        }
+
+        break;
+    default:
+        // we shouldn't get here, so better to add an assert and fail.
+        return;
+    }
 }
 
 void SPIClass::attachInterrupt(void) {
-	// Should be enableInterrupt()
+    // Should be enableInterrupt()
 }
 
 void SPIClass::detachInterrupt(void) {
-	// Should be disableInterrupt()
+    // Should be disableInterrupt()
 }
 
 /*
@@ -699,11 +699,11 @@ void SPIClass::_spi1EventCallback()
 }
 
 void SPIClass::_spi2EventCallback() {
-	reinterpret_cast<class SPIClass*>(_spi2_this)->EventCallback();
+    reinterpret_cast<class SPIClass*>(_spi2_this)->EventCallback();
 }
 #if BOARD_NR_SPI >= 3
 void SPIClass::_spi3EventCallback() {
-	reinterpret_cast<class SPIClass*>(_spi3_this)->EventCallback();
+    reinterpret_cast<class SPIClass*>(_spi3_this)->EventCallback();
 }
 #endif
 /*
@@ -711,57 +711,57 @@ void SPIClass::_spi3EventCallback() {
 */
 
 static const spi_pins* dev_to_spi_pins(spi_dev *dev) {
-	switch (dev->clk_id) {
+    switch (dev->clk_id) {
 #if BOARD_NR_SPI >= 1
-	case RCC_SPI1: return board_spi_pins;
+    case RCC_SPI1: return board_spi_pins;
 #endif
 #if BOARD_NR_SPI >= 2
-	case RCC_SPI2: return board_spi_pins + 1;
+    case RCC_SPI2: return board_spi_pins + 1;
 #endif
 #if BOARD_NR_SPI >= 3
-	case RCC_SPI3: return board_spi_pins + 2;
+    case RCC_SPI3: return board_spi_pins + 2;
 #endif
-	default:       return NULL;
-	}
+    default:       return NULL;
+    }
 }
 
 static void disable_pwm(const stm32_pin_info *i) {
-	if (i->timer_device) {
-		timer_set_mode(i->timer_device, i->timer_channel, TIMER_DISABLED);
-	}
+    if (i->timer_device) {
+        timer_set_mode(i->timer_device, i->timer_channel, TIMER_DISABLED);
+    }
 }
 
 static void configure_gpios(spi_dev *dev, bool as_master) {
-	const spi_pins *pins = dev_to_spi_pins(dev);
+    const spi_pins *pins = dev_to_spi_pins(dev);
 
-	if (!pins) {
-		return;
-	}
+    if (!pins) {
+        return;
+    }
 
-	const stm32_pin_info *nssi = &PIN_MAP[pins->nss];
-	const stm32_pin_info *scki = &PIN_MAP[pins->sck];
-	const stm32_pin_info *misoi = &PIN_MAP[pins->miso];
-	const stm32_pin_info *mosii = &PIN_MAP[pins->mosi];
+    const stm32_pin_info *nssi = &PIN_MAP[pins->nss];
+    const stm32_pin_info *scki = &PIN_MAP[pins->sck];
+    const stm32_pin_info *misoi = &PIN_MAP[pins->miso];
+    const stm32_pin_info *mosii = &PIN_MAP[pins->mosi];
 
-	disable_pwm(nssi);
-	disable_pwm(scki);
-	disable_pwm(misoi);
-	disable_pwm(mosii);
+    disable_pwm(nssi);
+    disable_pwm(scki);
+    disable_pwm(misoi);
+    disable_pwm(mosii);
 
-	spi_config_gpios(dev, as_master, nssi->gpio_device, nssi->gpio_bit,
-	scki->gpio_device, scki->gpio_bit, misoi->gpio_bit,
-	mosii->gpio_bit);
+    spi_config_gpios(dev, as_master, nssi->gpio_device, nssi->gpio_bit,
+    scki->gpio_device, scki->gpio_bit, misoi->gpio_bit,
+    mosii->gpio_bit);
 }
 
 static const spi_baud_rate baud_rates[8] __FLASH__ = {
-	SPI_BAUD_PCLK_DIV_2,
-	SPI_BAUD_PCLK_DIV_4,
-	SPI_BAUD_PCLK_DIV_8,
-	SPI_BAUD_PCLK_DIV_16,
-	SPI_BAUD_PCLK_DIV_32,
-	SPI_BAUD_PCLK_DIV_64,
-	SPI_BAUD_PCLK_DIV_128,
-	SPI_BAUD_PCLK_DIV_256,
+    SPI_BAUD_PCLK_DIV_2,
+    SPI_BAUD_PCLK_DIV_4,
+    SPI_BAUD_PCLK_DIV_8,
+    SPI_BAUD_PCLK_DIV_16,
+    SPI_BAUD_PCLK_DIV_32,
+    SPI_BAUD_PCLK_DIV_64,
+    SPI_BAUD_PCLK_DIV_128,
+    SPI_BAUD_PCLK_DIV_256,
 };
 
 /*
@@ -769,22 +769,22 @@ static const spi_baud_rate baud_rates[8] __FLASH__ = {
 * (CYCLES_PER_MICROSECOND == 72, APB2 at 72MHz, APB1 at 36MHz).
 */
 static spi_baud_rate determine_baud_rate(spi_dev *dev, uint32_t freq) {
-	uint32_t clock = 0, i;
-	#ifdef SPI_DEBUG
-	Serial.print("determine_baud_rate("); Serial.print(freq); Serial.println(")");
-	#endif
-	switch (rcc_dev_clk(dev->clk_id))
-	{
-	case RCC_APB2: clock = STM32_PCLK2; break; // 72 Mhz
-	case RCC_APB1: clock = STM32_PCLK1; break; // 36 Mhz
-	}
-	clock /= 2;
-	i = 0;
-	while (i < 7 && freq < clock) {
-		clock /= 2;
-		i++;
-	}
-	return baud_rates[i];
+    uint32_t clock = 0, i;
+    #ifdef SPI_DEBUG
+    Serial.print("determine_baud_rate("); Serial.print(freq); Serial.println(")");
+    #endif
+    switch (rcc_dev_clk(dev->clk_id))
+    {
+    case RCC_APB2: clock = STM32_PCLK2; break; // 72 Mhz
+    case RCC_APB1: clock = STM32_PCLK1; break; // 36 Mhz
+    }
+    clock /= 2;
+    i = 0;
+    while (i < 7 && freq < clock) {
+        clock /= 2;
+        i++;
+    }
+    return baud_rates[i];
 }
 
 SPIClass SPI(1);

From 0393be34008f663b99141d46a9919b901e522dac Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sat, 15 Jul 2017 18:31:02 +1000
Subject: [PATCH 145/307] Added setClock() to Wire and Hardware - only 100000Hz
 and 400000Hz are supported

---
 STM32F1/libraries/Wire/HardWire.cpp | 15 +++++++++++++++
 STM32F1/libraries/Wire/HardWire.h   |  1 +
 STM32F1/libraries/Wire/Wire.cpp     | 26 ++++++++++++++++++++++++--
 STM32F1/libraries/Wire/Wire.h       |  9 ++++++++-
 4 files changed, 48 insertions(+), 3 deletions(-)

diff --git a/STM32F1/libraries/Wire/HardWire.cpp b/STM32F1/libraries/Wire/HardWire.cpp
index d81f584ae..51af7ad76 100644
--- a/STM32F1/libraries/Wire/HardWire.cpp
+++ b/STM32F1/libraries/Wire/HardWire.cpp
@@ -84,3 +84,18 @@ void HardWire::end() {
     i2c_disable(sel_hard);
     sel_hard = 0;
 }
+
+void HardWire::setClock(uint32_t frequencyHz)
+{
+	switch(frequencyHz)
+	{
+		case 400000:
+			dev_flags |= I2C_FAST_MODE;// set FAST_MODE bit
+			break;
+		case 100000:
+		default:
+			dev_flags &= ~I2C_FAST_MODE;// clear FAST_MODE bit
+			break;
+	}
+	
+}
diff --git a/STM32F1/libraries/Wire/HardWire.h b/STM32F1/libraries/Wire/HardWire.h
index bf59a2f24..4d49e1a28 100644
--- a/STM32F1/libraries/Wire/HardWire.h
+++ b/STM32F1/libraries/Wire/HardWire.h
@@ -66,6 +66,7 @@ class HardWire : public WireBase {
 	 */
 	void end();
 
+	void setClock(uint32_t frequencyHz);
     /*
      * Disables the I2C device and remove the device address.
      */
diff --git a/STM32F1/libraries/Wire/Wire.cpp b/STM32F1/libraries/Wire/Wire.cpp
index fff850be8..712adf45b 100644
--- a/STM32F1/libraries/Wire/Wire.cpp
+++ b/STM32F1/libraries/Wire/Wire.cpp
@@ -56,7 +56,9 @@
 
 void TwoWire::set_scl(bool state) {
     I2C_DELAY(this->i2c_delay);
-    digitalWrite(this->scl_pin,state);
+
+	gpio_write_bit(sclDevice,sclBit, state);
+//    digitalWrite(this->scl_pin,state);
     //Allow for clock stretching - dangerous currently
     if (state == HIGH) {
         while(digitalRead(this->scl_pin) == 0);
@@ -65,7 +67,8 @@ void TwoWire::set_scl(bool state) {
 
 void TwoWire::set_sda(bool state) {
 	I2C_DELAY(this->i2c_delay);
-    digitalWrite(this->sda_pin, state);
+	gpio_write_bit(sdaDevice,sdaBit, state);
+    //digitalWrite(this->sda_pin, state);
 }
 
 void TwoWire::i2c_start() {
@@ -198,6 +201,11 @@ void TwoWire::begin(uint8 self_addr) {
     rx_buf_len = 0;
     pinMode(this->scl_pin, OUTPUT_OPEN_DRAIN);
     pinMode(this->sda_pin, OUTPUT_OPEN_DRAIN);
+	
+	sclDevice = PIN_MAP[this->scl_pin].gpio_device;
+	sclBit = PIN_MAP[this->scl_pin].gpio_bit;	
+	sdaDevice = PIN_MAP[this->sda_pin].gpio_device;
+	sdaBit = PIN_MAP[this->sda_pin].gpio_bit;		
     set_scl(HIGH);
     set_sda(HIGH);
 }
@@ -214,6 +222,20 @@ void TwoWire::end()
 	}
 }
 
+void TwoWire::setClock(uint32_t frequencyHz)
+{
+	switch(frequencyHz)
+	{
+		case 400000:
+			i2c_delay = SOFT_FAST;
+			break;
+		case 100000:
+		default:
+			i2c_delay = SOFT_STANDARD;
+			break;
+	}
+}
+
 TwoWire::~TwoWire() {
     this->scl_pin=0;
     this->sda_pin=0;
diff --git a/STM32F1/libraries/Wire/Wire.h b/STM32F1/libraries/Wire/Wire.h
index df474da7c..8fbddaae9 100644
--- a/STM32F1/libraries/Wire/Wire.h
+++ b/STM32F1/libraries/Wire/Wire.h
@@ -50,7 +50,7 @@
 #define SDA PB7
 #define SCL PB6
 
-#define SOFT_STANDARD 27
+#define SOFT_STANDARD 19
 #define SOFT_FAST 0
 
 
@@ -126,6 +126,11 @@ class TwoWire : public WireBase {
      */
     uint8 process(uint8);
     uint8 process();
+ private:
+	gpio_dev 	*sdaDevice;
+	uint8 		sdaBit;
+	gpio_dev 	*sclDevice;
+	uint8 		sclBit;	
  public:
     /*
      * Accept pin numbers for SCL and SDA lines. Set the delay needed
@@ -139,6 +144,8 @@ class TwoWire : public WireBase {
      * .begin(uint8) in WireBase
      */
     void begin(uint8 = 0x00);
+	
+	void setClock(uint32_t frequencyHz);
 
     /*
      * Sets pins SDA and SCL to INPUT

From 4bfb444447905cd04c833d6538b6a0cee27f0d6a Mon Sep 17 00:00:00 2001
From: Cristi Marius Tiutiu <mtiutiu@gmail.com>
Date: Mon, 17 Jul 2017 10:35:23 +0300
Subject: [PATCH 146/307] added teensy like ide compiler opts menus

---
 STM32F1/boards.txt   | 419 ++++++++++++++++++++++++++++++++++++++++++-
 STM32F1/platform.txt |  10 +-
 STM32F3/boards.txt   |  32 ++++
 STM32F3/platform.txt |   8 +-
 STM32F4/boards.txt   | 132 +++++++++++++-
 STM32F4/platform.txt |   8 +-
 6 files changed, 593 insertions(+), 16 deletions(-)

diff --git a/STM32F1/boards.txt b/STM32F1/boards.txt
index 10a6591e6..b52623640 100644
--- a/STM32F1/boards.txt
+++ b/STM32F1/boards.txt
@@ -4,6 +4,7 @@ menu.device_variant=Variant
 menu.bootloader_version=Bootloader version
 menu.upload_method=Upload method
 menu.cpu_speed=CPU Speed(MHz)
+menu.opt=Optimize
 
 ##############################################################
 mapleMini.name=Maple Mini
@@ -43,6 +44,38 @@ mapleMini.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
 mapleMini.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
 mapleMini.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
 
+#-- Optimizations
+mapleMini.menu.opt.o2std=Faster
+mapleMini.menu.opt.o2std.build.flags.optimize=-O2
+mapleMini.menu.opt.o2std.build.flags.ldspecs=
+mapleMini.menu.opt.o2lto=Faster with LTO
+mapleMini.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+mapleMini.menu.opt.o2lto.build.flags.ldspecs=-flto
+mapleMini.menu.opt.o1std=Fast
+mapleMini.menu.opt.o1std.build.flags.optimize=-O1
+mapleMini.menu.opt.o1std.build.flags.ldspecs=
+mapleMini.menu.opt.o1lto=Fast with LTO
+mapleMini.menu.opt.o1lto.build.flags.optimize=-O1 -flto
+mapleMini.menu.opt.o1lto.build.flags.ldspecs=-flto
+mapleMini.menu.opt.o3std=Fastest
+mapleMini.menu.opt.o3std.build.flags.optimize=-O3
+mapleMini.menu.opt.o3std.build.flags.ldspecs=
+mapleMini.menu.opt.o3lto=Fastest with LTO
+mapleMini.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+mapleMini.menu.opt.o3lto.build.flags.ldspecs=-flto
+mapleMini.menu.opt.ogstd=Debug
+mapleMini.menu.opt.ogstd.build.flags.optimize=-Og
+mapleMini.menu.opt.ogstd.build.flags.ldspecs=
+mapleMini.menu.opt.oglto=Debug with LTO
+mapleMini.menu.opt.oglto.build.flags.optimize=-Og -flto
+mapleMini.menu.opt.oglto.build.flags.ldspecs=-flto
+mapleMini.menu.opt.osstd=Smallest Code
+mapleMini.menu.opt.osstd.build.flags.optimize=-Os
+mapleMini.menu.opt.osstd.build.flags.ldspecs=
+mapleMini.menu.opt.oslto=Smallest Code with LTO
+mapleMini.menu.opt.oslto.build.flags.optimize=-Os -flto
+mapleMini.menu.opt.oslto.build.flags.ldspecs=-flto
+
 
 ##############################################################
 maple.name=Maple (Rev 3)
@@ -66,6 +99,38 @@ maple.build.ldscript=ld/flash.ld
 maple.build.variant=maple
 maple.build.vect=VECT_TAB_ADDR=0x8005000
 
+#-- Optimizations
+maple.menu.opt.o2std=Faster
+maple.menu.opt.o2std.build.flags.optimize=-O2
+maple.menu.opt.o2std.build.flags.ldspecs=
+maple.menu.opt.o2lto=Faster with LTO
+maple.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+maple.menu.opt.o2lto.build.flags.ldspecs=-flto
+maple.menu.opt.o1std=Fast
+maple.menu.opt.o1std.build.flags.optimize=-O1
+maple.menu.opt.o1std.build.flags.ldspecs=
+maple.menu.opt.o1lto=Fast with LTO
+maple.menu.opt.o1lto.build.flags.optimize=-O1 -flto
+maple.menu.opt.o1lto.build.flags.ldspecs=-flto
+maple.menu.opt.o3std=Fastest
+maple.menu.opt.o3std.build.flags.optimize=-O3
+maple.menu.opt.o3std.build.flags.ldspecs=
+maple.menu.opt.o3lto=Fastest with LTO
+maple.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+maple.menu.opt.o3lto.build.flags.ldspecs=-flto
+maple.menu.opt.ogstd=Debug
+maple.menu.opt.ogstd.build.flags.optimize=-Og
+maple.menu.opt.ogstd.build.flags.ldspecs=
+maple.menu.opt.oglto=Debug with LTO
+maple.menu.opt.oglto.build.flags.optimize=-Og -flto
+maple.menu.opt.oglto.build.flags.ldspecs=-flto
+maple.menu.opt.osstd=Smallest Code
+maple.menu.opt.osstd.build.flags.optimize=-Os
+maple.menu.opt.osstd.build.flags.ldspecs=
+maple.menu.opt.oslto=Smallest Code with LTO
+maple.menu.opt.oslto.build.flags.optimize=-Os -flto
+maple.menu.opt.oslto.build.flags.ldspecs=-flto
+
 ##############################################################
 mapleRET6.name=Maple (RET6)
 
@@ -89,6 +154,38 @@ mapleRET6.upload.usbID=1EAF:0003
 mapleRET6.upload.altID=1
 mapleRET6.upload.auto_reset=true
 
+#-- Optimizations
+mapleRET6.menu.opt.o2std=Faster
+mapleRET6.menu.opt.o2std.build.flags.optimize=-O2
+mapleRET6.menu.opt.o2std.build.flags.ldspecs=
+mapleRET6.menu.opt.o2lto=Faster with LTO
+mapleRET6.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+mapleRET6.menu.opt.o2lto.build.flags.ldspecs=-flto
+mapleRET6.menu.opt.o1std=Fast
+mapleRET6.menu.opt.o1std.build.flags.optimize=-O1
+mapleRET6.menu.opt.o1std.build.flags.ldspecs=
+mapleRET6.menu.opt.o1lto=Fast with LTO
+mapleRET6.menu.opt.o1lto.build.flags.optimize=-O1 -flto
+mapleRET6.menu.opt.o1lto.build.flags.ldspecs=-flto
+mapleRET6.menu.opt.o3std=Fastest
+mapleRET6.menu.opt.o3std.build.flags.optimize=-O3
+mapleRET6.menu.opt.o3std.build.flags.ldspecs=
+mapleRET6.menu.opt.o3lto=Fastest with LTO
+mapleRET6.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+mapleRET6.menu.opt.o3lto.build.flags.ldspecs=-flto
+mapleRET6.menu.opt.ogstd=Debug
+mapleRET6.menu.opt.ogstd.build.flags.optimize=-Og
+mapleRET6.menu.opt.ogstd.build.flags.ldspecs=
+mapleRET6.menu.opt.oglto=Debug with LTO
+mapleRET6.menu.opt.oglto.build.flags.optimize=-Og -flto
+mapleRET6.menu.opt.oglto.build.flags.ldspecs=-flto
+mapleRET6.menu.opt.osstd=Smallest Code
+mapleRET6.menu.opt.osstd.build.flags.optimize=-Os
+mapleRET6.menu.opt.osstd.build.flags.ldspecs=
+mapleRET6.menu.opt.oslto=Smallest Code with LTO
+mapleRET6.menu.opt.oslto.build.flags.optimize=-Os -flto
+mapleRET6.menu.opt.oslto.build.flags.ldspecs=-flto
+
 ##############################################################
 
 microduino32_flash.name=Microduino Core STM32 to Flash
@@ -120,6 +217,38 @@ microduino32_flash.build.error_led_port=GPIOB
 microduino32_flash.build.error_led_pin=1
 microduino32_flash.build.gcc_ver=gcc-arm-none-eabi-4.8.3-2014q1
 
+#-- Optimizations
+microduino32_flash.menu.opt.o2std=Faster
+microduino32_flash.menu.opt.o2std.build.flags.optimize=-O2
+microduino32_flash.menu.opt.o2std.build.flags.ldspecs=
+microduino32_flash.menu.opt.o2lto=Faster with LTO
+microduino32_flash.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+microduino32_flash.menu.opt.o2lto.build.flags.ldspecs=-flto
+microduino32_flash.menu.opt.o1std=Fast
+microduino32_flash.menu.opt.o1std.build.flags.optimize=-O1
+microduino32_flash.menu.opt.o1std.build.flags.ldspecs=
+microduino32_flash.menu.opt.o1lto=Fast with LTO
+microduino32_flash.menu.opt.o1lto.build.flags.optimize=-O1 -flto
+microduino32_flash.menu.opt.o1lto.build.flags.ldspecs=-flto
+microduino32_flash.menu.opt.o3std=Fastest
+microduino32_flash.menu.opt.o3std.build.flags.optimize=-O3
+microduino32_flash.menu.opt.o3std.build.flags.ldspecs=
+microduino32_flash.menu.opt.o3lto=Fastest with LTO
+microduino32_flash.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+microduino32_flash.menu.opt.o3lto.build.flags.ldspecs=-flto
+microduino32_flash.menu.opt.ogstd=Debug
+microduino32_flash.menu.opt.ogstd.build.flags.optimize=-Og
+microduino32_flash.menu.opt.ogstd.build.flags.ldspecs=
+microduino32_flash.menu.opt.oglto=Debug with LTO
+microduino32_flash.menu.opt.oglto.build.flags.optimize=-Og -flto
+microduino32_flash.menu.opt.oglto.build.flags.ldspecs=-flto
+microduino32_flash.menu.opt.osstd=Smallest Code
+microduino32_flash.menu.opt.osstd.build.flags.optimize=-Os
+microduino32_flash.menu.opt.osstd.build.flags.ldspecs=
+microduino32_flash.menu.opt.oslto=Smallest Code with LTO
+microduino32_flash.menu.opt.oslto.build.flags.optimize=-Os -flto
+microduino32_flash.menu.opt.oslto.build.flags.ldspecs=-flto
+
 ##############################################################
 nucleo_f103rb.name=STM Nucleo F103RB (STLink)
 
@@ -158,6 +287,38 @@ nucleo_f103rb.menu.device_variant.NucleoF103_HSE=Nucleo F103 @ 72 MHz w/ crystal
 nucleo_f103rb.menu.device_variant.NucleoF103_HSE.build.f_cpu=72000000L
 nucleo_f103rb.menu.device_variant.NucleoF103_HSE.build.extra_flags=-DNUCLEO_HSE_CRYSTAL -DMCU_STM32F103RB -mthumb -march=armv7-m -D__STM32F1__
 
+#-- Optimizations
+nucleo_f103rb.menu.opt.o2std=Faster
+nucleo_f103rb.menu.opt.o2std.build.flags.optimize=-O2
+nucleo_f103rb.menu.opt.o2std.build.flags.ldspecs=
+nucleo_f103rb.menu.opt.o2lto=Faster with LTO
+nucleo_f103rb.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+nucleo_f103rb.menu.opt.o2lto.build.flags.ldspecs=-flto
+nucleo_f103rb.menu.opt.o1std=Fast
+nucleo_f103rb.menu.opt.o1std.build.flags.optimize=-O1
+nucleo_f103rb.menu.opt.o1std.build.flags.ldspecs=
+nucleo_f103rb.menu.opt.o1lto=Fast with LTO
+nucleo_f103rb.menu.opt.o1lto.build.flags.optimize=-O1 -flto
+nucleo_f103rb.menu.opt.o1lto.build.flags.ldspecs=-flto
+nucleo_f103rb.menu.opt.o3std=Fastest
+nucleo_f103rb.menu.opt.o3std.build.flags.optimize=-O3
+nucleo_f103rb.menu.opt.o3std.build.flags.ldspecs=
+nucleo_f103rb.menu.opt.o3lto=Fastest with LTO
+nucleo_f103rb.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+nucleo_f103rb.menu.opt.o3lto.build.flags.ldspecs=-flto
+nucleo_f103rb.menu.opt.ogstd=Debug
+nucleo_f103rb.menu.opt.ogstd.build.flags.optimize=-Og
+nucleo_f103rb.menu.opt.ogstd.build.flags.ldspecs=
+nucleo_f103rb.menu.opt.oglto=Debug with LTO
+nucleo_f103rb.menu.opt.oglto.build.flags.optimize=-Og -flto
+nucleo_f103rb.menu.opt.oglto.build.flags.ldspecs=-flto
+nucleo_f103rb.menu.opt.osstd=Smallest Code
+nucleo_f103rb.menu.opt.osstd.build.flags.optimize=-Os
+nucleo_f103rb.menu.opt.osstd.build.flags.ldspecs=
+nucleo_f103rb.menu.opt.oslto=Smallest Code with LTO
+nucleo_f103rb.menu.opt.oslto.build.flags.optimize=-Os -flto
+nucleo_f103rb.menu.opt.oslto.build.flags.ldspecs=-flto
+
 ###################### Generic STM32F103C ########################################
 
 genericSTM32F103C.name=Generic STM32F103C series
@@ -223,6 +384,38 @@ genericSTM32F103C.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
 genericSTM32F103C.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
 genericSTM32F103C.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
 
+#-- Optimizations
+genericSTM32F103C.menu.opt.o2std=Faster
+genericSTM32F103C.menu.opt.o2std.build.flags.optimize=-O2
+genericSTM32F103C.menu.opt.o2std.build.flags.ldspecs=
+genericSTM32F103C.menu.opt.o2lto=Faster with LTO
+genericSTM32F103C.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+genericSTM32F103C.menu.opt.o2lto.build.flags.ldspecs=-flto
+genericSTM32F103C.menu.opt.o1std=Fast
+genericSTM32F103C.menu.opt.o1std.build.flags.optimize=-O1
+genericSTM32F103C.menu.opt.o1std.build.flags.ldspecs=
+genericSTM32F103C.menu.opt.o1lto=Fast with LTO
+genericSTM32F103C.menu.opt.o1lto.build.flags.optimize=-O1 -flto
+genericSTM32F103C.menu.opt.o1lto.build.flags.ldspecs=-flto
+genericSTM32F103C.menu.opt.o3std=Fastest
+genericSTM32F103C.menu.opt.o3std.build.flags.optimize=-O3
+genericSTM32F103C.menu.opt.o3std.build.flags.ldspecs=
+genericSTM32F103C.menu.opt.o3lto=Fastest with LTO
+genericSTM32F103C.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+genericSTM32F103C.menu.opt.o3lto.build.flags.ldspecs=-flto
+genericSTM32F103C.menu.opt.ogstd=Debug
+genericSTM32F103C.menu.opt.ogstd.build.flags.optimize=-Og
+genericSTM32F103C.menu.opt.ogstd.build.flags.ldspecs=
+genericSTM32F103C.menu.opt.oglto=Debug with LTO
+genericSTM32F103C.menu.opt.oglto.build.flags.optimize=-Og -flto
+genericSTM32F103C.menu.opt.oglto.build.flags.ldspecs=-flto
+genericSTM32F103C.menu.opt.osstd=Smallest Code
+genericSTM32F103C.menu.opt.osstd.build.flags.optimize=-Os
+genericSTM32F103C.menu.opt.osstd.build.flags.ldspecs=
+genericSTM32F103C.menu.opt.oslto=Smallest Code with LTO
+genericSTM32F103C.menu.opt.oslto.build.flags.optimize=-Os -flto
+genericSTM32F103C.menu.opt.oslto.build.flags.ldspecs=-flto
+
 ########################### Generic STM32F103R ###########################
 
 genericSTM32F103R.name=Generic STM32F103R series
@@ -292,6 +485,38 @@ genericSTM32F103R.menu.upload_method.BMPMethod.upload.protocol=gdb_bmp
 genericSTM32F103R.menu.upload_method.BMPMethod.upload.tool=bmp_upload
 genericSTM32F103R.menu.upload_method.BMPMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG
 
+#-- Optimizations
+genericSTM32F103R.menu.opt.o2std=Faster
+genericSTM32F103R.menu.opt.o2std.build.flags.optimize=-O2
+genericSTM32F103R.menu.opt.o2std.build.flags.ldspecs=
+genericSTM32F103R.menu.opt.o2lto=Faster with LTO
+genericSTM32F103R.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+genericSTM32F103R.menu.opt.o2lto.build.flags.ldspecs=-flto
+genericSTM32F103R.menu.opt.o1std=Fast
+genericSTM32F103R.menu.opt.o1std.build.flags.optimize=-O1
+genericSTM32F103R.menu.opt.o1std.build.flags.ldspecs=
+genericSTM32F103R.menu.opt.o1lto=Fast with LTO
+genericSTM32F103R.menu.opt.o1lto.build.flags.optimize=-O1 -flto
+genericSTM32F103R.menu.opt.o1lto.build.flags.ldspecs=-flto
+genericSTM32F103R.menu.opt.o3std=Fastest
+genericSTM32F103R.menu.opt.o3std.build.flags.optimize=-O3
+genericSTM32F103R.menu.opt.o3std.build.flags.ldspecs=
+genericSTM32F103R.menu.opt.o3lto=Fastest with LTO
+genericSTM32F103R.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+genericSTM32F103R.menu.opt.o3lto.build.flags.ldspecs=-flto
+genericSTM32F103R.menu.opt.ogstd=Debug
+genericSTM32F103R.menu.opt.ogstd.build.flags.optimize=-Og
+genericSTM32F103R.menu.opt.ogstd.build.flags.ldspecs=
+genericSTM32F103R.menu.opt.oglto=Debug with LTO
+genericSTM32F103R.menu.opt.oglto.build.flags.optimize=-Og -flto
+genericSTM32F103R.menu.opt.oglto.build.flags.ldspecs=-flto
+genericSTM32F103R.menu.opt.osstd=Smallest Code
+genericSTM32F103R.menu.opt.osstd.build.flags.optimize=-Os
+genericSTM32F103R.menu.opt.osstd.build.flags.ldspecs=
+genericSTM32F103R.menu.opt.oslto=Smallest Code with LTO
+genericSTM32F103R.menu.opt.oslto.build.flags.optimize=-Os -flto
+genericSTM32F103R.menu.opt.oslto.build.flags.ldspecs=-flto
+
 ###################### Generic STM32F103T ########################################
 
 genericSTM32F103T.name=Generic STM32F103T series
@@ -345,6 +570,38 @@ genericSTM32F103T.menu.upload_method.BMPMethod.upload.protocol=gdb_bmp
 genericSTM32F103T.menu.upload_method.BMPMethod.upload.tool=bmp_upload
 genericSTM32F103T.menu.upload_method.BMPMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG
 
+#-- Optimizations
+genericSTM32F103T.menu.opt.o2std=Faster
+genericSTM32F103T.menu.opt.o2std.build.flags.optimize=-O2
+genericSTM32F103T.menu.opt.o2std.build.flags.ldspecs=
+genericSTM32F103T.menu.opt.o2lto=Faster with LTO
+genericSTM32F103T.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+genericSTM32F103T.menu.opt.o2lto.build.flags.ldspecs=-flto
+genericSTM32F103T.menu.opt.o1std=Fast
+genericSTM32F103T.menu.opt.o1std.build.flags.optimize=-O1
+genericSTM32F103T.menu.opt.o1std.build.flags.ldspecs=
+genericSTM32F103T.menu.opt.o1lto=Fast with LTO
+genericSTM32F103T.menu.opt.o1lto.build.flags.optimize=-O1 -flto
+genericSTM32F103T.menu.opt.o1lto.build.flags.ldspecs=-flto
+genericSTM32F103T.menu.opt.o3std=Fastest
+genericSTM32F103T.menu.opt.o3std.build.flags.optimize=-O3
+genericSTM32F103T.menu.opt.o3std.build.flags.ldspecs=
+genericSTM32F103T.menu.opt.o3lto=Fastest with LTO
+genericSTM32F103T.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+genericSTM32F103T.menu.opt.o3lto.build.flags.ldspecs=-flto
+genericSTM32F103T.menu.opt.ogstd=Debug
+genericSTM32F103T.menu.opt.ogstd.build.flags.optimize=-Og
+genericSTM32F103T.menu.opt.ogstd.build.flags.ldspecs=
+genericSTM32F103T.menu.opt.oglto=Debug with LTO
+genericSTM32F103T.menu.opt.oglto.build.flags.optimize=-Og -flto
+genericSTM32F103T.menu.opt.oglto.build.flags.ldspecs=-flto
+genericSTM32F103T.menu.opt.osstd=Smallest Code
+genericSTM32F103T.menu.opt.osstd.build.flags.optimize=-Os
+genericSTM32F103T.menu.opt.osstd.build.flags.ldspecs=
+genericSTM32F103T.menu.opt.oslto=Smallest Code with LTO
+genericSTM32F103T.menu.opt.oslto.build.flags.optimize=-Os -flto
+genericSTM32F103T.menu.opt.oslto.build.flags.ldspecs=-flto
+
 ########################### Generic STM32F103V ###########################
 
 genericSTM32F103V.name=Generic STM32F103V series
@@ -405,6 +662,38 @@ genericSTM32F103V.menu.upload_method.BMPMethod.upload.protocol=gdb_bmp
 genericSTM32F103V.menu.upload_method.BMPMethod.upload.tool=bmp_upload
 genericSTM32F103V.menu.upload_method.BMPMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG
 
+#-- Optimizations
+genericSTM32F103V.menu.opt.o2std=Faster
+genericSTM32F103V.menu.opt.o2std.build.flags.optimize=-O2
+genericSTM32F103V.menu.opt.o2std.build.flags.ldspecs=
+genericSTM32F103V.menu.opt.o2lto=Faster with LTO
+genericSTM32F103V.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+genericSTM32F103V.menu.opt.o2lto.build.flags.ldspecs=-flto
+genericSTM32F103V.menu.opt.o1std=Fast
+genericSTM32F103V.menu.opt.o1std.build.flags.optimize=-O1
+genericSTM32F103V.menu.opt.o1std.build.flags.ldspecs=
+genericSTM32F103V.menu.opt.o1lto=Fast with LTO
+genericSTM32F103V.menu.opt.o1lto.build.flags.optimize=-O1 -flto
+genericSTM32F103V.menu.opt.o1lto.build.flags.ldspecs=-flto
+genericSTM32F103V.menu.opt.o3std=Fastest
+genericSTM32F103V.menu.opt.o3std.build.flags.optimize=-O3
+genericSTM32F103V.menu.opt.o3std.build.flags.ldspecs=
+genericSTM32F103V.menu.opt.o3lto=Fastest with LTO
+genericSTM32F103V.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+genericSTM32F103V.menu.opt.o3lto.build.flags.ldspecs=-flto
+genericSTM32F103V.menu.opt.ogstd=Debug
+genericSTM32F103V.menu.opt.ogstd.build.flags.optimize=-Og
+genericSTM32F103V.menu.opt.ogstd.build.flags.ldspecs=
+genericSTM32F103V.menu.opt.oglto=Debug with LTO
+genericSTM32F103V.menu.opt.oglto.build.flags.optimize=-Og -flto
+genericSTM32F103V.menu.opt.oglto.build.flags.ldspecs=-flto
+genericSTM32F103V.menu.opt.osstd=Smallest Code
+genericSTM32F103V.menu.opt.osstd.build.flags.optimize=-Os
+genericSTM32F103V.menu.opt.osstd.build.flags.ldspecs=
+genericSTM32F103V.menu.opt.oslto=Smallest Code with LTO
+genericSTM32F103V.menu.opt.oslto.build.flags.optimize=-Os -flto
+genericSTM32F103V.menu.opt.oslto.build.flags.ldspecs=-flto
+
 ########################### Generic STM32F103Z ###########################
 
 genericSTM32F103Z.name=Generic STM32F103Z series
@@ -462,6 +751,38 @@ genericSTM32F103Z.menu.upload_method.BMPMethod.upload.protocol=gdb_bmp
 genericSTM32F103Z.menu.upload_method.BMPMethod.upload.tool=bmp_upload
 genericSTM32F103Z.menu.upload_method.BMPMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG
 
+#-- Optimizations
+genericSTM32F103Z.menu.opt.o2std=Faster
+genericSTM32F103Z.menu.opt.o2std.build.flags.optimize=-O2
+genericSTM32F103Z.menu.opt.o2std.build.flags.ldspecs=
+genericSTM32F103Z.menu.opt.o2lto=Faster with LTO
+genericSTM32F103Z.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+genericSTM32F103Z.menu.opt.o2lto.build.flags.ldspecs=-flto
+genericSTM32F103Z.menu.opt.o1std=Fast
+genericSTM32F103Z.menu.opt.o1std.build.flags.optimize=-O1
+genericSTM32F103Z.menu.opt.o1std.build.flags.ldspecs=
+genericSTM32F103Z.menu.opt.o1lto=Fast with LTO
+genericSTM32F103Z.menu.opt.o1lto.build.flags.optimize=-O1 -flto
+genericSTM32F103Z.menu.opt.o1lto.build.flags.ldspecs=-flto
+genericSTM32F103Z.menu.opt.o3std=Fastest
+genericSTM32F103Z.menu.opt.o3std.build.flags.optimize=-O3
+genericSTM32F103Z.menu.opt.o3std.build.flags.ldspecs=
+genericSTM32F103Z.menu.opt.o3lto=Fastest with LTO
+genericSTM32F103Z.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+genericSTM32F103Z.menu.opt.o3lto.build.flags.ldspecs=-flto
+genericSTM32F103Z.menu.opt.ogstd=Debug
+genericSTM32F103Z.menu.opt.ogstd.build.flags.optimize=-Og
+genericSTM32F103Z.menu.opt.ogstd.build.flags.ldspecs=
+genericSTM32F103Z.menu.opt.oglto=Debug with LTO
+genericSTM32F103Z.menu.opt.oglto.build.flags.optimize=-Og -flto
+genericSTM32F103Z.menu.opt.oglto.build.flags.ldspecs=-flto
+genericSTM32F103Z.menu.opt.osstd=Smallest Code
+genericSTM32F103Z.menu.opt.osstd.build.flags.optimize=-Os
+genericSTM32F103Z.menu.opt.osstd.build.flags.ldspecs=
+genericSTM32F103Z.menu.opt.oslto=Smallest Code with LTO
+genericSTM32F103Z.menu.opt.oslto.build.flags.optimize=-Os -flto
+genericSTM32F103Z.menu.opt.oslto.build.flags.ldspecs=-flto
+
 ###################### HYTiny STM32F103T ########################################
 
 hytiny-stm32f103t.name=HYTiny STM32F103TB
@@ -513,6 +834,37 @@ hytiny-stm32f103t.menu.upload_method.jlinkMethod.upload.protocol=jlink
 hytiny-stm32f103t.menu.upload_method.jlinkMethod.upload.tool=jlink_upload
 hytiny-stm32f103t.menu.upload_method.jlinkMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG=1 -DSERIAL_USB -DGENERIC_BOOTLOADER 
 
+#-- Optimizations
+hytiny-stm32f103t.menu.opt.o2std=Faster
+hytiny-stm32f103t.menu.opt.o2std.build.flags.optimize=-O2
+hytiny-stm32f103t.menu.opt.o2std.build.flags.ldspecs=
+hytiny-stm32f103t.menu.opt.o2lto=Faster with LTO
+hytiny-stm32f103t.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+hytiny-stm32f103t.menu.opt.o2lto.build.flags.ldspecs=-flto
+hytiny-stm32f103t.menu.opt.o1std=Fast
+hytiny-stm32f103t.menu.opt.o1std.build.flags.optimize=-O1
+hytiny-stm32f103t.menu.opt.o1std.build.flags.ldspecs=
+hytiny-stm32f103t.menu.opt.o1lto=Fast with LTO
+hytiny-stm32f103t.menu.opt.o1lto.build.flags.optimize=-O1 -flto
+hytiny-stm32f103t.menu.opt.o1lto.build.flags.ldspecs=-flto
+hytiny-stm32f103t.menu.opt.o3std=Fastest
+hytiny-stm32f103t.menu.opt.o3std.build.flags.optimize=-O3
+hytiny-stm32f103t.menu.opt.o3std.build.flags.ldspecs=
+hytiny-stm32f103t.menu.opt.o3lto=Fastest with LTO
+hytiny-stm32f103t.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+hytiny-stm32f103t.menu.opt.o3lto.build.flags.ldspecs=-flto
+hytiny-stm32f103t.menu.opt.ogstd=Debug
+hytiny-stm32f103t.menu.opt.ogstd.build.flags.optimize=-Og
+hytiny-stm32f103t.menu.opt.ogstd.build.flags.ldspecs=
+hytiny-stm32f103t.menu.opt.oglto=Debug with LTO
+hytiny-stm32f103t.menu.opt.oglto.build.flags.optimize=-Og -flto
+hytiny-stm32f103t.menu.opt.oglto.build.flags.ldspecs=-flto
+hytiny-stm32f103t.menu.opt.osstd=Smallest Code
+hytiny-stm32f103t.menu.opt.osstd.build.flags.optimize=-Os
+hytiny-stm32f103t.menu.opt.osstd.build.flags.ldspecs=
+hytiny-stm32f103t.menu.opt.oslto=Smallest Code with LTO
+hytiny-stm32f103t.menu.opt.oslto.build.flags.optimize=-Os -flto
+hytiny-stm32f103t.menu.opt.oslto.build.flags.ldspecs=-flto
 
 ###################### Generic GD32F103C  ########################################
 
@@ -576,6 +928,38 @@ genericGD32F103C.menu.cpu_speed.speed_96mhz.build.f_cpu=96000000L
 genericGD32F103C.menu.cpu_speed.speed_72mhz=72Mhz (compatibility)
 genericGD32F103C.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
 
+#-- Optimizations
+genericGD32F103C.menu.opt.o2std=Faster
+genericGD32F103C.menu.opt.o2std.build.flags.optimize=-O2
+genericGD32F103C.menu.opt.o2std.build.flags.ldspecs=
+genericGD32F103C.menu.opt.o2lto=Faster with LTO
+genericGD32F103C.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+genericGD32F103C.menu.opt.o2lto.build.flags.ldspecs=-flto
+genericGD32F103C.menu.opt.o1std=Fast
+genericGD32F103C.menu.opt.o1std.build.flags.optimize=-O1
+genericGD32F103C.menu.opt.o1std.build.flags.ldspecs=
+genericGD32F103C.menu.opt.o1lto=Fast with LTO
+genericGD32F103C.menu.opt.o1lto.build.flags.optimize=-O1 -flto
+genericGD32F103C.menu.opt.o1lto.build.flags.ldspecs=-flto
+genericGD32F103C.menu.opt.o3std=Fastest
+genericGD32F103C.menu.opt.o3std.build.flags.optimize=-O3
+genericGD32F103C.menu.opt.o3std.build.flags.ldspecs=
+genericGD32F103C.menu.opt.o3lto=Fastest with LTO
+genericGD32F103C.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+genericGD32F103C.menu.opt.o3lto.build.flags.ldspecs=-flto
+genericGD32F103C.menu.opt.ogstd=Debug
+genericGD32F103C.menu.opt.ogstd.build.flags.optimize=-Og
+genericGD32F103C.menu.opt.ogstd.build.flags.ldspecs=
+genericGD32F103C.menu.opt.oglto=Debug with LTO
+genericGD32F103C.menu.opt.oglto.build.flags.optimize=-Og -flto
+genericGD32F103C.menu.opt.oglto.build.flags.ldspecs=-flto
+genericGD32F103C.menu.opt.osstd=Smallest Code
+genericGD32F103C.menu.opt.osstd.build.flags.optimize=-Os
+genericGD32F103C.menu.opt.osstd.build.flags.ldspecs=
+genericGD32F103C.menu.opt.oslto=Smallest Code with LTO
+genericGD32F103C.menu.opt.oslto.build.flags.optimize=-Os -flto
+genericGD32F103C.menu.opt.oslto.build.flags.ldspecs=-flto
+
 ########################### STM32VLD to FLASH ###########################
 
 STM32VLD.name=STM32VLD to FLASH
@@ -604,5 +988,36 @@ STM32VLD.menu.upload_method.STLinkMethod.upload.protocol=STLink
 STM32VLD.menu.upload_method.STLinkMethod.upload.tool=stlink_upload
 STM32VLD.menu.upload_method.STLinkMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG  
 
-
-################################################################################
+#-- Optimizations
+STM32VLD.menu.opt.o2std=Faster
+STM32VLD.menu.opt.o2std.build.flags.optimize=-O2
+STM32VLD.menu.opt.o2std.build.flags.ldspecs=
+STM32VLD.menu.opt.o2lto=Faster with LTO
+STM32VLD.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+STM32VLD.menu.opt.o2lto.build.flags.ldspecs=-flto
+STM32VLD.menu.opt.o1std=Fast
+STM32VLD.menu.opt.o1std.build.flags.optimize=-O1
+STM32VLD.menu.opt.o1std.build.flags.ldspecs=
+STM32VLD.menu.opt.o1lto=Fast with LTO
+STM32VLD.menu.opt.o1lto.build.flags.optimize=-O1 -flto
+STM32VLD.menu.opt.o1lto.build.flags.ldspecs=-flto
+STM32VLD.menu.opt.o3std=Fastest
+STM32VLD.menu.opt.o3std.build.flags.optimize=-O3
+STM32VLD.menu.opt.o3std.build.flags.ldspecs=
+STM32VLD.menu.opt.o3lto=Fastest with LTO
+STM32VLD.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+STM32VLD.menu.opt.o3lto.build.flags.ldspecs=-flto
+STM32VLD.menu.opt.ogstd=Debug
+STM32VLD.menu.opt.ogstd.build.flags.optimize=-Og
+STM32VLD.menu.opt.ogstd.build.flags.ldspecs=
+STM32VLD.menu.opt.oglto=Debug with LTO
+STM32VLD.menu.opt.oglto.build.flags.optimize=-Og -flto
+STM32VLD.menu.opt.oglto.build.flags.ldspecs=-flto
+STM32VLD.menu.opt.osstd=Smallest Code
+STM32VLD.menu.opt.osstd.build.flags.optimize=-Os
+STM32VLD.menu.opt.osstd.build.flags.ldspecs=
+STM32VLD.menu.opt.oslto=Smallest Code with LTO
+STM32VLD.menu.opt.oslto.build.flags.optimize=-Os -flto
+STM32VLD.menu.opt.oslto.build.flags.ldspecs=-flto
+
+################################################################################
\ No newline at end of file
diff --git a/STM32F1/platform.txt b/STM32F1/platform.txt
index 3da3070c9..de1f206dc 100644
--- a/STM32F1/platform.txt
+++ b/STM32F1/platform.txt
@@ -16,20 +16,20 @@ compiler.warning_flags.all=-Wall -Wextra -DDEBUG_LEVEL=DEBUG_ALL
 # ----------------------
 compiler.path={runtime.tools.arm-none-eabi-gcc.path}/bin/
 compiler.c.cmd=arm-none-eabi-gcc
-compiler.c.flags=-c -g -Os {compiler.warning_flags} -std=gnu11 -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin} 
+compiler.c.flags=-c -g {build.flags.optimize} {compiler.warning_flags} -std=gnu11 -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin} 
 compiler.c.elf.cmd=arm-none-eabi-g++
-compiler.c.elf.flags=-Os -Wl,--gc-sections
+compiler.c.elf.flags={build.flags.optimize} -Wl,--gc-sections {build.flags.ldspecs}
 compiler.S.cmd=arm-none-eabi-gcc
 compiler.S.flags=-c -g -x assembler-with-cpp -MMD
 compiler.cpp.cmd=arm-none-eabi-g++
-compiler.cpp.flags=-c -g -Os {compiler.warning_flags} -std=gnu++11 -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin} 
+compiler.cpp.flags=-c -g {build.flags.optimize} {compiler.warning_flags} -std=gnu++11 -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin} 
 compiler.ar.cmd=arm-none-eabi-ar
 compiler.ar.flags=rcs
 compiler.objcopy.cmd=arm-none-eabi-objcopy
 compiler.objcopy.eep.flags=-O ihex -j .eeprom --set-section-flags=.eeprom=alloc,load --no-change-warnings --change-section-lma .eeprom=0
 compiler.elf2hex.flags=-O binary
 compiler.elf2hex.cmd=arm-none-eabi-objcopy
-compiler.ldflags=
+compiler.ldflags={build.flags.ldspecs}
 compiler.size.cmd=arm-none-eabi-size
 compiler.define=-DARDUINO=                            
 
@@ -160,4 +160,4 @@ tools.jlink_upload.path.linux={runtime.hardware.path}/tools/linux
 tools.jlink_upload.path.linux64={runtime.hardware.path}/tools/linux64
 tools.jlink_upload.upload.params.verbose=-d
 tools.jlink_upload.upload.params.quiet=n
-tools.jlink_upload.upload.pattern="{path}/{cmd}" "{build.path}/{build.project_name}.bin"
+tools.jlink_upload.upload.pattern="{path}/{cmd}" "{build.path}/{build.project_name}.bin"
\ No newline at end of file
diff --git a/STM32F3/boards.txt b/STM32F3/boards.txt
index 6c011bce3..bfe24bbf9 100644
--- a/STM32F3/boards.txt
+++ b/STM32F3/boards.txt
@@ -28,5 +28,37 @@ discovery_f3.build.error_led_port=GPIOE
 discovery_f3.build.error_led_pin=8
 discovery_f3.build.board=STM32F3Discovery
 
+#-- Optimizations
+discovery_f3.menu.opt.o2std=Faster
+discovery_f3.menu.opt.o2std.build.flags.optimize=-O2
+discovery_f3.menu.opt.o2std.build.flags.ldspecs=
+discovery_f3.menu.opt.o2lto=Faster with LTO
+discovery_f3.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+discovery_f3.menu.opt.o2lto.build.flags.ldspecs=-flto
+discovery_f3.menu.opt.o1std=Fast
+discovery_f3.menu.opt.o1std.build.flags.optimize=-O1
+discovery_f3.menu.opt.o1std.build.flags.ldspecs=
+discovery_f3.menu.opt.o1lto=Fast with LTO
+discovery_f3.menu.opt.o1lto.build.flags.optimize=-O1 -flto
+discovery_f3.menu.opt.o1lto.build.flags.ldspecs=-flto
+discovery_f3.menu.opt.o3std=Fastest
+discovery_f3.menu.opt.o3std.build.flags.optimize=-O3
+discovery_f3.menu.opt.o3std.build.flags.ldspecs=
+discovery_f3.menu.opt.o3lto=Fastest with LTO
+discovery_f3.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+discovery_f3.menu.opt.o3lto.build.flags.ldspecs=-flto
+discovery_f3.menu.opt.ogstd=Debug
+discovery_f3.menu.opt.ogstd.build.flags.optimize=-Og
+discovery_f3.menu.opt.ogstd.build.flags.ldspecs=
+discovery_f3.menu.opt.oglto=Debug with LTO
+discovery_f3.menu.opt.oglto.build.flags.optimize=-Og -flto
+discovery_f3.menu.opt.oglto.build.flags.ldspecs=-flto
+discovery_f3.menu.opt.osstd=Smallest Code
+discovery_f3.menu.opt.osstd.build.flags.optimize=-Os
+discovery_f3.menu.opt.osstd.build.flags.ldspecs=
+discovery_f3.menu.opt.oslto=Smallest Code with LTO
+discovery_f3.menu.opt.oslto.build.flags.optimize=-Os -flto
+discovery_f3.menu.opt.oslto.build.flags.ldspecs=-flto
+
 ##############################################################
 
diff --git a/STM32F3/platform.txt b/STM32F3/platform.txt
index 3218f85c1..94f787c81 100644
--- a/STM32F3/platform.txt
+++ b/STM32F3/platform.txt
@@ -12,20 +12,20 @@ version=0.1.0
 
 compiler.path={runtime.tools.arm-none-eabi-gcc.path}/bin/
 compiler.c.cmd=arm-none-eabi-gcc
-compiler.c.flags=-c -g -Os -w -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
+compiler.c.flags=-c -g {build.flags.optimize} -w -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
 compiler.c.elf.cmd=arm-none-eabi-g++
-compiler.c.elf.flags=-Os -Wl,--gc-sections
+compiler.c.elf.flags={build.flags.optimize} -Wl,--gc-sections {build.flags.ldspecs}
 compiler.S.cmd=arm-none-eabi-gcc
 compiler.S.flags=-c -g -x assembler-with-cpp -MMD
 compiler.cpp.cmd=arm-none-eabi-g++
-compiler.cpp.flags=-c -g -Os -w -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin} 
+compiler.cpp.flags=-c -g {build.flags.optimize} -w -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin} 
 compiler.ar.cmd=arm-none-eabi-ar
 compiler.ar.flags=rcs
 compiler.objcopy.cmd=arm-none-eabi-objcopy
 compiler.objcopy.eep.flags=-O ihex -j .eeprom --set-section-flags=.eeprom=alloc,load --no-change-warnings --change-section-lma .eeprom=0
 compiler.elf2hex.flags=-O binary
 compiler.elf2hex.cmd=arm-none-eabi-objcopy
-compiler.ldflags=
+compiler.ldflags={build.flags.ldspecs}
 compiler.size.cmd=arm-none-eabi-size
 compiler.define=-DARDUINO=                            
 
diff --git a/STM32F4/boards.txt b/STM32F4/boards.txt
index baf6f6e03..25a9c3197 100644
--- a/STM32F4/boards.txt
+++ b/STM32F4/boards.txt
@@ -36,6 +36,39 @@ discovery_f407.menu.usb_cfg.usb_serial=USB serial (CDC)
 discovery_f407.menu.usb_cfg.usb_serial.build.cpu_flags=-DSERIAL_USB
 discovery_f407.menu.usb_cfg.usb_msc=USB Mass Storage (MSC)
 discovery_f407.menu.usb_cfg.usb_msc.build.cpu_flags=-DUSB_MSC
+
+#-- Optimizations
+discovery_f407.menu.opt.o2std=Faster
+discovery_f407.menu.opt.o2std.build.flags.optimize=-O2
+discovery_f407.menu.opt.o2std.build.flags.ldspecs=
+discovery_f407.menu.opt.o2lto=Faster with LTO
+discovery_f407.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+discovery_f407.menu.opt.o2lto.build.flags.ldspecs=-flto
+discovery_f407.menu.opt.o1std=Fast
+discovery_f407.menu.opt.o1std.build.flags.optimize=-O1
+discovery_f407.menu.opt.o1std.build.flags.ldspecs=
+discovery_f407.menu.opt.o1lto=Fast with LTO
+discovery_f407.menu.opt.o1lto.build.flags.optimize=-O1 -flto
+discovery_f407.menu.opt.o1lto.build.flags.ldspecs=-flto
+discovery_f407.menu.opt.o3std=Fastest
+discovery_f407.menu.opt.o3std.build.flags.optimize=-O3
+discovery_f407.menu.opt.o3std.build.flags.ldspecs=
+discovery_f407.menu.opt.o3lto=Fastest with LTO
+discovery_f407.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+discovery_f407.menu.opt.o3lto.build.flags.ldspecs=-flto
+discovery_f407.menu.opt.ogstd=Debug
+discovery_f407.menu.opt.ogstd.build.flags.optimize=-Og
+discovery_f407.menu.opt.ogstd.build.flags.ldspecs=
+discovery_f407.menu.opt.oglto=Debug with LTO
+discovery_f407.menu.opt.oglto.build.flags.optimize=-Og -flto
+discovery_f407.menu.opt.oglto.build.flags.ldspecs=-flto
+discovery_f407.menu.opt.osstd=Smallest Code
+discovery_f407.menu.opt.osstd.build.flags.optimize=-Os
+discovery_f407.menu.opt.osstd.build.flags.ldspecs=
+discovery_f407.menu.opt.oslto=Smallest Code with LTO
+discovery_f407.menu.opt.oslto.build.flags.optimize=-Os -flto
+discovery_f407.menu.opt.oslto.build.flags.ldspecs=-flto
+
 ##############################################################
 generic_f407v.name=Generic STM32F407V series
 
@@ -72,6 +105,38 @@ generic_f407v.menu.usb_cfg.usb_serial.build.cpu_flags=-DSERIAL_USB
 generic_f407v.menu.usb_cfg.usb_msc=USB Mass Storage (MSC)
 generic_f407v.menu.usb_cfg.usb_msc.build.cpu_flags=-DUSB_MSC
 
+#-- Optimizations
+generic_f407v.menu.opt.o2std=Faster
+generic_f407v.menu.opt.o2std.build.flags.optimize=-O2
+generic_f407v.menu.opt.o2std.build.flags.ldspecs=
+generic_f407v.menu.opt.o2lto=Faster with LTO
+generic_f407v.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+generic_f407v.menu.opt.o2lto.build.flags.ldspecs=-flto
+generic_f407v.menu.opt.o1std=Fast
+generic_f407v.menu.opt.o1std.build.flags.optimize=-O1
+generic_f407v.menu.opt.o1std.build.flags.ldspecs=
+generic_f407v.menu.opt.o1lto=Fast with LTO
+generic_f407v.menu.opt.o1lto.build.flags.optimize=-O1 -flto
+generic_f407v.menu.opt.o1lto.build.flags.ldspecs=-flto
+generic_f407v.menu.opt.o3std=Fastest
+generic_f407v.menu.opt.o3std.build.flags.optimize=-O3
+generic_f407v.menu.opt.o3std.build.flags.ldspecs=
+generic_f407v.menu.opt.o3lto=Fastest with LTO
+generic_f407v.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+generic_f407v.menu.opt.o3lto.build.flags.ldspecs=-flto
+generic_f407v.menu.opt.ogstd=Debug
+generic_f407v.menu.opt.ogstd.build.flags.optimize=-Og
+generic_f407v.menu.opt.ogstd.build.flags.ldspecs=
+generic_f407v.menu.opt.oglto=Debug with LTO
+generic_f407v.menu.opt.oglto.build.flags.optimize=-Og -flto
+generic_f407v.menu.opt.oglto.build.flags.ldspecs=-flto
+generic_f407v.menu.opt.osstd=Smallest Code
+generic_f407v.menu.opt.osstd.build.flags.optimize=-Os
+generic_f407v.menu.opt.osstd.build.flags.ldspecs=
+generic_f407v.menu.opt.oslto=Smallest Code with LTO
+generic_f407v.menu.opt.oslto.build.flags.optimize=-Os -flto
+generic_f407v.menu.opt.oslto.build.flags.ldspecs=-flto
+
 ##############################################################
 stm32f4stamp.name=STM32F4Stamp F405
 
@@ -107,6 +172,39 @@ stm32f4stamp.menu.usb_cfg.usb_serial=USB serial (CDC)
 stm32f4stamp.menu.usb_cfg.usb_serial.build.cpu_flags=-DSERIAL_USB
 stm32f4stamp.menu.usb_cfg.usb_msc=USB Mass Storage (MSC)
 stm32f4stamp.menu.usb_cfg.usb_msc.build.cpu_flags=-DUSB_MSC
+
+#-- Optimizations
+stm32f4stamp.menu.opt.o2std=Faster
+stm32f4stamp.menu.opt.o2std.build.flags.optimize=-O2
+stm32f4stamp.menu.opt.o2std.build.flags.ldspecs=
+stm32f4stamp.menu.opt.o2lto=Faster with LTO
+stm32f4stamp.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+stm32f4stamp.menu.opt.o2lto.build.flags.ldspecs=-flto
+stm32f4stamp.menu.opt.o1std=Fast
+stm32f4stamp.menu.opt.o1std.build.flags.optimize=-O1
+stm32f4stamp.menu.opt.o1std.build.flags.ldspecs=
+stm32f4stamp.menu.opt.o1lto=Fast with LTO
+stm32f4stamp.menu.opt.o1lto.build.flags.optimize=-O1 -flto
+stm32f4stamp.menu.opt.o1lto.build.flags.ldspecs=-flto
+stm32f4stamp.menu.opt.o3std=Fastest
+stm32f4stamp.menu.opt.o3std.build.flags.optimize=-O3
+stm32f4stamp.menu.opt.o3std.build.flags.ldspecs=
+stm32f4stamp.menu.opt.o3lto=Fastest with LTO
+stm32f4stamp.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+stm32f4stamp.menu.opt.o3lto.build.flags.ldspecs=-flto
+stm32f4stamp.menu.opt.ogstd=Debug
+stm32f4stamp.menu.opt.ogstd.build.flags.optimize=-Og
+stm32f4stamp.menu.opt.ogstd.build.flags.ldspecs=
+stm32f4stamp.menu.opt.oglto=Debug with LTO
+stm32f4stamp.menu.opt.oglto.build.flags.optimize=-Og -flto
+stm32f4stamp.menu.opt.oglto.build.flags.ldspecs=-flto
+stm32f4stamp.menu.opt.osstd=Smallest Code
+stm32f4stamp.menu.opt.osstd.build.flags.optimize=-Os
+stm32f4stamp.menu.opt.osstd.build.flags.ldspecs=
+stm32f4stamp.menu.opt.oslto=Smallest Code with LTO
+stm32f4stamp.menu.opt.oslto.build.flags.optimize=-Os -flto
+stm32f4stamp.menu.opt.oslto.build.flags.ldspecs=-flto
+
 ##############################################################
 netduino2plus.name=Netduino2 F405
 
@@ -142,5 +240,37 @@ netduino2plus.menu.usb_cfg.usb_serial=USB serial (CDC)
 netduino2plus.menu.usb_cfg.usb_serial.build.cpu_flags=-DSERIAL_USB
 netduino2plus.menu.usb_cfg.usb_msc=USB Mass Storage (MSC)
 netduino2plus.menu.usb_cfg.usb_msc.build.cpu_flags=-DUSB_MSC
-##############################################################
 
+#-- Optimizations
+netduino2plus.menu.opt.o2std=Faster
+netduino2plus.menu.opt.o2std.build.flags.optimize=-O2
+netduino2plus.menu.opt.o2std.build.flags.ldspecs=
+netduino2plus.menu.opt.o2lto=Faster with LTO
+netduino2plus.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+netduino2plus.menu.opt.o2lto.build.flags.ldspecs=-flto
+netduino2plus.menu.opt.o1std=Fast
+netduino2plus.menu.opt.o1std.build.flags.optimize=-O1
+netduino2plus.menu.opt.o1std.build.flags.ldspecs=
+netduino2plus.menu.opt.o1lto=Fast with LTO
+netduino2plus.menu.opt.o1lto.build.flags.optimize=-O1 -flto
+netduino2plus.menu.opt.o1lto.build.flags.ldspecs=-flto
+netduino2plus.menu.opt.o3std=Fastest
+netduino2plus.menu.opt.o3std.build.flags.optimize=-O3
+netduino2plus.menu.opt.o3std.build.flags.ldspecs=
+netduino2plus.menu.opt.o3lto=Fastest with LTO
+netduino2plus.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+netduino2plus.menu.opt.o3lto.build.flags.ldspecs=-flto
+netduino2plus.menu.opt.ogstd=Debug
+netduino2plus.menu.opt.ogstd.build.flags.optimize=-Og
+netduino2plus.menu.opt.ogstd.build.flags.ldspecs=
+netduino2plus.menu.opt.oglto=Debug with LTO
+netduino2plus.menu.opt.oglto.build.flags.optimize=-Og -flto
+netduino2plus.menu.opt.oglto.build.flags.ldspecs=-flto
+netduino2plus.menu.opt.osstd=Smallest Code
+netduino2plus.menu.opt.osstd.build.flags.optimize=-Os
+netduino2plus.menu.opt.osstd.build.flags.ldspecs=
+netduino2plus.menu.opt.oslto=Smallest Code with LTO
+netduino2plus.menu.opt.oslto.build.flags.optimize=-Os -flto
+netduino2plus.menu.opt.oslto.build.flags.ldspecs=-flto
+
+##############################################################
diff --git a/STM32F4/platform.txt b/STM32F4/platform.txt
index b64fe3eee..92dc1ea9a 100755
--- a/STM32F4/platform.txt
+++ b/STM32F4/platform.txt
@@ -10,20 +10,20 @@ version=0.1.0
 # ----------------------
 compiler.path={runtime.tools.arm-none-eabi-gcc.path}/bin/
 compiler.c.cmd=arm-none-eabi-gcc
-compiler.c.flags=-c -g -Os -Wall -MMD -std=gnu11 -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
+compiler.c.flags=-c -g {build.flags.optimize} -Wall -MMD -std=gnu11 -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
 compiler.c.elf.cmd=arm-none-eabi-g++
-compiler.c.elf.flags=-Os -Wl,--gc-sections
+compiler.c.elf.flags={build.flags.optimize} -Wl,--gc-sections {build.flags.ldspecs}
 compiler.S.cmd=arm-none-eabi-gcc
 compiler.S.flags=-c -g -x assembler-with-cpp -MMD
 compiler.cpp.cmd=arm-none-eabi-g++
-compiler.cpp.flags=-c -g -Os -Wall -MMD -std=gnu++11 -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
+compiler.cpp.flags=-c -g {build.flags.optimize} -Wall -MMD -std=gnu++11 -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
 compiler.ar.cmd=arm-none-eabi-ar
 compiler.ar.flags=rcs
 compiler.objcopy.cmd=arm-none-eabi-objcopy
 compiler.objcopy.eep.flags=-O ihex -j .eeprom --set-section-flags=.eeprom=alloc,load --no-change-warnings --change-section-lma .eeprom=0
 compiler.elf2hex.flags=-O binary
 compiler.elf2hex.cmd=arm-none-eabi-objcopy
-compiler.ldflags=
+compiler.ldflags={build.flags.ldspecs}
 compiler.size.cmd=arm-none-eabi-size
 compiler.define=-DARDUINO=                            
 

From 4f3c4da648a72633a17d0ed3c105a02df277489f Mon Sep 17 00:00:00 2001
From: Cristi Marius Tiutiu <mtiutiu@gmail.com>
Date: Mon, 17 Jul 2017 10:45:37 +0300
Subject: [PATCH 147/307] added missing menu opts for F3/F4 boards

---
 STM32F3/boards.txt | 2 ++
 STM32F4/boards.txt | 1 +
 2 files changed, 3 insertions(+)

diff --git a/STM32F3/boards.txt b/STM32F3/boards.txt
index bfe24bbf9..d3a37353e 100644
--- a/STM32F3/boards.txt
+++ b/STM32F3/boards.txt
@@ -1,5 +1,7 @@
 # 
 
+menu.opt=Optimize
+
 ##############################################################
 discovery_f3.name=STM32F3Discovery
 
diff --git a/STM32F4/boards.txt b/STM32F4/boards.txt
index 25a9c3197..429ba4b96 100644
--- a/STM32F4/boards.txt
+++ b/STM32F4/boards.txt
@@ -1,6 +1,7 @@
 # 
 
 menu.usb_cfg=USB configuration
+menu.opt=Optimize
 
 ##############################################################
 discovery_f407.name=STM32 Discovery F407

From 01de9ee977a9335aed2b8dd07ff332c52a8f7386 Mon Sep 17 00:00:00 2001
From: Hemal Chevli <hemal_chevli@yahoo.com>
Date: Wed, 19 Jul 2017 10:46:25 +0530
Subject: [PATCH 148/307] Fixed headings

---
 README.md | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/README.md b/README.md
index 7e13786a2..4ffc9ed66 100644
--- a/README.md
+++ b/README.md
@@ -1,14 +1,14 @@
 Arduino STM32  
 =============  
 
-##Notice
+## Notice
 
 This software is experimental and a work in progress.
 Under no circumstances should these files be used in relation to any critical system(s).
 Use of these files is at your own risk.
 
 
-##Summary:  
+## Summary:  
 This repo contains, the "Hardware" files to support STM32 based boards on Arduino version 1.6.13 or 1.6.12 (some older versions may also work)  including [LeafLabs Maple, and Maple mini](http://www.leaflabs.com/about-maple/), and other generic STM32F103 boards  
 
 ***PRIMARY SUPPORT FORUM: http://www.stm32duino.com/***
@@ -16,7 +16,7 @@ This repo contains, the "Hardware" files to support STM32 based boards on Arduin
 ***We are also on Gitter https://gitter.im/stm32duino/Lobby/***
 [![Gitter](https://badges.gitter.im/Join%20Chat.svg)](https://gitter.im/stm32duino/Lobby?utm_source=badge&utm_medium=badge&utm_campaign=pr-badge&utm_content=badge)
 
-##Background & Support:  
+## Background & Support:  
 * Based on https://github.com/bobc/maple-asp, which is in turn based on LibMaple by Leaflabs  
 * **Please read the wiki (https://github.com/rogerclarkmelbourne/Arduino_STM32/wiki) for full details**
 * See also my blog: http://www.rogerclark.net/stm32f103-and-maple-maple-mini-with-arduino-1-5-x-ide/  
@@ -29,11 +29,11 @@ This repo contains, the "Hardware" files to support STM32 based boards on Arduin
 * 20150413: [STM32 for Arduino 1.6.2 or newer (update)](https://www.youtube.com/watch?v=TePglhSkghg)
 * 20150419: [Uploading via USB to Serial to STM32F103 boards](https://www.youtube.com/watch?v=G_RF0a0hrak)
 
-##Additional Links & Info:  
+## Additional Links & Info:  
 * https://www.hackster.io/rayburne/4-dollar-90-mips-32-bit-72-mhz-arm-arduino  
 
-##Purchase info:  
-###Entry level boards
+## Purchase info:  
+### Entry level boards
 
 * [Ebay search for "arduino maple"](http://www.ebay.com/sch/i.html?_from=R40&_sacat=0&LH_BIN=1&_nkw=arduino+maple&_sop=15) (currently costs <$5 with shipping)
 * [AliExpress search for "leaflabs maple"] (http://www.aliexpress.com/wholesale?catId=0&initiative_id=SB_20150607085526&SearchText=leaflabs+maple)

From b29fed855b440f3d55c627b9d4478940b7fff29d Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Wed, 19 Jul 2017 19:11:44 +0200
Subject: [PATCH 149/307] reworked RTC - no need for extra time library

http://www.stm32duino.com/viewtopic.php?f=39&t=775&p=31218#p31218
---
 .../examples/Test_RTClock/Test_RTClock.ino    | 209 +++++++++++++
 STM32F4/libraries/RTClock/library.properties  |   1 +
 STM32F4/libraries/RTClock/src/RTClock.cpp     | 293 ++++++++++--------
 STM32F4/libraries/RTClock/src/RTClock.h       | 136 ++++++--
 4 files changed, 485 insertions(+), 154 deletions(-)
 create mode 100644 STM32F4/libraries/RTClock/examples/Test_RTClock/Test_RTClock.ino

diff --git a/STM32F4/libraries/RTClock/examples/Test_RTClock/Test_RTClock.ino b/STM32F4/libraries/RTClock/examples/Test_RTClock/Test_RTClock.ino
new file mode 100644
index 000000000..ec6afa432
--- /dev/null
+++ b/STM32F4/libraries/RTClock/examples/Test_RTClock/Test_RTClock.ino
@@ -0,0 +1,209 @@
+/*
+	This is an example of how to use the RTclock of STM32F4 device
+	
+	This example can also be used to set the RTC to the current epoch time:
+	- goto: http://www.unixtimestamp.com/
+	- enter the current date and time to the right field "Timestamp converter"
+	- press the "Convert" button
+	- 
+*/
+
+#include <RTClock.h>
+
+#include <Streaming.h>
+
+
+//RTClock rt(RTCSEL_LSE); // initialise
+RTClock rtc;
+
+time_t tt;
+tm_t tm;
+
+const uint32_t DEFAULT_TIME = 1498944019; // 2017.07.01, 21:20:19 used as reference epoch time
+
+#define TIME_HEADER  'T'   // Header tag for serial time sync message
+#define TIME_REQUEST  7    // ASCII bell character requests a time sync message 
+
+#define LED_PIN BOARD_LED_PIN
+
+//-----------------------------------------------------------------------------
+void blink () 
+{
+	digitalWrite(LED_PIN, digitalRead(LED_PIN)?LOW:HIGH);
+}
+
+uint8_t s[20]; // for serial parsing
+
+//-----------------------------------------------------------------------------
+char * read_line()
+{
+	while ( Serial.available() ) Serial.read(); // empty Rx buffer
+	while ( Serial.available()<=0 ) ; // wait for new characters
+	uint8_t c, i = 0;
+	s[0] = 0;
+	while ( Serial.available() && (i<20) ) {
+		c = Serial.read();
+		if ( c=='\n' || c== '\r') {
+			s[i] = 0;
+			break;
+		}
+		s[i++] = c;
+	}
+	while ( Serial.available() ) Serial.read(); // flush Rx
+	return (char*)&s[0];
+}
+
+//-----------------------------------------------------------------------------
+void processSyncMessage(void)
+{
+	if ( Serial.available() ) {
+		if( *read_line()==(TIME_HEADER) ) {
+			uint32_t pctime = atoi((const char*)&s[1]);
+			Serial << ("Epoch time received: ") << pctime << endl;
+			if ( pctime >= DEFAULT_TIME) { // check the integer is a valid epoch time
+				rtc.setTime(pctime); // Set RTC to the time received via the serial port
+			}
+		}
+		Serial << endl;
+	}
+}
+
+//-----------------------------------------------------------------------------
+void Change_DateTime(void)
+{
+	// check and correct the weekday if necessary
+	rtc.getTime(tm);	
+	Serial << "Current weekday is " << (tm.weekday);
+	// get time elements
+	tt = rtc.makeTime(tm);
+	uint16_t tmp = rtc.weekday(tt);
+	if ( tmp!=tm.weekday ) {// correct weekday
+		rtc.setTime(tt);
+		Serial << " instead of " << tmp << ". Now is corrected.\n";
+	} else {
+		Serial << " - seems to be fine, no need to change it.\n";
+	}
+
+	uint8_t chg = 0;
+	// get time elements
+	rtc.getTime(tm);	
+	Serial << "\nCurrent RTC date: " << (1970+tm.year) << "." << (tm.month) << (".") << (tm.day) << (", weekday: ") << (tm.weekday) << endl;
+	Serial << "Do you want to change it? (y/n)\n";
+	if ( *read_line()=='y' ) {
+		// change here the date
+change_year:
+		Serial << "Current year: " << (1970+tm.year) << ". Enter new year in \"YYYY\" format (numbers only) or press enter to skip.\n";
+		if (*read_line()==0) goto change_month;
+		tmp = atoi((const char*)s);
+		if ( tmp<1970 ) { Serial << "Please enter a valid number greater than 1970\n"; goto change_year; }
+		Serial << "You entered: " << tmp << ". Accept value? (y/n)\n";
+		if ( *read_line()=='n' ) goto change_year;
+		tm.year = tmp-1970;
+		chg = 1;
+change_month:
+		Serial << "Current month: " << tm.month << ". Enter new month in \"MM\" format [1..12] or press enter to skip.\n";
+		if (*read_line()==0) goto change_day;
+		tmp = atoi((const char*)s);
+		if ( tmp<1 || tmp>12 ) { Serial << "Please enter a valid number [1..12]\n"; goto change_month; }
+		Serial << "You entered: " << tmp << ". Accept value? (y/n)\n";
+		if ( *read_line()=='n' ) goto change_month;
+		tm.month = tmp;
+		chg = 1;
+change_day:
+		Serial << "Current day: " << tm.day << ". Enter new day in \"DD\" format [1..31] or press enter to skip.\n";
+		if (*read_line()==0) goto change_weekday;
+		tmp = atoi((const char*)s);
+		if ( tmp<1 || tmp>31 ) { Serial << "Please enter a valid number [1..31]\n"; goto change_day; }
+		Serial << "You entered: " << tmp << ". Accept value? (y/n)\n";
+		if ( *read_line()=='n' ) goto change_day;
+		tm.day = tmp;
+		chg = 1;
+change_weekday:
+		Serial << "Current weekday: " << tm.weekday << ". Enter new weekday [1(=Monday)..7(=Sunday)] or press enter to skip.\n";
+		if (*read_line()==0) goto change_time;
+		tmp = atoi((const char*)s);
+		if ( tmp<1 || tmp>7 ) { Serial << "Please enter a valid number [1..7]\n"; goto change_weekday; }
+		Serial << "You entered: " << tmp << ". Accept value? (y/n)\n";
+		if ( *read_line()=='n' ) goto change_weekday;
+		tm.weekday = tmp;
+		chg = 1;
+change_time:
+		Serial << "Current RTC time: " << _TIME(tm.hour, tm.minute, tm.second) << endl;
+		Serial << "Do you want to change it? (y/n)\n";
+		if ( *read_line()=='n' ) goto change_end;
+change_hour:
+		Serial << "Current hour: " << tm.hour << ". Enter new hour [0..23] or press enter to skip.\n";
+		if (*read_line()==0) goto change_minute;
+		tmp = atoi((const char*)s);
+		if ( tmp>23 ) { Serial << "Please enter a valid number [0..23]\n"; goto change_hour; }
+		Serial << "You entered: " << tmp << ". Accept value? (y/n)\n";
+		if ( *read_line()=='n' ) goto change_hour;
+		tm.hour = tmp;
+		chg = 1;
+change_minute:
+		Serial << "Current minute: " << tm.minute << ". Enter new minute [0..59] or press enter to skip.\n";
+		if (*read_line()==0) goto change_second;
+		tmp = atoi((const char*)s);
+		if ( tmp>59 ) { Serial << "Please enter a valid number [0..59]\n"; goto change_minute; }
+		Serial << "You entered: " << tmp << ". Accept value? (y/n)\n";
+		if ( *read_line()=='n' ) goto change_minute;
+		tm.minute = tmp;
+		chg = 1;
+change_second:
+		Serial << "Current second: " << tm.second << ". Enter new second [0..59] or press enter to skip.\n";
+		if (*read_line()==0) goto change_end;
+		tmp = atoi((const char*)s);
+		if ( tmp>59 ) { Serial << "Please enter a valid number [0..59]\n"; goto change_second; }
+		Serial << "You entered: " << tmp << ". Accept value? (y/n)\n";
+		if ( *read_line()=='n' ) goto change_second;
+		tm.second = tmp;
+		chg = 1;
+	} else {
+		goto change_time;
+	}
+
+change_end:
+	if ( chg ) {
+		// set here the RTC time.
+		Serial << "Changed date & time: " << (1970+tm.year) << "." << (tm.month) << (".") << (tm.day) << (", weekday: ") << (tm.weekday) << ", " << _TIME(tm.hour, tm.minute, tm.second) << endl;
+		Serial << "Write now to RTC? (y/n)\n";
+		read_line();
+		if ( s[0]=='y' ) {
+			rtc.setTime(tm);
+			Serial << "Data written to RTC.\n\n";
+		}
+	} else
+		Serial << "RTC was not changed.\n\n";
+} 
+//-----------------------------------------------------------------------------
+void setup() 
+{
+	Serial.begin();
+	delay(3000);
+
+	pinMode(LED_PIN, OUTPUT);
+	
+	Serial << "This is an example of how to use the STM32F4 RTC library.\n\n";
+
+	Change_DateTime();
+}
+
+//-----------------------------------------------------------------------------
+void loop() 
+{
+	if ( Serial.available() ) {
+		// adjust time according to received epoch time from PC
+		processSyncMessage();
+	}
+
+	if (tt!=rtc.now()) {
+		// get epoch time
+		tt = rtc.now();
+		Serial << ("- RTC epoch timestamp = ") << (tt);
+		// get time elements
+		rtc.getTime(tm);
+		//rtc.breakTime(tt, tm);
+		Serial << (" == ") << (1970+tm.year) << "." << (tm.month) << (".") << (tm.day) << (", weekday ") << (tm.weekday) << (", ");
+		Serial << _TIME(tm.hour, tm.minute, tm.second) << endl;
+	}
+}
\ No newline at end of file
diff --git a/STM32F4/libraries/RTClock/library.properties b/STM32F4/libraries/RTClock/library.properties
index 5a5e4b71d..a8878f6ac 100644
--- a/STM32F4/libraries/RTClock/library.properties
+++ b/STM32F4/libraries/RTClock/library.properties
@@ -7,3 +7,4 @@ paragraph=Real Time Clock for STM32F4
 category=Other
 url=
 architectures=STM32F4
+maintainer=www.stm32duino.com
diff --git a/STM32F4/libraries/RTClock/src/RTClock.cpp b/STM32F4/libraries/RTClock/src/RTClock.cpp
index ee82c95b3..e7c2ca8da 100644
--- a/STM32F4/libraries/RTClock/src/RTClock.cpp
+++ b/STM32F4/libraries/RTClock/src/RTClock.cpp
@@ -42,15 +42,7 @@ voidFuncPtr handlerAlarmA = NULL;
 voidFuncPtr handlerAlarmB = NULL;
 voidFuncPtr handlerPeriodicWakeup = NULL;
 
-
-RTClock::RTClock() {
-    RTClock(RTCSEL_HSE, 7999, 124);
-}
-
-RTClock::RTClock(rtc_clk_src src) {
-    RTClock(src, 0, 0);	
-}
-
+//-----------------------------------------------------------------------------
 RTClock::RTClock(rtc_clk_src src, uint16 sync_prescaler, uint16 async_prescaler) {
     uint32 t = 0;
     RCC_BASE->APB1ENR |= RCC_APB1RSTR_PWRRST;
@@ -144,117 +136,155 @@ RTClock::~RTClock() {
 }
 */	
 	
-void RTClock::setTime (time_t time_stamp) {
-    unsigned char years = 0;
-    unsigned char months = 0;
-    unsigned char monthLength = 0;
-    unsigned char wdays = 0;
-    unsigned char hours = 0;
-    unsigned char mins = 0;
-    unsigned char secs = 0;
-    unsigned long days;
-
-    secs = time_stamp % 60;
-    time_stamp /= 60; // now it is minutes
-    mins = time_stamp % 60;
-    time_stamp /= 60; // now it is hours
-    hours = time_stamp % 24;
-    time_stamp /= 24; // now it is days
-    wdays = ((time_stamp + 4) % 7) + 1;  // Sunday is day 1 
-  
-    while((unsigned)(days += (LEAP_YEAR(years) ? 366 : 365)) <= time_stamp) {
-        years++;
-    }
-  
-    days -= LEAP_YEAR(years) ? 366 : 365;
-    time_stamp -= days; // now it is days in this year, starting at 0
-  
-    for (months = 0; months < 12; months++) {
-        if (months == 1) { // february
-            if (LEAP_YEAR(years)) {
-                monthLength = 29;
-            } else {
-                monthLength = 28;
-            }
-        } else {
-            monthLength = monthDays[months];
-        }
-    
-        if (time_stamp >= monthLength) {
-            time_stamp -= monthLength;
-        } else {
-            break;
-        }
-    }
-    months++;  // jan is month 1  
-    days = time_stamp + 1;     // day of month
-    rtc_enter_config_mode();
-    RTC_BASE->TR = ((hours / 10) << 20) | ((hours % 10) << 16) | ((mins / 10) << 12) | ((mins % 10) << 8) | ((secs / 10) << 4) | (secs % 10);
-    RTC_BASE->DR = ((years / 10) << 20) | ((years % 10) << 16) | (wdays << 13) | ((months / 10) << 12) | ((months % 10) << 8) |	((days / 10) << 4) | (days % 10);
-    rtc_exit_config_mode();		                
+//-----------------------------------------------------------------------------
+void RTClock::setTime (time_t time_stamp)
+{
+	breakTime(time_stamp, tm); // time will be broken to tm
+    setTime(tm);
 }
-	
-void RTClock::setTime (struct tm* tm_ptr) {
+
+//-----------------------------------------------------------------------------
+void RTClock::setTime (tm_t & tm)
+{
+    if (tm.year > 99)
+        tm.year = tm.year % 100;
     rtc_enter_config_mode();
-    if (tm_ptr->tm_year > 99)
-        tm_ptr->tm_year = tm_ptr->tm_year % 100;
-    tm_ptr->tm_wday = tm_ptr->tm_wday & 0x7;
-    RTC_BASE->TR = ((tm_ptr->tm_hour / 10) << 20) | ((tm_ptr->tm_hour % 10) << 16) | 
-			((tm_ptr->tm_min / 10) << 12) | ((tm_ptr->tm_min % 10) << 8) | 
-			((tm_ptr->tm_sec / 10) << 4) | (tm_ptr->tm_sec % 10);
-    RTC_BASE->DR = ((tm_ptr->tm_year / 10) << 20) | ((tm_ptr->tm_year % 10) << 16) | (tm_ptr->tm_wday << 13) | 
-			((tm_ptr->tm_mon / 10) << 12) | ((tm_ptr->tm_mon % 10) << 8) |
-			((tm_ptr->tm_mday / 10) << 4) | (tm_ptr->tm_mday % 10);
+    RTC_BASE->TR = BUILD_TIME_REGISTER(tm.hour, tm.minute, tm.second);
+    RTC_BASE->DR = BUILD_DATE_REGISTER(tm.year, tm.month, tm.day, tm.weekday);
     rtc_exit_config_mode();		                
 }
-	
-time_t RTClock::getTime() {
-    uint32 dr_reg = RTC_BASE->DR;
-    uint32 tr_reg = RTC_BASE->TR;
-    int years = 10 * ((dr_reg & 0x00F00000) >> 20) + ((dr_reg & 0x000F0000) >> 16);
-    int months = 10 * ((dr_reg & 0x00001000) >> 12) + ((dr_reg & 0x00000F00) >> 8);
-    int days = 10 * ((dr_reg & 0x00000030) >> 4) + (dr_reg & 0x000000F);
-    int hours = 10 * ((tr_reg & 0x00300000) >> 20) + ((tr_reg & 0x000F0000) >> 16);
-    int mins = 10 * ((tr_reg & 0x00007000) >> 12) + ((tr_reg & 0x0000F00) >> 8);
-    int secs = 10 * ((tr_reg & 0x00000070) >> 4) + (tr_reg & 0x0000000F);
-    // seconds from 1970 till 1 jan 00:00:00 of the given year
-    time_t t = (years + 30) * SECS_PER_DAY * 365;
-    for (int i = 0; i < (years + 30); i++) {
-	if (LEAP_YEAR(i)) {
-	    t +=  SECS_PER_DAY;   // add extra days for leap years
+
+/*============================================================================*/	
+/* functions to convert to and from system time */
+/* These are for interfacing with time serivces and are not normally needed in a sketch */
+
+// leap year calulator expects year argument as years offset from 1970
+#define LEAP_YEAR(Y)     ( ((1970+Y)>0) && !((1970+Y)%4) && ( ((1970+Y)%100) || !((1970+Y)%400) ) )
+
+//static const uint8_t monthDays[]={31,28,31,30,31,30,31,31,30,31,30,31}; // API starts months from 1, this array starts from 0
+
+//-----------------------------------------------------------------------------
+void RTClock::breakTime(time_t timeInput, tm_t & tm)
+{
+// break the given time_t into time components
+// this is a more compact version of the C library localtime function
+// note that year is offset from 1970 !!!
+
+	uint8_t year;
+	uint8_t month, monthLength;
+	uint32_t time;
+	uint32_t days;
+
+	time = (uint32_t)timeInput;
+	tm.second = time % 60;
+	time /= 60; // now it is minutes
+	tm.minute = time % 60;
+	time /= 60; // now it is hours
+	tm.hour = time % 24;
+	time /= 24; // now it is days
+	tm.weekday = ((time + 4) % 7); // Monday is day 1 // + 1;  // Sunday is day 1 
+
+	year = 0;
+	days = 0;
+	while((unsigned)(days += (LEAP_YEAR(year) ? 366 : 365)) <= time) {
+		year++;
 	}
-    }
-    // add days for this year, months start from 1
-    for (int i = 1; i < months; i++) {
-	if ( (i == 2) && LEAP_YEAR(years)) { 
-	    t += SECS_PER_DAY * 29;
-	} else {
-	    t += SECS_PER_DAY * monthDays[i - 1];  //monthDays array starts from 0
+	tm.year = year; // year is offset from 1970 
+
+	days -= LEAP_YEAR(year) ? 366 : 365;
+	time -= days; // now it is days in this year, starting at 0
+
+	days = 0;
+	month = 0;
+	monthLength = 0;
+	for (month=0; month<12; month++) {
+		if (month==1) { // february
+			if (LEAP_YEAR(year)) {
+				monthLength=29;
+			} else {
+				monthLength=28;
+			}
+		} else {
+			monthLength = monthDays[month];
+		}
+
+		if (time >= monthLength) {
+			time -= monthLength;
+		} else {
+			break;
+		}
 	}
-    }
-    t += (days - 1) * SECS_PER_DAY + hours * SECS_PER_HOUR + mins * SECS_PER_MIN + secs;
-    return t;
+	tm.month = month + 1;  // jan is month 1  
+	tm.day = time + 1;     // day of month
 }
-	
-struct tm* RTClock::getTime(struct tm* tm_ptr) {
-    uint32 dr_reg = RTC_BASE->DR;
-    uint32 tr_reg = RTC_BASE->TR;
-    tm_ptr->tm_year = 10 * ((dr_reg & 0x00F00000) >> 20) + ((dr_reg & 0x000F0000) >> 16);
-    tm_ptr->tm_mon = 10 * ((dr_reg & 0x00001000) >> 12) + ((dr_reg & 0x00000F00) >> 8);
-    tm_ptr->tm_mday = 10 * ((dr_reg & 0x00000030) >> 4) + (dr_reg & 0x000000F);
-    tm_ptr->tm_hour = 10 * ((tr_reg & 0x00300000) >> 20) + ((tr_reg & 0x000F0000) >> 16);
-    tm_ptr->tm_min = 10 * ((tr_reg & 0x00007000) >> 12) + ((tr_reg & 0x0000F00) >> 8);
-    tm_ptr->tm_sec = 10 * ((tr_reg & 0x00000070) >> 4) + (tr_reg & 0x0000000F);
-    return tm_ptr;
+
+//-----------------------------------------------------------------------------
+time_t RTClock::makeTime(tm_t & tm)
+{
+// assemble time elements into time_t 
+// note year argument is offset from 1970 (see macros in time.h to convert to other formats)
+// previous version used full four digit year (or digits since 2000),i.e. 2009 was 2009 or 9
+  
+	int i;
+	uint32_t seconds;
+
+	// seconds from 1970 till 1 jan 00:00:00 of the given year
+	seconds = tm.year*(SECS_PER_DAY * 365);
+	for (i = 0; i < tm.year; i++) {
+		if (LEAP_YEAR(i)) {
+			seconds +=  SECS_PER_DAY;   // add extra days for leap years
+		}
+	}
+
+	// add days for this year, months start from 1
+	for (i = 1; i < tm.month; i++) {
+		if ( (i == 2) && LEAP_YEAR(tm.year)) { 
+			seconds += SECS_PER_DAY * 29;
+		} else {
+			seconds += SECS_PER_DAY * monthDays[i-1];  //monthDay array starts from 0
+		}
+	}
+	seconds+= (tm.day-1) * SECS_PER_DAY;
+	seconds+= tm.hour * SECS_PER_HOUR;
+	seconds+= tm.minute * SECS_PER_MIN;
+	seconds+= tm.second;
+	return (time_t)seconds; 
 }
-	
-void RTClock::setAlarmATime (tm * tm_ptr, bool hours_match, bool mins_match, bool secs_match, bool date_match) {
+
+//-----------------------------------------------------------------------------
+void RTClock::getTime(tm_t & tm)
+{
+    uint32_t dr_reg, tr_reg;
+	do { // read multiple time till both readings are equal
+		dr_reg = getDReg();
+		tr_reg = getTReg();
+	} while ( (dr_reg!=getDReg()) || (tr_reg!=getTReg()) );
+	tm.year    = _year(dr_reg);
+    tm.month   = _month(dr_reg);
+    tm.day     = _day(dr_reg);
+    tm.weekday = _weekday(dr_reg);
+    tm.pm      = _pm(tr_reg);
+    tm.hour    = _hour(tr_reg);
+    tm.minute  = _minute(tr_reg);
+    tm.second  = _second(tr_reg);
+}
+
+//-----------------------------------------------------------------------------
+time_t RTClock::getTime()
+{
+	getTime(tm);
+	return makeTime(tm);
+}
+
+//-----------------------------------------------------------------------------
+void RTClock::setAlarmATime (tm_t * tm_ptr, bool hours_match, bool mins_match, bool secs_match, bool date_match)
+{
     uint32 t = 0;
     rtc_enter_config_mode();
-    unsigned int bits = ((tm_ptr->tm_mday / 10) << 28) | ((tm_ptr->tm_mday % 10) << 24) |
-		        ((tm_ptr->tm_hour / 10) << 20) | ((tm_ptr->tm_hour % 10) << 16) | 
-			((tm_ptr->tm_min / 10) << 12) | ((tm_ptr->tm_min % 10) << 8) | 
-			((tm_ptr->tm_sec / 10) << 4) | (tm_ptr->tm_sec % 10);
+    unsigned int bits = ((tm_ptr->day / 10) << 28) | ((tm.day % 10) << 24) |
+		        ((tm_ptr->hour / 10) << 20) | ((tm_ptr->hour % 10) << 16) | 
+			((tm_ptr->minute / 10) << 12) | ((tm_ptr->minute % 10) << 8) | 
+			((tm_ptr->second / 10) << 4) | (tm_ptr->second % 10);
     if (!date_match) bits |= (1 << 31);
     if (!hours_match) bits |= (1 << 23);
     if (!mins_match) bits |= (1 << 15);
@@ -276,27 +306,30 @@ void RTClock::setAlarmATime (tm * tm_ptr, bool hours_match, bool mins_match, boo
     rtc_enable_alarm_event();
 }
 
-
-void RTClock::setAlarmATime (time_t alarm_time, bool hours_match, bool mins_match, bool secs_match, bool date_match) {	
-    struct tm* tm_ptr = gmtime(&alarm_time);
-    setAlarmATime(tm_ptr, hours_match, mins_match, secs_match, date_match);
+//-----------------------------------------------------------------------------
+void RTClock::setAlarmATime (time_t alarm_time, bool hours_match, bool mins_match, bool secs_match, bool date_match)
+{	
+    breakTime(alarm_time, tm);
+    setAlarmATime(&tm, hours_match, mins_match, secs_match, date_match);
 }
 
-
-void RTClock::turnOffAlarmA() {
+//-----------------------------------------------------------------------------
+void RTClock::turnOffAlarmA(void)
+{
     rtc_enter_config_mode();
     RTC_BASE->CR &= ~(1 << RTC_CR_ALRAIE_BIT); // turn off ALRAIE
     rtc_exit_config_mode();
 }
 
-
-void RTClock::setAlarmBTime (tm * tm_ptr, bool hours_match, bool mins_match, bool secs_match, bool date_match) {
+//-----------------------------------------------------------------------------
+void RTClock::setAlarmBTime (tm_t * tm_ptr, bool hours_match, bool mins_match, bool secs_match, bool date_match)
+{
     uint32 t = 0;
     rtc_enter_config_mode();
-    unsigned int bits = ((tm_ptr->tm_mday / 10) << 28) | ((tm_ptr->tm_mday % 10) << 24) |
-		        ((tm_ptr->tm_hour / 10) << 20) | ((tm_ptr->tm_hour % 10) << 16) | 
-			((tm_ptr->tm_min / 10) << 12) | ((tm_ptr->tm_min % 10) << 8) | 
-			((tm_ptr->tm_sec / 10) << 4) | (tm_ptr->tm_sec % 10);
+    unsigned int bits = ((tm_ptr->day / 10) << 28) | ((tm_ptr->day % 10) << 24) |
+		        ((tm_ptr->hour / 10) << 20) | ((tm_ptr->hour % 10) << 16) | 
+			((tm_ptr->minute / 10) << 12) | ((tm_ptr->minute % 10) << 8) | 
+			((tm_ptr->second / 10) << 4) | (tm_ptr->second % 10);
     if (!date_match) bits |= (1 << 31);
     if (!hours_match) bits |= (1 << 23);
     if (!mins_match) bits |= (1 << 15);
@@ -318,21 +351,23 @@ void RTClock::setAlarmBTime (tm * tm_ptr, bool hours_match, bool mins_match, boo
     rtc_enable_alarm_event();
 }
 
-
-void RTClock::setAlarmBTime (time_t alarm_time, bool hours_match, bool mins_match, bool secs_match, bool date_match) {	
-    struct tm* tm_ptr = gmtime(&alarm_time);
-    setAlarmBTime(tm_ptr, hours_match, mins_match, secs_match, date_match);
+//-----------------------------------------------------------------------------
+void RTClock::setAlarmBTime (time_t alarm_time, bool hours_match, bool mins_match, bool secs_match, bool date_match)
+{	
+    breakTime(alarm_time, tm);
+    setAlarmBTime(&tm, hours_match, mins_match, secs_match, date_match);
 }
 
-
+//-----------------------------------------------------------------------------
 void RTClock::turnOffAlarmB() {
     rtc_enter_config_mode();
     RTC_BASE->CR &= ~(1 << RTC_CR_ALRBIE_BIT); // turn off ALRBIE
     rtc_exit_config_mode();
 }
 
-
-void RTClock::setPeriodicWakeup(uint16 period) {
+//-----------------------------------------------------------------------------
+void RTClock::setPeriodicWakeup(uint16 period)
+{
     uint32 t = 0;
     rtc_enter_config_mode();
     RTC_BASE->CR &= ~(1 << RTC_CR_WUTE_BIT);
diff --git a/STM32F4/libraries/RTClock/src/RTClock.h b/STM32F4/libraries/RTClock/src/RTClock.h
index facaa0043..c13bf5f52 100644
--- a/STM32F4/libraries/RTClock/src/RTClock.h
+++ b/STM32F4/libraries/RTClock/src/RTClock.h
@@ -1,29 +1,35 @@
-#include <libmaple/rcc.h>
-#include <libmaple/bitband.h>
-#include <libmaple/pwr.h>
-#include <libmaple/bkp.h>
-#include <libmaple/nvic.h>
-#include <libmaple/exti.h>
-#include <time.h>
-
 
 #ifndef _RTCLOCK_H_
 #define _RTCLOCK_H_
 
-//#define RTC_DEBUG
 
 #ifdef __cplusplus
 extern "C" {
 #endif
+
+
+#include <sys/types.h> // for __time_t_defined
+#include <libmaple/rcc.h>
+#include <libmaple/bkp.h>
+#include <libmaple/exti.h>
+#include <stdio.h>
+#include <stdlib.h>
+#include <string.h>
+
+//#define RTC_DEBUG
+
+
+#if !defined(__time_t_defined) // avoid conflict with newlib or other posix libc
+  #warning "Using private time_t definintion"
+  typedef uint32_t time_t;
+#endif
+
 #ifdef RTC_DEBUG
         extern void dbg_printf(const char *fmt, ... );
         #define rtc_debug_printf(fmt, ...) dbg_printf(fmt, ##__VA_ARGS__);
 #else
         #define rtc_debug_printf(...) 
 #endif
-#ifdef __cplusplus
-}
-#endif
 
 
 #define SECS_PER_MIN  (60UL)
@@ -33,7 +39,7 @@ extern "C" {
 #define SECS_PER_WEEK (SECS_PER_DAY * DAYS_PER_WEEK)
 #define SECS_PER_YEAR (SECS_PER_WEEK * 52UL)
 #define SECS_YR_2000  (946684800UL) // the time at the start of y2k
-#define LEAP_YEAR(Y)     ( ((1970+Y)>0) && !((1970+Y)%4) && ( ((1970+Y)%100) || !((1970+Y)%400) ) )
+#define LEAP_YEAR(Y)  ( ((1970+Y)>0) && !((1970+Y)%4) && ( ((1970+Y)%100) || !((1970+Y)%400) ) )
 
 static  const unsigned char monthDays[]={31,28,31,30,31,30,31,31,30,31,30,31}; // API starts months from 1, this array starts from 0
 
@@ -91,6 +97,28 @@ typedef enum rtc_clk_src {
 	RTCSEL_HSE		= 0x13,
 } rtc_clk_src;
 
+// Time register
+#define RTC_TR_PM_BIT     22
+#define RTC_TR_HOUR_BIT   16
+#define RTC_TR_MINUTE_BIT  8
+#define RTC_TR_SECOND_BIT  0
+
+#define RTC_TR_PM_MASK     (0x01)//<<RTC_TR_PM_BIT)
+#define RTC_TR_HOUR_MASK   (0x3F)//<<RTC_TR_HOUR_BIT)
+#define RTC_TR_MINUTE_MASK (0x7F)//<<RTC_TR_MINUTE_BIT)
+#define RTC_TR_SECOND_MASK (0x7F)//<<RTC_TR_SECOND_BIT)
+
+// Date register
+#define RTC_DR_YEAR_BIT    16
+#define RTC_DR_WEEKDAY_BIT 13
+#define RTC_DR_MONTH_BIT    8
+#define RTC_DR_DAY_BIT      0
+
+#define RTC_DR_YEAR_MASK    (0xFF)//<<RTC_TR_YEAR_BIT)
+#define RTC_DR_WEEKDAY_MASK (0x07)//<<RTC_TR_WEEKDAY_BIT)
+#define RTC_DR_MONTH_MASK   (0x1F)//<<RTC_TR_MONTH_BIT)
+#define RTC_DR_DAY_MASK     (0x3F)//<<RTC_TR_DAY_BIT)
+
 
 /* Control Register */
 #define RTC_CR_TSIE_BIT 	15
@@ -118,24 +146,69 @@ typedef enum rtc_clk_src {
 #define RTC_ISR_ALRAWF_BIT 	0
 
 
+#define BUILD_TIME_REGISTER(h, m, s) ( ( bin2bcd((h&RTC_TR_HOUR_MASK)) << RTC_TR_HOUR_BIT ) | \
+                                       ( bin2bcd((m&RTC_TR_MINUTE_MASK)) << RTC_TR_MINUTE_BIT ) | \
+								       ( bin2bcd((s&RTC_TR_SECOND_MASK)) << RTC_TR_SECOND_BIT) )
+
+#define BUILD_DATE_REGISTER(y, m, d, wd) ( ( bin2bcd((y&RTC_DR_YEAR_MASK)) << RTC_DR_YEAR_BIT ) | \
+                                           ( bin2bcd((m&RTC_DR_MONTH_MASK)) << RTC_DR_MONTH_BIT) | \
+									       ( bin2bcd((d&RTC_DR_DAY_MASK)) << RTC_DR_DAY_BIT ) | \
+									       ( (wd&RTC_DR_WEEKDAY_MASK) << RTC_DR_WEEKDAY_BIT ) )
+
+typedef struct tm_t {
+	uint8_t  year;    // years since 1970
+	uint8_t  month;   // month of a year - [ 1 to 12 ]
+	uint8_t  day;     // day of a month - [ 1 to 31 ]
+	uint8_t  weekday; // day of a week (first day is Monday) - [ 1 to 7 ]
+	uint8_t  pm;      // AM: 0, PM: 1
+	uint8_t  hour;    // hour of a day - [ 0 to 23 ]
+	uint8_t  minute;  // minute of an hour - [ 0 to 59 ]
+	uint8_t  second;  // second of a minute - [ 0 to 59 ]
+} tm_t;
+
+static inline uint8_t bcd2bin(uint8_t b) { return ( (10*(b>>4)) + (b&0x0F) ); }
+static inline uint8_t bin2bcd(uint8_t b) { return ( ((b/10)<<4) + (b%10) ); }
 
 class RTClock {
- public:
- 	RTClock();
-        RTClock(rtc_clk_src src ); 
+  public:
+ 	RTClock() { RTClock(RTCSEL_LSE, 0, 0); }
+    RTClock(rtc_clk_src src ) { RTClock(src, 0, 0);	} 
 	RTClock(rtc_clk_src src, uint16 sync_prescaler, uint16 async_prescaler);
 	//~RTClock(); //to implement
+	
+	void breakTime(time_t epoch_time, tm_t & tm);
+	time_t makeTime(tm_t & tm);
 
 	void setTime (time_t time_stamp);
-	void setTime (struct tm * tm_ptr); 
+	void setTime (tm_t & tm); 
 	
-	struct tm* getTime(struct tm* tm_ptr); 
 	time_t getTime();
+	void getTime(tm_t & tm);
+	#define now getTime
+
+	uint8_t year(void)    { getTime(tm); return tm.year; }
+	uint8_t month(void)   { getTime(tm); return tm.month; }
+	uint8_t day(void)     { getTime(tm); return tm.day; }
+	uint8_t weekday(void) { getTime(tm); return tm.weekday; }
+	uint8_t hour(void)    { getTime(tm); return tm.hour; }
+	uint8_t minute(void)  { getTime(tm); return tm.minute; }
+	uint8_t second(void)  { getTime(tm); return tm.second; }
+	//uint8_t pm(void)      { return _pm(RTC_BASE->TR); }
+	uint8_t isPM(void)    { return ( hour()>=12 ); }
 	
-	void setAlarmATime (tm * tm_ptr, bool hours_match = true, bool mins_match = true, bool secs_match = true, bool date_match = false);
+	uint8_t year(time_t t)    { breakTime(t, tm); return tm.year; }
+	uint8_t month(time_t t)   { breakTime(t, tm); return tm.month; }
+	uint8_t day(time_t t)     { breakTime(t, tm); return tm.day; }
+	uint8_t weekday(time_t t) { breakTime(t, tm); return tm.weekday; }
+	uint8_t hour(time_t t)    { breakTime(t, tm); return tm.hour; }
+	uint8_t minute(time_t t)  { breakTime(t, tm); return tm.minute; }
+	uint8_t second(time_t t)  { breakTime(t, tm); return tm.second; }
+	uint8_t isPM(time_t t)    { return (hour(t)>=12); }
+	
+	void setAlarmATime (tm_t * tm_ptr, bool hours_match = true, bool mins_match = true, bool secs_match = true, bool date_match = false);
 	void setAlarmATime (time_t alarm_time, bool hours_match = true, bool mins_match = true, bool secs_match = true, bool date_match = false); 
 	void turnOffAlarmA();
-	void setAlarmBTime (tm * tm_ptr, bool hours_match = true, bool mins_match = true, bool secs_match = true, bool date_match = false);
+	void setAlarmBTime (tm_t * tm_ptr, bool hours_match = true, bool mins_match = true, bool secs_match = true, bool date_match = false);
 	void setAlarmBTime (time_t alarm_time, bool hours_match = true, bool mins_match = true, bool secs_match = true, bool date_match = false); 
 	void turnOffAlarmB();
 	
@@ -143,17 +216,29 @@ class RTClock {
 
 	void attachPeriodicWakeupInterrupt(voidFuncPtr function); 
 	void detachPeriodicWakeupInterrupt();
+	inline void attachSecondsInterrupt(voidFuncPtr function) { attachPeriodicWakeupInterrupt(function); }
+	inline void detachSecondsInterrupt() { detachPeriodicWakeupInterrupt(); }
 
 	void attachAlarmAInterrupt(voidFuncPtr function); 
 	void detachAlarmAInterrupt();
 	void attachAlarmBInterrupt(voidFuncPtr function); 
 	void detachAlarmBInterrupt();
 
- //private:
-
-} ;
+  private:
+	inline uint8_t _year(uint32_t dr)    { return bcd2bin( (dr>>RTC_DR_YEAR_BIT) & RTC_DR_YEAR_MASK ); }
+	inline uint8_t _month(uint32_t dr)   { return bcd2bin( (dr>>RTC_DR_MONTH_BIT) & RTC_DR_MONTH_MASK ); }
+	inline uint8_t _day(uint32_t dr)     { return bcd2bin( (dr>>RTC_DR_DAY_BIT) & RTC_DR_DAY_MASK ); }
+	inline uint8_t _weekday(uint32_t dr) { return bcd2bin( (dr>>RTC_DR_WEEKDAY_BIT) & RTC_DR_WEEKDAY_MASK ); }
+	inline uint8_t _pm(uint32_t tr)      { return ( (tr>>RTC_TR_PM_BIT) & RTC_TR_PM_MASK ); }
+	inline uint8_t _hour(uint32_t tr)    { return bcd2bin( (tr>>RTC_TR_HOUR_BIT) & RTC_TR_HOUR_MASK ); }
+	inline uint8_t _minute(uint32_t tr)  { return bcd2bin( (tr>>RTC_TR_MINUTE_BIT) & RTC_TR_MINUTE_MASK ); }
+	inline uint8_t _second(uint32_t tr)  { return bcd2bin( (tr>>RTC_TR_SECOND_BIT) & RTC_TR_SECOND_MASK ); }
 
+	tm_t tm;
+};
 
+inline uint32_t getTReg(void) { return (uint32_t)(RTC_BASE->TR); }
+inline uint32_t getDReg(void) { return (uint32_t)(RTC_BASE->DR); }
 
 /**
  * @brief Clear the register synchronized flag. The flag is then set by hardware after a write to PRL/DIV or CNT.
@@ -246,7 +331,8 @@ static inline void rtc_disable_wakeup_event() {
 	*bb_perip(&EXTI_BASE->RTSR, EXTI_RTC_WAKEUP_BIT) = 0;
 }
 
-
+#ifdef __cplusplus
+}
+#endif
 
 #endif // _RTCLOCK_H_
-                                                                                        
\ No newline at end of file

From 6b856152216df10212454461043930fd8e0f3bc8 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Thu, 20 Jul 2017 17:43:13 +1000
Subject: [PATCH 150/307] Change Wire endTransmission to have bool instead of
 unit8 argument - to match with the Arduino API

---
 STM32F1/libraries/Wire/WireBase.cpp | 2 +-
 STM32F1/libraries/Wire/WireBase.h   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/STM32F1/libraries/Wire/WireBase.cpp b/STM32F1/libraries/Wire/WireBase.cpp
index 73d039836..90ec37044 100644
--- a/STM32F1/libraries/Wire/WireBase.cpp
+++ b/STM32F1/libraries/Wire/WireBase.cpp
@@ -59,7 +59,7 @@ void WireBase::beginTransmission(int slave_address) {
     beginTransmission((uint8)slave_address);
 }
 
-uint8 WireBase::endTransmission(uint8 stop) {
+uint8 WireBase::endTransmission(bool stop) {
     uint8 retVal;
     if (tx_buf_overflow) {
         return EDATA;
diff --git a/STM32F1/libraries/Wire/WireBase.h b/STM32F1/libraries/Wire/WireBase.h
index 4038428d5..5e51ab78c 100644
--- a/STM32F1/libraries/Wire/WireBase.h
+++ b/STM32F1/libraries/Wire/WireBase.h
@@ -91,7 +91,7 @@ class WireBase { // Abstraction is awesome!
      * Call the process function to process the message if the TX
      * buffer has not overflowed.
      */
-    uint8 endTransmission(uint8);
+    uint8 endTransmission(bool);
     uint8 endTransmission(void);
 
     /*

From 0db43ae36f8e2f378fbd3d7fd4b834febd20dc0c Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Fri, 28 Jul 2017 17:51:54 +0200
Subject: [PATCH 151/307] SPI clean up + add 16 bit access functions in 8 bit
 mode

---
 STM32F1/libraries/SPI/src/SPI.cpp | 68 ++++++++++++-------------------
 STM32F1/libraries/SPI/src/SPI.h   | 44 +++++++++-----------
 2 files changed, 46 insertions(+), 66 deletions(-)

diff --git a/STM32F1/libraries/SPI/src/SPI.cpp b/STM32F1/libraries/SPI/src/SPI.cpp
index 94e5031c8..34df62e33 100644
--- a/STM32F1/libraries/SPI/src/SPI.cpp
+++ b/STM32F1/libraries/SPI/src/SPI.cpp
@@ -31,7 +31,6 @@
 
 #include "SPI.h"
 
-//#define SPI_DEBUG
 
 #include <libmaple/timer.h>
 #include <libmaple/util.h>
@@ -92,11 +91,10 @@ static const spi_pins board_spi_pins[] __FLASH__ = {
  * Constructor
  */
 
-SPIClass::SPIClass(uint32 spi_num) {
-
+SPIClass::SPIClass(uint32 spi_num)
+{
     _currentSetting=&_settings[spi_num-1];// SPI channels are called 1 2 and 3 but the array is zero indexed
 
-    
     switch (spi_num) {
 #if BOARD_NR_SPI >= 1
     case 1:
@@ -119,7 +117,7 @@ SPIClass::SPIClass(uint32 spi_num) {
     default:
         ASSERT(0);
     }
-    
+
     // Init things specific to each SPI device
     // clock divider setup is a bit of hack, and needs to be improved at a later date.
     _settings[0].spi_d = SPI1;
@@ -149,9 +147,6 @@ SPIClass::SPIClass(uint32 spi_num) {
  */
 void SPIClass::updateSettings(void) {
     uint32 flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | _currentSetting->dataSize | SPI_SW_SLAVE | SPI_SOFT_SS);
-    #ifdef SPI_DEBUG
-    Serial.print("spi_master_enable("); Serial.print(_currentSetting->clockDivider); Serial.print(","); Serial.print(_currentSetting->dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
-    #endif
     spi_master_enable(_currentSetting->spi_d, (spi_baud_rate)_currentSetting->clockDivider, (spi_mode)_currentSetting->dataMode, flags);
 }
 
@@ -167,9 +162,6 @@ void SPIClass::beginSlave(void) {
     spi_init(_currentSetting->spi_d);
     configure_gpios(_currentSetting->spi_d, 0);
     uint32 flags = ((_currentSetting->bitOrder == MSBFIRST ? SPI_FRAME_MSB : SPI_FRAME_LSB) | _currentSetting->dataSize | SPI_RX_ONLY);
-    #ifdef SPI_DEBUG
-    Serial.print("spi_slave_enable("); Serial.print(_currentSetting->dataMode); Serial.print(","); Serial.print(flags); Serial.println(")");
-    #endif
     spi_slave_enable(_currentSetting->spi_d, (spi_mode)_currentSetting->dataMode, flags);
     // added for DMA callbacks.
     _currentSetting->state = SPI_STATE_READY;
@@ -199,9 +191,6 @@ void SPIClass::end(void) {
 /* Roger Clark added  3 functions */
 void SPIClass::setClockDivider(uint32_t clockDivider)
 {
-    #ifdef SPI_DEBUG
-    Serial.print("Clock divider set to "); Serial.println(clockDivider);
-    #endif
     _currentSetting->clockDivider = clockDivider;
     uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_BR);
     _currentSetting->spi_d->regs->CR1 = cr1 | (clockDivider & SPI_CR1_BR);
@@ -209,9 +198,6 @@ void SPIClass::setClockDivider(uint32_t clockDivider)
 
 void SPIClass::setBitOrder(BitOrder bitOrder)
 {
-    #ifdef SPI_DEBUG
-    Serial.print("Bit order set to "); Serial.println(bitOrder);
-    #endif
     _currentSetting->bitOrder = bitOrder;
     uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_LSBFIRST);
     if ( bitOrder==LSBFIRST )	cr1 |= SPI_CR1_LSBFIRST;
@@ -258,9 +244,6 @@ bit 0 - CPHA : Clock phase
  
 If someone finds this is not the case or sees a logic error with this let me know ;-) 
  */
-    #ifdef SPI_DEBUG
-    Serial.print("Data mode set to "); Serial.println(dataMode);
-    #endif
     _currentSetting->dataMode = dataMode;
     uint32 cr1 = _currentSetting->spi_d->regs->CR1 & ~(SPI_CR1_CPOL|SPI_CR1_CPHA);
     _currentSetting->spi_d->regs->CR1 = cr1 | (dataMode & (SPI_CR1_CPOL|SPI_CR1_CPHA));
@@ -268,9 +251,6 @@ If someone finds this is not the case or sees a logic error with this let me kno
 
 void SPIClass::beginTransaction(uint8_t pin, SPISettings settings)
 {
-    #ifdef SPI_DEBUG
-    Serial.println("SPIClass::beginTransaction");
-    #endif
     setBitOrder(settings.bitOrder);
     setDataMode(settings.dataMode);
     setDataSize(settings.dataSize);
@@ -280,9 +260,6 @@ void SPIClass::beginTransaction(uint8_t pin, SPISettings settings)
 
 void SPIClass::beginTransactionSlave(SPISettings settings)
 {
-    #ifdef SPI_DEBUG
-    Serial.println(F("SPIClass::beginTransactionSlave"));
-    #endif
     setBitOrder(settings.bitOrder);
     setDataMode(settings.dataMode);
     setDataSize(settings.dataSize);
@@ -291,9 +268,6 @@ void SPIClass::beginTransactionSlave(SPISettings settings)
 
 void SPIClass::endTransaction(void)
 {
-    #ifdef SPI_DEBUG
-    Serial.println("SPIClass::endTransaction");
-    #endif
     //digitalWrite(_SSPin,HIGH);
 #if false
 // code from SAM core
@@ -355,6 +329,16 @@ void SPIClass::write(uint16 data)
     while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
 }
 
+void SPIClass::write16(uint16 data)
+{
+    // Added by stevestrong: write two consecutive bytes in 8 bit mode (DFF=0)
+    spi_tx_reg(_currentSetting->spi_d, data>>8); // write high byte
+    while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // Wait until TXE=1
+    spi_tx_reg(_currentSetting->spi_d, data); // write low byte
+    while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // Wait until TXE=1
+    while (spi_is_busy(_currentSetting->spi_d) != 0); // wait until BSY=0
+}
+
 void SPIClass::write(uint16 data, uint32 n)
 {
     // Added by stevstrong: Repeatedly send same data by the specified number of times
@@ -384,14 +368,21 @@ uint8 SPIClass::transfer(uint8 byte) const
     return (uint8)spi_rx_reg(spi_d); // "... and read the last received data."
 }
 
-uint16_t SPIClass::transfer16(uint16_t wr_data) const
+uint16_t SPIClass::transfer16(uint16_t data) const
 {
+    // Modified by stevestrong: write & read two consecutive bytes in 8 bit mode (DFF=0)
+	// This is more effective than two distinct byte transfers
     spi_dev * spi_d = _currentSetting->spi_d;
-    spi_rx_reg(spi_d); // read any previous data
-    spi_tx_reg(spi_d, wr_data); // "2. Write the first data item to be transmitted into the SPI_DR register (this clears the TXE flag)."
-    while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
-    while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
-    return (uint16)spi_rx_reg(spi_d); // "... and read the last received data."
+    spi_rx_reg(spi_d);                   // read any previous data
+    spi_tx_reg(spi_d, data>>8);          // write high byte
+    while (spi_is_tx_empty(spi_d) == 0); // wait until TXE=1
+    while (spi_is_busy(spi_d) != 0);     // wait until BSY=0
+	uint16_t ret = spi_rx_reg(spi_d)<<8; // read and shift high byte
+    spi_tx_reg(spi_d, data);             // write low byte
+    while (spi_is_tx_empty(spi_d) == 0); // wait until TXE=1
+    while (spi_is_busy(spi_d) != 0);     // wait until BSY=0
+	ret += spi_rx_reg(spi_d);            // read low byte
+    return ret;
 }
 
 /*  Roger Clark and Victor Perez, 2015
@@ -523,7 +514,7 @@ uint8 SPIClass::dmaSendAsync(void * transmitBuf, uint16 length, bool minc) {
             //delayMicroseconds(10);
             if ((millis() - m) > DMA_TIMEOUT) { b = 2; break; }
         }		
-        
+
         while (spi_is_tx_empty(_currentSetting->spi_d) == 0); // "5. Wait until TXE=1 ..."
         while (spi_is_busy(_currentSetting->spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI." 
         spi_tx_dma_disable(_currentSetting->spi_d);
@@ -531,11 +522,9 @@ uint8 SPIClass::dmaSendAsync(void * transmitBuf, uint16 length, bool minc) {
         _currentSetting->state = SPI_STATE_READY;
     }
 
-    
     if (length == 0) return 0;
     uint32 flags = ( (DMA_MINC_MODE*minc) | DMA_FROM_MEM | DMA_TRNS_CMPLT);
 
-    
     dma_init(_currentSetting->spiDmaDev);
     // TX
     dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
@@ -770,9 +759,6 @@ static const spi_baud_rate baud_rates[8] __FLASH__ = {
 */
 static spi_baud_rate determine_baud_rate(spi_dev *dev, uint32_t freq) {
     uint32_t clock = 0, i;
-    #ifdef SPI_DEBUG
-    Serial.print("determine_baud_rate("); Serial.print(freq); Serial.println(")");
-    #endif
     switch (rcc_dev_clk(dev->clk_id))
     {
     case RCC_APB2: clock = STM32_PCLK2; break; // 72 Mhz
diff --git a/STM32F1/libraries/SPI/src/SPI.h b/STM32F1/libraries/SPI/src/SPI.h
index 2160d2696..25eea861c 100644
--- a/STM32F1/libraries/SPI/src/SPI.h
+++ b/STM32F1/libraries/SPI/src/SPI.h
@@ -176,8 +176,6 @@ static void (*_spi3_this);
 class SPIClass {
 public:
 
-
-
     /**
      * @param spiPortNumber Number of the SPI port to manage.
      */
@@ -187,8 +185,6 @@ class SPIClass {
      * Set up/tear down
      */
 
-
-
     /**
      * @brief Equivalent to begin(SPI_1_125MHZ, MSBFIRST, 0).
      */
@@ -268,14 +264,15 @@ class SPIClass {
      * @brief Transmit one byte/word.
      * @param data to transmit.
      */
-    void write(uint16 data);	
-	
+    void write(uint16 data);
+    void write16(uint16 data); // write 2 bytes in 8 bit mode (DFF=0)
+
     /**
      * @brief Transmit one byte/word a specified number of times.
      * @param data to transmit.
      */
     void write(uint16 data, uint32 n);	
-	
+
     /**
      * @brief Transmit multiple bytes/words.
      * @param buffer Bytes/words to transmit.
@@ -293,7 +290,7 @@ class SPIClass {
      */
     uint8 transfer(uint8 data) const;
     uint16_t transfer16(uint16_t data) const;
-	
+
 	/**
      * @brief Sets up a DMA Transfer for "length" bytes.
 	 * The transfer mode (8 or 16 bit mode) is evaluated from the SPI peripheral setting.
@@ -321,7 +318,7 @@ class SPIClass {
     uint8 dmaSend(void * transmitBuf, uint16 length, bool minc = 1);
     void dmaSendSet(void * transmitBuf, bool minc);
     uint8 dmaSendRepeat(uint16 length);
-	
+
     uint8 dmaSendAsync(void * transmitBuf, uint16 length, bool minc = 1);
     /*
      * Pin accessors
@@ -354,24 +351,21 @@ class SPIClass {
      *        this HardwareSPI instance.
      */
     spi_dev* c_dev(void) { return _currentSetting->spi_d; }
-	
-		
+
     spi_dev *dev(){ return _currentSetting->spi_d;}
-	
-	 /**
-     * @brief Sets the number of the SPI peripheral to be used by
-     *        this HardwareSPI instance.
-	 *
-	 * @param spi_num Number of the SPI port. 1-2 in low density devices
-	 *			or 1-3 in high density devices.
-     */
-	
+
+    /**
+    * @brief Sets the number of the SPI peripheral to be used by
+    *        this HardwareSPI instance.
+    *
+    * @param spi_num Number of the SPI port. 1-2 in low density devices
+    *			or 1-3 in high density devices.
+    */
     void setModule(int spi_num)
     {
         _currentSetting=&_settings[spi_num-1];// SPI channels are called 1 2 and 3 but the array is zero indexed
     }
 
-
     /* -- The following methods are deprecated --------------------------- */
 
     /**
@@ -403,20 +397,20 @@ class SPIClass {
      * @see HardwareSPI::read()
      */
     uint8 recv(void);
-	
+
 private:
 
 	SPISettings _settings[BOARD_NR_SPI];
 	SPISettings *_currentSetting;
-	
+
 	void updateSettings(void);
     /*
 	* Functions added for DMA transfers with Callback. 
 	* Experimental.
 	*/
-	
+
     void EventCallback(void);
-    
+
     static void _spi1EventCallback(void);
     static void _spi2EventCallback(void);
     #if BOARD_NR_SPI >= 3

From 0aae3d31f1ca1a43b1afc3619acf215406837e39 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sun, 30 Jul 2017 16:07:30 +1000
Subject: [PATCH 152/307] Changed order of optimisation options, so that
 current settings (-Os) are the default, and reverted F4 and F3 boards.txt to
 current master to remove these changes from those boards, as they will need
 to be updated in the same way I did for the F1, and I don't have time to do
 it now

---
 STM32F1/boards.txt | 442 ++++++++++++++++++++++-----------------------
 STM32F3/boards.txt |  34 ----
 STM32F4/boards.txt | 133 +-------------
 3 files changed, 222 insertions(+), 387 deletions(-)

diff --git a/STM32F1/boards.txt b/STM32F1/boards.txt
index b52623640..fe18609e1 100644
--- a/STM32F1/boards.txt
+++ b/STM32F1/boards.txt
@@ -45,36 +45,36 @@ mapleMini.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
 mapleMini.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
 
 #-- Optimizations
-mapleMini.menu.opt.o2std=Faster
-mapleMini.menu.opt.o2std.build.flags.optimize=-O2
-mapleMini.menu.opt.o2std.build.flags.ldspecs=
-mapleMini.menu.opt.o2lto=Faster with LTO
-mapleMini.menu.opt.o2lto.build.flags.optimize=-O2 -flto
-mapleMini.menu.opt.o2lto.build.flags.ldspecs=-flto
-mapleMini.menu.opt.o1std=Fast
+mapleMini.menu.opt.osstd=Smallest (default)
+mapleMini.menu.opt.osstd.build.flags.optimize=-Os
+mapleMini.menu.opt.osstd.build.flags.ldspecs=
+mapleMini.menu.opt.oslto=Smallest Code with LTO
+mapleMini.menu.opt.oslto.build.flags.optimize=-Os -flto
+mapleMini.menu.opt.oslto.build.flags.ldspecs=-flto
+mapleMini.menu.opt.o1std=Fast (-O1)
 mapleMini.menu.opt.o1std.build.flags.optimize=-O1
 mapleMini.menu.opt.o1std.build.flags.ldspecs=
-mapleMini.menu.opt.o1lto=Fast with LTO
+mapleMini.menu.opt.o1lto=Fast (-O1) with LTO
 mapleMini.menu.opt.o1lto.build.flags.optimize=-O1 -flto
 mapleMini.menu.opt.o1lto.build.flags.ldspecs=-flto
-mapleMini.menu.opt.o3std=Fastest
+mapleMini.menu.opt.o2std=Faster (-O2)
+mapleMini.menu.opt.o2std.build.flags.optimize=-O2
+mapleMini.menu.opt.o2std.build.flags.ldspecs=
+mapleMini.menu.opt.o2lto=Faster (-O2) with LTO
+mapleMini.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+mapleMini.menu.opt.o2lto.build.flags.ldspecs=-flto
+mapleMini.menu.opt.o3std=Fastest (-03)
 mapleMini.menu.opt.o3std.build.flags.optimize=-O3
 mapleMini.menu.opt.o3std.build.flags.ldspecs=
-mapleMini.menu.opt.o3lto=Fastest with LTO
+mapleMini.menu.opt.o3lto=Fastest (-0) with LTO
 mapleMini.menu.opt.o3lto.build.flags.optimize=-O3 -flto
 mapleMini.menu.opt.o3lto.build.flags.ldspecs=-flto
-mapleMini.menu.opt.ogstd=Debug
+mapleMini.menu.opt.ogstd=Debug (-g)
 mapleMini.menu.opt.ogstd.build.flags.optimize=-Og
 mapleMini.menu.opt.ogstd.build.flags.ldspecs=
 mapleMini.menu.opt.oglto=Debug with LTO
 mapleMini.menu.opt.oglto.build.flags.optimize=-Og -flto
 mapleMini.menu.opt.oglto.build.flags.ldspecs=-flto
-mapleMini.menu.opt.osstd=Smallest Code
-mapleMini.menu.opt.osstd.build.flags.optimize=-Os
-mapleMini.menu.opt.osstd.build.flags.ldspecs=
-mapleMini.menu.opt.oslto=Smallest Code with LTO
-mapleMini.menu.opt.oslto.build.flags.optimize=-Os -flto
-mapleMini.menu.opt.oslto.build.flags.ldspecs=-flto
 
 
 ##############################################################
@@ -100,36 +100,36 @@ maple.build.variant=maple
 maple.build.vect=VECT_TAB_ADDR=0x8005000
 
 #-- Optimizations
-maple.menu.opt.o2std=Faster
-maple.menu.opt.o2std.build.flags.optimize=-O2
-maple.menu.opt.o2std.build.flags.ldspecs=
-maple.menu.opt.o2lto=Faster with LTO
-maple.menu.opt.o2lto.build.flags.optimize=-O2 -flto
-maple.menu.opt.o2lto.build.flags.ldspecs=-flto
-maple.menu.opt.o1std=Fast
+maple.menu.opt.osstd=Smallest (default)
+maple.menu.opt.osstd.build.flags.optimize=-Os
+maple.menu.opt.osstd.build.flags.ldspecs=
+maple.menu.opt.oslto=Smallest Code with LTO
+maple.menu.opt.oslto.build.flags.optimize=-Os -flto
+maple.menu.opt.oslto.build.flags.ldspecs=-flto
+maple.menu.opt.o1std=Fast (-O1)
 maple.menu.opt.o1std.build.flags.optimize=-O1
 maple.menu.opt.o1std.build.flags.ldspecs=
-maple.menu.opt.o1lto=Fast with LTO
+maple.menu.opt.o1lto=Fast (-O1) with LTO
 maple.menu.opt.o1lto.build.flags.optimize=-O1 -flto
 maple.menu.opt.o1lto.build.flags.ldspecs=-flto
-maple.menu.opt.o3std=Fastest
+maple.menu.opt.o2std=Faster (-O2)
+maple.menu.opt.o2std.build.flags.optimize=-O2
+maple.menu.opt.o2std.build.flags.ldspecs=
+maple.menu.opt.o2lto=Faster (-O2) with LTO
+maple.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+maple.menu.opt.o2lto.build.flags.ldspecs=-flto
+maple.menu.opt.o3std=Fastest (-03)
 maple.menu.opt.o3std.build.flags.optimize=-O3
 maple.menu.opt.o3std.build.flags.ldspecs=
-maple.menu.opt.o3lto=Fastest with LTO
+maple.menu.opt.o3lto=Fastest (-0) with LTO
 maple.menu.opt.o3lto.build.flags.optimize=-O3 -flto
 maple.menu.opt.o3lto.build.flags.ldspecs=-flto
-maple.menu.opt.ogstd=Debug
+maple.menu.opt.ogstd=Debug (-g)
 maple.menu.opt.ogstd.build.flags.optimize=-Og
 maple.menu.opt.ogstd.build.flags.ldspecs=
 maple.menu.opt.oglto=Debug with LTO
 maple.menu.opt.oglto.build.flags.optimize=-Og -flto
 maple.menu.opt.oglto.build.flags.ldspecs=-flto
-maple.menu.opt.osstd=Smallest Code
-maple.menu.opt.osstd.build.flags.optimize=-Os
-maple.menu.opt.osstd.build.flags.ldspecs=
-maple.menu.opt.oslto=Smallest Code with LTO
-maple.menu.opt.oslto.build.flags.optimize=-Os -flto
-maple.menu.opt.oslto.build.flags.ldspecs=-flto
 
 ##############################################################
 mapleRET6.name=Maple (RET6)
@@ -155,36 +155,36 @@ mapleRET6.upload.altID=1
 mapleRET6.upload.auto_reset=true
 
 #-- Optimizations
-mapleRET6.menu.opt.o2std=Faster
-mapleRET6.menu.opt.o2std.build.flags.optimize=-O2
-mapleRET6.menu.opt.o2std.build.flags.ldspecs=
-mapleRET6.menu.opt.o2lto=Faster with LTO
-mapleRET6.menu.opt.o2lto.build.flags.optimize=-O2 -flto
-mapleRET6.menu.opt.o2lto.build.flags.ldspecs=-flto
-mapleRET6.menu.opt.o1std=Fast
+mapleRET6.menu.opt.osstd=Smallest (default)
+mapleRET6.menu.opt.osstd.build.flags.optimize=-Os
+mapleRET6.menu.opt.osstd.build.flags.ldspecs=
+mapleRET6.menu.opt.oslto=Smallest Code with LTO
+mapleRET6.menu.opt.oslto.build.flags.optimize=-Os -flto
+mapleRET6.menu.opt.oslto.build.flags.ldspecs=-flto
+mapleRET6.menu.opt.o1std=Fast (-O1)
 mapleRET6.menu.opt.o1std.build.flags.optimize=-O1
 mapleRET6.menu.opt.o1std.build.flags.ldspecs=
-mapleRET6.menu.opt.o1lto=Fast with LTO
+mapleRET6.menu.opt.o1lto=Fast (-O1) with LTO
 mapleRET6.menu.opt.o1lto.build.flags.optimize=-O1 -flto
 mapleRET6.menu.opt.o1lto.build.flags.ldspecs=-flto
-mapleRET6.menu.opt.o3std=Fastest
+mapleRET6.menu.opt.o2std=Faster (-O2)
+mapleRET6.menu.opt.o2std.build.flags.optimize=-O2
+mapleRET6.menu.opt.o2std.build.flags.ldspecs=
+mapleRET6.menu.opt.o2lto=Faster (-O2) with LTO
+mapleRET6.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+mapleRET6.menu.opt.o2lto.build.flags.ldspecs=-flto
+mapleRET6.menu.opt.o3std=Fastest (-03)
 mapleRET6.menu.opt.o3std.build.flags.optimize=-O3
 mapleRET6.menu.opt.o3std.build.flags.ldspecs=
-mapleRET6.menu.opt.o3lto=Fastest with LTO
+mapleRET6.menu.opt.o3lto=Fastest (-0) with LTO
 mapleRET6.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+mapleRET6.menu.opt.ogstd=Debug (-g)
 mapleRET6.menu.opt.o3lto.build.flags.ldspecs=-flto
-mapleRET6.menu.opt.ogstd=Debug
 mapleRET6.menu.opt.ogstd.build.flags.optimize=-Og
 mapleRET6.menu.opt.ogstd.build.flags.ldspecs=
 mapleRET6.menu.opt.oglto=Debug with LTO
 mapleRET6.menu.opt.oglto.build.flags.optimize=-Og -flto
 mapleRET6.menu.opt.oglto.build.flags.ldspecs=-flto
-mapleRET6.menu.opt.osstd=Smallest Code
-mapleRET6.menu.opt.osstd.build.flags.optimize=-Os
-mapleRET6.menu.opt.osstd.build.flags.ldspecs=
-mapleRET6.menu.opt.oslto=Smallest Code with LTO
-mapleRET6.menu.opt.oslto.build.flags.optimize=-Os -flto
-mapleRET6.menu.opt.oslto.build.flags.ldspecs=-flto
 
 ##############################################################
 
@@ -218,36 +218,36 @@ microduino32_flash.build.error_led_pin=1
 microduino32_flash.build.gcc_ver=gcc-arm-none-eabi-4.8.3-2014q1
 
 #-- Optimizations
-microduino32_flash.menu.opt.o2std=Faster
-microduino32_flash.menu.opt.o2std.build.flags.optimize=-O2
-microduino32_flash.menu.opt.o2std.build.flags.ldspecs=
-microduino32_flash.menu.opt.o2lto=Faster with LTO
-microduino32_flash.menu.opt.o2lto.build.flags.optimize=-O2 -flto
-microduino32_flash.menu.opt.o2lto.build.flags.ldspecs=-flto
-microduino32_flash.menu.opt.o1std=Fast
+microduino32_flash.menu.opt.osstd=Smallest (default)
+microduino32_flash.menu.opt.osstd.build.flags.optimize=-Os
+microduino32_flash.menu.opt.osstd.build.flags.ldspecs=
+microduino32_flash.menu.opt.oslto=Smallest Code with LTO
+microduino32_flash.menu.opt.oslto.build.flags.optimize=-Os -flto
+microduino32_flash.menu.opt.oslto.build.flags.ldspecs=-flto
+microduino32_flash.menu.opt.o1std=Fast (-O1)
 microduino32_flash.menu.opt.o1std.build.flags.optimize=-O1
 microduino32_flash.menu.opt.o1std.build.flags.ldspecs=
-microduino32_flash.menu.opt.o1lto=Fast with LTO
+microduino32_flash.menu.opt.o1lto=Fast (-O1) with LTO
 microduino32_flash.menu.opt.o1lto.build.flags.optimize=-O1 -flto
 microduino32_flash.menu.opt.o1lto.build.flags.ldspecs=-flto
-microduino32_flash.menu.opt.o3std=Fastest
+microduino32_flash.menu.opt.o2std=Faster (-O2)
+microduino32_flash.menu.opt.o2std.build.flags.optimize=-O2
+microduino32_flash.menu.opt.o2std.build.flags.ldspecs=
+microduino32_flash.menu.opt.o2lto=Faster (-O2) with LTO
+microduino32_flash.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+microduino32_flash.menu.opt.o2lto.build.flags.ldspecs=-flto
+microduino32_flash.menu.opt.o3std=Fastest (-03)
 microduino32_flash.menu.opt.o3std.build.flags.optimize=-O3
 microduino32_flash.menu.opt.o3std.build.flags.ldspecs=
-microduino32_flash.menu.opt.o3lto=Fastest with LTO
+microduino32_flash.menu.opt.o3lto=Fastest (-0) with LTO
 microduino32_flash.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+microduino32_flash.menu.opt.ogstd=Debug (-g)
 microduino32_flash.menu.opt.o3lto.build.flags.ldspecs=-flto
-microduino32_flash.menu.opt.ogstd=Debug
 microduino32_flash.menu.opt.ogstd.build.flags.optimize=-Og
 microduino32_flash.menu.opt.ogstd.build.flags.ldspecs=
 microduino32_flash.menu.opt.oglto=Debug with LTO
 microduino32_flash.menu.opt.oglto.build.flags.optimize=-Og -flto
 microduino32_flash.menu.opt.oglto.build.flags.ldspecs=-flto
-microduino32_flash.menu.opt.osstd=Smallest Code
-microduino32_flash.menu.opt.osstd.build.flags.optimize=-Os
-microduino32_flash.menu.opt.osstd.build.flags.ldspecs=
-microduino32_flash.menu.opt.oslto=Smallest Code with LTO
-microduino32_flash.menu.opt.oslto.build.flags.optimize=-Os -flto
-microduino32_flash.menu.opt.oslto.build.flags.ldspecs=-flto
 
 ##############################################################
 nucleo_f103rb.name=STM Nucleo F103RB (STLink)
@@ -288,36 +288,36 @@ nucleo_f103rb.menu.device_variant.NucleoF103_HSE.build.f_cpu=72000000L
 nucleo_f103rb.menu.device_variant.NucleoF103_HSE.build.extra_flags=-DNUCLEO_HSE_CRYSTAL -DMCU_STM32F103RB -mthumb -march=armv7-m -D__STM32F1__
 
 #-- Optimizations
-nucleo_f103rb.menu.opt.o2std=Faster
-nucleo_f103rb.menu.opt.o2std.build.flags.optimize=-O2
-nucleo_f103rb.menu.opt.o2std.build.flags.ldspecs=
-nucleo_f103rb.menu.opt.o2lto=Faster with LTO
-nucleo_f103rb.menu.opt.o2lto.build.flags.optimize=-O2 -flto
-nucleo_f103rb.menu.opt.o2lto.build.flags.ldspecs=-flto
-nucleo_f103rb.menu.opt.o1std=Fast
+nucleo_f103rb.menu.opt.osstd=Smallest (default)
+nucleo_f103rb.menu.opt.osstd.build.flags.optimize=-Os
+nucleo_f103rb.menu.opt.osstd.build.flags.ldspecs=
+nucleo_f103rb.menu.opt.oslto=Smallest Code with LTO
+nucleo_f103rb.menu.opt.oslto.build.flags.optimize=-Os -flto
+nucleo_f103rb.menu.opt.oslto.build.flags.ldspecs=-flto
+nucleo_f103rb.menu.opt.o1std=Fast (-O1)
 nucleo_f103rb.menu.opt.o1std.build.flags.optimize=-O1
 nucleo_f103rb.menu.opt.o1std.build.flags.ldspecs=
-nucleo_f103rb.menu.opt.o1lto=Fast with LTO
+nucleo_f103rb.menu.opt.o1lto=Fast (-O1) with LTO
 nucleo_f103rb.menu.opt.o1lto.build.flags.optimize=-O1 -flto
 nucleo_f103rb.menu.opt.o1lto.build.flags.ldspecs=-flto
-nucleo_f103rb.menu.opt.o3std=Fastest
+nucleo_f103rb.menu.opt.o2std=Faster (-O2)
+nucleo_f103rb.menu.opt.o2std.build.flags.optimize=-O2
+nucleo_f103rb.menu.opt.o2std.build.flags.ldspecs=
+nucleo_f103rb.menu.opt.o2lto=Faster (-O2) with LTO
+nucleo_f103rb.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+nucleo_f103rb.menu.opt.o2lto.build.flags.ldspecs=-flto
+nucleo_f103rb.menu.opt.o3std=Fastest (-03)
 nucleo_f103rb.menu.opt.o3std.build.flags.optimize=-O3
 nucleo_f103rb.menu.opt.o3std.build.flags.ldspecs=
-nucleo_f103rb.menu.opt.o3lto=Fastest with LTO
+nucleo_f103rb.menu.opt.o3lto=Fastest (-0) with LTO
 nucleo_f103rb.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+nucleo_f103rb.menu.opt.ogstd=Debug (-g)
 nucleo_f103rb.menu.opt.o3lto.build.flags.ldspecs=-flto
-nucleo_f103rb.menu.opt.ogstd=Debug
 nucleo_f103rb.menu.opt.ogstd.build.flags.optimize=-Og
 nucleo_f103rb.menu.opt.ogstd.build.flags.ldspecs=
 nucleo_f103rb.menu.opt.oglto=Debug with LTO
 nucleo_f103rb.menu.opt.oglto.build.flags.optimize=-Og -flto
 nucleo_f103rb.menu.opt.oglto.build.flags.ldspecs=-flto
-nucleo_f103rb.menu.opt.osstd=Smallest Code
-nucleo_f103rb.menu.opt.osstd.build.flags.optimize=-Os
-nucleo_f103rb.menu.opt.osstd.build.flags.ldspecs=
-nucleo_f103rb.menu.opt.oslto=Smallest Code with LTO
-nucleo_f103rb.menu.opt.oslto.build.flags.optimize=-Os -flto
-nucleo_f103rb.menu.opt.oslto.build.flags.ldspecs=-flto
 
 ###################### Generic STM32F103C ########################################
 
@@ -385,36 +385,36 @@ genericSTM32F103C.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
 genericSTM32F103C.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
 
 #-- Optimizations
-genericSTM32F103C.menu.opt.o2std=Faster
-genericSTM32F103C.menu.opt.o2std.build.flags.optimize=-O2
-genericSTM32F103C.menu.opt.o2std.build.flags.ldspecs=
-genericSTM32F103C.menu.opt.o2lto=Faster with LTO
-genericSTM32F103C.menu.opt.o2lto.build.flags.optimize=-O2 -flto
-genericSTM32F103C.menu.opt.o2lto.build.flags.ldspecs=-flto
-genericSTM32F103C.menu.opt.o1std=Fast
+genericSTM32F103C.menu.opt.osstd=Smallest (default)
+genericSTM32F103C.menu.opt.osstd.build.flags.optimize=-Os
+genericSTM32F103C.menu.opt.osstd.build.flags.ldspecs=
+genericSTM32F103C.menu.opt.oslto=Smallest Code with LTO
+genericSTM32F103C.menu.opt.oslto.build.flags.optimize=-Os -flto
+genericSTM32F103C.menu.opt.oslto.build.flags.ldspecs=-flto
+genericSTM32F103C.menu.opt.o1std=Fast (-O1)
 genericSTM32F103C.menu.opt.o1std.build.flags.optimize=-O1
 genericSTM32F103C.menu.opt.o1std.build.flags.ldspecs=
-genericSTM32F103C.menu.opt.o1lto=Fast with LTO
+genericSTM32F103C.menu.opt.o1lto=Fast (-O1) with LTO
 genericSTM32F103C.menu.opt.o1lto.build.flags.optimize=-O1 -flto
 genericSTM32F103C.menu.opt.o1lto.build.flags.ldspecs=-flto
-genericSTM32F103C.menu.opt.o3std=Fastest
+genericSTM32F103C.menu.opt.o2std=Faster (-O2)
+genericSTM32F103C.menu.opt.o2std.build.flags.optimize=-O2
+genericSTM32F103C.menu.opt.o2std.build.flags.ldspecs=
+genericSTM32F103C.menu.opt.o2lto=Faster (-O2) with LTO
+genericSTM32F103C.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+genericSTM32F103C.menu.opt.o2lto.build.flags.ldspecs=-flto
+genericSTM32F103C.menu.opt.o3std=Fastest (-03)
 genericSTM32F103C.menu.opt.o3std.build.flags.optimize=-O3
 genericSTM32F103C.menu.opt.o3std.build.flags.ldspecs=
-genericSTM32F103C.menu.opt.o3lto=Fastest with LTO
+genericSTM32F103C.menu.opt.o3lto=Fastest (-0) with LTO
 genericSTM32F103C.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+genericSTM32F103C.menu.opt.ogstd=Debug (-g)
 genericSTM32F103C.menu.opt.o3lto.build.flags.ldspecs=-flto
-genericSTM32F103C.menu.opt.ogstd=Debug
 genericSTM32F103C.menu.opt.ogstd.build.flags.optimize=-Og
 genericSTM32F103C.menu.opt.ogstd.build.flags.ldspecs=
 genericSTM32F103C.menu.opt.oglto=Debug with LTO
 genericSTM32F103C.menu.opt.oglto.build.flags.optimize=-Og -flto
 genericSTM32F103C.menu.opt.oglto.build.flags.ldspecs=-flto
-genericSTM32F103C.menu.opt.osstd=Smallest Code
-genericSTM32F103C.menu.opt.osstd.build.flags.optimize=-Os
-genericSTM32F103C.menu.opt.osstd.build.flags.ldspecs=
-genericSTM32F103C.menu.opt.oslto=Smallest Code with LTO
-genericSTM32F103C.menu.opt.oslto.build.flags.optimize=-Os -flto
-genericSTM32F103C.menu.opt.oslto.build.flags.ldspecs=-flto
 
 ########################### Generic STM32F103R ###########################
 
@@ -486,36 +486,36 @@ genericSTM32F103R.menu.upload_method.BMPMethod.upload.tool=bmp_upload
 genericSTM32F103R.menu.upload_method.BMPMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG
 
 #-- Optimizations
-genericSTM32F103R.menu.opt.o2std=Faster
-genericSTM32F103R.menu.opt.o2std.build.flags.optimize=-O2
-genericSTM32F103R.menu.opt.o2std.build.flags.ldspecs=
-genericSTM32F103R.menu.opt.o2lto=Faster with LTO
-genericSTM32F103R.menu.opt.o2lto.build.flags.optimize=-O2 -flto
-genericSTM32F103R.menu.opt.o2lto.build.flags.ldspecs=-flto
-genericSTM32F103R.menu.opt.o1std=Fast
+genericSTM32F103R.menu.opt.osstd=Smallest (default)
+genericSTM32F103R.menu.opt.osstd.build.flags.optimize=-Os
+genericSTM32F103R.menu.opt.osstd.build.flags.ldspecs=
+genericSTM32F103R.menu.opt.oslto=Smallest Code with LTO
+genericSTM32F103R.menu.opt.oslto.build.flags.optimize=-Os -flto
+genericSTM32F103R.menu.opt.oslto.build.flags.ldspecs=-flto
+genericSTM32F103R.menu.opt.o1std=Fast (-O1)
 genericSTM32F103R.menu.opt.o1std.build.flags.optimize=-O1
 genericSTM32F103R.menu.opt.o1std.build.flags.ldspecs=
-genericSTM32F103R.menu.opt.o1lto=Fast with LTO
+genericSTM32F103R.menu.opt.o1lto=Fast (-O1) with LTO
 genericSTM32F103R.menu.opt.o1lto.build.flags.optimize=-O1 -flto
 genericSTM32F103R.menu.opt.o1lto.build.flags.ldspecs=-flto
-genericSTM32F103R.menu.opt.o3std=Fastest
+genericSTM32F103R.menu.opt.o2std=Faster (-O2)
+genericSTM32F103R.menu.opt.o2std.build.flags.optimize=-O2
+genericSTM32F103R.menu.opt.o2std.build.flags.ldspecs=
+genericSTM32F103R.menu.opt.o2lto=Faster (-O2) with LTO
+genericSTM32F103R.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+genericSTM32F103R.menu.opt.o2lto.build.flags.ldspecs=-flto
+genericSTM32F103R.menu.opt.o3std=Fastest (-03)
 genericSTM32F103R.menu.opt.o3std.build.flags.optimize=-O3
 genericSTM32F103R.menu.opt.o3std.build.flags.ldspecs=
-genericSTM32F103R.menu.opt.o3lto=Fastest with LTO
+genericSTM32F103R.menu.opt.o3lto=Fastest (-0) with LTO
 genericSTM32F103R.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+genericSTM32F103R.menu.opt.ogstd=Debug (-g)
 genericSTM32F103R.menu.opt.o3lto.build.flags.ldspecs=-flto
-genericSTM32F103R.menu.opt.ogstd=Debug
 genericSTM32F103R.menu.opt.ogstd.build.flags.optimize=-Og
 genericSTM32F103R.menu.opt.ogstd.build.flags.ldspecs=
 genericSTM32F103R.menu.opt.oglto=Debug with LTO
 genericSTM32F103R.menu.opt.oglto.build.flags.optimize=-Og -flto
 genericSTM32F103R.menu.opt.oglto.build.flags.ldspecs=-flto
-genericSTM32F103R.menu.opt.osstd=Smallest Code
-genericSTM32F103R.menu.opt.osstd.build.flags.optimize=-Os
-genericSTM32F103R.menu.opt.osstd.build.flags.ldspecs=
-genericSTM32F103R.menu.opt.oslto=Smallest Code with LTO
-genericSTM32F103R.menu.opt.oslto.build.flags.optimize=-Os -flto
-genericSTM32F103R.menu.opt.oslto.build.flags.ldspecs=-flto
 
 ###################### Generic STM32F103T ########################################
 
@@ -571,36 +571,36 @@ genericSTM32F103T.menu.upload_method.BMPMethod.upload.tool=bmp_upload
 genericSTM32F103T.menu.upload_method.BMPMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG
 
 #-- Optimizations
-genericSTM32F103T.menu.opt.o2std=Faster
-genericSTM32F103T.menu.opt.o2std.build.flags.optimize=-O2
-genericSTM32F103T.menu.opt.o2std.build.flags.ldspecs=
-genericSTM32F103T.menu.opt.o2lto=Faster with LTO
-genericSTM32F103T.menu.opt.o2lto.build.flags.optimize=-O2 -flto
-genericSTM32F103T.menu.opt.o2lto.build.flags.ldspecs=-flto
-genericSTM32F103T.menu.opt.o1std=Fast
+genericSTM32F103T.menu.opt.osstd=Smallest (default)
+genericSTM32F103T.menu.opt.osstd.build.flags.optimize=-Os
+genericSTM32F103T.menu.opt.osstd.build.flags.ldspecs=
+genericSTM32F103T.menu.opt.oslto=Smallest Code with LTO
+genericSTM32F103T.menu.opt.oslto.build.flags.optimize=-Os -flto
+genericSTM32F103T.menu.opt.oslto.build.flags.ldspecs=-flto
+genericSTM32F103T.menu.opt.o1std=Fast (-O1)
 genericSTM32F103T.menu.opt.o1std.build.flags.optimize=-O1
 genericSTM32F103T.menu.opt.o1std.build.flags.ldspecs=
-genericSTM32F103T.menu.opt.o1lto=Fast with LTO
+genericSTM32F103T.menu.opt.o1lto=Fast (-O1) with LTO
 genericSTM32F103T.menu.opt.o1lto.build.flags.optimize=-O1 -flto
 genericSTM32F103T.menu.opt.o1lto.build.flags.ldspecs=-flto
-genericSTM32F103T.menu.opt.o3std=Fastest
+genericSTM32F103T.menu.opt.o2std=Faster (-O2)
+genericSTM32F103T.menu.opt.o2std.build.flags.optimize=-O2
+genericSTM32F103T.menu.opt.o2std.build.flags.ldspecs=
+genericSTM32F103T.menu.opt.o2lto=Faster (-O2) with LTO
+genericSTM32F103T.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+genericSTM32F103T.menu.opt.o2lto.build.flags.ldspecs=-flto
+genericSTM32F103T.menu.opt.o3std=Fastest (-03)
 genericSTM32F103T.menu.opt.o3std.build.flags.optimize=-O3
 genericSTM32F103T.menu.opt.o3std.build.flags.ldspecs=
-genericSTM32F103T.menu.opt.o3lto=Fastest with LTO
+genericSTM32F103T.menu.opt.o3lto=Fastest (-0) with LTO
 genericSTM32F103T.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+genericSTM32F103T.menu.opt.ogstd=Debug (-g)
 genericSTM32F103T.menu.opt.o3lto.build.flags.ldspecs=-flto
-genericSTM32F103T.menu.opt.ogstd=Debug
 genericSTM32F103T.menu.opt.ogstd.build.flags.optimize=-Og
 genericSTM32F103T.menu.opt.ogstd.build.flags.ldspecs=
 genericSTM32F103T.menu.opt.oglto=Debug with LTO
 genericSTM32F103T.menu.opt.oglto.build.flags.optimize=-Og -flto
 genericSTM32F103T.menu.opt.oglto.build.flags.ldspecs=-flto
-genericSTM32F103T.menu.opt.osstd=Smallest Code
-genericSTM32F103T.menu.opt.osstd.build.flags.optimize=-Os
-genericSTM32F103T.menu.opt.osstd.build.flags.ldspecs=
-genericSTM32F103T.menu.opt.oslto=Smallest Code with LTO
-genericSTM32F103T.menu.opt.oslto.build.flags.optimize=-Os -flto
-genericSTM32F103T.menu.opt.oslto.build.flags.ldspecs=-flto
 
 ########################### Generic STM32F103V ###########################
 
@@ -663,36 +663,36 @@ genericSTM32F103V.menu.upload_method.BMPMethod.upload.tool=bmp_upload
 genericSTM32F103V.menu.upload_method.BMPMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG
 
 #-- Optimizations
-genericSTM32F103V.menu.opt.o2std=Faster
-genericSTM32F103V.menu.opt.o2std.build.flags.optimize=-O2
-genericSTM32F103V.menu.opt.o2std.build.flags.ldspecs=
-genericSTM32F103V.menu.opt.o2lto=Faster with LTO
-genericSTM32F103V.menu.opt.o2lto.build.flags.optimize=-O2 -flto
-genericSTM32F103V.menu.opt.o2lto.build.flags.ldspecs=-flto
-genericSTM32F103V.menu.opt.o1std=Fast
+genericSTM32F103V.menu.opt.osstd=Smallest (default)
+genericSTM32F103V.menu.opt.osstd.build.flags.optimize=-Os
+genericSTM32F103V.menu.opt.osstd.build.flags.ldspecs=
+genericSTM32F103V.menu.opt.oslto=Smallest Code with LTO
+genericSTM32F103V.menu.opt.oslto.build.flags.optimize=-Os -flto
+genericSTM32F103V.menu.opt.oslto.build.flags.ldspecs=-flto
+genericSTM32F103V.menu.opt.o1std=Fast (-O1)
 genericSTM32F103V.menu.opt.o1std.build.flags.optimize=-O1
 genericSTM32F103V.menu.opt.o1std.build.flags.ldspecs=
-genericSTM32F103V.menu.opt.o1lto=Fast with LTO
+genericSTM32F103V.menu.opt.o1lto=Fast (-O1) with LTO
 genericSTM32F103V.menu.opt.o1lto.build.flags.optimize=-O1 -flto
 genericSTM32F103V.menu.opt.o1lto.build.flags.ldspecs=-flto
-genericSTM32F103V.menu.opt.o3std=Fastest
+genericSTM32F103V.menu.opt.o2std=Faster (-O2)
+genericSTM32F103V.menu.opt.o2std.build.flags.optimize=-O2
+genericSTM32F103V.menu.opt.o2std.build.flags.ldspecs=
+genericSTM32F103V.menu.opt.o2lto=Faster (-O2) with LTO
+genericSTM32F103V.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+genericSTM32F103V.menu.opt.o2lto.build.flags.ldspecs=-flto
+genericSTM32F103V.menu.opt.o3std=Fastest (-03)
 genericSTM32F103V.menu.opt.o3std.build.flags.optimize=-O3
 genericSTM32F103V.menu.opt.o3std.build.flags.ldspecs=
-genericSTM32F103V.menu.opt.o3lto=Fastest with LTO
+genericSTM32F103V.menu.opt.o3lto=Fastest (-0) with LTO
 genericSTM32F103V.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+genericSTM32F103V.menu.opt.ogstd=Debug (-g)
 genericSTM32F103V.menu.opt.o3lto.build.flags.ldspecs=-flto
-genericSTM32F103V.menu.opt.ogstd=Debug
 genericSTM32F103V.menu.opt.ogstd.build.flags.optimize=-Og
 genericSTM32F103V.menu.opt.ogstd.build.flags.ldspecs=
 genericSTM32F103V.menu.opt.oglto=Debug with LTO
 genericSTM32F103V.menu.opt.oglto.build.flags.optimize=-Og -flto
 genericSTM32F103V.menu.opt.oglto.build.flags.ldspecs=-flto
-genericSTM32F103V.menu.opt.osstd=Smallest Code
-genericSTM32F103V.menu.opt.osstd.build.flags.optimize=-Os
-genericSTM32F103V.menu.opt.osstd.build.flags.ldspecs=
-genericSTM32F103V.menu.opt.oslto=Smallest Code with LTO
-genericSTM32F103V.menu.opt.oslto.build.flags.optimize=-Os -flto
-genericSTM32F103V.menu.opt.oslto.build.flags.ldspecs=-flto
 
 ########################### Generic STM32F103Z ###########################
 
@@ -752,36 +752,36 @@ genericSTM32F103Z.menu.upload_method.BMPMethod.upload.tool=bmp_upload
 genericSTM32F103Z.menu.upload_method.BMPMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG
 
 #-- Optimizations
-genericSTM32F103Z.menu.opt.o2std=Faster
-genericSTM32F103Z.menu.opt.o2std.build.flags.optimize=-O2
-genericSTM32F103Z.menu.opt.o2std.build.flags.ldspecs=
-genericSTM32F103Z.menu.opt.o2lto=Faster with LTO
-genericSTM32F103Z.menu.opt.o2lto.build.flags.optimize=-O2 -flto
-genericSTM32F103Z.menu.opt.o2lto.build.flags.ldspecs=-flto
-genericSTM32F103Z.menu.opt.o1std=Fast
+genericSTM32F103Z.menu.opt.osstd=Smallest (default)
+genericSTM32F103Z.menu.opt.osstd.build.flags.optimize=-Os
+genericSTM32F103Z.menu.opt.osstd.build.flags.ldspecs=
+genericSTM32F103Z.menu.opt.oslto=Smallest Code with LTO
+genericSTM32F103Z.menu.opt.oslto.build.flags.optimize=-Os -flto
+genericSTM32F103Z.menu.opt.oslto.build.flags.ldspecs=-flto
+genericSTM32F103Z.menu.opt.o1std=Fast (-O1)
 genericSTM32F103Z.menu.opt.o1std.build.flags.optimize=-O1
 genericSTM32F103Z.menu.opt.o1std.build.flags.ldspecs=
-genericSTM32F103Z.menu.opt.o1lto=Fast with LTO
+genericSTM32F103Z.menu.opt.o1lto=Fast (-O1) with LTO
 genericSTM32F103Z.menu.opt.o1lto.build.flags.optimize=-O1 -flto
 genericSTM32F103Z.menu.opt.o1lto.build.flags.ldspecs=-flto
-genericSTM32F103Z.menu.opt.o3std=Fastest
+genericSTM32F103Z.menu.opt.o2std=Faster (-O2)
+genericSTM32F103Z.menu.opt.o2std.build.flags.optimize=-O2
+genericSTM32F103Z.menu.opt.o2std.build.flags.ldspecs=
+genericSTM32F103Z.menu.opt.o2lto=Faster (-O2) with LTO
+genericSTM32F103Z.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+genericSTM32F103Z.menu.opt.o2lto.build.flags.ldspecs=-flto
+genericSTM32F103Z.menu.opt.o3std=Fastest (-03)
 genericSTM32F103Z.menu.opt.o3std.build.flags.optimize=-O3
 genericSTM32F103Z.menu.opt.o3std.build.flags.ldspecs=
-genericSTM32F103Z.menu.opt.o3lto=Fastest with LTO
+genericSTM32F103Z.menu.opt.o3lto=Fastest (-0) with LTO
 genericSTM32F103Z.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+genericSTM32F103Z.menu.opt.ogstd=Debug (-g)
 genericSTM32F103Z.menu.opt.o3lto.build.flags.ldspecs=-flto
-genericSTM32F103Z.menu.opt.ogstd=Debug
 genericSTM32F103Z.menu.opt.ogstd.build.flags.optimize=-Og
 genericSTM32F103Z.menu.opt.ogstd.build.flags.ldspecs=
 genericSTM32F103Z.menu.opt.oglto=Debug with LTO
 genericSTM32F103Z.menu.opt.oglto.build.flags.optimize=-Og -flto
 genericSTM32F103Z.menu.opt.oglto.build.flags.ldspecs=-flto
-genericSTM32F103Z.menu.opt.osstd=Smallest Code
-genericSTM32F103Z.menu.opt.osstd.build.flags.optimize=-Os
-genericSTM32F103Z.menu.opt.osstd.build.flags.ldspecs=
-genericSTM32F103Z.menu.opt.oslto=Smallest Code with LTO
-genericSTM32F103Z.menu.opt.oslto.build.flags.optimize=-Os -flto
-genericSTM32F103Z.menu.opt.oslto.build.flags.ldspecs=-flto
 
 ###################### HYTiny STM32F103T ########################################
 
@@ -835,36 +835,36 @@ hytiny-stm32f103t.menu.upload_method.jlinkMethod.upload.tool=jlink_upload
 hytiny-stm32f103t.menu.upload_method.jlinkMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG=1 -DSERIAL_USB -DGENERIC_BOOTLOADER 
 
 #-- Optimizations
-hytiny-stm32f103t.menu.opt.o2std=Faster
-hytiny-stm32f103t.menu.opt.o2std.build.flags.optimize=-O2
-hytiny-stm32f103t.menu.opt.o2std.build.flags.ldspecs=
-hytiny-stm32f103t.menu.opt.o2lto=Faster with LTO
-hytiny-stm32f103t.menu.opt.o2lto.build.flags.optimize=-O2 -flto
-hytiny-stm32f103t.menu.opt.o2lto.build.flags.ldspecs=-flto
-hytiny-stm32f103t.menu.opt.o1std=Fast
+hytiny-stm32f103t.menu.opt.osstd=Smallest (default)
+hytiny-stm32f103t.menu.opt.osstd.build.flags.optimize=-Os
+hytiny-stm32f103t.menu.opt.osstd.build.flags.ldspecs=
+hytiny-stm32f103t.menu.opt.oslto=Smallest Code with LTO
+hytiny-stm32f103t.menu.opt.oslto.build.flags.optimize=-Os -flto
+hytiny-stm32f103t.menu.opt.oslto.build.flags.ldspecs=-flto
+hytiny-stm32f103t.menu.opt.o1std=Fast (-O1)
 hytiny-stm32f103t.menu.opt.o1std.build.flags.optimize=-O1
 hytiny-stm32f103t.menu.opt.o1std.build.flags.ldspecs=
-hytiny-stm32f103t.menu.opt.o1lto=Fast with LTO
+hytiny-stm32f103t.menu.opt.o1lto=Fast (-O1) with LTO
 hytiny-stm32f103t.menu.opt.o1lto.build.flags.optimize=-O1 -flto
 hytiny-stm32f103t.menu.opt.o1lto.build.flags.ldspecs=-flto
-hytiny-stm32f103t.menu.opt.o3std=Fastest
+hytiny-stm32f103t.menu.opt.o2std=Faster (-O2)
+hytiny-stm32f103t.menu.opt.o2std.build.flags.optimize=-O2
+hytiny-stm32f103t.menu.opt.o2std.build.flags.ldspecs=
+hytiny-stm32f103t.menu.opt.o2lto=Faster (-O2) with LTO
+hytiny-stm32f103t.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+hytiny-stm32f103t.menu.opt.o2lto.build.flags.ldspecs=-flto
+hytiny-stm32f103t.menu.opt.o3std=Fastest (-03)
 hytiny-stm32f103t.menu.opt.o3std.build.flags.optimize=-O3
 hytiny-stm32f103t.menu.opt.o3std.build.flags.ldspecs=
-hytiny-stm32f103t.menu.opt.o3lto=Fastest with LTO
+hytiny-stm32f103t.menu.opt.o3lto=Fastest (-0) with LTO
 hytiny-stm32f103t.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+hytiny-stm32f103t.menu.opt.ogstd=Debug (-g)
 hytiny-stm32f103t.menu.opt.o3lto.build.flags.ldspecs=-flto
-hytiny-stm32f103t.menu.opt.ogstd=Debug
 hytiny-stm32f103t.menu.opt.ogstd.build.flags.optimize=-Og
 hytiny-stm32f103t.menu.opt.ogstd.build.flags.ldspecs=
 hytiny-stm32f103t.menu.opt.oglto=Debug with LTO
 hytiny-stm32f103t.menu.opt.oglto.build.flags.optimize=-Og -flto
 hytiny-stm32f103t.menu.opt.oglto.build.flags.ldspecs=-flto
-hytiny-stm32f103t.menu.opt.osstd=Smallest Code
-hytiny-stm32f103t.menu.opt.osstd.build.flags.optimize=-Os
-hytiny-stm32f103t.menu.opt.osstd.build.flags.ldspecs=
-hytiny-stm32f103t.menu.opt.oslto=Smallest Code with LTO
-hytiny-stm32f103t.menu.opt.oslto.build.flags.optimize=-Os -flto
-hytiny-stm32f103t.menu.opt.oslto.build.flags.ldspecs=-flto
 
 ###################### Generic GD32F103C  ########################################
 
@@ -929,36 +929,36 @@ genericGD32F103C.menu.cpu_speed.speed_72mhz=72Mhz (compatibility)
 genericGD32F103C.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
 
 #-- Optimizations
-genericGD32F103C.menu.opt.o2std=Faster
-genericGD32F103C.menu.opt.o2std.build.flags.optimize=-O2
-genericGD32F103C.menu.opt.o2std.build.flags.ldspecs=
-genericGD32F103C.menu.opt.o2lto=Faster with LTO
-genericGD32F103C.menu.opt.o2lto.build.flags.optimize=-O2 -flto
-genericGD32F103C.menu.opt.o2lto.build.flags.ldspecs=-flto
-genericGD32F103C.menu.opt.o1std=Fast
+genericGD32F103C.menu.opt.osstd=Smallest (default)
+genericGD32F103C.menu.opt.osstd.build.flags.optimize=-Os
+genericGD32F103C.menu.opt.osstd.build.flags.ldspecs=
+genericGD32F103C.menu.opt.oslto=Smallest Code with LTO
+genericGD32F103C.menu.opt.oslto.build.flags.optimize=-Os -flto
+genericGD32F103C.menu.opt.oslto.build.flags.ldspecs=-flto
+genericGD32F103C.menu.opt.o1std=Fast (-O1)
 genericGD32F103C.menu.opt.o1std.build.flags.optimize=-O1
 genericGD32F103C.menu.opt.o1std.build.flags.ldspecs=
-genericGD32F103C.menu.opt.o1lto=Fast with LTO
+genericGD32F103C.menu.opt.o1lto=Fast (-O1) with LTO
 genericGD32F103C.menu.opt.o1lto.build.flags.optimize=-O1 -flto
 genericGD32F103C.menu.opt.o1lto.build.flags.ldspecs=-flto
-genericGD32F103C.menu.opt.o3std=Fastest
+genericGD32F103C.menu.opt.o2std=Faster (-O2)
+genericGD32F103C.menu.opt.o2std.build.flags.optimize=-O2
+genericGD32F103C.menu.opt.o2std.build.flags.ldspecs=
+genericGD32F103C.menu.opt.o2lto=Faster (-O2) with LTO
+genericGD32F103C.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+genericGD32F103C.menu.opt.o2lto.build.flags.ldspecs=-flto
+genericGD32F103C.menu.opt.o3std=Fastest (-03)
 genericGD32F103C.menu.opt.o3std.build.flags.optimize=-O3
 genericGD32F103C.menu.opt.o3std.build.flags.ldspecs=
-genericGD32F103C.menu.opt.o3lto=Fastest with LTO
+genericGD32F103C.menu.opt.o3lto=Fastest (-0) with LTO
 genericGD32F103C.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+genericGD32F103C.menu.opt.ogstd=Debug (-g)
 genericGD32F103C.menu.opt.o3lto.build.flags.ldspecs=-flto
-genericGD32F103C.menu.opt.ogstd=Debug
 genericGD32F103C.menu.opt.ogstd.build.flags.optimize=-Og
 genericGD32F103C.menu.opt.ogstd.build.flags.ldspecs=
 genericGD32F103C.menu.opt.oglto=Debug with LTO
 genericGD32F103C.menu.opt.oglto.build.flags.optimize=-Og -flto
 genericGD32F103C.menu.opt.oglto.build.flags.ldspecs=-flto
-genericGD32F103C.menu.opt.osstd=Smallest Code
-genericGD32F103C.menu.opt.osstd.build.flags.optimize=-Os
-genericGD32F103C.menu.opt.osstd.build.flags.ldspecs=
-genericGD32F103C.menu.opt.oslto=Smallest Code with LTO
-genericGD32F103C.menu.opt.oslto.build.flags.optimize=-Os -flto
-genericGD32F103C.menu.opt.oslto.build.flags.ldspecs=-flto
 
 ########################### STM32VLD to FLASH ###########################
 
@@ -989,35 +989,35 @@ STM32VLD.menu.upload_method.STLinkMethod.upload.tool=stlink_upload
 STM32VLD.menu.upload_method.STLinkMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG  
 
 #-- Optimizations
-STM32VLD.menu.opt.o2std=Faster
-STM32VLD.menu.opt.o2std.build.flags.optimize=-O2
-STM32VLD.menu.opt.o2std.build.flags.ldspecs=
-STM32VLD.menu.opt.o2lto=Faster with LTO
-STM32VLD.menu.opt.o2lto.build.flags.optimize=-O2 -flto
-STM32VLD.menu.opt.o2lto.build.flags.ldspecs=-flto
-STM32VLD.menu.opt.o1std=Fast
+STM32VLD.menu.opt.osstd=Smallest (default)
+STM32VLD.menu.opt.osstd.build.flags.optimize=-Os
+STM32VLD.menu.opt.osstd.build.flags.ldspecs=
+STM32VLD.menu.opt.oslto=Smallest Code with LTO
+STM32VLD.menu.opt.oslto.build.flags.optimize=-Os -flto
+STM32VLD.menu.opt.oslto.build.flags.ldspecs=-flto
+STM32VLD.menu.opt.o1std=Fast (-O1)
 STM32VLD.menu.opt.o1std.build.flags.optimize=-O1
 STM32VLD.menu.opt.o1std.build.flags.ldspecs=
-STM32VLD.menu.opt.o1lto=Fast with LTO
+STM32VLD.menu.opt.o1lto=Fast (-O1) with LTO
 STM32VLD.menu.opt.o1lto.build.flags.optimize=-O1 -flto
 STM32VLD.menu.opt.o1lto.build.flags.ldspecs=-flto
-STM32VLD.menu.opt.o3std=Fastest
+STM32VLD.menu.opt.o2std=Faster (-O2)
+STM32VLD.menu.opt.o2std.build.flags.optimize=-O2
+STM32VLD.menu.opt.o2std.build.flags.ldspecs=
+STM32VLD.menu.opt.o2lto=Faster (-O2) with LTO
+STM32VLD.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+STM32VLD.menu.opt.o2lto.build.flags.ldspecs=-flto
+STM32VLD.menu.opt.o3std=Fastest (-03)
 STM32VLD.menu.opt.o3std.build.flags.optimize=-O3
 STM32VLD.menu.opt.o3std.build.flags.ldspecs=
-STM32VLD.menu.opt.o3lto=Fastest with LTO
+STM32VLD.menu.opt.o3lto=Fastest (-0) with LTO
 STM32VLD.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+STM32VLD.menu.opt.ogstd=Debug (-g)
 STM32VLD.menu.opt.o3lto.build.flags.ldspecs=-flto
-STM32VLD.menu.opt.ogstd=Debug
 STM32VLD.menu.opt.ogstd.build.flags.optimize=-Og
 STM32VLD.menu.opt.ogstd.build.flags.ldspecs=
 STM32VLD.menu.opt.oglto=Debug with LTO
 STM32VLD.menu.opt.oglto.build.flags.optimize=-Og -flto
 STM32VLD.menu.opt.oglto.build.flags.ldspecs=-flto
-STM32VLD.menu.opt.osstd=Smallest Code
-STM32VLD.menu.opt.osstd.build.flags.optimize=-Os
-STM32VLD.menu.opt.osstd.build.flags.ldspecs=
-STM32VLD.menu.opt.oslto=Smallest Code with LTO
-STM32VLD.menu.opt.oslto.build.flags.optimize=-Os -flto
-STM32VLD.menu.opt.oslto.build.flags.ldspecs=-flto
 
 ################################################################################
\ No newline at end of file
diff --git a/STM32F3/boards.txt b/STM32F3/boards.txt
index d3a37353e..6c011bce3 100644
--- a/STM32F3/boards.txt
+++ b/STM32F3/boards.txt
@@ -1,7 +1,5 @@
 # 
 
-menu.opt=Optimize
-
 ##############################################################
 discovery_f3.name=STM32F3Discovery
 
@@ -30,37 +28,5 @@ discovery_f3.build.error_led_port=GPIOE
 discovery_f3.build.error_led_pin=8
 discovery_f3.build.board=STM32F3Discovery
 
-#-- Optimizations
-discovery_f3.menu.opt.o2std=Faster
-discovery_f3.menu.opt.o2std.build.flags.optimize=-O2
-discovery_f3.menu.opt.o2std.build.flags.ldspecs=
-discovery_f3.menu.opt.o2lto=Faster with LTO
-discovery_f3.menu.opt.o2lto.build.flags.optimize=-O2 -flto
-discovery_f3.menu.opt.o2lto.build.flags.ldspecs=-flto
-discovery_f3.menu.opt.o1std=Fast
-discovery_f3.menu.opt.o1std.build.flags.optimize=-O1
-discovery_f3.menu.opt.o1std.build.flags.ldspecs=
-discovery_f3.menu.opt.o1lto=Fast with LTO
-discovery_f3.menu.opt.o1lto.build.flags.optimize=-O1 -flto
-discovery_f3.menu.opt.o1lto.build.flags.ldspecs=-flto
-discovery_f3.menu.opt.o3std=Fastest
-discovery_f3.menu.opt.o3std.build.flags.optimize=-O3
-discovery_f3.menu.opt.o3std.build.flags.ldspecs=
-discovery_f3.menu.opt.o3lto=Fastest with LTO
-discovery_f3.menu.opt.o3lto.build.flags.optimize=-O3 -flto
-discovery_f3.menu.opt.o3lto.build.flags.ldspecs=-flto
-discovery_f3.menu.opt.ogstd=Debug
-discovery_f3.menu.opt.ogstd.build.flags.optimize=-Og
-discovery_f3.menu.opt.ogstd.build.flags.ldspecs=
-discovery_f3.menu.opt.oglto=Debug with LTO
-discovery_f3.menu.opt.oglto.build.flags.optimize=-Og -flto
-discovery_f3.menu.opt.oglto.build.flags.ldspecs=-flto
-discovery_f3.menu.opt.osstd=Smallest Code
-discovery_f3.menu.opt.osstd.build.flags.optimize=-Os
-discovery_f3.menu.opt.osstd.build.flags.ldspecs=
-discovery_f3.menu.opt.oslto=Smallest Code with LTO
-discovery_f3.menu.opt.oslto.build.flags.optimize=-Os -flto
-discovery_f3.menu.opt.oslto.build.flags.ldspecs=-flto
-
 ##############################################################
 
diff --git a/STM32F4/boards.txt b/STM32F4/boards.txt
index 429ba4b96..baf6f6e03 100644
--- a/STM32F4/boards.txt
+++ b/STM32F4/boards.txt
@@ -1,7 +1,6 @@
 # 
 
 menu.usb_cfg=USB configuration
-menu.opt=Optimize
 
 ##############################################################
 discovery_f407.name=STM32 Discovery F407
@@ -37,39 +36,6 @@ discovery_f407.menu.usb_cfg.usb_serial=USB serial (CDC)
 discovery_f407.menu.usb_cfg.usb_serial.build.cpu_flags=-DSERIAL_USB
 discovery_f407.menu.usb_cfg.usb_msc=USB Mass Storage (MSC)
 discovery_f407.menu.usb_cfg.usb_msc.build.cpu_flags=-DUSB_MSC
-
-#-- Optimizations
-discovery_f407.menu.opt.o2std=Faster
-discovery_f407.menu.opt.o2std.build.flags.optimize=-O2
-discovery_f407.menu.opt.o2std.build.flags.ldspecs=
-discovery_f407.menu.opt.o2lto=Faster with LTO
-discovery_f407.menu.opt.o2lto.build.flags.optimize=-O2 -flto
-discovery_f407.menu.opt.o2lto.build.flags.ldspecs=-flto
-discovery_f407.menu.opt.o1std=Fast
-discovery_f407.menu.opt.o1std.build.flags.optimize=-O1
-discovery_f407.menu.opt.o1std.build.flags.ldspecs=
-discovery_f407.menu.opt.o1lto=Fast with LTO
-discovery_f407.menu.opt.o1lto.build.flags.optimize=-O1 -flto
-discovery_f407.menu.opt.o1lto.build.flags.ldspecs=-flto
-discovery_f407.menu.opt.o3std=Fastest
-discovery_f407.menu.opt.o3std.build.flags.optimize=-O3
-discovery_f407.menu.opt.o3std.build.flags.ldspecs=
-discovery_f407.menu.opt.o3lto=Fastest with LTO
-discovery_f407.menu.opt.o3lto.build.flags.optimize=-O3 -flto
-discovery_f407.menu.opt.o3lto.build.flags.ldspecs=-flto
-discovery_f407.menu.opt.ogstd=Debug
-discovery_f407.menu.opt.ogstd.build.flags.optimize=-Og
-discovery_f407.menu.opt.ogstd.build.flags.ldspecs=
-discovery_f407.menu.opt.oglto=Debug with LTO
-discovery_f407.menu.opt.oglto.build.flags.optimize=-Og -flto
-discovery_f407.menu.opt.oglto.build.flags.ldspecs=-flto
-discovery_f407.menu.opt.osstd=Smallest Code
-discovery_f407.menu.opt.osstd.build.flags.optimize=-Os
-discovery_f407.menu.opt.osstd.build.flags.ldspecs=
-discovery_f407.menu.opt.oslto=Smallest Code with LTO
-discovery_f407.menu.opt.oslto.build.flags.optimize=-Os -flto
-discovery_f407.menu.opt.oslto.build.flags.ldspecs=-flto
-
 ##############################################################
 generic_f407v.name=Generic STM32F407V series
 
@@ -106,38 +72,6 @@ generic_f407v.menu.usb_cfg.usb_serial.build.cpu_flags=-DSERIAL_USB
 generic_f407v.menu.usb_cfg.usb_msc=USB Mass Storage (MSC)
 generic_f407v.menu.usb_cfg.usb_msc.build.cpu_flags=-DUSB_MSC
 
-#-- Optimizations
-generic_f407v.menu.opt.o2std=Faster
-generic_f407v.menu.opt.o2std.build.flags.optimize=-O2
-generic_f407v.menu.opt.o2std.build.flags.ldspecs=
-generic_f407v.menu.opt.o2lto=Faster with LTO
-generic_f407v.menu.opt.o2lto.build.flags.optimize=-O2 -flto
-generic_f407v.menu.opt.o2lto.build.flags.ldspecs=-flto
-generic_f407v.menu.opt.o1std=Fast
-generic_f407v.menu.opt.o1std.build.flags.optimize=-O1
-generic_f407v.menu.opt.o1std.build.flags.ldspecs=
-generic_f407v.menu.opt.o1lto=Fast with LTO
-generic_f407v.menu.opt.o1lto.build.flags.optimize=-O1 -flto
-generic_f407v.menu.opt.o1lto.build.flags.ldspecs=-flto
-generic_f407v.menu.opt.o3std=Fastest
-generic_f407v.menu.opt.o3std.build.flags.optimize=-O3
-generic_f407v.menu.opt.o3std.build.flags.ldspecs=
-generic_f407v.menu.opt.o3lto=Fastest with LTO
-generic_f407v.menu.opt.o3lto.build.flags.optimize=-O3 -flto
-generic_f407v.menu.opt.o3lto.build.flags.ldspecs=-flto
-generic_f407v.menu.opt.ogstd=Debug
-generic_f407v.menu.opt.ogstd.build.flags.optimize=-Og
-generic_f407v.menu.opt.ogstd.build.flags.ldspecs=
-generic_f407v.menu.opt.oglto=Debug with LTO
-generic_f407v.menu.opt.oglto.build.flags.optimize=-Og -flto
-generic_f407v.menu.opt.oglto.build.flags.ldspecs=-flto
-generic_f407v.menu.opt.osstd=Smallest Code
-generic_f407v.menu.opt.osstd.build.flags.optimize=-Os
-generic_f407v.menu.opt.osstd.build.flags.ldspecs=
-generic_f407v.menu.opt.oslto=Smallest Code with LTO
-generic_f407v.menu.opt.oslto.build.flags.optimize=-Os -flto
-generic_f407v.menu.opt.oslto.build.flags.ldspecs=-flto
-
 ##############################################################
 stm32f4stamp.name=STM32F4Stamp F405
 
@@ -173,39 +107,6 @@ stm32f4stamp.menu.usb_cfg.usb_serial=USB serial (CDC)
 stm32f4stamp.menu.usb_cfg.usb_serial.build.cpu_flags=-DSERIAL_USB
 stm32f4stamp.menu.usb_cfg.usb_msc=USB Mass Storage (MSC)
 stm32f4stamp.menu.usb_cfg.usb_msc.build.cpu_flags=-DUSB_MSC
-
-#-- Optimizations
-stm32f4stamp.menu.opt.o2std=Faster
-stm32f4stamp.menu.opt.o2std.build.flags.optimize=-O2
-stm32f4stamp.menu.opt.o2std.build.flags.ldspecs=
-stm32f4stamp.menu.opt.o2lto=Faster with LTO
-stm32f4stamp.menu.opt.o2lto.build.flags.optimize=-O2 -flto
-stm32f4stamp.menu.opt.o2lto.build.flags.ldspecs=-flto
-stm32f4stamp.menu.opt.o1std=Fast
-stm32f4stamp.menu.opt.o1std.build.flags.optimize=-O1
-stm32f4stamp.menu.opt.o1std.build.flags.ldspecs=
-stm32f4stamp.menu.opt.o1lto=Fast with LTO
-stm32f4stamp.menu.opt.o1lto.build.flags.optimize=-O1 -flto
-stm32f4stamp.menu.opt.o1lto.build.flags.ldspecs=-flto
-stm32f4stamp.menu.opt.o3std=Fastest
-stm32f4stamp.menu.opt.o3std.build.flags.optimize=-O3
-stm32f4stamp.menu.opt.o3std.build.flags.ldspecs=
-stm32f4stamp.menu.opt.o3lto=Fastest with LTO
-stm32f4stamp.menu.opt.o3lto.build.flags.optimize=-O3 -flto
-stm32f4stamp.menu.opt.o3lto.build.flags.ldspecs=-flto
-stm32f4stamp.menu.opt.ogstd=Debug
-stm32f4stamp.menu.opt.ogstd.build.flags.optimize=-Og
-stm32f4stamp.menu.opt.ogstd.build.flags.ldspecs=
-stm32f4stamp.menu.opt.oglto=Debug with LTO
-stm32f4stamp.menu.opt.oglto.build.flags.optimize=-Og -flto
-stm32f4stamp.menu.opt.oglto.build.flags.ldspecs=-flto
-stm32f4stamp.menu.opt.osstd=Smallest Code
-stm32f4stamp.menu.opt.osstd.build.flags.optimize=-Os
-stm32f4stamp.menu.opt.osstd.build.flags.ldspecs=
-stm32f4stamp.menu.opt.oslto=Smallest Code with LTO
-stm32f4stamp.menu.opt.oslto.build.flags.optimize=-Os -flto
-stm32f4stamp.menu.opt.oslto.build.flags.ldspecs=-flto
-
 ##############################################################
 netduino2plus.name=Netduino2 F405
 
@@ -241,37 +142,5 @@ netduino2plus.menu.usb_cfg.usb_serial=USB serial (CDC)
 netduino2plus.menu.usb_cfg.usb_serial.build.cpu_flags=-DSERIAL_USB
 netduino2plus.menu.usb_cfg.usb_msc=USB Mass Storage (MSC)
 netduino2plus.menu.usb_cfg.usb_msc.build.cpu_flags=-DUSB_MSC
-
-#-- Optimizations
-netduino2plus.menu.opt.o2std=Faster
-netduino2plus.menu.opt.o2std.build.flags.optimize=-O2
-netduino2plus.menu.opt.o2std.build.flags.ldspecs=
-netduino2plus.menu.opt.o2lto=Faster with LTO
-netduino2plus.menu.opt.o2lto.build.flags.optimize=-O2 -flto
-netduino2plus.menu.opt.o2lto.build.flags.ldspecs=-flto
-netduino2plus.menu.opt.o1std=Fast
-netduino2plus.menu.opt.o1std.build.flags.optimize=-O1
-netduino2plus.menu.opt.o1std.build.flags.ldspecs=
-netduino2plus.menu.opt.o1lto=Fast with LTO
-netduino2plus.menu.opt.o1lto.build.flags.optimize=-O1 -flto
-netduino2plus.menu.opt.o1lto.build.flags.ldspecs=-flto
-netduino2plus.menu.opt.o3std=Fastest
-netduino2plus.menu.opt.o3std.build.flags.optimize=-O3
-netduino2plus.menu.opt.o3std.build.flags.ldspecs=
-netduino2plus.menu.opt.o3lto=Fastest with LTO
-netduino2plus.menu.opt.o3lto.build.flags.optimize=-O3 -flto
-netduino2plus.menu.opt.o3lto.build.flags.ldspecs=-flto
-netduino2plus.menu.opt.ogstd=Debug
-netduino2plus.menu.opt.ogstd.build.flags.optimize=-Og
-netduino2plus.menu.opt.ogstd.build.flags.ldspecs=
-netduino2plus.menu.opt.oglto=Debug with LTO
-netduino2plus.menu.opt.oglto.build.flags.optimize=-Og -flto
-netduino2plus.menu.opt.oglto.build.flags.ldspecs=-flto
-netduino2plus.menu.opt.osstd=Smallest Code
-netduino2plus.menu.opt.osstd.build.flags.optimize=-Os
-netduino2plus.menu.opt.osstd.build.flags.ldspecs=
-netduino2plus.menu.opt.oslto=Smallest Code with LTO
-netduino2plus.menu.opt.oslto.build.flags.optimize=-Os -flto
-netduino2plus.menu.opt.oslto.build.flags.ldspecs=-flto
-
 ##############################################################
+

From a683dfccca19bbe84322c7b56152961e0f59cb0c Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sun, 30 Jul 2017 16:16:24 +1000
Subject: [PATCH 153/307] revert changes to STM32F3/platform.txt and
 STM32F4/platform.txt as they should not have been changed in the previous
 commit

---
 STM32F3/platform.txt | 8 ++++----
 STM32F4/platform.txt | 8 ++++----
 2 files changed, 8 insertions(+), 8 deletions(-)

diff --git a/STM32F3/platform.txt b/STM32F3/platform.txt
index 94f787c81..3218f85c1 100644
--- a/STM32F3/platform.txt
+++ b/STM32F3/platform.txt
@@ -12,20 +12,20 @@ version=0.1.0
 
 compiler.path={runtime.tools.arm-none-eabi-gcc.path}/bin/
 compiler.c.cmd=arm-none-eabi-gcc
-compiler.c.flags=-c -g {build.flags.optimize} -w -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
+compiler.c.flags=-c -g -Os -w -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
 compiler.c.elf.cmd=arm-none-eabi-g++
-compiler.c.elf.flags={build.flags.optimize} -Wl,--gc-sections {build.flags.ldspecs}
+compiler.c.elf.flags=-Os -Wl,--gc-sections
 compiler.S.cmd=arm-none-eabi-gcc
 compiler.S.flags=-c -g -x assembler-with-cpp -MMD
 compiler.cpp.cmd=arm-none-eabi-g++
-compiler.cpp.flags=-c -g {build.flags.optimize} -w -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin} 
+compiler.cpp.flags=-c -g -Os -w -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin} 
 compiler.ar.cmd=arm-none-eabi-ar
 compiler.ar.flags=rcs
 compiler.objcopy.cmd=arm-none-eabi-objcopy
 compiler.objcopy.eep.flags=-O ihex -j .eeprom --set-section-flags=.eeprom=alloc,load --no-change-warnings --change-section-lma .eeprom=0
 compiler.elf2hex.flags=-O binary
 compiler.elf2hex.cmd=arm-none-eabi-objcopy
-compiler.ldflags={build.flags.ldspecs}
+compiler.ldflags=
 compiler.size.cmd=arm-none-eabi-size
 compiler.define=-DARDUINO=                            
 
diff --git a/STM32F4/platform.txt b/STM32F4/platform.txt
index 92dc1ea9a..b64fe3eee 100755
--- a/STM32F4/platform.txt
+++ b/STM32F4/platform.txt
@@ -10,20 +10,20 @@ version=0.1.0
 # ----------------------
 compiler.path={runtime.tools.arm-none-eabi-gcc.path}/bin/
 compiler.c.cmd=arm-none-eabi-gcc
-compiler.c.flags=-c -g {build.flags.optimize} -Wall -MMD -std=gnu11 -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
+compiler.c.flags=-c -g -Os -Wall -MMD -std=gnu11 -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
 compiler.c.elf.cmd=arm-none-eabi-g++
-compiler.c.elf.flags={build.flags.optimize} -Wl,--gc-sections {build.flags.ldspecs}
+compiler.c.elf.flags=-Os -Wl,--gc-sections
 compiler.S.cmd=arm-none-eabi-gcc
 compiler.S.flags=-c -g -x assembler-with-cpp -MMD
 compiler.cpp.cmd=arm-none-eabi-g++
-compiler.cpp.flags=-c -g {build.flags.optimize} -Wall -MMD -std=gnu++11 -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
+compiler.cpp.flags=-c -g -Os -Wall -MMD -std=gnu++11 -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
 compiler.ar.cmd=arm-none-eabi-ar
 compiler.ar.flags=rcs
 compiler.objcopy.cmd=arm-none-eabi-objcopy
 compiler.objcopy.eep.flags=-O ihex -j .eeprom --set-section-flags=.eeprom=alloc,load --no-change-warnings --change-section-lma .eeprom=0
 compiler.elf2hex.flags=-O binary
 compiler.elf2hex.cmd=arm-none-eabi-objcopy
-compiler.ldflags={build.flags.ldspecs}
+compiler.ldflags=
 compiler.size.cmd=arm-none-eabi-size
 compiler.define=-DARDUINO=                            
 

From 86d823a3b5f80121e3f5b51f653b7bf83de2a668 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sun, 30 Jul 2017 16:21:26 +1000
Subject: [PATCH 154/307] Fixed typo in optimisation menu

---
 STM32F1/boards.txt | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/STM32F1/boards.txt b/STM32F1/boards.txt
index fe18609e1..3ed5158c2 100644
--- a/STM32F1/boards.txt
+++ b/STM32F1/boards.txt
@@ -66,7 +66,7 @@ mapleMini.menu.opt.o2lto.build.flags.ldspecs=-flto
 mapleMini.menu.opt.o3std=Fastest (-03)
 mapleMini.menu.opt.o3std.build.flags.optimize=-O3
 mapleMini.menu.opt.o3std.build.flags.ldspecs=
-mapleMini.menu.opt.o3lto=Fastest (-0) with LTO
+mapleMini.menu.opt.o3lto=Fastest (-O3) with LTO
 mapleMini.menu.opt.o3lto.build.flags.optimize=-O3 -flto
 mapleMini.menu.opt.o3lto.build.flags.ldspecs=-flto
 mapleMini.menu.opt.ogstd=Debug (-g)
@@ -121,7 +121,7 @@ maple.menu.opt.o2lto.build.flags.ldspecs=-flto
 maple.menu.opt.o3std=Fastest (-03)
 maple.menu.opt.o3std.build.flags.optimize=-O3
 maple.menu.opt.o3std.build.flags.ldspecs=
-maple.menu.opt.o3lto=Fastest (-0) with LTO
+maple.menu.opt.o3lto=Fastest (-O3) with LTO
 maple.menu.opt.o3lto.build.flags.optimize=-O3 -flto
 maple.menu.opt.o3lto.build.flags.ldspecs=-flto
 maple.menu.opt.ogstd=Debug (-g)
@@ -176,7 +176,7 @@ mapleRET6.menu.opt.o2lto.build.flags.ldspecs=-flto
 mapleRET6.menu.opt.o3std=Fastest (-03)
 mapleRET6.menu.opt.o3std.build.flags.optimize=-O3
 mapleRET6.menu.opt.o3std.build.flags.ldspecs=
-mapleRET6.menu.opt.o3lto=Fastest (-0) with LTO
+mapleRET6.menu.opt.o3lto=Fastest (-O3) with LTO
 mapleRET6.menu.opt.o3lto.build.flags.optimize=-O3 -flto
 mapleRET6.menu.opt.ogstd=Debug (-g)
 mapleRET6.menu.opt.o3lto.build.flags.ldspecs=-flto
@@ -239,7 +239,7 @@ microduino32_flash.menu.opt.o2lto.build.flags.ldspecs=-flto
 microduino32_flash.menu.opt.o3std=Fastest (-03)
 microduino32_flash.menu.opt.o3std.build.flags.optimize=-O3
 microduino32_flash.menu.opt.o3std.build.flags.ldspecs=
-microduino32_flash.menu.opt.o3lto=Fastest (-0) with LTO
+microduino32_flash.menu.opt.o3lto=Fastest (-O3) with LTO
 microduino32_flash.menu.opt.o3lto.build.flags.optimize=-O3 -flto
 microduino32_flash.menu.opt.ogstd=Debug (-g)
 microduino32_flash.menu.opt.o3lto.build.flags.ldspecs=-flto
@@ -309,7 +309,7 @@ nucleo_f103rb.menu.opt.o2lto.build.flags.ldspecs=-flto
 nucleo_f103rb.menu.opt.o3std=Fastest (-03)
 nucleo_f103rb.menu.opt.o3std.build.flags.optimize=-O3
 nucleo_f103rb.menu.opt.o3std.build.flags.ldspecs=
-nucleo_f103rb.menu.opt.o3lto=Fastest (-0) with LTO
+nucleo_f103rb.menu.opt.o3lto=Fastest (-O3) with LTO
 nucleo_f103rb.menu.opt.o3lto.build.flags.optimize=-O3 -flto
 nucleo_f103rb.menu.opt.ogstd=Debug (-g)
 nucleo_f103rb.menu.opt.o3lto.build.flags.ldspecs=-flto
@@ -406,7 +406,7 @@ genericSTM32F103C.menu.opt.o2lto.build.flags.ldspecs=-flto
 genericSTM32F103C.menu.opt.o3std=Fastest (-03)
 genericSTM32F103C.menu.opt.o3std.build.flags.optimize=-O3
 genericSTM32F103C.menu.opt.o3std.build.flags.ldspecs=
-genericSTM32F103C.menu.opt.o3lto=Fastest (-0) with LTO
+genericSTM32F103C.menu.opt.o3lto=Fastest (-O3) with LTO
 genericSTM32F103C.menu.opt.o3lto.build.flags.optimize=-O3 -flto
 genericSTM32F103C.menu.opt.ogstd=Debug (-g)
 genericSTM32F103C.menu.opt.o3lto.build.flags.ldspecs=-flto
@@ -507,7 +507,7 @@ genericSTM32F103R.menu.opt.o2lto.build.flags.ldspecs=-flto
 genericSTM32F103R.menu.opt.o3std=Fastest (-03)
 genericSTM32F103R.menu.opt.o3std.build.flags.optimize=-O3
 genericSTM32F103R.menu.opt.o3std.build.flags.ldspecs=
-genericSTM32F103R.menu.opt.o3lto=Fastest (-0) with LTO
+genericSTM32F103R.menu.opt.o3lto=Fastest (-O3) with LTO
 genericSTM32F103R.menu.opt.o3lto.build.flags.optimize=-O3 -flto
 genericSTM32F103R.menu.opt.ogstd=Debug (-g)
 genericSTM32F103R.menu.opt.o3lto.build.flags.ldspecs=-flto
@@ -592,7 +592,7 @@ genericSTM32F103T.menu.opt.o2lto.build.flags.ldspecs=-flto
 genericSTM32F103T.menu.opt.o3std=Fastest (-03)
 genericSTM32F103T.menu.opt.o3std.build.flags.optimize=-O3
 genericSTM32F103T.menu.opt.o3std.build.flags.ldspecs=
-genericSTM32F103T.menu.opt.o3lto=Fastest (-0) with LTO
+genericSTM32F103T.menu.opt.o3lto=Fastest (-O3) with LTO
 genericSTM32F103T.menu.opt.o3lto.build.flags.optimize=-O3 -flto
 genericSTM32F103T.menu.opt.ogstd=Debug (-g)
 genericSTM32F103T.menu.opt.o3lto.build.flags.ldspecs=-flto
@@ -684,7 +684,7 @@ genericSTM32F103V.menu.opt.o2lto.build.flags.ldspecs=-flto
 genericSTM32F103V.menu.opt.o3std=Fastest (-03)
 genericSTM32F103V.menu.opt.o3std.build.flags.optimize=-O3
 genericSTM32F103V.menu.opt.o3std.build.flags.ldspecs=
-genericSTM32F103V.menu.opt.o3lto=Fastest (-0) with LTO
+genericSTM32F103V.menu.opt.o3lto=Fastest (-O3) with LTO
 genericSTM32F103V.menu.opt.o3lto.build.flags.optimize=-O3 -flto
 genericSTM32F103V.menu.opt.ogstd=Debug (-g)
 genericSTM32F103V.menu.opt.o3lto.build.flags.ldspecs=-flto
@@ -773,7 +773,7 @@ genericSTM32F103Z.menu.opt.o2lto.build.flags.ldspecs=-flto
 genericSTM32F103Z.menu.opt.o3std=Fastest (-03)
 genericSTM32F103Z.menu.opt.o3std.build.flags.optimize=-O3
 genericSTM32F103Z.menu.opt.o3std.build.flags.ldspecs=
-genericSTM32F103Z.menu.opt.o3lto=Fastest (-0) with LTO
+genericSTM32F103Z.menu.opt.o3lto=Fastest (-O3) with LTO
 genericSTM32F103Z.menu.opt.o3lto.build.flags.optimize=-O3 -flto
 genericSTM32F103Z.menu.opt.ogstd=Debug (-g)
 genericSTM32F103Z.menu.opt.o3lto.build.flags.ldspecs=-flto
@@ -856,7 +856,7 @@ hytiny-stm32f103t.menu.opt.o2lto.build.flags.ldspecs=-flto
 hytiny-stm32f103t.menu.opt.o3std=Fastest (-03)
 hytiny-stm32f103t.menu.opt.o3std.build.flags.optimize=-O3
 hytiny-stm32f103t.menu.opt.o3std.build.flags.ldspecs=
-hytiny-stm32f103t.menu.opt.o3lto=Fastest (-0) with LTO
+hytiny-stm32f103t.menu.opt.o3lto=Fastest (-O3) with LTO
 hytiny-stm32f103t.menu.opt.o3lto.build.flags.optimize=-O3 -flto
 hytiny-stm32f103t.menu.opt.ogstd=Debug (-g)
 hytiny-stm32f103t.menu.opt.o3lto.build.flags.ldspecs=-flto
@@ -950,7 +950,7 @@ genericGD32F103C.menu.opt.o2lto.build.flags.ldspecs=-flto
 genericGD32F103C.menu.opt.o3std=Fastest (-03)
 genericGD32F103C.menu.opt.o3std.build.flags.optimize=-O3
 genericGD32F103C.menu.opt.o3std.build.flags.ldspecs=
-genericGD32F103C.menu.opt.o3lto=Fastest (-0) with LTO
+genericGD32F103C.menu.opt.o3lto=Fastest (-O3) with LTO
 genericGD32F103C.menu.opt.o3lto.build.flags.optimize=-O3 -flto
 genericGD32F103C.menu.opt.ogstd=Debug (-g)
 genericGD32F103C.menu.opt.o3lto.build.flags.ldspecs=-flto
@@ -1010,7 +1010,7 @@ STM32VLD.menu.opt.o2lto.build.flags.ldspecs=-flto
 STM32VLD.menu.opt.o3std=Fastest (-03)
 STM32VLD.menu.opt.o3std.build.flags.optimize=-O3
 STM32VLD.menu.opt.o3std.build.flags.ldspecs=
-STM32VLD.menu.opt.o3lto=Fastest (-0) with LTO
+STM32VLD.menu.opt.o3lto=Fastest (-O3) with LTO
 STM32VLD.menu.opt.o3lto.build.flags.optimize=-O3 -flto
 STM32VLD.menu.opt.ogstd=Debug (-g)
 STM32VLD.menu.opt.o3lto.build.flags.ldspecs=-flto

From 7aae010eae645972e8bab22ff2a5c69a4a205407 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sun, 30 Jul 2017 17:05:57 +1000
Subject: [PATCH 155/307] Fixed yet another of my typos in the optimisation
 menu

---
 STM32F1/boards.txt | 26 +++++++++++++-------------
 1 file changed, 13 insertions(+), 13 deletions(-)

diff --git a/STM32F1/boards.txt b/STM32F1/boards.txt
index 3ed5158c2..c80bda9ac 100644
--- a/STM32F1/boards.txt
+++ b/STM32F1/boards.txt
@@ -63,7 +63,7 @@ mapleMini.menu.opt.o2std.build.flags.ldspecs=
 mapleMini.menu.opt.o2lto=Faster (-O2) with LTO
 mapleMini.menu.opt.o2lto.build.flags.optimize=-O2 -flto
 mapleMini.menu.opt.o2lto.build.flags.ldspecs=-flto
-mapleMini.menu.opt.o3std=Fastest (-03)
+mapleMini.menu.opt.o3std=Fastest (-O3)
 mapleMini.menu.opt.o3std.build.flags.optimize=-O3
 mapleMini.menu.opt.o3std.build.flags.ldspecs=
 mapleMini.menu.opt.o3lto=Fastest (-O3) with LTO
@@ -118,7 +118,7 @@ maple.menu.opt.o2std.build.flags.ldspecs=
 maple.menu.opt.o2lto=Faster (-O2) with LTO
 maple.menu.opt.o2lto.build.flags.optimize=-O2 -flto
 maple.menu.opt.o2lto.build.flags.ldspecs=-flto
-maple.menu.opt.o3std=Fastest (-03)
+maple.menu.opt.o3std=Fastest (-O3)
 maple.menu.opt.o3std.build.flags.optimize=-O3
 maple.menu.opt.o3std.build.flags.ldspecs=
 maple.menu.opt.o3lto=Fastest (-O3) with LTO
@@ -173,7 +173,7 @@ mapleRET6.menu.opt.o2std.build.flags.ldspecs=
 mapleRET6.menu.opt.o2lto=Faster (-O2) with LTO
 mapleRET6.menu.opt.o2lto.build.flags.optimize=-O2 -flto
 mapleRET6.menu.opt.o2lto.build.flags.ldspecs=-flto
-mapleRET6.menu.opt.o3std=Fastest (-03)
+mapleRET6.menu.opt.o3std=Fastest (-O3)
 mapleRET6.menu.opt.o3std.build.flags.optimize=-O3
 mapleRET6.menu.opt.o3std.build.flags.ldspecs=
 mapleRET6.menu.opt.o3lto=Fastest (-O3) with LTO
@@ -236,7 +236,7 @@ microduino32_flash.menu.opt.o2std.build.flags.ldspecs=
 microduino32_flash.menu.opt.o2lto=Faster (-O2) with LTO
 microduino32_flash.menu.opt.o2lto.build.flags.optimize=-O2 -flto
 microduino32_flash.menu.opt.o2lto.build.flags.ldspecs=-flto
-microduino32_flash.menu.opt.o3std=Fastest (-03)
+microduino32_flash.menu.opt.o3std=Fastest (-O3)
 microduino32_flash.menu.opt.o3std.build.flags.optimize=-O3
 microduino32_flash.menu.opt.o3std.build.flags.ldspecs=
 microduino32_flash.menu.opt.o3lto=Fastest (-O3) with LTO
@@ -306,7 +306,7 @@ nucleo_f103rb.menu.opt.o2std.build.flags.ldspecs=
 nucleo_f103rb.menu.opt.o2lto=Faster (-O2) with LTO
 nucleo_f103rb.menu.opt.o2lto.build.flags.optimize=-O2 -flto
 nucleo_f103rb.menu.opt.o2lto.build.flags.ldspecs=-flto
-nucleo_f103rb.menu.opt.o3std=Fastest (-03)
+nucleo_f103rb.menu.opt.o3std=Fastest (-O3)
 nucleo_f103rb.menu.opt.o3std.build.flags.optimize=-O3
 nucleo_f103rb.menu.opt.o3std.build.flags.ldspecs=
 nucleo_f103rb.menu.opt.o3lto=Fastest (-O3) with LTO
@@ -403,7 +403,7 @@ genericSTM32F103C.menu.opt.o2std.build.flags.ldspecs=
 genericSTM32F103C.menu.opt.o2lto=Faster (-O2) with LTO
 genericSTM32F103C.menu.opt.o2lto.build.flags.optimize=-O2 -flto
 genericSTM32F103C.menu.opt.o2lto.build.flags.ldspecs=-flto
-genericSTM32F103C.menu.opt.o3std=Fastest (-03)
+genericSTM32F103C.menu.opt.o3std=Fastest (-O3)
 genericSTM32F103C.menu.opt.o3std.build.flags.optimize=-O3
 genericSTM32F103C.menu.opt.o3std.build.flags.ldspecs=
 genericSTM32F103C.menu.opt.o3lto=Fastest (-O3) with LTO
@@ -504,7 +504,7 @@ genericSTM32F103R.menu.opt.o2std.build.flags.ldspecs=
 genericSTM32F103R.menu.opt.o2lto=Faster (-O2) with LTO
 genericSTM32F103R.menu.opt.o2lto.build.flags.optimize=-O2 -flto
 genericSTM32F103R.menu.opt.o2lto.build.flags.ldspecs=-flto
-genericSTM32F103R.menu.opt.o3std=Fastest (-03)
+genericSTM32F103R.menu.opt.o3std=Fastest (-O3)
 genericSTM32F103R.menu.opt.o3std.build.flags.optimize=-O3
 genericSTM32F103R.menu.opt.o3std.build.flags.ldspecs=
 genericSTM32F103R.menu.opt.o3lto=Fastest (-O3) with LTO
@@ -589,7 +589,7 @@ genericSTM32F103T.menu.opt.o2std.build.flags.ldspecs=
 genericSTM32F103T.menu.opt.o2lto=Faster (-O2) with LTO
 genericSTM32F103T.menu.opt.o2lto.build.flags.optimize=-O2 -flto
 genericSTM32F103T.menu.opt.o2lto.build.flags.ldspecs=-flto
-genericSTM32F103T.menu.opt.o3std=Fastest (-03)
+genericSTM32F103T.menu.opt.o3std=Fastest (-O3)
 genericSTM32F103T.menu.opt.o3std.build.flags.optimize=-O3
 genericSTM32F103T.menu.opt.o3std.build.flags.ldspecs=
 genericSTM32F103T.menu.opt.o3lto=Fastest (-O3) with LTO
@@ -681,7 +681,7 @@ genericSTM32F103V.menu.opt.o2std.build.flags.ldspecs=
 genericSTM32F103V.menu.opt.o2lto=Faster (-O2) with LTO
 genericSTM32F103V.menu.opt.o2lto.build.flags.optimize=-O2 -flto
 genericSTM32F103V.menu.opt.o2lto.build.flags.ldspecs=-flto
-genericSTM32F103V.menu.opt.o3std=Fastest (-03)
+genericSTM32F103V.menu.opt.o3std=Fastest (-O3)
 genericSTM32F103V.menu.opt.o3std.build.flags.optimize=-O3
 genericSTM32F103V.menu.opt.o3std.build.flags.ldspecs=
 genericSTM32F103V.menu.opt.o3lto=Fastest (-O3) with LTO
@@ -770,7 +770,7 @@ genericSTM32F103Z.menu.opt.o2std.build.flags.ldspecs=
 genericSTM32F103Z.menu.opt.o2lto=Faster (-O2) with LTO
 genericSTM32F103Z.menu.opt.o2lto.build.flags.optimize=-O2 -flto
 genericSTM32F103Z.menu.opt.o2lto.build.flags.ldspecs=-flto
-genericSTM32F103Z.menu.opt.o3std=Fastest (-03)
+genericSTM32F103Z.menu.opt.o3std=Fastest (-O3)
 genericSTM32F103Z.menu.opt.o3std.build.flags.optimize=-O3
 genericSTM32F103Z.menu.opt.o3std.build.flags.ldspecs=
 genericSTM32F103Z.menu.opt.o3lto=Fastest (-O3) with LTO
@@ -853,7 +853,7 @@ hytiny-stm32f103t.menu.opt.o2std.build.flags.ldspecs=
 hytiny-stm32f103t.menu.opt.o2lto=Faster (-O2) with LTO
 hytiny-stm32f103t.menu.opt.o2lto.build.flags.optimize=-O2 -flto
 hytiny-stm32f103t.menu.opt.o2lto.build.flags.ldspecs=-flto
-hytiny-stm32f103t.menu.opt.o3std=Fastest (-03)
+hytiny-stm32f103t.menu.opt.o3std=Fastest (-O3)
 hytiny-stm32f103t.menu.opt.o3std.build.flags.optimize=-O3
 hytiny-stm32f103t.menu.opt.o3std.build.flags.ldspecs=
 hytiny-stm32f103t.menu.opt.o3lto=Fastest (-O3) with LTO
@@ -947,7 +947,7 @@ genericGD32F103C.menu.opt.o2std.build.flags.ldspecs=
 genericGD32F103C.menu.opt.o2lto=Faster (-O2) with LTO
 genericGD32F103C.menu.opt.o2lto.build.flags.optimize=-O2 -flto
 genericGD32F103C.menu.opt.o2lto.build.flags.ldspecs=-flto
-genericGD32F103C.menu.opt.o3std=Fastest (-03)
+genericGD32F103C.menu.opt.o3std=Fastest (-O3)
 genericGD32F103C.menu.opt.o3std.build.flags.optimize=-O3
 genericGD32F103C.menu.opt.o3std.build.flags.ldspecs=
 genericGD32F103C.menu.opt.o3lto=Fastest (-O3) with LTO
@@ -1007,7 +1007,7 @@ STM32VLD.menu.opt.o2std.build.flags.ldspecs=
 STM32VLD.menu.opt.o2lto=Faster (-O2) with LTO
 STM32VLD.menu.opt.o2lto.build.flags.optimize=-O2 -flto
 STM32VLD.menu.opt.o2lto.build.flags.ldspecs=-flto
-STM32VLD.menu.opt.o3std=Fastest (-03)
+STM32VLD.menu.opt.o3std=Fastest (-O3)
 STM32VLD.menu.opt.o3std.build.flags.optimize=-O3
 STM32VLD.menu.opt.o3std.build.flags.ldspecs=
 STM32VLD.menu.opt.o3lto=Fastest (-O3) with LTO

From cb901b4e4f8c8630bf570ffbf30a4ca46cbcb840 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sun, 30 Jul 2017 17:43:40 +1000
Subject: [PATCH 156/307] Added CPU Speed menu to all boards except Nucleo RB,
 with additional entry for 128Mhz Turbo - NO USB. Note only tested on the Blue
 Pill

---
 STM32F1/boards.txt                            | 105 ++++++++++++++++++
 .../wirish/boards_setup.cpp                   |  12 +-
 .../wirish/boards_setup.cpp                   |  12 +-
 .../wirish/boards_setup.cpp                   |  12 +-
 .../wirish/boards_setup.cpp                   |  12 +-
 .../wirish/boards_setup.cpp                   |  12 +-
 .../wirish/boards_setup.cpp                   |  12 +-
 .../hytiny_stm32f103t/wirish/boards_setup.cpp |  12 +-
 .../variants/maple/wirish/boards_setup.cpp    |  12 +-
 .../maple_mini/wirish/boards_setup.cpp        |  12 +-
 .../maple_ret6/wirish/boards_setup.cpp        |  12 +-
 .../microduino/wirish/boards_setup.cpp        |  12 +-
 12 files changed, 182 insertions(+), 55 deletions(-)

diff --git a/STM32F1/boards.txt b/STM32F1/boards.txt
index c80bda9ac..adb200625 100644
--- a/STM32F1/boards.txt
+++ b/STM32F1/boards.txt
@@ -44,6 +44,16 @@ mapleMini.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
 mapleMini.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
 mapleMini.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
 
+#-- CPU Clock frequency
+mapleMini.menu.cpu_speed.speed_72mhz=72Mhz (Normal)
+mapleMini.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
+
+mapleMini.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
+mapleMini.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
+
+mapleMini.menu.cpu_speed.speed_128mhz=128Mhz (Turbo NO USB!)
+mapleMini.menu.cpu_speed.speed_128mhz.build.f_cpu=128000000L
+
 #-- Optimizations
 mapleMini.menu.opt.osstd=Smallest (default)
 mapleMini.menu.opt.osstd.build.flags.optimize=-Os
@@ -99,6 +109,16 @@ maple.build.ldscript=ld/flash.ld
 maple.build.variant=maple
 maple.build.vect=VECT_TAB_ADDR=0x8005000
 
+#-- CPU Clock frequency
+maple.menu.cpu_speed.speed_72mhz=72Mhz (Normal)
+maple.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
+
+maple.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
+maple.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
+
+maple.menu.cpu_speed.speed_128mhz=128Mhz (Turbo NO USB!)
+maple.menu.cpu_speed.speed_128mhz.build.f_cpu=128000000L
+
 #-- Optimizations
 maple.menu.opt.osstd=Smallest (default)
 maple.menu.opt.osstd.build.flags.optimize=-Os
@@ -154,6 +174,17 @@ mapleRET6.upload.usbID=1EAF:0003
 mapleRET6.upload.altID=1
 mapleRET6.upload.auto_reset=true
 
+#-- CPU Clock frequency
+mapleRET6.menu.cpu_speed.speed_72mhz=72Mhz (Normal)
+mapleRET6.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
+
+mapleRET6.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
+mapleRET6.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
+
+mapleRET6.menu.cpu_speed.speed_128mhz=128Mhz (Turbo NO USB!)
+mapleRET6.menu.cpu_speed.speed_128mhz.build.f_cpu=128000000L
+
+
 #-- Optimizations
 mapleRET6.menu.opt.osstd=Smallest (default)
 mapleRET6.menu.opt.osstd.build.flags.optimize=-Os
@@ -217,6 +248,16 @@ microduino32_flash.build.error_led_port=GPIOB
 microduino32_flash.build.error_led_pin=1
 microduino32_flash.build.gcc_ver=gcc-arm-none-eabi-4.8.3-2014q1
 
+#-- CPU Clock frequency
+microduino32_flash.menu.cpu_speed.speed_72mhz=72Mhz (Normal)
+microduino32_flash.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
+
+microduino32_flash.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
+microduino32_flash.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
+
+microduino32_flash.menu.cpu_speed.speed_128mhz=128Mhz (Turbo NO USB!)
+microduino32_flash.menu.cpu_speed.speed_128mhz.build.f_cpu=128000000L
+
 #-- Optimizations
 microduino32_flash.menu.opt.osstd=Smallest (default)
 microduino32_flash.menu.opt.osstd.build.flags.optimize=-Os
@@ -384,6 +425,9 @@ genericSTM32F103C.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
 genericSTM32F103C.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
 genericSTM32F103C.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
 
+genericSTM32F103C.menu.cpu_speed.speed_128mhz=128Mhz (Turbo NO USB!)
+genericSTM32F103C.menu.cpu_speed.speed_128mhz.build.f_cpu=128000000L
+
 #-- Optimizations
 genericSTM32F103C.menu.opt.osstd=Smallest (default)
 genericSTM32F103C.menu.opt.osstd.build.flags.optimize=-Os
@@ -485,6 +529,17 @@ genericSTM32F103R.menu.upload_method.BMPMethod.upload.protocol=gdb_bmp
 genericSTM32F103R.menu.upload_method.BMPMethod.upload.tool=bmp_upload
 genericSTM32F103R.menu.upload_method.BMPMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG
 
+#-- CPU Clock frequency
+genericSTM32F103R.menu.cpu_speed.speed_72mhz=72Mhz (Normal)
+genericSTM32F103R.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
+
+genericSTM32F103R.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
+genericSTM32F103R.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
+
+genericSTM32F103R.menu.cpu_speed.speed_128mhz=128Mhz (Turbo NO USB!)
+genericSTM32F103R.menu.cpu_speed.speed_128mhz.build.f_cpu=128000000L
+
+
 #-- Optimizations
 genericSTM32F103R.menu.opt.osstd=Smallest (default)
 genericSTM32F103R.menu.opt.osstd.build.flags.optimize=-Os
@@ -570,6 +625,16 @@ genericSTM32F103T.menu.upload_method.BMPMethod.upload.protocol=gdb_bmp
 genericSTM32F103T.menu.upload_method.BMPMethod.upload.tool=bmp_upload
 genericSTM32F103T.menu.upload_method.BMPMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG
 
+#-- CPU Clock frequency
+genericSTM32F103T.menu.cpu_speed.speed_72mhz=72Mhz (Normal)
+genericSTM32F103T.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
+
+genericSTM32F103T.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
+genericSTM32F103T.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
+
+genericSTM32F103T.menu.cpu_speed.speed_128mhz=128Mhz (Turbo NO USB!)
+genericSTM32F103T.menu.cpu_speed.speed_128mhz.build.f_cpu=128000000L
+
 #-- Optimizations
 genericSTM32F103T.menu.opt.osstd=Smallest (default)
 genericSTM32F103T.menu.opt.osstd.build.flags.optimize=-Os
@@ -662,6 +727,16 @@ genericSTM32F103V.menu.upload_method.BMPMethod.upload.protocol=gdb_bmp
 genericSTM32F103V.menu.upload_method.BMPMethod.upload.tool=bmp_upload
 genericSTM32F103V.menu.upload_method.BMPMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG
 
+#-- CPU Clock frequency
+genericSTM32F103V.menu.cpu_speed.speed_72mhz=72Mhz (Normal)
+genericSTM32F103V.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
+
+genericSTM32F103V.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
+genericSTM32F103V.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
+
+genericSTM32F103V.menu.cpu_speed.speed_128mhz=128Mhz (Turbo NO USB!)
+genericSTM32F103V.menu.cpu_speed.speed_128mhz.build.f_cpu=128000000L
+
 #-- Optimizations
 genericSTM32F103V.menu.opt.osstd=Smallest (default)
 genericSTM32F103V.menu.opt.osstd.build.flags.optimize=-Os
@@ -751,6 +826,16 @@ genericSTM32F103Z.menu.upload_method.BMPMethod.upload.protocol=gdb_bmp
 genericSTM32F103Z.menu.upload_method.BMPMethod.upload.tool=bmp_upload
 genericSTM32F103Z.menu.upload_method.BMPMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG
 
+#-- CPU Clock frequency
+genericSTM32F103Z.menu.cpu_speed.speed_72mhz=72Mhz (Normal)
+genericSTM32F103Z.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
+
+genericSTM32F103Z.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
+genericSTM32F103Z.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
+
+genericSTM32F103Z.menu.cpu_speed.speed_128mhz=128Mhz (Turbo NO USB!)
+genericSTM32F103Z.menu.cpu_speed.speed_128mhz.build.f_cpu=128000000L
+
 #-- Optimizations
 genericSTM32F103Z.menu.opt.osstd=Smallest (default)
 genericSTM32F103Z.menu.opt.osstd.build.flags.optimize=-Os
@@ -834,6 +919,16 @@ hytiny-stm32f103t.menu.upload_method.jlinkMethod.upload.protocol=jlink
 hytiny-stm32f103t.menu.upload_method.jlinkMethod.upload.tool=jlink_upload
 hytiny-stm32f103t.menu.upload_method.jlinkMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG=1 -DSERIAL_USB -DGENERIC_BOOTLOADER 
 
+#-- CPU Clock frequency
+hytiny-stm32f103t.menu.cpu_speed.speed_72mhz=72Mhz (Normal)
+hytiny-stm32f103t.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
+
+hytiny-stm32f103t.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
+hytiny-stm32f103t.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
+
+hytiny-stm32f103t.menu.cpu_speed.speed_128mhz=128Mhz (Turbo NO USB!)
+hytiny-stm32f103t.menu.cpu_speed.speed_128mhz.build.f_cpu=128000000L
+
 #-- Optimizations
 hytiny-stm32f103t.menu.opt.osstd=Smallest (default)
 hytiny-stm32f103t.menu.opt.osstd.build.flags.optimize=-Os
@@ -988,6 +1083,16 @@ STM32VLD.menu.upload_method.STLinkMethod.upload.protocol=STLink
 STM32VLD.menu.upload_method.STLinkMethod.upload.tool=stlink_upload
 STM32VLD.menu.upload_method.STLinkMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG  
 
+#-- CPU Clock frequency
+STM32VLD.menu.cpu_speed.speed_72mhz=72Mhz (Normal)
+STM32VLD.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
+
+STM32VLD.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
+STM32VLD.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
+
+STM32VLD.menu.cpu_speed.speed_128mhz=128Mhz (Turbo NO USB!)
+STM32VLD.menu.cpu_speed.speed_128mhz.build.f_cpu=128000000L
+
 #-- Optimizations
 STM32VLD.menu.opt.osstd=Smallest (default)
 STM32VLD.menu.opt.osstd.build.flags.optimize=-Os
diff --git a/STM32F1/variants/generic_stm32f103c/wirish/boards_setup.cpp b/STM32F1/variants/generic_stm32f103c/wirish/boards_setup.cpp
index 551628264..9e8332eec 100644
--- a/STM32F1/variants/generic_stm32f103c/wirish/boards_setup.cpp
+++ b/STM32F1/variants/generic_stm32f103c/wirish/boards_setup.cpp
@@ -48,11 +48,13 @@
 // works for F103 performance line MCUs, which is all that LeafLabs
 // currently officially supports).
 #ifndef BOARD_RCC_PLLMUL
-  #if F_CPU==72000000
-	#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
-  #elif F_CPU==48000000
-	#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
-  #endif
+	#if F_CPU==128000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
+	#elif F_CPU==72000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+	#elif F_CPU==48000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
+	#endif
 #endif
 
 namespace wirish {
diff --git a/STM32F1/variants/generic_stm32f103r/wirish/boards_setup.cpp b/STM32F1/variants/generic_stm32f103r/wirish/boards_setup.cpp
index d7774f763..04130152c 100644
--- a/STM32F1/variants/generic_stm32f103r/wirish/boards_setup.cpp
+++ b/STM32F1/variants/generic_stm32f103r/wirish/boards_setup.cpp
@@ -48,11 +48,13 @@
 // works for F103 performance line MCUs, which is all that LeafLabs
 // currently officially supports).
 #ifndef BOARD_RCC_PLLMUL
-  #if F_CPU==72000000
-	#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
-  #elif F_CPU==48000000
-	#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
-  #endif
+	#if F_CPU==128000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
+	#elif F_CPU==72000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+	#elif F_CPU==48000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
+	#endif
 #endif
 
 namespace wirish {
diff --git a/STM32F1/variants/generic_stm32f103r8/wirish/boards_setup.cpp b/STM32F1/variants/generic_stm32f103r8/wirish/boards_setup.cpp
index 7c939771e..8da724ded 100644
--- a/STM32F1/variants/generic_stm32f103r8/wirish/boards_setup.cpp
+++ b/STM32F1/variants/generic_stm32f103r8/wirish/boards_setup.cpp
@@ -48,11 +48,13 @@
 // works for F103 performance line MCUs, which is all that LeafLabs
 // currently officially supports).
 #ifndef BOARD_RCC_PLLMUL
-  #if F_CPU==72000000
-	#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
-  #elif F_CPU==48000000
-	#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
-  #endif
+	#if F_CPU==128000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
+	#elif F_CPU==72000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+	#elif F_CPU==48000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
+	#endif
 #endif
 
 namespace wirish {
diff --git a/STM32F1/variants/generic_stm32f103t/wirish/boards_setup.cpp b/STM32F1/variants/generic_stm32f103t/wirish/boards_setup.cpp
index 551628264..9e8332eec 100644
--- a/STM32F1/variants/generic_stm32f103t/wirish/boards_setup.cpp
+++ b/STM32F1/variants/generic_stm32f103t/wirish/boards_setup.cpp
@@ -48,11 +48,13 @@
 // works for F103 performance line MCUs, which is all that LeafLabs
 // currently officially supports).
 #ifndef BOARD_RCC_PLLMUL
-  #if F_CPU==72000000
-	#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
-  #elif F_CPU==48000000
-	#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
-  #endif
+	#if F_CPU==128000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
+	#elif F_CPU==72000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+	#elif F_CPU==48000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
+	#endif
 #endif
 
 namespace wirish {
diff --git a/STM32F1/variants/generic_stm32f103v/wirish/boards_setup.cpp b/STM32F1/variants/generic_stm32f103v/wirish/boards_setup.cpp
index 1f23679ab..dba014b91 100644
--- a/STM32F1/variants/generic_stm32f103v/wirish/boards_setup.cpp
+++ b/STM32F1/variants/generic_stm32f103v/wirish/boards_setup.cpp
@@ -48,11 +48,13 @@
 // works for F103 performance line MCUs, which is all that LeafLabs
 // currently officially supports).
 #ifndef BOARD_RCC_PLLMUL
-  #if F_CPU==72000000
-	#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
-  #elif F_CPU==48000000
-	#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
-  #endif
+	#if F_CPU==128000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
+	#elif F_CPU==72000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+	#elif F_CPU==48000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
+	#endif
 #endif
 
 namespace wirish {
diff --git a/STM32F1/variants/generic_stm32f103z/wirish/boards_setup.cpp b/STM32F1/variants/generic_stm32f103z/wirish/boards_setup.cpp
index e2cfe4ad8..3d4e4e8cf 100644
--- a/STM32F1/variants/generic_stm32f103z/wirish/boards_setup.cpp
+++ b/STM32F1/variants/generic_stm32f103z/wirish/boards_setup.cpp
@@ -48,11 +48,13 @@
 // works for F103 performance line MCUs, which is all that LeafLabs
 // currently officially supports).
 #ifndef BOARD_RCC_PLLMUL
-  #if F_CPU==72000000
-	#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
-  #elif F_CPU==48000000
-	#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
-  #endif
+	#if F_CPU==128000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
+	#elif F_CPU==72000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+	#elif F_CPU==48000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
+	#endif
 #endif
 
 namespace wirish {
diff --git a/STM32F1/variants/hytiny_stm32f103t/wirish/boards_setup.cpp b/STM32F1/variants/hytiny_stm32f103t/wirish/boards_setup.cpp
index df393473b..f10fcf864 100644
--- a/STM32F1/variants/hytiny_stm32f103t/wirish/boards_setup.cpp
+++ b/STM32F1/variants/hytiny_stm32f103t/wirish/boards_setup.cpp
@@ -48,11 +48,13 @@
 // works for F103 performance line MCUs, which is all that LeafLabs
 // currently officially supports).
 #ifndef BOARD_RCC_PLLMUL
-  #if F_CPU==72000000
-	#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
-  #elif F_CPU==48000000
-	#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
-  #endif
+	#if F_CPU==128000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
+	#elif F_CPU==72000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+	#elif F_CPU==48000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
+	#endif
 #endif
 
 namespace wirish {
diff --git a/STM32F1/variants/maple/wirish/boards_setup.cpp b/STM32F1/variants/maple/wirish/boards_setup.cpp
index 1071d6da5..c4b55c099 100644
--- a/STM32F1/variants/maple/wirish/boards_setup.cpp
+++ b/STM32F1/variants/maple/wirish/boards_setup.cpp
@@ -48,11 +48,13 @@
 // works for F103 performance line MCUs, which is all that LeafLabs
 // currently officially supports).
 #ifndef BOARD_RCC_PLLMUL
-  #if F_CPU==72000000
-	#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
-  #elif F_CPU==48000000
-	#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
-  #endif
+	#if F_CPU==128000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
+	#elif F_CPU==72000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+	#elif F_CPU==48000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
+	#endif
 #endif
 
 namespace wirish {
diff --git a/STM32F1/variants/maple_mini/wirish/boards_setup.cpp b/STM32F1/variants/maple_mini/wirish/boards_setup.cpp
index df393473b..f10fcf864 100644
--- a/STM32F1/variants/maple_mini/wirish/boards_setup.cpp
+++ b/STM32F1/variants/maple_mini/wirish/boards_setup.cpp
@@ -48,11 +48,13 @@
 // works for F103 performance line MCUs, which is all that LeafLabs
 // currently officially supports).
 #ifndef BOARD_RCC_PLLMUL
-  #if F_CPU==72000000
-	#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
-  #elif F_CPU==48000000
-	#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
-  #endif
+	#if F_CPU==128000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
+	#elif F_CPU==72000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+	#elif F_CPU==48000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
+	#endif
 #endif
 
 namespace wirish {
diff --git a/STM32F1/variants/maple_ret6/wirish/boards_setup.cpp b/STM32F1/variants/maple_ret6/wirish/boards_setup.cpp
index 1071d6da5..c4b55c099 100644
--- a/STM32F1/variants/maple_ret6/wirish/boards_setup.cpp
+++ b/STM32F1/variants/maple_ret6/wirish/boards_setup.cpp
@@ -48,11 +48,13 @@
 // works for F103 performance line MCUs, which is all that LeafLabs
 // currently officially supports).
 #ifndef BOARD_RCC_PLLMUL
-  #if F_CPU==72000000
-	#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
-  #elif F_CPU==48000000
-	#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
-  #endif
+	#if F_CPU==128000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
+	#elif F_CPU==72000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+	#elif F_CPU==48000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
+	#endif
 #endif
 
 namespace wirish {
diff --git a/STM32F1/variants/microduino/wirish/boards_setup.cpp b/STM32F1/variants/microduino/wirish/boards_setup.cpp
index e8998435b..785753a20 100644
--- a/STM32F1/variants/microduino/wirish/boards_setup.cpp
+++ b/STM32F1/variants/microduino/wirish/boards_setup.cpp
@@ -48,11 +48,13 @@
 // works for F103 performance line MCUs, which is all that LeafLabs
 // currently officially supports).
 #ifndef BOARD_RCC_PLLMUL
-  #if F_CPU==72000000
-	#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
-  #elif F_CPU==48000000
-	#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
-  #endif
+	#if F_CPU==128000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_16
+	#elif F_CPU==72000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_9
+	#elif F_CPU==48000000
+		#define BOARD_RCC_PLLMUL RCC_PLLMUL_6
+	#endif
 #endif
 
 namespace wirish {

From 375a8f84b570077d6260babe6c040aef14f6235e Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sun, 30 Jul 2017 20:08:20 +1000
Subject: [PATCH 157/307] Fixed typo in F1 boards.txt for STM32F103CB RAM size

---
 STM32F1/boards.txt | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/boards.txt b/STM32F1/boards.txt
index adb200625..9c2def417 100644
--- a/STM32F1/boards.txt
+++ b/STM32F1/boards.txt
@@ -385,7 +385,7 @@ genericSTM32F103C.menu.device_variant.STM32F103CB=STM32F103CB (20k RAM. 128k Fla
 genericSTM32F103C.menu.device_variant.STM32F103CB.build.cpu_flags=-DMCU_STM32F103CB
 genericSTM32F103C.menu.device_variant.STM32F103CB.build.ldscript=ld/jtag.ld
 genericSTM32F103C.menu.device_variant.STM32F103CB.upload.maximum_size=131072
-genericSTM32F103C.menu.device_variant.STM32F103C8.upload.maximum_data_size=20480
+genericSTM32F103C.menu.device_variant.STM32F103CB.upload.maximum_data_size=20480
 
 #---------------------------- UPLOAD METHODS ---------------------------
 

From 14ddcfd97dd82d0e1f91b9fb90307bcf7d597fc9 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Mon, 31 Jul 2017 10:51:52 +1000
Subject: [PATCH 158/307] Changed text on 128Mhz CPU speed option - to add
 warning that there is No USB and also Manual reset needed to upload

---
 STM32F1/boards.txt | 22 +++++++++++-----------
 1 file changed, 11 insertions(+), 11 deletions(-)

diff --git a/STM32F1/boards.txt b/STM32F1/boards.txt
index 9c2def417..ef6fc8e2c 100644
--- a/STM32F1/boards.txt
+++ b/STM32F1/boards.txt
@@ -51,7 +51,7 @@ mapleMini.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
 mapleMini.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
 mapleMini.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
 
-mapleMini.menu.cpu_speed.speed_128mhz=128Mhz (Turbo NO USB!)
+mapleMini.menu.cpu_speed.speed_128mhz=Overclocked 128Mhz NO USB SERIAL. MANUAL RESET NEEDED TO UPLOAD
 mapleMini.menu.cpu_speed.speed_128mhz.build.f_cpu=128000000L
 
 #-- Optimizations
@@ -116,7 +116,7 @@ maple.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
 maple.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
 maple.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
 
-maple.menu.cpu_speed.speed_128mhz=128Mhz (Turbo NO USB!)
+maple.menu.cpu_speed.speed_128mhz=Overclocked 128Mhz NO USB SERIAL. MANUAL RESET NEEDED TO UPLOAD
 maple.menu.cpu_speed.speed_128mhz.build.f_cpu=128000000L
 
 #-- Optimizations
@@ -181,7 +181,7 @@ mapleRET6.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
 mapleRET6.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
 mapleRET6.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
 
-mapleRET6.menu.cpu_speed.speed_128mhz=128Mhz (Turbo NO USB!)
+mapleRET6.menu.cpu_speed.speed_128mhz=Overclocked 128Mhz NO USB SERIAL. MANUAL RESET NEEDED TO UPLOAD
 mapleRET6.menu.cpu_speed.speed_128mhz.build.f_cpu=128000000L
 
 
@@ -255,7 +255,7 @@ microduino32_flash.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
 microduino32_flash.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
 microduino32_flash.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
 
-microduino32_flash.menu.cpu_speed.speed_128mhz=128Mhz (Turbo NO USB!)
+microduino32_flash.menu.cpu_speed.speed_128mhz=Overclocked 128Mhz NO USB SERIAL. MANUAL RESET NEEDED TO UPLOAD
 microduino32_flash.menu.cpu_speed.speed_128mhz.build.f_cpu=128000000L
 
 #-- Optimizations
@@ -425,7 +425,7 @@ genericSTM32F103C.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
 genericSTM32F103C.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
 genericSTM32F103C.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
 
-genericSTM32F103C.menu.cpu_speed.speed_128mhz=128Mhz (Turbo NO USB!)
+genericSTM32F103C.menu.cpu_speed.speed_128mhz=Overclocked 128Mhz NO USB SERIAL. MANUAL RESET NEEDED TO UPLOAD
 genericSTM32F103C.menu.cpu_speed.speed_128mhz.build.f_cpu=128000000L
 
 #-- Optimizations
@@ -536,7 +536,7 @@ genericSTM32F103R.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
 genericSTM32F103R.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
 genericSTM32F103R.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
 
-genericSTM32F103R.menu.cpu_speed.speed_128mhz=128Mhz (Turbo NO USB!)
+genericSTM32F103R.menu.cpu_speed.speed_128mhz=Overclocked 128Mhz NO USB SERIAL. MANUAL RESET NEEDED TO UPLOAD
 genericSTM32F103R.menu.cpu_speed.speed_128mhz.build.f_cpu=128000000L
 
 
@@ -632,7 +632,7 @@ genericSTM32F103T.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
 genericSTM32F103T.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
 genericSTM32F103T.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
 
-genericSTM32F103T.menu.cpu_speed.speed_128mhz=128Mhz (Turbo NO USB!)
+genericSTM32F103T.menu.cpu_speed.speed_128mhz=Overclocked 128Mhz NO USB SERIAL. MANUAL RESET NEEDED TO UPLOAD
 genericSTM32F103T.menu.cpu_speed.speed_128mhz.build.f_cpu=128000000L
 
 #-- Optimizations
@@ -734,7 +734,7 @@ genericSTM32F103V.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
 genericSTM32F103V.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
 genericSTM32F103V.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
 
-genericSTM32F103V.menu.cpu_speed.speed_128mhz=128Mhz (Turbo NO USB!)
+genericSTM32F103V.menu.cpu_speed.speed_128mhz=Overclocked 128Mhz NO USB SERIAL. MANUAL RESET NEEDED TO UPLOAD
 genericSTM32F103V.menu.cpu_speed.speed_128mhz.build.f_cpu=128000000L
 
 #-- Optimizations
@@ -833,7 +833,7 @@ genericSTM32F103Z.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
 genericSTM32F103Z.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
 genericSTM32F103Z.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
 
-genericSTM32F103Z.menu.cpu_speed.speed_128mhz=128Mhz (Turbo NO USB!)
+genericSTM32F103Z.menu.cpu_speed.speed_128mhz=Overclocked 128Mhz NO USB SERIAL. MANUAL RESET NEEDED TO UPLOAD
 genericSTM32F103Z.menu.cpu_speed.speed_128mhz.build.f_cpu=128000000L
 
 #-- Optimizations
@@ -926,7 +926,7 @@ hytiny-stm32f103t.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
 hytiny-stm32f103t.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
 hytiny-stm32f103t.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
 
-hytiny-stm32f103t.menu.cpu_speed.speed_128mhz=128Mhz (Turbo NO USB!)
+hytiny-stm32f103t.menu.cpu_speed.speed_128mhz=Overclocked 128Mhz NO USB SERIAL. MANUAL RESET NEEDED TO UPLOAD
 hytiny-stm32f103t.menu.cpu_speed.speed_128mhz.build.f_cpu=128000000L
 
 #-- Optimizations
@@ -1090,7 +1090,7 @@ STM32VLD.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
 STM32VLD.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
 STM32VLD.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
 
-STM32VLD.menu.cpu_speed.speed_128mhz=128Mhz (Turbo NO USB!)
+STM32VLD.menu.cpu_speed.speed_128mhz=Overclocked 128Mhz NO USB SERIAL. MANUAL RESET NEEDED TO UPLOAD
 STM32VLD.menu.cpu_speed.speed_128mhz.build.f_cpu=128000000L
 
 #-- Optimizations

From 7d1119ee3456e6db4e44dc8a621671d83af76f88 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Mon, 31 Jul 2017 10:56:31 +1000
Subject: [PATCH 159/307] Removed Debug with LTO optimisation option, to fix
 issue #320

---
 STM32F1/boards.txt | 39 ---------------------------------------
 1 file changed, 39 deletions(-)

diff --git a/STM32F1/boards.txt b/STM32F1/boards.txt
index ef6fc8e2c..9cef20747 100644
--- a/STM32F1/boards.txt
+++ b/STM32F1/boards.txt
@@ -82,9 +82,6 @@ mapleMini.menu.opt.o3lto.build.flags.ldspecs=-flto
 mapleMini.menu.opt.ogstd=Debug (-g)
 mapleMini.menu.opt.ogstd.build.flags.optimize=-Og
 mapleMini.menu.opt.ogstd.build.flags.ldspecs=
-mapleMini.menu.opt.oglto=Debug with LTO
-mapleMini.menu.opt.oglto.build.flags.optimize=-Og -flto
-mapleMini.menu.opt.oglto.build.flags.ldspecs=-flto
 
 
 ##############################################################
@@ -147,9 +144,6 @@ maple.menu.opt.o3lto.build.flags.ldspecs=-flto
 maple.menu.opt.ogstd=Debug (-g)
 maple.menu.opt.ogstd.build.flags.optimize=-Og
 maple.menu.opt.ogstd.build.flags.ldspecs=
-maple.menu.opt.oglto=Debug with LTO
-maple.menu.opt.oglto.build.flags.optimize=-Og -flto
-maple.menu.opt.oglto.build.flags.ldspecs=-flto
 
 ##############################################################
 mapleRET6.name=Maple (RET6)
@@ -213,9 +207,6 @@ mapleRET6.menu.opt.ogstd=Debug (-g)
 mapleRET6.menu.opt.o3lto.build.flags.ldspecs=-flto
 mapleRET6.menu.opt.ogstd.build.flags.optimize=-Og
 mapleRET6.menu.opt.ogstd.build.flags.ldspecs=
-mapleRET6.menu.opt.oglto=Debug with LTO
-mapleRET6.menu.opt.oglto.build.flags.optimize=-Og -flto
-mapleRET6.menu.opt.oglto.build.flags.ldspecs=-flto
 
 ##############################################################
 
@@ -286,9 +277,6 @@ microduino32_flash.menu.opt.ogstd=Debug (-g)
 microduino32_flash.menu.opt.o3lto.build.flags.ldspecs=-flto
 microduino32_flash.menu.opt.ogstd.build.flags.optimize=-Og
 microduino32_flash.menu.opt.ogstd.build.flags.ldspecs=
-microduino32_flash.menu.opt.oglto=Debug with LTO
-microduino32_flash.menu.opt.oglto.build.flags.optimize=-Og -flto
-microduino32_flash.menu.opt.oglto.build.flags.ldspecs=-flto
 
 ##############################################################
 nucleo_f103rb.name=STM Nucleo F103RB (STLink)
@@ -356,9 +344,6 @@ nucleo_f103rb.menu.opt.ogstd=Debug (-g)
 nucleo_f103rb.menu.opt.o3lto.build.flags.ldspecs=-flto
 nucleo_f103rb.menu.opt.ogstd.build.flags.optimize=-Og
 nucleo_f103rb.menu.opt.ogstd.build.flags.ldspecs=
-nucleo_f103rb.menu.opt.oglto=Debug with LTO
-nucleo_f103rb.menu.opt.oglto.build.flags.optimize=-Og -flto
-nucleo_f103rb.menu.opt.oglto.build.flags.ldspecs=-flto
 
 ###################### Generic STM32F103C ########################################
 
@@ -456,9 +441,6 @@ genericSTM32F103C.menu.opt.ogstd=Debug (-g)
 genericSTM32F103C.menu.opt.o3lto.build.flags.ldspecs=-flto
 genericSTM32F103C.menu.opt.ogstd.build.flags.optimize=-Og
 genericSTM32F103C.menu.opt.ogstd.build.flags.ldspecs=
-genericSTM32F103C.menu.opt.oglto=Debug with LTO
-genericSTM32F103C.menu.opt.oglto.build.flags.optimize=-Og -flto
-genericSTM32F103C.menu.opt.oglto.build.flags.ldspecs=-flto
 
 ########################### Generic STM32F103R ###########################
 
@@ -568,9 +550,6 @@ genericSTM32F103R.menu.opt.ogstd=Debug (-g)
 genericSTM32F103R.menu.opt.o3lto.build.flags.ldspecs=-flto
 genericSTM32F103R.menu.opt.ogstd.build.flags.optimize=-Og
 genericSTM32F103R.menu.opt.ogstd.build.flags.ldspecs=
-genericSTM32F103R.menu.opt.oglto=Debug with LTO
-genericSTM32F103R.menu.opt.oglto.build.flags.optimize=-Og -flto
-genericSTM32F103R.menu.opt.oglto.build.flags.ldspecs=-flto
 
 ###################### Generic STM32F103T ########################################
 
@@ -663,9 +642,6 @@ genericSTM32F103T.menu.opt.ogstd=Debug (-g)
 genericSTM32F103T.menu.opt.o3lto.build.flags.ldspecs=-flto
 genericSTM32F103T.menu.opt.ogstd.build.flags.optimize=-Og
 genericSTM32F103T.menu.opt.ogstd.build.flags.ldspecs=
-genericSTM32F103T.menu.opt.oglto=Debug with LTO
-genericSTM32F103T.menu.opt.oglto.build.flags.optimize=-Og -flto
-genericSTM32F103T.menu.opt.oglto.build.flags.ldspecs=-flto
 
 ########################### Generic STM32F103V ###########################
 
@@ -765,9 +741,6 @@ genericSTM32F103V.menu.opt.ogstd=Debug (-g)
 genericSTM32F103V.menu.opt.o3lto.build.flags.ldspecs=-flto
 genericSTM32F103V.menu.opt.ogstd.build.flags.optimize=-Og
 genericSTM32F103V.menu.opt.ogstd.build.flags.ldspecs=
-genericSTM32F103V.menu.opt.oglto=Debug with LTO
-genericSTM32F103V.menu.opt.oglto.build.flags.optimize=-Og -flto
-genericSTM32F103V.menu.opt.oglto.build.flags.ldspecs=-flto
 
 ########################### Generic STM32F103Z ###########################
 
@@ -864,9 +837,6 @@ genericSTM32F103Z.menu.opt.ogstd=Debug (-g)
 genericSTM32F103Z.menu.opt.o3lto.build.flags.ldspecs=-flto
 genericSTM32F103Z.menu.opt.ogstd.build.flags.optimize=-Og
 genericSTM32F103Z.menu.opt.ogstd.build.flags.ldspecs=
-genericSTM32F103Z.menu.opt.oglto=Debug with LTO
-genericSTM32F103Z.menu.opt.oglto.build.flags.optimize=-Og -flto
-genericSTM32F103Z.menu.opt.oglto.build.flags.ldspecs=-flto
 
 ###################### HYTiny STM32F103T ########################################
 
@@ -957,9 +927,6 @@ hytiny-stm32f103t.menu.opt.ogstd=Debug (-g)
 hytiny-stm32f103t.menu.opt.o3lto.build.flags.ldspecs=-flto
 hytiny-stm32f103t.menu.opt.ogstd.build.flags.optimize=-Og
 hytiny-stm32f103t.menu.opt.ogstd.build.flags.ldspecs=
-hytiny-stm32f103t.menu.opt.oglto=Debug with LTO
-hytiny-stm32f103t.menu.opt.oglto.build.flags.optimize=-Og -flto
-hytiny-stm32f103t.menu.opt.oglto.build.flags.ldspecs=-flto
 
 ###################### Generic GD32F103C  ########################################
 
@@ -1051,9 +1018,6 @@ genericGD32F103C.menu.opt.ogstd=Debug (-g)
 genericGD32F103C.menu.opt.o3lto.build.flags.ldspecs=-flto
 genericGD32F103C.menu.opt.ogstd.build.flags.optimize=-Og
 genericGD32F103C.menu.opt.ogstd.build.flags.ldspecs=
-genericGD32F103C.menu.opt.oglto=Debug with LTO
-genericGD32F103C.menu.opt.oglto.build.flags.optimize=-Og -flto
-genericGD32F103C.menu.opt.oglto.build.flags.ldspecs=-flto
 
 ########################### STM32VLD to FLASH ###########################
 
@@ -1121,8 +1085,5 @@ STM32VLD.menu.opt.ogstd=Debug (-g)
 STM32VLD.menu.opt.o3lto.build.flags.ldspecs=-flto
 STM32VLD.menu.opt.ogstd.build.flags.optimize=-Og
 STM32VLD.menu.opt.ogstd.build.flags.ldspecs=
-STM32VLD.menu.opt.oglto=Debug with LTO
-STM32VLD.menu.opt.oglto.build.flags.optimize=-Og -flto
-STM32VLD.menu.opt.oglto.build.flags.ldspecs=-flto
 
 ################################################################################
\ No newline at end of file

From ac27993d10a9d910890b6c655a4435fcd1f10ab6 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Mon, 31 Jul 2017 13:33:00 +1000
Subject: [PATCH 160/307] Added makeWord macro and functions to fix #316

---
 STM32F1/cores/maple/wirish_math.cpp | 9 +++++++++
 STM32F1/cores/maple/wirish_math.h   | 6 ++++++
 2 files changed, 15 insertions(+)

diff --git a/STM32F1/cores/maple/wirish_math.cpp b/STM32F1/cores/maple/wirish_math.cpp
index 3b682d388..f8ada9f96 100644
--- a/STM32F1/cores/maple/wirish_math.cpp
+++ b/STM32F1/cores/maple/wirish_math.cpp
@@ -47,3 +47,12 @@ long random(long howsmall, long howbig) {
     return random(diff) + howsmall;
 }
 
+extern uint16_t makeWord( uint16_t w )
+{
+  return w ;
+}
+
+extern uint16_t makeWord( uint8_t h, uint8_t l )
+{
+  return (h << 8) | l ;
+}
diff --git a/STM32F1/cores/maple/wirish_math.h b/STM32F1/cores/maple/wirish_math.h
index d103d8632..9140d066e 100644
--- a/STM32F1/cores/maple/wirish_math.h
+++ b/STM32F1/cores/maple/wirish_math.h
@@ -33,6 +33,7 @@
 #define _WIRISH_WIRISH_MATH_H_
 
 #include <math.h>
+#include <stdint.h>
 
 /**
  * @brief Initialize the pseudo-random number generator.
@@ -161,4 +162,9 @@ double sqrt(double x);
  */
 double pow(double x, double y);
 
+extern uint16_t makeWord( uint16_t w ) ;
+extern uint16_t makeWord( uint8_t h, uint8_t l ) ;
+
+#define word(...) makeWord(__VA_ARGS__)
+
 #endif

From c0f655f90ff0a89e7c88b05e94c2826bace60510 Mon Sep 17 00:00:00 2001
From: Cristi Marius Tiutiu <mtiutiu@gmail.com>
Date: Mon, 31 Jul 2017 11:42:28 +0300
Subject: [PATCH 161/307] added menu optimizations support for F3/F4 boards

---
 STM32F3/boards.txt   |  30 +++++++++++
 STM32F3/platform.txt |   8 +--
 STM32F4/boards.txt   | 116 +++++++++++++++++++++++++++++++++++++++++++
 STM32F4/platform.txt |   8 +--
 4 files changed, 154 insertions(+), 8 deletions(-)

diff --git a/STM32F3/boards.txt b/STM32F3/boards.txt
index 6c011bce3..98a184df4 100644
--- a/STM32F3/boards.txt
+++ b/STM32F3/boards.txt
@@ -1,5 +1,7 @@
 # 
 
+menu.opt=Optimize
+
 ##############################################################
 discovery_f3.name=STM32F3Discovery
 
@@ -28,5 +30,33 @@ discovery_f3.build.error_led_port=GPIOE
 discovery_f3.build.error_led_pin=8
 discovery_f3.build.board=STM32F3Discovery
 
+#-- Optimizations
+discovery_f3.menu.opt.osstd=Smallest (default)
+discovery_f3.menu.opt.osstd.build.flags.optimize=-Os
+discovery_f3.menu.opt.osstd.build.flags.ldspecs=
+discovery_f3.menu.opt.oslto=Smallest Code with LTO
+discovery_f3.menu.opt.oslto.build.flags.optimize=-Os -flto
+discovery_f3.menu.opt.oslto.build.flags.ldspecs=-flto
+discovery_f3.menu.opt.o1std=Fast (-O1)
+discovery_f3.menu.opt.o1std.build.flags.optimize=-O1
+discovery_f3.menu.opt.o1std.build.flags.ldspecs=
+discovery_f3.menu.opt.o1lto=Fast (-O1) with LTO
+discovery_f3.menu.opt.o1lto.build.flags.optimize=-O1 -flto
+discovery_f3.menu.opt.o1lto.build.flags.ldspecs=-flto
+discovery_f3.menu.opt.o2std=Faster (-O2)
+discovery_f3.menu.opt.o2std.build.flags.optimize=-O2
+discovery_f3.menu.opt.o2std.build.flags.ldspecs=
+discovery_f3.menu.opt.o2lto=Faster (-O2) with LTO
+discovery_f3.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+discovery_f3.menu.opt.o2lto.build.flags.ldspecs=-flto
+discovery_f3.menu.opt.o3std=Fastest (-O3)
+discovery_f3.menu.opt.o3std.build.flags.optimize=-O3
+discovery_f3.menu.opt.o3std.build.flags.ldspecs=
+discovery_f3.menu.opt.o3lto=Fastest (-O3) with LTO
+discovery_f3.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+discovery_f3.menu.opt.o3lto.build.flags.ldspecs=-flto
+discovery_f3.menu.opt.ogstd=Debug (-g)
+discovery_f3.menu.opt.ogstd.build.flags.optimize=-Og
+discovery_f3.menu.opt.ogstd.build.flags.ldspecs=
 ##############################################################
 
diff --git a/STM32F3/platform.txt b/STM32F3/platform.txt
index 3218f85c1..94f787c81 100644
--- a/STM32F3/platform.txt
+++ b/STM32F3/platform.txt
@@ -12,20 +12,20 @@ version=0.1.0
 
 compiler.path={runtime.tools.arm-none-eabi-gcc.path}/bin/
 compiler.c.cmd=arm-none-eabi-gcc
-compiler.c.flags=-c -g -Os -w -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
+compiler.c.flags=-c -g {build.flags.optimize} -w -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
 compiler.c.elf.cmd=arm-none-eabi-g++
-compiler.c.elf.flags=-Os -Wl,--gc-sections
+compiler.c.elf.flags={build.flags.optimize} -Wl,--gc-sections {build.flags.ldspecs}
 compiler.S.cmd=arm-none-eabi-gcc
 compiler.S.flags=-c -g -x assembler-with-cpp -MMD
 compiler.cpp.cmd=arm-none-eabi-g++
-compiler.cpp.flags=-c -g -Os -w -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin} 
+compiler.cpp.flags=-c -g {build.flags.optimize} -w -MMD -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin} 
 compiler.ar.cmd=arm-none-eabi-ar
 compiler.ar.flags=rcs
 compiler.objcopy.cmd=arm-none-eabi-objcopy
 compiler.objcopy.eep.flags=-O ihex -j .eeprom --set-section-flags=.eeprom=alloc,load --no-change-warnings --change-section-lma .eeprom=0
 compiler.elf2hex.flags=-O binary
 compiler.elf2hex.cmd=arm-none-eabi-objcopy
-compiler.ldflags=
+compiler.ldflags={build.flags.ldspecs}
 compiler.size.cmd=arm-none-eabi-size
 compiler.define=-DARDUINO=                            
 
diff --git a/STM32F4/boards.txt b/STM32F4/boards.txt
index baf6f6e03..abc40f02b 100644
--- a/STM32F4/boards.txt
+++ b/STM32F4/boards.txt
@@ -1,6 +1,7 @@
 # 
 
 menu.usb_cfg=USB configuration
+menu.opt=Optimize
 
 ##############################################################
 discovery_f407.name=STM32 Discovery F407
@@ -36,6 +37,35 @@ discovery_f407.menu.usb_cfg.usb_serial=USB serial (CDC)
 discovery_f407.menu.usb_cfg.usb_serial.build.cpu_flags=-DSERIAL_USB
 discovery_f407.menu.usb_cfg.usb_msc=USB Mass Storage (MSC)
 discovery_f407.menu.usb_cfg.usb_msc.build.cpu_flags=-DUSB_MSC
+
+#-- Optimizations
+discovery_f407.menu.opt.osstd=Smallest (default)
+discovery_f407.menu.opt.osstd.build.flags.optimize=-Os
+discovery_f407.menu.opt.osstd.build.flags.ldspecs=
+discovery_f407.menu.opt.oslto=Smallest Code with LTO
+discovery_f407.menu.opt.oslto.build.flags.optimize=-Os -flto
+discovery_f407.menu.opt.oslto.build.flags.ldspecs=-flto
+discovery_f407.menu.opt.o1std=Fast (-O1)
+discovery_f407.menu.opt.o1std.build.flags.optimize=-O1
+discovery_f407.menu.opt.o1std.build.flags.ldspecs=
+discovery_f407.menu.opt.o1lto=Fast (-O1) with LTO
+discovery_f407.menu.opt.o1lto.build.flags.optimize=-O1 -flto
+discovery_f407.menu.opt.o1lto.build.flags.ldspecs=-flto
+discovery_f407.menu.opt.o2std=Faster (-O2)
+discovery_f407.menu.opt.o2std.build.flags.optimize=-O2
+discovery_f407.menu.opt.o2std.build.flags.ldspecs=
+discovery_f407.menu.opt.o2lto=Faster (-O2) with LTO
+discovery_f407.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+discovery_f407.menu.opt.o2lto.build.flags.ldspecs=-flto
+discovery_f407.menu.opt.o3std=Fastest (-O3)
+discovery_f407.menu.opt.o3std.build.flags.optimize=-O3
+discovery_f407.menu.opt.o3std.build.flags.ldspecs=
+discovery_f407.menu.opt.o3lto=Fastest (-O3) with LTO
+discovery_f407.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+discovery_f407.menu.opt.o3lto.build.flags.ldspecs=-flto
+discovery_f407.menu.opt.ogstd=Debug (-g)
+discovery_f407.menu.opt.ogstd.build.flags.optimize=-Og
+discovery_f407.menu.opt.ogstd.build.flags.ldspecs=
 ##############################################################
 generic_f407v.name=Generic STM32F407V series
 
@@ -72,6 +102,34 @@ generic_f407v.menu.usb_cfg.usb_serial.build.cpu_flags=-DSERIAL_USB
 generic_f407v.menu.usb_cfg.usb_msc=USB Mass Storage (MSC)
 generic_f407v.menu.usb_cfg.usb_msc.build.cpu_flags=-DUSB_MSC
 
+#-- Optimizations
+generic_f407v.menu.opt.osstd=Smallest (default)
+generic_f407v.menu.opt.osstd.build.flags.optimize=-Os
+generic_f407v.menu.opt.osstd.build.flags.ldspecs=
+generic_f407v.menu.opt.oslto=Smallest Code with LTO
+generic_f407v.menu.opt.oslto.build.flags.optimize=-Os -flto
+generic_f407v.menu.opt.oslto.build.flags.ldspecs=-flto
+generic_f407v.menu.opt.o1std=Fast (-O1)
+generic_f407v.menu.opt.o1std.build.flags.optimize=-O1
+generic_f407v.menu.opt.o1std.build.flags.ldspecs=
+generic_f407v.menu.opt.o1lto=Fast (-O1) with LTO
+generic_f407v.menu.opt.o1lto.build.flags.optimize=-O1 -flto
+generic_f407v.menu.opt.o1lto.build.flags.ldspecs=-flto
+generic_f407v.menu.opt.o2std=Faster (-O2)
+generic_f407v.menu.opt.o2std.build.flags.optimize=-O2
+generic_f407v.menu.opt.o2std.build.flags.ldspecs=
+generic_f407v.menu.opt.o2lto=Faster (-O2) with LTO
+generic_f407v.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+generic_f407v.menu.opt.o2lto.build.flags.ldspecs=-flto
+generic_f407v.menu.opt.o3std=Fastest (-O3)
+generic_f407v.menu.opt.o3std.build.flags.optimize=-O3
+generic_f407v.menu.opt.o3std.build.flags.ldspecs=
+generic_f407v.menu.opt.o3lto=Fastest (-O3) with LTO
+generic_f407v.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+generic_f407v.menu.opt.o3lto.build.flags.ldspecs=-flto
+generic_f407v.menu.opt.ogstd=Debug (-g)
+generic_f407v.menu.opt.ogstd.build.flags.optimize=-Og
+generic_f407v.menu.opt.ogstd.build.flags.ldspecs=
 ##############################################################
 stm32f4stamp.name=STM32F4Stamp F405
 
@@ -107,6 +165,35 @@ stm32f4stamp.menu.usb_cfg.usb_serial=USB serial (CDC)
 stm32f4stamp.menu.usb_cfg.usb_serial.build.cpu_flags=-DSERIAL_USB
 stm32f4stamp.menu.usb_cfg.usb_msc=USB Mass Storage (MSC)
 stm32f4stamp.menu.usb_cfg.usb_msc.build.cpu_flags=-DUSB_MSC
+
+#-- Optimizations
+stm32f4stamp.menu.opt.osstd=Smallest (default)
+stm32f4stamp.menu.opt.osstd.build.flags.optimize=-Os
+stm32f4stamp.menu.opt.osstd.build.flags.ldspecs=
+stm32f4stamp.menu.opt.oslto=Smallest Code with LTO
+stm32f4stamp.menu.opt.oslto.build.flags.optimize=-Os -flto
+stm32f4stamp.menu.opt.oslto.build.flags.ldspecs=-flto
+stm32f4stamp.menu.opt.o1std=Fast (-O1)
+stm32f4stamp.menu.opt.o1std.build.flags.optimize=-O1
+stm32f4stamp.menu.opt.o1std.build.flags.ldspecs=
+stm32f4stamp.menu.opt.o1lto=Fast (-O1) with LTO
+stm32f4stamp.menu.opt.o1lto.build.flags.optimize=-O1 -flto
+stm32f4stamp.menu.opt.o1lto.build.flags.ldspecs=-flto
+stm32f4stamp.menu.opt.o2std=Faster (-O2)
+stm32f4stamp.menu.opt.o2std.build.flags.optimize=-O2
+stm32f4stamp.menu.opt.o2std.build.flags.ldspecs=
+stm32f4stamp.menu.opt.o2lto=Faster (-O2) with LTO
+stm32f4stamp.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+stm32f4stamp.menu.opt.o2lto.build.flags.ldspecs=-flto
+stm32f4stamp.menu.opt.o3std=Fastest (-O3)
+stm32f4stamp.menu.opt.o3std.build.flags.optimize=-O3
+stm32f4stamp.menu.opt.o3std.build.flags.ldspecs=
+stm32f4stamp.menu.opt.o3lto=Fastest (-O3) with LTO
+stm32f4stamp.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+stm32f4stamp.menu.opt.o3lto.build.flags.ldspecs=-flto
+stm32f4stamp.menu.opt.ogstd=Debug (-g)
+stm32f4stamp.menu.opt.ogstd.build.flags.optimize=-Og
+stm32f4stamp.menu.opt.ogstd.build.flags.ldspecs=
 ##############################################################
 netduino2plus.name=Netduino2 F405
 
@@ -142,5 +229,34 @@ netduino2plus.menu.usb_cfg.usb_serial=USB serial (CDC)
 netduino2plus.menu.usb_cfg.usb_serial.build.cpu_flags=-DSERIAL_USB
 netduino2plus.menu.usb_cfg.usb_msc=USB Mass Storage (MSC)
 netduino2plus.menu.usb_cfg.usb_msc.build.cpu_flags=-DUSB_MSC
+
+#-- Optimizations
+netduino2plus.menu.opt.osstd=Smallest (default)
+netduino2plus.menu.opt.osstd.build.flags.optimize=-Os
+netduino2plus.menu.opt.osstd.build.flags.ldspecs=
+netduino2plus.menu.opt.oslto=Smallest Code with LTO
+netduino2plus.menu.opt.oslto.build.flags.optimize=-Os -flto
+netduino2plus.menu.opt.oslto.build.flags.ldspecs=-flto
+netduino2plus.menu.opt.o1std=Fast (-O1)
+netduino2plus.menu.opt.o1std.build.flags.optimize=-O1
+netduino2plus.menu.opt.o1std.build.flags.ldspecs=
+netduino2plus.menu.opt.o1lto=Fast (-O1) with LTO
+netduino2plus.menu.opt.o1lto.build.flags.optimize=-O1 -flto
+netduino2plus.menu.opt.o1lto.build.flags.ldspecs=-flto
+netduino2plus.menu.opt.o2std=Faster (-O2)
+netduino2plus.menu.opt.o2std.build.flags.optimize=-O2
+netduino2plus.menu.opt.o2std.build.flags.ldspecs=
+netduino2plus.menu.opt.o2lto=Faster (-O2) with LTO
+netduino2plus.menu.opt.o2lto.build.flags.optimize=-O2 -flto
+netduino2plus.menu.opt.o2lto.build.flags.ldspecs=-flto
+netduino2plus.menu.opt.o3std=Fastest (-O3)
+netduino2plus.menu.opt.o3std.build.flags.optimize=-O3
+netduino2plus.menu.opt.o3std.build.flags.ldspecs=
+netduino2plus.menu.opt.o3lto=Fastest (-O3) with LTO
+netduino2plus.menu.opt.o3lto.build.flags.optimize=-O3 -flto
+netduino2plus.menu.opt.o3lto.build.flags.ldspecs=-flto
+netduino2plus.menu.opt.ogstd=Debug (-g)
+netduino2plus.menu.opt.ogstd.build.flags.optimize=-Og
+netduino2plus.menu.opt.ogstd.build.flags.ldspecs=
 ##############################################################
 
diff --git a/STM32F4/platform.txt b/STM32F4/platform.txt
index b64fe3eee..92dc1ea9a 100755
--- a/STM32F4/platform.txt
+++ b/STM32F4/platform.txt
@@ -10,20 +10,20 @@ version=0.1.0
 # ----------------------
 compiler.path={runtime.tools.arm-none-eabi-gcc.path}/bin/
 compiler.c.cmd=arm-none-eabi-gcc
-compiler.c.flags=-c -g -Os -Wall -MMD -std=gnu11 -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
+compiler.c.flags=-c -g {build.flags.optimize} -Wall -MMD -std=gnu11 -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
 compiler.c.elf.cmd=arm-none-eabi-g++
-compiler.c.elf.flags=-Os -Wl,--gc-sections
+compiler.c.elf.flags={build.flags.optimize} -Wl,--gc-sections {build.flags.ldspecs}
 compiler.S.cmd=arm-none-eabi-gcc
 compiler.S.flags=-c -g -x assembler-with-cpp -MMD
 compiler.cpp.cmd=arm-none-eabi-g++
-compiler.cpp.flags=-c -g -Os -Wall -MMD -std=gnu++11 -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
+compiler.cpp.flags=-c -g {build.flags.optimize} -Wall -MMD -std=gnu++11 -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
 compiler.ar.cmd=arm-none-eabi-ar
 compiler.ar.flags=rcs
 compiler.objcopy.cmd=arm-none-eabi-objcopy
 compiler.objcopy.eep.flags=-O ihex -j .eeprom --set-section-flags=.eeprom=alloc,load --no-change-warnings --change-section-lma .eeprom=0
 compiler.elf2hex.flags=-O binary
 compiler.elf2hex.cmd=arm-none-eabi-objcopy
-compiler.ldflags=
+compiler.ldflags={build.flags.ldspecs}
 compiler.size.cmd=arm-none-eabi-size
 compiler.define=-DARDUINO=                            
 

From bc41851ce49b2ab669c1ad649387fc8eda8254e6 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Tue, 1 Aug 2017 16:47:39 +1000
Subject: [PATCH 162/307] Changed default Wire (I2C) to use hardware I2C rather
 than bit banged software. The existing software Wire implementation has been
 retained as SoftWare.  Examples have also been updated to include Wire,
 HardWire and Softwire.

---
 STM32F1/libraries/Wire/HardWire.cpp           | 101 -------
 STM32F1/libraries/Wire/HardWire.h             |  78 ------
 STM32F1/libraries/Wire/SoftWire.cpp           | 246 ++++++++++++++++++
 STM32F1/libraries/Wire/SoftWire.h             | 163 ++++++++++++
 STM32F1/libraries/Wire/Wire.cpp               | 229 +++-------------
 STM32F1/libraries/Wire/Wire.h                 | 145 +++--------
 .../i2c_scanner_hardwire.ino}                 |   2 +-
 .../i2c_scanner_softwire.ino                  |  54 ++++
 8 files changed, 537 insertions(+), 481 deletions(-)
 delete mode 100644 STM32F1/libraries/Wire/HardWire.cpp
 delete mode 100644 STM32F1/libraries/Wire/HardWire.h
 create mode 100644 STM32F1/libraries/Wire/SoftWire.cpp
 create mode 100644 STM32F1/libraries/Wire/SoftWire.h
 rename STM32F1/libraries/Wire/examples/{i2c_scanner_hwire/i2c_scanner_hwire.ino => i2c_scanner_hardwire/i2c_scanner_hardwire.ino} (98%)
 create mode 100644 STM32F1/libraries/Wire/examples/i2c_scanner_softwire/i2c_scanner_softwire.ino

diff --git a/STM32F1/libraries/Wire/HardWire.cpp b/STM32F1/libraries/Wire/HardWire.cpp
deleted file mode 100644
index 51af7ad76..000000000
--- a/STM32F1/libraries/Wire/HardWire.cpp
+++ /dev/null
@@ -1,101 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 LeafLabs LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file HardWire.cpp
- * @author Trystan Jones <crenn6977@gmail.com>
- * @brief Wire library, uses the hardware I2C available in the Maple to
- *        interact with I2C slave devices.
- */
-
-/*
- * Library created by crenn to use the new WireBase system and allow Arduino
- * users easy interaction with the I2C Hardware in a familiar method.
- */
-
-#include "HardWire.h"
-
-uint8 HardWire::process(uint8 stop) {
-    int8 res = i2c_master_xfer(sel_hard, &itc_msg, 1, 0);
-    if (res == I2C_ERROR_PROTOCOL) {
-        if (sel_hard->error_flags & I2C_SR1_AF) { /* NACK */
-            res = (sel_hard->error_flags & I2C_SR1_ADDR ? ENACKADDR : 
-                                                          ENACKTRNS);
-        } else if (sel_hard->error_flags & I2C_SR1_OVR) { /* Over/Underrun */
-            res = EDATA;
-        } else { /* Bus or Arbitration error */
-            res = EOTHER;
-        }
-        i2c_disable(sel_hard);
-        i2c_master_enable(sel_hard, (I2C_BUS_RESET | dev_flags));
-    }
-    return res;
-}
-
-uint8 HardWire::process(){
-	return process(true);
-}
-
-// TODO: Add in Error Handling if devsel is out of range for other Maples
-HardWire::HardWire(uint8 dev_sel, uint8 flags) {
-    if (dev_sel == 1) {
-        sel_hard = I2C1;
-    } else if (dev_sel == 2) {
-        sel_hard = I2C2;
-    } else {
-        ASSERT(1);
-    }
-    dev_flags = flags;
-}
-
-HardWire::~HardWire() {
-    i2c_disable(sel_hard);
-    sel_hard = 0;
-}
-
-void HardWire::begin(uint8 self_addr) {
-    i2c_master_enable(sel_hard, dev_flags);
-}
-
-void HardWire::end() {
-    i2c_disable(sel_hard);
-    sel_hard = 0;
-}
-
-void HardWire::setClock(uint32_t frequencyHz)
-{
-	switch(frequencyHz)
-	{
-		case 400000:
-			dev_flags |= I2C_FAST_MODE;// set FAST_MODE bit
-			break;
-		case 100000:
-		default:
-			dev_flags &= ~I2C_FAST_MODE;// clear FAST_MODE bit
-			break;
-	}
-	
-}
diff --git a/STM32F1/libraries/Wire/HardWire.h b/STM32F1/libraries/Wire/HardWire.h
deleted file mode 100644
index 4d49e1a28..000000000
--- a/STM32F1/libraries/Wire/HardWire.h
+++ /dev/null
@@ -1,78 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 LeafLabs LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file HardWire.h
- * @author Trystan Jones <crenn6977@gmail.com>
- * @brief Wire library, uses the hardware I2C available in the Maple to
- *        interact with I2C slave devices.
- */
-
-/*
- * Library created by crenn to use the new WireBase system and allow Arduino
- * users easy interaction with the I2C Hardware in a familiar method.
- */
-
-#ifndef _HARDWIRE_H_
-#define _HARDWIRE_H_
-
-#include "WireBase.h"
-#include "wirish.h"
-#include <libmaple/i2c.h>
-
-class HardWire : public WireBase {
-private:
-    i2c_dev* sel_hard;
-    uint8    dev_flags;
-protected:
-    /*
-     * Processes the incoming I2C message defined by WireBase to the
-     * hardware. If an error occured, restart the I2C device.
-     */
-    uint8 process(uint8);
-    uint8 process();
-public:
-    /*
-     * Check if devsel is within range and enable selected I2C interface with
-     * passed flags
-     */
-    HardWire(uint8, uint8 = 0);
-	
-	/*
-	 * Shuts down (disables) the hardware I2C
-	 */
-	void end();
-
-	void setClock(uint32_t frequencyHz);
-    /*
-     * Disables the I2C device and remove the device address.
-     */
-    ~HardWire();
-
-    void begin(uint8 = 0x00);
-};
-extern HardWire HWire;
-#endif // _HARDWIRE_H_
diff --git a/STM32F1/libraries/Wire/SoftWire.cpp b/STM32F1/libraries/Wire/SoftWire.cpp
new file mode 100644
index 000000000..781bb976f
--- /dev/null
+++ b/STM32F1/libraries/Wire/SoftWire.cpp
@@ -0,0 +1,246 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 LeafLabs LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file Wire.cpp
+ * @author Trystan Jones <crenn6977@gmail.com>
+ * @brief Wire library, uses the WireBase to create the primary interface
+ *        while keeping low level interactions invisible to the user.
+ */
+
+/*
+ * Library updated by crenn to follow new Wire system.
+ * Code was derived from the original Wire for maple code by leaflabs and the
+ * modifications by gke and ala42.
+ */
+ /*
+  * Updated by Roger Clark. 20141111. Fixed issue when process() returned because of missing ACK (often caused by invalid device address being used), caused SCL to be left
+  * LOW so that in the next call to process() , the first clock pulse was not sent, because SCL was LOW when it should have been high.
+  */
+ /*
+  * Updated by Brandon Green. 20172306. Implementing the repeated start functionality.
+  */
+
+#include "SoftWire.h"
+
+#define I2C_WRITE 0
+#define I2C_READ  1
+
+/* low level conventions:
+ * - SDA/SCL idle high (expected high)
+ * - always start with i2c_delay rather than end
+ */
+
+void TwoWire::set_scl(bool state) {
+    I2C_DELAY(this->i2c_delay);
+
+	gpio_write_bit(sclDevice,sclBit, state);
+//    digitalWrite(this->scl_pin,state);
+    //Allow for clock stretching - dangerous currently
+    if (state == HIGH) {
+        while(digitalRead(this->scl_pin) == 0);
+    }
+}
+
+void TwoWire::set_sda(bool state) {
+	I2C_DELAY(this->i2c_delay);
+	gpio_write_bit(sdaDevice,sdaBit, state);
+    //digitalWrite(this->sda_pin, state);
+}
+
+void TwoWire::i2c_start() {
+    set_sda(LOW);
+    set_scl(LOW);
+}
+
+void TwoWire::i2c_stop() {
+    set_sda(LOW);
+    set_scl(HIGH);
+    set_sda(HIGH);
+}
+
+void TwoWire::i2c_repeated_start() {
+    set_sda(HIGH);
+    set_scl(HIGH);
+    set_sda(LOW);
+}
+
+bool TwoWire::i2c_get_ack() {
+    set_scl(LOW);
+    set_sda(HIGH);
+    set_scl(HIGH);
+
+    bool ret = !digitalRead(this->sda_pin);
+    set_scl(LOW);
+    return ret;
+}
+
+void TwoWire::i2c_send_ack() {
+    set_sda(LOW);
+    set_scl(HIGH);
+    set_scl(LOW);
+}
+
+void TwoWire::i2c_send_nack() {
+    set_sda(HIGH);
+    set_scl(HIGH);
+    set_scl(LOW);
+}
+
+uint8 TwoWire::i2c_shift_in() {
+    uint8 data = 0;
+    set_sda(HIGH);
+
+    int i;
+    for (i = 0; i < 8; i++) {
+        set_scl(HIGH);
+        data |= digitalRead(this->sda_pin) << (7-i);
+        set_scl(LOW);
+    }
+
+    return data;
+}
+
+void TwoWire::i2c_shift_out(uint8 val) {
+    int i;
+    for (i = 0; i < 8; i++) {
+        set_sda(!!(val & (1 << (7 - i)) ) );
+        set_scl(HIGH);
+        set_scl(LOW);
+    }
+}
+
+//process needs to be updated for repeated start.
+uint8 TwoWire::process(uint8 stop) {
+    itc_msg.xferred = 0;
+
+    uint8 sla_addr = (itc_msg.addr << 1);
+    if (itc_msg.flags == I2C_MSG_READ) {
+        sla_addr |= I2C_READ;
+    }
+    i2c_start();
+    // shift out the address we're transmitting to
+    i2c_shift_out(sla_addr);
+    if (!i2c_get_ack()) 
+	{
+		i2c_stop();// Roger Clark. 20141110 added to set clock high again, as it will be left in a low state otherwise
+        return ENACKADDR;
+    }
+    // Recieving
+    if (itc_msg.flags == I2C_MSG_READ) {
+        while (itc_msg.xferred < itc_msg.length) {
+            itc_msg.data[itc_msg.xferred++] = i2c_shift_in();
+            if (itc_msg.xferred < itc_msg.length) 
+			{
+                i2c_send_ack();
+            } 
+			else 
+			{
+                i2c_send_nack();
+            }
+        }
+    }
+    // Sending
+    else {
+        for (uint8 i = 0; i < itc_msg.length; i++) {
+            i2c_shift_out(itc_msg.data[i]);
+            if (!i2c_get_ack()) 
+			{
+				i2c_stop();// Roger Clark. 20141110 added to set clock high again, as it will be left in a low state otherwise
+                return ENACKTRNS;
+            }
+            itc_msg.xferred++;
+        }
+    }
+    if(stop == true)
+		i2c_stop();
+    else i2c_repeated_start();
+	
+    return SUCCESS;
+}
+
+// For compatibility with legacy code
+uint8 TwoWire::process(){
+	return process(true);
+}
+
+// TODO: Add in Error Handling if pins is out of range for other Maples
+// TODO: Make delays more capable
+TwoWire::TwoWire(uint8 scl, uint8 sda, uint8 delay) : i2c_delay(delay) {
+    this->scl_pin=scl;
+    this->sda_pin=sda;
+}
+
+void TwoWire::begin(uint8 self_addr) {
+    tx_buf_idx = 0;
+    tx_buf_overflow = false;
+    rx_buf_idx = 0;
+    rx_buf_len = 0;
+    pinMode(this->scl_pin, OUTPUT_OPEN_DRAIN);
+    pinMode(this->sda_pin, OUTPUT_OPEN_DRAIN);
+	
+	sclDevice = PIN_MAP[this->scl_pin].gpio_device;
+	sclBit = PIN_MAP[this->scl_pin].gpio_bit;	
+	sdaDevice = PIN_MAP[this->sda_pin].gpio_device;
+	sdaBit = PIN_MAP[this->sda_pin].gpio_bit;		
+    set_scl(HIGH);
+    set_sda(HIGH);
+}
+
+void TwoWire::end()
+{
+	if (this->scl_pin)
+	{
+		pinMode(this->scl_pin, INPUT);
+	}
+	if (this->sda_pin)
+	{
+		pinMode(this->sda_pin, INPUT);
+	}
+}
+
+void TwoWire::setClock(uint32_t frequencyHz)
+{
+	switch(frequencyHz)
+	{
+		case 400000:
+			i2c_delay = SOFT_FAST;
+			break;
+		case 100000:
+		default:
+			i2c_delay = SOFT_STANDARD;
+			break;
+	}
+}
+
+TwoWire::~TwoWire() {
+    this->scl_pin=0;
+    this->sda_pin=0;
+}
+
+// Declare the instance that the users of the library can use
+//TwoWire Wire(SCL, SDA, SOFT_STANDARD);
+//TwoWire Wire(PB6, PB7, SOFT_FAST);
diff --git a/STM32F1/libraries/Wire/SoftWire.h b/STM32F1/libraries/Wire/SoftWire.h
new file mode 100644
index 000000000..0804c0f11
--- /dev/null
+++ b/STM32F1/libraries/Wire/SoftWire.h
@@ -0,0 +1,163 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 LeafLabs LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file Wire.h
+ * @author Trystan Jones <crenn6977@gmail.com>
+ * @brief Wire library, uses the WireBase to create the primary interface
+ *        while keeping low level interactions invisible to the user.
+ */
+
+/*
+ * Library updated by crenn to follow new Wire system.
+ * Code was derived from the original Wire for maple code by leaflabs and the
+ * modifications by gke and ala42.
+ */
+
+#ifndef _SOFTWIRE_H_
+#define _SOFTWIRE_H_
+
+#include "WireBase.h"
+#include "wirish.h"
+
+/*
+ * On the Maple, let the default pins be in the same location as the Arduino
+ * pins
+ */
+#define SDA PB7
+#define SCL PB6
+
+#define SOFT_STANDARD 19
+#define SOFT_FAST 0
+
+
+//#define I2C_DELAY(x) {uint32 time=micros(); while(time>(micros()+x));}
+#define I2C_DELAY(x) do{for(int i=0;i<x;i++) {asm volatile("nop");}}while(0)
+
+#define BUFFER_LENGTH 32
+
+
+class TwoWire : public WireBase {
+ public:
+    uint8 		i2c_delay;
+    uint8       scl_pin;
+    uint8       sda_pin;
+
+    /*
+     * Sets the SCL line to HIGH/LOW and allow for clock stretching by slave
+     * devices
+     */
+    void set_scl(bool);
+
+    /*
+     * Sets the SDA line to HIGH/LOW
+     */
+    void set_sda(bool);
+
+    /*
+     * Creates a Start condition on the bus
+     */
+    void i2c_start();
+
+    /*
+     * Creates a Stop condition on the bus
+     */
+    void  i2c_stop();
+    
+    /*
+     * Created a Repeated Start condition on the bus
+     */
+    void i2c_repeated_start();
+    
+    /*
+     * Gets an ACK condition from a slave device on the bus
+     */
+    bool i2c_get_ack();
+
+    /*
+     * Creates a ACK condition on the bus
+     */
+    void i2c_send_ack();
+
+    /*
+     * Creates a NACK condition on the bus
+     */
+    void i2c_send_nack();
+
+    /*
+     * Shifts in the data through SDA and clocks SCL for the slave device
+     */
+    uint8 i2c_shift_in();
+
+    /*
+     * Shifts out the data through SDA and clocks SCL for the slave device
+     */
+    void i2c_shift_out(uint8);
+	
+	
+
+	
+ protected:
+    /*
+     * Processes the incoming I2C message defined by WireBase
+     */
+    uint8 process(uint8);
+    uint8 process();
+ private:
+	gpio_dev 	*sdaDevice;
+	uint8 		sdaBit;
+	gpio_dev 	*sclDevice;
+	uint8 		sclBit;	
+ public:
+    /*
+     * Accept pin numbers for SCL and SDA lines. Set the delay needed
+     * to create the timing for I2C's Standard Mode and Fast Mode.
+     */
+    TwoWire(uint8 scl=SCL, uint8 sda=SDA, uint8 delay=SOFT_STANDARD);
+
+    /*
+     * Sets pins SDA and SCL to OUPTUT_OPEN_DRAIN, joining I2C bus as
+     * master. This function overwrites the default behaviour of
+     * .begin(uint8) in WireBase
+     */
+    void begin(uint8 = 0x00);
+	
+	void setClock(uint32_t frequencyHz);
+
+    /*
+     * Sets pins SDA and SCL to INPUT
+     */
+	void end();	
+	
+    /*
+     * If object is destroyed, set pin numbers to 0.
+     */
+    ~TwoWire();
+};
+
+//extern TwoWire Wire;
+
+#endif // _WIRE_H_
diff --git a/STM32F1/libraries/Wire/Wire.cpp b/STM32F1/libraries/Wire/Wire.cpp
index 712adf45b..d8252c1c0 100644
--- a/STM32F1/libraries/Wire/Wire.cpp
+++ b/STM32F1/libraries/Wire/Wire.cpp
@@ -25,222 +25,79 @@
  *****************************************************************************/
 
 /**
- * @file Wire.cpp
+ * @file HardWire.cpp
  * @author Trystan Jones <crenn6977@gmail.com>
- * @brief Wire library, uses the WireBase to create the primary interface
- *        while keeping low level interactions invisible to the user.
+ * @brief Wire library, uses the hardware I2C available in the Maple to
+ *        interact with I2C slave devices.
  */
 
 /*
- * Library updated by crenn to follow new Wire system.
- * Code was derived from the original Wire for maple code by leaflabs and the
- * modifications by gke and ala42.
+ * Library created by crenn to use the new WireBase system and allow Arduino
+ * users easy interaction with the I2C Hardware in a familiar method.
  */
- /*
-  * Updated by Roger Clark. 20141111. Fixed issue when process() returned because of missing ACK (often caused by invalid device address being used), caused SCL to be left
-  * LOW so that in the next call to process() , the first clock pulse was not sent, because SCL was LOW when it should have been high.
-  */
- /*
-  * Updated by Brandon Green. 20172306. Implementing the repeated start functionality.
-  */
 
 #include "Wire.h"
 
-#define I2C_WRITE 0
-#define I2C_READ  1
-
-/* low level conventions:
- * - SDA/SCL idle high (expected high)
- * - always start with i2c_delay rather than end
- */
-
-void TwoWire::set_scl(bool state) {
-    I2C_DELAY(this->i2c_delay);
-
-	gpio_write_bit(sclDevice,sclBit, state);
-//    digitalWrite(this->scl_pin,state);
-    //Allow for clock stretching - dangerous currently
-    if (state == HIGH) {
-        while(digitalRead(this->scl_pin) == 0);
+uint8 HardWire::process(uint8 stop) {
+    int8 res = i2c_master_xfer(sel_hard, &itc_msg, 1, 0);
+    if (res == I2C_ERROR_PROTOCOL) {
+        if (sel_hard->error_flags & I2C_SR1_AF) { /* NACK */
+            res = (sel_hard->error_flags & I2C_SR1_ADDR ? ENACKADDR : 
+                                                          ENACKTRNS);
+        } else if (sel_hard->error_flags & I2C_SR1_OVR) { /* Over/Underrun */
+            res = EDATA;
+        } else { /* Bus or Arbitration error */
+            res = EOTHER;
+        }
+        i2c_disable(sel_hard);
+        i2c_master_enable(sel_hard, (I2C_BUS_RESET | dev_flags));
     }
+    return res;
 }
 
-void TwoWire::set_sda(bool state) {
-	I2C_DELAY(this->i2c_delay);
-	gpio_write_bit(sdaDevice,sdaBit, state);
-    //digitalWrite(this->sda_pin, state);
-}
-
-void TwoWire::i2c_start() {
-    set_sda(LOW);
-    set_scl(LOW);
-}
-
-void TwoWire::i2c_stop() {
-    set_sda(LOW);
-    set_scl(HIGH);
-    set_sda(HIGH);
-}
-
-void TwoWire::i2c_repeated_start() {
-    set_sda(HIGH);
-    set_scl(HIGH);
-    set_sda(LOW);
-}
-
-bool TwoWire::i2c_get_ack() {
-    set_scl(LOW);
-    set_sda(HIGH);
-    set_scl(HIGH);
-
-    bool ret = !digitalRead(this->sda_pin);
-    set_scl(LOW);
-    return ret;
-}
-
-void TwoWire::i2c_send_ack() {
-    set_sda(LOW);
-    set_scl(HIGH);
-    set_scl(LOW);
-}
-
-void TwoWire::i2c_send_nack() {
-    set_sda(HIGH);
-    set_scl(HIGH);
-    set_scl(LOW);
-}
-
-uint8 TwoWire::i2c_shift_in() {
-    uint8 data = 0;
-    set_sda(HIGH);
-
-    int i;
-    for (i = 0; i < 8; i++) {
-        set_scl(HIGH);
-        data |= digitalRead(this->sda_pin) << (7-i);
-        set_scl(LOW);
-    }
-
-    return data;
-}
-
-void TwoWire::i2c_shift_out(uint8 val) {
-    int i;
-    for (i = 0; i < 8; i++) {
-        set_sda(!!(val & (1 << (7 - i)) ) );
-        set_scl(HIGH);
-        set_scl(LOW);
-    }
+uint8 HardWire::process(){
+	return process(true);
 }
 
-//process needs to be updated for repeated start.
-uint8 TwoWire::process(uint8 stop) {
-    itc_msg.xferred = 0;
-
-    uint8 sla_addr = (itc_msg.addr << 1);
-    if (itc_msg.flags == I2C_MSG_READ) {
-        sla_addr |= I2C_READ;
-    }
-    i2c_start();
-    // shift out the address we're transmitting to
-    i2c_shift_out(sla_addr);
-    if (!i2c_get_ack()) 
-	{
-		i2c_stop();// Roger Clark. 20141110 added to set clock high again, as it will be left in a low state otherwise
-        return ENACKADDR;
+// TODO: Add in Error Handling if devsel is out of range for other Maples
+HardWire::HardWire(uint8 dev_sel, uint8 flags) {
+    if (dev_sel == 1) {
+        sel_hard = I2C1;
+    } else if (dev_sel == 2) {
+        sel_hard = I2C2;
+    } else {
+        ASSERT(1);
     }
-    // Recieving
-    if (itc_msg.flags == I2C_MSG_READ) {
-        while (itc_msg.xferred < itc_msg.length) {
-            itc_msg.data[itc_msg.xferred++] = i2c_shift_in();
-            if (itc_msg.xferred < itc_msg.length) 
-			{
-                i2c_send_ack();
-            } 
-			else 
-			{
-                i2c_send_nack();
-            }
-        }
-    }
-    // Sending
-    else {
-        for (uint8 i = 0; i < itc_msg.length; i++) {
-            i2c_shift_out(itc_msg.data[i]);
-            if (!i2c_get_ack()) 
-			{
-				i2c_stop();// Roger Clark. 20141110 added to set clock high again, as it will be left in a low state otherwise
-                return ENACKTRNS;
-            }
-            itc_msg.xferred++;
-        }
-    }
-    if(stop == true)
-		i2c_stop();
-    else i2c_repeated_start();
-	
-    return SUCCESS;
+    dev_flags = flags;
 }
 
-// For compatibility with legacy code
-uint8 TwoWire::process(){
-	return process(true);
+HardWire::~HardWire() {
+    i2c_disable(sel_hard);
+    sel_hard = 0;
 }
 
-// TODO: Add in Error Handling if pins is out of range for other Maples
-// TODO: Make delays more capable
-TwoWire::TwoWire(uint8 scl, uint8 sda, uint8 delay) : i2c_delay(delay) {
-    this->scl_pin=scl;
-    this->sda_pin=sda;
+void HardWire::begin(uint8 self_addr) {
+    i2c_master_enable(sel_hard, dev_flags);
 }
 
-void TwoWire::begin(uint8 self_addr) {
-    tx_buf_idx = 0;
-    tx_buf_overflow = false;
-    rx_buf_idx = 0;
-    rx_buf_len = 0;
-    pinMode(this->scl_pin, OUTPUT_OPEN_DRAIN);
-    pinMode(this->sda_pin, OUTPUT_OPEN_DRAIN);
-	
-	sclDevice = PIN_MAP[this->scl_pin].gpio_device;
-	sclBit = PIN_MAP[this->scl_pin].gpio_bit;	
-	sdaDevice = PIN_MAP[this->sda_pin].gpio_device;
-	sdaBit = PIN_MAP[this->sda_pin].gpio_bit;		
-    set_scl(HIGH);
-    set_sda(HIGH);
+void HardWire::end() {
+    i2c_disable(sel_hard);
+    sel_hard = 0;
 }
 
-void TwoWire::end()
-{
-	if (this->scl_pin)
-	{
-		pinMode(this->scl_pin, INPUT);
-	}
-	if (this->sda_pin)
-	{
-		pinMode(this->sda_pin, INPUT);
-	}
-}
-
-void TwoWire::setClock(uint32_t frequencyHz)
+void HardWire::setClock(uint32_t frequencyHz)
 {
 	switch(frequencyHz)
 	{
 		case 400000:
-			i2c_delay = SOFT_FAST;
+			dev_flags |= I2C_FAST_MODE;// set FAST_MODE bit
 			break;
 		case 100000:
 		default:
-			i2c_delay = SOFT_STANDARD;
+			dev_flags &= ~I2C_FAST_MODE;// clear FAST_MODE bit
 			break;
 	}
+	
 }
 
-TwoWire::~TwoWire() {
-    this->scl_pin=0;
-    this->sda_pin=0;
-}
-
-// Declare the instance that the users of the library can use
-TwoWire Wire(SCL, SDA, SOFT_STANDARD);
-//TwoWire Wire(PB6, PB7, SOFT_STANDARD);
+HardWire Wire(1, I2C_FAST_MODE);;
diff --git a/STM32F1/libraries/Wire/Wire.h b/STM32F1/libraries/Wire/Wire.h
index 8fbddaae9..88d4a1bd4 100644
--- a/STM32F1/libraries/Wire/Wire.h
+++ b/STM32F1/libraries/Wire/Wire.h
@@ -25,139 +25,54 @@
  *****************************************************************************/
 
 /**
- * @file Wire.h
+ * @file HardWire.h
  * @author Trystan Jones <crenn6977@gmail.com>
- * @brief Wire library, uses the WireBase to create the primary interface
- *        while keeping low level interactions invisible to the user.
+ * @brief Wire library, uses the hardware I2C available in the Maple to
+ *        interact with I2C slave devices.
  */
 
 /*
- * Library updated by crenn to follow new Wire system.
- * Code was derived from the original Wire for maple code by leaflabs and the
- * modifications by gke and ala42.
+ * Library created by crenn to use the new WireBase system and allow Arduino
+ * users easy interaction with the I2C Hardware in a familiar method.
  */
 
-#ifndef _WIRE_H_
-#define _WIRE_H_
+#ifndef _HARDWIRE_H_
+#define _HARDWIRE_H_
 
 #include "WireBase.h"
 #include "wirish.h"
+#include <libmaple/i2c.h>
 
-/*
- * On the Maple, let the default pins be in the same location as the Arduino
- * pins
- */
-#define SDA PB7
-#define SCL PB6
-
-#define SOFT_STANDARD 19
-#define SOFT_FAST 0
-
-
-//#define I2C_DELAY(x) {uint32 time=micros(); while(time>(micros()+x));}
-#define I2C_DELAY(x) do{for(int i=0;i<x;i++) {asm volatile("nop");}}while(0)
-
-#define BUFFER_LENGTH 32
-
-
-class TwoWire : public WireBase {
- public:
-    uint8 		i2c_delay;
-    uint8       scl_pin;
-    uint8       sda_pin;
-
+class HardWire : public WireBase {
+private:
+    i2c_dev* sel_hard;
+    uint8    dev_flags;
+protected:
     /*
-     * Sets the SCL line to HIGH/LOW and allow for clock stretching by slave
-     * devices
-     */
-    void set_scl(bool);
-
-    /*
-     * Sets the SDA line to HIGH/LOW
-     */
-    void set_sda(bool);
-
-    /*
-     * Creates a Start condition on the bus
-     */
-    void i2c_start();
-
-    /*
-     * Creates a Stop condition on the bus
-     */
-    void  i2c_stop();
-    
-    /*
-     * Created a Repeated Start condition on the bus
-     */
-    void i2c_repeated_start();
-    
-    /*
-     * Gets an ACK condition from a slave device on the bus
-     */
-    bool i2c_get_ack();
-
-    /*
-     * Creates a ACK condition on the bus
-     */
-    void i2c_send_ack();
-
-    /*
-     * Creates a NACK condition on the bus
-     */
-    void i2c_send_nack();
-
-    /*
-     * Shifts in the data through SDA and clocks SCL for the slave device
-     */
-    uint8 i2c_shift_in();
-
-    /*
-     * Shifts out the data through SDA and clocks SCL for the slave device
-     */
-    void i2c_shift_out(uint8);
-	
-	
-
-	
- protected:
-    /*
-     * Processes the incoming I2C message defined by WireBase
+     * Processes the incoming I2C message defined by WireBase to the
+     * hardware. If an error occured, restart the I2C device.
      */
     uint8 process(uint8);
     uint8 process();
- private:
-	gpio_dev 	*sdaDevice;
-	uint8 		sdaBit;
-	gpio_dev 	*sclDevice;
-	uint8 		sclBit;	
- public:
+public:
     /*
-     * Accept pin numbers for SCL and SDA lines. Set the delay needed
-     * to create the timing for I2C's Standard Mode and Fast Mode.
+     * Check if devsel is within range and enable selected I2C interface with
+     * passed flags
      */
-    TwoWire(uint8 scl=SCL, uint8 sda=SDA, uint8 delay=SOFT_STANDARD);
-
-    /*
-     * Sets pins SDA and SCL to OUPTUT_OPEN_DRAIN, joining I2C bus as
-     * master. This function overwrites the default behaviour of
-     * .begin(uint8) in WireBase
-     */
-    void begin(uint8 = 0x00);
+    HardWire(uint8, uint8 = 0);
 	
-	void setClock(uint32_t frequencyHz);
+	/*
+	 * Shuts down (disables) the hardware I2C
+	 */
+	void end();
 
+	void setClock(uint32_t frequencyHz);
     /*
-     * Sets pins SDA and SCL to INPUT
-     */
-	void end();	
-	
-    /*
-     * If object is destroyed, set pin numbers to 0.
+     * Disables the I2C device and remove the device address.
      */
-    ~TwoWire();
-};
+    ~HardWire();
 
-extern TwoWire Wire;
-
-#endif // _WIRE_H_
+    void begin(uint8 = 0x00);
+};
+extern HardWire Wire;
+#endif // _HARDWIRE_H_
diff --git a/STM32F1/libraries/Wire/examples/i2c_scanner_hwire/i2c_scanner_hwire.ino b/STM32F1/libraries/Wire/examples/i2c_scanner_hardwire/i2c_scanner_hardwire.ino
similarity index 98%
rename from STM32F1/libraries/Wire/examples/i2c_scanner_hwire/i2c_scanner_hwire.ino
rename to STM32F1/libraries/Wire/examples/i2c_scanner_hardwire/i2c_scanner_hardwire.ino
index 745cae6a7..d2b3bd430 100644
--- a/STM32F1/libraries/Wire/examples/i2c_scanner_hwire/i2c_scanner_hwire.ino
+++ b/STM32F1/libraries/Wire/examples/i2c_scanner_hardwire/i2c_scanner_hardwire.ino
@@ -26,7 +26,7 @@
 // Devices with higher bit address might not be seen properly.
 //
 
-#include <HardWire.h>
+#include <Wire.h>
 
 HardWire HWire(1, I2C_FAST_MODE); // I2c1
 
diff --git a/STM32F1/libraries/Wire/examples/i2c_scanner_softwire/i2c_scanner_softwire.ino b/STM32F1/libraries/Wire/examples/i2c_scanner_softwire/i2c_scanner_softwire.ino
new file mode 100644
index 000000000..0b4580a1e
--- /dev/null
+++ b/STM32F1/libraries/Wire/examples/i2c_scanner_softwire/i2c_scanner_softwire.ino
@@ -0,0 +1,54 @@
+// --------------------------------------
+// i2c_scanner
+//
+//
+
+#include <SoftWire.h>
+
+TwoWire SWire(PB6, PB7, SOFT_FAST);
+
+
+void setup() {
+  Serial.begin(115200);
+  SWire.begin();
+  Serial.println("\nSoftware I2C.. Scanner");
+}
+
+
+void loop() {
+  byte error, address;
+  int nDevices;
+
+  Serial.println("Scanning...");
+
+  nDevices = 0;
+  for(address = 1; address < 127; address++) {
+    // The i2c_scanner uses the return value of
+    // the Write.endTransmisstion to see if
+    // a device did acknowledge to the address.
+
+    SWire.beginTransmission(address);
+    error = SWire.endTransmission();
+    
+    if (error == 0) {
+      Serial.print("I2C device found at address 0x");
+      if (address < 16) 
+        Serial.print("0");
+      Serial.println(address, HEX);
+
+      nDevices++;
+    }
+    else if (error == 4) {
+      Serial.print("Unknown error at address 0x");
+      if (address < 16) 
+        Serial.print("0");
+      Serial.println(address, HEX);
+    }    
+  }
+  if (nDevices == 0)
+    Serial.println("No I2C devices found");
+  else
+    Serial.println("done");
+
+  delay(5000);           // wait 5 seconds for next scan
+}
\ No newline at end of file

From 859a447ecfb74a4a2b173d05e8e956e23a8aa05a Mon Sep 17 00:00:00 2001
From: Cristi Marius Tiutiu <mtiutiu@gmail.com>
Date: Tue, 1 Aug 2017 10:35:47 +0300
Subject: [PATCH 163/307] linux fix for gd32 variant in boards.txt

---
 STM32F1/boards.txt | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/STM32F1/boards.txt b/STM32F1/boards.txt
index 9cef20747..b3eac901f 100644
--- a/STM32F1/boards.txt
+++ b/STM32F1/boards.txt
@@ -931,7 +931,7 @@ hytiny-stm32f103t.menu.opt.ogstd.build.flags.ldspecs=
 ###################### Generic GD32F103C  ########################################
 
 genericGD32F103C.name=Generic GD32F103C series
-genericGD32F103C.build.variant=generic_GD32f103c
+genericGD32F103C.build.variant=generic_gd32f103c
 genericGD32F103C.build.vect=VECT_TAB_ADDR=0x8000000
 genericGD32F103C.build.core=maple
 genericGD32F103C.build.board=GENERIC_GD32F103C
@@ -1086,4 +1086,4 @@ STM32VLD.menu.opt.o3lto.build.flags.ldspecs=-flto
 STM32VLD.menu.opt.ogstd.build.flags.optimize=-Og
 STM32VLD.menu.opt.ogstd.build.flags.ldspecs=
 
-################################################################################
\ No newline at end of file
+################################################################################

From 0a9d06b5e5398588df747dcc8c5a5399cf0b157b Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Thu, 3 Aug 2017 09:28:14 +1000
Subject: [PATCH 164/307] Fix typo in dma.h (thanks to @stevestrong)

---
 STM32F1/system/libmaple/stm32f1/include/series/dma.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/system/libmaple/stm32f1/include/series/dma.h b/STM32F1/system/libmaple/stm32f1/include/series/dma.h
index ff6185795..56e559ba9 100644
--- a/STM32F1/system/libmaple/stm32f1/include/series/dma.h
+++ b/STM32F1/system/libmaple/stm32f1/include/series/dma.h
@@ -152,7 +152,7 @@ typedef struct dma_tube_reg_map {
 
 #define DMA_ISR_TEIF (1 << DMA_ISR_TEIF_BIT)
 #define DMA_ISR_HTIF (1 << DMA_ISR_HTIF_BIT)
-#define DMA_ISR_TCID (1 << DMA_ISR_TCIF_BIT)
+#define DMA_ISR_TCIF (1 << DMA_ISR_TCIF_BIT)
 #define DMA_ISR_GIF  (1 << DMA_ISR_GIF_BIT)
 
 #define DMA_ISR_TEIF7_BIT               27

From 1ea988a57d0d5923967722e4cee092db496892c0 Mon Sep 17 00:00:00 2001
From: victorpv <victor_pv@hotmail.com>
Date: Thu, 3 Aug 2017 11:47:15 -0500
Subject: [PATCH 165/307] Correcting FreeRTOS900 examples

The examples were still including the 821 version of FreeRTOS, so changing them to include the right one.
---
 .../libraries/FreeRTOS900/examples/rtos_blink/rtos_blink.ino    | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/libraries/FreeRTOS900/examples/rtos_blink/rtos_blink.ino b/STM32F1/libraries/FreeRTOS900/examples/rtos_blink/rtos_blink.ino
index a972b6c18..935c6294f 100644
--- a/STM32F1/libraries/FreeRTOS900/examples/rtos_blink/rtos_blink.ino
+++ b/STM32F1/libraries/FreeRTOS900/examples/rtos_blink/rtos_blink.ino
@@ -1,6 +1,6 @@
 //#include <wirish/wirish.h>
 //#include "libraries/FreeRTOS/MapleFreeRTOS.h"
-#include <MapleFreeRTOS821.h>
+#include <MapleFreeRTOS900.h>
 
 static void vLEDFlashTask(void *pvParameters) {
     for (;;) {

From db9a70c74f76195f2a365482475e373a78f25f56 Mon Sep 17 00:00:00 2001
From: victorpv <victor_pv@hotmail.com>
Date: Thu, 3 Aug 2017 11:48:26 -0500
Subject: [PATCH 166/307] Correcting FreeRTOS900 example.

---
 .../examples/rtos_display_blink/rtos_display_blink.ino          | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/libraries/FreeRTOS900/examples/rtos_display_blink/rtos_display_blink.ino b/STM32F1/libraries/FreeRTOS900/examples/rtos_display_blink/rtos_display_blink.ino
index bd6c3e4e0..7d9210050 100644
--- a/STM32F1/libraries/FreeRTOS900/examples/rtos_display_blink/rtos_display_blink.ino
+++ b/STM32F1/libraries/FreeRTOS900/examples/rtos_display_blink/rtos_display_blink.ino
@@ -1,5 +1,5 @@
 #define USE_SEMAPHORE_DMA1
-#include <MapleFreeRTOS821.h>
+#include <MapleFreeRTOS900.h>
 #include <SPI.h>
 #include <Adafruit_GFX.h>
 #include <TFT_ILI9163C.h>

From 8f7a0b6d5a47b70093a6f355f6ecf24e3e189f74 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Fri, 4 Aug 2017 20:34:48 +1000
Subject: [PATCH 167/307] Added pushColors() to ILI9341 library to better
 support the OV7670 camera

---
 .../Adafruit_ILI9341_STM.cpp                    | 17 +++++++++++++++++
 .../Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.h |  1 +
 2 files changed, 18 insertions(+)

diff --git a/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.cpp b/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.cpp
index db57b3e56..766b91034 100644
--- a/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.cpp
+++ b/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.cpp
@@ -386,6 +386,23 @@ void Adafruit_ILI9341_STM::pushColor(uint16_t color) {
   if (hwSPI) spi_end();
 }
 
+void Adafruit_ILI9341_STM::pushColors(void * colorBuffer, uint16_t nr_pixels, uint8_t async)
+{
+  *dcport |=  dcpinmask;
+  *csport &= ~cspinmask;
+
+  if (async==0) 
+  {
+    SPI.dmaSend(colorBuffer, nr_pixels, 1);
+	*csport |= cspinmask;
+  }
+  else
+  {
+    SPI.dmaSendAsync(colorBuffer, nr_pixels, 1);
+  }
+
+}
+
 void Adafruit_ILI9341_STM::drawPixel(int16_t x, int16_t y, uint16_t color) {
 
   if ((x < 0) || (x >= _width) || (y < 0) || (y >= _height)) return;
diff --git a/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.h b/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.h
index 137b7a4b5..7ee395c6c 100644
--- a/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.h
+++ b/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.h
@@ -107,6 +107,7 @@ class Adafruit_ILI9341_STM : public Adafruit_GFX {
   void     begin(void),
            setAddrWindow(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1),
            pushColor(uint16_t color),
+		   pushColors(void * colorBuffer, uint16_t nr_pixels, uint8_t async),
            fillScreen(uint16_t color),
 		   #if defined (__STM32F1__)
 		   drawLine(int16_t x0, int16_t y0,int16_t x1, int16_t y1, uint16_t color),

From 33411b6e946dc0fc71420420f847c6bac6ce2aad Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sun, 6 Aug 2017 21:04:02 +1000
Subject: [PATCH 168/307] Default Wire to 100khz

---
 STM32F1/libraries/Wire/Wire.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/libraries/Wire/Wire.cpp b/STM32F1/libraries/Wire/Wire.cpp
index d8252c1c0..c4e9befa7 100644
--- a/STM32F1/libraries/Wire/Wire.cpp
+++ b/STM32F1/libraries/Wire/Wire.cpp
@@ -100,4 +100,4 @@ void HardWire::setClock(uint32_t frequencyHz)
 	
 }
 
-HardWire Wire(1, I2C_FAST_MODE);;
+HardWire Wire(1);

From a9767e4c535e28ecf781f98fc8fbc85e134b406c Mon Sep 17 00:00:00 2001
From: victorpv <victor_pv@hotmail.com>
Date: Fri, 18 Aug 2017 17:33:00 -0500
Subject: [PATCH 169/307] Adding new.cpp as in F1 core.

This is to avoid libstdc++ being pulled in when new() is used.
Already included in the F1 in 2016.
Discussed on this thread:
http://www.stm32duino.com/viewtopic.php?f=39&t=2460&p=33163
---
 STM32F4/cores/maple/new.cpp | 35 +++++++++++++++++++++++++++++++++++
 1 file changed, 35 insertions(+)
 create mode 100644 STM32F4/cores/maple/new.cpp

diff --git a/STM32F4/cores/maple/new.cpp b/STM32F4/cores/maple/new.cpp
new file mode 100644
index 000000000..7553ddf35
--- /dev/null
+++ b/STM32F4/cores/maple/new.cpp
@@ -0,0 +1,35 @@
+/*
+  Copyright (c) 2014 Arduino.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. 
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+#include <stdlib.h>
+
+void *operator new(size_t size) {
+  return malloc(size);
+}
+
+void *operator new[](size_t size) {
+  return malloc(size);
+}
+
+void operator delete(void * ptr) {
+  free(ptr);
+}
+
+void operator delete[](void * ptr) {
+  free(ptr);
+}

From 71d5ab9112ab0c28e2c216a31b3a3ff05d0b1d37 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Fri, 25 Aug 2017 18:33:04 +1000
Subject: [PATCH 170/307] Wire lib change buffer size definition to
 BUFFER_LENGTH for better AVR compatibility

---
 STM32F1/libraries/Wire/SoftWire.h   | 2 +-
 STM32F1/libraries/Wire/WireBase.cpp | 6 +++---
 STM32F1/libraries/Wire/WireBase.h   | 6 +++---
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/STM32F1/libraries/Wire/SoftWire.h b/STM32F1/libraries/Wire/SoftWire.h
index 0804c0f11..136dc3d8c 100644
--- a/STM32F1/libraries/Wire/SoftWire.h
+++ b/STM32F1/libraries/Wire/SoftWire.h
@@ -57,7 +57,7 @@
 //#define I2C_DELAY(x) {uint32 time=micros(); while(time>(micros()+x));}
 #define I2C_DELAY(x) do{for(int i=0;i<x;i++) {asm volatile("nop");}}while(0)
 
-#define BUFFER_LENGTH 32
+
 
 
 class TwoWire : public WireBase {
diff --git a/STM32F1/libraries/Wire/WireBase.cpp b/STM32F1/libraries/Wire/WireBase.cpp
index 90ec37044..220d845d7 100644
--- a/STM32F1/libraries/Wire/WireBase.cpp
+++ b/STM32F1/libraries/Wire/WireBase.cpp
@@ -78,8 +78,8 @@ uint8 WireBase::endTransmission(){
 // call, allows for the Arduino style to stay while also giving the flexibility
 // to bulk send
 uint8 WireBase::requestFrom(uint8 address, int num_bytes) {
-    if (num_bytes > WIRE_BUFSIZ) {
-        num_bytes = WIRE_BUFSIZ;
+    if (num_bytes > BUFFER_LENGTH) {
+        num_bytes = BUFFER_LENGTH;
     }
     itc_msg.addr = address;
     itc_msg.flags = I2C_MSG_READ;
@@ -96,7 +96,7 @@ uint8 WireBase::requestFrom(int address, int numBytes) {
 }
 
 void WireBase::write(uint8 value) {
-    if (tx_buf_idx == WIRE_BUFSIZ) {
+    if (tx_buf_idx == BUFFER_LENGTH) {
         tx_buf_overflow = true;
         return;
     }
diff --git a/STM32F1/libraries/Wire/WireBase.h b/STM32F1/libraries/Wire/WireBase.h
index 5e51ab78c..72facded6 100644
--- a/STM32F1/libraries/Wire/WireBase.h
+++ b/STM32F1/libraries/Wire/WireBase.h
@@ -44,7 +44,7 @@
 #include "wirish.h"
 #include <libmaple/i2c.h>
 
-#define WIRE_BUFSIZ 32
+#define BUFFER_LENGTH 32
 
 /* return codes from endTransmission() */
 #define SUCCESS   0        /* transmission was successful */
@@ -56,11 +56,11 @@
 class WireBase { // Abstraction is awesome!
 protected:
     i2c_msg itc_msg;
-    uint8 rx_buf[WIRE_BUFSIZ];      /* receive buffer */
+    uint8 rx_buf[BUFFER_LENGTH];      /* receive buffer */
     uint8 rx_buf_idx;               /* first unread idx in rx_buf */
     uint8 rx_buf_len;               /* number of bytes read */
 
-    uint8 tx_buf[WIRE_BUFSIZ];      /* transmit buffer */
+    uint8 tx_buf[BUFFER_LENGTH];      /* transmit buffer */
     uint8 tx_buf_idx;  // next idx available in tx_buf, -1 overflow
     boolean tx_buf_overflow;
 

From 5058d8f5838b8b5b63ba21f0ea950585d849a4d3 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sat, 26 Aug 2017 14:37:40 +1000
Subject: [PATCH 171/307] Removed support for GD32 - by removing entry from
 boards.txt

---
 STM32F1/boards.txt | 91 ----------------------------------------------
 1 file changed, 91 deletions(-)

diff --git a/STM32F1/boards.txt b/STM32F1/boards.txt
index b3eac901f..6d110d040 100644
--- a/STM32F1/boards.txt
+++ b/STM32F1/boards.txt
@@ -928,97 +928,6 @@ hytiny-stm32f103t.menu.opt.o3lto.build.flags.ldspecs=-flto
 hytiny-stm32f103t.menu.opt.ogstd.build.flags.optimize=-Og
 hytiny-stm32f103t.menu.opt.ogstd.build.flags.ldspecs=
 
-###################### Generic GD32F103C  ########################################
-
-genericGD32F103C.name=Generic GD32F103C series
-genericGD32F103C.build.variant=generic_gd32f103c
-genericGD32F103C.build.vect=VECT_TAB_ADDR=0x8000000
-genericGD32F103C.build.core=maple
-genericGD32F103C.build.board=GENERIC_GD32F103C
-genericGD32F103C.upload.use_1200bps_touch=false
-genericGD32F103C.upload.file_type=bin
-genericGD32F103C.upload.auto_reset=true
-genericGD32F103C.build.cpu_flags=-DMCU_STM32F103CB  
-genericGD32F103C.build.f_cpu=72000000L
-
-## GD32F103C8 -------------------------
-genericGD32F103C.menu.device_variant.GD32F103C8=GD32F103C8 (20k RAM. 64k Flash)
-genericGD32F103C.menu.device_variant.GD32F103C8.build.ldscript=ld/jtag_c8.ld
-genericGD32F103C.menu.device_variant.GD32F103C8.upload.maximum_size=65536
-genericGD32F103C.menu.device_variant.GD32F103C8.upload.maximum_data_size=20480
-
-## GD32F103CB -------------------------
-genericGD32F103C.menu.device_variant.GD32F103CB=GD32F103CB (20k RAM. 128k Flash)
-genericGD32F103C.menu.device_variant.GD32F103CB.build.ldscript=ld/jtag.ld
-genericGD32F103C.menu.device_variant.GD32F103CB.upload.maximum_size=131072
-genericGD32F103C.menu.device_variant.GD32F103CB.upload.maximum_data_size=20480
-
-#---------------------------- UPLOAD METHODS ---------------------------
-
-genericGD32F103C.menu.upload_method.DFUUploadMethod=GD32duino bootloader
-
-genericGD32F103C.menu.upload_method.DFUUploadMethod.upload.protocol=maple_dfu
-genericGD32F103C.menu.upload_method.DFUUploadMethod.upload.tool=maple_upload
-genericGD32F103C.menu.upload_method.DFUUploadMethod.build.upload_flags=-DSERIAL_USB -DGENERIC_BOOTLOADER 
-genericGD32F103C.menu.upload_method.DFUUploadMethod.build.vect=VECT_TAB_ADDR=0x8002000
-genericGD32F103C.menu.upload_method.DFUUploadMethod.build.ldscript=ld/bootloader_20.ld
-genericGD32F103C.menu.upload_method.DFUUploadMethod.upload.usbID=1EAF:0003
-genericGD32F103C.menu.upload_method.DFUUploadMethod.upload.altID=2
-
-genericGD32F103C.menu.upload_method.serialMethod=Serial
-genericGD32F103C.menu.upload_method.serialMethod.upload.protocol=maple_serial
-genericGD32F103C.menu.upload_method.serialMethod.upload.tool=serial_upload
-genericGD32F103C.menu.upload_method.serialMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG=1
-
-genericGD32F103C.menu.upload_method.STLinkMethod=STLink
-genericGD32F103C.menu.upload_method.STLinkMethod.upload.protocol=STLink
-genericGD32F103C.menu.upload_method.STLinkMethod.upload.tool=stlink_upload
-genericGD32F103C.menu.upload_method.STLinkMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG=1 -DSERIAL_USB -DGENERIC_BOOTLOADER
-
-
-genericGD32F103C.menu.upload_method.BMPMethod=BMP (Black Magic Probe)
-genericGD32F103C.menu.upload_method.BMPMethod.upload.protocol=gdb_bmp
-genericGD32F103C.menu.upload_method.BMPMethod.upload.tool=bmp_upload
-genericGD32F103C.menu.upload_method.BMPMethod.build.upload_flags=-DCONFIG_MAPLE_MINI_NO_DISABLE_DEBUG
-
-genericGD32F103C.menu.cpu_speed.speed_120mhz=120Mhz (overdrive)
-genericGD32F103C.menu.cpu_speed.speed_120mhz.build.f_cpu=120000000L
-
-genericGD32F103C.menu.cpu_speed.speed_96mhz=96Mhz (Stable)
-genericGD32F103C.menu.cpu_speed.speed_96mhz.build.f_cpu=96000000L
-
-genericGD32F103C.menu.cpu_speed.speed_72mhz=72Mhz (compatibility)
-genericGD32F103C.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
-
-#-- Optimizations
-genericGD32F103C.menu.opt.osstd=Smallest (default)
-genericGD32F103C.menu.opt.osstd.build.flags.optimize=-Os
-genericGD32F103C.menu.opt.osstd.build.flags.ldspecs=
-genericGD32F103C.menu.opt.oslto=Smallest Code with LTO
-genericGD32F103C.menu.opt.oslto.build.flags.optimize=-Os -flto
-genericGD32F103C.menu.opt.oslto.build.flags.ldspecs=-flto
-genericGD32F103C.menu.opt.o1std=Fast (-O1)
-genericGD32F103C.menu.opt.o1std.build.flags.optimize=-O1
-genericGD32F103C.menu.opt.o1std.build.flags.ldspecs=
-genericGD32F103C.menu.opt.o1lto=Fast (-O1) with LTO
-genericGD32F103C.menu.opt.o1lto.build.flags.optimize=-O1 -flto
-genericGD32F103C.menu.opt.o1lto.build.flags.ldspecs=-flto
-genericGD32F103C.menu.opt.o2std=Faster (-O2)
-genericGD32F103C.menu.opt.o2std.build.flags.optimize=-O2
-genericGD32F103C.menu.opt.o2std.build.flags.ldspecs=
-genericGD32F103C.menu.opt.o2lto=Faster (-O2) with LTO
-genericGD32F103C.menu.opt.o2lto.build.flags.optimize=-O2 -flto
-genericGD32F103C.menu.opt.o2lto.build.flags.ldspecs=-flto
-genericGD32F103C.menu.opt.o3std=Fastest (-O3)
-genericGD32F103C.menu.opt.o3std.build.flags.optimize=-O3
-genericGD32F103C.menu.opt.o3std.build.flags.ldspecs=
-genericGD32F103C.menu.opt.o3lto=Fastest (-O3) with LTO
-genericGD32F103C.menu.opt.o3lto.build.flags.optimize=-O3 -flto
-genericGD32F103C.menu.opt.ogstd=Debug (-g)
-genericGD32F103C.menu.opt.o3lto.build.flags.ldspecs=-flto
-genericGD32F103C.menu.opt.ogstd.build.flags.optimize=-Og
-genericGD32F103C.menu.opt.ogstd.build.flags.ldspecs=
-
 ########################### STM32VLD to FLASH ###########################
 
 STM32VLD.name=STM32VLD to FLASH

From 47c94bc10ca54c8394f0ff800d6a88a4f90ace22 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sat, 26 Aug 2017 20:34:43 +1000
Subject: [PATCH 172/307] Update Arduino IDE version in readme

---
 README.md | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/README.md b/README.md
index 4ffc9ed66..9d167cf79 100644
--- a/README.md
+++ b/README.md
@@ -9,7 +9,7 @@ Use of these files is at your own risk.
 
 
 ## Summary:  
-This repo contains, the "Hardware" files to support STM32 based boards on Arduino version 1.6.13 or 1.6.12 (some older versions may also work)  including [LeafLabs Maple, and Maple mini](http://www.leaflabs.com/about-maple/), and other generic STM32F103 boards  
+This repo contains, the "Hardware" files to support STM32 based boards on Arduino version 1.8.x (some older versions may also work)  including [LeafLabs Maple, and Maple mini](http://www.leaflabs.com/about-maple/), and other generic STM32F103 boards  
 
 ***PRIMARY SUPPORT FORUM: http://www.stm32duino.com/***
 

From e6ed2d5cccff1cf6ca4bd98ec42b4d02377587f3 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Tue, 29 Aug 2017 11:16:43 +0200
Subject: [PATCH 173/307] Update RTClock.cpp

bugfix setAlarmATime - corrected day variable
---
 STM32F4/libraries/RTClock/src/RTClock.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F4/libraries/RTClock/src/RTClock.cpp b/STM32F4/libraries/RTClock/src/RTClock.cpp
index e7c2ca8da..a6ef9f15e 100644
--- a/STM32F4/libraries/RTClock/src/RTClock.cpp
+++ b/STM32F4/libraries/RTClock/src/RTClock.cpp
@@ -281,7 +281,7 @@ void RTClock::setAlarmATime (tm_t * tm_ptr, bool hours_match, bool mins_match, b
 {
     uint32 t = 0;
     rtc_enter_config_mode();
-    unsigned int bits = ((tm_ptr->day / 10) << 28) | ((tm.day % 10) << 24) |
+    unsigned int bits = ((tm_ptr->day / 10) << 28) | ((tm_ptr->day % 10) << 24) |
 		        ((tm_ptr->hour / 10) << 20) | ((tm_ptr->hour % 10) << 16) | 
 			((tm_ptr->minute / 10) << 12) | ((tm_ptr->minute % 10) << 8) | 
 			((tm_ptr->second / 10) << 4) | (tm_ptr->second % 10);

From fbe6264003935b48cf12ff1790d0c11f3342edd6 Mon Sep 17 00:00:00 2001
From: csnol <csnol@126.com>
Date: Tue, 29 Aug 2017 10:07:42 -0500
Subject: [PATCH 174/307] Rewrite the RTClock library.

---
 STM32F1/libraries/RTClock/src/RTClock.cpp | 114 +++++++++++++++++++---
 STM32F1/libraries/RTClock/src/RTClock.h   |  63 ++++++++++--
 2 files changed, 157 insertions(+), 20 deletions(-)

diff --git a/STM32F1/libraries/RTClock/src/RTClock.cpp b/STM32F1/libraries/RTClock/src/RTClock.cpp
index 869e15219..f2f8501ef 100644
--- a/STM32F1/libraries/RTClock/src/RTClock.cpp
+++ b/STM32F1/libraries/RTClock/src/RTClock.cpp
@@ -81,21 +81,108 @@
 */	
 	
 	void RTClock::setTime (time_t time_stamp) {
-		rtc_set_count(time_stamp);
+			breakTime(time_stamp, tmm); // time will be broken to tm
+    setTime(tmm);
+		//rtc_set_count(time_stamp);
 	}
 	
-	void RTClock::setTime (struct tm* tm_ptr) {
-		rtc_set_count(mktime (tm_ptr));
-	}
+	#define LEAP_YEAR(Y)     ( ((1970+Y)>0) && !((1970+Y)%4) && ( ((1970+Y)%100) || !((1970+Y)%400) ) )
 	
+	//-----------------------------------------------------------------------------
+void RTClock::breakTime(time_t timeInput, tm_t & tmm)
+{
+// break the given time_t into time components
+// this is a more compact version of the C library localtime function
+// note that year is offset from 1970 !!!
+
+	uint8_t year;
+	uint8_t month, monthLength;
+	uint32_t time;
+	uint32_t days;
+
+	time = (uint32_t)timeInput;
+	tmm.second = time % 60;
+	time /= 60; // now it is minutes
+	tmm.minute = time % 60;
+	time /= 60; // now it is hours
+	tmm.hour = time % 24;
+	time /= 24; // now it is days
+	tmm.weekday = ((time + 4) % 7); // Monday is day 1 // + 1;  // Sunday is day 1 
+
+	year = 0;
+	days = 0;
+	while((unsigned)(days += (LEAP_YEAR(year) ? 366 : 365)) <= time) {
+		year++;
+	}
+	tmm.year = year; // year is offset from 1970 
+
+	days -= LEAP_YEAR(year) ? 366 : 365;
+	time -= days; // now it is days in this year, starting at 0
+
+	days = 0;
+	month = 0;
+	monthLength = 0;
+	for (month=0; month<12; month++) {
+		if (month==1) { // february
+			if (LEAP_YEAR(year)) {
+				monthLength=29;
+			} else {
+				monthLength=28;
+			}
+		} else {
+			monthLength = monthDays[month];
+		}
+
+		if (time >= monthLength) {
+			time -= monthLength;
+		} else {
+			break;
+		}
+	}
+	tmm.month = month + 1;  // jan is month 1  
+	tmm.day = time + 1;     // day of month
+}
+
+//-----------------------------------------------------------------------------
+time_t RTClock::makeTime(tm_t & tmm)
+{
+// assemble time elements into time_t 
+// note year argument is offset from 1970 (see macros in time.h to convert to other formats)
+// previous version used full four digit year (or digits since 2000),i.e. 2009 was 2009 or 9
+  
+	int i;
+	uint32_t seconds;
+
+	// seconds from 1970 till 1 jan 00:00:00 of the given year
+	seconds = tmm.year*(SECS_PER_DAY * 365);
+	for (i = 0; i < tmm.year; i++) {
+		if (LEAP_YEAR(i)) {
+			seconds +=  SECS_PER_DAY;   // add extra days for leap years
+		}
+	}
+
+	// add days for this year, months start from 1
+	for (i = 1; i < tmm.month; i++) {
+		if ( (i == 2) && LEAP_YEAR(tmm.year)) { 
+			seconds += SECS_PER_DAY * 29;
+		} else {
+			seconds += SECS_PER_DAY * monthDays[i-1];  //monthDay array starts from 0
+		}
+	}
+	seconds+= (tmm.day-1) * SECS_PER_DAY;
+	seconds+= tmm.hour * SECS_PER_HOUR;
+	seconds+= tmm.minute * SECS_PER_MIN;
+	seconds+= tmm.second;
+	return (time_t)seconds; 
+}
+
 	time_t RTClock::getTime() {
 		return rtc_get_count();
 	}
-	
-	struct tm*  RTClock::getTime(struct tm* tm_ptr) {
+
+    void RTClock::getTime(tm_t & tm_ptr) {
 		time_t res = rtc_get_count();
-		tm_ptr = gmtime(&res); //why not gmtime? 
-		return tm_ptr;
+		breakTime(res, tm_ptr);
 	}
 	
 	void RTClock::createAlarm(voidFuncPtr function, time_t alarm_time_t) {
@@ -110,15 +197,16 @@
 		rtc_detach_interrupt(RTC_SECONDS_INTERRUPT);
 	}
 
-	
-	void RTClock::createAlarm(voidFuncPtr function, tm* alarm_tm) {
-		time_t alarm = mktime(alarm_tm);//convert to time_t
+
+	void RTClock::createAlarm(voidFuncPtr function, tm_t & alarm_tm) {
+		time_t alarm = makeTime(alarm_tm);//convert to time_t
 		createAlarm(function, alarm);	
 	}
 
 //change alarm time	
-	void RTClock::setAlarmTime (tm * tm_ptr) {
-		time_t time = mktime(tm_ptr);//convert to time_t
+
+	void RTClock::setAlarmTime (tm_t  & tm_ptr) {
+		time_t time = makeTime(tm_ptr);//convert to time_t
 		rtc_set_alarm(time); //must be int... for standardization sake. 
 	}
 
diff --git a/STM32F1/libraries/RTClock/src/RTClock.h b/STM32F1/libraries/RTClock/src/RTClock.h
index 443a30b5d..711992e1f 100644
--- a/STM32F1/libraries/RTClock/src/RTClock.h
+++ b/STM32F1/libraries/RTClock/src/RTClock.h
@@ -7,9 +7,35 @@
 #ifndef _RTCLOCK_H_
 #define _RTCLOCK_H_
 
+#define SECS_PER_MIN  (60UL)
+#define SECS_PER_HOUR (3600UL)
+#define SECS_PER_DAY  (SECS_PER_HOUR * 24UL)
+#define DAYS_PER_WEEK (7UL)
+#define SECS_PER_WEEK (SECS_PER_DAY * DAYS_PER_WEEK)
+#define SECS_PER_YEAR (SECS_PER_WEEK * 52UL)
+#define SECS_YR_2000  (946684800UL) // the time at the start of y2k
+#define LEAP_YEAR(Y)  ( ((1970+Y)>0) && !((1970+Y)%4) && ( ((1970+Y)%100) || !((1970+Y)%400) ) )
 
+#if !defined(__time_t_defined) // avoid conflict with newlib or other posix libc
+  #warning "Using private time_t definintion"
+  typedef uint32_t time_t;
+#endif
 
+static  const unsigned char monthDays[]={31,28,31,30,31,30,31,31,30,31,30,31}; // API starts months from 1, this array starts from 0
 
+typedef struct tm_t {
+	uint8_t  year;    // years since 1970
+	uint8_t  month;   // month of a year - [ 1 to 12 ]
+	uint8_t  day;     // day of a month - [ 1 to 31 ]
+	uint8_t  weekday; // day of a week (first day is Sunday) - [ 0 to 6 ]
+	uint8_t  pm;      // AM: 0, PM: 1
+	uint8_t  hour;    // hour of a day - [ 0 to 23 ]
+	uint8_t  minute;  // minute of an hour - [ 0 to 59 ]
+	uint8_t  second;  // second of a minute - [ 0 to 59 ]
+} tm_t;
+
+static inline uint8_t bcd2bin(uint8_t b) { return ( (10*(b>>4)) + (b&0x0F) ); }
+static inline uint8_t bin2bcd(uint8_t b) { return ( ((b/10)<<4) + (b%10) ); }
 
 class RTClock {
  public:
@@ -18,24 +44,47 @@ class RTClock {
 	RTClock(rtc_clk_src src, uint16 prescaler );
 	//~RTClock(); //to implement
 	
-
+	void breakTime(time_t epoch_time, tm_t & tmm);
+	time_t makeTime(tm_t & tmm);
+	
 	void setTime (time_t time_stamp);
-	void setTime (struct tm * tm_ptr); 
+	void setTime (tm_t & tmm); 
 	
-	struct tm* getTime(struct tm* tm_ptr); 
 	time_t getTime();
+	void getTime(tm_t & tmm );
+		#define now getTime
+
+	uint8_t year(void)    { getTime(tmm); return tmm.year; }
+	uint8_t month(void)   { getTime(tmm); return tmm.month; }
+	uint8_t day(void)     { getTime(tmm); return tmm.day; }
+	uint8_t weekday(void) { getTime(tmm); return tmm.weekday; }
+	uint8_t hour(void)    { getTime(tmm); return tmm.hour; }
+	uint8_t minute(void)  { getTime(tmm); return tmm.minute; }
+	uint8_t second(void)  { getTime(tmm); return tmm.second; }
+	uint8_t isPM(void)    { return ( hour()>=12 ); }
+	
+	uint8_t year(time_t t)    { breakTime(t, tmm); return tmm.year; }
+	uint8_t month(time_t t)   { breakTime(t, tmm); return tmm.month; }
+	uint8_t day(time_t t)     { breakTime(t, tmm); return tmm.day; }
+	uint8_t weekday(time_t t) { breakTime(t, tmm); return tmm.weekday; }
+	uint8_t hour(time_t t)    { breakTime(t, tmm); return tmm.hour; }
+	uint8_t minute(time_t t)  { breakTime(t, tmm); return tmm.minute; }
+	uint8_t second(time_t t)  { breakTime(t, tmm); return tmm.second; }
+	uint8_t isPM(time_t t)    { return (hour(t)>=12); }
 	
 	void createAlarm(voidFuncPtr function, time_t alarm_time_t); 
-	void createAlarm(voidFuncPtr function, struct tm* alarm_tm);
+	void createAlarm(voidFuncPtr function, struct tm_t & alarm_tm);
 	
 	void attachSecondsInterrupt(voidFuncPtr function); 
 	void detachSecondsInterrupt();
 	
-	void setAlarmTime (tm * tm_ptr);
+	void setAlarmTime (tm_t  & tm_ptr);
 	void setAlarmTime (time_t alarm_time); 
- //private:
+	
+ 
+	tm_t tmm;
+};
 
-} ;
 
 
 

From 27f8e127a4d9bdd5c77c026088a3655b9e57f95a Mon Sep 17 00:00:00 2001
From: csnol <csnol@126.com>
Date: Tue, 29 Aug 2017 23:13:02 +0800
Subject: [PATCH 175/307] Create a RTC example for new library.

---
 .../examples/RTC-Serial-Set-Newlibrary.ino    | 80 +++++++++++++++++++
 1 file changed, 80 insertions(+)
 create mode 100644 STM32F1/libraries/RTClock/examples/RTC-Serial-Set-Newlibrary.ino

diff --git a/STM32F1/libraries/RTClock/examples/RTC-Serial-Set-Newlibrary.ino b/STM32F1/libraries/RTClock/examples/RTC-Serial-Set-Newlibrary.ino
new file mode 100644
index 000000000..ba89a4e02
--- /dev/null
+++ b/STM32F1/libraries/RTClock/examples/RTC-Serial-Set-Newlibrary.ino
@@ -0,0 +1,80 @@
+/*   STM32F103C8 Black Pill ( PB12)
+
+  Serialport set and display RTC clock , Write by CSNOL https://github.com/csnol/STM32-Examples
+  based on https://github.com/rogerclarkmelbourne/Arduino_STM32
+
+  1. Blink on PB12 per 1s.
+  2. change to your timezone in the sketch; .
+  3. get Unix epoch time from https://www.epochconverter.com/ ;
+  4. last step input the 10 bits number( example: 1503945555) to Serialport ;
+  5. the clock will be reset to you wanted.
+
+  ##  Why the 10 bits Unix epoch time be used?
+****Because I wanna connect to NTP server by ESP-8266.
+****in the <NTPClient.h> library. getNtpTime() will return this 10 bits Unix epoch time.
+*/
+
+
+#include <RTClock.h>
+
+RTClock rtclock (RTCSEL_LSE); // initialise
+time_t tt;
+tm_t mtt = { 47, 8, 27, 0, 1, 20, 30, 30 };
+char weekday1[][7] = {"Sun", "Mon", "Tue", "Wed", "Thu", "Fri", "Sat"};  // 0,1,2,3,4,5,6
+uint8_t timeread[11];
+int timezone = 8 * 3600;    // timezone -8 + DST +1 = -7  CA USA
+time_t tt1;
+
+#define LED_PIN PB12
+
+// This function is called in the attachSecondsInterrpt
+void blink ()
+{
+  digitalWrite(LED_PIN, !digitalRead(LED_PIN));
+  tt++;
+}
+
+void setup()
+{
+  Serial.begin(115200);
+  pinMode(LED_PIN, OUTPUT);
+  tt = rtclock.makeTime(mtt);
+  tt1 = tt;
+  rtclock.attachSecondsInterrupt(blink);// Call blink
+}
+
+
+int i = 0;
+void loop()
+{
+  while (Serial.available())
+  { timeread[i] = Serial.read();
+    if (i < 11) {
+      i++;
+    }
+    else {
+      i = 0;
+      tt = (timeread[0] - '0') * 1000000000 + (timeread[1] - '0') * 100000000 + (timeread[2] - '0') * 10000000 + (timeread[3] - '0') * 1000000 + (timeread[4] - '0') * 100000;
+      tt += (timeread[5] - '0') * 10000 + (timeread[6] - '0') * 1000 + (timeread[7] - '0') * 100 + (timeread[8] - '0') * 10 + (timeread[9] - '0') + timezone;
+    }
+  }
+  if (tt1 != tt)
+  {
+    tt1 = tt;
+    rtclock.breakTime(tt, mtt);
+    Serial.print("Date:  ");
+    Serial.print(mtt.day);
+    Serial.print("- ");
+    Serial.print(mtt.month);
+    Serial.print("  ");
+    Serial.print(mtt.year + 1970);
+    Serial.print("  ");
+    Serial.print(weekday1[mtt.weekday]);
+    Serial.print("  Time: ");
+    Serial.print(mtt.hour);
+    Serial.print(" : ");
+    Serial.print(mtt.minute);
+    Serial.print(" : ");
+    Serial.println(mtt.second);
+  }
+}

From 6e92ddd8bc0a723359a52d86a3cd004be178385d Mon Sep 17 00:00:00 2001
From: csnol <csnol@126.com>
Date: Tue, 29 Aug 2017 10:30:27 -0500
Subject: [PATCH 176/307] Add STM32F103-RTC-Serial-Set.jpg

---
 .../examples/STM32F103-RTC-Serial-Set.jpg      | Bin 0 -> 131470 bytes
 1 file changed, 0 insertions(+), 0 deletions(-)
 create mode 100644 STM32F1/libraries/RTClock/examples/STM32F103-RTC-Serial-Set.jpg

diff --git a/STM32F1/libraries/RTClock/examples/STM32F103-RTC-Serial-Set.jpg b/STM32F1/libraries/RTClock/examples/STM32F103-RTC-Serial-Set.jpg
new file mode 100644
index 0000000000000000000000000000000000000000..b2e701ea9e4789dd48ad0bbfe2c93534d7c61c19
GIT binary patch
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literal 0
HcmV?d00001


From 6c0be70f2efa2706e8ad0eb617dcb9226c0d335e Mon Sep 17 00:00:00 2001
From: csnol <csnol@126.com>
Date: Wed, 30 Aug 2017 23:28:01 +0800
Subject: [PATCH 177/307] Update RTClock.cpp

---
 STM32F1/libraries/RTClock/src/RTClock.cpp | 10 +++++++---
 1 file changed, 7 insertions(+), 3 deletions(-)

diff --git a/STM32F1/libraries/RTClock/src/RTClock.cpp b/STM32F1/libraries/RTClock/src/RTClock.cpp
index f2f8501ef..5baaa40a1 100644
--- a/STM32F1/libraries/RTClock/src/RTClock.cpp
+++ b/STM32F1/libraries/RTClock/src/RTClock.cpp
@@ -81,12 +81,16 @@
 */	
 	
 	void RTClock::setTime (time_t time_stamp) {
-			breakTime(time_stamp, tmm); // time will be broken to tm
-    setTime(tmm);
+		breakTime(time_stamp, tmm); // time will be broken to tmm
+    		setTime(tmm);
 		//rtc_set_count(time_stamp);
 	}
 	
-	#define LEAP_YEAR(Y)     ( ((1970+Y)>0) && !((1970+Y)%4) && ( ((1970+Y)%100) || !((1970+Y)%400) ) )
+	void RTClock::setTime (time_t time_stamp) {
+		rtc_set_count(time_stamp);
+	}
+	
+#define LEAP_YEAR(Y)     ( ((1970+Y)>0) && !((1970+Y)%4) && ( ((1970+Y)%100) || !((1970+Y)%400) ) )
 	
 	//-----------------------------------------------------------------------------
 void RTClock::breakTime(time_t timeInput, tm_t & tmm)

From d53cacdb1ec2298382fec602164562690e815eec Mon Sep 17 00:00:00 2001
From: csnol <csnol@126.com>
Date: Wed, 30 Aug 2017 23:37:41 +0800
Subject: [PATCH 178/307] Update RTClock.cpp

---
 STM32F1/libraries/RTClock/src/RTClock.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/STM32F1/libraries/RTClock/src/RTClock.cpp b/STM32F1/libraries/RTClock/src/RTClock.cpp
index 5baaa40a1..cc7b63e8d 100644
--- a/STM32F1/libraries/RTClock/src/RTClock.cpp
+++ b/STM32F1/libraries/RTClock/src/RTClock.cpp
@@ -80,9 +80,9 @@
 	}
 */	
 	
-	void RTClock::setTime (time_t time_stamp) {
-		breakTime(time_stamp, tmm); // time will be broken to tmm
-    		setTime(tmm);
+	void RTClock::setTime (tm_t & tmm) {
+		time_t mktm = makeTime(tmm); // time will be make to mktm
+    		setTime(mktm);
 		//rtc_set_count(time_stamp);
 	}
 	

From f12bad6790eff27e7f107ca689298473153fdf49 Mon Sep 17 00:00:00 2001
From: Jan Chrillesen <chrille@gmail.com>
Date: Thu, 31 Aug 2017 20:54:29 +0200
Subject: [PATCH 179/307] add JLink upload support for OSX

---
 tools/macosx/jlink_upload | 9 +++++++++
 1 file changed, 9 insertions(+)
 create mode 100755 tools/macosx/jlink_upload

diff --git a/tools/macosx/jlink_upload b/tools/macosx/jlink_upload
new file mode 100755
index 000000000..a9e981026
--- /dev/null
+++ b/tools/macosx/jlink_upload
@@ -0,0 +1,9 @@
+#!/bin/bash
+
+echo erase > "$1".jlink
+echo loadbin "$1" , 0x8000000 >> "$1".jlink
+echo r >> "$1".jlink
+echo q >> "$1".jlink
+
+/Applications/SEGGER/JLink/JLinkExe -device STM32F103C8 -if SWD -speed auto -CommanderScript "$1".jlink
+

From 58e50e7fd9062e45ec23d575a16cd411522c37cb Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sun, 3 Sep 2017 10:51:08 +1000
Subject: [PATCH 180/307] Add partial support for a DFU bootloader for the F4

---
 STM32F4/boards.txt                            | 26 ++++++++++++++++++-
 STM32F4/cores/maple/libmaple/libmaple.h       |  2 ++
 STM32F4/platform.txt                          | 10 +++----
 .../generic_f407v/ld/bootloader_8004000.ld    | 21 +++++++++++++++
 4 files changed, 53 insertions(+), 6 deletions(-)
 create mode 100644 STM32F4/variants/generic_f407v/ld/bootloader_8004000.ld

diff --git a/STM32F4/boards.txt b/STM32F4/boards.txt
index abc40f02b..907e6f7f4 100644
--- a/STM32F4/boards.txt
+++ b/STM32F4/boards.txt
@@ -2,6 +2,7 @@
 
 menu.usb_cfg=USB configuration
 menu.opt=Optimize
+menu.upload_method=Upload method
 
 ##############################################################
 discovery_f407.name=STM32 Discovery F407
@@ -30,6 +31,7 @@ discovery_f407.build.density=STM32_HIGH_DENSITY
 discovery_f407.build.error_led_port=GPIOD
 discovery_f407.build.error_led_pin=14
 discovery_f407.build.board=STM32DiscoveryF407
+discovery_f407.build.vect_flags=-DVECT_TAB_FLASH -DUSER_ADDR_ROM=(uint32)0x08000000
 
 discovery_f407.menu.usb_cfg.usb_nc=USB inactive
 discovery_f407.menu.usb_cfg.usb_nc.build.cpu_flags=-DUSB_NC
@@ -92,16 +94,37 @@ generic_f407v.build.density=STM32_HIGH_DENSITY
 generic_f407v.build.error_led_port=GPIOA
 generic_f407v.build.error_led_pin=7
 generic_f407v.build.board=STM32GenericF407VET6
+generic_f407v.build.vect_flags=-DVECT_TAB_FLASH -DUSER_ADDR_ROM=(uint32)0x08000000
 
 generic_f407v.menu.usb_cfg.usb_nc=USB inactive
 generic_f407v.menu.usb_cfg.usb_nc.build.cpu_flags=-DUSB_NC
 
 generic_f407v.menu.usb_cfg.usb_serial=USB serial (CDC)
 generic_f407v.menu.usb_cfg.usb_serial.build.cpu_flags=-DSERIAL_USB
-
 generic_f407v.menu.usb_cfg.usb_msc=USB Mass Storage (MSC)
 generic_f407v.menu.usb_cfg.usb_msc.build.cpu_flags=-DUSB_MSC
 
+#note STLink is the default from the main block of config above, so does not need settings for everything
+generic_f407v.menu.upload_method.STLinkMethod=STLink
+generic_f407v.menu.upload_method.STLinkMethod.upload.protocol=STLink
+generic_f407v.menu.upload_method.STLinkMethod.upload.tool=stlink_upload
+generic_f407v.menu.upload_method.STLinkMethod.upload.dfuse_addr=0x08004000
+generic_f407v.menu.upload_method.STLinkMethod.build.vect_flags=-DVECT_TAB_FLASH -DUSER_ADDR_ROM=(uint32)0x08000000
+
+
+generic_f407v.menu.upload_method.DFUUploadMethod=STM32duino bootloader
+generic_f407v.menu.upload_method.DFUUploadMethod.upload.protocol=maple_dfu
+generic_f407v.menu.upload_method.DFUUploadMethod.upload.tool=maple_upload
+generic_f407v.menu.upload_method.DFUUploadMethod.build.vect_flags=-DVECT_TAB_FLASH -DUSER_ADDR_ROM=(uint32)0x08004000
+generic_f407v.menu.upload_method.DFUUploadMethod.build.ldscript=ld/bootloader_8004000.ld
+generic_f407v.menu.upload_method.DFUUploadMethod.upload.usbID=1EAF:0003
+generic_f407v.menu.upload_method.DFUUploadMethod.upload.altID=2
+
+
+
+
+
+
 #-- Optimizations
 generic_f407v.menu.opt.osstd=Smallest (default)
 generic_f407v.menu.opt.osstd.build.flags.optimize=-Os
@@ -158,6 +181,7 @@ stm32f4stamp.build.density=STM32_HIGH_DENSITY
 stm32f4stamp.build.error_led_port=GPIOD
 stm32f4stamp.build.error_led_pin=14
 stm32f4stamp.build.board=STM32F4StampF405
+stm32f4stamp.build.vect_flags=-DVECT_TAB_FLASH -DUSER_ADDR_ROM=(uint32)0x08000000
 
 stm32f4stamp.menu.usb_cfg.usb_nc=USB inactive
 stm32f4stamp.menu.usb_cfg.usb_nc.build.cpu_flags=-DUSB_NC
diff --git a/STM32F4/cores/maple/libmaple/libmaple.h b/STM32F4/cores/maple/libmaple/libmaple.h
index 8360ba390..2ec0b2836 100644
--- a/STM32F4/cores/maple/libmaple/libmaple.h
+++ b/STM32F4/cores/maple/libmaple/libmaple.h
@@ -47,7 +47,9 @@
     #define STACK_TOP     0x20000800
 #elif defined(BOARD_freeflight)
 */
+#ifndef USER_ADDR_ROM
 #define USER_ADDR_ROM 0x08000000
+#endif
 #define USER_ADDR_RAM 0x20000C00
 #define STACK_TOP     0x20000800
 /*
diff --git a/STM32F4/platform.txt b/STM32F4/platform.txt
index 92dc1ea9a..d115210cc 100755
--- a/STM32F4/platform.txt
+++ b/STM32F4/platform.txt
@@ -10,13 +10,13 @@ version=0.1.0
 # ----------------------
 compiler.path={runtime.tools.arm-none-eabi-gcc.path}/bin/
 compiler.c.cmd=arm-none-eabi-gcc
-compiler.c.flags=-c -g {build.flags.optimize} -Wall -MMD -std=gnu11 -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
+compiler.c.flags=-c -g {build.flags.optimize} -Wall -MMD -std=gnu11 -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -DBOARD_{build.variant} {build.vect_flags} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
 compiler.c.elf.cmd=arm-none-eabi-g++
 compiler.c.elf.flags={build.flags.optimize} -Wl,--gc-sections {build.flags.ldspecs}
 compiler.S.cmd=arm-none-eabi-gcc
 compiler.S.flags=-c -g -x assembler-with-cpp -MMD
 compiler.cpp.cmd=arm-none-eabi-g++
-compiler.cpp.flags=-c -g {build.flags.optimize} -Wall -MMD -std=gnu++11 -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant} -D{build.vect} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
+compiler.cpp.flags=-c -g {build.flags.optimize} -Wall -MMD -std=gnu++11 -ffunction-sections -fdata-sections -nostdlib --param max-inline-insns-single=500 -fno-rtti -fno-exceptions -DBOARD_{build.variant} {build.vect_flags} -DERROR_LED_PORT={build.error_led_port} -DERROR_LED_PIN={build.error_led_pin}
 compiler.ar.cmd=arm-none-eabi-ar
 compiler.ar.flags=rcs
 compiler.objcopy.cmd=arm-none-eabi-objcopy
@@ -64,13 +64,13 @@ compiler.libs.c.flags="-I{build.system.path}/libmaple" "-I{build.core.path}/libm
 # ---------------------
 
 ## Compile c files
-recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.c.flags} -mcpu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.c.extra_flags} {build.extra_flags} {build.cpu_flags} {compiler.libs.c.flags} {includes} "{source_file}" -o "{object_file}"
+recipe.c.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.c.flags} -mcpu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.c.extra_flags} {build.extra_flags} {build.cpu_flags} {build.vect_flags} {compiler.libs.c.flags} {includes} "{source_file}" -o "{object_file}"
 
 ## Compile c++ files
-recipe.cpp.o.pattern="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.flags} -mcpu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {build.cpu_flags} {build.hs_flag} {build.common_flags} {compiler.libs.c.flags} {includes} "{source_file}" -o "{object_file}"
+recipe.cpp.o.pattern="{compiler.path}{compiler.cpp.cmd}" {compiler.cpp.flags} -mcpu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.cpp.extra_flags} {build.extra_flags} {build.cpu_flags} {build.vect_flags} {build.hs_flag} {build.common_flags} {compiler.libs.c.flags} {includes} "{source_file}" -o "{object_file}"
 
 ## Compile S files
-recipe.S.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.S.flags} -mcpu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.S.extra_flags} {build.extra_flags} {build.cpu_flags} {build.hs_flag} {build.common_flags} {compiler.libs.c.flags} {includes} "{source_file}" -o "{object_file}"
+recipe.S.o.pattern="{compiler.path}{compiler.c.cmd}" {compiler.S.flags} -mcpu={build.mcu} -DF_CPU={build.f_cpu} -DARDUINO={runtime.ide.version} -DARDUINO_{build.board} -DARDUINO_ARCH_{build.arch} {compiler.S.extra_flags} {build.extra_flags} {build.cpu_flags} {build.vect_flags} {build.hs_flag} {build.common_flags} {compiler.libs.c.flags} {includes} "{source_file}" -o "{object_file}"
 
 ## Create archives
 recipe.ar.pattern="{compiler.path}{compiler.ar.cmd}" {compiler.ar.flags} {compiler.ar.extra_flags} "{archive_file_path}" "{object_file}"
diff --git a/STM32F4/variants/generic_f407v/ld/bootloader_8004000.ld b/STM32F4/variants/generic_f407v/ld/bootloader_8004000.ld
new file mode 100644
index 000000000..677683e24
--- /dev/null
+++ b/STM32F4/variants/generic_f407v/ld/bootloader_8004000.ld
@@ -0,0 +1,21 @@
+/*
+ * STM32F4xx high density linker script for
+ * JTAG (bare metal, no bootloader) builds.
+ */
+
+MEMORY
+{
+  ccmram (rw): ORIGIN = 0x10000000, LENGTH = 64K
+  ram (rwx)  : ORIGIN = 0x20000000, LENGTH = 128K
+  rom (rx)   : ORIGIN = 0x08004000, LENGTH = 496K
+}
+
+/* GROUP(libcs3_stm32_high_density.a) */
+
+REGION_ALIAS("REGION_TEXT", rom);
+REGION_ALIAS("REGION_DATA", ram);
+REGION_ALIAS("REGION_BSS", ram);
+REGION_ALIAS("REGION_RODATA", rom);
+
+_FLASH_BUILD = 1;
+INCLUDE common.inc

From b1e1782019265992abf115a513be6facec68d259 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sun, 3 Sep 2017 11:00:16 +1000
Subject: [PATCH 181/307] Fix for map() function - supplied by @Pito

---
 STM32F1/cores/maple/wirish_math.h | 11 ++++++-----
 STM32F4/cores/maple/wirish_math.h | 11 ++++++-----
 2 files changed, 12 insertions(+), 10 deletions(-)

diff --git a/STM32F1/cores/maple/wirish_math.h b/STM32F1/cores/maple/wirish_math.h
index 9140d066e..b85253fb5 100644
--- a/STM32F1/cores/maple/wirish_math.h
+++ b/STM32F1/cores/maple/wirish_math.h
@@ -79,11 +79,12 @@ long random(long min, long max);
  * @param toEnd the end of the value's mapped range.
  * @return the mapped value.
  */
-static inline long map(long value, long fromStart, long fromEnd,
-                long toStart, long toEnd) {
-    return (value - fromStart) * (toEnd - toStart) / (fromEnd - fromStart) +
-        toStart;
-}
+ // Fix by Pito 9/2017
+  static inline int32_t map(int32_t value, int32_t fromStart, int32_t fromEnd,
+     int32_t toStart, int32_t toEnd) {
+     return ((int64_t)(value - fromStart) * (toEnd - toStart)) / (fromEnd - fromStart) +
+         toStart;
+ }
 
 #define PI          3.1415926535897932384626433832795
 #define HALF_PI     1.5707963267948966192313216916398
diff --git a/STM32F4/cores/maple/wirish_math.h b/STM32F4/cores/maple/wirish_math.h
index 0b8b22260..e0373728d 100644
--- a/STM32F4/cores/maple/wirish_math.h
+++ b/STM32F4/cores/maple/wirish_math.h
@@ -78,11 +78,12 @@ long random(long min, long max);
  * @param toEnd the end of the value's mapped range.
  * @return the mapped value.
  */
-static inline long map(long value, long fromStart, long fromEnd,
-                long toStart, long toEnd) {
-    return (value - fromStart) * (toEnd - toStart) / (fromEnd - fromStart) +
-        toStart;
-}
+ // Fix by Pito 9/2017
+  static inline int32_t map(int32_t value, int32_t fromStart, int32_t fromEnd,
+     int32_t toStart, int32_t toEnd) {
+     return ((int64_t)(value - fromStart) * (toEnd - toStart)) / (fromEnd - fromStart) +
+         toStart;
+ }
 
 #define PI          3.1415926535897932384626433832795
 #define HALF_PI     1.5707963267948966192313216916398

From 56abaa31735b0c7137cedef5484178cd0855866e Mon Sep 17 00:00:00 2001
From: victorpv <victor_pv@hotmail.com>
Date: Mon, 4 Sep 2017 10:41:58 -0500
Subject: [PATCH 182/307] Correction to upload issue in Sloeber

As discussed in http://stm32duino.com/viewtopic.php?f=41&t=2535
Changes to the Generic Boards options so the maple dfu option is the default one and Sloeber uploads correctly.
---
 STM32F1/boards.txt | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/STM32F1/boards.txt b/STM32F1/boards.txt
index 6d110d040..10379ec55 100644
--- a/STM32F1/boards.txt
+++ b/STM32F1/boards.txt
@@ -357,6 +357,8 @@ genericSTM32F103C.build.board=GENERIC_STM32F103C
 genericSTM32F103C.upload.use_1200bps_touch=false
 genericSTM32F103C.upload.file_type=bin
 genericSTM32F103C.upload.auto_reset=true
+genericSTM32F103C.upload.tool=maple_upload
+genericSTM32F103C.upload.protocol=maple_dfu
 
 ## STM32F103C8 -------------------------
 genericSTM32F103C.menu.device_variant.STM32F103C8=STM32F103C8 (20k RAM. 64k Flash)
@@ -454,6 +456,8 @@ genericSTM32F103R.build.board=GENERIC_STM32F103R
 genericSTM32F103R.upload.use_1200bps_touch=false
 genericSTM32F103R.upload.file_type=bin
 genericSTM32F103R.upload.auto_reset=true
+genericSTM32F103R.upload.tool=maple_upload
+genericSTM32F103R.upload.protocol=maple_dfu
 
 genericSTM32F103R.menu.device_variant.STM32F103R8=STM32F103R8 (20k RAM. 64k Flash)
 genericSTM32F103R.menu.device_variant.STM32F103R8.build.variant=generic_stm32f103r8
@@ -563,6 +567,8 @@ genericSTM32F103T.build.board=GENERIC_STM32F103T
 genericSTM32F103T.upload.use_1200bps_touch=false
 genericSTM32F103T.upload.file_type=bin
 genericSTM32F103T.upload.auto_reset=true
+genericSTM32F103T.upload.tool=maple_upload
+genericSTM32F103T.upload.protocol=maple_dfu
 
 ## STM32F103T8 -------------------------
 genericSTM32F103T.menu.device_variant.STM32F103T8=STM32F103T8 (20k RAM. 64k Flash)
@@ -655,6 +661,8 @@ genericSTM32F103V.build.board=GENERIC_STM32F103V
 genericSTM32F103V.upload.use_1200bps_touch=false
 genericSTM32F103V.upload.file_type=bin
 genericSTM32F103V.upload.auto_reset=true
+genericSTM32F103V.upload.tool=maple_upload
+genericSTM32F103V.upload.protocol=maple_dfu
 
 genericSTM32F103V.build.error_led_port=GPIOE
 genericSTM32F103V.build.error_led_pin=6
@@ -754,6 +762,8 @@ genericSTM32F103Z.build.board=GENERIC_STM32F103Z
 genericSTM32F103Z.upload.use_1200bps_touch=false
 genericSTM32F103Z.upload.file_type=bin
 genericSTM32F103Z.upload.auto_reset=true
+genericSTM32F103Z.upload.tool=maple_upload
+genericSTM32F103Z.upload.protocol=maple_dfu
 
 genericSTM32F103Z.menu.device_variant.STM32F103ZC=STM32F103ZC
 genericSTM32F103Z.menu.device_variant.STM32F103ZC.build.cpu_flags=-DMCU_STM32F103ZC

From 81100beeea63040ff429ac87420f1162bcaf909c Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Tue, 5 Sep 2017 17:03:16 +1000
Subject: [PATCH 183/307] Updated readme

---
 README.md | 1 +
 1 file changed, 1 insertion(+)

diff --git a/README.md b/README.md
index 9d167cf79..9493be94e 100644
--- a/README.md
+++ b/README.md
@@ -7,6 +7,7 @@ This software is experimental and a work in progress.
 Under no circumstances should these files be used in relation to any critical system(s).
 Use of these files is at your own risk.
 
+THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
 
 ## Summary:  
 This repo contains, the "Hardware" files to support STM32 based boards on Arduino version 1.8.x (some older versions may also work)  including [LeafLabs Maple, and Maple mini](http://www.leaflabs.com/about-maple/), and other generic STM32F103 boards  

From f769556e9a5d74161bba2daff09ea8d25ab216cc Mon Sep 17 00:00:00 2001
From: victorpv <victor_pv@hotmail.com>
Date: Mon, 11 Sep 2017 21:25:09 -0500
Subject: [PATCH 184/307] F1 SDIO initial version

---
 STM32F1/libraries/SDIO/SdioF1.cpp | 852 ++++++++++++++++++++++++++++++
 1 file changed, 852 insertions(+)
 create mode 100644 STM32F1/libraries/SDIO/SdioF1.cpp

diff --git a/STM32F1/libraries/SDIO/SdioF1.cpp b/STM32F1/libraries/SDIO/SdioF1.cpp
new file mode 100644
index 000000000..8957b37d3
--- /dev/null
+++ b/STM32F1/libraries/SDIO/SdioF1.cpp
@@ -0,0 +1,852 @@
+/* Arduino SdCard Library
+ * Copyright (C) 2016 by William Greiman
+ *
+ * This file is part of the Arduino SdSpiCard Library
+ *
+ * This Library is free software: you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * This Library is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with the Arduino SdSpiCard Library.  If not, see
+ * <http://www.gnu.org/licenses/>.
+ */
+
+#include "SdioF1.h"
+#include <libmaple/sdio.h>
+#include <libmaple/dma.h>
+#include <boards.h>
+
+
+#define USE_DEBUG_MODE 0
+#define USE_YIELD 0
+
+//==============================================================================
+//#define SDHC_PROCTL_DTW_4BIT 0x01
+#define CMD8_RETRIES 10
+#define BUSY_TIMEOUT_MILLIS 1500
+//==============================================================================
+#define CMD_RESP_NONE SDIO_CMD_WAIT_NO_RESP
+#define CMD_RESP_R1   SDIO_CMD_WAIT_SHORT_RESP // normal response
+#define CMD_RESP_R1b  SDIO_CMD_WAIT_SHORT_RESP // normal response + busy data line (optional)
+#define CMD_RESP_R2   SDIO_CMD_WAIT_LONG_RESP  // CID, CSD
+#define CMD_RESP_R3   SDIO_CMD_WAIT_SHORT_RESP // OCR register, response to ACMD41
+#define CMD_RESP_R6   SDIO_CMD_WAIT_SHORT_RESP // published RCA response, response to CMD3
+#define CMD_RESP_R7   SDIO_CMD_WAIT_SHORT_RESP // response to CMD8
+
+#define CMD0_XFERTYP    (uint16_t)( CMD0   | CMD_RESP_NONE )
+#define CMD2_XFERTYP    (uint16_t)( CMD2   | CMD_RESP_R2   )
+#define CMD3_XFERTYP    (uint16_t)( CMD3   | CMD_RESP_R6   )
+#define CMD6_XFERTYP    (uint16_t)( CMD6   | CMD_RESP_R1   )
+#define ACMD6_XFERTYP   (uint16_t)( ACMD6  | CMD_RESP_R1   )
+#define CMD7_XFERTYP    (uint16_t)( CMD7   | CMD_RESP_R1b  )
+#define CMD8_XFERTYP    (uint16_t)( CMD8   | CMD_RESP_R7   )
+#define CMD9_XFERTYP    (uint16_t)( CMD9   | CMD_RESP_R2   )
+#define CMD10_XFERTYP   (uint16_t)( CMD10  | CMD_RESP_R2   )
+#define CMD12_XFERTYP   (uint16_t)( CMD12  | CMD_RESP_R1b  )
+#define CMD13_XFERTYP   (uint16_t)( CMD13  | CMD_RESP_R1   )
+#define CMD17_XFERTYP   (uint16_t)( CMD17  | CMD_RESP_R1   )
+#define CMD18_XFERTYP   (uint16_t)( CMD18  | CMD_RESP_R1   )
+#define ACMD23_XFERTYP  (uint16_t)( ACMD23 | CMD_RESP_R1   )
+#define CMD24_XFERTYP   (uint16_t)( CMD24  | CMD_RESP_R1   )
+#define CMD25_XFERTYP   (uint16_t)( CMD25  | CMD_RESP_R1   )
+#define CMD32_XFERTYP   (uint16_t)( CMD32  | CMD_RESP_R1   )
+#define CMD33_XFERTYP   (uint16_t)( CMD32  | CMD_RESP_R1   )
+#define CMD38_XFERTYP   (uint16_t)( CMD38  | CMD_RESP_R1b  )
+#define ACMD41_XFERTYP  (uint16_t)( ACMD41 | CMD_RESP_R3   )
+
+#define CMD55_XFERTYP   (uint16_t)( CMD55  | CMD_RESP_R1   )
+
+//=============================================================================
+//static void enableGPIO(bool enable);
+//static void enableDmaIrs();
+static void initSDHC(void);
+static bool isBusyCMD13(void);
+static bool isBusyTransferComplete(void);
+//static bool isBusyCommandComplete();
+//static bool isBusyCommandInhibit();
+static bool readReg16(uint32_t xfertyp, void* data);
+//static void setSdclk(uint32_t kHzMax);
+static bool yieldTimeout(bool (*fcn)(void));
+static bool waitDmaStatus(void);
+static bool waitTimeout(bool (*fcn)(void));
+//-----------------------------------------------------------------------------
+#define TRX_RD 0
+#define TRX_WR 1
+static uint8_t m_dir = TRX_RD;
+static bool (*m_busyFcn)() = 0;
+static bool m_initDone = false;
+static uint32_t m_lba; // for raw non-DMA read(write)Start, read(write)Data, read(write)Stop
+static uint32_t m_cnt; // for raw non-DMA read(write)Start, read(write)Data, read(write)Stop
+static bool m_version2;
+static bool m_highCapacity;
+static uint8_t m_errorCode = SD_CARD_ERROR_INIT_NOT_CALLED;
+static uint32_t m_errorLine = 0;
+static uint32_t m_rca;
+//static volatile bool m_dmaBusy = false;
+static volatile uint32_t m_irqstat;
+static uint32_t m_sdClkKhz = 0;
+static uint32_t m_ocr;
+static cid_t m_cid;
+static csd_t m_csd;
+static uint32_t t = 0;
+//=============================================================================
+/*
+ *  Todo Remove this or change it, but rather remove since this can be checked with debugger.
+ */
+#if USE_DEBUG_MODE
+#define DBG_PRINT() { \
+	Serial.write('_'); Serial.print(__FUNCTION__); Serial.write('_'); Serial.print(__LINE__); Serial.print(": "); \
+	Serial.print("DMA->LISR: "); Serial.print(SDIO_DMA_DEV->regs->LISR, HEX); \
+	/*Serial.print("DMA->HISR: "); Serial.println(SDIO_DMA_DEV->regs->HISR, HEX);*/ \
+	Serial.print(", DMA->CR: "); Serial.print(SDIO_DMA_DEV->regs->STREAM[SDIO_DMA_CHANNEL].CR, HEX); \
+	Serial.print(", DMA->NDTR: "); Serial.print(SDIO_DMA_DEV->regs->STREAM[SDIO_DMA_CHANNEL].NDTR, HEX); \
+	/**/Serial.print(", DMA->PAR: "); Serial.print(SDIO_DMA_DEV->regs->STREAM[SDIO_DMA_CHANNEL].PAR, HEX); \
+	/**/Serial.print(", DMA->M0AR: "); Serial.print(SDIO_DMA_DEV->regs->STREAM[SDIO_DMA_CHANNEL].M0AR, HEX); \
+	Serial.print(", DMA->FCR: "); Serial.print(SDIO_DMA_DEV->regs->STREAM[SDIO_DMA_CHANNEL].FCR, HEX); \
+ \
+	/*Serial.print(" SDIO->POWER: "); Serial.println(SDIO->POWER, HEX);*/ \
+	Serial.print(", SDIO->CLKCR: "); Serial.print(SDIO->CLKCR, HEX); \
+	Serial.print(", SDIO->DTIMER: "); Serial.print(SDIO->DTIMER, HEX); \
+	Serial.print(", SDIO->DCTRL: "); Serial.print(SDIO->DCTRL, HEX); \
+	/**/Serial.print(", SDIO->DLEN: "); Serial.print(SDIO->DLEN); \
+	Serial.print(", SDIO->DCOUNT: "); Serial.print(SDIO->DCOUNT); \
+	Serial.print(", SDIO->STA: "); Serial.println(SDIO->STA, HEX); \
+	/*delay(1);*/ \
+}
+#define DBG_PIN PD0
+
+#else  // USE_DEBUG_MODE
+#define DBG_PRINT()
+#endif  // USE_DEBUG_MODE
+
+/*****************************************************************************/
+static void _panic(const char *message, uint32_t code)
+{
+	Serial.print(message); Serial.println(code, HEX);
+	//Block the execution with blinky leds
+	while (1);
+/*
+	pinMode(BOARD_LED_PIN, OUTPUT);
+	//pinMode(BOARD_LED2_PIN, OUTPUT);
+	while (1) {
+		digitalWrite(BOARD_LED_PIN, HIGH);
+		//digitalWrite(BOARD_LED2_PIN, LOW);
+		delay(250);
+		digitalWrite(BOARD_LED_PIN, LOW);
+		//digitalWrite(BOARD_LED2_PIN, HIGH);
+		delay(250);
+	}
+	*/
+}
+/*===========================================================================*/
+/*
+ * Todo: Change the DMA parts so it works with F1 DMA, but since yield is disabled, we can ignore it for now.
+*/
+    
+#if USE_YIELD
+void yield(void)
+{
+	uint32_t val = SDIO->STA;
+	if ( val & SDIO_STA_TRX_ERROR_FLAGS ) {
+		Serial.print("SDIO ERROR:: SDIO->CLKCR: "); Serial.print(SDIO->CLKCR, HEX); \
+		Serial.print(", SDIO->DTIMER: "); Serial.print(SDIO->DTIMER, HEX); \
+		Serial.print(", SDIO->DCTRL: "); Serial.print(SDIO->DCTRL, HEX); \
+		Serial.print(", SDIO->DLEN: "); Serial.print(SDIO->DLEN); \
+		Serial.print(", SDIO->DCOUNT: "); Serial.print(SDIO->DCOUNT); \
+		Serial.print(", SDIO->STA: "); Serial.print(SDIO->STA, HEX); \
+		Serial.print(", SDIO->RESP0: "); Serial.println(SDIO->RESP[0], HEX); \
+		if (val & SDIO_STA_STBITERR) Serial.print(" STBITERR");
+		if (val & SDIO_STA_RXOVERR) Serial.print(" RXOVERR");
+		if (val & SDIO_STA_TXUNDERR) Serial.print(" TXUNDERR");
+		if (val & SDIO_STA_DTIMEOUT) Serial.print(" DTIMEOUT");
+		if (val & SDIO_STA_DCRCFAIL) Serial.print(" DCRCFAIL");
+		_panic(" - SDIO: Data Transmission Error ", val);
+	}
+
+	val = dma_get_isr_bits(SDIO_DMA_DEV, SDIO_DMA_CHANNEL);
+	if ( val & DMA_ISR_FEIF ) {
+		val ^= DMA_ISR_FEIF;
+		dma_clear_isr_bits(SDIO_DMA_DEV, SDIO_DMA_CHANNEL);
+	}
+	if ( val ) {
+		if (val & DMA_ISR_TEIF) Serial.print(" TEIF");
+		if (val & DMA_ISR_DMEIF) Serial.print(" DMEIF");
+		//if (val & DMA_ISR_FEIF) Serial.print(" FEIF");
+		_panic(" - DMA: Data Transmission Error ", val);
+	}
+	//Serial.write('.');
+}
+#endif
+//=============================================================================
+// Error function and macro.
+inline bool setSdErrorCode(uint8_t code, uint32_t line) {
+  m_errorCode = code;
+  m_errorLine = line;
+  return false;  // setSdErrorCode
+}
+#define sdError(code) setSdErrorCode(code, __LINE__)
+//=============================================================================
+/* ISR
+void sdhc_isr() {
+  SDHC_IRQSIGEN = 0;
+  m_irqstat = SDHC_IRQSTAT;
+  SDHC_IRQSTAT = m_irqstat;
+  m_dmaBusy = false;
+}*/
+//=============================================================================
+// Static functions.
+//-----------------------------------------------------------------------------
+static bool cardCommand(uint16_t xfertyp, uint32_t arg)
+{
+#if USE_DEBUG_MODE==2
+	Serial.print("cardCommand: "); Serial.print(xfertyp&SDIO_CMD_CMDINDEX); Serial.print(", arg: "); Serial.print(arg, HEX);
+#endif
+	uint8_t resp = sdio_cmd_send(xfertyp, arg); // returns non-zero if fails, zero if OK
+#if USE_DEBUG_MODE==2
+	Serial.print(", resp: "); Serial.print(resp, HEX);
+	Serial.print(", SDIO->STA: "); Serial.print(SDIO->STA, HEX); Serial.print(", cmd_resp: "); Serial.print(SDIO->RESP[0], HEX);
+	if ( (xfertyp&SDIO_CMD_WAIT_LONG_RESP)==SDIO_CMD_WAIT_LONG_RESP ) {
+		Serial.print(", "); Serial.print(SDIO->RESP[1], HEX); Serial.print(", "); Serial.print(SDIO->RESP[2], HEX); Serial.print(", "); Serial.println(SDIO->RESP[3], HEX);
+	} else Serial.println();
+#endif
+	return resp; // return non-zero when OK
+}
+//-----------------------------------------------------------------------------
+static bool cardAcmd(uint32_t rca, uint32_t xfertyp, uint32_t arg) {
+  return cardCommand(CMD55_XFERTYP, rca) && cardCommand((uint16_t)xfertyp, arg);
+}
+/*---------------------------------------------------------------------------*/
+static bool cardCMD6(uint32_t arg, uint8_t* status) {
+  // CMD6 returns 64 bytes.
+  // use polling only for the moment
+	if (waitTimeout(isBusyCMD13)) {
+		return sdError(SD_CARD_ERROR_CMD13);
+	}
+	// get the 64 bytes over data lines
+	sdio_setup_transfer(80000, 64, (SDIO_BLOCKSIZE_64 | SDIO_DIR_RX | SDIO_DCTRL_DTEN));
+
+	cardCommand(CMD6_XFERTYP, arg);
+
+	// wait data Rx response
+	if (waitTimeout(isBusyTransferComplete)) {
+		return sdError(SD_CARD_ERROR_CMD6);
+	}
+DBG_PRINT();
+	// copy 64 bytes as 16 words from FIFO to buffer
+	for (uint8_t i=0; i<16; i++) {
+		*(uint32_t*)(&status[i<<2]) = SDIO->FIFO;
+	}
+	//SDIO->DCTRL = 0; // disable data controller
+
+#if USE_DEBUG_MODE
+	Serial.print("read data: "); for (uint8_t i=0; i<17; i++) { Serial.print(status[i], HEX); Serial.print(", "); } Serial.println();
+#endif
+return true;
+}
+//-----------------------------------------------------------------------------
+static void initSDHC(void)
+{
+	sdio_begin();
+	DBG_PRINT();
+}
+/*---------------------------------------------------------------------------*/
+static bool isBusyCMD13(void) {
+  if (!cardCommand(CMD13_XFERTYP, m_rca)) { // SEND_STATUS
+    // Caller will timeout.
+    return true;
+  }
+  return !(SDIO->RESP[0] & CARD_STATUS_READY_FOR_DATA);
+}
+/*---------------------------------------------------------------------------*/
+static bool isBusyDMA(void)
+{
+	uint8_t isr = dma_get_isr_bits(SDIO_DMA_DEV, SDIO_DMA_CHANNEL);
+    isr &= DMA_ISR_TCIF | DMA_ISR_TEIF;
+	//if (isr&DMA_ISR_TCIF) dma_disable(SDIO_DMA_DEV, SDIO_DMA_CHANNEL);
+	return !(isr); // ignore transfer error flag
+}
+/*---------------------------------------------------------------------------*/
+static bool isBusyTransferComplete(void)
+{
+	uint32_t mask = SDIO->STA &(SDIO_STA_DATAEND | SDIO_STA_TRX_ERROR_FLAGS);
+#if USE_DEBUG_MODE
+	if ( mask & SDIO_STA_TRX_ERROR_FLAGS ) {
+		Serial.print("XFER ERROR: SDIO->STA: "); Serial.print(SDIO->STA, HEX);
+		if (mask & SDIO_STA_STBITERR) Serial.print(" STBITERR");
+		if (mask & SDIO_STA_RXOVERR)  Serial.print(" RXOVERR");
+		if (mask & SDIO_STA_TXUNDERR) Serial.print(" TXUNDERR");
+		if (mask & SDIO_STA_DTIMEOUT) Serial.print(" DTIMEOUT");
+		if (mask & SDIO_STA_DCRCFAIL) Serial.print(" DCRCFAIL");
+		Serial.println();
+	}
+#endif
+	if (mask) {
+		dma_disable(SDIO_DMA_DEV, SDIO_DMA_CHANNEL);
+		return false;
+	}
+	return true;
+}
+/*---------------------------------------------------------------------------*/
+static void trxStart(uint8_t* buf, uint32_t n, uint8_t dir)
+{
+	m_dir = dir;
+	uint32_t flags = (SDIO_BLOCKSIZE_512 | SDIO_DCTRL_DTEN);
+	if (dir==TRX_RD) flags |= SDIO_DIR_RX;
+	// setup SDIO to transfer n blocks of 512 bytes
+	sdio_setup_transfer(0x00FFFFFF, n, flags);
+}
+/*---------------------------------------------------------------------------*/
+static bool trxStop()
+{
+	if (!cardCommand(CMD12_XFERTYP, 0)) {
+		return sdError(SD_CARD_ERROR_CMD12);
+	}
+	if ( t ) {
+		Serial.print(", in "); Serial.println(millis()-t);
+		t = 0;
+	}
+	return true;
+}
+/*---------------------------------------------------------------------------*/
+static bool dmaTrxStart(uint8_t* buf, uint32_t n, uint8_t dir)
+{
+	m_dir = dir;
+	if ((3 & (uint32_t)buf) || n == 0) { // check alignment
+		_panic("- transferStart: unaligned buffer address ", (uint32_t)buf);
+		return sdError(SD_CARD_ERROR_DMA);
+	}
+	if (dir==TRX_RD && yieldTimeout(isBusyCMD13)) {
+		return sdError(SD_CARD_ERROR_CMD13);
+	}
+	uint32_t flags = (SDIO_BLOCKSIZE_512 | SDIO_DCTRL_DMAEN | SDIO_DCTRL_DTEN);
+	if (dir==TRX_RD) flags |= SDIO_DIR_RX;
+	// setup SDIO to transfer n blocks of 512 bytes
+	sdio_setup_transfer(0x00FFFFFF, n, flags);
+	// setup SDIO_DMA_DEV stream 3 channel 4
+	/*
+	 * Moved to begin.
+	 */
+	//dma_init(SDIO_DMA_DEV);
+	/*
+	* Todo. Check this, channel must be disabled to change DMA priority, and seems like channel is not completing transfers
+	 */
+	//dma_set_priority(SDIO_DMA_DEV, SDIO_DMA_CHANNEL, DMA_PRIORITY_VERY_HIGH);
+	flags = (DMA_MINC_MODE);
+	// not extra flag if read
+	if (dir!=TRX_RD) flags |= DMA_FROM_MEM;// write
+	dma_setup_transfer(SDIO_DMA_DEV, SDIO_DMA_CHANNEL, &SDIO->FIFO, DMA_SIZE_32BITS,  buf, DMA_SIZE_32BITS, flags);
+	dma_set_num_transfers(SDIO_DMA_DEV, SDIO_DMA_CHANNEL, n>>2); // F1 DMA controller counts each word as 1 data item.
+	//dma_set_fifo_flags(SDIO_DMA_DEV, SDIO_DMA_CHANNEL, (DMA_FCR_DMDIS | DMA_FCR_FTH_FULL)); // disable direct mode | threshold FULL
+	dma_clear_isr_bits(SDIO_DMA_DEV, SDIO_DMA_CHANNEL);
+	dma_enable(SDIO_DMA_DEV, SDIO_DMA_CHANNEL);
+	return true;
+}
+/*---------------------------------------------------------------------------*/
+static bool dmaTrxEnd(bool multi_block)
+{
+	if ( !waitDmaStatus() ) {
+		DBG_PRINT();
+		return sdError(SD_CARD_ERROR_DMA);
+	}
+	if ( waitTimeout(isBusyTransferComplete) ) {
+		if (m_dir==TRX_RD)
+			return sdError(SD_CARD_ERROR_READ_TIMEOUT);
+		else
+			return sdError(SD_CARD_ERROR_WRITE_TIMEOUT);
+	}
+	if (multi_block) {
+		return trxStop();
+	} else {
+		if ( t ) {
+			Serial.print(", in "); Serial.println(millis()-t);
+			t = 0;
+		}
+		return true;
+	}
+}
+//-----------------------------------------------------------------------------
+// Read 16 byte CID or CSD register.
+static bool readReg16(uint32_t xfertyp, void* data)
+{
+  uint8_t* d = reinterpret_cast<uint8_t*>(data);
+  if (!cardCommand(xfertyp, m_rca)) {
+    return false;  // Caller will set errorCode.
+  }
+  *(uint32_t*)(&d[0])  = __builtin_bswap32(SDIO->RESP[0]);
+  *(uint32_t*)(&d[4])  = __builtin_bswap32(SDIO->RESP[1]);
+  *(uint32_t*)(&d[8])  = __builtin_bswap32(SDIO->RESP[2]);
+  *(uint32_t*)(&d[12]) = __builtin_bswap32(SDIO->RESP[3]);
+  d[15] = 0;
+  return true;
+}
+/*---------------------------------------------------------------------------*/
+// Return true if timeout occurs.
+static bool yieldTimeout(bool (*fcn)()) {
+  uint32_t m = millis();
+  while (fcn()) {
+    if ((millis() - m) > BUSY_TIMEOUT_MILLIS) {
+      return true;
+    }
+    yield();
+  }
+  return false;  // Caller will set errorCode.
+}
+/*---------------------------------------------------------------------------*/
+static bool waitDmaStatus(void)
+{
+  if (yieldTimeout(isBusyDMA)) {
+    return false;  // Caller will set errorCode.
+  }
+  return true;
+}
+/*---------------------------------------------------------------------------*/
+// Return true if timeout occurs.
+static bool waitTimeout(bool (*fcn)(void)) {
+  uint32_t m = millis();
+  while (fcn()) {
+    if ((millis() - m) > BUSY_TIMEOUT_MILLIS) {
+      return true;
+    }
+	delayMicroseconds(1);
+  }
+  return false;  // Caller will set errorCode.
+}
+
+uint32_t aligned[128]; // temporary buffer for misaligned buffers
+//=============================================================================
+bool SdioCard::begin(void)
+{
+  m_initDone = false;
+  m_errorCode = SD_CARD_ERROR_NONE;
+  m_highCapacity = false;
+  m_version2 = false;
+
+#if USE_DEBUG_MODE
+pinMode(DBG_PIN, OUTPUT);
+digitalWrite(DBG_PIN, HIGH);
+delay(100);
+#endif
+  // initialize controller.
+  initSDHC();
+
+  // initialize DMA device
+	dma_init(SDIO_DMA_DEV);
+	dma_disable(SDIO_DMA_DEV, SDIO_DMA_CHANNEL); // Disable DMA in case it was left enabled from a previous use.
+	/*
+	 * Todo. Check this, channel must be disabled to change DMA priority, and seems like channel is not completing transfers
+	 */
+	dma_set_priority(SDIO_DMA_DEV, SDIO_DMA_CHANNEL, DMA_PRIORITY_VERY_HIGH);
+
+  if (!cardCommand(CMD0_XFERTYP, 0)) {
+    return sdError(SD_CARD_ERROR_CMD0);
+  }
+  // Try several times for case of reset delay.
+  for (uint32_t i = 0; i < CMD8_RETRIES; i++) {
+    if (cardCommand(CMD8_XFERTYP, 0X1AA)) {
+      if (SDIO->RESP[0] != 0X1AA) {
+        return sdError(SD_CARD_ERROR_CMD8);
+      }
+      m_version2 = true;
+      break;
+    }
+  }
+  uint32_t arg = m_version2 ? 0X40300000 : 0x00300000;
+  uint32_t m = millis();
+  do {
+    if (!cardAcmd(0, ACMD41_XFERTYP, arg) ||
+       ((millis() - m) > BUSY_TIMEOUT_MILLIS)) {
+      return sdError(SD_CARD_ERROR_ACMD41);
+    }
+  } while ((SDIO->RESP[0] & 0x80000000) == 0);
+
+  m_ocr = SDIO->RESP[0];
+  if (m_ocr & 0x40000000) {
+    // Is high capacity.
+    m_highCapacity = true;
+  }
+  if (!cardCommand(CMD2_XFERTYP, 0)) {
+    return sdError(SD_CARD_ERROR_CMD2);
+  }
+  if (!cardCommand(CMD3_XFERTYP, 0)) {
+    return sdError(SD_CARD_ERROR_CMD3);
+  }
+  m_rca = SDIO->RESP[0] & 0xFFFF0000;
+  if (!readReg16(CMD9_XFERTYP, &m_csd)) {
+    return sdError(SD_CARD_ERROR_CMD9);
+  }
+  if (!readReg16(CMD10_XFERTYP, &m_cid)) {
+    return sdError(SD_CARD_ERROR_CMD10);
+  }
+  if (!cardCommand(CMD7_XFERTYP, m_rca)) {
+    return sdError(SD_CARD_ERROR_CMD7);
+  }
+  // Set card to bus width four.
+  /*
+  if (!cardAcmd(m_rca, ACMD6_XFERTYP, 2)) {
+    return sdError(SD_CARD_ERROR_ACMD6);
+  }
+  sdio_set_dbus_width(SDIO_CLKCR_WIDBUS_4BIT);
+	*/
+
+  // Determine if High Speed mode is supported and set frequency.
+  uint8_t status[64];
+  // see "Physical Layer Simplified Specification Version 6.00", chapter 4.3.10, Table 4-13.
+  // Support Bits of Functions in Function Group 1: bits 415:400, which are bytes [12][13]
+  // Function Selection of Function Group 1: bits 379:376, which is low nibble of byte [16]
+  if (cardCMD6(0X00FFFFFF, status) && (2 & status[13]) &&
+      cardCMD6(0X80FFFFF1, status) && (status[16] & 0XF) == 1) {
+	//Serial.println("\n*** 50MHz clock supported ***");
+  } else {
+	//_panic("*** Only 25MHz clock supported! ***", 0);
+  }
+
+  /*
+   * Todo Raise clock to 24Mhz once transfers work
+   */
+  m_sdClkKhz = 24000;	// set clock to 24MHz
+  sdio_set_clock(m_sdClkKhz*1000);
+
+  m_initDone = true;
+  return true;
+}
+//-----------------------------------------------------------------------------
+uint32_t SdioCard::cardSize(void) {
+  return sdCardCapacity(&m_csd);
+}
+/*---------------------------------------------------------------------------*/
+bool SdioCard::erase(uint32_t firstBlock, uint32_t lastBlock) {
+  // check for single block erase
+  if (!m_csd.v1.erase_blk_en) {
+    // erase size mask
+    uint8_t m = (m_csd.v1.sector_size_high << 1) | m_csd.v1.sector_size_low;
+    if ((firstBlock & m) != 0 || ((lastBlock + 1) & m) != 0) {
+      // error card can't erase specified area
+      return sdError(SD_CARD_ERROR_ERASE_SINGLE_BLOCK);
+    }
+  }
+  if (!m_highCapacity) {
+    firstBlock <<= 9;
+    lastBlock <<= 9;
+  }
+  if (!cardCommand(CMD32_XFERTYP, firstBlock)) {
+    return sdError(SD_CARD_ERROR_CMD32);
+  }
+  if (!cardCommand(CMD33_XFERTYP, lastBlock)) {
+     return sdError(SD_CARD_ERROR_CMD33);
+  }
+  if (!cardCommand(CMD38_XFERTYP, 0)) {
+    return sdError(SD_CARD_ERROR_CMD38);
+  }
+  if (waitTimeout(isBusyCMD13)) {
+    return sdError(SD_CARD_ERROR_ERASE_TIMEOUT);
+  }
+  return true;
+}
+//-----------------------------------------------------------------------------
+uint8_t SdioCard::errorCode() {
+  return m_errorCode;
+}
+//-----------------------------------------------------------------------------
+uint32_t SdioCard::errorData() {
+  return m_irqstat;
+}
+//-----------------------------------------------------------------------------
+uint32_t SdioCard::errorLine() {
+  return m_errorLine;
+}
+//-----------------------------------------------------------------------------
+bool SdioCard::isBusy() {
+  return m_busyFcn ? m_busyFcn() : m_initDone && isBusyCMD13();
+}
+//-----------------------------------------------------------------------------
+uint32_t SdioCard::kHzSdClk() {
+  return m_sdClkKhz;
+}
+/*---------------------------------------------------------------------------*/
+bool SdioCard::readBlock(uint32_t lba, uint8_t* buf)
+{
+#if USE_DEBUG_MODE
+	Serial.print("readBlock: ");  Serial.println(lba); //Serial.print(", buf: "); Serial.println((uint32_t)buf, HEX);
+#endif
+	// prepare SDIO and DMA for data read transfer
+	dmaTrxStart((uint32_t)buf & 3 ? (uint8_t*)aligned : buf, 512, TRX_RD);
+	// send command to start data transfer
+	if ( !cardCommand(CMD17_XFERTYP, (m_highCapacity ? lba : 512*lba)) ) {
+		return sdError(SD_CARD_ERROR_CMD17);
+	}
+	if ( dmaTrxEnd(0)) {
+		if ( (uint32_t)buf & 3 ) {
+			//memcpy(buf, aligned, 512);
+			register uint8_t * dst = buf;
+			register uint8_t * src = (uint8_t *)aligned;
+			register uint16_t i = 64;
+			while ( i-- ) { // do 8 byte copies, is much faster than single byte copy
+				*dst++ = *src++; *dst++ = *src++; *dst++ = *src++; *dst++ = *src++;
+				*dst++ = *src++; *dst++ = *src++; *dst++ = *src++; *dst++ = *src++;
+			}
+		}
+		return true;
+	}
+	return false;
+}
+/*---------------------------------------------------------------------------*/
+bool SdioCard::readBlocks(uint32_t lba, uint8_t* buf, size_t n)
+{
+#if USE_DEBUG_MODE
+	Serial.print("readBlocks: ");  Serial.print(lba);
+	//Serial.print(", buf: "); Serial.print((uint32_t)buf, HEX);
+	Serial.print(", "); Serial.println(n);
+#endif
+	if ((uint32_t)buf & 3) {
+		for (size_t i = 0; i < n; i++, lba++, buf += 512) {
+			if (!readBlock(lba, buf)) {
+				return false;  // readBlock will set errorCode.
+			}
+		}
+		return true;
+	}
+	// prepare SDIO and DMA for data read transfer
+	dmaTrxStart(buf, 512*n, TRX_RD);
+	// send command to start data transfer
+	if ( !cardCommand(CMD18_XFERTYP, (m_highCapacity ? lba : 512*lba)) ) {
+		return sdError(SD_CARD_ERROR_CMD18);
+	}
+	return dmaTrxEnd(1);
+}
+//-----------------------------------------------------------------------------
+bool SdioCard::readCID(void* cid) {
+  memcpy(cid, &m_cid, 16);
+  return true;
+}
+//-----------------------------------------------------------------------------
+bool SdioCard::readCSD(void* csd) {
+  memcpy(csd, &m_csd, 16);
+  return true;
+}
+/*---------------------------------------------------------------------------*/
+bool SdioCard::readData(uint8_t *dst)
+{
+	//Serial.print("readData: "); Serial.print(m_lba); Serial.print(", m_cnt: "); Serial.println(m_cnt);
+	if ( m_cnt==0 ) return false;
+	if (yieldTimeout(isBusyCMD13)) { // wait for previous transmission end
+		return sdError(SD_CARD_ERROR_CMD13);
+	}
+	// non-DMA block read
+	trxStart(dst, 512, TRX_RD);
+	// send command to start data transfer
+	if ( !cardCommand(CMD17_XFERTYP, (m_highCapacity ? m_lba : 512*m_lba)) ) {
+		return sdError(SD_CARD_ERROR_CMD17);
+	}
+	// Receive a data block from the SDIO
+	register uint32_t STA; // to speed up SDIO flags checking
+	register uint16_t cnt = 512;
+	register uint32_t * ptr = (uint32_t *)dst;
+	// ----> TIME CRITICAL SECTION BEGIN <----
+	do {
+		STA = SDIO->STA;
+		if (STA & SDIO_STA_RXFIFOHF) {
+			// Receive FIFO half full, there are at least 8 words in it
+			noInterrupts();
+			*ptr++ = SDIO->FIFO; *ptr++ = SDIO->FIFO; *ptr++ = SDIO->FIFO; *ptr++ = SDIO->FIFO;
+			*ptr++ = SDIO->FIFO; *ptr++ = SDIO->FIFO; *ptr++ = SDIO->FIFO; *ptr++ = SDIO->FIFO;
+			interrupts();
+			cnt -= 8;
+		}
+	} while ( !(STA & (SDIO_STA_DATAEND | SDIO_STA_TRX_ERROR_FLAGS)) );
+	// <---- TIME CRITICAL SECTION END ---->
+
+	// read data still available in FIFO
+	while ( (SDIO->STA & SDIO_STA_RXDAVL) && (cnt--) ) {
+		*ptr++ = SDIO->FIFO;
+	}
+	// check error, temporary stuff, remove for final version
+	if ( SDIO->STA & SDIO_STA_TRX_ERROR_FLAGS ) {
+		_panic("ERROR: non-DMA read error ", SDIO->STA);
+		return false;
+	}
+	m_lba++;
+	m_cnt--;
+	return !(SDIO->STA&SDIO_STA_TRX_ERROR_FLAGS);
+}
+//-----------------------------------------------------------------------------
+bool SdioCard::readOCR(uint32_t* ocr) {
+  *ocr = m_ocr;
+  return true;
+}
+//-----------------------------------------------------------------------------
+bool SdioCard::readStart(uint32_t lba)
+{
+  m_lba = lba;
+  m_cnt = 1024;
+  return true;
+}
+/*---------------------------------------------------------------------------*/
+// SDHC will do Auto CMD12 after count blocks.
+bool SdioCard::readStart(uint32_t lba, uint32_t count)
+{
+	//Serial.print("readStart: "); Serial.print(lba); Serial.print(", cnt: "); Serial.println(count);
+  m_lba = lba;
+  m_cnt = count;
+  return true;
+}
+/*---------------------------------------------------------------------------*/
+bool SdioCard::readStop()
+{
+	//Serial.println("readStop.");
+  m_lba = 0;
+  m_cnt = 0;
+  return true;
+}
+//-----------------------------------------------------------------------------
+bool SdioCard::syncBlocks() {
+  return true;
+}
+//-----------------------------------------------------------------------------
+uint8_t SdioCard::type() {
+  return  m_version2 ? m_highCapacity ?
+          SD_CARD_TYPE_SDHC : SD_CARD_TYPE_SD2 : SD_CARD_TYPE_SD1;
+}
+/*---------------------------------------------------------------------------*/
+bool SdioCard::writeBlock(uint32_t lba, const uint8_t* buf)
+{
+#if USE_DEBUG_MODE
+	Serial.print("writeBlock: ");  Serial.println(lba); //Serial.print(", buf: "); Serial.println((uint32_t)buf, HEX);
+#endif
+	uint8_t * ptr = (uint8_t *)buf;
+	if (3 & (uint32_t)ptr) {
+		Serial.print("writeBlock: "); Serial.print(lba);
+		Serial.print(", buf: "); Serial.print((uint32_t)ptr, HEX);
+		//memcpy(aligned, buf, 512);
+		register uint8_t * src = (uint8_t *)ptr;
+		ptr = (uint8_t *)aligned;
+		register uint8_t * dst = ptr;
+		register uint16_t i = 64;
+		while ( i-- ) { // do 8 byte copies, is much faster than single byte copy
+			*dst++ = *src++; *dst++ = *src++; *dst++ = *src++; *dst++ = *src++;
+			*dst++ = *src++; *dst++ = *src++; *dst++ = *src++; *dst++ = *src++;
+		}
+	}
+	if (yieldTimeout(isBusyCMD13)) { // wait for previous transmission end
+		return sdError(SD_CARD_ERROR_CMD13);
+	}
+	// send command to start data transfer
+	if ( !cardCommand(CMD24_XFERTYP, (m_highCapacity ? lba : 512*lba)) ) {
+		return sdError(SD_CARD_ERROR_CMD24);
+	}
+	// prepare SDIO and DMA for data transfer
+	dmaTrxStart(ptr, 512, TRX_WR); // 1 block, write transfer
+
+	return dmaTrxEnd(0);
+}
+/*---------------------------------------------------------------------------*/
+bool SdioCard::writeBlocks(uint32_t lba, const uint8_t* buf, size_t n)
+{
+#if USE_DEBUG_MODE
+	Serial.print("writeBlocks: ");  Serial.print(lba);
+	//Serial.print(", buf: "); Serial.print((uint32_t)buf, HEX);
+	Serial.print(", "); Serial.println(n);
+#endif
+	if (3 & (uint32_t)buf) { // misaligned buffer address, write single blocks
+		for (size_t i = 0; i < n; i++, lba++, buf += 512) {
+			if (!writeBlock(lba, buf)) {
+				return false;  // writeBlock will set errorCode.
+			}
+		}
+		return true;
+	}
+	if (yieldTimeout(isBusyCMD13)) {
+		return sdError(SD_CARD_ERROR_CMD13);
+	}
+#if 0
+	// set number of blocks to write - this can speed up block write
+	if ( !cardAcmd(m_rca, ACMD23_XFERTYP, n) ) {
+		return sdError(SD_CARD_ERROR_ACMD23);
+	}
+#endif
+	// send command to start data transfer
+	if ( !cardCommand(CMD25_XFERTYP, (m_highCapacity ? lba : 512*lba)) ) {
+		return sdError(SD_CARD_ERROR_CMD25);
+	}
+	// prepare SDIO and DMA for data transfer
+	dmaTrxStart((uint8_t *)buf, 512*n, TRX_WR); // n blocks, write transfer
+
+	return dmaTrxEnd(1);
+}
+/*---------------------------------------------------------------------------*/
+bool SdioCard::writeData(const uint8_t* src)
+{
+	//Serial.print("writeData: "); Serial.print(m_lba); Serial.print(", cnt: "); Serial.println(m_cnt);
+	if ( !m_cnt ) return false;
+	if (yieldTimeout(isBusyCMD13)) { // wait for previous transmission end
+		return sdError(SD_CARD_ERROR_CMD13);
+	}
+	// send command to start block data transfer
+	if ( !cardCommand(CMD24_XFERTYP, (m_highCapacity ? m_lba : 512*m_lba)) ) {
+		return sdError(SD_CARD_ERROR_CMD24);
+	}
+	// non-DMA block write
+	trxStart((uint8_t*)src, 512, TRX_WR);
+	// Receive a data block from the SDIO
+	register uint32_t STA; // to speed up SDIO flags checking
+	register uint16_t cnt = 512;
+	register uint32_t * ptr = (uint32_t*)src;
+	// pre-fill up the FIFO with 32 words
+	noInterrupts();
+	while ( (cnt--)>(512-32) ) SDIO->FIFO = *ptr++;
+	interrupts();
+	// ----> TIME CRITICAL SECTION BEGIN <----
+	do {
+		STA = SDIO->STA;
+		if (STA & SDIO_STA_TXFIFOHE) {
+			// Transmit FIFO half empty, fill up the remaining 16 words
+			noInterrupts();
+			SDIO->FIFO = *ptr++; SDIO->FIFO = *ptr++; SDIO->FIFO = *ptr++; SDIO->FIFO = *ptr++;
+			SDIO->FIFO = *ptr++; SDIO->FIFO = *ptr++; SDIO->FIFO = *ptr++; SDIO->FIFO = *ptr++;
+			SDIO->FIFO = *ptr++; SDIO->FIFO = *ptr++; SDIO->FIFO = *ptr++; SDIO->FIFO = *ptr++;
+			SDIO->FIFO = *ptr++; SDIO->FIFO = *ptr++; SDIO->FIFO = *ptr++; SDIO->FIFO = *ptr++;
+			interrupts();
+			cnt -= 16;
+		}
+	} while ( !(STA & (SDIO_STA_DATAEND | SDIO_STA_TRX_ERROR_FLAGS)) && cnt);
+	// <---- TIME CRITICAL SECTION END ---->
+	if ( waitTimeout(isBusyTransferComplete) ) {
+		return sdError(SD_CARD_ERROR_WRITE_TIMEOUT);
+	}
+	m_lba++;
+	m_cnt--;
+	if (SDIO->STA&SDIO_STA_TRX_ERROR_FLAGS) {
+		_panic("writeData error: ", SDIO->STA);
+	}
+	return !(SDIO->STA&SDIO_STA_TRX_ERROR_FLAGS);
+}
+//-----------------------------------------------------------------------------
+bool SdioCard::writeStart(uint32_t lba)
+{
+  m_lba = lba;
+  m_cnt = 1024;
+  return true;
+}
+/*---------------------------------------------------------------------------*/
+// SDHC will do Auto CMD12 after count blocks.
+bool SdioCard::writeStart(uint32_t lba, uint32_t count)
+{
+	//Serial.print("writeStart: "); Serial.print(lba); Serial.print(", cnt: "); Serial.println(count);
+  m_lba = lba;
+  m_cnt = count;
+  return true;
+}
+/*---------------------------------------------------------------------------*/
+bool SdioCard::writeStop()
+{
+	//Serial.println("writeStop.");
+  m_lba = 0;
+  m_cnt = 0;
+  return true;
+}

From 434cb255a56197ab2e686ba04c2ea281ce46ab4f Mon Sep 17 00:00:00 2001
From: victorpv <victor_pv@hotmail.com>
Date: Mon, 11 Sep 2017 21:26:50 -0500
Subject: [PATCH 185/307] F1 SDIO

---
 STM32F1/libraries/SDIO/SdioF1.h | 7 +++++++
 1 file changed, 7 insertions(+)
 create mode 100644 STM32F1/libraries/SDIO/SdioF1.h

diff --git a/STM32F1/libraries/SDIO/SdioF1.h b/STM32F1/libraries/SDIO/SdioF1.h
new file mode 100644
index 000000000..c995b1c5c
--- /dev/null
+++ b/STM32F1/libraries/SDIO/SdioF1.h
@@ -0,0 +1,7 @@
+
+#ifndef _SDIOF4_H_
+#define _SDIOF4_H_
+
+#include <SdFat.h>
+
+#endif

From 7e1cc92d237ea809b715325cab2aae8366af7b3e Mon Sep 17 00:00:00 2001
From: victorpv <victor_pv@hotmail.com>
Date: Mon, 11 Sep 2017 21:28:07 -0500
Subject: [PATCH 186/307] SDIO

---
 .../system/libmaple/include/libmaple/sdio.h   | 270 ++++++++++++++++++
 1 file changed, 270 insertions(+)
 create mode 100644 STM32F1/system/libmaple/include/libmaple/sdio.h

diff --git a/STM32F1/system/libmaple/include/libmaple/sdio.h b/STM32F1/system/libmaple/include/libmaple/sdio.h
new file mode 100644
index 000000000..dec31c8b7
--- /dev/null
+++ b/STM32F1/system/libmaple/include/libmaple/sdio.h
@@ -0,0 +1,270 @@
+/******************************************************************************
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file sdio.h
+ * @brief Secure digital input/output interface.
+ */
+
+#ifndef _SDIO_H_
+#define _SDIO_H_
+
+#include <libmaple/libmaple_types.h>
+#include <libmaple/stm32.h>
+#include <libmaple/gpio.h>
+
+
+/*
+#include <libmaple/rcc.h>
+#include <libmaple/nvic.h>
+
+//#include <boards.h>
+#include <stdint.h>
+//#include <wirish.h>
+ */
+
+#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
+
+/*
+ * DMA controller and channel used in STM32F103
+ */
+
+#define SDIO_DMA_DEV        DMA2
+#define SDIO_DMA_CHANNEL    DMA_CH4
+/*
+#ifdef __cplusplus
+extern "C" {
+#endif
+*/
+
+/*
+ * Register maps and devices
+ */
+
+// SDIO register map type
+typedef struct sdio_reg_map {
+    __io uint32 POWER;    // 0x00
+    __io uint32 CLKCR;    // 0x04
+    __io uint32 ARG;      // 0x08
+    __io uint32 CMD;      // 0x0C
+    __io uint32 RESPCMD;  // 0x10 (0x3F)
+    const uint32 RESP[4]; // 0x14 - contain the card status, which is part of the received response.
+    __io uint32 DTIMER;   // 0x24 - contains the data timeout period, in card bus clock periods.
+    __io uint32 DLEN;     // 0x28 (0x01FF FFFF) - contains the number of data bytes to be transferred
+    __io uint32 DCTRL;    // 0x2C
+    __io uint32 DCOUNT;   // 0x30 (0x01FF FFFF)
+    __io uint32 STA;      // 0x34
+    __io uint32 ICR;      // 0x38
+    __io uint32 MASK;     // 0x3C
+    const uint32 RESERVED1[2];
+    __io uint32 FIFOCNT;  // 0x48 (0x01FF FFFF)
+    const uint32 RESERVED2[13];
+    __io uint32 FIFO;     // 0x80
+} sdio_reg_map;
+#define sdio_dev sdio_reg_map
+
+/** SDIO register map base pointer */
+#define SDIO_BASE                       ((struct sdio_reg_map*)0x40018000)
+
+extern sdio_dev * SDIO;
+
+/*
+ * Register bit definitions
+ */
+
+/* NOR/PSRAM chip-select control registers */
+
+// SDIO_POWER register bits
+// At least seven HCLK clock periods are needed between two write accesses to this register.
+// After a data write, data cannot be written to this register for three SDIOCLK clock periods
+// plus two PCLK2 clock periods.
+#define SDIO_POWER_PWRCTRL_OFF         0x00
+#define SDIO_POWER_PWRCTRL_ON          0x03
+
+// SDIO_CLKCR register bits
+// Controls the SDIO_CK output clock.
+// After a data write, data cannot be written to this register for three SDIOCLK clock periods
+// plus two PCLK2 clock periods. SDIO_CK can also be stopped during the read wait interval
+// for SD I/O cards: in this case the SDIO_CLKCR register does not control SDIO_CK.
+#define SDIO_CLKCR_HWFC_EN          (1<<14) // HW Flow Control enable - DON'T USE!!! (see errata sheet 2.12.1)
+                                            // Overrun errors (Rx mode) and FIFO underrun (Tx mode)
+											// should be managed by the application software.
+#define SDIO_CLKCR_NEGEDGE          (1<<13) // SDIO_CK de-phasing selection bit - DON'T USE!!! (see errata sheet 2.12.4)
+#define SDIO_CLKCR_WIDBUS           (3<<11) // Data bus width
+#define SDIO_CLKCR_WIDBUS_1BIT      (0<<11) // 1 bit (SDIO_D0 used)
+#define SDIO_CLKCR_WIDBUS_4BIT      (1<<11) // 4-bit (SDIO_D[3:0] used)
+#define SDIO_CLKCR_BYPASS           (1<<10) // Clock divider bypass enable bit - SDIO_CK = SDIOCLK, CLKDIV not relevant.
+#define SDIO_CLKCR_PWRSAV           (1<<9)  // 0: SDIO_CK clock is always enabled, 1: SDIO_CK is only enabled when the bus is active
+#define SDIO_CLKCR_CLKEN            (1<<8)  // Clock enable
+#define SDIO_CLKCR_CLKDIV           (0xFF)  // SDIO_CK = SDIOCLK / [CLKDIV + 2]
+#define SDIOCLK 					72000000UL // SDIO master clock frequency
+
+// SDIO_CMD register bits
+// After a data write, data cannot be written to this register for three SDIOCLK clock periods
+// plus two PCLK2 clock periods.
+// MultiMediaCards can send two kinds of response: short responses, 48 bits long, or long
+// responses,136 bits long. SD card and SD I/O card can send only short responses, the
+// argument can vary according to the type of response: the software will distinguish the type
+// of response according to the sent command. CE-ATA devices send only short responses.
+#define SDIO_CMD_ATACMD          (1<<14)
+#define SDIO_CMD_NIEN            (1<<13)
+#define SDIO_CMD_ENCMDCOMPL      (1<<12)
+#define SDIO_CMD_SDIOSUSPEND     (1<<11)
+#define SDIO_CMD_CPSMEN          (1<<10)
+#define SDIO_CMD_WAITPEND        (1<<9)
+#define SDIO_CMD_WAITINT         (1<<8)
+#define SDIO_CMD_WAITRESP        (3<<6)
+#define SDIO_CMD_WAIT_NO_RESP    (0<<6)
+#define SDIO_CMD_WAIT_SHORT_RESP (1<<6)
+#define SDIO_CMD_WAIT_LONG_RESP  (3<<6)
+#define SDIO_CMD_CMDINDEX        (0x3F)
+
+// SDIO_DLEN register bits
+// For a block data transfer, the value in the data length register must be a multiple of the block
+// size (see SDIO_DCTRL). A data transfer must be written to the data timer register and the
+// data length register before being written to the data control register.
+// For an SDIO multibyte transfer the value in the data length register must be between 1 and 512.
+#define SDIO_DLEN_DATALENGTH     (0x01FFFFFF)
+
+// SDIO_DCTRL register bits
+// Controls the data path state machine (DPSM).
+// After a data write, data cannot be written to this register for three SDIOCLK clock periods
+// plus two PCLK2 clock periods.
+#define SDIO_DCTRL_SDIOEN        (1<<11)  // the DPSM performs an SD I/O-card-specific operation.
+#define SDIO_DCTRL_RWMODE        (1<<10)  // 0: Read Wait control stopping SDIO_D2, 1:Read Wait control using SDIO_CK
+#define SDIO_DCTRL_RWSTOP        (1<<9)   // 0: Read wait in progress if RWSTART bit is set, 1: Enable for read wait stop if RWSTART bit is set
+#define SDIO_DCTRL_RWSTART       (1<<8)   // read wait operation starts
+#define SDIO_DCTRL_DBLOCKSIZE    (0xF<<4) // Define the data block length when the block data transfer mode is selected: 2^N bytes
+#define SDIO_BLOCKSIZE_64        (6<<4)
+#define SDIO_BLOCKSIZE_512       (9<<4)
+#define SDIO_DCTRL_DMAEN         (1<<3)   // DMA enable
+#define SDIO_DCTRL_DTMODE        (1<<2)   // Data transfer mode selection: 0: Block data transfer, 1: Stream or SDIO multi-byte data transfer
+#define SDIO_DCTRL_DTDIR         (1<<1)   // Data transfer direction selection: 0: From controller to card, 1: From card to controller.
+#define SDIO_DIR_TX              (0<<1)
+#define SDIO_DIR_RX              (1<<1)
+#define SDIO_DCTRL_DTEN          (1<<0)   // Start data transfer. Depending on the direction bit, DTDIR,
+                                          // the DPSM moves to the Wait_S, Wait_R state or Readwait if RW Start is set immediately at
+										  // the beginning of the transfer. It is not necessary to clear the enable bit after the end of a data
+										  // transfer but the SDIO_DCTRL must be updated to enable a new data transfer
+// The meaning of the DTMODE bit changes according to the value of the SDIOEN bit:
+// When DTEN=0 and DTMODE=1, the MultiMediaCard stream mode is enabled.
+// When DTEN=1 and DTMODE=1, the peripheral enables an SDIO multi-byte transfer.
+
+// SDIO_STA register bits
+#define SDIO_STA_CEATAEND        (1<<23) // CE-ATA command completion signal received for CMD61
+#define SDIO_STA_SDIOIT          (1<<22) // SDIO interrupt received
+#define SDIO_STA_RXDAVL          (1<<21) // Data available in receive FIFO
+#define SDIO_STA_TXDAVL          (1<<20) // Data available in transmit FIFO
+#define SDIO_STA_RXFIFOE         (1<<19) // Receive FIFO empty
+#define SDIO_STA_TXFIFOE         (1<<18) // Transmit FIFO empty (2 words)
+#define SDIO_STA_RXFIFOF         (1<<17) // Receive FIFO full (2 words before the FIFO is full.)
+#define SDIO_STA_TXFIFOF         (1<<16) // Transmit FIFO full
+#define SDIO_STA_RXFIFOHF        (1<<15) // Receive FIFO half full: there are at least 8 words in the FIFO
+#define SDIO_STA_TXFIFOHE        (1<<14) // Transmit FIFO half empty: at least 8 words can be written into the FIFO
+#define SDIO_STA_RXACT           (1<<13) // Data receive in progress
+#define SDIO_STA_TXACT           (1<<12) // Data transmit in progress
+#define SDIO_STA_CMDACT          (1<<11) // Command transfer in progress
+#define SDIO_STA_DBCKEND         (1<<10) // Data block sent/received (CRC check passed)
+#define SDIO_STA_STBITERR        (1<<9)  // Start bit not detected on all data signals in wide bus mode
+#define SDIO_STA_DATAEND         (1<<8)  // Data end (data counter SDIOCOUNT is zero)
+#define SDIO_STA_CMDSENT         (1<<7)  // Command sent (no response required)
+#define SDIO_STA_CMDREND         (1<<6)  // Command response received (CRC check passed)
+#define SDIO_STA_RXOVERR         (1<<5)  // Received FIFO overrun error
+#define SDIO_STA_TXUNDERR        (1<<4)  // Transmit FIFO underrun error
+#define SDIO_STA_DTIMEOUT        (1<<3)  // Data timeout
+#define SDIO_STA_CTIMEOUT        (1<<2)  // Command response timeout. The Command TimeOut period has a fixed value of 64 SDIO_CK clock periods.
+#define SDIO_STA_DCRCFAIL        (1<<1)  // Data block sent/received (CRC check failed)
+#define SDIO_STA_CCRCFAIL        (1<<0)  // Command response received (CRC check failed)
+
+#define SDIO_STA_CMD_ERROR_FLAGS (SDIO_STA_CTIMEOUT | SDIO_STA_CCRCFAIL)
+#define SDIO_STA_TRX_ERROR_FLAGS (SDIO_STA_STBITERR | SDIO_STA_RXOVERR | SDIO_STA_TXUNDERR | SDIO_STA_DTIMEOUT | SDIO_STA_DCRCFAIL)
+#define SDIO_STA_TRX_ACT_FLAGS   (SDIO_STA_RXACT|SDIO_STA_TXACT)
+
+// SDIO_ICR register bits (WO - write only)
+#define SDIO_ICR_CEATAENDC       (1<<23) // clear CEATAEND  flag
+#define SDIO_ICR_SDIOITC         (1<<22) // clear SDIOIT    flag
+#define SDIO_ICR_DBCKENDC        (1<<10) // clear DBCKENDC  flag
+#define SDIO_ICR_STBITERRC       (1<<9)  // clear STBITERRC flag
+#define SDIO_ICR_DATAENDC        (1<<8)  // clear DATAENDC  flag
+#define SDIO_ICR_CMDSENTC        (1<<7)  // clear CMDSENTC  flag
+#define SDIO_ICR_CMDRENDC        (1<<6)  // clear CMDREND   flag
+#define SDIO_ICR_RXOVERRC        (1<<5)  // clear RXOVERR   flag
+#define SDIO_ICR_TXUNDERRC       (1<<4)  // clear TXUNDERR  flag
+#define SDIO_ICR_DTIMEOUTC       (1<<3)  // clear DTIMEOUT  flag
+#define SDIO_ICR_CTIMEOUTC       (1<<2)  // clear CTIMEOUT  flag
+#define SDIO_ICR_DCRCFAILC       (1<<1)  // clear DCRCFAIL  flag
+#define SDIO_ICR_CCRCFAILC       (1<<0)  // clear CCRCFAIL  flag
+
+#define SDIO_ICR_CMD_FLAGS   (SDIO_ICR_CEATAENDC | SDIO_ICR_SDIOITC | SDIO_ICR_CMDSENTC | SDIO_ICR_CMDRENDC | SDIO_ICR_CTIMEOUTC | SDIO_ICR_CCRCFAILC)
+#define SDIO_ICR_DATA_FLAGS  (SDIO_ICR_DBCKENDC | SDIO_ICR_STBITERRC | SDIO_ICR_DATAENDC | SDIO_ICR_RXOVERRC | SDIO_ICR_TXUNDERRC | SDIO_ICR_DTIMEOUTC | SDIO_ICR_DCRCFAILC)
+
+// SDIO_MASK register bits
+// Determines which status flags generate an interrupt request by setting the corresponding bit to 1b.
+#define SDIO_MASK_CEATAENDIE        (1<<23) // enable CEATAEND interrupt 
+#define SDIO_MASK_SDIOITIE          (1<<22) // enable SDIOIT   interrupt
+#define SDIO_MASK_RXDAVLIE          (1<<21) // enable RXDAVL   interrupt
+#define SDIO_MASK_TXDAVLIE          (1<<20) // enable TXDAVL   interrupt
+#define SDIO_MASK_RXFIFOEIE         (1<<19) // enable RXFIFOE  interrupt
+#define SDIO_MASK_TXFIFOEIE         (1<<18) // enable TXFIFOE  interrupt
+#define SDIO_MASK_RXFIFOFIE         (1<<17) // enable RXFIFOF  interrupt
+#define SDIO_MASK_TXFIFOFIE         (1<<16) // enable TXFIFOF  interrupt
+#define SDIO_MASK_RXFIFOHFIE        (1<<15) // enable RXFIFOHF interrupt
+#define SDIO_MASK_TXFIFOHEIE        (1<<14) // enable TXFIFOHE interrupt
+#define SDIO_MASK_RXACTIE           (1<<13) // enable RXACT    interrupt
+#define SDIO_MASK_TXACTIE           (1<<12) // enable TXACT    interrupt
+#define SDIO_MASK_CMDACTIE          (1<<11) // enable CMDACT   interrupt
+#define SDIO_MASK_DBCKENDIE         (1<<10) // enable DBCKENDC interrupt
+#define SDIO_MASK_STBITERRIE        (1<<9)  // enable STBITERR interrupt
+#define SDIO_MASK_DATAENDIE         (1<<8)  // enable DATAENDC interrupt
+#define SDIO_MASK_CMDSENTIE         (1<<7)  // enable CMDSENTC interrupt
+#define SDIO_MASK_CMDRENDIE         (1<<6)  // enable CMDREND  interrupt
+#define SDIO_MASK_RXOVERRIE         (1<<5)  // enable RXOVERR  interrupt
+#define SDIO_MASK_TXUNDERRIE        (1<<4)  // enable TXUNDERR interrupt
+#define SDIO_MASK_DTIMEOUTIE        (1<<3)  // enable DTIMEOUT interrupt
+#define SDIO_MASK_CTIMEOUTIE        (1<<2)  // enable CTIMEOUT interrupt
+#define SDIO_MASK_DCRCFAILIE        (1<<1)  // enable DCRCFAIL interrupt
+#define SDIO_MASK_CCRCFAILIE        (1<<0)  // enable CCRCFAIL interrupt
+
+
+void sdio_enable(void);
+void sdio_disable(void);
+void sdio_begin(void);
+uint8_t sdio_cmd_send(uint16_t cmd_index_resp_type, uint32_t arg);
+void sdio_set_clock(uint32_t clk);
+void sdio_set_dbus_width(uint16_t bus_w);
+void sdio_set_dblock_size(uint8_t dbsize);
+//void sdio_trx_enable(uint8_t dir);
+inline void sdio_trx_enable(void)
+{
+	SDIO->DCTRL |= SDIO_DCTRL_DTEN; // enable data transfer
+}
+
+inline uint32_t sdio_cmd_xfer_ongoing(void) { return (SDIO->STA&SDIO_STA_CMDACT); }
+inline uint32_t sdio_cmd_complete(void) { return (SDIO->STA&SDIO_STA_CMDSENT); }
+
+inline void sdio_setup_transfer(uint32_t dtimer, uint32_t dlen, uint16_t flags)
+{
+	SDIO->ICR = SDIO_ICR_DATA_FLAGS; // clear data access relevant flags
+	SDIO->DTIMER = dtimer;
+	SDIO->DLEN = dlen;
+	SDIO->DCTRL = flags;// | SDIO_DCTRL_DTEN; // enable data transfer
+}
+
+/*
+#ifdef __cplusplus
+} // extern "C"
+#endif
+*/
+
+#endif /* (STM32_HIGH_DENSITY) || (STM32_XL_DENSITY) */
+
+#endif

From 8929bbbde08b1896626c9c2b50e1c865804e918d Mon Sep 17 00:00:00 2001
From: victorpv <victor_pv@hotmail.com>
Date: Mon, 11 Sep 2017 21:29:33 -0500
Subject: [PATCH 187/307] F1 SDIO

---
 STM32F1/cores/maple/sdio.cpp | 198 +++++++++++++++++++++++++++++++++++
 1 file changed, 198 insertions(+)
 create mode 100644 STM32F1/cores/maple/sdio.cpp

diff --git a/STM32F1/cores/maple/sdio.cpp b/STM32F1/cores/maple/sdio.cpp
new file mode 100644
index 000000000..8bd94915b
--- /dev/null
+++ b/STM32F1/cores/maple/sdio.cpp
@@ -0,0 +1,198 @@
+/******************************************************************************
+  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/sdio.c
+ * @author stevstrong
+ * @brief Secure digital input/output interface.
+ */
+
+#include <libmaple/sdio.h>
+#include <libmaple/gpio.h>
+#include <boards.h>
+#include "wirish.h"
+
+
+//#include <libmaple/libmaple.h>
+//#include <libmaple/rcc.h>
+//#include <series/gpio.h>
+//#include "wirish.h"
+//#include "boards.h"
+//
+
+#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
+
+sdio_dev * SDIO = SDIO_BASE;
+
+#define DELAY_LONG 10
+#define DELAY_SHORT 1
+
+uint8_t dly = DELAY_LONG; // microseconds delay after accessing registers
+
+/*
+ * SDIO convenience routines
+ */
+void sdio_gpios_init(void)
+{
+	gpio_set_mode(PIN_MAP[BOARD_SDIO_D0].gpio_device, PIN_MAP[BOARD_SDIO_D0].gpio_bit, GPIO_AF_OUTPUT_PP);
+	gpio_set_mode(PIN_MAP[BOARD_SDIO_D1].gpio_device, PIN_MAP[BOARD_SDIO_D1].gpio_bit, GPIO_AF_OUTPUT_PP);
+	gpio_set_mode(PIN_MAP[BOARD_SDIO_D2].gpio_device, PIN_MAP[BOARD_SDIO_D2].gpio_bit, GPIO_AF_OUTPUT_PP);
+	gpio_set_mode(PIN_MAP[BOARD_SDIO_D3].gpio_device, PIN_MAP[BOARD_SDIO_D3].gpio_bit, GPIO_AF_OUTPUT_PP);
+	gpio_set_mode(PIN_MAP[BOARD_SDIO_CLK].gpio_device, PIN_MAP[BOARD_SDIO_CLK].gpio_bit, GPIO_AF_OUTPUT_PP);
+	gpio_set_mode(PIN_MAP[BOARD_SDIO_CMD].gpio_device, PIN_MAP[BOARD_SDIO_CMD].gpio_bit, GPIO_AF_OUTPUT_PP);
+	/*
+	 *  Todo just remove it, not needed for F1.
+	 */
+     /*
+	gpio_set_af_mode(BOARD_SDIO_D0, 12);
+	gpio_set_af_mode(BOARD_SDIO_D1, 12);
+	gpio_set_af_mode(BOARD_SDIO_D2, 12);
+	gpio_set_af_mode(BOARD_SDIO_D3, 12);
+	gpio_set_af_mode(BOARD_SDIO_CLK, 12);
+	gpio_set_af_mode(BOARD_SDIO_CMD, 12);
+    */
+}
+
+void sdio_gpios_deinit(void)
+{
+	gpio_set_mode(PIN_MAP[BOARD_SDIO_D0].gpio_device, PIN_MAP[BOARD_SDIO_D0].gpio_bit, GPIO_INPUT_FLOATING);
+	gpio_set_mode(PIN_MAP[BOARD_SDIO_D1].gpio_device, PIN_MAP[BOARD_SDIO_D1].gpio_bit, GPIO_INPUT_FLOATING);
+	gpio_set_mode(PIN_MAP[BOARD_SDIO_D2].gpio_device, PIN_MAP[BOARD_SDIO_D2].gpio_bit, GPIO_INPUT_FLOATING);
+	gpio_set_mode(PIN_MAP[BOARD_SDIO_D3].gpio_device, PIN_MAP[BOARD_SDIO_D3].gpio_bit, GPIO_INPUT_FLOATING);
+	gpio_set_mode(PIN_MAP[BOARD_SDIO_CLK].gpio_device, PIN_MAP[BOARD_SDIO_CLK].gpio_bit, GPIO_INPUT_FLOATING);
+	gpio_set_mode(PIN_MAP[BOARD_SDIO_CMD].gpio_device, PIN_MAP[BOARD_SDIO_CMD].gpio_bit, GPIO_INPUT_FLOATING);
+
+	/*
+	 *  Todo just remove it, not needed for F1.
+	 */
+     /*
+	gpio_set_af_mode(BOARD_SDIO_D0, 0);
+	gpio_set_af_mode(BOARD_SDIO_D1, 0);
+	gpio_set_af_mode(BOARD_SDIO_D2, 0);
+	gpio_set_af_mode(BOARD_SDIO_D3, 0);
+	gpio_set_af_mode(BOARD_SDIO_CLK, 0);
+	gpio_set_af_mode(BOARD_SDIO_CMD, 0);
+     */
+}
+
+/**
+ * @brief Initialize and reset the SDIO device.
+ */
+void sdio_init(void)
+{
+    rcc_clk_enable(RCC_SDIO);
+    rcc_reset_dev(RCC_SDIO);
+}
+
+void sdio_power_on(void)
+{
+    SDIO->POWER = SDIO_POWER_PWRCTRL_ON;
+// After a data write, data cannot be written to this register for three SDIOCLK clock periods
+// plus two PCLK2 clock periods.
+	delay_us(DELAY_LONG);
+}
+
+void sdio_power_off(void)
+{
+    SDIO->POWER = SDIO_POWER_PWRCTRL_OFF;
+// After a data write, data cannot be written to this register for three SDIOCLK clock periods
+// plus two PCLK2 clock periods.
+	delay_us(DELAY_LONG);
+}
+
+void sdio_set_clock(uint32_t clk)
+{
+	if (clk>24000000UL) clk = 24000000UL; // limit the SDIO master clock to 24MHz
+
+	if (clk<1000000) dly = DELAY_LONG;
+	else dly = DELAY_SHORT;
+
+	sdio_disable();
+	SDIO->CLKCR = (SDIO->CLKCR & (~(SDIO_CLKCR_CLKDIV|SDIO_CLKCR_BYPASS))) | SDIO_CLKCR_CLKEN | (((SDIOCLK/clk)-2)&SDIO_CLKCR_CLKDIV);
+	delay_us(dly);
+}
+
+void sdio_set_dbus_width(uint16_t bus_w)
+{
+	SDIO->CLKCR = (SDIO->CLKCR & (~SDIO_CLKCR_WIDBUS)) | bus_w;
+	delay_us(dly);
+}
+
+void sdio_set_dblock_size(uint8_t dbsize)
+{
+	SDIO->DCTRL = (SDIO->DCTRL&(~SDIO_DCTRL_DBLOCKSIZE)) | ((dbsize&0xF)<<4);
+	delay_us(dly);
+}
+
+void sdio_enable(void)
+{
+	SDIO->CLKCR |= SDIO_CLKCR_CLKEN;
+	delay_us(dly);
+}
+
+void sdio_disable(void)
+{
+	SDIO->CLKCR ^= SDIO_CLKCR_CLKEN;
+	delay_us(dly);
+}
+
+/**
+ * @brief Configure and enable the SDIO device.
+ */
+void sdio_begin(void)
+{
+	sdio_gpios_init();
+	sdio_init();
+	sdio_power_on();
+	// Set initial SCK rate.
+	sdio_set_clock(400000);
+	delay_us(200); // generate 80 pulses at 400kHz
+}
+
+/**
+ * @brief Disables the SDIO device.
+ */
+void sdio_end(void)
+{
+	sdio_disable();
+	while ( sdio_cmd_xfer_ongoing() );
+	sdio_power_off();
+    rcc_clk_disable(RCC_SDIO);
+	sdio_gpios_deinit();
+}
+
+/**
+ * @brief Send command by the SDIO device.
+ */
+uint8_t sdio_cmd_send(uint16_t cmd_index_resp_type, uint32_t arg)
+{
+	uint8_t retries = 10; // in case of errors
+	do { // retry command if errors detected
+		// clear interrupt flags - IMPORTANT!!!
+		SDIO->ICR = SDIO_ICR_CMD_FLAGS;
+		// write command
+		SDIO->ARG = arg;
+		SDIO->CMD = (uint32_t)(SDIO_CMD_CPSMEN | cmd_index_resp_type );
+		while ( (SDIO->STA&SDIO_STA_CMDACT) ) ; // wait for actual command transfer to finish
+		// wait for response, if the case
+		if ( cmd_index_resp_type&(SDIO_CMD_WAIT_SHORT_RESP|SDIO_CMD_WAIT_LONG_RESP) ) {
+			while ( !(SDIO->STA&(SDIO_STA_CMDREND|SDIO_STA_CMD_ERROR_FLAGS)) ) ;
+		} else break; // no response required
+		if ( SDIO->STA&(SDIO_STA_CMDREND|SDIO_STA_CTIMEOUT) )
+			break; // response received or timeout
+		// ignore CRC error for CMD5 and ACMD41
+		if ( ((cmd_index_resp_type&SDIO_CMD_CMDINDEX)==5) || ((cmd_index_resp_type&SDIO_CMD_CMDINDEX)==41) )
+			break;
+	} while ( (--retries) );
+	return (uint8_t)retries;
+}
+
+#endif // defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)

From 1db95cf251f8100610fd716fbe7a5f970b931207 Mon Sep 17 00:00:00 2001
From: victorpv <victor_pv@hotmail.com>
Date: Mon, 11 Sep 2017 21:40:25 -0500
Subject: [PATCH 188/307] F1 SDIO

---
 STM32F1/variants/generic_stm32f103r/board/board.h | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/STM32F1/variants/generic_stm32f103r/board/board.h b/STM32F1/variants/generic_stm32f103r/board/board.h
index 0719afaa5..925c882e3 100644
--- a/STM32F1/variants/generic_stm32f103r/board/board.h
+++ b/STM32F1/variants/generic_stm32f103r/board/board.h
@@ -102,6 +102,16 @@
 #define BOARD_USB_DISC_DEV      GPIOC
 #define BOARD_USB_DISC_BIT      12
 
+/*
+ * SDIO Pins
+ */
+#define BOARD_SDIO_D0 			PC8
+#define BOARD_SDIO_D1 			PC9
+#define BOARD_SDIO_D2 			PC10
+#define BOARD_SDIO_D3 			PC11
+#define BOARD_SDIO_CLK 			PC12
+#define BOARD_SDIO_CMD 			PD2
+
 /* Pin aliases: these give the GPIO port/bit for each pin as an
  * enum. These are optional, but recommended. They make it easier to
  * write code using low-level GPIO functionality. */

From 799f2b3b8a42a180879260dff910d682e3a2d104 Mon Sep 17 00:00:00 2001
From: victorpv <victor_pv@hotmail.com>
Date: Mon, 11 Sep 2017 22:01:55 -0500
Subject: [PATCH 189/307] Correct issue with port speed not changing.

The current implementation will not change speed if Wire.setClock is called after begin() since the flags are only applied when the port is enabled from being disabled.
Corrected that by adding 2 lines to disable the port, and then enable it again with the new settings.
Tested and confirmed the new speed is applied.
---
 STM32F1/libraries/Wire/Wire.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/STM32F1/libraries/Wire/Wire.cpp b/STM32F1/libraries/Wire/Wire.cpp
index c4e9befa7..3f5f16123 100644
--- a/STM32F1/libraries/Wire/Wire.cpp
+++ b/STM32F1/libraries/Wire/Wire.cpp
@@ -97,7 +97,8 @@ void HardWire::setClock(uint32_t frequencyHz)
 			dev_flags &= ~I2C_FAST_MODE;// clear FAST_MODE bit
 			break;
 	}
-	
+	i2c_disable(sel_hard);
+	i2c_master_enable(sel_hard, dev_flags);
 }
 
 HardWire Wire(1);

From a530b6a3d46385586e6ece1202ee505c09157150 Mon Sep 17 00:00:00 2001
From: victorpv <victor_pv@hotmail.com>
Date: Mon, 11 Sep 2017 22:49:03 -0500
Subject: [PATCH 190/307] Update Wire.cpp

Adds a check to verify if the port had been already enabled, and only in that case disables/re-enables the port. This also solves the issue of setClock being called after begin(), but doesn't not enable the port if begin() had not been called yet.
---
 STM32F1/libraries/Wire/Wire.cpp | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/STM32F1/libraries/Wire/Wire.cpp b/STM32F1/libraries/Wire/Wire.cpp
index 3f5f16123..a026e2ef7 100644
--- a/STM32F1/libraries/Wire/Wire.cpp
+++ b/STM32F1/libraries/Wire/Wire.cpp
@@ -97,8 +97,10 @@ void HardWire::setClock(uint32_t frequencyHz)
 			dev_flags &= ~I2C_FAST_MODE;// clear FAST_MODE bit
 			break;
 	}
-	i2c_disable(sel_hard);
-	i2c_master_enable(sel_hard, dev_flags);
+	if (sel_hard->regs->CR1 & I2C_CR1_PE){
+	    i2c_disable(sel_hard);
+	    i2c_master_enable(sel_hard, dev_flags);
+	}
 }
 
 HardWire Wire(1);

From 7752fc68f2860afc096c707529d740f3766268f2 Mon Sep 17 00:00:00 2001
From: csnol <csnol@126.com>
Date: Wed, 13 Sep 2017 04:08:04 +0800
Subject: [PATCH 191/307] add attachAlarmInterrupt() detachAlarmInterrupt()

---
 STM32F1/libraries/RTClock/src/RTClock.cpp | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/STM32F1/libraries/RTClock/src/RTClock.cpp b/STM32F1/libraries/RTClock/src/RTClock.cpp
index cc7b63e8d..deefcf00e 100644
--- a/STM32F1/libraries/RTClock/src/RTClock.cpp
+++ b/STM32F1/libraries/RTClock/src/RTClock.cpp
@@ -201,6 +201,18 @@ time_t RTClock::makeTime(tm_t & tmm)
 		rtc_detach_interrupt(RTC_SECONDS_INTERRUPT);
 	}
 
+        void RTClock::attachAlarmInterrupt(voidFuncPtr function, time_t alarm_time) {  // Don't need run RTClock::setAlarmTime(time_t alarm_time)
+		rtc_set_alarm(alarm_time);
+		rtc_attach_interrupt(RTC_ALARM_GLOBAL_INTERRUPT, function);
+	}
+	
+	void RTClock::attachAlarmInterrupt(voidFuncPtr function) {       // Must run RTClock::setAlarmTime (time_t alarm_time or tm_t & alarm_tm) first
+		rtc_attach_interrupt(RTC_ALARM_GLOBAL_INTERRUPT, function);
+	}
+	
+	void RTClock::detachAlarmInterrupt() {
+		rtc_detach_interrupt(RTC_ALARM_GLOBAL_INTERRUPT);
+	}
 
 	void RTClock::createAlarm(voidFuncPtr function, tm_t & alarm_tm) {
 		time_t alarm = makeTime(alarm_tm);//convert to time_t

From a87ad87fa71bb7190b2e6bdc94d097752c4cd359 Mon Sep 17 00:00:00 2001
From: csnol <csnol@126.com>
Date: Wed, 13 Sep 2017 04:10:25 +0800
Subject: [PATCH 192/307] add attachAlarmInterrupt and detachAlarmInterrupt

---
 STM32F1/libraries/RTClock/src/RTClock.h | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/STM32F1/libraries/RTClock/src/RTClock.h b/STM32F1/libraries/RTClock/src/RTClock.h
index 711992e1f..aa97ac98d 100644
--- a/STM32F1/libraries/RTClock/src/RTClock.h
+++ b/STM32F1/libraries/RTClock/src/RTClock.h
@@ -78,6 +78,10 @@ class RTClock {
 	void attachSecondsInterrupt(voidFuncPtr function); 
 	void detachSecondsInterrupt();
 	
+        void attachAlarmInterrupt(voidFuncPtr function); 
+	void attachAlarmInterrupt(voidFuncPtr function, time_t alarm_time);
+	void detachAlarmInterrupt();
+	
 	void setAlarmTime (tm_t  & tm_ptr);
 	void setAlarmTime (time_t alarm_time); 
 	
@@ -89,4 +93,4 @@ class RTClock {
 
 
 #endif // _RTCLOCK_H_
-                                                                                        
\ No newline at end of file
+                                                                                        

From 30f8527eaa67d78fdffdc475a5620bda36bac87e Mon Sep 17 00:00:00 2001
From: csnol <csnol@126.com>
Date: Wed, 13 Sep 2017 10:53:08 +0800
Subject: [PATCH 193/307] added TimeZone(time_t xxx, timezone);

Usage:
time_t localtime;
localtime = TimeZone(UnixTime, 8);   // Beijing timezone = 8
---
 STM32F1/libraries/RTClock/src/RTClock.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/STM32F1/libraries/RTClock/src/RTClock.h b/STM32F1/libraries/RTClock/src/RTClock.h
index aa97ac98d..74f7397da 100644
--- a/STM32F1/libraries/RTClock/src/RTClock.h
+++ b/STM32F1/libraries/RTClock/src/RTClock.h
@@ -72,6 +72,8 @@ class RTClock {
 	uint8_t second(time_t t)  { breakTime(t, tmm); return tmm.second; }
 	uint8_t isPM(time_t t)    { return (hour(t)>=12); }
 	
+	time_t TimeZone(time_t t, uint8_t TZ)  { return ( t - (TZ * SECS_PER_HOUR)); }    // usage: localtime = TimeZone(UnixTime, 8); // Beijing timezone = 8  
+	
 	void createAlarm(voidFuncPtr function, time_t alarm_time_t); 
 	void createAlarm(voidFuncPtr function, struct tm_t & alarm_tm);
 	

From 6be069cdb6094bd3957f65184625f4e20287e3d0 Mon Sep 17 00:00:00 2001
From: csnol <csnol@126.com>
Date: Wed, 13 Sep 2017 11:02:24 +0800
Subject: [PATCH 194/307] change TZ from unit_8 to int, negatives timezone

usage: localtime = TimeZone(UnixTime, -7);   // CA USA = -7
---
 STM32F1/libraries/RTClock/src/RTClock.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/libraries/RTClock/src/RTClock.h b/STM32F1/libraries/RTClock/src/RTClock.h
index 74f7397da..e67fcb33b 100644
--- a/STM32F1/libraries/RTClock/src/RTClock.h
+++ b/STM32F1/libraries/RTClock/src/RTClock.h
@@ -72,7 +72,7 @@ class RTClock {
 	uint8_t second(time_t t)  { breakTime(t, tmm); return tmm.second; }
 	uint8_t isPM(time_t t)    { return (hour(t)>=12); }
 	
-	time_t TimeZone(time_t t, uint8_t TZ)  { return ( t - (TZ * SECS_PER_HOUR)); }    // usage: localtime = TimeZone(UnixTime, 8); // Beijing timezone = 8  
+	time_t TimeZone(time_t t, int TZ)  { return ( t - (TZ * SECS_PER_HOUR)); }    // usage: localtime = TimeZone(UnixTime, 8); // Beijing timezone = 8  
 	
 	void createAlarm(voidFuncPtr function, time_t alarm_time_t); 
 	void createAlarm(voidFuncPtr function, struct tm_t & alarm_tm);

From ed797d43e530087dd8d9deaf3a5684df49c3e1bd Mon Sep 17 00:00:00 2001
From: csnol <csnol@126.com>
Date: Thu, 14 Sep 2017 00:03:55 +0800
Subject: [PATCH 195/307] Tested on BluePill  for new function of RTC

---
 .../BlutPill-RTClock-test.ino                 | 130 ++++++++++++++++++
 1 file changed, 130 insertions(+)
 create mode 100644 STM32F1/libraries/RTClock/examples/BlutPill-RTClock-test/BlutPill-RTClock-test.ino

diff --git a/STM32F1/libraries/RTClock/examples/BlutPill-RTClock-test/BlutPill-RTClock-test.ino b/STM32F1/libraries/RTClock/examples/BlutPill-RTClock-test/BlutPill-RTClock-test.ino
new file mode 100644
index 000000000..b6e661069
--- /dev/null
+++ b/STM32F1/libraries/RTClock/examples/BlutPill-RTClock-test/BlutPill-RTClock-test.ino
@@ -0,0 +1,130 @@
+/*   STM32F103C8 Blue Pill ( PC13)
+
+  Serialport set and display RTC clock , Write by CSNOL https://github.com/csnol/STM32-Examples
+  based on https://github.com/rogerclarkmelbourne/Arduino_STM32
+
+  1. Blink on PC13 per 4s or 7s by attachAlarmInterrupt for 10 times
+  2. Second counter by attachSecondsInterrpt
+  3. Serial output on(41s) or off(21s) by creatAlarm
+  4. change to your timezone in the sketch; .
+  3. get Unix epoch time from https://www.epochconverter.com/ ;
+  4. last step input the 10 bits number( example: 1503945555) to Serialport ;
+  5. the clock will be reset to you wanted.
+
+  ##  Why the 10 bits Unix epoch time be used?
+****Because I wanna connect to NTP server by ESP-8266.
+****in the <NTPClient.h> library. getNtpTime() will return this 10 bits Unix epoch time.
+*/
+
+
+#include <RTClock.h>
+
+RTClock rtclock (RTCSEL_LSE); // initialise
+int timezone = 8;      // change to your timezone
+time_t tt;
+time_t tt1;
+tm_t mtt = { 47, 9, 13, 3, 1, 22, 30, 30 };    // init time 47+1970 = 2017  Unix epoch Time counted from 00:00:00 1 Jan 1970  
+char weekday1[][7] = {"Sun", "Mon", "Tue", "Wed", "Thu", "Fri", "Sat"};  // 0,1,2,3,4,5,6
+uint8_t dateread[11];
+int globAlmCount = 0;
+int lastGlobAlmCount;
+int SPECAlmCount = 0;
+int lastSPECAlmCount;
+int i = 0;
+int alarmcount = 3;
+uint8_t AlarmExchange = 0;
+bool dispflag = true;
+
+#define LED_PIN PC13
+
+// This function is called in the attachSecondsInterrpt
+void SecondCount ()
+{
+  tt++;
+}
+// This function is called in the attachAlarmInterrpt
+void blink ()
+{
+  digitalWrite(LED_PIN, !digitalRead(LED_PIN));
+  globAlmCount++;
+  //tt++;
+}
+
+void OnOffSerial ()
+{
+  dispflag = !dispflag;
+  SPECAlmCount++;
+}
+
+void setup()
+{
+  lastGlobAlmCount = ~globAlmCount;
+  lastSPECAlmCount = ~SPECAlmCount;
+  Serial.begin(115200);
+  pinMode(LED_PIN, OUTPUT);
+  tt = rtclock.makeTime(mtt);   
+  tt1 = tt;
+  rtclock.attachAlarmInterrupt(blink);// Call blink
+  rtclock.attachSecondsInterrupt(SecondCount);// Call SecondCount
+}
+
+void loop()
+{
+  while (Serial.available())
+  { dateread[i] = Serial.read();
+    if (i < 11) {
+      i++;
+    }
+    else {
+      i = 0;
+      tt = (dateread[0] - '0') * 1000000000 + (dateread[1] - '0') * 100000000 + (dateread[2] - '0') * 10000000 + (dateread[3] - '0') * 1000000 + (dateread[4] - '0') * 100000;
+      tt += (dateread[5] - '0') * 10000 + (dateread[6] - '0') * 1000 + (dateread[7] - '0') * 100 + (dateread[8] - '0') * 10 + (dateread[9] - '0');
+      tt = rtclock.TimeZone(tt, timezone);    //adjust to your local date
+    }
+  }
+  if (lastGlobAlmCount != globAlmCount | lastSPECAlmCount != SPECAlmCount ) {
+    if (globAlmCount == 10) {        // to detachAlarmInterrupt and start creatAlarm after 10 times about 110s
+      rtclock.detachAlarmInterrupt();
+      globAlmCount = 0;
+      rtclock.createAlarm(OnOffSerial, (rtclock.getTime() + 20));   // call OnOffSerial stop output date from Serial after 2 mins
+      alarmcount = 20;   //change to creatAlarm  21S close Serial output and 41s open Serial output.
+    }
+    else {
+      lastGlobAlmCount = globAlmCount;
+      lastSPECAlmCount = SPECAlmCount;
+      Serial.println(" Say hello to every guys ");
+      if(dispflag == false)
+      Serial.println(" SPECAlarm turn Display Off ");
+      switch (AlarmExchange)  {
+        case 0:
+          rtclock.setAlarmTime(rtclock.getTime() + alarmcount);  // reset alarm = current time + 4s for attachAlarmInterrupt,  21s for creatAlarm
+          AlarmExchange = 1;
+          break;
+        case 1:
+          rtclock.breakTime(rtclock.getTime() + alarmcount * 2, mtt); //// reset alarm = current time + 7s for attachAlarmInterrupt,  41s for creatAlarm
+          rtclock.setAlarmTime(mtt);
+          AlarmExchange = 0;
+          break;
+      }
+    }
+  }
+  if (tt1 != tt & dispflag == true )
+  {
+    tt1 = tt;
+    rtclock.breakTime(tt, mtt);
+    Serial.print("Date:  ");
+    Serial.print(mtt.day);
+    Serial.print("- ");
+    Serial.print(mtt.month);
+    Serial.print("  ");
+    Serial.print(mtt.year + 1970);
+    Serial.print("  ");
+    Serial.print(weekday1[mtt.weekday]);
+    Serial.print("  Time: ");
+    Serial.print(mtt.hour);
+    Serial.print(" : ");
+    Serial.print(mtt.minute);
+    Serial.print(" : ");
+    Serial.println(mtt.second);
+  }
+}

From 2d6abe679aeaa4d12e19d6a3e3f234b418b956c9 Mon Sep 17 00:00:00 2001
From: csnol <csnol@126.com>
Date: Thu, 14 Sep 2017 15:05:42 +0800
Subject: [PATCH 196/307] Add keywords for new functions

---
 STM32F1/libraries/RTClock/keywords.txt | 29 +++++++++++++++++++++-----
 1 file changed, 24 insertions(+), 5 deletions(-)

diff --git a/STM32F1/libraries/RTClock/keywords.txt b/STM32F1/libraries/RTClock/keywords.txt
index ddd0680b8..31bf13e05 100644
--- a/STM32F1/libraries/RTClock/keywords.txt
+++ b/STM32F1/libraries/RTClock/keywords.txt
@@ -5,16 +5,35 @@
 #######################################
 # Datatypes (KEYWORD1)
 #######################################
-RTClock	KEYWORD1
 
+RTClock			KEYWORD1
 
-setTime					KEYWORD2
-getTime					KEYWORD2
 
-createAlarm				KEYWORD2
+setTime			KEYWORD2
+getTime			KEYWORD2
+
+createAlarm		KEYWORD2
+setAlarmTime		KEYWORD2
+
 attachSecondsInterrupt	KEYWORD2
 detachSecondsInterrupt	KEYWORD2
-setAlarmTime			KEYWORD2
+
+attachAlarmInterrupt	KEYWORD2
+detachAlarmInterrupt	KEYWORD2
+
+breakTime		KEYWORD2
+makeTime		KEYWORD2
+
+TimeZone		KEYWORD2
+now			KEYWORD2
+year			KEYWORD2
+month			KEYWORD2
+day			KEYWORD2
+weekday			KEYWORD2
+hour			KEYWORD2
+minute			KEYWORD2
+second			KEYWORD2
+isPM			KEYWORD2
 
 
 #######################################

From fa7bcde3cd21b50fd23b5ef3e10cf0445aed75ea Mon Sep 17 00:00:00 2001
From: csnol <csnol@126.com>
Date: Thu, 14 Sep 2017 16:05:28 +0800
Subject: [PATCH 197/307] Update example for Chinese friends.  timezone and
 filename error

---
 .../BluePill-RTClock-test.ino}                | 31 ++++++++++++-------
 STM32F1/libraries/RTClock/src/RTClock.h       |  4 +--
 2 files changed, 22 insertions(+), 13 deletions(-)
 rename STM32F1/libraries/RTClock/examples/{BlutPill-RTClock-test/BlutPill-RTClock-test.ino => BluePill-RTClock-test/BluePill-RTClock-test.ino} (74%)

diff --git a/STM32F1/libraries/RTClock/examples/BlutPill-RTClock-test/BlutPill-RTClock-test.ino b/STM32F1/libraries/RTClock/examples/BluePill-RTClock-test/BluePill-RTClock-test.ino
similarity index 74%
rename from STM32F1/libraries/RTClock/examples/BlutPill-RTClock-test/BlutPill-RTClock-test.ino
rename to STM32F1/libraries/RTClock/examples/BluePill-RTClock-test/BluePill-RTClock-test.ino
index b6e661069..d49025a1d 100644
--- a/STM32F1/libraries/RTClock/examples/BlutPill-RTClock-test/BlutPill-RTClock-test.ino
+++ b/STM32F1/libraries/RTClock/examples/BluePill-RTClock-test/BluePill-RTClock-test.ino
@@ -14,6 +14,13 @@
   ##  Why the 10 bits Unix epoch time be used?
 ****Because I wanna connect to NTP server by ESP-8266.
 ****in the <NTPClient.h> library. getNtpTime() will return this 10 bits Unix epoch time.
+*
+*  嗨！朋友们， 这是一个STM32F10x系列的RTC应用的例子，希望对你的编码有所帮助
+*  这个程序基于https://github.com/rogerclarkmelbourne/Arduino_STM32 ， 感谢所有贡献者的付出。
+*  程序测试了 F10x系列RTC 的 几种中断， 并通过LED和串口进行表达。
+*  RTClock 使用 UTC 作为时间标准， 你可以从https://www.epochconverter.com/ 获得 Unix epoch time数值
+*  并通过串口进行设置， 当然你也可以略微修改一下串口接收处理方法，直接从串口接收日期形式。如 2017-9-13-10:30:00, 
+*  另外一个方法是通过ESP8266获取NTP网络时间，并定期发送给F10x进行更新。
 */
 
 
@@ -23,7 +30,7 @@ RTClock rtclock (RTCSEL_LSE); // initialise
 int timezone = 8;      // change to your timezone
 time_t tt;
 time_t tt1;
-tm_t mtt = { 47, 9, 13, 3, 1, 22, 30, 30 };    // init time 47+1970 = 2017  Unix epoch Time counted from 00:00:00 1 Jan 1970  
+tm_t mtt = { 47, 9, 13, 3, 11, 22, 30, 30 };    // init time 47+1970 = 2017  Unix epoch Time counted from 00:00:00 1 Jan 1970  
 char weekday1[][7] = {"Sun", "Mon", "Tue", "Wed", "Thu", "Fri", "Sat"};  // 0,1,2,3,4,5,6
 uint8_t dateread[11];
 int globAlmCount = 0;
@@ -62,7 +69,8 @@ void setup()
   lastSPECAlmCount = ~SPECAlmCount;
   Serial.begin(115200);
   pinMode(LED_PIN, OUTPUT);
-  tt = rtclock.makeTime(mtt);   
+  tt = rtclock.makeTime(mtt); 
+  rtclock.setTime(tt);  
   tt1 = tt;
   rtclock.attachAlarmInterrupt(blink);// Call blink
   rtclock.attachSecondsInterrupt(SecondCount);// Call SecondCount
@@ -79,7 +87,8 @@ void loop()
       i = 0;
       tt = (dateread[0] - '0') * 1000000000 + (dateread[1] - '0') * 100000000 + (dateread[2] - '0') * 10000000 + (dateread[3] - '0') * 1000000 + (dateread[4] - '0') * 100000;
       tt += (dateread[5] - '0') * 10000 + (dateread[6] - '0') * 1000 + (dateread[7] - '0') * 100 + (dateread[8] - '0') * 10 + (dateread[9] - '0');
-      tt = rtclock.TimeZone(tt, timezone);    //adjust to your local date
+      rtclock.TimeZone(tt, timezone);    //adjust to your local date
+      rtclock.setTime(rtclock.TimeZone(tt, timezone));
     }
   }
   if (lastGlobAlmCount != globAlmCount | lastSPECAlmCount != SPECAlmCount ) {
@@ -111,20 +120,20 @@ void loop()
   if (tt1 != tt & dispflag == true )
   {
     tt1 = tt;
-    rtclock.breakTime(tt, mtt);
+    //rtclock.breakTime(tt, mtt);
     Serial.print("Date:  ");
-    Serial.print(mtt.day);
+    Serial.print(rtclock.day());
     Serial.print("- ");
-    Serial.print(mtt.month);
+    Serial.print(rtclock.month());
     Serial.print("  ");
-    Serial.print(mtt.year + 1970);
+    Serial.print(rtclock.year() + 1970);
     Serial.print("  ");
-    Serial.print(weekday1[mtt.weekday]);
+    Serial.print(weekday1[rtclock.weekday()]);
     Serial.print("  Time: ");
-    Serial.print(mtt.hour);
+    Serial.print(rtclock.hour());
     Serial.print(" : ");
-    Serial.print(mtt.minute);
+    Serial.print(rtclock.minute());
     Serial.print(" : ");
-    Serial.println(mtt.second);
+    Serial.println(rtclock.second());
   }
 }
diff --git a/STM32F1/libraries/RTClock/src/RTClock.h b/STM32F1/libraries/RTClock/src/RTClock.h
index e67fcb33b..6f1cba067 100644
--- a/STM32F1/libraries/RTClock/src/RTClock.h
+++ b/STM32F1/libraries/RTClock/src/RTClock.h
@@ -72,7 +72,7 @@ class RTClock {
 	uint8_t second(time_t t)  { breakTime(t, tmm); return tmm.second; }
 	uint8_t isPM(time_t t)    { return (hour(t)>=12); }
 	
-	time_t TimeZone(time_t t, int TZ)  { return ( t - (TZ * SECS_PER_HOUR)); }    // usage: localtime = TimeZone(UnixTime, 8); // Beijing timezone = 8  
+	time_t TimeZone(time_t t, int TZ)  { return ( t + (TZ * SECS_PER_HOUR)); }    // usage: localtime = TimeZone(UnixTime, 8); // Beijing timezone = 8  
 	
 	void createAlarm(voidFuncPtr function, time_t alarm_time_t); 
 	void createAlarm(voidFuncPtr function, struct tm_t & alarm_tm);
@@ -95,4 +95,4 @@ class RTClock {
 
 
 #endif // _RTCLOCK_H_
-                                                                                        
+                                                                                        
\ No newline at end of file

From c25957ee21b93686f650d3157714551a6dbbc10f Mon Sep 17 00:00:00 2001
From: csnol <csnol@126.com>
Date: Thu, 14 Sep 2017 20:47:12 +0800
Subject: [PATCH 198/307] Add removeAlarm function

---
 .../examples/RTC-Serial-Set-Newlibrary.ino    |  80 ------------------
 .../examples/STM32F103-RTC-Serial-Set.jpg     | Bin 131470 -> 0 bytes
 STM32F1/libraries/RTClock/keywords.txt        |   1 +
 STM32F1/libraries/RTClock/src/RTClock.cpp     |   4 +
 STM32F1/libraries/RTClock/src/RTClock.h       |   3 +-
 5 files changed, 7 insertions(+), 81 deletions(-)
 delete mode 100644 STM32F1/libraries/RTClock/examples/RTC-Serial-Set-Newlibrary.ino
 delete mode 100644 STM32F1/libraries/RTClock/examples/STM32F103-RTC-Serial-Set.jpg

diff --git a/STM32F1/libraries/RTClock/examples/RTC-Serial-Set-Newlibrary.ino b/STM32F1/libraries/RTClock/examples/RTC-Serial-Set-Newlibrary.ino
deleted file mode 100644
index ba89a4e02..000000000
--- a/STM32F1/libraries/RTClock/examples/RTC-Serial-Set-Newlibrary.ino
+++ /dev/null
@@ -1,80 +0,0 @@
-/*   STM32F103C8 Black Pill ( PB12)
-
-  Serialport set and display RTC clock , Write by CSNOL https://github.com/csnol/STM32-Examples
-  based on https://github.com/rogerclarkmelbourne/Arduino_STM32
-
-  1. Blink on PB12 per 1s.
-  2. change to your timezone in the sketch; .
-  3. get Unix epoch time from https://www.epochconverter.com/ ;
-  4. last step input the 10 bits number( example: 1503945555) to Serialport ;
-  5. the clock will be reset to you wanted.
-
-  ##  Why the 10 bits Unix epoch time be used?
-****Because I wanna connect to NTP server by ESP-8266.
-****in the <NTPClient.h> library. getNtpTime() will return this 10 bits Unix epoch time.
-*/
-
-
-#include <RTClock.h>
-
-RTClock rtclock (RTCSEL_LSE); // initialise
-time_t tt;
-tm_t mtt = { 47, 8, 27, 0, 1, 20, 30, 30 };
-char weekday1[][7] = {"Sun", "Mon", "Tue", "Wed", "Thu", "Fri", "Sat"};  // 0,1,2,3,4,5,6
-uint8_t timeread[11];
-int timezone = 8 * 3600;    // timezone -8 + DST +1 = -7  CA USA
-time_t tt1;
-
-#define LED_PIN PB12
-
-// This function is called in the attachSecondsInterrpt
-void blink ()
-{
-  digitalWrite(LED_PIN, !digitalRead(LED_PIN));
-  tt++;
-}
-
-void setup()
-{
-  Serial.begin(115200);
-  pinMode(LED_PIN, OUTPUT);
-  tt = rtclock.makeTime(mtt);
-  tt1 = tt;
-  rtclock.attachSecondsInterrupt(blink);// Call blink
-}
-
-
-int i = 0;
-void loop()
-{
-  while (Serial.available())
-  { timeread[i] = Serial.read();
-    if (i < 11) {
-      i++;
-    }
-    else {
-      i = 0;
-      tt = (timeread[0] - '0') * 1000000000 + (timeread[1] - '0') * 100000000 + (timeread[2] - '0') * 10000000 + (timeread[3] - '0') * 1000000 + (timeread[4] - '0') * 100000;
-      tt += (timeread[5] - '0') * 10000 + (timeread[6] - '0') * 1000 + (timeread[7] - '0') * 100 + (timeread[8] - '0') * 10 + (timeread[9] - '0') + timezone;
-    }
-  }
-  if (tt1 != tt)
-  {
-    tt1 = tt;
-    rtclock.breakTime(tt, mtt);
-    Serial.print("Date:  ");
-    Serial.print(mtt.day);
-    Serial.print("- ");
-    Serial.print(mtt.month);
-    Serial.print("  ");
-    Serial.print(mtt.year + 1970);
-    Serial.print("  ");
-    Serial.print(weekday1[mtt.weekday]);
-    Serial.print("  Time: ");
-    Serial.print(mtt.hour);
-    Serial.print(" : ");
-    Serial.print(mtt.minute);
-    Serial.print(" : ");
-    Serial.println(mtt.second);
-  }
-}
diff --git a/STM32F1/libraries/RTClock/examples/STM32F103-RTC-Serial-Set.jpg b/STM32F1/libraries/RTClock/examples/STM32F103-RTC-Serial-Set.jpg
deleted file mode 100644
index b2e701ea9e4789dd48ad0bbfe2c93534d7c61c19..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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diff --git a/STM32F1/libraries/RTClock/keywords.txt b/STM32F1/libraries/RTClock/keywords.txt
index 31bf13e05..7e9a60d18 100644
--- a/STM32F1/libraries/RTClock/keywords.txt
+++ b/STM32F1/libraries/RTClock/keywords.txt
@@ -13,6 +13,7 @@ setTime			KEYWORD2
 getTime			KEYWORD2
 
 createAlarm		KEYWORD2
+removeAlarm		KEYWORD2
 setAlarmTime		KEYWORD2
 
 attachSecondsInterrupt	KEYWORD2
diff --git a/STM32F1/libraries/RTClock/src/RTClock.cpp b/STM32F1/libraries/RTClock/src/RTClock.cpp
index deefcf00e..e95bead86 100644
--- a/STM32F1/libraries/RTClock/src/RTClock.cpp
+++ b/STM32F1/libraries/RTClock/src/RTClock.cpp
@@ -194,6 +194,10 @@ time_t RTClock::makeTime(tm_t & tmm)
 		rtc_attach_interrupt(RTC_ALARM_SPECIFIC_INTERRUPT, function);
 	}
 	
+	void RTClock::removeAlarm() {
+		rtc_detach_interrupt(RTC_ALARM_SPECIFIC_INTERRUPT);
+	}
+	
 	void RTClock::attachSecondsInterrupt(voidFuncPtr function) {
 		rtc_attach_interrupt(RTC_SECONDS_INTERRUPT, function);
 	}
diff --git a/STM32F1/libraries/RTClock/src/RTClock.h b/STM32F1/libraries/RTClock/src/RTClock.h
index 6f1cba067..4d8399e80 100644
--- a/STM32F1/libraries/RTClock/src/RTClock.h
+++ b/STM32F1/libraries/RTClock/src/RTClock.h
@@ -76,11 +76,12 @@ class RTClock {
 	
 	void createAlarm(voidFuncPtr function, time_t alarm_time_t); 
 	void createAlarm(voidFuncPtr function, struct tm_t & alarm_tm);
+	void removeAlarm();
 	
 	void attachSecondsInterrupt(voidFuncPtr function); 
 	void detachSecondsInterrupt();
 	
-        void attachAlarmInterrupt(voidFuncPtr function); 
+    void attachAlarmInterrupt(voidFuncPtr function); 
 	void attachAlarmInterrupt(voidFuncPtr function, time_t alarm_time);
 	void detachAlarmInterrupt();
 	

From f84f73c4a1a350e8eda607a5e6b54f2b39a8c608 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Tue, 19 Sep 2017 20:42:16 +0200
Subject: [PATCH 199/307] Create hooks.c

similar to F1 - it was missing
---
 STM32F4/cores/maple/hooks.c | 31 +++++++++++++++++++++++++++++++
 1 file changed, 31 insertions(+)
 create mode 100644 STM32F4/cores/maple/hooks.c

diff --git a/STM32F4/cores/maple/hooks.c b/STM32F4/cores/maple/hooks.c
new file mode 100644
index 000000000..641eabc73
--- /dev/null
+++ b/STM32F4/cores/maple/hooks.c
@@ -0,0 +1,31 @@
+/*
+  Copyright (c) 2012 Arduino.  All right reserved.
+
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
+
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.
+  See the GNU Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+*/
+
+/**
+ * Empty yield() hook.
+ *
+ * This function is intended to be used by library writers to build
+ * libraries or sketches that supports cooperative threads.
+ *
+ * Its defined as a weak symbol and it can be redefined to implement a
+ * real cooperative scheduler.
+ */
+static void __empty() {
+	// Empty
+}
+void yield(void) __attribute__ ((weak, alias("__empty")));

From f8d28b8663a53fa37f75c2f20ed0aebc81c83fba Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Thu, 21 Sep 2017 17:35:20 +1000
Subject: [PATCH 200/307] Removed unused cygwin dll's from tools/win

---
 tools/win/cygiconv-2.dll | Bin 969728 -> 0 bytes
 tools/win/cygwin1.dll    | Bin 1872821 -> 0 bytes
 2 files changed, 0 insertions(+), 0 deletions(-)
 delete mode 100644 tools/win/cygiconv-2.dll
 delete mode 100644 tools/win/cygwin1.dll

diff --git a/tools/win/cygiconv-2.dll b/tools/win/cygiconv-2.dll
deleted file mode 100644
index 64fd39e3e9e2f266dfbb45bb8e6a6c5799cb14e8..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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From 43129d17a5dbe3835fa304d0f9ffdd9bd3274773 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Fri, 22 Sep 2017 11:26:58 +0200
Subject: [PATCH 201/307] Update graphicstest.ino

- use Adafruit_GFX_AS lib instead of Adafruit_GFX
---
 .../examples/graphicstest/graphicstest.ino                    | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/STM32F1/libraries/Adafruit_ILI9341_STM/examples/graphicstest/graphicstest.ino b/STM32F1/libraries/Adafruit_ILI9341_STM/examples/graphicstest/graphicstest.ino
index c75c99573..872b3e535 100644
--- a/STM32F1/libraries/Adafruit_ILI9341_STM/examples/graphicstest/graphicstest.ino
+++ b/STM32F1/libraries/Adafruit_ILI9341_STM/examples/graphicstest/graphicstest.ino
@@ -15,7 +15,7 @@
 
 
 #include "SPI.h"
-#include "Adafruit_GFX.h"
+#include "Adafruit_GFX_AS.h"
 #include "Adafruit_ILI9341_STM.h"
 
 // For the Adafruit shield, these are the default.
@@ -346,4 +346,4 @@ unsigned long testFilledRoundRects() {
   }
 
   return micros() - start;
-}
\ No newline at end of file
+}

From 6b2ca7dbe70d7354c26d775f7d83a98cf8d537d8 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Fri, 22 Sep 2017 11:28:08 +0200
Subject: [PATCH 202/307] Update onoffbutton.ino

use Adafruit_GFX_AS lib instead of Adafruit_GFX
---
 .../Adafruit_ILI9341_STM/examples/onoffbutton/onoffbutton.ino   | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/libraries/Adafruit_ILI9341_STM/examples/onoffbutton/onoffbutton.ino b/STM32F1/libraries/Adafruit_ILI9341_STM/examples/onoffbutton/onoffbutton.ino
index b37383599..5f6049642 100644
--- a/STM32F1/libraries/Adafruit_ILI9341_STM/examples/onoffbutton/onoffbutton.ino
+++ b/STM32F1/libraries/Adafruit_ILI9341_STM/examples/onoffbutton/onoffbutton.ino
@@ -3,7 +3,7 @@
 //
 //Thanks to Adafruit forums member Asteroid for the original sketch!
 //
-#include <Adafruit_GFX.h>
+#include <Adafruit_GFX_AS.h>
 #include <SPI.h>
 #include <Wire.h>
 #include <Adafruit_ILI9341_STM.h>

From 5c1708e193962df2b1ad4f39a6a6cb035b41bea4 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Fri, 22 Sep 2017 11:29:41 +0200
Subject: [PATCH 203/307] Update onoffbutton_breakout.ino

- use Adafruit_GFX_AS lib instead of Adafruit_GFX
---
 .../examples/onoffbutton_breakout/onoffbutton_breakout.ino      | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/libraries/Adafruit_ILI9341_STM/examples/onoffbutton_breakout/onoffbutton_breakout.ino b/STM32F1/libraries/Adafruit_ILI9341_STM/examples/onoffbutton_breakout/onoffbutton_breakout.ino
index 9e35441da..ad8fef205 100644
--- a/STM32F1/libraries/Adafruit_ILI9341_STM/examples/onoffbutton_breakout/onoffbutton_breakout.ino
+++ b/STM32F1/libraries/Adafruit_ILI9341_STM/examples/onoffbutton_breakout/onoffbutton_breakout.ino
@@ -3,7 +3,7 @@
 //
 //Thanks to Adafruit forums member Asteroid for the original sketch!
 //
-#include <Adafruit_GFX.h>
+#include <Adafruit_GFX_AS.h>
 #include <SPI.h>
 #include <Wire.h>
 #include <Adafruit_ILI9341_STM.h>

From db000d1411128e2611a849d394bddc760a731453 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Fri, 22 Sep 2017 11:30:29 +0200
Subject: [PATCH 204/307] Update spitftbitmap.ino

- use Adafruit_GFX_AS lib instead of Adafruit_GFX
---
 .../Adafruit_ILI9341_STM/examples/spitftbitmap/spitftbitmap.ino | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/libraries/Adafruit_ILI9341_STM/examples/spitftbitmap/spitftbitmap.ino b/STM32F1/libraries/Adafruit_ILI9341_STM/examples/spitftbitmap/spitftbitmap.ino
index 84ff46450..5e46d68da 100644
--- a/STM32F1/libraries/Adafruit_ILI9341_STM/examples/spitftbitmap/spitftbitmap.ino
+++ b/STM32F1/libraries/Adafruit_ILI9341_STM/examples/spitftbitmap/spitftbitmap.ino
@@ -14,7 +14,7 @@
  ****************************************************/
 
 
-#include <Adafruit_GFX.h>    // Core graphics library
+#include <Adafruit_GFX_AS.h>    // Core graphics library
 #include "Adafruit_ILI9341_STM.h" // Hardware-specific library
 #include <SPI.h>
 #include <SD.h>

From c6c53b79ad4a2f89f3fb5b0dd6ddb153d6da3a9d Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Fri, 22 Sep 2017 11:31:00 +0200
Subject: [PATCH 205/307] Update touchpaint.ino

- use Adafruit_GFX_AS lib instead of Adafruit_GFX
---
 .../Adafruit_ILI9341_STM/examples/touchpaint/touchpaint.ino     | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/libraries/Adafruit_ILI9341_STM/examples/touchpaint/touchpaint.ino b/STM32F1/libraries/Adafruit_ILI9341_STM/examples/touchpaint/touchpaint.ino
index e10ecd9cf..5d09180dc 100644
--- a/STM32F1/libraries/Adafruit_ILI9341_STM/examples/touchpaint/touchpaint.ino
+++ b/STM32F1/libraries/Adafruit_ILI9341_STM/examples/touchpaint/touchpaint.ino
@@ -14,7 +14,7 @@
  ****************************************************/
 
 
-#include <Adafruit_GFX.h>    // Core graphics library
+#include <Adafruit_GFX_AS.h>    // Core graphics library
 #include <SPI.h>
 #include <Wire.h>      // this is needed even tho we aren't using it
 #include <Adafruit_ILI9341.h>

From 7fda02a821dbb962a2ee33c814cd106dc85f1883 Mon Sep 17 00:00:00 2001
From: Bill Greiman <fat16lib@sbcglobal.net>
Date: Fri, 22 Sep 2017 10:40:05 -0700
Subject: [PATCH 206/307] SPI add const qualifier

Add const qualifier to SPI member function arguments for write and
transmit buffers.
---
 STM32F1/libraries/SPI/src/SPI.cpp | 22 +++++++++++-----------
 STM32F1/libraries/SPI/src/SPI.h   | 12 ++++++------
 STM32F4/libraries/SPI/src/SPI.cpp | 10 +++++-----
 STM32F4/libraries/SPI/src/SPI.h   |  6 +++---
 4 files changed, 25 insertions(+), 25 deletions(-)

diff --git a/STM32F1/libraries/SPI/src/SPI.cpp b/STM32F1/libraries/SPI/src/SPI.cpp
index 34df62e33..c07e2ea4a 100644
--- a/STM32F1/libraries/SPI/src/SPI.cpp
+++ b/STM32F1/libraries/SPI/src/SPI.cpp
@@ -350,10 +350,10 @@ void SPIClass::write(uint16 data, uint32 n)
     while ( (regs->SR & SPI_SR_BSY) != 0); // wait until BSY=0 before returning 
 }
 
-void SPIClass::write(void *data, uint32 length)
+void SPIClass::write(const void *data, uint32 length)
 {
     spi_dev * spi_d = _currentSetting->spi_d;
-    spi_tx(spi_d, (void*)data, length); // data can be array of bytes or words
+    spi_tx(spi_d, data, length); // data can be array of bytes or words
     while (spi_is_tx_empty(spi_d) == 0); // "5. Wait until TXE=1 ..."
     while (spi_is_busy(spi_d) != 0); // "... and then wait until BSY=0 before disabling the SPI."
 }
@@ -391,7 +391,7 @@ uint16_t SPIClass::transfer16(uint16_t data) const
 *	On exit TX buffer is not modified, and RX buffer cotains the received data.
 *	Still in progress.
 */
-void SPIClass::dmaTransferSet(void *transmitBuf, void *receiveBuf) {
+void SPIClass::dmaTransferSet(const void *transmitBuf, void *receiveBuf) {
     dma_init(_currentSetting->spiDmaDev);
     //spi_rx_dma_enable(_currentSetting->spi_d);
     //spi_tx_dma_enable(_currentSetting->spi_d);
@@ -401,11 +401,11 @@ void SPIClass::dmaTransferSet(void *transmitBuf, void *receiveBuf) {
     if (!transmitBuf) {
     transmitBuf = &ff;
     dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
-                       transmitBuf, dma_bit_size, (DMA_FROM_MEM));// Transmit FF repeatedly
+                       (volatile void*)transmitBuf, dma_bit_size, (DMA_FROM_MEM));// Transmit FF repeatedly
     }
     else {
     dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
-                       transmitBuf, dma_bit_size, (DMA_MINC_MODE |  DMA_FROM_MEM ));// Transmit buffer DMA
+                       (volatile void*)transmitBuf, dma_bit_size, (DMA_MINC_MODE |  DMA_FROM_MEM ));// Transmit buffer DMA
     }
     dma_set_priority(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, DMA_PRIORITY_LOW);
     dma_set_priority(_currentSetting->spiDmaDev, _currentSetting->spiRxDmaChannel, DMA_PRIORITY_VERY_HIGH);
@@ -451,7 +451,7 @@ uint8 SPIClass::dmaTransferRepeat(uint16 length) {
 *	Still in progress.
 */
 
-uint8 SPIClass::dmaTransfer(void *transmitBuf, void *receiveBuf, uint16 length) {
+uint8 SPIClass::dmaTransfer(const void *transmitBuf, void *receiveBuf, uint16 length) {
     dmaTransferSet(transmitBuf, receiveBuf);
     return dmaTransferRepeat(length);
 }
@@ -463,12 +463,12 @@ uint8 SPIClass::dmaTransfer(void *transmitBuf, void *receiveBuf, uint16 length)
 *	2016 - stevstrong - reworked to automatically detect bit size from SPI setting
 */
 
-void SPIClass::dmaSendSet(void * transmitBuf, bool minc) {
+void SPIClass::dmaSendSet(const void * transmitBuf, bool minc) {
    uint32 flags = ( (DMA_MINC_MODE*minc) | DMA_FROM_MEM | DMA_TRNS_CMPLT);
    dma_init(_currentSetting->spiDmaDev);
    dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
    dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
-                       transmitBuf, dma_bit_size, flags);// Transmit buffer DMA
+                       (volatile void*)transmitBuf, dma_bit_size, flags);// Transmit buffer DMA
    dma_set_priority(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, DMA_PRIORITY_LOW);
 }
 
@@ -498,12 +498,12 @@ uint8 SPIClass::dmaSendRepeat(uint16 length) {
     return b;
 }
 
-uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length, bool minc) {
+uint8 SPIClass::dmaSend(const void * transmitBuf, uint16 length, bool minc) {
     dmaSendSet(transmitBuf, minc);
     return dmaSendRepeat(length);
 }
 
-uint8 SPIClass::dmaSendAsync(void * transmitBuf, uint16 length, bool minc) {
+uint8 SPIClass::dmaSendAsync(const void * transmitBuf, uint16 length, bool minc) {
     uint8 b = 0;	
 
     if (_currentSetting->state != SPI_STATE_READY)
@@ -529,7 +529,7 @@ uint8 SPIClass::dmaSendAsync(void * transmitBuf, uint16 length, bool minc) {
     // TX
     dma_xfer_size dma_bit_size = (_currentSetting->dataSize==DATA_SIZE_16BIT) ? DMA_SIZE_16BITS : DMA_SIZE_8BITS;
     dma_setup_transfer(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, &_currentSetting->spi_d->regs->DR, dma_bit_size,
-    transmitBuf, dma_bit_size, flags);// Transmit buffer DMA 
+    (volatile void*)transmitBuf, dma_bit_size, flags);// Transmit buffer DMA 
     dma_set_num_transfers(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel, length);
     dma_clear_isr_bits(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);
     dma_enable(_currentSetting->spiDmaDev, _currentSetting->spiTxDmaChannel);// enable transmit
diff --git a/STM32F1/libraries/SPI/src/SPI.h b/STM32F1/libraries/SPI/src/SPI.h
index 25eea861c..686d23d4f 100644
--- a/STM32F1/libraries/SPI/src/SPI.h
+++ b/STM32F1/libraries/SPI/src/SPI.h
@@ -278,7 +278,7 @@ class SPIClass {
      * @param buffer Bytes/words to transmit.
      * @param length Number of bytes/words in buffer to transmit.
      */
-    void write(void * buffer, uint32 length);
+    void write(const void * buffer, uint32 length);
 
     /**
      * @brief Transmit a byte, then return the next unread byte.
@@ -301,8 +301,8 @@ class SPIClass {
      * @param receiveBuf buffer Bytes to save received data. 
      * @param length Number of bytes in buffer to transmit.
 	 */
-    uint8 dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length);
-    void dmaTransferSet(void *transmitBuf, void *receiveBuf);
+    uint8 dmaTransfer(const void * transmitBuf, void * receiveBuf, uint16 length);
+    void dmaTransferSet(const void *transmitBuf, void *receiveBuf);
     uint8 dmaTransferRepeat(uint16 length);
 
 	/**
@@ -315,11 +315,11 @@ class SPIClass {
      * @param length Number of bytes in buffer to transmit.
 	 * @param minc Set to use Memory Increment mode, clear to use Circular mode.
      */
-    uint8 dmaSend(void * transmitBuf, uint16 length, bool minc = 1);
-    void dmaSendSet(void * transmitBuf, bool minc);
+    uint8 dmaSend(const void * transmitBuf, uint16 length, bool minc = 1);
+    void dmaSendSet(const void * transmitBuf, bool minc);
     uint8 dmaSendRepeat(uint16 length);
 
-    uint8 dmaSendAsync(void * transmitBuf, uint16 length, bool minc = 1);
+    uint8 dmaSendAsync(const void * transmitBuf, uint16 length, bool minc = 1);
     /*
      * Pin accessors
      */
diff --git a/STM32F4/libraries/SPI/src/SPI.cpp b/STM32F4/libraries/SPI/src/SPI.cpp
index 45aa366b2..72a4c4835 100644
--- a/STM32F4/libraries/SPI/src/SPI.cpp
+++ b/STM32F4/libraries/SPI/src/SPI.cpp
@@ -372,7 +372,7 @@ void SPIClass::write(uint16 data, uint32 n)
 	while ( (regs->SR & SPI_SR_BSY) != 0); // wait until BSY=0 before returning 
 }
 
-void SPIClass::write(void *data, uint32 length)
+void SPIClass::write(const void *data, uint32 length)
 {
 	spi_dev * spi_d = _currentSetting->spi_d;
 	spi_tx(spi_d, (void*)data, length); // data can be array of bytes or words
@@ -407,7 +407,7 @@ uint16_t SPIClass::transfer16(uint16_t wr_data) const
 *	On exit TX buffer is not modified, and RX buffer contains the received data.
 *	Still in progress.
 */
-uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length)
+uint8 SPIClass::dmaTransfer(const void * transmitBuf, void * receiveBuf, uint16 length)
 {
 	if (length == 0) return 0;
 
@@ -442,7 +442,7 @@ uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length
 						_currentSetting->spiDmaChannel,
 						dma_bit_size,
 						&_currentSetting->spi_d->regs->DR,	// peripheral address
-						transmitBuf,						// memory bank 0 address
+						(volatile void*)transmitBuf,						// memory bank 0 address
 						NULL,								// memory bank 1 address
 						flags
 	);
@@ -477,7 +477,7 @@ uint8 SPIClass::dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length
 *	Still in progress.
 *	2016 - stevstrong - reworked to automatically detect bit size from SPI setting
 */
-uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length, bool minc)
+uint8 SPIClass::dmaSend(const void * transmitBuf, uint16 length, bool minc)
 {
 	if (length == 0) return 0;
 	uint8 b = 0;
@@ -489,7 +489,7 @@ uint8 SPIClass::dmaSend(void * transmitBuf, uint16 length, bool minc)
 						_currentSetting->spiDmaChannel,
 						dma_bit_size,
 						&_currentSetting->spi_d->regs->DR,	// peripheral address
-						transmitBuf,						// memory bank 0 address
+						(volatile void*)transmitBuf,						// memory bank 0 address
 						NULL,								// memory bank 1 address
 						( (DMA_MINC_MODE*minc) | DMA_FROM_MEM ) //| DMA_TRNS_CMPLT ) // flags
 	);// Transmit buffer DMA 
diff --git a/STM32F4/libraries/SPI/src/SPI.h b/STM32F4/libraries/SPI/src/SPI.h
index cabc0c260..f46795ce3 100644
--- a/STM32F4/libraries/SPI/src/SPI.h
+++ b/STM32F4/libraries/SPI/src/SPI.h
@@ -248,7 +248,7 @@ class SPIClass {
      * @param buffer Bytes/words to transmit.
      * @param length Number of bytes/words in buffer to transmit.
      */
-    void write(void * buffer, uint32 length);
+    void write(const void * buffer, uint32 length);
 
     /**
      * @brief Transmit a byte, then return the next unread byte.
@@ -272,7 +272,7 @@ class SPIClass {
      * @param receiveBuf buffer Bytes to save received data. 
      * @param length Number of bytes in buffer to transmit.
 	 */
-	uint8 dmaTransfer(void * transmitBuf, void * receiveBuf, uint16 length);
+	uint8 dmaTransfer(const void * transmitBuf, void * receiveBuf, uint16 length);
 
 	/**
      * @brief Sets up a DMA Transmit for SPI 8 or 16 bit transfer mode.
@@ -283,7 +283,7 @@ class SPIClass {
      * @param data buffer half words to transmit,
      * @param length Number of bytes in buffer to transmit.
      */
-	uint8 dmaSend(void * transmitBuf, uint16 length, bool minc = 1);
+	uint8 dmaSend(const void * transmitBuf, uint16 length, bool minc = 1);
 #endif
 
     /*

From f65e6905e93fb9c844c557aac62233872b34c4a5 Mon Sep 17 00:00:00 2001
From: Peter Edwards <sweetlilmre@gmail.com>
Date: Thu, 28 Sep 2017 12:08:59 +0200
Subject: [PATCH 207/307] Removed non standard functionality from Print class
 for BYTE "base" as this is available via e.g. Serial.write and conflicts with
 the FatFS library and potentially anything else defining BYTE Fixed sketches
 using this behaviour

---
 STM32F1/cores/maple/Print.cpp                        | 12 +-----------
 STM32F1/cores/maple/Print.h                          |  1 -
 .../examples/Communication/ASCIITable/ASCIITable.ino |  2 +-
 .../examples/Communication/MIDI/Midi.ino             |  6 +++---
 .../SerialCallResponse/SerialCallResponse.ino        |  8 ++++----
 .../SerialPassthrough/SerialPassthrough.ino          |  2 +-
 .../examples/General/USB_ASCII/USB_ASCII.ino         |  2 +-
 STM32F3/cores/maple/wirish/Print.cpp                 | 10 +---------
 STM32F3/cores/maple/wirish/Print.h                   |  1 -
 STM32F4/cores/maple/Print.cpp                        | 12 +-----------
 STM32F4/cores/maple/Print.h                          |  1 -
 11 files changed, 13 insertions(+), 44 deletions(-)

diff --git a/STM32F1/cores/maple/Print.cpp b/STM32F1/cores/maple/Print.cpp
index 76f386b78..0a71cf018 100644
--- a/STM32F1/cores/maple/Print.cpp
+++ b/STM32F1/cores/maple/Print.cpp
@@ -99,10 +99,6 @@ size_t Print::print(unsigned long n, int base) {
 }
 
 size_t Print::print(long long n, int base) {
-    if (base == BYTE) 
-	{
-        return write((uint8)n);
-    }
     if (n < 0) {
         print('-');
         n = -n;
@@ -111,13 +107,7 @@ size_t Print::print(long long n, int base) {
 }
 
 size_t Print::print(unsigned long long n, int base) {
-size_t c=0;
-    if (base == BYTE) {
-        c= write((uint8)n);
-    } else {
-        c= printNumber(n, base);
-    }
-	return c;
+	return printNumber(n, base);
 }
 
 size_t Print::print(double n, int digits) {
diff --git a/STM32F1/cores/maple/Print.h b/STM32F1/cores/maple/Print.h
index bd373853f..f265facc2 100644
--- a/STM32F1/cores/maple/Print.h
+++ b/STM32F1/cores/maple/Print.h
@@ -28,7 +28,6 @@
 #include "Printable.h"
 
 enum {
-    BYTE = 0,
     BIN  = 2,
     OCT  = 8,
     DEC  = 10,
diff --git a/STM32F1/libraries/A_STM32_Examples/examples/Communication/ASCIITable/ASCIITable.ino b/STM32F1/libraries/A_STM32_Examples/examples/Communication/ASCIITable/ASCIITable.ino
index fc5e5d73e..d64745729 100644
--- a/STM32F1/libraries/A_STM32_Examples/examples/Communication/ASCIITable/ASCIITable.ino
+++ b/STM32F1/libraries/A_STM32_Examples/examples/Communication/ASCIITable/ASCIITable.ino
@@ -47,7 +47,7 @@ void loop() {
     // Prints value unaltered, i.e. the raw binary version of the
     // byte. The serial monitor interprets all bytes as
     // ASCII, so 33, the first number,  will show up as '!'
-    Serial.print(thisByte, BYTE);
+    Serial.write(thisByte);
 
     Serial.print(", dec: ");
     // Prints value as string as an ASCII-encoded decimal (base 10).
diff --git a/STM32F1/libraries/A_STM32_Examples/examples/Communication/MIDI/Midi.ino b/STM32F1/libraries/A_STM32_Examples/examples/Communication/MIDI/Midi.ino
index 820ffdc6f..4feaea799 100644
--- a/STM32F1/libraries/A_STM32_Examples/examples/Communication/MIDI/Midi.ino
+++ b/STM32F1/libraries/A_STM32_Examples/examples/Communication/MIDI/Midi.ino
@@ -44,8 +44,8 @@ void loop() {
 // Plays a MIDI note.  Doesn't check to see that cmd is greater than
 // 127, or that data values are less than 127:
 void noteOn(int cmd, int pitch, int velocity) {
-    Serial1.print(cmd, BYTE);
-    Serial1.print(pitch, BYTE);
-    Serial1.print(velocity, BYTE);
+    Serial1.write(cmd);
+    Serial1.write(pitch);
+    Serial1.write(velocity);
 }
 
diff --git a/STM32F1/libraries/A_STM32_Examples/examples/Communication/SerialCallResponse/SerialCallResponse.ino b/STM32F1/libraries/A_STM32_Examples/examples/Communication/SerialCallResponse/SerialCallResponse.ino
index eee35e3cc..81270cf83 100644
--- a/STM32F1/libraries/A_STM32_Examples/examples/Communication/SerialCallResponse/SerialCallResponse.ino
+++ b/STM32F1/libraries/A_STM32_Examples/examples/Communication/SerialCallResponse/SerialCallResponse.ino
@@ -50,15 +50,15 @@ void loop() {
         // read switch, map it to 0 or 255
         thirdSensor = map(digitalRead(2), 0, 1, 0, 255);
         // send sensor values:
-        Serial.print(firstSensor, BYTE);
-        Serial.print(secondSensor, BYTE);
-        Serial.print(thirdSensor, BYTE);
+        Serial.write(firstSensor);
+        Serial.write(secondSensor);
+        Serial.write(thirdSensor);
     }
 }
 
 void establishContact() {
     while (Serial.available() <= 0) {
-        Serial.print('A', BYTE);   // send a capital A
+        Serial.write('A');   // send a capital A
         delay(300);
     }
 }
diff --git a/STM32F1/libraries/A_STM32_Examples/examples/Communication/SerialPassthrough/SerialPassthrough.ino b/STM32F1/libraries/A_STM32_Examples/examples/Communication/SerialPassthrough/SerialPassthrough.ino
index 71b9e34fd..0d348f898 100644
--- a/STM32F1/libraries/A_STM32_Examples/examples/Communication/SerialPassthrough/SerialPassthrough.ino
+++ b/STM32F1/libraries/A_STM32_Examples/examples/Communication/SerialPassthrough/SerialPassthrough.ino
@@ -26,6 +26,6 @@ void loop() {
     // Read from Serial1, send over USB on Maple (or uses hardware serial 1 and hardware serial 2 on non-maple boards:
     if (Serial1.available()) {
         inByte = Serial1.read();
-        Serial.print(inByte, BYTE);
+        Serial.write(inByte);
     }
 }
diff --git a/STM32F1/libraries/A_STM32_Examples/examples/General/USB_ASCII/USB_ASCII.ino b/STM32F1/libraries/A_STM32_Examples/examples/General/USB_ASCII/USB_ASCII.ino
index a884978dc..8a6fe5359 100644
--- a/STM32F1/libraries/A_STM32_Examples/examples/General/USB_ASCII/USB_ASCII.ino
+++ b/STM32F1/libraries/A_STM32_Examples/examples/General/USB_ASCII/USB_ASCII.ino
@@ -67,7 +67,7 @@ void loop() {
     // Prints value unaltered, i.e. the raw binary version of the
     // byte. The serial monitor interprets all bytes as
     // ASCII, so 33, the first number,  will show up as '!'
-    Serial.print(thisByte, BYTE);
+    Serial.write(thisByte);
 
     Serial.print(", dec: ");
     // Prints value as string as an ASCII-encoded decimal (base 10).
diff --git a/STM32F3/cores/maple/wirish/Print.cpp b/STM32F3/cores/maple/wirish/Print.cpp
index f6bc0c6be..9a8808dd3 100644
--- a/STM32F3/cores/maple/wirish/Print.cpp
+++ b/STM32F3/cores/maple/wirish/Print.cpp
@@ -88,10 +88,6 @@ void Print::print(unsigned long n, int base) {
 }
 
 void Print::print(long long n, int base) {
-    if (base == BYTE) {
-        write((uint8)n);
-        return;
-    }
     if (n < 0) {
         print('-');
         n = -n;
@@ -100,11 +96,7 @@ void Print::print(long long n, int base) {
 }
 
 void Print::print(unsigned long long n, int base) {
-    if (base == BYTE) {
-        write((uint8)n);
-    } else {
-        printNumber(n, base);
-    }
+    printNumber(n, base);
 }
 
 void Print::print(double n, int digits) {
diff --git a/STM32F3/cores/maple/wirish/Print.h b/STM32F3/cores/maple/wirish/Print.h
index 5fd0b7a5c..52203eae0 100644
--- a/STM32F3/cores/maple/wirish/Print.h
+++ b/STM32F3/cores/maple/wirish/Print.h
@@ -26,7 +26,6 @@
 #include <libmaple/libmaple_types.h>
 
 enum {
-    BYTE = 0,
     BIN  = 2,
     OCT  = 8,
     DEC  = 10,
diff --git a/STM32F4/cores/maple/Print.cpp b/STM32F4/cores/maple/Print.cpp
index 76f386b78..0a71cf018 100644
--- a/STM32F4/cores/maple/Print.cpp
+++ b/STM32F4/cores/maple/Print.cpp
@@ -99,10 +99,6 @@ size_t Print::print(unsigned long n, int base) {
 }
 
 size_t Print::print(long long n, int base) {
-    if (base == BYTE) 
-	{
-        return write((uint8)n);
-    }
     if (n < 0) {
         print('-');
         n = -n;
@@ -111,13 +107,7 @@ size_t Print::print(long long n, int base) {
 }
 
 size_t Print::print(unsigned long long n, int base) {
-size_t c=0;
-    if (base == BYTE) {
-        c= write((uint8)n);
-    } else {
-        c= printNumber(n, base);
-    }
-	return c;
+	return printNumber(n, base);
 }
 
 size_t Print::print(double n, int digits) {
diff --git a/STM32F4/cores/maple/Print.h b/STM32F4/cores/maple/Print.h
index bd373853f..f265facc2 100644
--- a/STM32F4/cores/maple/Print.h
+++ b/STM32F4/cores/maple/Print.h
@@ -28,7 +28,6 @@
 #include "Printable.h"
 
 enum {
-    BYTE = 0,
     BIN  = 2,
     OCT  = 8,
     DEC  = 10,

From 31fa24bdd1cc9d86a96e23f8d21e5a80569273d0 Mon Sep 17 00:00:00 2001
From: victorpv <victor_pv@hotmail.com>
Date: Wed, 4 Oct 2017 00:29:13 -0500
Subject: [PATCH 208/307] Update to util_adc.c file to pass pointer correctly.

This was wrong and causing warnings during compilation.
---
 STM32F1/libraries/STM32ADC/src/utility/util_adc.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/STM32F1/libraries/STM32ADC/src/utility/util_adc.c b/STM32F1/libraries/STM32ADC/src/utility/util_adc.c
index e64b58e20..360b235cd 100644
--- a/STM32F1/libraries/STM32ADC/src/utility/util_adc.c
+++ b/STM32F1/libraries/STM32ADC/src/utility/util_adc.c
@@ -137,8 +137,8 @@ void adc_dma_enable(adc_dev * dev) {
   bb_peri_set_bit(&dev->regs->CR2, ADC_CR2_DMA_BIT, 1);
 }
 
-uint8 poll_adc_convert(adc_dev *dev) {
-  return bb_peri_get_bit(dev->regs->SR, ADC_SR_EOC_BIT);
+uint8 poll_adc_convert(adc_dev * dev) {
+  return bb_peri_get_bit(&dev->regs->SR, ADC_SR_EOC_BIT);
   }
 
 

From ac7ccee71f90d0f2de28014022fac716956ce686 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Wed, 4 Oct 2017 11:11:05 +0200
Subject: [PATCH 209/307] Update touchpaint.ino

changed to correct header file
---
 .../Adafruit_ILI9341_STM/examples/touchpaint/touchpaint.ino     | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/libraries/Adafruit_ILI9341_STM/examples/touchpaint/touchpaint.ino b/STM32F1/libraries/Adafruit_ILI9341_STM/examples/touchpaint/touchpaint.ino
index 5d09180dc..0b29cd49e 100644
--- a/STM32F1/libraries/Adafruit_ILI9341_STM/examples/touchpaint/touchpaint.ino
+++ b/STM32F1/libraries/Adafruit_ILI9341_STM/examples/touchpaint/touchpaint.ino
@@ -17,7 +17,7 @@
 #include <Adafruit_GFX_AS.h>    // Core graphics library
 #include <SPI.h>
 #include <Wire.h>      // this is needed even tho we aren't using it
-#include <Adafruit_ILI9341.h>
+#include <Adafruit_ILI9341_STM.h>
 #include <Adafruit_STMPE610.h>
 
 // This is calibration data for the raw touch data to the screen coordinates

From 308b5c410f119a0d901f37fc3b7061d9883624b0 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Fri, 6 Oct 2017 18:04:56 +0200
Subject: [PATCH 210/307] Update boards.cpp

- remove repeated call to setup serial USB
---
 STM32F4/cores/maple/boards.cpp | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/STM32F4/cores/maple/boards.cpp b/STM32F4/cores/maple/boards.cpp
index 0d55e9414..4b0480f67 100644
--- a/STM32F4/cores/maple/boards.cpp
+++ b/STM32F4/cores/maple/boards.cpp
@@ -69,8 +69,7 @@ void init(void) {
     setupTimers();
 
 #ifdef SERIAL_USB
-    setupUSB();
-    SerialUSB.begin();
+    SerialUSB.begin(); // includes { setupUSB(); }
 #endif
 }
 

From 84d9c2bd204e34d83fcf848bf4824bbc6e010d04 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sun, 8 Oct 2017 14:03:20 +1100
Subject: [PATCH 211/307] Fixed issue in OLED_I2C lib caused by change to
 HardWire as default I2C

---
 STM32F1/libraries/OLED_I2C/hardware/arm/HW_STM32.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/libraries/OLED_I2C/hardware/arm/HW_STM32.h b/STM32F1/libraries/OLED_I2C/hardware/arm/HW_STM32.h
index 7060b448d..25967c7ca 100644
--- a/STM32F1/libraries/OLED_I2C/hardware/arm/HW_STM32.h
+++ b/STM32F1/libraries/OLED_I2C/hardware/arm/HW_STM32.h
@@ -1,4 +1,4 @@
-#include "HardWire.h"
+#include "Wire.h"
 #define WIRE_WRITE HWIRE.write
 
  HardWire HWIRE(2,I2C_FAST_MODE); // stupid compiler

From 3c2fce63eed6beb4652ec08b68dd0b7e035949d1 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sun, 8 Oct 2017 14:26:59 +1100
Subject: [PATCH 212/307] Update ILI9341 STM lib with version from SteveStrong,
 and also added ReadPixelsRGB24 to steve's version

---
 .../Adafruit_ILI9341_STM.cpp                  | 545 ++++++------------
 .../Adafruit_ILI9341_STM.h                    |  82 +--
 2 files changed, 223 insertions(+), 404 deletions(-)

diff --git a/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.cpp b/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.cpp
index 766b91034..914e4d153 100644
--- a/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.cpp
+++ b/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.cpp
@@ -4,119 +4,26 @@ This library has been modified for the Maple Mini.
 Includes DMA transfers on DMA1 CH2 and CH3.
 */
 #include <Adafruit_ILI9341_STM.h>
-#include <avr/pgmspace.h>
-#include <limits.h>
-#include <libmaple/dma.h>
-#include "pins_arduino.h"
-#include "wiring_private.h"
-#include <SPI.h> // Using library SPI in folder: D:\Documents\Arduino\hardware\STM32\STM32F1XX\libraries\SPI
-
-
-// Constructor when using software SPI.  All output pins are configurable.
-Adafruit_ILI9341_STM::Adafruit_ILI9341_STM(int8_t cs, int8_t dc, int8_t mosi,
-    int8_t sclk, int8_t rst, int8_t miso) : Adafruit_GFX(ILI9341_TFTWIDTH, ILI9341_TFTHEIGHT) {
-  _cs   = cs;
-  _dc   = dc;
-  _mosi  = mosi;
-  _miso = miso;
-  _sclk = sclk;
-  _rst  = rst;
-  hwSPI = false;
-}
 
 
 // Constructor when using hardware SPI.  Faster, but must use SPI pins
 // specific to each board type (e.g. 11,13 for Uno, 51,52 for Mega, etc.)
-Adafruit_ILI9341_STM::Adafruit_ILI9341_STM(int8_t cs, int8_t dc, int8_t rst) : Adafruit_GFX(ILI9341_TFTWIDTH, ILI9341_TFTHEIGHT) {
+Adafruit_ILI9341_STM::Adafruit_ILI9341_STM(int8_t cs, int8_t dc, int8_t rst) : Adafruit_GFX(ILI9341_TFTWIDTH, ILI9341_TFTHEIGHT)
+{
   _cs   = cs;
   _dc   = dc;
   _rst  = rst;
-  hwSPI = true;
-  _mosi  = _sclk = 0;
-}
-
-
-void Adafruit_ILI9341_STM::spiwrite(uint16_t c) {
-
-  //Serial.print("0x"); Serial.print(c, HEX); Serial.print(", ");
-
-  if (hwSPI)
-  {
-#if defined (__AVR__)
-    uint8_t backupSPCR = SPCR;
-    SPCR = mySPCR;
-    SPDR = c;
-    while (!(SPSR & _BV(SPIF)));
-    SPCR = backupSPCR;
-#elif defined(TEENSYDUINO)
-    SPI.transfer(c);
-#elif defined (__STM32F1__)
-    SPI.write(c);
-#elif defined (__arm__)
-    SPI.setClockDivider(11); // 8-ish MHz (full! speed!)
-    SPI.setBitOrder(MSBFIRST);
-    SPI.setDataMode(SPI_MODE0);
-    SPI.transfer(c);
-
-#endif
-  } else {
-    // Fast SPI bitbang swiped from LPD8806 library
-    for (uint8_t bit = 0x80; bit; bit >>= 1) {
-      if (c & bit) {
-        //digitalWrite(_mosi, HIGH);
-        *mosiport |=  mosipinmask;
-      } else {
-        //digitalWrite(_mosi, LOW);
-        *mosiport &= ~mosipinmask;
-      }
-      //digitalWrite(_sclk, HIGH);
-      *clkport |=  clkpinmask;
-      //digitalWrite(_sclk, LOW);
-      *clkport &= ~clkpinmask;
-    }
-  }
 }
 
 
-void Adafruit_ILI9341_STM::writecommand(uint8_t c) {
-  *dcport &=  ~dcpinmask;
-  *csport &= ~cspinmask;
-
-  spiwrite(c);
-
-  *csport |= cspinmask;
-}
-
-
-void Adafruit_ILI9341_STM::writedata(uint8_t c) {
-  *dcport |=  dcpinmask;
-  *csport &= ~cspinmask;
-
+void Adafruit_ILI9341_STM::writecommand(uint8_t c)
+{
+  dc_command();
+  cs_clear();
   spiwrite(c);
-
-  *csport |= cspinmask;
+  dc_data();
 }
 
-// If the SPI library has transaction support, these functions
-// establish settings and protect from interference from other
-// libraries.  Otherwise, they simply do nothing.
-#ifdef SPI_HAS_TRANSACTION
-static inline void spi_begin(void) __attribute__((always_inline));
-static inline void spi_begin(void) {
-#ifdef __STM32F1__
-  SPI.beginTransaction(SPISettings(36000000, MSBFIRST, SPI_MODE0));
-#else
-  SPI.beginTransaction(SPISettings(8000000, MSBFIRST, SPI_MODE0));
-#endif
-}
-static inline void spi_end(void) __attribute__((always_inline));
-static inline void spi_end(void) {
-  SPI.endTransaction();
-}
-#else
-#define spi_begin()
-#define spi_end()
-#endif
 
 // Rather than a bazillion writecommand() and writedata() calls, screen
 // initialization commands and arguments are organized in these tables
@@ -128,8 +35,8 @@ static inline void spi_end(void) {
 
 // Companion code to the above tables.  Reads and issues
 // a series of LCD commands stored in PROGMEM byte array.
-void Adafruit_ILI9341_STM::commandList(uint8_t *addr) {
-
+void Adafruit_ILI9341_STM::commandList(uint8_t *addr)
+{
   uint8_t  numCommands, numArgs;
   uint16_t ms;
 
@@ -152,54 +59,24 @@ void Adafruit_ILI9341_STM::commandList(uint8_t *addr) {
 }
 
 
-void Adafruit_ILI9341_STM::begin(void) {
-  if (_rst > 0) {
-    pinMode(_rst, OUTPUT);
-    digitalWrite(_rst, LOW);
-  }
-
+void Adafruit_ILI9341_STM::begin(SPIClass & spi, uint32_t freq)
+{
+  mSPI = spi;
+  _freq = freq;
+  _safe_freq = (freq>SAFE_FREQ) ? SAFE_FREQ : _freq;
   pinMode(_dc, OUTPUT);
   pinMode(_cs, OUTPUT);
-  csport    = portOutputRegister(digitalPinToPort(_cs));
+  csport    = portSetRegister(_cs);
   cspinmask = digitalPinToBitMask(_cs);
-  dcport    = portOutputRegister(digitalPinToPort(_dc));
+  cs_set(); // deactivate chip
+  dcport    = portSetRegister(_dc);
   dcpinmask = digitalPinToBitMask(_dc);
 
-  if (hwSPI) { // Using hardware SPI
-#if defined (__AVR__)
-    SPI.begin();
-    SPI.setClockDivider(SPI_CLOCK_DIV2); // 8 MHz (full! speed!)
-    SPI.setBitOrder(MSBFIRST);
-    SPI.setDataMode(SPI_MODE0);
-    mySPCR = SPCR;
-#elif defined(TEENSYDUINO)
-    SPI.begin();
-    SPI.setClockDivider(SPI_CLOCK_DIV2); // 8 MHz (full! speed!)
-    SPI.setBitOrder(MSBFIRST);
-    SPI.setDataMode(SPI_MODE0);
-#elif defined (__STM32F1__)
-    SPI.beginTransaction(SPISettings(36000000));
-
-#elif defined (__arm__)
-    SPI.begin();
-    SPI.setClockDivider(11); // 8-ish MHz (full! speed!)
-    SPI.setBitOrder(MSBFIRST);
-    SPI.setDataMode(SPI_MODE0);
-#endif
-  } else {
-    pinMode(_sclk, OUTPUT);
-    pinMode(_mosi, OUTPUT);
-    pinMode(_miso, INPUT);
-    clkport     = portOutputRegister(digitalPinToPort(_sclk));
-    clkpinmask  = digitalPinToBitMask(_sclk);
-    mosiport    = portOutputRegister(digitalPinToPort(_mosi));
-    mosipinmask = digitalPinToBitMask(_mosi);
-    *clkport   &= ~clkpinmask;
-    *mosiport  &= ~mosipinmask;
-  }
+  mSPI.beginTransaction(SPISettings(_safe_freq, MSBFIRST, SPI_MODE0, DATA_SIZE_8BIT));
 
   // toggle RST low to reset
   if (_rst > 0) {
+    pinMode(_rst, OUTPUT);
     digitalWrite(_rst, HIGH);
     delay(5);
     digitalWrite(_rst, LOW);
@@ -222,7 +99,6 @@ void Adafruit_ILI9341_STM::begin(void) {
   */
   //if(cmdList) commandList(cmdList);
 
-  if (hwSPI) spi_begin();
   writecommand(0xEF);
   writedata(0x03);
   writedata(0x80);
@@ -265,7 +141,7 @@ void Adafruit_ILI9341_STM::begin(void) {
   writedata(0x10);   //SAP[2:0];BT[3:0]
 
   writecommand(ILI9341_VMCTR1);    //VCM control
-  writedata(0x3e); //�Աȶȵ���
+  writedata(0x3e);
   writedata(0x28);
 
   writecommand(ILI9341_VMCTR2);    //VCM control2
@@ -327,182 +203,129 @@ void Adafruit_ILI9341_STM::begin(void) {
   writedata(0x0F);
 
   writecommand(ILI9341_SLPOUT);    //Exit Sleep
-  if (hwSPI) spi_end();
   delay(120);
-  if (hwSPI) spi_begin();
   writecommand(ILI9341_DISPON);    //Display on
-  if (hwSPI) spi_end();
-  if (hwSPI) SPI.setDataSize(SPI_CR1_DFF);
+  delay(120);
+  cs_set();
 
-}
+  _width  = ILI9341_TFTWIDTH;
+  _height = ILI9341_TFTHEIGHT;
 
+  mSPI.beginTransaction(SPISettings(_freq, MSBFIRST, SPI_MODE0, DATA_SIZE_16BIT));
 
-void Adafruit_ILI9341_STM::setAddrWindow(uint16_t x0, uint16_t y0, uint16_t x1,
-                                        uint16_t y1) {
-#if defined (__STM32F1__)  
-  writecommand(ILI9341_CASET); // Column addr set
-  *dcport |=  dcpinmask;
-  *csport &= ~cspinmask;
-  SPI.write(x0);
-  SPI.write(x1);
-  
-  writecommand(ILI9341_PASET); // Row addr set
-  *dcport |=  dcpinmask;
-  *csport &= ~cspinmask;
-  SPI.write(y0);
-  SPI.write(y1);
+}
 
-  writecommand(ILI9341_RAMWR); // write to RAM
 
-#else										
+void Adafruit_ILI9341_STM::setAddrWindow(uint16_t x0, uint16_t y0,
+                                         uint16_t x1, uint16_t y1)
+{
   writecommand(ILI9341_CASET); // Column addr set
-  writedata(x0 >> 8);
-  writedata(x0 & 0xFF);     // XSTART
-  writedata(x1 >> 8);
-  writedata(x1 & 0xFF);     // XEND
-
+  spiwrite(x0);
+  spiwrite(x1);
+  
   writecommand(ILI9341_PASET); // Row addr set
-  writedata(y0 >> 8);
-  writedata(y0);     // YSTART
-  writedata(y1 >> 8);
-  writedata(y1);     // YEND
+  spiwrite(y0);
+  spiwrite(y1);
 
   writecommand(ILI9341_RAMWR); // write to RAM
-#endif 
 }
 
 
-void Adafruit_ILI9341_STM::pushColor(uint16_t color) {
-  if (hwSPI) spi_begin();
-  //digitalWrite(_dc, HIGH);
-  *dcport |=  dcpinmask;
-  //digitalWrite(_cs, LOW);
-  *csport &= ~cspinmask;
-
-  spiwrite(color);
-
-  *csport |= cspinmask;
-  //digitalWrite(_cs, HIGH);
-  if (hwSPI) spi_end();
-}
-
 void Adafruit_ILI9341_STM::pushColors(void * colorBuffer, uint16_t nr_pixels, uint8_t async)
 {
-  *dcport |=  dcpinmask;
-  *csport &= ~cspinmask;
+  cs_clear();
 
-  if (async==0) 
-  {
-    SPI.dmaSend(colorBuffer, nr_pixels, 1);
-	*csport |= cspinmask;
-  }
-  else
-  {
-    SPI.dmaSendAsync(colorBuffer, nr_pixels, 1);
+  if (async==0) {
+    mSPI.dmaSend(colorBuffer, nr_pixels, 1);
+    cs_set();
+  } else {
+    mSPI.dmaSendAsync(colorBuffer, nr_pixels, 1);
   }
-
 }
 
-void Adafruit_ILI9341_STM::drawPixel(int16_t x, int16_t y, uint16_t color) {
+void Adafruit_ILI9341_STM::pushColor(uint16_t color)
+{
+  cs_clear();
+  spiwrite(color);
+  cs_set();
+}
 
+void Adafruit_ILI9341_STM::drawPixel(int16_t x, int16_t y, uint16_t color)
+{
   if ((x < 0) || (x >= _width) || (y < 0) || (y >= _height)) return;
 
-  if (hwSPI) spi_begin();
   setAddrWindow(x, y, x + 1, y + 1);
 
-  *dcport |=  dcpinmask;
-  *csport &= ~cspinmask;
-
   spiwrite(color);
 
-  *csport |= cspinmask;
-  if (hwSPI) spi_end();
+  cs_set();
 }
 
 
 void Adafruit_ILI9341_STM::drawFastVLine(int16_t x, int16_t y, int16_t h,
-                                        uint16_t color) {
-
+                                        uint16_t color)
+{
   // Rudimentary clipping
   if ((x >= _width) || (y >= _height || h < 1)) return;
-
   if ((y + h - 1) >= _height)
     h = _height - y;
   if (h < 2 ) {
-	drawPixel(x, y, color);
-	return;
+    drawPixel(x, y, color);
+    return;
   }
 
-  //  if (hwSPI) spi_begin();
   setAddrWindow(x, y, x, y + h - 1);
 
-  *dcport |=  dcpinmask;
-  *csport &= ~cspinmask;
-  
-#if defined (__STM32F1__)
-  lineBuffer[0] = color;
-  SPI.dmaSend(lineBuffer, h, 0);
- #else
-  uint8_t hi = color >> 8, lo = color;
-  while (h--) {
-    spiwrite(hi);
-    spiwrite(lo);
+  if (h>DMA_ON_LIMIT) {
+    lineBuffer[0] = color;
+    mSPI.dmaSend(lineBuffer, h, 0);
+  } else {
+    mSPI.write(color, h);
   }
-#endif
-  *csport |= cspinmask;
+  cs_set();
 }
 
 
 void Adafruit_ILI9341_STM::drawFastHLine(int16_t x, int16_t y, int16_t w,
-                                        uint16_t color) {
-
-  
+                                        uint16_t color)
+{
   // Rudimentary clipping
   if ((x >= _width) || (y >= _height || w < 1)) return;
   if ((x + w - 1) >= _width)  w = _width - x;
   if (w < 2 ) {
-	drawPixel(x, y, color);
-	return;
+    drawPixel(x, y, color);
+    return;
   }
 
-//  if (hwSPI) spi_begin();
   setAddrWindow(x, y, x + w - 1, y);
-  *dcport |=  dcpinmask;
-  *csport &= ~cspinmask;
 
-#if defined (__STM32F1__)
-  lineBuffer[0] = color;
-  SPI.dmaSend(lineBuffer, w, 0);
-#else
-	uint8_t hi = color >> 8, lo = color;
-    while (w--) {
-      spiwrite(hi);
-      spiwrite(lo);
-    }
-#endif
-  *csport |= cspinmask;
-  //digitalWrite(_cs, HIGH);
-//  if (hwSPI) spi_end();
+  if (w>DMA_ON_LIMIT) {
+    lineBuffer[0] = color;
+    mSPI.dmaSend(lineBuffer, w, 0);
+  } else {
+    mSPI.write(color, w);
+  }
+  cs_set();
 }
 
-void Adafruit_ILI9341_STM::fillScreen(uint16_t color) {
-#if defined (__STM32F1__)
-  setAddrWindow(0, 0, _width - 1, _height - 1);
-  *dcport |=  dcpinmask;
-  *csport &= ~cspinmask;
+void Adafruit_ILI9341_STM::fillScreen(uint16_t color)
+{
   lineBuffer[0] = color;
-  SPI.dmaSend(lineBuffer, (65535), 0);
-  SPI.dmaSend(lineBuffer, ((_width * _height) - 65535), 0);
-
-#else
-  fillRect(0, 0,  _width, _height, color);
-#endif 
+  setAddrWindow(0, 0, _width - 1, _height - 1);
+  uint32_t nr_bytes = _width * _height;
+  while ( nr_bytes>65535 ) {
+    nr_bytes -= 65535;
+    mSPI.dmaSend(lineBuffer, (65535), 0);
+  }
+  mSPI.dmaSend(lineBuffer, nr_bytes, 0);
+  cs_set();
 }
 
 // fill a rectangle
 void Adafruit_ILI9341_STM::fillRect(int16_t x, int16_t y, int16_t w, int16_t h,
-                                   uint16_t color) {
-
+                                   uint16_t color)
+{
+  lineBuffer[0] = color;
   // rudimentary clipping (drawChar w/big text requires this)
   if ((x >= _width) || (y >= _height || h < 1 || w < 1)) return;
   if ((x + w - 1) >= _width)  w = _width  - x;
@@ -511,41 +334,26 @@ void Adafruit_ILI9341_STM::fillRect(int16_t x, int16_t y, int16_t w, int16_t h,
     drawPixel(x, y, color);
     return;
   }
-  
-  if (hwSPI) spi_begin();
-  setAddrWindow(x, y, x + w - 1, y + h - 1);
 
-  *dcport |=  dcpinmask;
-  *csport &= ~cspinmask;
-#if defined (__STM32F1__)
-  lineBuffer[0] = color;
-  if (w*h <= 65535) {
-  SPI.dmaSend(lineBuffer, (w*h), 0);
-  }
-  else {
-  SPI.dmaSend(lineBuffer, (65535), 0);
-  SPI.dmaSend(lineBuffer, ((w*h) - 65535), 0);
-  }
-#else
-  uint8_t hi = color >> 8, lo = color;
-  for(y=h; y>0; y--) 
-  {
-    for(x=w; x>0; x--)
-	{
-      SPI.write(hi);
-      SPI.write(lo);
+  setAddrWindow(x, y, x + w - 1, y + h - 1);
+  uint32_t nr_bytes = w * h;
+  if ( nr_bytes>DMA_ON_LIMIT ) {
+    while ( nr_bytes>65535 ) {
+      nr_bytes -= 65535;
+      mSPI.dmaSend(lineBuffer, (65535), 0);
     }
+    mSPI.dmaSend(lineBuffer, nr_bytes, 0);
+  } else {
+    mSPI.write(color, nr_bytes);
   }
-#endif
-  *csport |= cspinmask;
-  if (hwSPI) spi_end();
+  cs_set();
 }
 
 /*
 * Draw lines faster by calculating straight sections and drawing them with fastVline and fastHline.
 */
-#if defined (__STM32F1__)
-void Adafruit_ILI9341_STM::drawLine(int16_t x0, int16_t y0,int16_t x1, int16_t y1, uint16_t color)
+void Adafruit_ILI9341_STM::drawLine(int16_t x0, int16_t y0,
+                                    int16_t x1, int16_t y1, uint16_t color)
 {
 	if ((y0 < 0 && y1 <0) || (y0 > _height && y1 > _height)) return;
 	if ((x0 < 0 && x1 <0) || (x0 > _width && x1 > _width)) return;
@@ -601,8 +409,6 @@ void Adafruit_ILI9341_STM::drawLine(int16_t x0, int16_t y0,int16_t x1, int16_t y
 	}
 
 	int16_t xbegin = x0;
-	lineBuffer[0] = color;
-	*csport &= ~cspinmask;
 	if (steep) {
 		for (; x0 <= x1; x0++) {
 			err -= dy;
@@ -650,11 +456,7 @@ void Adafruit_ILI9341_STM::drawLine(int16_t x0, int16_t y0,int16_t x1, int16_t y
 			drawFastHLine(xbegin, y0, x0 - xbegin, color);
 		}
 	}
-	*csport |= cspinmask;
 }
-#endif
-
-
 
 // Pass 8-bit (each) R,G,B, get back 16-bit packed color
 uint16_t Adafruit_ILI9341_STM::color565(uint8_t r, uint8_t g, uint8_t b) {
@@ -670,118 +472,133 @@ uint16_t Adafruit_ILI9341_STM::color565(uint8_t r, uint8_t g, uint8_t b) {
 #define MADCTL_BGR 0x08
 #define MADCTL_MH  0x04
 
-void Adafruit_ILI9341_STM::setRotation(uint8_t m) {
-
-  if (hwSPI) spi_begin();
-  if (hwSPI) SPI.setDataSize(0);
-  writecommand(ILI9341_MADCTL);
+void Adafruit_ILI9341_STM::setRotation(uint8_t m)
+{
   rotation = m % 4; // can't be higher than 3
   switch (rotation) {
     case 0:
-      writedata(MADCTL_MX | MADCTL_BGR);
+      m = (MADCTL_MX | MADCTL_BGR);
       _width  = ILI9341_TFTWIDTH;
       _height = ILI9341_TFTHEIGHT;
       break;
     case 1:
-      writedata(MADCTL_MV | MADCTL_BGR);
+      m = (MADCTL_MV | MADCTL_BGR);
       _width  = ILI9341_TFTHEIGHT;
       _height = ILI9341_TFTWIDTH;
       break;
     case 2:
-      writedata(MADCTL_MY | MADCTL_BGR);
+      m = (MADCTL_MY | MADCTL_BGR);
       _width  = ILI9341_TFTWIDTH;
       _height = ILI9341_TFTHEIGHT;
       break;
     case 3:
-      writedata(MADCTL_MX | MADCTL_MY | MADCTL_MV | MADCTL_BGR);
+      m = (MADCTL_MX | MADCTL_MY | MADCTL_MV | MADCTL_BGR);
       _width  = ILI9341_TFTHEIGHT;
       _height = ILI9341_TFTWIDTH;
       break;
   }
-  if (hwSPI) SPI.setDataSize(SPI_CR1_DFF);
-  if (hwSPI) spi_end();
+  mSPI.setDataSize(DATA_SIZE_8BIT);
+  writecommand(ILI9341_MADCTL);
+  writedata(m);
+  cs_set();
+  mSPI.setDataSize(DATA_SIZE_16BIT);
 }
 
 
-void Adafruit_ILI9341_STM::invertDisplay(boolean i) {
-  if (hwSPI) spi_begin();
+void Adafruit_ILI9341_STM::invertDisplay(boolean i)
+{
   writecommand(i ? ILI9341_INVON : ILI9341_INVOFF);
-  if (hwSPI) spi_end();
+  cs_set();
 }
 
 
-////////// stuff not actively being used, but kept for posterity
-
-
-uint8_t Adafruit_ILI9341_STM::spiread(void) {
-  uint8_t r = 0;
-
-  if (hwSPI) {
-#if defined (__AVR__)
-    uint8_t backupSPCR = SPCR;
-    SPCR = mySPCR;
-    SPDR = 0x00;
-    while (!(SPSR & _BV(SPIF)));
-    r = SPDR;
-    SPCR = backupSPCR;
-#elif defined(TEENSYDUINO)
-    r = SPI.transfer(0x00);
-#elif defined (__STM32F1__)
-    r = SPI.transfer(0x00);
-#elif defined (__arm__)
-    SPI.setClockDivider(11); // 8-ish MHz (full! speed!)
-    SPI.setBitOrder(MSBFIRST);
-    SPI.setDataMode(SPI_MODE0);
-    r = SPI.transfer(0x00);
-#endif
-  } else {
+uint16_t Adafruit_ILI9341_STM::readPixel(int16_t x, int16_t y)
+{
+  mSPI.beginTransaction(SPISettings(_safe_freq, MSBFIRST, SPI_MODE0, DATA_SIZE_8BIT));
 
-    for (uint8_t i = 0; i < 8; i++) {
-      digitalWrite(_sclk, LOW);
-      digitalWrite(_sclk, HIGH);
-      r <<= 1;
-      if (digitalRead(_miso))
-        r |= 0x1;
-    }
-  }
-  //Serial.print("read: 0x"); Serial.print(r, HEX);
+  writecommand(ILI9341_CASET); // Column addr set
+  spiwrite16(x);
+  spiwrite16(x);
+  writecommand(ILI9341_PASET); // Row addr set
+  spiwrite16(y);
+  spiwrite16(y);
+  writecommand(ILI9341_RAMRD); // read GRAM
+  (void)spiread();             //dummy read
+  uint8_t r = spiread();
+  uint8_t g = spiread();
+  uint8_t b = spiread();
+  cs_set();
 
-  return r;
+  mSPI.beginTransaction(SPISettings(_freq, MSBFIRST, SPI_MODE0, DATA_SIZE_16BIT));
+
+  return color565(r, g, b);
 }
 
-uint8_t Adafruit_ILI9341_STM::readdata(void) {
-  digitalWrite(_dc, HIGH);
-  digitalWrite(_cs, LOW);
-  uint8_t r = spiread();
-  digitalWrite(_cs, HIGH);
+uint16_t Adafruit_ILI9341_STM::readPixels(int16_t x1, int16_t y1, int16_t x2, int16_t y2, uint16_t *buf)
+{
+  mSPI.beginTransaction(SPISettings(_safe_freq, MSBFIRST, SPI_MODE0, DATA_SIZE_8BIT));
 
-  return r;
+  writecommand(ILI9341_CASET); // Column addr set
+  spiwrite16(x1);
+  spiwrite16(x2);
+  writecommand(ILI9341_PASET); // Row addr set
+  spiwrite16(y1);
+  spiwrite16(y2);
+  writecommand(ILI9341_RAMRD); // read GRAM
+  (void)spiread();             //dummy read
+  uint8_t r, g, b;
+  uint16_t len = (x2-x1+1)*(y2-y1+1);
+  uint16_t ret = len;
+  while (len--) {
+    r = spiread();
+    g = spiread();
+    b = spiread();
+    *buf++ = color565(r, g, b);
+  }
+  cs_set();
+
+  mSPI.beginTransaction(SPISettings(_freq, MSBFIRST, SPI_MODE0, DATA_SIZE_16BIT));
+  return ret;
 }
 
 
-uint8_t Adafruit_ILI9341_STM::readcommand8(uint8_t c, uint8_t index) {
-  if (hwSPI) spi_begin();
-  digitalWrite(_dc, LOW); // command
-  digitalWrite(_cs, LOW);
-  spiwrite(0xD9);  // woo sekret command?
-  digitalWrite(_dc, HIGH); // data
-  spiwrite(0x10 + index);
-  digitalWrite(_cs, HIGH);
+uint16_t Adafruit_ILI9341_STM::readPixelsRGB24(int16_t x1, int16_t y1, int16_t x2, int16_t y2, uint8_t *buf)
+{
+  mSPI.beginTransaction(SPISettings(_safe_freq, MSBFIRST, SPI_MODE0, DATA_SIZE_8BIT));
 
-  digitalWrite(_dc, LOW);
-  //if(hwSPI) digitalWrite(_sclk, LOW);
-  digitalWrite(_cs, LOW);
-  spiwrite(c);
+  writecommand(ILI9341_CASET); // Column addr set
+  spiwrite16(x1);
+  spiwrite16(x2);
+  writecommand(ILI9341_PASET); // Row addr set
+  spiwrite16(y1);
+  spiwrite16(y2);
+  writecommand(ILI9341_RAMRD); // read GRAM
+  (void)spiread();             //dummy read
+  uint8_t r, g, b;
+  uint16_t len = (x2-x1+1)*(y2-y1+1);
+  uint16_t ret = len;
+
+  mSPI.dmaTransfer(buf, buf, len*3);
+  cs_set();
+
+  mSPI.beginTransaction(SPISettings(_freq, MSBFIRST, SPI_MODE0, DATA_SIZE_16BIT));
+  return ret;
+}
 
-  digitalWrite(_dc, HIGH);
+uint8_t Adafruit_ILI9341_STM::readcommand8(uint8_t c, uint8_t index)
+{
+  // the SPI clock must be set lower
+  mSPI.beginTransaction(SPISettings(_safe_freq, MSBFIRST, SPI_MODE0, DATA_SIZE_8BIT));
+
+  writecommand(c);
   uint8_t r = spiread();
-  digitalWrite(_cs, HIGH);
-  if (hwSPI) spi_end();
+  cs_set();
+
+  mSPI.beginTransaction(SPISettings(_freq, MSBFIRST, SPI_MODE0, DATA_SIZE_16BIT));
   return r;
 }
 
 
-
 /*
 
  uint16_t Adafruit_ILI9341_STM::readcommand16(uint8_t c) {
diff --git a/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.h b/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.h
index 7ee395c6c..b77b3562f 100644
--- a/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.h
+++ b/STM32F1/libraries/Adafruit_ILI9341_STM/Adafruit_ILI9341_STM.h
@@ -7,9 +7,8 @@ This library has been modified for the Maple Mini
 #define _ADAFRUIT_ILI9341H_
 
 #include "Arduino.h"
-#include "Print.h"
 #include <Adafruit_GFX_AS.h>
-#include <avr/pgmspace.h>
+#include <SPI.h>
 
 #ifndef swap
   #define swap(a, b) { int16_t t = a; a = b; b = t; }
@@ -100,18 +99,15 @@ class Adafruit_ILI9341_STM : public Adafruit_GFX {
 
  public:
 
-  Adafruit_ILI9341_STM(int8_t _CS, int8_t _DC, int8_t _MOSI, int8_t _SCLK,
-		   int8_t _RST, int8_t _MISO);
   Adafruit_ILI9341_STM(int8_t _CS, int8_t _DC, int8_t _RST = -1);
-  
-  void     begin(void),
-           setAddrWindow(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1),
+
+  void     begin(SPIClass & spi, uint32_t freq=48000000);
+  void     begin(void) { begin(SPI); }
+  void     setAddrWindow(uint16_t x0, uint16_t y0, uint16_t x1, uint16_t y1),
            pushColor(uint16_t color),
-		   pushColors(void * colorBuffer, uint16_t nr_pixels, uint8_t async),
+           pushColors(void * colorBuffer, uint16_t nr_pixels, uint8_t async=0),
            fillScreen(uint16_t color),
-		   #if defined (__STM32F1__)
 		   drawLine(int16_t x0, int16_t y0,int16_t x1, int16_t y1, uint16_t color),
-		   #endif
            drawPixel(int16_t x, int16_t y, uint16_t color),
            drawFastVLine(int16_t x, int16_t y, int16_t h, uint16_t color),
            drawFastHLine(int16_t x, int16_t y, int16_t w, uint16_t color),
@@ -122,43 +118,49 @@ class Adafruit_ILI9341_STM : public Adafruit_GFX {
   uint16_t color565(uint8_t r, uint8_t g, uint8_t b);
 
   /* These are not for current use, 8-bit protocol only! */
-  uint8_t  readdata(void),
-    readcommand8(uint8_t reg, uint8_t index = 0);
+  uint16_t readPixel(int16_t x, int16_t y);
+  uint16_t readPixels(int16_t x1, int16_t y1, int16_t x2, int16_t y2, uint16_t *buf);
+  uint16_t readPixelsRGB24(int16_t x1, int16_t y1, int16_t x2, int16_t y2, uint8_t *buf);
+
+  uint8_t  readcommand8(uint8_t reg, uint8_t index = 0);
   /*
   uint16_t readcommand16(uint8_t);
   uint32_t readcommand32(uint8_t);
-  void     dummyclock(void);
-  */  
+  */
+
+#define DMA_ON_LIMIT 250 // do DMA only for more data than this
+#define SAFE_FREQ  24000000ul // 24MHz for reading
+
+#define writePixel drawPixel
 
-  void     spiwrite(uint16_t),
-    writecommand(uint8_t c),
-    writedata(uint8_t d),
-    commandList(uint8_t *addr);
-  uint8_t  spiread(void);
+#define dc_command() ( *dcport  =(uint32_t)dcpinmask<<16 ) // 0
+#define dc_data()    ( *dcport  =(uint32_t)dcpinmask )     // 1
+#define cs_clear()   ( *csport  =(uint32_t)cspinmask<<16 )
+#define cs_set()     ( *csport  =(uint32_t)cspinmask )
+#define clk_clear()  ( *clkport =(uint32_t)clkpinmask<<16 )
+#define clk_set()    ( *clkport =(uint32_t)clkpinmask )
+#define mosi_clear() ( *mosiport=(uint32_t)misopinmask<<16 )
+#define mosi_set()   ( *mosiport=(uint32_t)misopinmask )
+#define miso_in()    ( (*misoport)&misopinmask )
 
+  inline uint8_t spiread(void)  { return mSPI.transfer(0x00); }
+  inline uint8_t readdata(void) { return mSPI.transfer(0x00); }
+  inline void    writedata(uint8_t c)   { mSPI.write(c); }
+  inline void    spiwrite(uint16_t c)   { mSPI.write(c); }
+  inline void    spiwrite16(uint16_t c) { mSPI.write16(c); } // 8 bit mode
+
+  void  writecommand(uint8_t c),
+        commandList(uint8_t *addr);
 
  private:
-  uint8_t  tabcolor;
-
-
-
-
-  boolean  hwSPI;
-#if defined (__AVR__) || defined(TEENSYDUINO)
-  uint8_t mySPCR;
-  volatile uint8_t *mosiport, *clkport, *dcport, *rsport, *csport;
-  int8_t  _cs, _dc, _rst, _mosi, _miso, _sclk;
-  uint8_t  mosipinmask, clkpinmask, cspinmask, dcpinmask;
-#elif defined (__STM32F1__)
-    volatile uint32 *mosiport, *clkport, *dcport, *rsport, *csport;
-    uint32_t  _cs, _dc, _rst, _mosi, _miso, _sclk;
-    uint32_t  mosipinmask, clkpinmask, cspinmask, dcpinmask;
-	uint16_t lineBuffer[ILI9341_TFTHEIGHT]; // DMA buffer. 16bit color data per pixel
-#elif defined (__arm__)
-    volatile RwReg *mosiport, *clkport, *dcport, *rsport, *csport;
-    uint32_t  _cs, _dc, _rst, _mosi, _miso, _sclk;
-    uint32_t  mosipinmask, clkpinmask, cspinmask, dcpinmask;
-#endif
+  uint32_t _freq, _safe_freq;
+  SPIClass & mSPI = SPI;
+
+  volatile uint32_t *csport, *dcport;
+  int8_t  _cs, _dc, _rst;
+  uint16_t  cspinmask, dcpinmask;
+  uint16_t lineBuffer[ILI9341_TFTHEIGHT]; // DMA buffer. 16bit color data per pixel
 };
 
+
 #endif

From a89d0b935b6f177ef1eb52e17b3e8c670c5168cc Mon Sep 17 00:00:00 2001
From: csnol <csnol@126.com>
Date: Wed, 18 Oct 2017 21:42:31 +0800
Subject: [PATCH 213/307] Half-hour TimeZone supported

---
 STM32F1/libraries/RTClock/src/RTClock.cpp | 16 ++++++++++++++++
 STM32F1/libraries/RTClock/src/RTClock.h   |  9 ++++++++-
 2 files changed, 24 insertions(+), 1 deletion(-)
 mode change 100644 => 100755 STM32F1/libraries/RTClock/src/RTClock.cpp
 mode change 100644 => 100755 STM32F1/libraries/RTClock/src/RTClock.h

diff --git a/STM32F1/libraries/RTClock/src/RTClock.cpp b/STM32F1/libraries/RTClock/src/RTClock.cpp
old mode 100644
new mode 100755
index e95bead86..0bfe7dfbd
--- a/STM32F1/libraries/RTClock/src/RTClock.cpp
+++ b/STM32F1/libraries/RTClock/src/RTClock.cpp
@@ -79,6 +79,22 @@
 	//to implement
 	}
 */	
+
+	// Usage:  1.  localtime = TimeZone(UnixTime, 9, 1)  means SAT +09:30 TimeZone; 
+    //         2.  localtime = TimeZone(UnixTime, -3, 1)  means NST,NFT -03:30 TimeZone;
+    //         3.  TimeZone(UnixTime, 8, 0)  same function as TimeZone(UnixTime, 8)  -> CCT +08:00
+    
+	time_t RTClock::TimeZone(time_t t, int TZ, bool HFZ)  {    // HFZ : Half-hour TimeZone flag
+	if(HFZ) {
+	if(TZ > 0 )
+ 	return ( t + (TZ * SECS_PER_HOUR) + 1800); 
+	else
+ 	return ( t + (TZ * SECS_PER_HOUR) - 1800); 
+	}
+	else
+	return ( t + (TZ * SECS_PER_HOUR));
+	}
+// 
 	
 	void RTClock::setTime (tm_t & tmm) {
 		time_t mktm = makeTime(tmm); // time will be make to mktm
diff --git a/STM32F1/libraries/RTClock/src/RTClock.h b/STM32F1/libraries/RTClock/src/RTClock.h
old mode 100644
new mode 100755
index 4d8399e80..d6b3090d2
--- a/STM32F1/libraries/RTClock/src/RTClock.h
+++ b/STM32F1/libraries/RTClock/src/RTClock.h
@@ -15,6 +15,7 @@
 #define SECS_PER_YEAR (SECS_PER_WEEK * 52UL)
 #define SECS_YR_2000  (946684800UL) // the time at the start of y2k
 #define LEAP_YEAR(Y)  ( ((1970+Y)>0) && !((1970+Y)%4) && ( ((1970+Y)%100) || !((1970+Y)%400) ) )
+#define HALFTZ 0
 
 #if !defined(__time_t_defined) // avoid conflict with newlib or other posix libc
   #warning "Using private time_t definintion"
@@ -71,8 +72,14 @@ class RTClock {
 	uint8_t minute(time_t t)  { breakTime(t, tmm); return tmm.minute; }
 	uint8_t second(time_t t)  { breakTime(t, tmm); return tmm.second; }
 	uint8_t isPM(time_t t)    { return (hour(t)>=12); }
+
+	// Usage: localtime = TimeZone(UnixTime, 8); 
+	time_t TimeZone(time_t t, int TZ) { return ( t + (TZ * SECS_PER_HOUR)); } 
 	
-	time_t TimeZone(time_t t, int TZ)  { return ( t + (TZ * SECS_PER_HOUR)); }    // usage: localtime = TimeZone(UnixTime, 8); // Beijing timezone = 8  
+	// Usage:  1.  localtime = TimeZone(UnixTime, 9, 1)  means SAT +09:30 TimeZone; 
+    //         2.  localtime = TimeZone(UnixTime, -3, 1)  means NST,NFT -03:30 TimeZone;
+    //         3.  TimeZone(UnixTime, 8, 0)  same function as TimeZone(UnixTime, 8)  -> CCT +08:00
+	time_t TimeZone(time_t t, int TZ, bool HFZ);   // HFZ : Half-hour TimeZone flag
 	
 	void createAlarm(voidFuncPtr function, time_t alarm_time_t); 
 	void createAlarm(voidFuncPtr function, struct tm_t & alarm_tm);

From 9f5cdd2d24bf4c0d24f99963221cee5a8fe38f42 Mon Sep 17 00:00:00 2001
From: csnol <csnol@126.com>
Date: Wed, 18 Oct 2017 21:45:19 +0800
Subject: [PATCH 214/307] updated

---
 STM32F1/libraries/RTClock/src/RTClock.h | 1 -
 1 file changed, 1 deletion(-)

diff --git a/STM32F1/libraries/RTClock/src/RTClock.h b/STM32F1/libraries/RTClock/src/RTClock.h
index d6b3090d2..c0954ea0f 100755
--- a/STM32F1/libraries/RTClock/src/RTClock.h
+++ b/STM32F1/libraries/RTClock/src/RTClock.h
@@ -15,7 +15,6 @@
 #define SECS_PER_YEAR (SECS_PER_WEEK * 52UL)
 #define SECS_YR_2000  (946684800UL) // the time at the start of y2k
 #define LEAP_YEAR(Y)  ( ((1970+Y)>0) && !((1970+Y)%4) && ( ((1970+Y)%100) || !((1970+Y)%400) ) )
-#define HALFTZ 0
 
 #if !defined(__time_t_defined) // avoid conflict with newlib or other posix libc
   #warning "Using private time_t definintion"

From 80ae49dd5037315e652eec43d04c25dc57c91364 Mon Sep 17 00:00:00 2001
From: Michel Stempin <michel.stempin@wanadoo.fr>
Date: Wed, 18 Oct 2017 22:04:54 +0200
Subject: [PATCH 215/307] Added missing SDIO pins for F103V and F103Z

---
 STM32F1/variants/generic_stm32f103v/board/board.h | 10 ++++++++++
 STM32F1/variants/generic_stm32f103z/board/board.h | 10 ++++++++++
 2 files changed, 20 insertions(+)

diff --git a/STM32F1/variants/generic_stm32f103v/board/board.h b/STM32F1/variants/generic_stm32f103v/board/board.h
index 92f2bf8a1..3bb680a78 100644
--- a/STM32F1/variants/generic_stm32f103v/board/board.h
+++ b/STM32F1/variants/generic_stm32f103v/board/board.h
@@ -109,6 +109,16 @@
 #define BOARD_USB_DISC_DEV      GPIOC
 #define BOARD_USB_DISC_BIT      12
 
+/*
+ * SDIO Pins
+ */
+#define BOARD_SDIO_D0 			PC8
+#define BOARD_SDIO_D1 			PC9
+#define BOARD_SDIO_D2 			PC10
+#define BOARD_SDIO_D3 			PC11
+#define BOARD_SDIO_CLK 			PC12
+#define BOARD_SDIO_CMD 			PD2
+
 /* Pin aliases: these give the GPIO port/bit for each pin as an
  * enum. These are optional, but recommended. They make it easier to
  * write code using low-level GPIO functionality. */
diff --git a/STM32F1/variants/generic_stm32f103z/board/board.h b/STM32F1/variants/generic_stm32f103z/board/board.h
index c9bf4b5e8..fe4856796 100644
--- a/STM32F1/variants/generic_stm32f103z/board/board.h
+++ b/STM32F1/variants/generic_stm32f103z/board/board.h
@@ -102,6 +102,16 @@
 #define BOARD_USB_DISC_DEV      GPIOC
 #define BOARD_USB_DISC_BIT      12
 
+/*
+ * SDIO Pins
+ */
+#define BOARD_SDIO_D0 			PC8
+#define BOARD_SDIO_D1 			PC9
+#define BOARD_SDIO_D2 			PC10
+#define BOARD_SDIO_D3 			PC11
+#define BOARD_SDIO_CLK 			PC12
+#define BOARD_SDIO_CMD 			PD2
+
 /* Pin aliases: these give the GPIO port/bit for each pin as an
  * enum. These are optional, but recommended. They make it easier to
  * write code using low-level GPIO functionality. */

From c741afa74a87c17dafe49f1de3bb3d7f2f17b08d Mon Sep 17 00:00:00 2001
From: csnol <csnol@126.com>
Date: Thu, 19 Oct 2017 17:23:48 +0800
Subject: [PATCH 216/307] Update TimeZone function

Add  TimeZone(UnixTime, HourOffset, MinuteOffset)
---
 STM32F1/libraries/RTClock/src/RTClock.cpp | 15 ---------------
 STM32F1/libraries/RTClock/src/RTClock.h   |  6 ++----
 2 files changed, 2 insertions(+), 19 deletions(-)

diff --git a/STM32F1/libraries/RTClock/src/RTClock.cpp b/STM32F1/libraries/RTClock/src/RTClock.cpp
index 0bfe7dfbd..5f0467f62 100755
--- a/STM32F1/libraries/RTClock/src/RTClock.cpp
+++ b/STM32F1/libraries/RTClock/src/RTClock.cpp
@@ -80,21 +80,6 @@
 	}
 */	
 
-	// Usage:  1.  localtime = TimeZone(UnixTime, 9, 1)  means SAT +09:30 TimeZone; 
-    //         2.  localtime = TimeZone(UnixTime, -3, 1)  means NST,NFT -03:30 TimeZone;
-    //         3.  TimeZone(UnixTime, 8, 0)  same function as TimeZone(UnixTime, 8)  -> CCT +08:00
-    
-	time_t RTClock::TimeZone(time_t t, int TZ, bool HFZ)  {    // HFZ : Half-hour TimeZone flag
-	if(HFZ) {
-	if(TZ > 0 )
- 	return ( t + (TZ * SECS_PER_HOUR) + 1800); 
-	else
- 	return ( t + (TZ * SECS_PER_HOUR) - 1800); 
-	}
-	else
-	return ( t + (TZ * SECS_PER_HOUR));
-	}
-// 
 	
 	void RTClock::setTime (tm_t & tmm) {
 		time_t mktm = makeTime(tmm); // time will be make to mktm
diff --git a/STM32F1/libraries/RTClock/src/RTClock.h b/STM32F1/libraries/RTClock/src/RTClock.h
index c0954ea0f..60b6fbcba 100755
--- a/STM32F1/libraries/RTClock/src/RTClock.h
+++ b/STM32F1/libraries/RTClock/src/RTClock.h
@@ -75,10 +75,8 @@ class RTClock {
 	// Usage: localtime = TimeZone(UnixTime, 8); 
 	time_t TimeZone(time_t t, int TZ) { return ( t + (TZ * SECS_PER_HOUR)); } 
 	
-	// Usage:  1.  localtime = TimeZone(UnixTime, 9, 1)  means SAT +09:30 TimeZone; 
-    //         2.  localtime = TimeZone(UnixTime, -3, 1)  means NST,NFT -03:30 TimeZone;
-    //         3.  TimeZone(UnixTime, 8, 0)  same function as TimeZone(UnixTime, 8)  -> CCT +08:00
-	time_t TimeZone(time_t t, int TZ, bool HFZ);   // HFZ : Half-hour TimeZone flag
+	// Usage:  1.  localtime = TimeZone(UnixTime, 9, 45)  ->   UTC +09:45 TimeZone; 
+	time_t TimeZone(time_t t, int HTZ, int MTZ)  { return ( t + (HTZ * SECS_PER_HOUR) + (MTZ * 60); }    // HTZ = Hour offset, MTZ = Minute offset
 	
 	void createAlarm(voidFuncPtr function, time_t alarm_time_t); 
 	void createAlarm(voidFuncPtr function, struct tm_t & alarm_tm);

From 4870e27855ade718158ee61d572c9d35072ef4db Mon Sep 17 00:00:00 2001
From: csnol <csnol@126.com>
Date: Thu, 19 Oct 2017 17:26:42 +0800
Subject: [PATCH 217/307] Update

---
 STM32F1/libraries/RTClock/src/RTClock.cpp | 1 -
 1 file changed, 1 deletion(-)

diff --git a/STM32F1/libraries/RTClock/src/RTClock.cpp b/STM32F1/libraries/RTClock/src/RTClock.cpp
index 5f0467f62..e95bead86 100755
--- a/STM32F1/libraries/RTClock/src/RTClock.cpp
+++ b/STM32F1/libraries/RTClock/src/RTClock.cpp
@@ -79,7 +79,6 @@
 	//to implement
 	}
 */	
-
 	
 	void RTClock::setTime (tm_t & tmm) {
 		time_t mktm = makeTime(tmm); // time will be make to mktm

From 588f9db6976f3f1f5b332955484e4fc22123b71d Mon Sep 17 00:00:00 2001
From: csnol <csnol@126.com>
Date: Thu, 19 Oct 2017 18:31:23 +0800
Subject: [PATCH 218/307] update

---
 STM32F1/libraries/RTClock/src/RTClock.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/libraries/RTClock/src/RTClock.h b/STM32F1/libraries/RTClock/src/RTClock.h
index 60b6fbcba..71015a586 100755
--- a/STM32F1/libraries/RTClock/src/RTClock.h
+++ b/STM32F1/libraries/RTClock/src/RTClock.h
@@ -76,7 +76,7 @@ class RTClock {
 	time_t TimeZone(time_t t, int TZ) { return ( t + (TZ * SECS_PER_HOUR)); } 
 	
 	// Usage:  1.  localtime = TimeZone(UnixTime, 9, 45)  ->   UTC +09:45 TimeZone; 
-	time_t TimeZone(time_t t, int HTZ, int MTZ)  { return ( t + (HTZ * SECS_PER_HOUR) + (MTZ * 60); }    // HTZ = Hour offset, MTZ = Minute offset
+	time_t TimeZone(time_t t, int HTZ, int MTZ)  { return ( t + (HTZ * SECS_PER_HOUR) + (MTZ * 60)); }    // HTZ = Hour offset, MTZ = Minute offset
 	
 	void createAlarm(voidFuncPtr function, time_t alarm_time_t); 
 	void createAlarm(voidFuncPtr function, struct tm_t & alarm_tm);

From 4a3e23949b3efde74bf786cf91f78cb6315fed04 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Tue, 31 Oct 2017 20:05:31 +1100
Subject: [PATCH 219/307] Added DMA enable and disable functions to hardware
 timers, thanks to @stevstrong

---
 STM32F1/cores/maple/HardwareTimer.cpp | 9 +++++++++
 STM32F1/cores/maple/HardwareTimer.h   | 6 ++++++
 2 files changed, 15 insertions(+)

diff --git a/STM32F1/cores/maple/HardwareTimer.cpp b/STM32F1/cores/maple/HardwareTimer.cpp
index ecd1b11cf..abf1e623f 100644
--- a/STM32F1/cores/maple/HardwareTimer.cpp
+++ b/STM32F1/cores/maple/HardwareTimer.cpp
@@ -138,6 +138,15 @@ void HardwareTimer::detachInterrupt(int channel) {
     timer_detach_interrupt(this->dev, (uint8)channel);
 }
 
+
+void HardwareTimer::enableDMA(int channel) {
+    timer_dma_enable_req(this->dev, (uint8)channel);
+}
+
+void HardwareTimer::disableDMA(int channel) {
+    timer_dma_disable_req(this->dev, (uint8)channel);
+}
+
 void HardwareTimer::refresh(void) {
     timer_generate_update(this->dev);
 }
diff --git a/STM32F1/cores/maple/HardwareTimer.h b/STM32F1/cores/maple/HardwareTimer.h
index 75601d0cb..d5356ca21 100644
--- a/STM32F1/cores/maple/HardwareTimer.h
+++ b/STM32F1/cores/maple/HardwareTimer.h
@@ -245,6 +245,12 @@ class HardwareTimer {
 
     /* Escape hatch */
 
+	 /**
+     * @brief Enable/disable DMA request for the input channel.
+     */
+	void enableDMA(int channel);
+	void disableDMA(int channel);
+	
     /**
      * @brief Get a pointer to the underlying libmaple timer_dev for
      *        this HardwareTimer instance.

From e14c83fe8d39d7012075f8a98c72a2b0a335c4e8 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Wed, 1 Nov 2017 15:24:04 +0100
Subject: [PATCH 220/307] Update tone.cpp

- make tone() blocking for the input duration time
---
 STM32F1/cores/maple/tone.cpp | 7 ++++---
 1 file changed, 4 insertions(+), 3 deletions(-)

diff --git a/STM32F1/cores/maple/tone.cpp b/STM32F1/cores/maple/tone.cpp
index 965bfddc9..45cfa0eec 100644
--- a/STM32F1/cores/maple/tone.cpp
+++ b/STM32F1/cores/maple/tone.cpp
@@ -60,7 +60,7 @@ uint8_t tone_ntimer = TONE_TIMER;               // timer used to generate freque
 bool tone_state = true;             // last pin state for toggling
 short tone_pin = -1;                // pin for outputting sound
 short tone_freq = 444;              // tone frequency (0=pause)
-uint32_t tone_nhw = 0;              // tone duration in number of half waves
+volatile uint32_t tone_nhw = 0;              // tone duration in number of half waves
 uint16_t tone_tcount = 0;           // time between handler calls in 1/36 usec
 uint16_t tone_ncount = 0;           // handler call between toggling
 uint16_t tone_n = 0;                // remaining handler calls before toggling
@@ -146,12 +146,12 @@ void tone(uint32_t pin, uint32_t freq, uint32_t duration) {
 
    tone_timer->pause();
 
-   if(freq > 0 && duration >0 ){
+   if(freq > 0){
       uint32_t count = (F_CPU/4)/freq;       // timer counts per half wave
       tone_ncount = tone_n = (count>>16)+1; // number of 16-bit count chunk
       tone_tcount = count/tone_ncount;      // size of count chunk
       if(duration > 0) // number of half waves to be generated
-         tone_nhw = ((duration*(freq>0?freq:100))/1000)<<1;
+         tone_nhw = ((duration*freq)/1000)<<1;
       else  // no duration specified, continuous sound until noTone() called
          tone_nhw = 0;
 
@@ -186,6 +186,7 @@ void tone(uint32_t pin, uint32_t freq, uint32_t duration) {
       pinMode(tone_pin, INPUT);
 
    }
+   while(tone_nhw) ; // blocks till duration elapsed
 }
 
 ////////////////////////////////////////////////////////////////////////////////

From 2c33a0237134df4d5337fca38c17b9d1d74a4b8a Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Thu, 2 Nov 2017 17:50:34 +1100
Subject: [PATCH 221/307] Correct argument type bug in utoa (itoa.c itoa.h) See
 PR #271

---
 STM32F1/cores/maple/itoa.c | 2 +-
 STM32F1/cores/maple/itoa.h | 2 +-
 STM32F4/cores/maple/itoa.c | 2 +-
 STM32F4/cores/maple/itoa.h | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/STM32F1/cores/maple/itoa.c b/STM32F1/cores/maple/itoa.c
index ee74f829f..33efd14c6 100644
--- a/STM32F1/cores/maple/itoa.c
+++ b/STM32F1/cores/maple/itoa.c
@@ -124,7 +124,7 @@ extern char* ltoa( long value, char *string, int radix )
    (__GNUC_MINOR__ == 9 && __GNUC_PATCHLEVEL__ > 2)))
 extern char* utoa( unsigned value, char *string, int radix )
 #else
-extern char* utoa( unsigned long value, char *string, int radix )
+extern char* utoa( unsigned int value, char *string, int radix )
 #endif
 {
   return ultoa( value, string, radix ) ;
diff --git a/STM32F1/cores/maple/itoa.h b/STM32F1/cores/maple/itoa.h
index b88204c0e..9997b65c6 100644
--- a/STM32F1/cores/maple/itoa.h
+++ b/STM32F1/cores/maple/itoa.h
@@ -35,7 +35,7 @@ extern char* ltoa( long value, char *string, int radix ) ;
    (__GNUC_MINOR__ == 9 && __GNUC_PATCHLEVEL__ > 2)))
 extern char* utoa( unsigned value, char *string, int radix ) ;
 #else
-extern char* utoa( unsigned long value, char *string, int radix ) ;
+extern char* utoa( unsigned int value, char *string, int radix ) ;
 #endif
 extern char* ultoa( unsigned long value, char *string, int radix ) ;
 #endif /* 0 */
diff --git a/STM32F4/cores/maple/itoa.c b/STM32F4/cores/maple/itoa.c
index ee74f829f..33efd14c6 100644
--- a/STM32F4/cores/maple/itoa.c
+++ b/STM32F4/cores/maple/itoa.c
@@ -124,7 +124,7 @@ extern char* ltoa( long value, char *string, int radix )
    (__GNUC_MINOR__ == 9 && __GNUC_PATCHLEVEL__ > 2)))
 extern char* utoa( unsigned value, char *string, int radix )
 #else
-extern char* utoa( unsigned long value, char *string, int radix )
+extern char* utoa( unsigned int value, char *string, int radix )
 #endif
 {
   return ultoa( value, string, radix ) ;
diff --git a/STM32F4/cores/maple/itoa.h b/STM32F4/cores/maple/itoa.h
index a6e893de8..a317e82c1 100644
--- a/STM32F4/cores/maple/itoa.h
+++ b/STM32F4/cores/maple/itoa.h
@@ -35,7 +35,7 @@ extern char* ltoa( long value, char *string, int radix ) ;
    (__GNUC_MINOR__ == 9 && __GNUC_PATCHLEVEL__ > 2)))
 extern char* utoa( unsigned value, char *string, int radix ) ;
 #else
-extern char* utoa( unsigned long value, char *string, int radix ) ;
+extern char* utoa( unsigned int value, char *string, int radix ) ;
 #endif
 extern char* ultoa( unsigned long value, char *string, int radix ) ;
 #endif /* 0 */

From 15ce8137b92f5b0cdb3c6e5ac51f02e52eb2c7a4 Mon Sep 17 00:00:00 2001
From: "aka. N[]NE in gaming communities" <lgtngstk@hotmail.com>
Date: Mon, 6 Nov 2017 08:55:32 -0500
Subject: [PATCH 222/307] Update BlinkNcount.ino

Uses `#define` for LED pin instead of 5 literals
---
 .../General/BlinkNcount/BlinkNcount.ino       | 21 +++++++++++--------
 1 file changed, 12 insertions(+), 9 deletions(-)

diff --git a/STM32F1/libraries/A_STM32_Examples/examples/General/BlinkNcount/BlinkNcount.ino b/STM32F1/libraries/A_STM32_Examples/examples/General/BlinkNcount/BlinkNcount.ino
index 1b1f58a9f..b05ece9c4 100644
--- a/STM32F1/libraries/A_STM32_Examples/examples/General/BlinkNcount/BlinkNcount.ino
+++ b/STM32F1/libraries/A_STM32_Examples/examples/General/BlinkNcount/BlinkNcount.ino
@@ -1,35 +1,38 @@
 /*
-  BlinkNcount for Maple Mini by m. ray burnette
+  BlinkNcount for Maple Mini by m. ray burnette, update by The Lightning Stalker to use #define
     Sketch uses 13,808 bytes (12%) of program storage space. Maximum is 108,000 bytes.
     Global variables use 2,592 bytes of dynamic memory.
   Turns on an LED on for one second, then off for one second, repeatedly.
   Counts and displays the count on the attached serial monitor
   This example code is in the public domain.
- */
+*/
+
+#define LED_PIN PB1  // Maple Mini LED is on PB1, other boards may vary
+
 int n = 0;
 
 
-void setup() {                
+void setup() {
   // initialize the digital pin as an output.
-  pinMode(33, OUTPUT);
+  pinMode(LED_PIN, OUTPUT);
   // Initialize virtual COM over USB on Maple Mini
   Serial.begin(9600);  // BAUD has no effect on USB serial: placeholder for physical UART
   // wait for serial monitor to be connected.
   while (!Serial)
   {
-    digitalWrite(33,!digitalRead(33));// Turn the LED from off to on, or on to off
+    digitalWrite(LED_PIN, !digitalRead(LED_PIN)); // Turn the LED from off to on, or on to off
     delay(100);         // fast blink
   }
   Serial.println("Blink LED & count Demo");
 }
 
 void loop() {
-  digitalWrite(33, HIGH);   // set the LED on
+  digitalWrite(LED_PIN, HIGH);   // set the LED on
   delay(500);              // wait for a second
-  digitalWrite(33, LOW);    // set the LED off
+  digitalWrite(LED_PIN, LOW);    // set the LED off
   Serial.print("Loop #: ");
   n++;
   Serial.println(n);
-   
-  delay(500);              // wait 
+
+  delay(500);              // wait
 }

From 15d12bee18188a4276b83272bb6545713a3fc697 Mon Sep 17 00:00:00 2001
From: "aka. N[]NE in gaming communities" <lgtngstk@hotmail.com>
Date: Mon, 6 Nov 2017 19:00:41 -0500
Subject: [PATCH 223/307] Update BlinkNcount.c

Changed pin to PC13
---
 .../examples/General/BlinkNcount/BlinkNcount.ino                | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/libraries/A_STM32_Examples/examples/General/BlinkNcount/BlinkNcount.ino b/STM32F1/libraries/A_STM32_Examples/examples/General/BlinkNcount/BlinkNcount.ino
index b05ece9c4..60a4c17f6 100644
--- a/STM32F1/libraries/A_STM32_Examples/examples/General/BlinkNcount/BlinkNcount.ino
+++ b/STM32F1/libraries/A_STM32_Examples/examples/General/BlinkNcount/BlinkNcount.ino
@@ -7,7 +7,7 @@
   This example code is in the public domain.
 */
 
-#define LED_PIN PB1  // Maple Mini LED is on PB1, other boards may vary
+#define LED_PIN PC13  // Maple Mini LED is on PB1, other boards may vary
 
 int n = 0;
 

From c5ed88921ef7228bdd8decf9711e98536c3bd6a1 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Wed, 8 Nov 2017 15:29:25 +1100
Subject: [PATCH 224/307] Changed serial upload speed to 115200 as this speed
 is compatible with most USB to Serial adaptors

---
 tools/linux/serial_upload   | 2 +-
 tools/linux64/serial_upload | 2 +-
 tools/macosx/serial_upload  | 2 +-
 tools/win/serial_upload.bat | 2 +-
 4 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/tools/linux/serial_upload b/tools/linux/serial_upload
index 05d17c6e5..755444aad 100755
--- a/tools/linux/serial_upload
+++ b/tools/linux/serial_upload
@@ -1,2 +1,2 @@
 #!/bin/bash
-$(dirname $0)/stm32flash/stm32flash -g 0x8000000 -b 230400 -w "$4" /dev/"$1" 
+$(dirname $0)/stm32flash/stm32flash -g 0x8000000 -b 115200 -w "$4" /dev/"$1" 
diff --git a/tools/linux64/serial_upload b/tools/linux64/serial_upload
index 05d17c6e5..755444aad 100755
--- a/tools/linux64/serial_upload
+++ b/tools/linux64/serial_upload
@@ -1,2 +1,2 @@
 #!/bin/bash
-$(dirname $0)/stm32flash/stm32flash -g 0x8000000 -b 230400 -w "$4" /dev/"$1" 
+$(dirname $0)/stm32flash/stm32flash -g 0x8000000 -b 115200 -w "$4" /dev/"$1" 
diff --git a/tools/macosx/serial_upload b/tools/macosx/serial_upload
index 05d17c6e5..755444aad 100755
--- a/tools/macosx/serial_upload
+++ b/tools/macosx/serial_upload
@@ -1,2 +1,2 @@
 #!/bin/bash
-$(dirname $0)/stm32flash/stm32flash -g 0x8000000 -b 230400 -w "$4" /dev/"$1" 
+$(dirname $0)/stm32flash/stm32flash -g 0x8000000 -b 115200 -w "$4" /dev/"$1" 
diff --git a/tools/win/serial_upload.bat b/tools/win/serial_upload.bat
index d733be745..4c50fb707 100644
--- a/tools/win/serial_upload.bat
+++ b/tools/win/serial_upload.bat
@@ -8,7 +8,7 @@ cd %~dp0
 rem: the two line below are needed to fix path issues with incorrect slashes before the bin file name
 set str=%4
 set str=%str:/=\%
-stm32flash -g 0x8000000 -b 230400 -w %str% %1 
+stm32flash -g 0x8000000 -b 115200 -w %str% %1 
 rem: C:\Python27\python.exe stm32loader.py -e -w -p %1 -g -b 115200  %str%
 
 rem: ------------- use STM's own uploader 

From fd00f020722d7f8e69a974d28f4b9de4c5d62fe4 Mon Sep 17 00:00:00 2001
From: LightningStalker <lgtngstk@hotmail.com>
Date: Fri, 10 Nov 2017 04:10:31 -0500
Subject: [PATCH 225/307] Update BlinkNcount.ino to use LED_BUILTIN

---
 .../examples/General/BlinkNcount/BlinkNcount.ino  | 15 ++++++---------
 STM32F1/variants/generic_stm32f103c/variant.h     |  2 +-
 2 files changed, 7 insertions(+), 10 deletions(-)

diff --git a/STM32F1/libraries/A_STM32_Examples/examples/General/BlinkNcount/BlinkNcount.ino b/STM32F1/libraries/A_STM32_Examples/examples/General/BlinkNcount/BlinkNcount.ino
index 60a4c17f6..11f88f806 100644
--- a/STM32F1/libraries/A_STM32_Examples/examples/General/BlinkNcount/BlinkNcount.ino
+++ b/STM32F1/libraries/A_STM32_Examples/examples/General/BlinkNcount/BlinkNcount.ino
@@ -1,35 +1,32 @@
 /*
-  BlinkNcount for Maple Mini by m. ray burnette, update by The Lightning Stalker to use #define
+  BlinkNcount for Maple Mini by m. ray burnette
     Sketch uses 13,808 bytes (12%) of program storage space. Maximum is 108,000 bytes.
     Global variables use 2,592 bytes of dynamic memory.
   Turns on an LED on for one second, then off for one second, repeatedly.
   Counts and displays the count on the attached serial monitor
   This example code is in the public domain.
-*/
-
-#define LED_PIN PC13  // Maple Mini LED is on PB1, other boards may vary
-
+ */
 int n = 0;
 
 
 void setup() {
   // initialize the digital pin as an output.
-  pinMode(LED_PIN, OUTPUT);
+  pinMode(LED_BUILTIN, OUTPUT);
   // Initialize virtual COM over USB on Maple Mini
   Serial.begin(9600);  // BAUD has no effect on USB serial: placeholder for physical UART
   // wait for serial monitor to be connected.
   while (!Serial)
   {
-    digitalWrite(LED_PIN, !digitalRead(LED_PIN)); // Turn the LED from off to on, or on to off
+    digitalWrite(LED_BUILTIN,!digitalRead(LED_BUILTIN)); // Turn the LED from off to on, or on to off
     delay(100);         // fast blink
   }
   Serial.println("Blink LED & count Demo");
 }
 
 void loop() {
-  digitalWrite(LED_PIN, HIGH);   // set the LED on
+  digitalWrite(LED_BUILTIN, HIGH);   // set the LED on
   delay(500);              // wait for a second
-  digitalWrite(LED_PIN, LOW);    // set the LED off
+  digitalWrite(LED_BUILTIN, LOW);    // set the LED off
   Serial.print("Loop #: ");
   n++;
   Serial.println(n);
diff --git a/STM32F1/variants/generic_stm32f103c/variant.h b/STM32F1/variants/generic_stm32f103c/variant.h
index 4a9cfcd19..dc4b894f9 100644
--- a/STM32F1/variants/generic_stm32f103c/variant.h
+++ b/STM32F1/variants/generic_stm32f103c/variant.h
@@ -19,4 +19,4 @@ static const uint8_t SCK  = BOARD_SPI1_SCK_PIN;
 
 #define LED_BUILTIN PC13
 
-#endif /* _VARIANT_ARDUINO_STM32_ */
\ No newline at end of file
+#endif /* _VARIANT_ARDUINO_STM32_ */

From 9b4122ecaf999bd80c1ce6333d001883e44b4556 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Mon, 13 Nov 2017 11:56:13 +1100
Subject: [PATCH 226/307] Fixed exmple for HardTimerAsEncoder being in wrong
 location

---
 .../examples}/Sensors/HardTimerAsEncoder/HardTimerAsEncoder.ino   | 0
 1 file changed, 0 insertions(+), 0 deletions(-)
 rename {examples => STM32F1/libraries/A_STM32_Examples/examples}/Sensors/HardTimerAsEncoder/HardTimerAsEncoder.ino (100%)

diff --git a/examples/Sensors/HardTimerAsEncoder/HardTimerAsEncoder.ino b/STM32F1/libraries/A_STM32_Examples/examples/Sensors/HardTimerAsEncoder/HardTimerAsEncoder.ino
similarity index 100%
rename from examples/Sensors/HardTimerAsEncoder/HardTimerAsEncoder.ino
rename to STM32F1/libraries/A_STM32_Examples/examples/Sensors/HardTimerAsEncoder/HardTimerAsEncoder.ino

From c5caa5d288ca6c4a08fb8fe7e2125e6988cd1065 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Mon, 13 Nov 2017 12:03:19 +1100
Subject: [PATCH 227/307] Fixed missing definition of digitalPinToInterrupt, by
 adding macro which simply uses the pin number - as it doesnt need to be
 mapped

---
 STM32F1/cores/maple/wirish.h | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/STM32F1/cores/maple/wirish.h b/STM32F1/cores/maple/wirish.h
index 3ffee8331..eb07c771c 100644
--- a/STM32F1/cores/maple/wirish.h
+++ b/STM32F1/cores/maple/wirish.h
@@ -104,5 +104,7 @@ typedef unsigned int word;
 #define clockCyclesToMicroseconds(a) ( ((a) * 1000L) / (F_CPU / 1000L) )
 #define microsecondsToClockCycles(a) ( (a) * (F_CPU / 1000000L) )
 
+#define digitalPinToInterrupt(pin) (pin)
+
 #endif
 

From c66ca2ae9c6429d50d2e73b5fbc9b7c41c1268e6 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Mon, 13 Nov 2017 12:55:05 +1100
Subject: [PATCH 228/307] Fixed #273

---
 STM32F1/boards.txt | 1 -
 1 file changed, 1 deletion(-)

diff --git a/STM32F1/boards.txt b/STM32F1/boards.txt
index 10379ec55..96d94939d 100644
--- a/STM32F1/boards.txt
+++ b/STM32F1/boards.txt
@@ -299,7 +299,6 @@ nucleo_f103rb.build.core=maple
 nucleo_f103rb.build.ldscript=ld/jtag.ld
 nucleo_f103rb.build.variant=nucleo_f103rb
 nucleo_f103rb.build.variant_system_lib=libmaple.a
-nucleo_f103rb.build.vect=VECT_TAB_FLASH
 nucleo_f103rb.build.density=STM32_MEDIUM_DENSITY
 nucleo_f103rb.build.error_led_port=GPIOB
 nucleo_f103rb.build.error_led_pin=1

From dfb5bd4c30f42fa9cf2a0aef6b7d2a50a594fa97 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Mon, 13 Nov 2017 13:02:27 +0100
Subject: [PATCH 229/307] Update timer.h

- clear the IRQ flag before enabling the IRQ
---
 STM32F1/system/libmaple/include/libmaple/timer.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/STM32F1/system/libmaple/include/libmaple/timer.h b/STM32F1/system/libmaple/include/libmaple/timer.h
index 28b6c95ce..2c83e5e81 100644
--- a/STM32F1/system/libmaple/include/libmaple/timer.h
+++ b/STM32F1/system/libmaple/include/libmaple/timer.h
@@ -828,6 +828,7 @@ static inline void timer_dma_disable_req(timer_dev *dev, uint8 channel) {
  * @see timer_channel
  */
 static inline void timer_enable_irq(timer_dev *dev, uint8 interrupt) {
+    *bb_perip(&(dev->regs).adv->SR, interrupt) = 0; // clear interrupt flag
     *bb_perip(&(dev->regs).adv->DIER, interrupt) = 1;
 }
 

From 85f159b3a50bfe867c64ad78b6494f7a57150f5d Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Mon, 13 Nov 2017 13:06:52 +0100
Subject: [PATCH 230/307] Update boards.txt

remove duplicated lines
---
 STM32F1/boards.txt | 7 -------
 1 file changed, 7 deletions(-)

diff --git a/STM32F1/boards.txt b/STM32F1/boards.txt
index 96d94939d..49c12932a 100644
--- a/STM32F1/boards.txt
+++ b/STM32F1/boards.txt
@@ -44,13 +44,6 @@ mapleMini.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
 mapleMini.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
 mapleMini.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
 
-#-- CPU Clock frequency
-mapleMini.menu.cpu_speed.speed_72mhz=72Mhz (Normal)
-mapleMini.menu.cpu_speed.speed_72mhz.build.f_cpu=72000000L
-
-mapleMini.menu.cpu_speed.speed_48mhz=48Mhz (Slow - with USB)
-mapleMini.menu.cpu_speed.speed_48mhz.build.f_cpu=48000000L
-
 mapleMini.menu.cpu_speed.speed_128mhz=Overclocked 128Mhz NO USB SERIAL. MANUAL RESET NEEDED TO UPLOAD
 mapleMini.menu.cpu_speed.speed_128mhz.build.f_cpu=128000000L
 

From 9b03f0841d35bdb848701f684c8a85a92dec24e5 Mon Sep 17 00:00:00 2001
From: Alberto Alonso <alberto.linked@gmail.com>
Date: Mon, 13 Nov 2017 12:15:07 -0600
Subject: [PATCH 231/307] Solve race condition with arduino IDE monitoring
 serial port

I encountered a race condition upon which, even though the udev rules were working and uploads succeed, the serial monitor can not re-establish communications.

If the serial monitor is left open when doing an upload the error shown is:

[...]
Copying data from PC to DFU device
Starting download: [##################################################] finished!
state(8) = dfuMANIFEST-WAIT-RESET, status(0) = No error condition is present
Done!
Resetting USB to switch back to runtime mode
Waiting for /dev/ttyACM0 serial...Done
processing.app.SerialException: Error opening serial port '/dev/ttyACM0'. Try consulting the documentation at http://playground.arduino.cc/Linux/All#Permission
	at processing.app.Serial.<init>(Serial.java:145)
	at processing.app.Serial.<init>(Serial.java:82)
	at processing.app.SerialMonitor$4.<init>(SerialMonitor.java:101)
	at processing.app.SerialMonitor.open(SerialMonitor.java:101)
	at processing.app.AbstractMonitor.resume(AbstractMonitor.java:104)
	at processing.app.Editor.resumeOrCloseSerialMonitor(Editor.java:2218)
	at processing.app.Editor.access$2200(Editor.java:79)
	at processing.app.Editor$DefaultExportHandler.run(Editor.java:2196)
	at java.lang.Thread.run(Thread.java:748)
Error opening serial port '/dev/ttyACM0'. Try consulting the documentation at http://playground.arduino.cc/Linux/All#Permission

I traced it to the device being opened prior to the permissions/ownership changes.

When testing via -c the upload script waits for the character device creation, but at that point the udev rules have not changed the permissions. By testing the readability of the device via the -r test, we wait until the new permissions have been applied.

I imagine this is specific to the Linux kernel and the speed of the machine being used. In my case:
arduino-1.8.5
Linux 4.4.0-98-generic #121-Ubuntu SMP
but the change should work on any system with proper udev rules / permissions.
---
 tools/linux/maple_upload | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/tools/linux/maple_upload b/tools/linux/maple_upload
index 195317468..50d2ae557 100755
--- a/tools/linux/maple_upload
+++ b/tools/linux/maple_upload
@@ -42,7 +42,7 @@ fi
 echo -n Waiting for ${dummy_port_fullpath} serial...
 
 COUNTER=0
-while [ ! -c ${dummy_port_fullpath} ] && ((COUNTER++ < 40)); do
+while [ ! -r ${dummy_port_fullpath} ] && ((COUNTER++ < 40)); do
     sleep 0.1
 done
 

From 908a57a28e3e193e9f6070911e6b69b533ce716f Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Wed, 15 Nov 2017 22:56:00 +0100
Subject: [PATCH 232/307] Suppressing 'warning: missing initializer for member
 ... [-Wmissing-field-initializers]'

---
 STM32F1/variants/STM32VLD/board.cpp            | 4 +++-
 STM32F1/variants/generic_gd32f103c/board.cpp   | 6 +++---
 STM32F1/variants/generic_stm32f103c/board.cpp  | 7 +++----
 STM32F1/variants/generic_stm32f103r/board.cpp  | 4 +++-
 STM32F1/variants/generic_stm32f103r8/board.cpp | 4 +++-
 STM32F1/variants/generic_stm32f103t/board.cpp  | 4 +++-
 STM32F1/variants/generic_stm32f103v/board.cpp  | 6 ++++--
 STM32F1/variants/generic_stm32f103z/board.cpp  | 5 ++++-
 STM32F1/variants/hytiny_stm32f103t/board.cpp   | 4 +++-
 STM32F1/variants/maple/board.cpp               | 3 +++
 STM32F1/variants/maple_mini/board.cpp          | 5 ++++-
 STM32F1/variants/maple_ret6/board.cpp          | 5 ++++-
 STM32F1/variants/microduino/board.cpp          | 3 +++
 STM32F1/variants/nucleo_f103rb/board.cpp       | 5 ++++-
 14 files changed, 47 insertions(+), 18 deletions(-)

diff --git a/STM32F1/variants/STM32VLD/board.cpp b/STM32F1/variants/STM32VLD/board.cpp
index 1cecbd932..2561814a6 100644
--- a/STM32F1/variants/STM32VLD/board.cpp
+++ b/STM32F1/variants/STM32VLD/board.cpp
@@ -51,7 +51,8 @@ void boardInit(void) {
 }
 
 // Note. See the enum of pin names in board.h
-
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
 
@@ -113,6 +114,7 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 	{&gpiod,   NULL, NULL, 1, 0, ADCx},  /* PD2 */
 	{&gpiod,   NULL, NULL, 2, 0, ADCx},  /* PD2 */
 };
+#pragma GCC diagnostic pop
 
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
     PA0, PA1, PA2, PA3, PA6, PA7, PA8, PA9, PA10, PB0, PB1, PB6, PB7, PB8, PB9
diff --git a/STM32F1/variants/generic_gd32f103c/board.cpp b/STM32F1/variants/generic_gd32f103c/board.cpp
index 8b136f2a1..54f60beba 100644
--- a/STM32F1/variants/generic_gd32f103c/board.cpp
+++ b/STM32F1/variants/generic_gd32f103c/board.cpp
@@ -51,7 +51,8 @@ void boardInit(void) {
 }
 
 // Note. See the enum of pin names in board.h
-
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
 
@@ -93,9 +94,8 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
     {&gpioc,   NULL, NULL, 14, 0, ADCx}, /* PC14 */
     {&gpioc,   NULL, NULL, 15, 0, ADCx}, /* PC15 */
 
-
-
 };
+#pragma GCC diagnostic pop
 
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
     PB0, PA7, PA6, PA3, PA2, PA1, PA0, PB7, PB6, PA10, PA9, PA8
diff --git a/STM32F1/variants/generic_stm32f103c/board.cpp b/STM32F1/variants/generic_stm32f103c/board.cpp
index 7102adb9c..ac786cf00 100644
--- a/STM32F1/variants/generic_stm32f103c/board.cpp
+++ b/STM32F1/variants/generic_stm32f103c/board.cpp
@@ -51,7 +51,8 @@ void boardInit(void) {
 }
 
 // Note. See the enum of pin names in board.h
-
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
 
@@ -92,10 +93,8 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
     {&gpioc,   NULL, NULL, 13, 0, ADCx}, /* PC13 */	
     {&gpioc,   NULL, NULL, 14, 0, ADCx}, /* PC14 */
     {&gpioc,   NULL, NULL, 15, 0, ADCx}, /* PC15 */
-
-
-
 };
+#pragma GCC diagnostic pop
 
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
     PB0, PA7, PA6, PA3, PA2, PA1, PA0, PB7, PB6, PA10, PA9, PA8
diff --git a/STM32F1/variants/generic_stm32f103r/board.cpp b/STM32F1/variants/generic_stm32f103r/board.cpp
index 3e3589c23..e50314e2b 100644
--- a/STM32F1/variants/generic_stm32f103r/board.cpp
+++ b/STM32F1/variants/generic_stm32f103r/board.cpp
@@ -69,7 +69,8 @@ void boardInit(void) {
 // - Timer channel (1 to 4, for PWM), or 0 if none
 // - ADC device, or NULL if none
 // - ADC channel, or ADCx if none
-
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 /*
     gpio_dev *gpio_device;      GPIO device 
@@ -137,6 +138,7 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 	{&gpiod,   NULL, NULL,   1, 0, ADCx} , /* PD1  OSC_OUT */
 	{&gpiod,   NULL, NULL,   2, 0, ADCx} , /* PD2  TIM3_ETR/UART5_RX SDIO_CMD */
 };
+#pragma GCC diagnostic pop
 
 /*  Basically everything that is defined as having a timer us PWM */
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
diff --git a/STM32F1/variants/generic_stm32f103r8/board.cpp b/STM32F1/variants/generic_stm32f103r8/board.cpp
index 05f85a5cc..1987651b7 100644
--- a/STM32F1/variants/generic_stm32f103r8/board.cpp
+++ b/STM32F1/variants/generic_stm32f103r8/board.cpp
@@ -51,7 +51,8 @@ void boardInit(void) {
 }
 
 // Note. See the enum of pin names in board.h
-
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
 
@@ -111,6 +112,7 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
     {&gpiod,   NULL, NULL, 2, 0, ADCx},  /* PD2 */
 };
+#pragma GCC diagnostic pop
 
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
     PB0, PA7, PA6, PA3, PA2, PA1, PA0, PB7, PB6, PA10, PA9, PA8, PC6, PC7, PC8, PC9
diff --git a/STM32F1/variants/generic_stm32f103t/board.cpp b/STM32F1/variants/generic_stm32f103t/board.cpp
index e7a1dc0e0..003d225b3 100644
--- a/STM32F1/variants/generic_stm32f103t/board.cpp
+++ b/STM32F1/variants/generic_stm32f103t/board.cpp
@@ -51,7 +51,8 @@ void boardInit(void) {
 }
 
 // Note. See the enum of pin names in board.h
-
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
 
@@ -81,6 +82,7 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
     {&gpiob, &timer4, NULL,  6, 1, ADCx}, /* PB6 */
     {&gpiob, &timer4, NULL,  7, 2, ADCx}, /* PB7 */	
 };
+#pragma GCC diagnostic pop
 
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
     PB0, PA7, PA6, PA3, PA2, PA1, PA0, PB7, PB6, PA10, PA9, PA8
diff --git a/STM32F1/variants/generic_stm32f103v/board.cpp b/STM32F1/variants/generic_stm32f103v/board.cpp
index 9c137725a..8b241694c 100644
--- a/STM32F1/variants/generic_stm32f103v/board.cpp
+++ b/STM32F1/variants/generic_stm32f103v/board.cpp
@@ -68,7 +68,8 @@ void boardInit(void) {
 // - Timer channel (1 to 4, for PWM), or 0 if none
 // - ADC device, or NULL if none
 // - ADC channel, or ADCx if none
-
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 /*
     gpio_dev *gpio_device;      GPIO device 
@@ -166,6 +167,7 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 	{&gpioe,   NULL, NULL,  15, 0, ADCx} , /* PE15 FSMC_D12 */	
 	
 };
+#pragma GCC diagnostic pop
 
 /*  Basically everything that is defined as having a timer us PWM */
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
@@ -196,4 +198,4 @@ extern const uint8 boardUsedPins[BOARD_NR_USED_PINS] __FLASH__ = {
 	DEFINE_HWSERIAL(Serial2, 3);
 	DEFINE_HWSERIAL_UART(Serial3, 4);
 	DEFINE_HWSERIAL_UART(Serial4, 5);
-#endif
\ No newline at end of file
+#endif
diff --git a/STM32F1/variants/generic_stm32f103z/board.cpp b/STM32F1/variants/generic_stm32f103z/board.cpp
index 830479e96..4d2e4e989 100644
--- a/STM32F1/variants/generic_stm32f103z/board.cpp
+++ b/STM32F1/variants/generic_stm32f103z/board.cpp
@@ -69,6 +69,8 @@ void boardInit(void) {
 // - ADC device, or NULL if none
 // - ADC channel, or ADCx if none
 
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 /*
     gpio_dev *gpio_device;      GPIO device 
@@ -201,6 +203,7 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 	{&gpiog,   NULL, NULL,  14, 0, ADCx} , /* PG14  */
 	{&gpiog,   NULL, NULL,  15, 0, ADCx}  /* PG15  */		
 };
+#pragma GCC diagnostic pop
 
 /*  Basically everything that is defined as having a timer us PWM */
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
@@ -231,4 +234,4 @@ extern const uint8 boardUsedPins[BOARD_NR_USED_PINS] __FLASH__ = {
 	DEFINE_HWSERIAL(Serial2, 3);
 	DEFINE_HWSERIAL_UART(Serial3, 4);
 	DEFINE_HWSERIAL_UART(Serial4, 5);
-#endif
\ No newline at end of file
+#endif
diff --git a/STM32F1/variants/hytiny_stm32f103t/board.cpp b/STM32F1/variants/hytiny_stm32f103t/board.cpp
index f1fb44f07..d1260a6d0 100644
--- a/STM32F1/variants/hytiny_stm32f103t/board.cpp
+++ b/STM32F1/variants/hytiny_stm32f103t/board.cpp
@@ -51,7 +51,8 @@ void boardInit(void) {
 }
 
 // Note. See the enum of pin names in board.h
-
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
 
@@ -82,6 +83,7 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
     {&gpiob, &timer4, NULL,  7, 2, ADCx}, /* PB7 */	
 
 };
+#pragma GCC diagnostic pop
 
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
     PB0, PA7, PA6, PA3, PA2, PA1, PA0, PB7, PB6, PA10, PA9, PA8
diff --git a/STM32F1/variants/maple/board.cpp b/STM32F1/variants/maple/board.cpp
index a4c033557..b1584e7ea 100644
--- a/STM32F1/variants/maple/board.cpp
+++ b/STM32F1/variants/maple/board.cpp
@@ -68,6 +68,8 @@ void boardInit(void) {
 // - Timer channel (1 to 4, for PWM), or 0 if none
 // - ADC device, or NULL if none
 // - ADC channel, or ADCx if none
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
     /* Top header */
@@ -126,6 +128,7 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
     PMAP_ROW(&gpiob,   3,   NULL,  0, NULL, ADCx), /* D42/PB3  */
     PMAP_ROW(&gpiob,   4,   NULL,  0, NULL, ADCx), /* D43/PB4  */
 };
+#pragma GCC diagnostic pop
 
 // Array of pins you can use for pwmWrite(). Keep it in Flash because
 // it doesn't change, and so we don't waste RAM.
diff --git a/STM32F1/variants/maple_mini/board.cpp b/STM32F1/variants/maple_mini/board.cpp
index f49b33682..bf63364ae 100644
--- a/STM32F1/variants/maple_mini/board.cpp
+++ b/STM32F1/variants/maple_mini/board.cpp
@@ -50,6 +50,8 @@ void boardInit(void) {
 #endif
 }
 
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
     /* Top header */
@@ -92,6 +94,7 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
     {&gpiob, &timer4, NULL,  8, 3, ADCx}, /* D32/PB8 */
     {&gpiob, &timer3, &adc1,  1, 4,    9}, /* D33/PB1 */
 };
+#pragma GCC diagnostic pop
 
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
     3, 4, 5, 8, 9, 10, 11, 15, 16, 25, 26, 27
@@ -125,4 +128,4 @@ DEFINE_HWSERIAL(Serial1, 1);
 DEFINE_HWSERIAL(Serial2, 2);
 DEFINE_HWSERIAL(Serial3, 3);
 		
-	
\ No newline at end of file
+	
diff --git a/STM32F1/variants/maple_ret6/board.cpp b/STM32F1/variants/maple_ret6/board.cpp
index fb9277985..dfec977ba 100644
--- a/STM32F1/variants/maple_ret6/board.cpp
+++ b/STM32F1/variants/maple_ret6/board.cpp
@@ -69,6 +69,8 @@ void boardInit(void) {
 // - ADC device, or NULL if none
 // - ADC channel, or ADCx if none
 
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 /*
     gpio_dev *gpio_device;      GPIO device 
@@ -143,6 +145,7 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 	{ &gpiod, NULL, NULL, 1, 0, ADCx }, /* PD1  OSC_OUT */
 	{ &gpiob, NULL, NULL, 2, 0, ADCx }, /* PB2  */
 };
+#pragma GCC diagnostic pop
 
 /*  Basically everything that is defined as having a timer us PWM */
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
@@ -175,4 +178,4 @@ DEFINE_HWSERIAL(Serial1, 1);
 DEFINE_HWSERIAL(Serial2, 2);
 DEFINE_HWSERIAL(Serial3, 3);
 DEFINE_HWSERIAL_UART(Serial4, 4);
-DEFINE_HWSERIAL_UART(Serial5, 5);
\ No newline at end of file
+DEFINE_HWSERIAL_UART(Serial5, 5);
diff --git a/STM32F1/variants/microduino/board.cpp b/STM32F1/variants/microduino/board.cpp
index 2a002887b..d7b4a97d1 100644
--- a/STM32F1/variants/microduino/board.cpp
+++ b/STM32F1/variants/microduino/board.cpp
@@ -51,6 +51,8 @@ void boardInit(void) {
 #endif
 }
 
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
 
@@ -84,6 +86,7 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
     // FIXME: find out which pin is the button, if any
     {&gpiob,   NULL, NULL,  8, 0, ADCx}, /* D24/PB8??/Button */
 };
+#pragma GCC diagnostic pop
 
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
     0, 1, 4, 11, 12, 14, 15, 16, 17, 18, 19, 20, 21, 23
diff --git a/STM32F1/variants/nucleo_f103rb/board.cpp b/STM32F1/variants/nucleo_f103rb/board.cpp
index 9f3e08ae7..9754a2d43 100644
--- a/STM32F1/variants/nucleo_f103rb/board.cpp
+++ b/STM32F1/variants/nucleo_f103rb/board.cpp
@@ -93,6 +93,8 @@ rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSI_DIV_2, &pll_data};
 
 //       0    1    3      4    2     5
 //       0    1    2      4    2     5
+#pragma GCC diagnostic push
+#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
     /* Arduino-like header, right connectors */
@@ -149,6 +151,7 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
    // PMAP_ROW(&gpioa,  14,   NULL,  0, NULL, ADCx), /* D42/PA14  do not use*/
    // PMAP_ROW(&gpioa,  15,   &timer2,  1, NULL, ADCx), /* D43/PA15 do not use*/
 };
+#pragma GCC diagnostic pop
 
 // Array of pins you can use for pwmWrite(). Keep it in Flash because
 // it doesn't change, and so we don't waste RAM.
@@ -256,4 +259,4 @@ MOSI alternate functions on the GPIO ports.
    DEFINE_HWSERIAL(Serial, 3);// Use HW Serial 2 as "Serial"
    DEFINE_HWSERIAL(Serial1, 2);
    DEFINE_HWSERIAL(Serial2, 1);
-#endif
\ No newline at end of file
+#endif

From 8d9e2f24b6cde18363f113c70dc4fdae06941599 Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Wed, 15 Nov 2017 23:19:31 +0100
Subject: [PATCH 233/307] Suppressing 'warning: unused parameter ...
 [-Wunused-parameter]'

---
 STM32F1/cores/maple/libmaple/adc_f1.c         |  2 +-
 STM32F1/cores/maple/libmaple/spi_f1.c         |  2 +-
 STM32F1/cores/maple/libmaple/timer.c          |  2 +-
 STM32F1/cores/maple/libmaple/util.c           |  2 +-
 .../cores/maple/stm32f1/wiring_pulse_f1.cpp   |  2 +-
 STM32F1/cores/maple/usb_serial.cpp            |  4 ++--
 STM32F1/libraries/Wire/WireBase.cpp           |  2 +-
 .../libmaple/stm32f1/include/series/i2c.h     |  2 +-
 STM32F1/variants/STM32VLD/wirish/syscalls.c   | 22 +++++++++----------
 .../generic_gd32f103c/wirish/syscalls.c       | 18 +++++++--------
 .../generic_stm32f103c/wirish/syscalls.c      | 22 +++++++++----------
 .../generic_stm32f103r8/wirish/syscalls.c     | 22 +++++++++----------
 .../generic_stm32f103t/wirish/syscalls.c      | 22 +++++++++----------
 .../generic_stm32f103v/wirish/syscalls.c      | 22 +++++++++----------
 .../generic_stm32f103z/wirish/syscalls.c      | 22 +++++++++----------
 .../hytiny_stm32f103t/wirish/syscalls.c       | 22 +++++++++----------
 STM32F1/variants/maple/wirish/syscalls.c      | 22 +++++++++----------
 STM32F1/variants/maple_mini/wirish/syscalls.c | 22 +++++++++----------
 STM32F1/variants/maple_ret6/wirish/syscalls.c | 22 +++++++++----------
 STM32F1/variants/microduino/wirish/syscalls.c | 22 +++++++++----------
 .../variants/nucleo_f103rb/wirish/syscalls.c  | 22 +++++++++----------
 21 files changed, 150 insertions(+), 150 deletions(-)

diff --git a/STM32F1/cores/maple/libmaple/adc_f1.c b/STM32F1/cores/maple/libmaple/adc_f1.c
index d099f6d50..5305b02af 100644
--- a/STM32F1/cores/maple/libmaple/adc_f1.c
+++ b/STM32F1/cores/maple/libmaple/adc_f1.c
@@ -203,7 +203,7 @@ void adc_foreach(void (*fn)(adc_dev*)) {
 #endif
 }
 
-void adc_config_gpio(adc_dev *ignored, gpio_dev *gdev, uint8 bit) {
+void adc_config_gpio(adc_dev *ignored __attribute__((unused)), gpio_dev *gdev, uint8 bit) {
     gpio_set_mode(gdev, bit, GPIO_INPUT_ANALOG);
 }
 
diff --git a/STM32F1/cores/maple/libmaple/spi_f1.c b/STM32F1/cores/maple/libmaple/spi_f1.c
index bbea5a440..d920761a0 100644
--- a/STM32F1/cores/maple/libmaple/spi_f1.c
+++ b/STM32F1/cores/maple/libmaple/spi_f1.c
@@ -54,7 +54,7 @@ spi_dev *SPI3 = &spi3;
  * Routines
  */
 
-void spi_config_gpios(spi_dev *ignored,
+void spi_config_gpios(spi_dev *ignored __attribute__((unused)),
                       uint8 as_master,
                       gpio_dev *nss_dev,
                       uint8 nss_bit,
diff --git a/STM32F1/cores/maple/libmaple/timer.c b/STM32F1/cores/maple/libmaple/timer.c
index daf8e439c..70e20654c 100644
--- a/STM32F1/cores/maple/libmaple/timer.c
+++ b/STM32F1/cores/maple/libmaple/timer.c
@@ -327,7 +327,7 @@ static void output_compare_mode(timer_dev *dev, uint8 channel) {
 }
 
 //added by CARLOS.
-static void encoder_mode(timer_dev *dev, uint8 channel) {
+static void encoder_mode(timer_dev *dev, uint8 channel __attribute__((unused))) {
     
     //prescaler. 
     //(dev->regs).gen->PSC = 1;
diff --git a/STM32F1/cores/maple/libmaple/util.c b/STM32F1/cores/maple/libmaple/util.c
index 4c0b2c8ec..f488ea4d4 100644
--- a/STM32F1/cores/maple/libmaple/util.c
+++ b/STM32F1/cores/maple/libmaple/util.c
@@ -88,7 +88,7 @@ void _fail(const char* file, int line, const char* exp) {
  * Provide an __assert_func handler to libc so that calls to assert()
  * get redirected to _fail.
  */
-void __assert_func(const char* file, int line, const char* method,
+void __assert_func(const char* file, int line, const char* method __attribute__((unused)),
                    const char* expression) {
     _fail(file, line, expression);
 }
diff --git a/STM32F1/cores/maple/stm32f1/wiring_pulse_f1.cpp b/STM32F1/cores/maple/stm32f1/wiring_pulse_f1.cpp
index 9ca4d7fb8..d9287b07b 100644
--- a/STM32F1/cores/maple/stm32f1/wiring_pulse_f1.cpp
+++ b/STM32F1/cores/maple/stm32f1/wiring_pulse_f1.cpp
@@ -26,7 +26,7 @@
   * to be slighly more accurate the maxLoops variable really needs to take into account the loop setup code, but its probably as good as necessary
   *
   */
-uint32_t pulseIn( uint32_t pin, uint32_t state, uint32_t timeout )
+uint32_t pulseIn( uint32_t pin, uint32_t state __attribute__((unused)), uint32_t timeout )
 {
    // cache the port and bit of the pin in order to speed up the
    // pulse width measuring loop and achieve finer resolution.  calling
diff --git a/STM32F1/cores/maple/usb_serial.cpp b/STM32F1/cores/maple/usb_serial.cpp
index 0902c50e6..e6d5cb0e5 100644
--- a/STM32F1/cores/maple/usb_serial.cpp
+++ b/STM32F1/cores/maple/usb_serial.cpp
@@ -236,7 +236,7 @@ enum reset_state_t {
 
 static reset_state_t reset_state = DTR_UNSET;
 
-static void ifaceSetupHook(unsigned hook, void *requestvp) {
+static void ifaceSetupHook(unsigned hook __attribute__((unused)), void *requestvp) {
     uint8 request = *(uint8*)requestvp;
 
     // Ignore requests we're not interested in.
@@ -290,7 +290,7 @@ static void wait_reset(void) {
 #define STACK_TOP 0x20000800
 #define EXC_RETURN 0xFFFFFFF9
 #define DEFAULT_CPSR 0x61000000
-static void rxHook(unsigned hook, void *ignored) {
+static void rxHook(unsigned hook __attribute__((unused)), void *ignored __attribute__((unused))) {
     /* FIXME this is mad buggy; we need a new reset sequence. E.g. NAK
      * after each RX means you can't reset if any bytes are waiting. */
     if (reset_state == DTR_NEGEDGE) {
diff --git a/STM32F1/libraries/Wire/WireBase.cpp b/STM32F1/libraries/Wire/WireBase.cpp
index 220d845d7..eaa7f91ad 100644
--- a/STM32F1/libraries/Wire/WireBase.cpp
+++ b/STM32F1/libraries/Wire/WireBase.cpp
@@ -41,7 +41,7 @@
 #include "WireBase.h"
 #include "wirish.h"
 
-void WireBase::begin(uint8 self_addr) {
+void WireBase::begin(uint8 self_addr __attribute__((unused))) {
     tx_buf_idx = 0;
     tx_buf_overflow = false;
     rx_buf_idx = 0;
diff --git a/STM32F1/system/libmaple/stm32f1/include/series/i2c.h b/STM32F1/system/libmaple/stm32f1/include/series/i2c.h
index f4079559c..35655036a 100644
--- a/STM32F1/system/libmaple/stm32f1/include/series/i2c.h
+++ b/STM32F1/system/libmaple/stm32f1/include/series/i2c.h
@@ -59,7 +59,7 @@ extern i2c_dev* const I2C2;
  * For internal use
  */
 
-static inline uint32 _i2c_bus_clk(i2c_dev *dev) {
+static inline uint32 _i2c_bus_clk(i2c_dev *dev __attribute__((unused))) {
     /* Both I2C peripherals are on APB1 */
     return STM32_PCLK1 / (1000 * 1000);
 }
diff --git a/STM32F1/variants/STM32VLD/wirish/syscalls.c b/STM32F1/variants/STM32VLD/wirish/syscalls.c
index d42536c58..91ed5a104 100644
--- a/STM32F1/variants/STM32VLD/wirish/syscalls.c
+++ b/STM32F1/variants/STM32VLD/wirish/syscalls.c
@@ -76,28 +76,28 @@ void *_sbrk(int incr) {
     return ret;
 }
 
-__weak int _open(const char *path, int flags, ...) {
+__weak int _open(const char *path __attribute__((unused)), int flags __attribute__((unused)), ...) {
     return 1;
 }
 
-__weak int _close(int fd) {
+__weak int _close(int fd __attribute__((unused))) {
     return 0;
 }
 
-__weak int _fstat(int fd, struct stat *st) {
+__weak int _fstat(int fd __attribute__((unused)), struct stat *st) {
     st->st_mode = S_IFCHR;
     return 0;
 }
 
-__weak int _isatty(int fd) {
+__weak int _isatty(int fd __attribute__((unused))) {
     return 1;
 }
 
-__weak int isatty(int fd) {
+__weak int isatty(int fd __attribute__((unused))) {
     return 1;
 }
 
-__weak int _lseek(int fd, off_t pos, int whence) {
+__weak int _lseek(int fd __attribute__((unused)), off_t pos __attribute__((unused)), int whence __attribute__((unused))) {
     return -1;
 }
 
@@ -106,13 +106,13 @@ __weak unsigned char getch(void) {
 }
 
 
-__weak int _read(int fd, char *buf, size_t cnt) {
+__weak int _read(int fd __attribute__((unused)), char *buf, size_t cnt __attribute__((unused))) {
     *buf = getch();
 
     return 1;
 }
 
-__weak void putch(unsigned char c) {
+__weak void putch(unsigned char c __attribute__((unused))) {
 }
 
 __weak void cgets(char *s, int bufsize) {
@@ -155,7 +155,7 @@ __weak void cgets(char *s, int bufsize) {
     return;
 }
 
-__weak int _write(int fd, const char *buf, size_t cnt) {
+__weak int _write(int fd __attribute__((unused)), const char *buf, size_t cnt) {
     int i;
 
     for (i = 0; i < cnt; i++)
@@ -165,12 +165,12 @@ __weak int _write(int fd, const char *buf, size_t cnt) {
 }
 
 /* Override fgets() in newlib with a version that does line editing */
-__weak char *fgets(char *s, int bufsize, void *f) {
+__weak char *fgets(char *s, int bufsize, void *f __attribute__((unused))) {
     cgets(s, bufsize);
     return s;
 }
 
-__weak void _exit(int exitcode) {
+__weak void _exit(int exitcode __attribute__((unused))) {
     while (1)
         ;
 }
diff --git a/STM32F1/variants/generic_gd32f103c/wirish/syscalls.c b/STM32F1/variants/generic_gd32f103c/wirish/syscalls.c
index d5f2d9fac..6558dbd3b 100644
--- a/STM32F1/variants/generic_gd32f103c/wirish/syscalls.c
+++ b/STM32F1/variants/generic_gd32f103c/wirish/syscalls.c
@@ -76,15 +76,15 @@ void *_sbrk(int incr) {
     return ret;
 }
 
-__weak int _open(const char *path, int flags, ...) {
+__weak int _open(const char *path __attribute__((unused)), int flags __attribute__((unused)), ...) {
     return 1;
 }
 
-__weak int _close(int fd) {
+__weak int _close(int fd __attribute__((unused))) {
     return 0;
 }
 
-__weak int _fstat(int fd, struct stat *st) {
+__weak int _fstat(int fd __attribute__((unused)), struct stat *st) {
     st->st_mode = S_IFCHR;
     return 0;
 }
@@ -97,7 +97,7 @@ __weak int isatty(int fd) {
     return 1;
 }
 
-__weak int _lseek(int fd, off_t pos, int whence) {
+__weak int _lseek(int fd __attribute__((unused)), off_t pos __attribute__((unused)), int whence __attribute__((unused))) {
     return -1;
 }
 
@@ -106,13 +106,13 @@ __weak unsigned char getch(void) {
 }
 
 
-__weak int _read(int fd, char *buf, size_t cnt) {
+__weak int _read(int fd __attribute__((unused)), char *buf, size_t cnt __attribute__((unused))) {
     *buf = getch();
 
     return 1;
 }
 
-__weak void putch(unsigned char c) {
+__weak void putch(unsigned char c __attribute__((unused))) {
 }
 
 __weak void cgets(char *s, int bufsize) {
@@ -155,7 +155,7 @@ __weak void cgets(char *s, int bufsize) {
     return;
 }
 
-__weak int _write(int fd, const char *buf, size_t cnt) {
+__weak int _write(int fd __attribute__((unused)), const char *buf, size_t cnt) {
     int i;
 
     for (i = 0; i < cnt; i++)
@@ -165,12 +165,12 @@ __weak int _write(int fd, const char *buf, size_t cnt) {
 }
 
 /* Override fgets() in newlib with a version that does line editing */
-__weak char *fgets(char *s, int bufsize, void *f) {
+__weak char *fgets(char *s, int bufsize, void *f __attribute__((unused))) {
     cgets(s, bufsize);
     return s;
 }
 
-__weak void _exit(int exitcode) {
+__weak void _exit(int exitcode __attribute__((unused))) {
     while (1)
         ;
 }
diff --git a/STM32F1/variants/generic_stm32f103c/wirish/syscalls.c b/STM32F1/variants/generic_stm32f103c/wirish/syscalls.c
index d42536c58..91ed5a104 100644
--- a/STM32F1/variants/generic_stm32f103c/wirish/syscalls.c
+++ b/STM32F1/variants/generic_stm32f103c/wirish/syscalls.c
@@ -76,28 +76,28 @@ void *_sbrk(int incr) {
     return ret;
 }
 
-__weak int _open(const char *path, int flags, ...) {
+__weak int _open(const char *path __attribute__((unused)), int flags __attribute__((unused)), ...) {
     return 1;
 }
 
-__weak int _close(int fd) {
+__weak int _close(int fd __attribute__((unused))) {
     return 0;
 }
 
-__weak int _fstat(int fd, struct stat *st) {
+__weak int _fstat(int fd __attribute__((unused)), struct stat *st) {
     st->st_mode = S_IFCHR;
     return 0;
 }
 
-__weak int _isatty(int fd) {
+__weak int _isatty(int fd __attribute__((unused))) {
     return 1;
 }
 
-__weak int isatty(int fd) {
+__weak int isatty(int fd __attribute__((unused))) {
     return 1;
 }
 
-__weak int _lseek(int fd, off_t pos, int whence) {
+__weak int _lseek(int fd __attribute__((unused)), off_t pos __attribute__((unused)), int whence __attribute__((unused))) {
     return -1;
 }
 
@@ -106,13 +106,13 @@ __weak unsigned char getch(void) {
 }
 
 
-__weak int _read(int fd, char *buf, size_t cnt) {
+__weak int _read(int fd __attribute__((unused)), char *buf, size_t cnt __attribute__((unused))) {
     *buf = getch();
 
     return 1;
 }
 
-__weak void putch(unsigned char c) {
+__weak void putch(unsigned char c __attribute__((unused))) {
 }
 
 __weak void cgets(char *s, int bufsize) {
@@ -155,7 +155,7 @@ __weak void cgets(char *s, int bufsize) {
     return;
 }
 
-__weak int _write(int fd, const char *buf, size_t cnt) {
+__weak int _write(int fd __attribute__((unused)), const char *buf, size_t cnt) {
     int i;
 
     for (i = 0; i < cnt; i++)
@@ -165,12 +165,12 @@ __weak int _write(int fd, const char *buf, size_t cnt) {
 }
 
 /* Override fgets() in newlib with a version that does line editing */
-__weak char *fgets(char *s, int bufsize, void *f) {
+__weak char *fgets(char *s, int bufsize, void *f __attribute__((unused))) {
     cgets(s, bufsize);
     return s;
 }
 
-__weak void _exit(int exitcode) {
+__weak void _exit(int exitcode __attribute__((unused))) {
     while (1)
         ;
 }
diff --git a/STM32F1/variants/generic_stm32f103r8/wirish/syscalls.c b/STM32F1/variants/generic_stm32f103r8/wirish/syscalls.c
index d42536c58..91ed5a104 100644
--- a/STM32F1/variants/generic_stm32f103r8/wirish/syscalls.c
+++ b/STM32F1/variants/generic_stm32f103r8/wirish/syscalls.c
@@ -76,28 +76,28 @@ void *_sbrk(int incr) {
     return ret;
 }
 
-__weak int _open(const char *path, int flags, ...) {
+__weak int _open(const char *path __attribute__((unused)), int flags __attribute__((unused)), ...) {
     return 1;
 }
 
-__weak int _close(int fd) {
+__weak int _close(int fd __attribute__((unused))) {
     return 0;
 }
 
-__weak int _fstat(int fd, struct stat *st) {
+__weak int _fstat(int fd __attribute__((unused)), struct stat *st) {
     st->st_mode = S_IFCHR;
     return 0;
 }
 
-__weak int _isatty(int fd) {
+__weak int _isatty(int fd __attribute__((unused))) {
     return 1;
 }
 
-__weak int isatty(int fd) {
+__weak int isatty(int fd __attribute__((unused))) {
     return 1;
 }
 
-__weak int _lseek(int fd, off_t pos, int whence) {
+__weak int _lseek(int fd __attribute__((unused)), off_t pos __attribute__((unused)), int whence __attribute__((unused))) {
     return -1;
 }
 
@@ -106,13 +106,13 @@ __weak unsigned char getch(void) {
 }
 
 
-__weak int _read(int fd, char *buf, size_t cnt) {
+__weak int _read(int fd __attribute__((unused)), char *buf, size_t cnt __attribute__((unused))) {
     *buf = getch();
 
     return 1;
 }
 
-__weak void putch(unsigned char c) {
+__weak void putch(unsigned char c __attribute__((unused))) {
 }
 
 __weak void cgets(char *s, int bufsize) {
@@ -155,7 +155,7 @@ __weak void cgets(char *s, int bufsize) {
     return;
 }
 
-__weak int _write(int fd, const char *buf, size_t cnt) {
+__weak int _write(int fd __attribute__((unused)), const char *buf, size_t cnt) {
     int i;
 
     for (i = 0; i < cnt; i++)
@@ -165,12 +165,12 @@ __weak int _write(int fd, const char *buf, size_t cnt) {
 }
 
 /* Override fgets() in newlib with a version that does line editing */
-__weak char *fgets(char *s, int bufsize, void *f) {
+__weak char *fgets(char *s, int bufsize, void *f __attribute__((unused))) {
     cgets(s, bufsize);
     return s;
 }
 
-__weak void _exit(int exitcode) {
+__weak void _exit(int exitcode __attribute__((unused))) {
     while (1)
         ;
 }
diff --git a/STM32F1/variants/generic_stm32f103t/wirish/syscalls.c b/STM32F1/variants/generic_stm32f103t/wirish/syscalls.c
index d42536c58..91ed5a104 100644
--- a/STM32F1/variants/generic_stm32f103t/wirish/syscalls.c
+++ b/STM32F1/variants/generic_stm32f103t/wirish/syscalls.c
@@ -76,28 +76,28 @@ void *_sbrk(int incr) {
     return ret;
 }
 
-__weak int _open(const char *path, int flags, ...) {
+__weak int _open(const char *path __attribute__((unused)), int flags __attribute__((unused)), ...) {
     return 1;
 }
 
-__weak int _close(int fd) {
+__weak int _close(int fd __attribute__((unused))) {
     return 0;
 }
 
-__weak int _fstat(int fd, struct stat *st) {
+__weak int _fstat(int fd __attribute__((unused)), struct stat *st) {
     st->st_mode = S_IFCHR;
     return 0;
 }
 
-__weak int _isatty(int fd) {
+__weak int _isatty(int fd __attribute__((unused))) {
     return 1;
 }
 
-__weak int isatty(int fd) {
+__weak int isatty(int fd __attribute__((unused))) {
     return 1;
 }
 
-__weak int _lseek(int fd, off_t pos, int whence) {
+__weak int _lseek(int fd __attribute__((unused)), off_t pos __attribute__((unused)), int whence __attribute__((unused))) {
     return -1;
 }
 
@@ -106,13 +106,13 @@ __weak unsigned char getch(void) {
 }
 
 
-__weak int _read(int fd, char *buf, size_t cnt) {
+__weak int _read(int fd __attribute__((unused)), char *buf, size_t cnt __attribute__((unused))) {
     *buf = getch();
 
     return 1;
 }
 
-__weak void putch(unsigned char c) {
+__weak void putch(unsigned char c __attribute__((unused))) {
 }
 
 __weak void cgets(char *s, int bufsize) {
@@ -155,7 +155,7 @@ __weak void cgets(char *s, int bufsize) {
     return;
 }
 
-__weak int _write(int fd, const char *buf, size_t cnt) {
+__weak int _write(int fd __attribute__((unused)), const char *buf, size_t cnt) {
     int i;
 
     for (i = 0; i < cnt; i++)
@@ -165,12 +165,12 @@ __weak int _write(int fd, const char *buf, size_t cnt) {
 }
 
 /* Override fgets() in newlib with a version that does line editing */
-__weak char *fgets(char *s, int bufsize, void *f) {
+__weak char *fgets(char *s, int bufsize, void *f __attribute__((unused))) {
     cgets(s, bufsize);
     return s;
 }
 
-__weak void _exit(int exitcode) {
+__weak void _exit(int exitcode __attribute__((unused))) {
     while (1)
         ;
 }
diff --git a/STM32F1/variants/generic_stm32f103v/wirish/syscalls.c b/STM32F1/variants/generic_stm32f103v/wirish/syscalls.c
index d5f2d9fac..ec1c34dba 100644
--- a/STM32F1/variants/generic_stm32f103v/wirish/syscalls.c
+++ b/STM32F1/variants/generic_stm32f103v/wirish/syscalls.c
@@ -76,28 +76,28 @@ void *_sbrk(int incr) {
     return ret;
 }
 
-__weak int _open(const char *path, int flags, ...) {
+__weak int _open(const char *path __attribute__((unused)), int flags __attribute__((unused)), ...) {
     return 1;
 }
 
-__weak int _close(int fd) {
+__weak int _close(int fd __attribute__((unused))) {
     return 0;
 }
 
-__weak int _fstat(int fd, struct stat *st) {
+__weak int _fstat(int fd __attribute__((unused)), struct stat *st) {
     st->st_mode = S_IFCHR;
     return 0;
 }
 
-__weak int _isatty(int fd) {
+__weak int _isatty(int fd __attribute__((unused))) {
     return 1;
 }
 
-__weak int isatty(int fd) {
+__weak int isatty(int fd __attribute__((unused))) {
     return 1;
 }
 
-__weak int _lseek(int fd, off_t pos, int whence) {
+__weak int _lseek(int fd __attribute__((unused)), off_t pos __attribute__((unused)), int whence __attribute__((unused))) {
     return -1;
 }
 
@@ -106,13 +106,13 @@ __weak unsigned char getch(void) {
 }
 
 
-__weak int _read(int fd, char *buf, size_t cnt) {
+__weak int _read(int fd __attribute__((unused)), char *buf, size_t cnt __attribute__((unused))) {
     *buf = getch();
 
     return 1;
 }
 
-__weak void putch(unsigned char c) {
+__weak void putch(unsigned char c __attribute__((unused))) {
 }
 
 __weak void cgets(char *s, int bufsize) {
@@ -155,7 +155,7 @@ __weak void cgets(char *s, int bufsize) {
     return;
 }
 
-__weak int _write(int fd, const char *buf, size_t cnt) {
+__weak int _write(int fd __attribute__((unused)), const char *buf, size_t cnt) {
     int i;
 
     for (i = 0; i < cnt; i++)
@@ -165,12 +165,12 @@ __weak int _write(int fd, const char *buf, size_t cnt) {
 }
 
 /* Override fgets() in newlib with a version that does line editing */
-__weak char *fgets(char *s, int bufsize, void *f) {
+__weak char *fgets(char *s, int bufsize, void *f __attribute__((unused))) {
     cgets(s, bufsize);
     return s;
 }
 
-__weak void _exit(int exitcode) {
+__weak void _exit(int exitcode __attribute__((unused))) {
     while (1)
         ;
 }
diff --git a/STM32F1/variants/generic_stm32f103z/wirish/syscalls.c b/STM32F1/variants/generic_stm32f103z/wirish/syscalls.c
index d42536c58..91ed5a104 100644
--- a/STM32F1/variants/generic_stm32f103z/wirish/syscalls.c
+++ b/STM32F1/variants/generic_stm32f103z/wirish/syscalls.c
@@ -76,28 +76,28 @@ void *_sbrk(int incr) {
     return ret;
 }
 
-__weak int _open(const char *path, int flags, ...) {
+__weak int _open(const char *path __attribute__((unused)), int flags __attribute__((unused)), ...) {
     return 1;
 }
 
-__weak int _close(int fd) {
+__weak int _close(int fd __attribute__((unused))) {
     return 0;
 }
 
-__weak int _fstat(int fd, struct stat *st) {
+__weak int _fstat(int fd __attribute__((unused)), struct stat *st) {
     st->st_mode = S_IFCHR;
     return 0;
 }
 
-__weak int _isatty(int fd) {
+__weak int _isatty(int fd __attribute__((unused))) {
     return 1;
 }
 
-__weak int isatty(int fd) {
+__weak int isatty(int fd __attribute__((unused))) {
     return 1;
 }
 
-__weak int _lseek(int fd, off_t pos, int whence) {
+__weak int _lseek(int fd __attribute__((unused)), off_t pos __attribute__((unused)), int whence __attribute__((unused))) {
     return -1;
 }
 
@@ -106,13 +106,13 @@ __weak unsigned char getch(void) {
 }
 
 
-__weak int _read(int fd, char *buf, size_t cnt) {
+__weak int _read(int fd __attribute__((unused)), char *buf, size_t cnt __attribute__((unused))) {
     *buf = getch();
 
     return 1;
 }
 
-__weak void putch(unsigned char c) {
+__weak void putch(unsigned char c __attribute__((unused))) {
 }
 
 __weak void cgets(char *s, int bufsize) {
@@ -155,7 +155,7 @@ __weak void cgets(char *s, int bufsize) {
     return;
 }
 
-__weak int _write(int fd, const char *buf, size_t cnt) {
+__weak int _write(int fd __attribute__((unused)), const char *buf, size_t cnt) {
     int i;
 
     for (i = 0; i < cnt; i++)
@@ -165,12 +165,12 @@ __weak int _write(int fd, const char *buf, size_t cnt) {
 }
 
 /* Override fgets() in newlib with a version that does line editing */
-__weak char *fgets(char *s, int bufsize, void *f) {
+__weak char *fgets(char *s, int bufsize, void *f __attribute__((unused))) {
     cgets(s, bufsize);
     return s;
 }
 
-__weak void _exit(int exitcode) {
+__weak void _exit(int exitcode __attribute__((unused))) {
     while (1)
         ;
 }
diff --git a/STM32F1/variants/hytiny_stm32f103t/wirish/syscalls.c b/STM32F1/variants/hytiny_stm32f103t/wirish/syscalls.c
index d5f2d9fac..ec1c34dba 100644
--- a/STM32F1/variants/hytiny_stm32f103t/wirish/syscalls.c
+++ b/STM32F1/variants/hytiny_stm32f103t/wirish/syscalls.c
@@ -76,28 +76,28 @@ void *_sbrk(int incr) {
     return ret;
 }
 
-__weak int _open(const char *path, int flags, ...) {
+__weak int _open(const char *path __attribute__((unused)), int flags __attribute__((unused)), ...) {
     return 1;
 }
 
-__weak int _close(int fd) {
+__weak int _close(int fd __attribute__((unused))) {
     return 0;
 }
 
-__weak int _fstat(int fd, struct stat *st) {
+__weak int _fstat(int fd __attribute__((unused)), struct stat *st) {
     st->st_mode = S_IFCHR;
     return 0;
 }
 
-__weak int _isatty(int fd) {
+__weak int _isatty(int fd __attribute__((unused))) {
     return 1;
 }
 
-__weak int isatty(int fd) {
+__weak int isatty(int fd __attribute__((unused))) {
     return 1;
 }
 
-__weak int _lseek(int fd, off_t pos, int whence) {
+__weak int _lseek(int fd __attribute__((unused)), off_t pos __attribute__((unused)), int whence __attribute__((unused))) {
     return -1;
 }
 
@@ -106,13 +106,13 @@ __weak unsigned char getch(void) {
 }
 
 
-__weak int _read(int fd, char *buf, size_t cnt) {
+__weak int _read(int fd __attribute__((unused)), char *buf, size_t cnt __attribute__((unused))) {
     *buf = getch();
 
     return 1;
 }
 
-__weak void putch(unsigned char c) {
+__weak void putch(unsigned char c __attribute__((unused))) {
 }
 
 __weak void cgets(char *s, int bufsize) {
@@ -155,7 +155,7 @@ __weak void cgets(char *s, int bufsize) {
     return;
 }
 
-__weak int _write(int fd, const char *buf, size_t cnt) {
+__weak int _write(int fd __attribute__((unused)), const char *buf, size_t cnt) {
     int i;
 
     for (i = 0; i < cnt; i++)
@@ -165,12 +165,12 @@ __weak int _write(int fd, const char *buf, size_t cnt) {
 }
 
 /* Override fgets() in newlib with a version that does line editing */
-__weak char *fgets(char *s, int bufsize, void *f) {
+__weak char *fgets(char *s, int bufsize, void *f __attribute__((unused))) {
     cgets(s, bufsize);
     return s;
 }
 
-__weak void _exit(int exitcode) {
+__weak void _exit(int exitcode __attribute__((unused))) {
     while (1)
         ;
 }
diff --git a/STM32F1/variants/maple/wirish/syscalls.c b/STM32F1/variants/maple/wirish/syscalls.c
index d5f2d9fac..ec1c34dba 100644
--- a/STM32F1/variants/maple/wirish/syscalls.c
+++ b/STM32F1/variants/maple/wirish/syscalls.c
@@ -76,28 +76,28 @@ void *_sbrk(int incr) {
     return ret;
 }
 
-__weak int _open(const char *path, int flags, ...) {
+__weak int _open(const char *path __attribute__((unused)), int flags __attribute__((unused)), ...) {
     return 1;
 }
 
-__weak int _close(int fd) {
+__weak int _close(int fd __attribute__((unused))) {
     return 0;
 }
 
-__weak int _fstat(int fd, struct stat *st) {
+__weak int _fstat(int fd __attribute__((unused)), struct stat *st) {
     st->st_mode = S_IFCHR;
     return 0;
 }
 
-__weak int _isatty(int fd) {
+__weak int _isatty(int fd __attribute__((unused))) {
     return 1;
 }
 
-__weak int isatty(int fd) {
+__weak int isatty(int fd __attribute__((unused))) {
     return 1;
 }
 
-__weak int _lseek(int fd, off_t pos, int whence) {
+__weak int _lseek(int fd __attribute__((unused)), off_t pos __attribute__((unused)), int whence __attribute__((unused))) {
     return -1;
 }
 
@@ -106,13 +106,13 @@ __weak unsigned char getch(void) {
 }
 
 
-__weak int _read(int fd, char *buf, size_t cnt) {
+__weak int _read(int fd __attribute__((unused)), char *buf, size_t cnt __attribute__((unused))) {
     *buf = getch();
 
     return 1;
 }
 
-__weak void putch(unsigned char c) {
+__weak void putch(unsigned char c __attribute__((unused))) {
 }
 
 __weak void cgets(char *s, int bufsize) {
@@ -155,7 +155,7 @@ __weak void cgets(char *s, int bufsize) {
     return;
 }
 
-__weak int _write(int fd, const char *buf, size_t cnt) {
+__weak int _write(int fd __attribute__((unused)), const char *buf, size_t cnt) {
     int i;
 
     for (i = 0; i < cnt; i++)
@@ -165,12 +165,12 @@ __weak int _write(int fd, const char *buf, size_t cnt) {
 }
 
 /* Override fgets() in newlib with a version that does line editing */
-__weak char *fgets(char *s, int bufsize, void *f) {
+__weak char *fgets(char *s, int bufsize, void *f __attribute__((unused))) {
     cgets(s, bufsize);
     return s;
 }
 
-__weak void _exit(int exitcode) {
+__weak void _exit(int exitcode __attribute__((unused))) {
     while (1)
         ;
 }
diff --git a/STM32F1/variants/maple_mini/wirish/syscalls.c b/STM32F1/variants/maple_mini/wirish/syscalls.c
index d5f2d9fac..ec1c34dba 100644
--- a/STM32F1/variants/maple_mini/wirish/syscalls.c
+++ b/STM32F1/variants/maple_mini/wirish/syscalls.c
@@ -76,28 +76,28 @@ void *_sbrk(int incr) {
     return ret;
 }
 
-__weak int _open(const char *path, int flags, ...) {
+__weak int _open(const char *path __attribute__((unused)), int flags __attribute__((unused)), ...) {
     return 1;
 }
 
-__weak int _close(int fd) {
+__weak int _close(int fd __attribute__((unused))) {
     return 0;
 }
 
-__weak int _fstat(int fd, struct stat *st) {
+__weak int _fstat(int fd __attribute__((unused)), struct stat *st) {
     st->st_mode = S_IFCHR;
     return 0;
 }
 
-__weak int _isatty(int fd) {
+__weak int _isatty(int fd __attribute__((unused))) {
     return 1;
 }
 
-__weak int isatty(int fd) {
+__weak int isatty(int fd __attribute__((unused))) {
     return 1;
 }
 
-__weak int _lseek(int fd, off_t pos, int whence) {
+__weak int _lseek(int fd __attribute__((unused)), off_t pos __attribute__((unused)), int whence __attribute__((unused))) {
     return -1;
 }
 
@@ -106,13 +106,13 @@ __weak unsigned char getch(void) {
 }
 
 
-__weak int _read(int fd, char *buf, size_t cnt) {
+__weak int _read(int fd __attribute__((unused)), char *buf, size_t cnt __attribute__((unused))) {
     *buf = getch();
 
     return 1;
 }
 
-__weak void putch(unsigned char c) {
+__weak void putch(unsigned char c __attribute__((unused))) {
 }
 
 __weak void cgets(char *s, int bufsize) {
@@ -155,7 +155,7 @@ __weak void cgets(char *s, int bufsize) {
     return;
 }
 
-__weak int _write(int fd, const char *buf, size_t cnt) {
+__weak int _write(int fd __attribute__((unused)), const char *buf, size_t cnt) {
     int i;
 
     for (i = 0; i < cnt; i++)
@@ -165,12 +165,12 @@ __weak int _write(int fd, const char *buf, size_t cnt) {
 }
 
 /* Override fgets() in newlib with a version that does line editing */
-__weak char *fgets(char *s, int bufsize, void *f) {
+__weak char *fgets(char *s, int bufsize, void *f __attribute__((unused))) {
     cgets(s, bufsize);
     return s;
 }
 
-__weak void _exit(int exitcode) {
+__weak void _exit(int exitcode __attribute__((unused))) {
     while (1)
         ;
 }
diff --git a/STM32F1/variants/maple_ret6/wirish/syscalls.c b/STM32F1/variants/maple_ret6/wirish/syscalls.c
index d5f2d9fac..ec1c34dba 100644
--- a/STM32F1/variants/maple_ret6/wirish/syscalls.c
+++ b/STM32F1/variants/maple_ret6/wirish/syscalls.c
@@ -76,28 +76,28 @@ void *_sbrk(int incr) {
     return ret;
 }
 
-__weak int _open(const char *path, int flags, ...) {
+__weak int _open(const char *path __attribute__((unused)), int flags __attribute__((unused)), ...) {
     return 1;
 }
 
-__weak int _close(int fd) {
+__weak int _close(int fd __attribute__((unused))) {
     return 0;
 }
 
-__weak int _fstat(int fd, struct stat *st) {
+__weak int _fstat(int fd __attribute__((unused)), struct stat *st) {
     st->st_mode = S_IFCHR;
     return 0;
 }
 
-__weak int _isatty(int fd) {
+__weak int _isatty(int fd __attribute__((unused))) {
     return 1;
 }
 
-__weak int isatty(int fd) {
+__weak int isatty(int fd __attribute__((unused))) {
     return 1;
 }
 
-__weak int _lseek(int fd, off_t pos, int whence) {
+__weak int _lseek(int fd __attribute__((unused)), off_t pos __attribute__((unused)), int whence __attribute__((unused))) {
     return -1;
 }
 
@@ -106,13 +106,13 @@ __weak unsigned char getch(void) {
 }
 
 
-__weak int _read(int fd, char *buf, size_t cnt) {
+__weak int _read(int fd __attribute__((unused)), char *buf, size_t cnt __attribute__((unused))) {
     *buf = getch();
 
     return 1;
 }
 
-__weak void putch(unsigned char c) {
+__weak void putch(unsigned char c __attribute__((unused))) {
 }
 
 __weak void cgets(char *s, int bufsize) {
@@ -155,7 +155,7 @@ __weak void cgets(char *s, int bufsize) {
     return;
 }
 
-__weak int _write(int fd, const char *buf, size_t cnt) {
+__weak int _write(int fd __attribute__((unused)), const char *buf, size_t cnt) {
     int i;
 
     for (i = 0; i < cnt; i++)
@@ -165,12 +165,12 @@ __weak int _write(int fd, const char *buf, size_t cnt) {
 }
 
 /* Override fgets() in newlib with a version that does line editing */
-__weak char *fgets(char *s, int bufsize, void *f) {
+__weak char *fgets(char *s, int bufsize, void *f __attribute__((unused))) {
     cgets(s, bufsize);
     return s;
 }
 
-__weak void _exit(int exitcode) {
+__weak void _exit(int exitcode __attribute__((unused))) {
     while (1)
         ;
 }
diff --git a/STM32F1/variants/microduino/wirish/syscalls.c b/STM32F1/variants/microduino/wirish/syscalls.c
index d5f2d9fac..ec1c34dba 100644
--- a/STM32F1/variants/microduino/wirish/syscalls.c
+++ b/STM32F1/variants/microduino/wirish/syscalls.c
@@ -76,28 +76,28 @@ void *_sbrk(int incr) {
     return ret;
 }
 
-__weak int _open(const char *path, int flags, ...) {
+__weak int _open(const char *path __attribute__((unused)), int flags __attribute__((unused)), ...) {
     return 1;
 }
 
-__weak int _close(int fd) {
+__weak int _close(int fd __attribute__((unused))) {
     return 0;
 }
 
-__weak int _fstat(int fd, struct stat *st) {
+__weak int _fstat(int fd __attribute__((unused)), struct stat *st) {
     st->st_mode = S_IFCHR;
     return 0;
 }
 
-__weak int _isatty(int fd) {
+__weak int _isatty(int fd __attribute__((unused))) {
     return 1;
 }
 
-__weak int isatty(int fd) {
+__weak int isatty(int fd __attribute__((unused))) {
     return 1;
 }
 
-__weak int _lseek(int fd, off_t pos, int whence) {
+__weak int _lseek(int fd __attribute__((unused)), off_t pos __attribute__((unused)), int whence __attribute__((unused))) {
     return -1;
 }
 
@@ -106,13 +106,13 @@ __weak unsigned char getch(void) {
 }
 
 
-__weak int _read(int fd, char *buf, size_t cnt) {
+__weak int _read(int fd __attribute__((unused)), char *buf, size_t cnt __attribute__((unused))) {
     *buf = getch();
 
     return 1;
 }
 
-__weak void putch(unsigned char c) {
+__weak void putch(unsigned char c __attribute__((unused))) {
 }
 
 __weak void cgets(char *s, int bufsize) {
@@ -155,7 +155,7 @@ __weak void cgets(char *s, int bufsize) {
     return;
 }
 
-__weak int _write(int fd, const char *buf, size_t cnt) {
+__weak int _write(int fd __attribute__((unused)), const char *buf, size_t cnt) {
     int i;
 
     for (i = 0; i < cnt; i++)
@@ -165,12 +165,12 @@ __weak int _write(int fd, const char *buf, size_t cnt) {
 }
 
 /* Override fgets() in newlib with a version that does line editing */
-__weak char *fgets(char *s, int bufsize, void *f) {
+__weak char *fgets(char *s, int bufsize, void *f __attribute__((unused))) {
     cgets(s, bufsize);
     return s;
 }
 
-__weak void _exit(int exitcode) {
+__weak void _exit(int exitcode __attribute__((unused))) {
     while (1)
         ;
 }
diff --git a/STM32F1/variants/nucleo_f103rb/wirish/syscalls.c b/STM32F1/variants/nucleo_f103rb/wirish/syscalls.c
index d5f2d9fac..ec1c34dba 100644
--- a/STM32F1/variants/nucleo_f103rb/wirish/syscalls.c
+++ b/STM32F1/variants/nucleo_f103rb/wirish/syscalls.c
@@ -76,28 +76,28 @@ void *_sbrk(int incr) {
     return ret;
 }
 
-__weak int _open(const char *path, int flags, ...) {
+__weak int _open(const char *path __attribute__((unused)), int flags __attribute__((unused)), ...) {
     return 1;
 }
 
-__weak int _close(int fd) {
+__weak int _close(int fd __attribute__((unused))) {
     return 0;
 }
 
-__weak int _fstat(int fd, struct stat *st) {
+__weak int _fstat(int fd __attribute__((unused)), struct stat *st) {
     st->st_mode = S_IFCHR;
     return 0;
 }
 
-__weak int _isatty(int fd) {
+__weak int _isatty(int fd __attribute__((unused))) {
     return 1;
 }
 
-__weak int isatty(int fd) {
+__weak int isatty(int fd __attribute__((unused))) {
     return 1;
 }
 
-__weak int _lseek(int fd, off_t pos, int whence) {
+__weak int _lseek(int fd __attribute__((unused)), off_t pos __attribute__((unused)), int whence __attribute__((unused))) {
     return -1;
 }
 
@@ -106,13 +106,13 @@ __weak unsigned char getch(void) {
 }
 
 
-__weak int _read(int fd, char *buf, size_t cnt) {
+__weak int _read(int fd __attribute__((unused)), char *buf, size_t cnt __attribute__((unused))) {
     *buf = getch();
 
     return 1;
 }
 
-__weak void putch(unsigned char c) {
+__weak void putch(unsigned char c __attribute__((unused))) {
 }
 
 __weak void cgets(char *s, int bufsize) {
@@ -155,7 +155,7 @@ __weak void cgets(char *s, int bufsize) {
     return;
 }
 
-__weak int _write(int fd, const char *buf, size_t cnt) {
+__weak int _write(int fd __attribute__((unused)), const char *buf, size_t cnt) {
     int i;
 
     for (i = 0; i < cnt; i++)
@@ -165,12 +165,12 @@ __weak int _write(int fd, const char *buf, size_t cnt) {
 }
 
 /* Override fgets() in newlib with a version that does line editing */
-__weak char *fgets(char *s, int bufsize, void *f) {
+__weak char *fgets(char *s, int bufsize, void *f __attribute__((unused))) {
     cgets(s, bufsize);
     return s;
 }
 
-__weak void _exit(int exitcode) {
+__weak void _exit(int exitcode __attribute__((unused))) {
     while (1)
         ;
 }

From 29ff4e739d35fda2760784a0c8945ee30ed3cb42 Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Thu, 16 Nov 2017 19:20:25 +0100
Subject: [PATCH 234/307] Fixed 'warning: missing initializer for member ...
 [-Wmissing-field-initializers]'

---
 STM32F1/cores/maple/boards_private.h          |   2 +-
 STM32F1/variants/STM32VLD/board.cpp           | 111 ++++-----
 STM32F1/variants/generic_gd32f103c/board.cpp  |  75 +++---
 STM32F1/variants/generic_stm32f103c/board.cpp |  75 +++---
 STM32F1/variants/generic_stm32f103r/board.cpp | 111 ++++-----
 .../variants/generic_stm32f103r8/board.cpp    | 107 ++++----
 STM32F1/variants/generic_stm32f103t/board.cpp |  51 ++--
 STM32F1/variants/generic_stm32f103v/board.cpp | 167 ++++++-------
 STM32F1/variants/generic_stm32f103z/board.cpp | 235 +++++++++---------
 STM32F1/variants/hytiny_stm32f103t/board.cpp  |  51 ++--
 STM32F1/variants/maple/board.cpp              |   3 -
 STM32F1/variants/maple_mini/board.cpp         |  71 +++---
 STM32F1/variants/maple_ret6/board.cpp         | 101 ++++----
 STM32F1/variants/microduino/board.cpp         |  57 ++---
 STM32F1/variants/nucleo_f103rb/board.cpp      | 101 ++++----
 STM32F3/cores/maple/wirish/boards_private.h   |   2 +-
 16 files changed, 639 insertions(+), 681 deletions(-)

diff --git a/STM32F1/cores/maple/boards_private.h b/STM32F1/cores/maple/boards_private.h
index 49867ca77..332843ddf 100644
--- a/STM32F1/cores/maple/boards_private.h
+++ b/STM32F1/cores/maple/boards_private.h
@@ -42,7 +42,7 @@
 
 /* Makes the PIN_MAP rows more human-readable. */
 #define PMAP_ROW(gpio_dev, gpio_bit, timer_dev, timer_ch, adc_dev, adc_ch) \
-    { gpio_dev, timer_dev, adc_dev, gpio_bit, timer_ch, adc_ch }
+    { gpio_dev, timer_dev, adc_dev, gpio_bit, timer_ch, adc_ch, 0}
 
 namespace wirish {
     namespace priv {
diff --git a/STM32F1/variants/STM32VLD/board.cpp b/STM32F1/variants/STM32VLD/board.cpp
index 2561814a6..182e8f721 100644
--- a/STM32F1/variants/STM32VLD/board.cpp
+++ b/STM32F1/variants/STM32VLD/board.cpp
@@ -51,70 +51,67 @@ void boardInit(void) {
 }
 
 // Note. See the enum of pin names in board.h
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
 
-    {&gpioa, &timer2, &adc1,  0, 1,    0}, /* PA0 */
-    {&gpioa, &timer2, &adc1,  1, 2,    1}, /* PA1 */
-    {&gpioa, &timer2, &adc1,  2, 3,    2}, /* PA2 */	
-    {&gpioa, &timer2, &adc1,  3, 4,    3}, /* PA3 */
-    {&gpioa,   	NULL, &adc1,  4, 0,    4}, /* PA4 */
-    {&gpioa,   	NULL, &adc1,  5, 0,    5}, /* PA5 */
-    {&gpioa, &timer3, &adc1,  6, 1,    6}, /* PA6 */
-    {&gpioa, &timer3, &adc1,  7, 2,    7}, /* PA7 */
-    {&gpioa, &timer1, NULL,  8, 1, ADCx}, /* PA8 */	
-    {&gpioa, &timer1, NULL,  9, 2, ADCx}, /* PA9 */	
-    {&gpioa, &timer1, NULL, 10, 3, ADCx}, /* PA10 */
-    {&gpioa,	NULL, NULL, 11, 0, ADCx}, /* PA11 */
-    {&gpioa,   	NULL, NULL, 12, 0, ADCx}, /* PA12 */	
-    {&gpioa,   	NULL, NULL, 13, 0, ADCx}, /* PA13 */	
-    {&gpioa,   	NULL, NULL, 14, 0, ADCx}, /* PA14 */
-    {&gpioa,   	NULL, NULL, 15, 0, ADCx}, /* PA15 */
+    {&gpioa, &timer2, &adc1,  0, 1,    0, 0}, /* PA0 */
+    {&gpioa, &timer2, &adc1,  1, 2,    1, 0}, /* PA1 */
+    {&gpioa, &timer2, &adc1,  2, 3,    2, 0}, /* PA2 */
+    {&gpioa, &timer2, &adc1,  3, 4,    3, 0}, /* PA3 */
+    {&gpioa,   	NULL, &adc1,  4, 0,    4, 0}, /* PA4 */
+    {&gpioa,   	NULL, &adc1,  5, 0,    5, 0}, /* PA5 */
+    {&gpioa, &timer3, &adc1,  6, 1,    6, 0}, /* PA6 */
+    {&gpioa, &timer3, &adc1,  7, 2,    7, 0}, /* PA7 */
+    {&gpioa, &timer1, NULL,  8, 1, ADCx, 0}, /* PA8 */
+    {&gpioa, &timer1, NULL,  9, 2, ADCx, 0}, /* PA9 */
+    {&gpioa, &timer1, NULL, 10, 3, ADCx, 0}, /* PA10 */
+    {&gpioa,	NULL, NULL, 11, 0, ADCx, 0}, /* PA11 */
+    {&gpioa,   	NULL, NULL, 12, 0, ADCx, 0}, /* PA12 */
+    {&gpioa,   	NULL, NULL, 13, 0, ADCx, 0}, /* PA13 */
+    {&gpioa,   	NULL, NULL, 14, 0, ADCx, 0}, /* PA14 */
+    {&gpioa,   	NULL, NULL, 15, 0, ADCx, 0}, /* PA15 */
 	
-    {&gpiob, &timer3, &adc1,  0, 3,    8}, /* PB0 */	
-    {&gpiob, &timer3, &adc1,  1, 4,    9}, /* PB1 */
-    {&gpiob,   	NULL, NULL,  2, 0, ADCx}, /* PB2 */
-    {&gpiob,   	NULL, NULL,  3, 0, ADCx}, /* PB3 */
-    {&gpiob,   NULL, NULL,  4, 0, ADCx}, /* PB4 */
-    {&gpiob,   NULL, NULL,  5, 0, ADCx}, /* PB5 */
-    {&gpiob, &timer4, NULL,  6, 1, ADCx}, /* PB6 */
-    {&gpiob, &timer4, NULL,  7, 2, ADCx}, /* PB7 */	
-    {&gpiob, &timer4, NULL,  8, 3, ADCx}, /* PB8 */	
-    {&gpiob, &timer4, NULL,  9, 4, ADCx}, /* PB9 */	
-    {&gpiob,   NULL, NULL, 10, 0, ADCx}, /* PB10 */	
-    {&gpiob,   NULL, NULL, 11, 0, ADCx}, /* PB11 */
-    {&gpiob,   NULL, NULL, 12, 0, ADCx}, /* PB12 */
-    {&gpiob,   NULL, NULL, 13, 0, ADCx}, /* PB13 */
-    {&gpiob,   NULL, NULL, 14, 0, ADCx}, /* PB14 */
-    {&gpiob,   NULL, NULL, 15, 0, ADCx}, /* PB15 */
+    {&gpiob, &timer3, &adc1,  0, 3,    8, 0}, /* PB0 */
+    {&gpiob, &timer3, &adc1,  1, 4,    9, 0}, /* PB1 */
+    {&gpiob,   	NULL, NULL,  2, 0, ADCx, 0}, /* PB2 */
+    {&gpiob,   	NULL, NULL,  3, 0, ADCx, 0}, /* PB3 */
+    {&gpiob,   NULL, NULL,  4, 0, ADCx, 0}, /* PB4 */
+    {&gpiob,   NULL, NULL,  5, 0, ADCx, 0}, /* PB5 */
+    {&gpiob, &timer4, NULL,  6, 1, ADCx, 0}, /* PB6 */
+    {&gpiob, &timer4, NULL,  7, 2, ADCx, 0}, /* PB7 */
+    {&gpiob, &timer4, NULL,  8, 3, ADCx, 0}, /* PB8 */
+    {&gpiob, &timer4, NULL,  9, 4, ADCx, 0}, /* PB9 */
+    {&gpiob,   NULL, NULL, 10, 0, ADCx, 0}, /* PB10 */
+    {&gpiob,   NULL, NULL, 11, 0, ADCx, 0}, /* PB11 */
+    {&gpiob,   NULL, NULL, 12, 0, ADCx, 0}, /* PB12 */
+    {&gpiob,   NULL, NULL, 13, 0, ADCx, 0}, /* PB13 */
+    {&gpiob,   NULL, NULL, 14, 0, ADCx, 0}, /* PB14 */
+    {&gpiob,   NULL, NULL, 15, 0, ADCx, 0}, /* PB15 */
 
 /* Andy Hull - the R8 is similar to the C8 but exposes more GPIO as follows */
-    {&gpioc,   NULL, &adc1, 0, 0, 10},  /* PC0 */
-    {&gpioc,   NULL, &adc1, 1, 0, 11},  /* PC1 */
-    {&gpioc,   NULL, &adc1, 2, 0, 12},  /* PC2 */
-    {&gpioc,   NULL, &adc1, 3, 0, 13},  /* PC3 */
-    {&gpioc,   NULL, &adc1, 4, 0, 14},  /* PC4 */
-    {&gpioc,   NULL, &adc1, 5, 0, 15},  /* PC5 */
-
-    {&gpioc,   NULL, NULL, 6, 0, ADCx},  /* PC6 */
-    {&gpioc,   NULL, NULL, 7, 0, ADCx},  /* PC7 */
-    {&gpioc,   NULL, NULL, 8, 0, ADCx},  /* PC8 */
-    {&gpioc,   NULL, NULL, 9, 0, ADCx},  /* PC9 */
-
-    {&gpioc,   NULL, NULL, 10, 0, ADCx}, /* PC10 */
-    {&gpioc,   NULL, NULL, 11, 0, ADCx}, /* PC11 */
-    {&gpioc,   NULL, NULL, 12, 0, ADCx}, /* PC12 */
-    {&gpioc,   NULL, NULL, 13, 0, ADCx}, /* PC13 */	
-    {&gpioc,   NULL, NULL, 14, 0, ADCx}, /* PC14 */
-    {&gpioc,   NULL, NULL, 15, 0, ADCx}, /* PC15 */
-
-    {&gpiod,   NULL, NULL, 0, 0, ADCx},  /* PD2 */
-	{&gpiod,   NULL, NULL, 1, 0, ADCx},  /* PD2 */
-	{&gpiod,   NULL, NULL, 2, 0, ADCx},  /* PD2 */
+    {&gpioc,   NULL, &adc1, 0, 0, 10, 0},  /* PC0 */
+    {&gpioc,   NULL, &adc1, 1, 0, 11, 0},  /* PC1 */
+    {&gpioc,   NULL, &adc1, 2, 0, 12, 0},  /* PC2 */
+    {&gpioc,   NULL, &adc1, 3, 0, 13, 0},  /* PC3 */
+    {&gpioc,   NULL, &adc1, 4, 0, 14, 0},  /* PC4 */
+    {&gpioc,   NULL, &adc1, 5, 0, 15, 0},  /* PC5 */
+
+    {&gpioc,   NULL, NULL, 6, 0, ADCx, 0},  /* PC6 */
+    {&gpioc,   NULL, NULL, 7, 0, ADCx, 0},  /* PC7 */
+    {&gpioc,   NULL, NULL, 8, 0, ADCx, 0},  /* PC8 */
+    {&gpioc,   NULL, NULL, 9, 0, ADCx, 0},  /* PC9 */
+
+    {&gpioc,   NULL, NULL, 10, 0, ADCx, 0}, /* PC10 */
+    {&gpioc,   NULL, NULL, 11, 0, ADCx, 0}, /* PC11 */
+    {&gpioc,   NULL, NULL, 12, 0, ADCx, 0}, /* PC12 */
+    {&gpioc,   NULL, NULL, 13, 0, ADCx, 0}, /* PC13 */
+    {&gpioc,   NULL, NULL, 14, 0, ADCx, 0}, /* PC14 */
+    {&gpioc,   NULL, NULL, 15, 0, ADCx, 0}, /* PC15 */
+
+    {&gpiod,   NULL, NULL, 0, 0, ADCx, 0},  /* PD2 */
+	{&gpiod,   NULL, NULL, 1, 0, ADCx, 0},  /* PD2 */
+	{&gpiod,   NULL, NULL, 2, 0, ADCx, 0},  /* PD2 */
 };
-#pragma GCC diagnostic pop
 
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
     PA0, PA1, PA2, PA3, PA6, PA7, PA8, PA9, PA10, PB0, PB1, PB6, PB7, PB8, PB9
diff --git a/STM32F1/variants/generic_gd32f103c/board.cpp b/STM32F1/variants/generic_gd32f103c/board.cpp
index 54f60beba..da22d526b 100644
--- a/STM32F1/variants/generic_gd32f103c/board.cpp
+++ b/STM32F1/variants/generic_gd32f103c/board.cpp
@@ -51,51 +51,48 @@ void boardInit(void) {
 }
 
 // Note. See the enum of pin names in board.h
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
 
-    {&gpioa, &timer2, &adc1,  0, 1,    0}, /* PA0 */
-    {&gpioa, &timer2, &adc1,  1, 2,    1}, /* PA1 */
-    {&gpioa, &timer2, &adc1,  2, 3,    2}, /* PA2 */	
-    {&gpioa, &timer2, &adc1,  3, 4,    3}, /* PA3 */
-    {&gpioa,   NULL, &adc1,  4, 0,    4}, /* PA4 */
-    {&gpioa,   NULL, &adc1,  5, 0,    5}, /* PA5 */
-    {&gpioa, &timer3, &adc1,  6, 1,    6}, /* PA6 */
-    {&gpioa, &timer3, &adc1,  7, 2,    7}, /* PA7 */
-    {&gpioa, &timer1, NULL,  8, 1, ADCx}, /* PA8 */	
-    {&gpioa, &timer1, NULL,  9, 2, ADCx}, /* PA9 */	
-    {&gpioa, &timer1, NULL, 10, 3, ADCx}, /* PA10 */
-    {&gpioa, &timer1, NULL, 11, 4, ADCx}, /* PA11 */
-    {&gpioa,   NULL, NULL, 12, 0, ADCx}, /* PA12 */	
-    {&gpioa,   NULL, NULL, 13, 0, ADCx}, /* PA13 */	
-    {&gpioa,   NULL, NULL, 14, 0, ADCx}, /* PA14 */
-    {&gpioa,   NULL, NULL, 15, 0, ADCx}, /* PA15 */
+    {&gpioa, &timer2, &adc1,  0, 1,    0, 0}, /* PA0 */
+    {&gpioa, &timer2, &adc1,  1, 2,    1, 0}, /* PA1 */
+    {&gpioa, &timer2, &adc1,  2, 3,    2, 0}, /* PA2 */
+    {&gpioa, &timer2, &adc1,  3, 4,    3, 0}, /* PA3 */
+    {&gpioa,   NULL, &adc1,  4, 0,    4, 0}, /* PA4 */
+    {&gpioa,   NULL, &adc1,  5, 0,    5, 0}, /* PA5 */
+    {&gpioa, &timer3, &adc1,  6, 1,    6, 0}, /* PA6 */
+    {&gpioa, &timer3, &adc1,  7, 2,    7, 0}, /* PA7 */
+    {&gpioa, &timer1, NULL,  8, 1, ADCx, 0}, /* PA8 */
+    {&gpioa, &timer1, NULL,  9, 2, ADCx, 0}, /* PA9 */
+    {&gpioa, &timer1, NULL, 10, 3, ADCx, 0}, /* PA10 */
+    {&gpioa, &timer1, NULL, 11, 4, ADCx, 0}, /* PA11 */
+    {&gpioa,   NULL, NULL, 12, 0, ADCx, 0}, /* PA12 */
+    {&gpioa,   NULL, NULL, 13, 0, ADCx, 0}, /* PA13 */
+    {&gpioa,   NULL, NULL, 14, 0, ADCx, 0}, /* PA14 */
+    {&gpioa,   NULL, NULL, 15, 0, ADCx, 0}, /* PA15 */
 	
-    {&gpiob, &timer3, &adc1,  0, 3,    8}, /* PB0 */	
-    {&gpiob, &timer3, &adc1,  1, 4,    9}, /* PB1 */
-    {&gpiob,   NULL, NULL,  2, 0, ADCx}, /* PB2 */
-    {&gpiob,   NULL, NULL,  3, 0, ADCx}, /* PB3 */
-    {&gpiob,   NULL, NULL,  4, 0, ADCx}, /* PB4 */
-    {&gpiob,   NULL, NULL,  5, 0, ADCx}, /* PB5 */
-    {&gpiob, &timer4, NULL,  6, 1, ADCx}, /* PB6 */
-    {&gpiob, &timer4, NULL,  7, 2, ADCx}, /* PB7 */	
-    {&gpiob, &timer4, NULL,  8, 3, ADCx}, /* PB8 */	
-    {&gpiob, &timer4, NULL,  9, 4, ADCx}, /* PB9 */	
-    {&gpiob,   NULL, NULL, 10, 0, ADCx}, /* PB10 */	
-    {&gpiob,   NULL, NULL, 11, 0, ADCx}, /* PB11 */
-    {&gpiob,   NULL, NULL, 12, 0, ADCx}, /* PB12 */
-    {&gpiob,   NULL, NULL, 13, 0, ADCx}, /* PB13 */
-    {&gpiob,   NULL, NULL, 14, 0, ADCx}, /* PB14 */
-    {&gpiob,   NULL, NULL, 15, 0, ADCx}, /* PB15 */
-
-    {&gpioc,   NULL, NULL, 13, 0, ADCx}, /* PC13 */	
-    {&gpioc,   NULL, NULL, 14, 0, ADCx}, /* PC14 */
-    {&gpioc,   NULL, NULL, 15, 0, ADCx}, /* PC15 */
+    {&gpiob, &timer3, &adc1,  0, 3,    8, 0}, /* PB0 */
+    {&gpiob, &timer3, &adc1,  1, 4,    9, 0}, /* PB1 */
+    {&gpiob,   NULL, NULL,  2, 0, ADCx, 0}, /* PB2 */
+    {&gpiob,   NULL, NULL,  3, 0, ADCx, 0}, /* PB3 */
+    {&gpiob,   NULL, NULL,  4, 0, ADCx, 0}, /* PB4 */
+    {&gpiob,   NULL, NULL,  5, 0, ADCx, 0}, /* PB5 */
+    {&gpiob, &timer4, NULL,  6, 1, ADCx, 0}, /* PB6 */
+    {&gpiob, &timer4, NULL,  7, 2, ADCx, 0}, /* PB7 */
+    {&gpiob, &timer4, NULL,  8, 3, ADCx, 0}, /* PB8 */
+    {&gpiob, &timer4, NULL,  9, 4, ADCx, 0}, /* PB9 */
+    {&gpiob,   NULL, NULL, 10, 0, ADCx, 0}, /* PB10 */
+    {&gpiob,   NULL, NULL, 11, 0, ADCx, 0}, /* PB11 */
+    {&gpiob,   NULL, NULL, 12, 0, ADCx, 0}, /* PB12 */
+    {&gpiob,   NULL, NULL, 13, 0, ADCx, 0}, /* PB13 */
+    {&gpiob,   NULL, NULL, 14, 0, ADCx, 0}, /* PB14 */
+    {&gpiob,   NULL, NULL, 15, 0, ADCx, 0}, /* PB15 */
+
+    {&gpioc,   NULL, NULL, 13, 0, ADCx, 0}, /* PC13 */
+    {&gpioc,   NULL, NULL, 14, 0, ADCx, 0}, /* PC14 */
+    {&gpioc,   NULL, NULL, 15, 0, ADCx, 0}, /* PC15 */
 
 };
-#pragma GCC diagnostic pop
 
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
     PB0, PA7, PA6, PA3, PA2, PA1, PA0, PB7, PB6, PA10, PA9, PA8
diff --git a/STM32F1/variants/generic_stm32f103c/board.cpp b/STM32F1/variants/generic_stm32f103c/board.cpp
index ac786cf00..7b33ba858 100644
--- a/STM32F1/variants/generic_stm32f103c/board.cpp
+++ b/STM32F1/variants/generic_stm32f103c/board.cpp
@@ -51,50 +51,47 @@ void boardInit(void) {
 }
 
 // Note. See the enum of pin names in board.h
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
 
-    {&gpioa, &timer2, &adc1,  0, 1,    0}, /* PA0 */
-    {&gpioa, &timer2, &adc1,  1, 2,    1}, /* PA1 */
-    {&gpioa, &timer2, &adc1,  2, 3,    2}, /* PA2 */	
-    {&gpioa, &timer2, &adc1,  3, 4,    3}, /* PA3 */
-    {&gpioa,   NULL, &adc1,  4, 0,    4}, /* PA4 */
-    {&gpioa,   NULL, &adc1,  5, 0,    5}, /* PA5 */
-    {&gpioa, &timer3, &adc1,  6, 1,    6}, /* PA6 */
-    {&gpioa, &timer3, &adc1,  7, 2,    7}, /* PA7 */
-    {&gpioa, &timer1, NULL,  8, 1, ADCx}, /* PA8 */	
-    {&gpioa, &timer1, NULL,  9, 2, ADCx}, /* PA9 */	
-    {&gpioa, &timer1, NULL, 10, 3, ADCx}, /* PA10 */
-    {&gpioa, &timer1, NULL, 11, 4, ADCx}, /* PA11 */
-    {&gpioa,   NULL, NULL, 12, 0, ADCx}, /* PA12 */	
-    {&gpioa,   NULL, NULL, 13, 0, ADCx}, /* PA13 */	
-    {&gpioa,   NULL, NULL, 14, 0, ADCx}, /* PA14 */
-    {&gpioa,   NULL, NULL, 15, 0, ADCx}, /* PA15 */
+    {&gpioa, &timer2, &adc1,  0, 1,    0, 0}, /* PA0 */
+    {&gpioa, &timer2, &adc1,  1, 2,    1, 0}, /* PA1 */
+    {&gpioa, &timer2, &adc1,  2, 3,    2, 0}, /* PA2 */
+    {&gpioa, &timer2, &adc1,  3, 4,    3, 0}, /* PA3 */
+    {&gpioa,   NULL, &adc1,  4, 0,    4, 0}, /* PA4 */
+    {&gpioa,   NULL, &adc1,  5, 0,    5, 0}, /* PA5 */
+    {&gpioa, &timer3, &adc1,  6, 1,    6, 0}, /* PA6 */
+    {&gpioa, &timer3, &adc1,  7, 2,    7, 0}, /* PA7 */
+    {&gpioa, &timer1, NULL,  8, 1, ADCx, 0}, /* PA8 */
+    {&gpioa, &timer1, NULL,  9, 2, ADCx, 0}, /* PA9 */
+    {&gpioa, &timer1, NULL, 10, 3, ADCx, 0}, /* PA10 */
+    {&gpioa, &timer1, NULL, 11, 4, ADCx, 0}, /* PA11 */
+    {&gpioa,   NULL, NULL, 12, 0, ADCx, 0}, /* PA12 */
+    {&gpioa,   NULL, NULL, 13, 0, ADCx, 0}, /* PA13 */
+    {&gpioa,   NULL, NULL, 14, 0, ADCx, 0}, /* PA14 */
+    {&gpioa,   NULL, NULL, 15, 0, ADCx, 0}, /* PA15 */
 	
-    {&gpiob, &timer3, &adc1,  0, 3,    8}, /* PB0 */	
-    {&gpiob, &timer3, &adc1,  1, 4,    9}, /* PB1 */
-    {&gpiob,   NULL, NULL,  2, 0, ADCx}, /* PB2 */
-    {&gpiob,   NULL, NULL,  3, 0, ADCx}, /* PB3 */
-    {&gpiob,   NULL, NULL,  4, 0, ADCx}, /* PB4 */
-    {&gpiob,   NULL, NULL,  5, 0, ADCx}, /* PB5 */
-    {&gpiob, &timer4, NULL,  6, 1, ADCx}, /* PB6 */
-    {&gpiob, &timer4, NULL,  7, 2, ADCx}, /* PB7 */	
-    {&gpiob, &timer4, NULL,  8, 3, ADCx}, /* PB8 */	
-    {&gpiob, &timer4, NULL,  9, 4, ADCx}, /* PB9 */	
-    {&gpiob,   NULL, NULL, 10, 0, ADCx}, /* PB10 */	
-    {&gpiob,   NULL, NULL, 11, 0, ADCx}, /* PB11 */
-    {&gpiob,   NULL, NULL, 12, 0, ADCx}, /* PB12 */
-    {&gpiob,   NULL, NULL, 13, 0, ADCx}, /* PB13 */
-    {&gpiob,   NULL, NULL, 14, 0, ADCx}, /* PB14 */
-    {&gpiob,   NULL, NULL, 15, 0, ADCx}, /* PB15 */
-
-    {&gpioc,   NULL, NULL, 13, 0, ADCx}, /* PC13 */	
-    {&gpioc,   NULL, NULL, 14, 0, ADCx}, /* PC14 */
-    {&gpioc,   NULL, NULL, 15, 0, ADCx}, /* PC15 */
+    {&gpiob, &timer3, &adc1,  0, 3,    8, 0}, /* PB0 */
+    {&gpiob, &timer3, &adc1,  1, 4,    9, 0}, /* PB1 */
+    {&gpiob,   NULL, NULL,  2, 0, ADCx, 0}, /* PB2 */
+    {&gpiob,   NULL, NULL,  3, 0, ADCx, 0}, /* PB3 */
+    {&gpiob,   NULL, NULL,  4, 0, ADCx, 0}, /* PB4 */
+    {&gpiob,   NULL, NULL,  5, 0, ADCx, 0}, /* PB5 */
+    {&gpiob, &timer4, NULL,  6, 1, ADCx, 0}, /* PB6 */
+    {&gpiob, &timer4, NULL,  7, 2, ADCx, 0}, /* PB7 */
+    {&gpiob, &timer4, NULL,  8, 3, ADCx, 0}, /* PB8 */
+    {&gpiob, &timer4, NULL,  9, 4, ADCx, 0}, /* PB9 */
+    {&gpiob,   NULL, NULL, 10, 0, ADCx, 0}, /* PB10 */
+    {&gpiob,   NULL, NULL, 11, 0, ADCx, 0}, /* PB11 */
+    {&gpiob,   NULL, NULL, 12, 0, ADCx, 0}, /* PB12 */
+    {&gpiob,   NULL, NULL, 13, 0, ADCx, 0}, /* PB13 */
+    {&gpiob,   NULL, NULL, 14, 0, ADCx, 0}, /* PB14 */
+    {&gpiob,   NULL, NULL, 15, 0, ADCx, 0}, /* PB15 */
+
+    {&gpioc,   NULL, NULL, 13, 0, ADCx, 0}, /* PC13 */
+    {&gpioc,   NULL, NULL, 14, 0, ADCx, 0}, /* PC14 */
+    {&gpioc,   NULL, NULL, 15, 0, ADCx, 0}, /* PC15 */
 };
-#pragma GCC diagnostic pop
 
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
     PB0, PA7, PA6, PA3, PA2, PA1, PA0, PB7, PB6, PA10, PA9, PA8
diff --git a/STM32F1/variants/generic_stm32f103r/board.cpp b/STM32F1/variants/generic_stm32f103r/board.cpp
index e50314e2b..e564425d0 100644
--- a/STM32F1/variants/generic_stm32f103r/board.cpp
+++ b/STM32F1/variants/generic_stm32f103r/board.cpp
@@ -69,8 +69,6 @@ void boardInit(void) {
 // - Timer channel (1 to 4, for PWM), or 0 if none
 // - ADC device, or NULL if none
 // - ADC channel, or ADCx if none
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 /*
     gpio_dev *gpio_device;      GPIO device 
@@ -82,63 +80,62 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 	uint8 pinMode; 				mode specific by pinMode call (Roger Clark added to optimize compatibility with Arduino API
 */
 
-    {&gpioa, &timer2, &adc1,  0, 1,    0}, /* PA0 */
-    {&gpioa, &timer2, &adc1,  1, 2,    1}, /* PA1 */
-	{&gpioa, &timer2, &adc1,  2, 3,    2}, /* PA2 */
-    {&gpioa, &timer2, &adc1,  3, 4,    3}, /* PA3 */
-	{&gpioa,   NULL, &adc1,  4, 0,    4}, /* PA4 */	
-    {&gpioa,   NULL, &adc1,  5, 0,    5}, /* PA5 */
-    {&gpioa, &timer3, &adc1,  6, 1,    6}, /* PA6 */
-    {&gpioa, &timer3, &adc1,  7, 2,    7}, /* PA7 */
-    {&gpioa, &timer1, NULL,  8, 1, ADCx}, /* PA8 */
-    {&gpioa, &timer1, NULL,  9, 2, ADCx}, /* PA9 */
-    {&gpioa, &timer1, NULL, 10, 3, ADCx}, /* PA10 */
-    {&gpioa,   NULL, NULL, 11, 0, ADCx}, /* PA11 */
-    {&gpioa,   NULL, NULL, 12, 0, ADCx}, /* PA12 */	
-    {&gpioa,   NULL, NULL, 13, 0, ADCx}, /* PA13 */
-    {&gpioa,   NULL, NULL, 14, 0, ADCx}, /* PA14 */
-    {&gpioa,   NULL, NULL, 15, 0, ADCx}, /* PA15 */
+    {&gpioa, &timer2, &adc1,  0, 1,    0, 0}, /* PA0 */
+    {&gpioa, &timer2, &adc1,  1, 2,    1, 0}, /* PA1 */
+	{&gpioa, &timer2, &adc1,  2, 3,    2, 0}, /* PA2 */
+    {&gpioa, &timer2, &adc1,  3, 4,    3, 0}, /* PA3 */
+	{&gpioa,   NULL, &adc1,  4, 0,    4, 0}, /* PA4 */
+    {&gpioa,   NULL, &adc1,  5, 0,    5, 0}, /* PA5 */
+    {&gpioa, &timer3, &adc1,  6, 1,    6, 0}, /* PA6 */
+    {&gpioa, &timer3, &adc1,  7, 2,    7, 0}, /* PA7 */
+    {&gpioa, &timer1, NULL,  8, 1, ADCx, 0}, /* PA8 */
+    {&gpioa, &timer1, NULL,  9, 2, ADCx, 0}, /* PA9 */
+    {&gpioa, &timer1, NULL, 10, 3, ADCx, 0}, /* PA10 */
+    {&gpioa,   NULL, NULL, 11, 0, ADCx, 0}, /* PA11 */
+    {&gpioa,   NULL, NULL, 12, 0, ADCx, 0}, /* PA12 */
+    {&gpioa,   NULL, NULL, 13, 0, ADCx, 0}, /* PA13 */
+    {&gpioa,   NULL, NULL, 14, 0, ADCx, 0}, /* PA14 */
+    {&gpioa,   NULL, NULL, 15, 0, ADCx, 0}, /* PA15 */
 	
-	{&gpiob, &timer3, &adc1,  0, 3,    8}, /* PB0 */
-	{&gpiob, &timer3, &adc1,  1, 4,    9}, /* PB1 */
-	{&gpiob,   NULL, NULL,  2, 0, ADCx}, /* PB2  */	
-	{&gpiob,   NULL, NULL,  3, 0, ADCx}, /* PB3  */
-    {&gpiob,   NULL, NULL,  4, 0, ADCx}, /* PB4  */
-    {&gpiob,   NULL, NULL,  5, 0, ADCx}, /* PB5 */
-    {&gpiob, &timer4, NULL,  6, 1, ADCx}, /* PB6 */
-    {&gpiob, &timer4, NULL,  7, 2, ADCx}, /* PB7 */
-    {&gpiob, &timer4, NULL,  8, 3, ADCx}, /* PB8 */
-	{&gpiob,   NULL, NULL,  9, 0, ADCx}, /* PB9 */
-    {&gpiob,   NULL, NULL, 10, 0, ADCx}, /* PB10 */
-    {&gpiob,   NULL, NULL, 11, 0, ADCx}, /* PB11 */
-    {&gpiob,   NULL, NULL, 12, 0, ADCx}, /* PB12 */
-    {&gpiob,   NULL, NULL, 13, 0, ADCx}, /* PB13 */
-    {&gpiob,   NULL, NULL, 14, 0, ADCx}, /* PB14 */
-    {&gpiob,   NULL, NULL, 15, 0, ADCx}, /* PB15 */
-
-
-    {&gpioc,   NULL, &adc1,  0, 0,   10}, /* PC0 */
-    {&gpioc,   NULL, &adc1,  1, 0,   11}, /* PC1 */
-    {&gpioc,   NULL, &adc1,  2, 0,   12}, /* PC2 */
-    {&gpioc,   NULL, &adc1,  3, 0,   13}, /* PC3 */
-    {&gpioc,   NULL, &adc1,  4, 0,   14}, /* PC4 */
-    {&gpioc,   NULL, &adc1,  5, 0,   15}, /* PC5 */
-    {&gpioc, &timer8, NULL,  6, 1, ADCx}, /* PC6 */	
-	{&gpioc, &timer8, NULL,  7, 2, ADCx}, /* PC7 */
-    {&gpioc, &timer8, NULL,  8, 3, ADCx}, /* PC8 */
-    {&gpioc, &timer8, NULL,  9, 4, ADCx}, /* PC9 */
-    {&gpioc,   NULL, NULL, 10, 0, ADCx}, /* PC10 UART4_TX/SDIO_D2 */
-    {&gpioc,   NULL, NULL, 11, 0, ADCx}, /* PC11 UART4_RX/SDIO_D3 */
-    {&gpioc,   NULL, NULL, 12, 0, ADCx}, /* PC12 UART5_TX/SDIO_CK */	
-    {&gpioc,   NULL, NULL, 13, 0, ADCx}, /* PC13 TAMPER-RTC */
-    {&gpioc,   NULL, NULL, 14, 0, ADCx}, /* PC14 OSC32_IN */
-    {&gpioc,   NULL, NULL, 15, 0, ADCx}, /* PC15 OSC32_OUT */
-
-	{&gpiod,   NULL, NULL,   0, 0, ADCx} , /* PD0 OSC_IN */
-	{&gpiod,   NULL, NULL,   1, 0, ADCx} , /* PD1  OSC_OUT */
-	{&gpiod,   NULL, NULL,   2, 0, ADCx} , /* PD2  TIM3_ETR/UART5_RX SDIO_CMD */
+	{&gpiob, &timer3, &adc1,  0, 3,    8, 0}, /* PB0 */
+	{&gpiob, &timer3, &adc1,  1, 4,    9, 0}, /* PB1 */
+	{&gpiob,   NULL, NULL,  2, 0, ADCx, 0}, /* PB2  */
+	{&gpiob,   NULL, NULL,  3, 0, ADCx, 0}, /* PB3  */
+    {&gpiob,   NULL, NULL,  4, 0, ADCx, 0}, /* PB4  */
+    {&gpiob,   NULL, NULL,  5, 0, ADCx, 0}, /* PB5 */
+    {&gpiob, &timer4, NULL,  6, 1, ADCx, 0}, /* PB6 */
+    {&gpiob, &timer4, NULL,  7, 2, ADCx, 0}, /* PB7 */
+    {&gpiob, &timer4, NULL,  8, 3, ADCx, 0}, /* PB8 */
+	{&gpiob,   NULL, NULL,  9, 0, ADCx, 0}, /* PB9 */
+    {&gpiob,   NULL, NULL, 10, 0, ADCx, 0}, /* PB10 */
+    {&gpiob,   NULL, NULL, 11, 0, ADCx, 0}, /* PB11 */
+    {&gpiob,   NULL, NULL, 12, 0, ADCx, 0}, /* PB12 */
+    {&gpiob,   NULL, NULL, 13, 0, ADCx, 0}, /* PB13 */
+    {&gpiob,   NULL, NULL, 14, 0, ADCx, 0}, /* PB14 */
+    {&gpiob,   NULL, NULL, 15, 0, ADCx, 0}, /* PB15 */
+
+
+    {&gpioc,   NULL, &adc1,  0, 0,   10, 0}, /* PC0 */
+    {&gpioc,   NULL, &adc1,  1, 0,   11, 0}, /* PC1 */
+    {&gpioc,   NULL, &adc1,  2, 0,   12, 0}, /* PC2 */
+    {&gpioc,   NULL, &adc1,  3, 0,   13, 0}, /* PC3 */
+    {&gpioc,   NULL, &adc1,  4, 0,   14, 0}, /* PC4 */
+    {&gpioc,   NULL, &adc1,  5, 0,   15, 0}, /* PC5 */
+    {&gpioc, &timer8, NULL,  6, 1, ADCx, 0}, /* PC6 */
+	{&gpioc, &timer8, NULL,  7, 2, ADCx, 0}, /* PC7 */
+    {&gpioc, &timer8, NULL,  8, 3, ADCx, 0}, /* PC8 */
+    {&gpioc, &timer8, NULL,  9, 4, ADCx, 0}, /* PC9 */
+    {&gpioc,   NULL, NULL, 10, 0, ADCx, 0}, /* PC10 UART4_TX/SDIO_D2 */
+    {&gpioc,   NULL, NULL, 11, 0, ADCx, 0}, /* PC11 UART4_RX/SDIO_D3 */
+    {&gpioc,   NULL, NULL, 12, 0, ADCx, 0}, /* PC12 UART5_TX/SDIO_CK */
+    {&gpioc,   NULL, NULL, 13, 0, ADCx, 0}, /* PC13 TAMPER-RTC */
+    {&gpioc,   NULL, NULL, 14, 0, ADCx, 0}, /* PC14 OSC32_IN */
+    {&gpioc,   NULL, NULL, 15, 0, ADCx, 0}, /* PC15 OSC32_OUT */
+
+	{&gpiod,   NULL, NULL,   0, 0, ADCx, 0} , /* PD0 OSC_IN */
+	{&gpiod,   NULL, NULL,   1, 0, ADCx, 0} , /* PD1  OSC_OUT */
+	{&gpiod,   NULL, NULL,   2, 0, ADCx, 0} , /* PD2  TIM3_ETR/UART5_RX SDIO_CMD */
 };
-#pragma GCC diagnostic pop
 
 /*  Basically everything that is defined as having a timer us PWM */
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
diff --git a/STM32F1/variants/generic_stm32f103r8/board.cpp b/STM32F1/variants/generic_stm32f103r8/board.cpp
index 1987651b7..f667d2fe7 100644
--- a/STM32F1/variants/generic_stm32f103r8/board.cpp
+++ b/STM32F1/variants/generic_stm32f103r8/board.cpp
@@ -51,68 +51,65 @@ void boardInit(void) {
 }
 
 // Note. See the enum of pin names in board.h
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
 
-    {&gpioa, &timer2, &adc1,  0, 1,    0}, /* PA0 */
-    {&gpioa, &timer2, &adc1,  1, 2,    1}, /* PA1 */
-    {&gpioa, &timer2, &adc1,  2, 3,    2}, /* PA2 */	
-    {&gpioa, &timer2, &adc1,  3, 4,    3}, /* PA3 */
-    {&gpioa,   NULL, &adc1,  4, 0,    4}, /* PA4 */
-    {&gpioa,   NULL, &adc1,  5, 0,    5}, /* PA5 */
-    {&gpioa, &timer3, &adc1,  6, 1,    6}, /* PA6 */
-    {&gpioa, &timer3, &adc1,  7, 2,    7}, /* PA7 */
-    {&gpioa, &timer1, NULL,  8, 1, ADCx}, /* PA8 */	
-    {&gpioa, &timer1, NULL,  9, 2, ADCx}, /* PA9 */	
-    {&gpioa, &timer1, NULL, 10, 3, ADCx}, /* PA10 */
-    {&gpioa, &timer1, NULL, 11, 4, ADCx}, /* PA11 */
-    {&gpioa,   NULL, NULL, 12, 0, ADCx}, /* PA12 */	
-    {&gpioa,   NULL, NULL, 13, 0, ADCx}, /* PA13 */	
-    {&gpioa,   NULL, NULL, 14, 0, ADCx}, /* PA14 */
-    {&gpioa,   NULL, NULL, 15, 0, ADCx}, /* PA15 */
+    {&gpioa, &timer2, &adc1,  0, 1,    0, 0}, /* PA0 */
+    {&gpioa, &timer2, &adc1,  1, 2,    1, 0}, /* PA1 */
+    {&gpioa, &timer2, &adc1,  2, 3,    2, 0}, /* PA2 */
+    {&gpioa, &timer2, &adc1,  3, 4,    3, 0}, /* PA3 */
+    {&gpioa,   NULL, &adc1,  4, 0,    4, 0}, /* PA4 */
+    {&gpioa,   NULL, &adc1,  5, 0,    5, 0}, /* PA5 */
+    {&gpioa, &timer3, &adc1,  6, 1,    6, 0}, /* PA6 */
+    {&gpioa, &timer3, &adc1,  7, 2,    7, 0}, /* PA7 */
+    {&gpioa, &timer1, NULL,  8, 1, ADCx, 0}, /* PA8 */
+    {&gpioa, &timer1, NULL,  9, 2, ADCx, 0}, /* PA9 */
+    {&gpioa, &timer1, NULL, 10, 3, ADCx, 0}, /* PA10 */
+    {&gpioa, &timer1, NULL, 11, 4, ADCx, 0}, /* PA11 */
+    {&gpioa,   NULL, NULL, 12, 0, ADCx, 0}, /* PA12 */
+    {&gpioa,   NULL, NULL, 13, 0, ADCx, 0}, /* PA13 */
+    {&gpioa,   NULL, NULL, 14, 0, ADCx, 0}, /* PA14 */
+    {&gpioa,   NULL, NULL, 15, 0, ADCx, 0}, /* PA15 */
 	
-    {&gpiob, &timer3, &adc1,  0, 3,    8}, /* PB0 */	
-    {&gpiob, &timer3, &adc1,  1, 4,    9}, /* PB1 */
-    {&gpiob,   NULL, NULL,  2, 0, ADCx}, /* PB2 */
-    {&gpiob,   NULL, NULL,  3, 0, ADCx}, /* PB3 */
-    {&gpiob,   NULL, NULL,  4, 0, ADCx}, /* PB4 */
-    {&gpiob,   NULL, NULL,  5, 0, ADCx}, /* PB5 */
-    {&gpiob, &timer4, NULL,  6, 1, ADCx}, /* PB6 */
-    {&gpiob, &timer4, NULL,  7, 2, ADCx}, /* PB7 */	
-    {&gpiob, &timer4, NULL,  8, 3, ADCx}, /* PB8 */	
-    {&gpiob, &timer4, NULL,  9, 4, ADCx}, /* PB9 */	
-    {&gpiob,   NULL, NULL, 10, 0, ADCx}, /* PB10 */	
-    {&gpiob,   NULL, NULL, 11, 0, ADCx}, /* PB11 */
-    {&gpiob,   NULL, NULL, 12, 0, ADCx}, /* PB12 */
-    {&gpiob,   NULL, NULL, 13, 0, ADCx}, /* PB13 */
-    {&gpiob,   NULL, NULL, 14, 0, ADCx}, /* PB14 */
-    {&gpiob,   NULL, NULL, 15, 0, ADCx}, /* PB15 */
+    {&gpiob, &timer3, &adc1,  0, 3,    8, 0}, /* PB0 */
+    {&gpiob, &timer3, &adc1,  1, 4,    9, 0}, /* PB1 */
+    {&gpiob,   NULL, NULL,  2, 0, ADCx, 0}, /* PB2 */
+    {&gpiob,   NULL, NULL,  3, 0, ADCx, 0}, /* PB3 */
+    {&gpiob,   NULL, NULL,  4, 0, ADCx, 0}, /* PB4 */
+    {&gpiob,   NULL, NULL,  5, 0, ADCx, 0}, /* PB5 */
+    {&gpiob, &timer4, NULL,  6, 1, ADCx, 0}, /* PB6 */
+    {&gpiob, &timer4, NULL,  7, 2, ADCx, 0}, /* PB7 */
+    {&gpiob, &timer4, NULL,  8, 3, ADCx, 0}, /* PB8 */
+    {&gpiob, &timer4, NULL,  9, 4, ADCx, 0}, /* PB9 */
+    {&gpiob,   NULL, NULL, 10, 0, ADCx, 0}, /* PB10 */
+    {&gpiob,   NULL, NULL, 11, 0, ADCx, 0}, /* PB11 */
+    {&gpiob,   NULL, NULL, 12, 0, ADCx, 0}, /* PB12 */
+    {&gpiob,   NULL, NULL, 13, 0, ADCx, 0}, /* PB13 */
+    {&gpiob,   NULL, NULL, 14, 0, ADCx, 0}, /* PB14 */
+    {&gpiob,   NULL, NULL, 15, 0, ADCx, 0}, /* PB15 */
 
 /* Andy Hull - the R8 is similar to the C8 but exposes more GPIO as follows */
-    {&gpioc,   NULL, &adc1, 0, 0, 10},  /* PC0 */
-    {&gpioc,   NULL, &adc1, 1, 0, 11},  /* PC1 */
-    {&gpioc,   NULL, &adc1, 2, 0, 12},  /* PC2 */
-    {&gpioc,   NULL, &adc1, 3, 0, 13},  /* PC3 */
-    {&gpioc,   NULL, &adc1, 4, 0, 14},  /* PC4 */
-    {&gpioc,   NULL, &adc1, 5, 0, 15},  /* PC5 */
-
-    {&gpioc,   NULL, NULL, 6, 0, ADCx},  /* PC6 */
-    {&gpioc,   NULL, NULL, 7, 0, ADCx},  /* PC7 */
-    {&gpioc,   NULL, NULL, 8, 0, ADCx},  /* PC8 */
-    {&gpioc,   NULL, NULL, 9, 0, ADCx},  /* PC9 */
-
-    {&gpioc,   NULL, NULL, 10, 0, ADCx}, /* PC10 */
-    {&gpioc,   NULL, NULL, 11, 0, ADCx}, /* PC11 */
-    {&gpioc,   NULL, NULL, 12, 0, ADCx}, /* PC12 */
-    {&gpioc,   NULL, NULL, 13, 0, ADCx}, /* PC13 */	
-    {&gpioc,   NULL, NULL, 14, 0, ADCx}, /* PC14 */
-    {&gpioc,   NULL, NULL, 15, 0, ADCx}, /* PC15 */
-
-    {&gpiod,   NULL, NULL, 2, 0, ADCx},  /* PD2 */
+    {&gpioc,   NULL, &adc1, 0, 0, 10, 0},  /* PC0 */
+    {&gpioc,   NULL, &adc1, 1, 0, 11, 0},  /* PC1 */
+    {&gpioc,   NULL, &adc1, 2, 0, 12, 0},  /* PC2 */
+    {&gpioc,   NULL, &adc1, 3, 0, 13, 0},  /* PC3 */
+    {&gpioc,   NULL, &adc1, 4, 0, 14, 0},  /* PC4 */
+    {&gpioc,   NULL, &adc1, 5, 0, 15, 0},  /* PC5 */
+
+    {&gpioc,   NULL, NULL, 6, 0, ADCx, 0},  /* PC6 */
+    {&gpioc,   NULL, NULL, 7, 0, ADCx, 0},  /* PC7 */
+    {&gpioc,   NULL, NULL, 8, 0, ADCx, 0},  /* PC8 */
+    {&gpioc,   NULL, NULL, 9, 0, ADCx, 0},  /* PC9 */
+
+    {&gpioc,   NULL, NULL, 10, 0, ADCx, 0}, /* PC10 */
+    {&gpioc,   NULL, NULL, 11, 0, ADCx, 0}, /* PC11 */
+    {&gpioc,   NULL, NULL, 12, 0, ADCx, 0}, /* PC12 */
+    {&gpioc,   NULL, NULL, 13, 0, ADCx, 0}, /* PC13 */
+    {&gpioc,   NULL, NULL, 14, 0, ADCx, 0}, /* PC14 */
+    {&gpioc,   NULL, NULL, 15, 0, ADCx, 0}, /* PC15 */
+
+    {&gpiod,   NULL, NULL, 2, 0, ADCx, 0},  /* PD2 */
 };
-#pragma GCC diagnostic pop
 
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
     PB0, PA7, PA6, PA3, PA2, PA1, PA0, PB7, PB6, PA10, PA9, PA8, PC6, PC7, PC8, PC9
diff --git a/STM32F1/variants/generic_stm32f103t/board.cpp b/STM32F1/variants/generic_stm32f103t/board.cpp
index 003d225b3..85c252c4d 100644
--- a/STM32F1/variants/generic_stm32f103t/board.cpp
+++ b/STM32F1/variants/generic_stm32f103t/board.cpp
@@ -51,38 +51,35 @@ void boardInit(void) {
 }
 
 // Note. See the enum of pin names in board.h
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
 
-    {&gpioa, &timer2, &adc1,  0, 1,    0}, /* PA0 */
-    {&gpioa, &timer2, &adc1,  1, 2,    1}, /* PA1 */
-    {&gpioa, &timer2, &adc1,  2, 3,    2}, /* PA2 */	
-    {&gpioa, &timer2, &adc1,  3, 4,    3}, /* PA3 */
-    {&gpioa,   NULL, &adc1,  4, 0,    4}, /* PA4 */
-    {&gpioa,   NULL, &adc1,  5, 0,    5}, /* PA5 */
-    {&gpioa, &timer3, &adc1,  6, 1,    6}, /* PA6 */
-    {&gpioa, &timer3, &adc1,  7, 2,    7}, /* PA7 */
-    {&gpioa, &timer1, NULL,  8, 1, ADCx}, /* PA8 */	
-    {&gpioa, &timer1, NULL,  9, 2, ADCx}, /* PA9 */	
-    {&gpioa, &timer1, NULL, 10, 3, ADCx}, /* PA10 */
-    {&gpioa, &timer1, NULL, 11, 4, ADCx}, /* PA11 */
-    {&gpioa,   NULL, NULL, 12, 0, ADCx}, /* PA12 */	
-    {&gpioa,   NULL, NULL, 13, 0, ADCx}, /* PA13 */	
-    {&gpioa,   NULL, NULL, 14, 0, ADCx}, /* PA14 */
-    {&gpioa,   NULL, NULL, 15, 0, ADCx}, /* PA15 */
+    {&gpioa, &timer2, &adc1,  0, 1,    0, 0}, /* PA0 */
+    {&gpioa, &timer2, &adc1,  1, 2,    1, 0}, /* PA1 */
+    {&gpioa, &timer2, &adc1,  2, 3,    2, 0}, /* PA2 */
+    {&gpioa, &timer2, &adc1,  3, 4,    3, 0}, /* PA3 */
+    {&gpioa,   NULL, &adc1,  4, 0,    4, 0}, /* PA4 */
+    {&gpioa,   NULL, &adc1,  5, 0,    5, 0}, /* PA5 */
+    {&gpioa, &timer3, &adc1,  6, 1,    6, 0}, /* PA6 */
+    {&gpioa, &timer3, &adc1,  7, 2,    7, 0}, /* PA7 */
+    {&gpioa, &timer1, NULL,  8, 1, ADCx, 0}, /* PA8 */
+    {&gpioa, &timer1, NULL,  9, 2, ADCx, 0}, /* PA9 */
+    {&gpioa, &timer1, NULL, 10, 3, ADCx, 0}, /* PA10 */
+    {&gpioa, &timer1, NULL, 11, 4, ADCx, 0}, /* PA11 */
+    {&gpioa,   NULL, NULL, 12, 0, ADCx, 0}, /* PA12 */
+    {&gpioa,   NULL, NULL, 13, 0, ADCx, 0}, /* PA13 */
+    {&gpioa,   NULL, NULL, 14, 0, ADCx, 0}, /* PA14 */
+    {&gpioa,   NULL, NULL, 15, 0, ADCx, 0}, /* PA15 */
 	
-    {&gpiob, &timer3, &adc1,  0, 3,    8}, /* PB0 */	
-    {&gpiob, &timer3, &adc1,  1, 4,    9}, /* PB1 */
-    {&gpiob,   NULL, NULL,  2, 0, ADCx}, /* PB2 */
-    {&gpiob,   NULL, NULL,  3, 0, ADCx}, /* PB3 */
-    {&gpiob,   NULL, NULL,  4, 0, ADCx}, /* PB4 */
-    {&gpiob,   NULL, NULL,  5, 0, ADCx}, /* PB5 */
-    {&gpiob, &timer4, NULL,  6, 1, ADCx}, /* PB6 */
-    {&gpiob, &timer4, NULL,  7, 2, ADCx}, /* PB7 */	
+    {&gpiob, &timer3, &adc1,  0, 3,    8, 0}, /* PB0 */
+    {&gpiob, &timer3, &adc1,  1, 4,    9, 0}, /* PB1 */
+    {&gpiob,   NULL, NULL,  2, 0, ADCx, 0}, /* PB2 */
+    {&gpiob,   NULL, NULL,  3, 0, ADCx, 0}, /* PB3 */
+    {&gpiob,   NULL, NULL,  4, 0, ADCx, 0}, /* PB4 */
+    {&gpiob,   NULL, NULL,  5, 0, ADCx, 0}, /* PB5 */
+    {&gpiob, &timer4, NULL,  6, 1, ADCx, 0}, /* PB6 */
+    {&gpiob, &timer4, NULL,  7, 2, ADCx, 0}, /* PB7 */
 };
-#pragma GCC diagnostic pop
 
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
     PB0, PA7, PA6, PA3, PA2, PA1, PA0, PB7, PB6, PA10, PA9, PA8
diff --git a/STM32F1/variants/generic_stm32f103v/board.cpp b/STM32F1/variants/generic_stm32f103v/board.cpp
index 8b241694c..a6b31655e 100644
--- a/STM32F1/variants/generic_stm32f103v/board.cpp
+++ b/STM32F1/variants/generic_stm32f103v/board.cpp
@@ -68,8 +68,6 @@ void boardInit(void) {
 // - Timer channel (1 to 4, for PWM), or 0 if none
 // - ADC device, or NULL if none
 // - ADC channel, or ADCx if none
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 /*
     gpio_dev *gpio_device;      GPIO device 
@@ -80,94 +78,93 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
     uint8 adc_channel;          Pin ADC channel, or ADCx if none. 
 */
 
-    {&gpioa, &timer2, &adc1,  0, 1,    0}, /* PA0 */
-    {&gpioa, &timer2, &adc1,  1, 2,    1}, /* PA1 */
-	{&gpioa, &timer2, &adc1,  2, 3,    2}, /* PA2 */
-    {&gpioa, &timer2, &adc1,  3, 4,    3}, /* PA3 */
-	{&gpioa,   NULL, &adc1,  4, 0,    4}, /* PA4 */	
-    {&gpioa,   NULL, &adc1,  5, 0,    5}, /* PA5 */
-    {&gpioa, &timer3, &adc1,  6, 1,    6}, /* PA6 */
-    {&gpioa, &timer3, &adc1,  7, 2,    7}, /* PA7 */
-    {&gpioa, &timer1, NULL,  8, 1, ADCx}, /* PA8 */
-    {&gpioa, &timer1, NULL,  9, 2, ADCx}, /* PA9 */
-    {&gpioa, &timer1, NULL, 10, 3, ADCx}, /* PA10 */
-    {&gpioa,   NULL, NULL, 11, 0, ADCx}, /* PA11 */ //Could have &timer1_CH4, but is also CAN_RX and USBDM 
-    {&gpioa,   NULL, NULL, 12, 0, ADCx}, /* PA12 */ //Could have &timer1_ETR, but is also CAN_TX and USBDP
-    {&gpioa,   NULL, NULL, 13, 0, ADCx}, /* PA13 */
-    {&gpioa,   NULL, NULL, 14, 0, ADCx}, /* PA14 */
-    {&gpioa,   NULL, NULL, 15, 0, ADCx}, /* PA15 */ //SPI3_NSS 
+    {&gpioa, &timer2, &adc1,  0, 1,    0, 0}, /* PA0 */
+    {&gpioa, &timer2, &adc1,  1, 2,    1, 0}, /* PA1 */
+	{&gpioa, &timer2, &adc1,  2, 3,    2, 0}, /* PA2 */
+    {&gpioa, &timer2, &adc1,  3, 4,    3, 0}, /* PA3 */
+	{&gpioa,   NULL, &adc1,  4, 0,    4, 0}, /* PA4 */
+    {&gpioa,   NULL, &adc1,  5, 0,    5, 0}, /* PA5 */
+    {&gpioa, &timer3, &adc1,  6, 1,    6, 0}, /* PA6 */
+    {&gpioa, &timer3, &adc1,  7, 2,    7, 0}, /* PA7 */
+    {&gpioa, &timer1, NULL,  8, 1, ADCx, 0}, /* PA8 */
+    {&gpioa, &timer1, NULL,  9, 2, ADCx, 0}, /* PA9 */
+    {&gpioa, &timer1, NULL, 10, 3, ADCx, 0}, /* PA10 */
+    {&gpioa,   NULL, NULL, 11, 0, ADCx, 0}, /* PA11 */ //Could have &timer1_CH4, but is also CAN_RX and USBDM
+    {&gpioa,   NULL, NULL, 12, 0, ADCx, 0}, /* PA12 */ //Could have &timer1_ETR, but is also CAN_TX and USBDP
+    {&gpioa,   NULL, NULL, 13, 0, ADCx, 0}, /* PA13 */
+    {&gpioa,   NULL, NULL, 14, 0, ADCx, 0}, /* PA14 */
+    {&gpioa,   NULL, NULL, 15, 0, ADCx, 0}, /* PA15 */ //SPI3_NSS
 	
-	{&gpiob, &timer3, &adc1,  0, 3,    8}, /* PB0 */ 
-	{&gpiob, &timer3, &adc1,  1, 4,    9}, /* PB1 */
+	{&gpiob, &timer3, &adc1,  0, 3,    8, 0}, /* PB0 */
+	{&gpiob, &timer3, &adc1,  1, 4,    9, 0}, /* PB1 */
 	/* NOTE PB2 is not included as its Boot 1 */
-	{&gpiob,   NULL, NULL,  3, 0, ADCx}, /* PB3  */ //JTDO, SPI3_SCK / I2S3_CK/
-    {&gpiob,   NULL, NULL,  4, 0, ADCx}, /* PB4  */ //NJTRST, SPI3_MISO
-    {&gpiob,   NULL, NULL,  5, 0, ADCx}, /* PB5 */ //I2C1_SMBA/ SPI3_MOSI
-    {&gpiob, &timer4, NULL,  6, 1, ADCx}, /* PB6 */ //I2C1_SCL(9)
-    {&gpiob, &timer4, NULL,  7, 2, ADCx}, /* PB7 */ //I2C1_SDA(9) / FSMC_NADV
-    {&gpiob, &timer4, NULL,  8, 3, ADCx}, /* PB8 */ //SDIO_D4
-	{&gpiob, &timer4, NULL,  9, 4, ADCx}, /* PB9 */ //SDIO_D5
-    {&gpiob,   NULL, NULL, 10, 0, ADCx}, /* PB10 */ //I2C2_SCL/USART3_TX
-    {&gpiob,   NULL, NULL, 11, 0, ADCx}, /* PB11 */ //I2C2_SDA/USART3_RX
-    {&gpiob,   NULL, NULL, 12, 0, ADCx}, /* PB12 */ //SPI2_NSS/I2S2_WS/I2C2_SMBA/USART3_CK
-    {&gpiob,   NULL, NULL, 13, 0, ADCx}, /* PB13 */ //SPI2_SCK/I2S2_CK/USART3_CTS
-    {&gpiob,   NULL, NULL, 14, 0, ADCx}, /* PB14 */ //SPI2_MISO/TIM1_CH2N/USART3_RTS
-    {&gpiob,   NULL, NULL, 15, 0, ADCx}, /* PB15 */ //SPI2_MOSI/I2S2_SD
-
-
-    {&gpioc,   NULL, &adc1,  0, 0,   10}, /* PC0 */
-    {&gpioc,   NULL, &adc1,  1, 0,   11}, /* PC1 */
-    {&gpioc,   NULL, &adc1,  2, 0,   12}, /* PC2 */
-    {&gpioc,   NULL, &adc1,  3, 0,   13}, /* PC3 */
-    {&gpioc,   NULL, &adc1,  4, 0,   14}, /* PC4 */
-    {&gpioc,   NULL, &adc1,  5, 0,   15}, /* PC5 */
-    {&gpioc, &timer8, NULL,  6, 1, ADCx}, /* PC6 I2S2_MCK/SDIO_D6*/	
-	{&gpioc, &timer8, NULL,  7, 2, ADCx}, /* PC7 I2S3_MCK/SDIO_D7*/
-    {&gpioc, &timer8, NULL,  8, 3, ADCx}, /* PC8 SDIO_D0*/
-    {&gpioc, &timer8, NULL,  9, 4, ADCx}, /* PC9 SDIO_D1*/
-    {&gpioc,   NULL, NULL, 10, 0, ADCx}, /* PC10 UART4_TX/SDIO_D2 */
-    {&gpioc,   NULL, NULL, 11, 0, ADCx}, /* PC11 UART4_RX/SDIO_D3 */
-    {&gpioc,   NULL, NULL, 12, 0, ADCx}, /* PC12 UART5_TX/SDIO_CK */	
-    {&gpioc,   NULL, NULL, 13, 0, ADCx}, /* PC13 TAMPER-RTC/ Limited output*/
-    {&gpioc,   NULL, NULL, 14, 0, ADCx}, /* PC14 OSC32_IN/ Limited output*/
-    {&gpioc,   NULL, NULL, 15, 0, ADCx}, /* PC15 OSC32_OUT/ Limited output*/
-
-	{&gpiod,   NULL, NULL,   0, 0, ADCx} , /* PD0 OSC_IN */
-	{&gpiod,   NULL, NULL,   1, 0, ADCx} , /* PD1  OSC_OUT */
-	{&gpiod,   NULL, NULL,   2, 0, ADCx} , /* PD2  TIM3_ETR/UART5_RX SDIO_CMD */
-	{&gpiod,   NULL, NULL,   3, 0, ADCx} , /* PD3  FSMC_CLK */
-	{&gpiod,   NULL, NULL,   4, 0, ADCx} , /* PD4  FSMC_NOE */
-	{&gpiod,   NULL, NULL,   5, 0, ADCx} , /* PD5  FSMC_NWE */
-	{&gpiod,   NULL, NULL,   6, 0, ADCx} , /* PD6  FSMC_NWAIT */
-	{&gpiod,   NULL, NULL,   7, 0, ADCx} , /* PD7  FSMC_NE1/FSMC_NCE2 */
-	{&gpiod,   NULL, NULL,   8, 0, ADCx} , /* PD8  FSMC_D13 */
-	{&gpiod,   NULL, NULL,   9, 0, ADCx} , /* PD9  FSMC_D14 */
-	{&gpiod,   NULL, NULL,  10, 0, ADCx} , /* PD10  FSMC_D15 */
-	{&gpiod,   NULL, NULL,  11, 0, ADCx} , /* PD11  FSMC_A16 */
-	{&gpiod,   NULL, NULL,  12, 0, ADCx} , /* PD12  FSMC_A17 */
-	{&gpiod,   NULL, NULL,  13, 0, ADCx} , /* PD13  FSMC_A18 */	
-	{&gpiod,   NULL, NULL,  14, 0, ADCx} , /* PD14  FSMC_D0 */
-	{&gpiod,   NULL, NULL,  15, 0, ADCx} , /* PD15  FSMC_D1 */
+	{&gpiob,   NULL, NULL,  3, 0, ADCx, 0}, /* PB3  */ //JTDO, SPI3_SCK / I2S3_CK/
+    {&gpiob,   NULL, NULL,  4, 0, ADCx, 0}, /* PB4  */ //NJTRST, SPI3_MISO
+    {&gpiob,   NULL, NULL,  5, 0, ADCx, 0}, /* PB5 */ //I2C1_SMBA/ SPI3_MOSI
+    {&gpiob, &timer4, NULL,  6, 1, ADCx, 0}, /* PB6 */ //I2C1_SCL(9)
+    {&gpiob, &timer4, NULL,  7, 2, ADCx, 0}, /* PB7 */ //I2C1_SDA(9) / FSMC_NADV
+    {&gpiob, &timer4, NULL,  8, 3, ADCx, 0}, /* PB8 */ //SDIO_D4
+	{&gpiob, &timer4, NULL,  9, 4, ADCx, 0}, /* PB9 */ //SDIO_D5
+    {&gpiob,   NULL, NULL, 10, 0, ADCx, 0}, /* PB10 */ //I2C2_SCL/USART3_TX
+    {&gpiob,   NULL, NULL, 11, 0, ADCx, 0}, /* PB11 */ //I2C2_SDA/USART3_RX
+    {&gpiob,   NULL, NULL, 12, 0, ADCx, 0}, /* PB12 */ //SPI2_NSS/I2S2_WS/I2C2_SMBA/USART3_CK
+    {&gpiob,   NULL, NULL, 13, 0, ADCx, 0}, /* PB13 */ //SPI2_SCK/I2S2_CK/USART3_CTS
+    {&gpiob,   NULL, NULL, 14, 0, ADCx, 0}, /* PB14 */ //SPI2_MISO/TIM1_CH2N/USART3_RTS
+    {&gpiob,   NULL, NULL, 15, 0, ADCx, 0}, /* PB15 */ //SPI2_MOSI/I2S2_SD
+
+
+    {&gpioc,   NULL, &adc1,  0, 0,   10, 0}, /* PC0 */
+    {&gpioc,   NULL, &adc1,  1, 0,   11, 0}, /* PC1 */
+    {&gpioc,   NULL, &adc1,  2, 0,   12, 0}, /* PC2 */
+    {&gpioc,   NULL, &adc1,  3, 0,   13, 0}, /* PC3 */
+    {&gpioc,   NULL, &adc1,  4, 0,   14, 0}, /* PC4 */
+    {&gpioc,   NULL, &adc1,  5, 0,   15, 0}, /* PC5 */
+    {&gpioc, &timer8, NULL,  6, 1, ADCx, 0}, /* PC6 I2S2_MCK/SDIO_D6*/
+	{&gpioc, &timer8, NULL,  7, 2, ADCx, 0}, /* PC7 I2S3_MCK/SDIO_D7*/
+    {&gpioc, &timer8, NULL,  8, 3, ADCx, 0}, /* PC8 SDIO_D0*/
+    {&gpioc, &timer8, NULL,  9, 4, ADCx, 0}, /* PC9 SDIO_D1*/
+    {&gpioc,   NULL, NULL, 10, 0, ADCx, 0}, /* PC10 UART4_TX/SDIO_D2 */
+    {&gpioc,   NULL, NULL, 11, 0, ADCx, 0}, /* PC11 UART4_RX/SDIO_D3 */
+    {&gpioc,   NULL, NULL, 12, 0, ADCx, 0}, /* PC12 UART5_TX/SDIO_CK */
+    {&gpioc,   NULL, NULL, 13, 0, ADCx, 0}, /* PC13 TAMPER-RTC/ Limited output*/
+    {&gpioc,   NULL, NULL, 14, 0, ADCx, 0}, /* PC14 OSC32_IN/ Limited output*/
+    {&gpioc,   NULL, NULL, 15, 0, ADCx, 0}, /* PC15 OSC32_OUT/ Limited output*/
+
+	{&gpiod,   NULL, NULL,   0, 0, ADCx, 0} , /* PD0 OSC_IN */
+	{&gpiod,   NULL, NULL,   1, 0, ADCx, 0} , /* PD1  OSC_OUT */
+	{&gpiod,   NULL, NULL,   2, 0, ADCx, 0} , /* PD2  TIM3_ETR/UART5_RX SDIO_CMD */
+	{&gpiod,   NULL, NULL,   3, 0, ADCx, 0} , /* PD3  FSMC_CLK */
+	{&gpiod,   NULL, NULL,   4, 0, ADCx, 0} , /* PD4  FSMC_NOE */
+	{&gpiod,   NULL, NULL,   5, 0, ADCx, 0} , /* PD5  FSMC_NWE */
+	{&gpiod,   NULL, NULL,   6, 0, ADCx, 0} , /* PD6  FSMC_NWAIT */
+	{&gpiod,   NULL, NULL,   7, 0, ADCx, 0} , /* PD7  FSMC_NE1/FSMC_NCE2 */
+	{&gpiod,   NULL, NULL,   8, 0, ADCx, 0} , /* PD8  FSMC_D13 */
+	{&gpiod,   NULL, NULL,   9, 0, ADCx, 0} , /* PD9  FSMC_D14 */
+	{&gpiod,   NULL, NULL,  10, 0, ADCx, 0} , /* PD10  FSMC_D15 */
+	{&gpiod,   NULL, NULL,  11, 0, ADCx, 0} , /* PD11  FSMC_A16 */
+	{&gpiod,   NULL, NULL,  12, 0, ADCx, 0} , /* PD12  FSMC_A17 */
+	{&gpiod,   NULL, NULL,  13, 0, ADCx, 0} , /* PD13  FSMC_A18 */	
+	{&gpiod,   NULL, NULL,  14, 0, ADCx, 0} , /* PD14  FSMC_D0 */
+	{&gpiod,   NULL, NULL,  15, 0, ADCx, 0} , /* PD15  FSMC_D1 */
 	
-	{&gpioe,   NULL, NULL,   0, 0, ADCx} , /* PE0  TIM4_ETR / FSMC_NBL0 */
-	{&gpioe,   NULL, NULL,   1, 0, ADCx} , /* PE1  FSMC_NBL1 */
-	{&gpioe,   NULL, NULL,   2, 0, ADCx} , /* PE2  TRACECK/ FSMC_A23 */
-	{&gpioe,   NULL, NULL,   3, 0, ADCx} , /* PE3  TRACED0/FSMC_A19 */
-	{&gpioe,   NULL, NULL,   4, 0, ADCx} , /* PE4  TRACED1/FSMC_A20 */
-	{&gpioe,   NULL, NULL,   5, 0, ADCx} , /* PE5  TRACED2/FSMC_A21 */
-	{&gpioe,   NULL, NULL,   6, 0, ADCx} , /* PE6  TRACED3/FSMC_A22 */
-	{&gpioe,   NULL, NULL,   7, 0, ADCx} , /* PE7  FSMC_D4 */
-	{&gpioe,   NULL, NULL,   8, 0, ADCx} , /* PE8  FSMC_D5 */
-	{&gpioe,   NULL, NULL,   9, 0, ADCx} , /* PE9  FSMC_D6 */
-	{&gpioe,   NULL, NULL,  10, 0, ADCx} , /* PE10 FSMC_D7 */
-	{&gpioe,   NULL, NULL,  11, 0, ADCx} , /* PE11 FSMC_D8 */
-	{&gpioe,   NULL, NULL,  12, 0, ADCx} , /* PE12 FSMC_D9 */
-	{&gpioe,   NULL, NULL,  13, 0, ADCx} , /* PE13 FSMC_D10 */	
-	{&gpioe,   NULL, NULL,  14, 0, ADCx} , /* PE14 FSMC_D11 */
-	{&gpioe,   NULL, NULL,  15, 0, ADCx} , /* PE15 FSMC_D12 */	
+	{&gpioe,   NULL, NULL,   0, 0, ADCx, 0} , /* PE0  TIM4_ETR / FSMC_NBL0 */
+	{&gpioe,   NULL, NULL,   1, 0, ADCx, 0} , /* PE1  FSMC_NBL1 */
+	{&gpioe,   NULL, NULL,   2, 0, ADCx, 0} , /* PE2  TRACECK/ FSMC_A23 */
+	{&gpioe,   NULL, NULL,   3, 0, ADCx, 0} , /* PE3  TRACED0/FSMC_A19 */
+	{&gpioe,   NULL, NULL,   4, 0, ADCx, 0} , /* PE4  TRACED1/FSMC_A20 */
+	{&gpioe,   NULL, NULL,   5, 0, ADCx, 0} , /* PE5  TRACED2/FSMC_A21 */
+	{&gpioe,   NULL, NULL,   6, 0, ADCx, 0} , /* PE6  TRACED3/FSMC_A22 */
+	{&gpioe,   NULL, NULL,   7, 0, ADCx, 0} , /* PE7  FSMC_D4 */
+	{&gpioe,   NULL, NULL,   8, 0, ADCx, 0} , /* PE8  FSMC_D5 */
+	{&gpioe,   NULL, NULL,   9, 0, ADCx, 0} , /* PE9  FSMC_D6 */
+	{&gpioe,   NULL, NULL,  10, 0, ADCx, 0} , /* PE10 FSMC_D7 */
+	{&gpioe,   NULL, NULL,  11, 0, ADCx, 0} , /* PE11 FSMC_D8 */
+	{&gpioe,   NULL, NULL,  12, 0, ADCx, 0} , /* PE12 FSMC_D9 */
+	{&gpioe,   NULL, NULL,  13, 0, ADCx, 0} , /* PE13 FSMC_D10 */	
+	{&gpioe,   NULL, NULL,  14, 0, ADCx, 0} , /* PE14 FSMC_D11 */
+	{&gpioe,   NULL, NULL,  15, 0, ADCx, 0} , /* PE15 FSMC_D12 */	
 	
 };
-#pragma GCC diagnostic pop
 
 /*  Basically everything that is defined as having a timer us PWM */
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
diff --git a/STM32F1/variants/generic_stm32f103z/board.cpp b/STM32F1/variants/generic_stm32f103z/board.cpp
index 4d2e4e989..0d112a32b 100644
--- a/STM32F1/variants/generic_stm32f103z/board.cpp
+++ b/STM32F1/variants/generic_stm32f103z/board.cpp
@@ -69,8 +69,6 @@ void boardInit(void) {
 // - ADC device, or NULL if none
 // - ADC channel, or ADCx if none
 
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 /*
     gpio_dev *gpio_device;      GPIO device 
@@ -82,128 +80,127 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 	uint8 pinMode; 				mode specific by pinMode call (Roger Clark added to optimize compatibility with Arduino API
 */
 
-    {&gpioa, &timer2, &adc1,  0, 1,    0}, /* PA0 */
-    {&gpioa, &timer2, &adc1,  1, 2,    1}, /* PA1 */
-	{&gpioa, &timer2, &adc1,  2, 3,    2}, /* PA2 */
-    {&gpioa, &timer2, &adc1,  3, 4,    3}, /* PA3 */
-	{&gpioa,   NULL, &adc1,  4, 0,    4}, /* PA4 */	
-    {&gpioa,   NULL, &adc1,  5, 0,    5}, /* PA5 */
-    {&gpioa, &timer3, &adc1,  6, 1,    6}, /* PA6 */
-    {&gpioa, &timer3, &adc1,  7, 2,    7}, /* PA7 */
-    {&gpioa, &timer1, NULL,  8, 1, ADCx}, /* PA8 */
-    {&gpioa, &timer1, NULL,  9, 2, ADCx}, /* PA9 */
-    {&gpioa, &timer1, NULL, 10, 3, ADCx}, /* PA10 */
-    {&gpioa,   NULL, NULL, 11, 0, ADCx}, /* PA11 */
-    {&gpioa,   NULL, NULL, 12, 0, ADCx}, /* PA12 */	
-    {&gpioa,   NULL, NULL, 13, 0, ADCx}, /* PA13 */
-    {&gpioa,   NULL, NULL, 14, 0, ADCx}, /* PA14 */
-    {&gpioa,   NULL, NULL, 15, 0, ADCx}, /* PA15 */
+    {&gpioa, &timer2, &adc1,  0, 1,    0, 0}, /* PA0 */
+    {&gpioa, &timer2, &adc1,  1, 2,    1, 0}, /* PA1 */
+	{&gpioa, &timer2, &adc1,  2, 3,    2, 0}, /* PA2 */
+    {&gpioa, &timer2, &adc1,  3, 4,    3, 0}, /* PA3 */
+	{&gpioa,   NULL, &adc1,  4, 0,    4, 0}, /* PA4 */
+    {&gpioa,   NULL, &adc1,  5, 0,    5, 0}, /* PA5 */
+    {&gpioa, &timer3, &adc1,  6, 1,    6, 0}, /* PA6 */
+    {&gpioa, &timer3, &adc1,  7, 2,    7, 0}, /* PA7 */
+    {&gpioa, &timer1, NULL,  8, 1, ADCx, 0}, /* PA8 */
+    {&gpioa, &timer1, NULL,  9, 2, ADCx, 0}, /* PA9 */
+    {&gpioa, &timer1, NULL, 10, 3, ADCx, 0}, /* PA10 */
+    {&gpioa,   NULL, NULL, 11, 0, ADCx, 0}, /* PA11 */
+    {&gpioa,   NULL, NULL, 12, 0, ADCx, 0}, /* PA12 */
+    {&gpioa,   NULL, NULL, 13, 0, ADCx, 0}, /* PA13 */
+    {&gpioa,   NULL, NULL, 14, 0, ADCx, 0}, /* PA14 */
+    {&gpioa,   NULL, NULL, 15, 0, ADCx, 0}, /* PA15 */
 	
-	{&gpiob, &timer3, &adc1,  0, 3,    8}, /* PB0 */
-	{&gpiob, &timer3, &adc1,  1, 4,    9}, /* PB1 */
-	{&gpiob, &timer3, &adc1,  2, 4,    9}, /* PB2 */
-	{&gpiob,   NULL, NULL,  3, 0, ADCx}, /* PB3  */
-    {&gpiob,   NULL, NULL,  4, 0, ADCx}, /* PB4  */
-    {&gpiob,   NULL, NULL,  5, 0, ADCx}, /* PB5 */
-    {&gpiob, &timer4, NULL,  6, 1, ADCx}, /* PB6 */
-    {&gpiob, &timer4, NULL,  7, 2, ADCx}, /* PB7 */
-    {&gpiob, &timer4, NULL,  8, 3, ADCx}, /* PB8 */
-	{&gpiob, &timer4, NULL,  9, 4, ADCx}, /* PB9 */
-    {&gpiob,   NULL, NULL, 10, 0, ADCx}, /* PB10 */
-    {&gpiob,   NULL, NULL, 11, 0, ADCx}, /* PB11 */
-    {&gpiob,   NULL, NULL, 12, 0, ADCx}, /* PB12 */
-    {&gpiob,   NULL, NULL, 13, 0, ADCx}, /* PB13 */
-    {&gpiob,   NULL, NULL, 14, 0, ADCx}, /* PB14 */
-    {&gpiob,   NULL, NULL, 15, 0, ADCx}, /* PB15 */
-
-
-    {&gpioc,   NULL, &adc1,  0, 0,   10}, /* PC0 */
-    {&gpioc,   NULL, &adc1,  1, 0,   11}, /* PC1 */
-    {&gpioc,   NULL, &adc1,  2, 0,   12}, /* PC2 */
-    {&gpioc,   NULL, &adc1,  3, 0,   13}, /* PC3 */
-    {&gpioc,   NULL, &adc1,  4, 0,   14}, /* PC4 */
-    {&gpioc,   NULL, &adc1,  5, 0,   15}, /* PC5 */
-    {&gpioc, &timer8, NULL,  6, 1, ADCx}, /* PC6 */	
-	{&gpioc, &timer8, NULL,  7, 2, ADCx}, /* PC7 */
-    {&gpioc, &timer8, NULL,  8, 3, ADCx}, /* PC8 */
-    {&gpioc, &timer8, NULL,  9, 4, ADCx}, /* PC9 */
-    {&gpioc,   NULL, NULL, 10, 0, ADCx}, /* PC10 UART4_TX/SDIO_D2 */
-    {&gpioc,   NULL, NULL, 11, 0, ADCx}, /* PC11 UART4_RX/SDIO_D3 */
-    {&gpioc,   NULL, NULL, 12, 0, ADCx}, /* PC12 UART5_TX/SDIO_CK */	
-    {&gpioc,   NULL, NULL, 13, 0, ADCx}, /* PC13 TAMPER-RTC */
-    {&gpioc,   NULL, NULL, 14, 0, ADCx}, /* PC14 OSC32_IN */
-    {&gpioc,   NULL, NULL, 15, 0, ADCx}, /* PC15 OSC32_OUT */
-
-	{&gpiod,   NULL, NULL,   0, 0, ADCx} , /* PD0 OSC_IN */
-	{&gpiod,   NULL, NULL,   1, 0, ADCx} , /* PD1  OSC_OUT */
-	{&gpiod,   NULL, NULL,   2, 0, ADCx} , /* PD2  TIM3_ETR/UART5_RX SDIO_CMD */
+	{&gpiob, &timer3, &adc1,  0, 3,    8, 0}, /* PB0 */
+	{&gpiob, &timer3, &adc1,  1, 4,    9, 0}, /* PB1 */
+	{&gpiob, &timer3, &adc1,  2, 4,    9, 0}, /* PB2 */
+	{&gpiob,   NULL, NULL,  3, 0, ADCx, 0}, /* PB3  */
+    {&gpiob,   NULL, NULL,  4, 0, ADCx, 0}, /* PB4  */
+    {&gpiob,   NULL, NULL,  5, 0, ADCx, 0}, /* PB5 */
+    {&gpiob, &timer4, NULL,  6, 1, ADCx, 0}, /* PB6 */
+    {&gpiob, &timer4, NULL,  7, 2, ADCx, 0}, /* PB7 */
+    {&gpiob, &timer4, NULL,  8, 3, ADCx, 0}, /* PB8 */
+	{&gpiob, &timer4, NULL,  9, 4, ADCx, 0}, /* PB9 */
+    {&gpiob,   NULL, NULL, 10, 0, ADCx, 0}, /* PB10 */
+    {&gpiob,   NULL, NULL, 11, 0, ADCx, 0}, /* PB11 */
+    {&gpiob,   NULL, NULL, 12, 0, ADCx, 0}, /* PB12 */
+    {&gpiob,   NULL, NULL, 13, 0, ADCx, 0}, /* PB13 */
+    {&gpiob,   NULL, NULL, 14, 0, ADCx, 0}, /* PB14 */
+    {&gpiob,   NULL, NULL, 15, 0, ADCx, 0}, /* PB15 */
+
+
+    {&gpioc,   NULL, &adc1,  0, 0,   10, 0}, /* PC0 */
+    {&gpioc,   NULL, &adc1,  1, 0,   11, 0}, /* PC1 */
+    {&gpioc,   NULL, &adc1,  2, 0,   12, 0}, /* PC2 */
+    {&gpioc,   NULL, &adc1,  3, 0,   13, 0}, /* PC3 */
+    {&gpioc,   NULL, &adc1,  4, 0,   14, 0}, /* PC4 */
+    {&gpioc,   NULL, &adc1,  5, 0,   15, 0}, /* PC5 */
+    {&gpioc, &timer8, NULL,  6, 1, ADCx, 0}, /* PC6 */
+	{&gpioc, &timer8, NULL,  7, 2, ADCx, 0}, /* PC7 */
+    {&gpioc, &timer8, NULL,  8, 3, ADCx, 0}, /* PC8 */
+    {&gpioc, &timer8, NULL,  9, 4, ADCx, 0}, /* PC9 */
+    {&gpioc,   NULL, NULL, 10, 0, ADCx, 0}, /* PC10 UART4_TX/SDIO_D2 */
+    {&gpioc,   NULL, NULL, 11, 0, ADCx, 0}, /* PC11 UART4_RX/SDIO_D3 */
+    {&gpioc,   NULL, NULL, 12, 0, ADCx, 0}, /* PC12 UART5_TX/SDIO_CK */
+    {&gpioc,   NULL, NULL, 13, 0, ADCx, 0}, /* PC13 TAMPER-RTC */
+    {&gpioc,   NULL, NULL, 14, 0, ADCx, 0}, /* PC14 OSC32_IN */
+    {&gpioc,   NULL, NULL, 15, 0, ADCx, 0}, /* PC15 OSC32_OUT */
+
+	{&gpiod,   NULL, NULL,   0, 0, ADCx, 0} , /* PD0 OSC_IN */
+	{&gpiod,   NULL, NULL,   1, 0, ADCx, 0} , /* PD1  OSC_OUT */
+	{&gpiod,   NULL, NULL,   2, 0, ADCx, 0} , /* PD2  TIM3_ETR/UART5_RX SDIO_CMD */
 	
-	{&gpiod,   NULL, NULL,   3, 0, ADCx} , /* PD3  FSMC_CLK */
-	{&gpiod,   NULL, NULL,   4, 0, ADCx} , /* PD4  FSMC_NOE */
-	{&gpiod,   NULL, NULL,   5, 0, ADCx} , /* PD5  FSMC_NWE */
-	{&gpiod,   NULL, NULL,   6, 0, ADCx} , /* PD6  FSMC_NWAIT */
-	{&gpiod,   NULL, NULL,   7, 0, ADCx} , /* PD7  FSMC_NE1/FSMC_NCE2 */
-	{&gpiod,   NULL, NULL,   8, 0, ADCx} , /* PD8  FSMC_D13 */
-	{&gpiod,   NULL, NULL,   9, 0, ADCx} , /* PD9  FSMC_D14 */
-	{&gpiod,   NULL, NULL,  10, 0, ADCx} , /* PD10  FSMC_D15 */
-	{&gpiod,   NULL, NULL,  11, 0, ADCx} , /* PD11  FSMC_A16 */
-	{&gpiod,   NULL, NULL,  12, 0, ADCx} , /* PD12  FSMC_A17 */
-	{&gpiod,   NULL, NULL,  13, 0, ADCx} , /* PD13  FSMC_A18 */	
-	{&gpiod,   NULL, NULL,  14, 0, ADCx} , /* PD14  FSMC_D0 */
-	{&gpiod,   NULL, NULL,  15, 0, ADCx} , /* PD15  FSMC_D1 */
+	{&gpiod,   NULL, NULL,   3, 0, ADCx, 0} , /* PD3  FSMC_CLK */
+	{&gpiod,   NULL, NULL,   4, 0, ADCx, 0} , /* PD4  FSMC_NOE */
+	{&gpiod,   NULL, NULL,   5, 0, ADCx, 0} , /* PD5  FSMC_NWE */
+	{&gpiod,   NULL, NULL,   6, 0, ADCx, 0} , /* PD6  FSMC_NWAIT */
+	{&gpiod,   NULL, NULL,   7, 0, ADCx, 0} , /* PD7  FSMC_NE1/FSMC_NCE2 */
+	{&gpiod,   NULL, NULL,   8, 0, ADCx, 0} , /* PD8  FSMC_D13 */
+	{&gpiod,   NULL, NULL,   9, 0, ADCx, 0} , /* PD9  FSMC_D14 */
+	{&gpiod,   NULL, NULL,  10, 0, ADCx, 0} , /* PD10  FSMC_D15 */
+	{&gpiod,   NULL, NULL,  11, 0, ADCx, 0} , /* PD11  FSMC_A16 */
+	{&gpiod,   NULL, NULL,  12, 0, ADCx, 0} , /* PD12  FSMC_A17 */
+	{&gpiod,   NULL, NULL,  13, 0, ADCx, 0} , /* PD13  FSMC_A18 */	
+	{&gpiod,   NULL, NULL,  14, 0, ADCx, 0} , /* PD14  FSMC_D0 */
+	{&gpiod,   NULL, NULL,  15, 0, ADCx, 0} , /* PD15  FSMC_D1 */
 	
-	{&gpioe,   NULL, NULL,   0, 0, ADCx} , /* PE0   */
-	{&gpioe,   NULL, NULL,   1, 0, ADCx} , /* PE1   */
-	{&gpioe,   NULL, NULL,   2, 0, ADCx} , /* PE2   */
-	{&gpioe,   NULL, NULL,   3, 0, ADCx} , /* PE3   */
-	{&gpioe,   NULL, NULL,   4, 0, ADCx} , /* PE4   */
-	{&gpioe,   NULL, NULL,   5, 0, ADCx} , /* PE5   */
-	{&gpioe,   NULL, NULL,   6, 0, ADCx} , /* PE6   */
-	{&gpioe,   NULL, NULL,   7, 0, ADCx} , /* PE7   */
-	{&gpioe,   NULL, NULL,   8, 0, ADCx} , /* PE8   */
-	{&gpioe,   NULL, NULL,   9, 0, ADCx} , /* PE9   */
-	{&gpioe,   NULL, NULL,  10, 0, ADCx} , /* PE10  */
-	{&gpioe,   NULL, NULL,  11, 0, ADCx} , /* PE11  */
-	{&gpioe,   NULL, NULL,  12, 0, ADCx} , /* PE12  */
-	{&gpioe,   NULL, NULL,  13, 0, ADCx} , /* PE13  */	
-	{&gpioe,   NULL, NULL,  14, 0, ADCx} , /* PE14  */
-	{&gpioe,   NULL, NULL,  15, 0, ADCx} , /* PE15  */	
-
-	{&gpiof,   NULL, NULL,   0, 0, ADCx} , /* PF0   */
-	{&gpiof,   NULL, NULL,   1, 0, ADCx} , /* PF1   */
-	{&gpiof,   NULL, NULL,   2, 0, ADCx} , /* PF2   */
-	{&gpiof,   NULL, NULL,   3, 0, ADCx} , /* PF3   */
-	{&gpiof,   NULL, NULL,   4, 0, ADCx} , /* PF4   */
-	{&gpiof,   NULL, NULL,   5, 0, ADCx} , /* PF5   */
-	{&gpiof,   NULL, NULL,   6, 0, ADCx} , /* PF6   */
-	{&gpiof,   NULL, NULL,   7, 0, ADCx} , /* PF7   */
-	{&gpiof,   NULL, NULL,   8, 0, ADCx} , /* PF8   */
-	{&gpiof,   NULL, NULL,   9, 0, ADCx} , /* PF9   */
-	{&gpiof,   NULL, NULL,  10, 0, ADCx} , /* PF10  */
-	{&gpiof,   NULL, NULL,  11, 0, ADCx} , /* PF11  */
-	{&gpiof,   NULL, NULL,  12, 0, ADCx} , /* PF12  */
-	{&gpiof,   NULL, NULL,  13, 0, ADCx} , /* PF13  */	
-	{&gpiof,   NULL, NULL,  14, 0, ADCx} , /* PF14  */
-	{&gpiof,   NULL, NULL,  15, 0, ADCx} , /* PF15  */		
+	{&gpioe,   NULL, NULL,   0, 0, ADCx, 0} , /* PE0   */
+	{&gpioe,   NULL, NULL,   1, 0, ADCx, 0} , /* PE1   */
+	{&gpioe,   NULL, NULL,   2, 0, ADCx, 0} , /* PE2   */
+	{&gpioe,   NULL, NULL,   3, 0, ADCx, 0} , /* PE3   */
+	{&gpioe,   NULL, NULL,   4, 0, ADCx, 0} , /* PE4   */
+	{&gpioe,   NULL, NULL,   5, 0, ADCx, 0} , /* PE5   */
+	{&gpioe,   NULL, NULL,   6, 0, ADCx, 0} , /* PE6   */
+	{&gpioe,   NULL, NULL,   7, 0, ADCx, 0} , /* PE7   */
+	{&gpioe,   NULL, NULL,   8, 0, ADCx, 0} , /* PE8   */
+	{&gpioe,   NULL, NULL,   9, 0, ADCx, 0} , /* PE9   */
+	{&gpioe,   NULL, NULL,  10, 0, ADCx, 0} , /* PE10  */
+	{&gpioe,   NULL, NULL,  11, 0, ADCx, 0} , /* PE11  */
+	{&gpioe,   NULL, NULL,  12, 0, ADCx, 0} , /* PE12  */
+	{&gpioe,   NULL, NULL,  13, 0, ADCx, 0} , /* PE13  */	
+	{&gpioe,   NULL, NULL,  14, 0, ADCx, 0} , /* PE14  */
+	{&gpioe,   NULL, NULL,  15, 0, ADCx, 0} , /* PE15  */	
+
+	{&gpiof,   NULL, NULL,   0, 0, ADCx, 0} , /* PF0   */
+	{&gpiof,   NULL, NULL,   1, 0, ADCx, 0} , /* PF1   */
+	{&gpiof,   NULL, NULL,   2, 0, ADCx, 0} , /* PF2   */
+	{&gpiof,   NULL, NULL,   3, 0, ADCx, 0} , /* PF3   */
+	{&gpiof,   NULL, NULL,   4, 0, ADCx, 0} , /* PF4   */
+	{&gpiof,   NULL, NULL,   5, 0, ADCx, 0} , /* PF5   */
+	{&gpiof,   NULL, NULL,   6, 0, ADCx, 0} , /* PF6   */
+	{&gpiof,   NULL, NULL,   7, 0, ADCx, 0} , /* PF7   */
+	{&gpiof,   NULL, NULL,   8, 0, ADCx, 0} , /* PF8   */
+	{&gpiof,   NULL, NULL,   9, 0, ADCx, 0} , /* PF9   */
+	{&gpiof,   NULL, NULL,  10, 0, ADCx, 0} , /* PF10  */
+	{&gpiof,   NULL, NULL,  11, 0, ADCx, 0} , /* PF11  */
+	{&gpiof,   NULL, NULL,  12, 0, ADCx, 0} , /* PF12  */
+	{&gpiof,   NULL, NULL,  13, 0, ADCx, 0} , /* PF13  */	
+	{&gpiof,   NULL, NULL,  14, 0, ADCx, 0} , /* PF14  */
+	{&gpiof,   NULL, NULL,  15, 0, ADCx, 0} , /* PF15  */		
 	
-	{&gpiog,   NULL, NULL,   0, 0, ADCx} , /* PG0   */
-	{&gpiog,   NULL, NULL,   1, 0, ADCx} , /* PG1   */
-	{&gpiog,   NULL, NULL,   2, 0, ADCx} , /* PG2   */
-	{&gpiog,   NULL, NULL,   3, 0, ADCx} , /* PG3   */
-	{&gpiog,   NULL, NULL,   4, 0, ADCx} , /* PG4   */
-	{&gpiog,   NULL, NULL,   5, 0, ADCx} , /* PG5   */
-	{&gpiog,   NULL, NULL,   6, 0, ADCx} , /* PG6   */
-	{&gpiog,   NULL, NULL,   7, 0, ADCx} , /* PG7   */
-	{&gpiog,   NULL, NULL,   8, 0, ADCx} , /* PG8   */
-	{&gpiog,   NULL, NULL,   9, 0, ADCx} , /* PG9   */
-	{&gpiog,   NULL, NULL,  10, 0, ADCx} , /* PG10  */
-	{&gpiog,   NULL, NULL,  11, 0, ADCx} , /* PG11  */
-	{&gpiog,   NULL, NULL,  12, 0, ADCx} , /* PG12  */
-	{&gpiog,   NULL, NULL,  13, 0, ADCx} , /* PG13  */	
-	{&gpiog,   NULL, NULL,  14, 0, ADCx} , /* PG14  */
-	{&gpiog,   NULL, NULL,  15, 0, ADCx}  /* PG15  */		
+	{&gpiog,   NULL, NULL,   0, 0, ADCx, 0} , /* PG0   */
+	{&gpiog,   NULL, NULL,   1, 0, ADCx, 0} , /* PG1   */
+	{&gpiog,   NULL, NULL,   2, 0, ADCx, 0} , /* PG2   */
+	{&gpiog,   NULL, NULL,   3, 0, ADCx, 0} , /* PG3   */
+	{&gpiog,   NULL, NULL,   4, 0, ADCx, 0} , /* PG4   */
+	{&gpiog,   NULL, NULL,   5, 0, ADCx, 0} , /* PG5   */
+	{&gpiog,   NULL, NULL,   6, 0, ADCx, 0} , /* PG6   */
+	{&gpiog,   NULL, NULL,   7, 0, ADCx, 0} , /* PG7   */
+	{&gpiog,   NULL, NULL,   8, 0, ADCx, 0} , /* PG8   */
+	{&gpiog,   NULL, NULL,   9, 0, ADCx, 0} , /* PG9   */
+	{&gpiog,   NULL, NULL,  10, 0, ADCx, 0} , /* PG10  */
+	{&gpiog,   NULL, NULL,  11, 0, ADCx, 0} , /* PG11  */
+	{&gpiog,   NULL, NULL,  12, 0, ADCx, 0} , /* PG12  */
+	{&gpiog,   NULL, NULL,  13, 0, ADCx, 0} , /* PG13  */	
+	{&gpiog,   NULL, NULL,  14, 0, ADCx, 0} , /* PG14  */
+	{&gpiog,   NULL, NULL,  15, 0, ADCx, 0}  /* PG15  */		
 };
-#pragma GCC diagnostic pop
 
 /*  Basically everything that is defined as having a timer us PWM */
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
diff --git a/STM32F1/variants/hytiny_stm32f103t/board.cpp b/STM32F1/variants/hytiny_stm32f103t/board.cpp
index d1260a6d0..b3fdd9b88 100644
--- a/STM32F1/variants/hytiny_stm32f103t/board.cpp
+++ b/STM32F1/variants/hytiny_stm32f103t/board.cpp
@@ -51,39 +51,36 @@ void boardInit(void) {
 }
 
 // Note. See the enum of pin names in board.h
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
 
-    {&gpioa, &timer2, &adc1,  0, 1,    0}, /* PA0 */
-    {&gpioa, &timer2, &adc1,  1, 2,    1}, /* PA1 */
-    {&gpioa, &timer2, &adc1,  2, 3,    2}, /* PA2 */	
-    {&gpioa, &timer2, &adc1,  3, 4,    3}, /* PA3 */
-    {&gpioa,   NULL, &adc1,  4, 0,    4}, /* PA4 */
-    {&gpioa,   NULL, &adc1,  5, 0,    5}, /* PA5 */
-    {&gpioa, &timer3, &adc1,  6, 1,    6}, /* PA6 */
-    {&gpioa, &timer3, &adc1,  7, 2,    7}, /* PA7 */
-    {&gpioa, &timer1, NULL,  8, 1, ADCx}, /* PA8 */	
-    {&gpioa, &timer1, NULL,  9, 2, ADCx}, /* PA9 */	
-    {&gpioa, &timer1, NULL, 10, 3, ADCx}, /* PA10 */
-    {&gpioa, &timer1, NULL, 11, 4, ADCx}, /* PA11 */
-    {&gpioa,   NULL, NULL, 12, 0, ADCx}, /* PA12 */	
-    {&gpioa,   NULL, NULL, 13, 0, ADCx}, /* PA13 */	
-    {&gpioa,   NULL, NULL, 14, 0, ADCx}, /* PA14 */
-    {&gpioa,   NULL, NULL, 15, 0, ADCx}, /* PA15 */
+    {&gpioa, &timer2, &adc1,  0, 1,    0, 0}, /* PA0 */
+    {&gpioa, &timer2, &adc1,  1, 2,    1, 0}, /* PA1 */
+    {&gpioa, &timer2, &adc1,  2, 3,    2, 0}, /* PA2 */
+    {&gpioa, &timer2, &adc1,  3, 4,    3, 0}, /* PA3 */
+    {&gpioa,   NULL, &adc1,  4, 0,    4, 0}, /* PA4 */
+    {&gpioa,   NULL, &adc1,  5, 0,    5, 0}, /* PA5 */
+    {&gpioa, &timer3, &adc1,  6, 1,    6, 0}, /* PA6 */
+    {&gpioa, &timer3, &adc1,  7, 2,    7, 0}, /* PA7 */
+    {&gpioa, &timer1, NULL,  8, 1, ADCx, 0}, /* PA8 */
+    {&gpioa, &timer1, NULL,  9, 2, ADCx, 0}, /* PA9 */
+    {&gpioa, &timer1, NULL, 10, 3, ADCx, 0}, /* PA10 */
+    {&gpioa, &timer1, NULL, 11, 4, ADCx, 0}, /* PA11 */
+    {&gpioa,   NULL, NULL, 12, 0, ADCx, 0}, /* PA12 */
+    {&gpioa,   NULL, NULL, 13, 0, ADCx, 0}, /* PA13 */
+    {&gpioa,   NULL, NULL, 14, 0, ADCx, 0}, /* PA14 */
+    {&gpioa,   NULL, NULL, 15, 0, ADCx, 0}, /* PA15 */
 	
-    {&gpiob, &timer3, &adc1,  0, 3,    8}, /* PB0 */	
-    {&gpiob, &timer3, &adc1,  1, 4,    9}, /* PB1 */
-    {&gpiob,   NULL, NULL,  2, 0, ADCx}, /* PB2 */
-    {&gpiob,   NULL, NULL,  3, 0, ADCx}, /* PB3 */
-    {&gpiob,   NULL, NULL,  4, 0, ADCx}, /* PB4 */
-    {&gpiob,   NULL, NULL,  5, 0, ADCx}, /* PB5 */
-    {&gpiob, &timer4, NULL,  6, 1, ADCx}, /* PB6 */
-    {&gpiob, &timer4, NULL,  7, 2, ADCx}, /* PB7 */	
+    {&gpiob, &timer3, &adc1,  0, 3,    8, 0}, /* PB0 */
+    {&gpiob, &timer3, &adc1,  1, 4,    9, 0}, /* PB1 */
+    {&gpiob,   NULL, NULL,  2, 0, ADCx, 0}, /* PB2 */
+    {&gpiob,   NULL, NULL,  3, 0, ADCx, 0}, /* PB3 */
+    {&gpiob,   NULL, NULL,  4, 0, ADCx, 0}, /* PB4 */
+    {&gpiob,   NULL, NULL,  5, 0, ADCx, 0}, /* PB5 */
+    {&gpiob, &timer4, NULL,  6, 1, ADCx, 0}, /* PB6 */
+    {&gpiob, &timer4, NULL,  7, 2, ADCx, 0}, /* PB7 */
 
 };
-#pragma GCC diagnostic pop
 
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
     PB0, PA7, PA6, PA3, PA2, PA1, PA0, PB7, PB6, PA10, PA9, PA8
diff --git a/STM32F1/variants/maple/board.cpp b/STM32F1/variants/maple/board.cpp
index b1584e7ea..a4c033557 100644
--- a/STM32F1/variants/maple/board.cpp
+++ b/STM32F1/variants/maple/board.cpp
@@ -68,8 +68,6 @@ void boardInit(void) {
 // - Timer channel (1 to 4, for PWM), or 0 if none
 // - ADC device, or NULL if none
 // - ADC channel, or ADCx if none
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
     /* Top header */
@@ -128,7 +126,6 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
     PMAP_ROW(&gpiob,   3,   NULL,  0, NULL, ADCx), /* D42/PB3  */
     PMAP_ROW(&gpiob,   4,   NULL,  0, NULL, ADCx), /* D43/PB4  */
 };
-#pragma GCC diagnostic pop
 
 // Array of pins you can use for pwmWrite(). Keep it in Flash because
 // it doesn't change, and so we don't waste RAM.
diff --git a/STM32F1/variants/maple_mini/board.cpp b/STM32F1/variants/maple_mini/board.cpp
index bf63364ae..72faa17fb 100644
--- a/STM32F1/variants/maple_mini/board.cpp
+++ b/STM32F1/variants/maple_mini/board.cpp
@@ -50,51 +50,48 @@ void boardInit(void) {
 #endif
 }
 
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
     /* Top header */
 
-    {&gpiob,   NULL, NULL, 11, 0, ADCx}, /* D0/PB11 */
-    {&gpiob,   NULL, NULL, 10, 0, ADCx}, /* D1/PB10 */
-    {&gpiob,   NULL, NULL,  2, 0, ADCx}, /* D2/PB2 */
-    {&gpiob, &timer3, &adc1,  0, 3,    8}, /* D3/PB0 */
-    {&gpioa, &timer3, &adc1,  7, 2,    7}, /* D4/PA7 */
-    {&gpioa, &timer3, &adc1,  6, 1,    6}, /* D5/PA6 */
-    {&gpioa,   NULL, &adc1,  5, 0,    5}, /* D6/PA5 */
-    {&gpioa,   NULL, &adc1,  4, 0,    4}, /* D7/PA4 */
-    {&gpioa, &timer2, &adc1,  3, 4,    3}, /* D8/PA3 */
-    {&gpioa, &timer2, &adc1,  2, 3,    2}, /* D9/PA2 */
-    {&gpioa, &timer2, &adc1,  1, 2,    1}, /* D10/PA1 */
-    {&gpioa, &timer2, &adc1,  0, 1,    0}, /* D11/PA0 */
-    {&gpioc,   NULL, NULL, 15, 0, ADCx}, /* D12/PC15 */
-    {&gpioc,   NULL, NULL, 14, 0, ADCx}, /* D13/PC14 */
-    {&gpioc,   NULL, NULL, 13, 0, ADCx}, /* D14/PC13 */
+    {&gpiob,   NULL, NULL, 11, 0, ADCx, 0}, /* D0/PB11 */
+    {&gpiob,   NULL, NULL, 10, 0, ADCx, 0}, /* D1/PB10 */
+    {&gpiob,   NULL, NULL,  2, 0, ADCx, 0}, /* D2/PB2 */
+    {&gpiob, &timer3, &adc1,  0, 3,    8, 0}, /* D3/PB0 */
+    {&gpioa, &timer3, &adc1,  7, 2,    7, 0}, /* D4/PA7 */
+    {&gpioa, &timer3, &adc1,  6, 1,    6, 0}, /* D5/PA6 */
+    {&gpioa,   NULL, &adc1,  5, 0,    5, 0}, /* D6/PA5 */
+    {&gpioa,   NULL, &adc1,  4, 0,    4, 0}, /* D7/PA4 */
+    {&gpioa, &timer2, &adc1,  3, 4,    3, 0}, /* D8/PA3 */
+    {&gpioa, &timer2, &adc1,  2, 3,    2, 0}, /* D9/PA2 */
+    {&gpioa, &timer2, &adc1,  1, 2,    1, 0}, /* D10/PA1 */
+    {&gpioa, &timer2, &adc1,  0, 1,    0, 0}, /* D11/PA0 */
+    {&gpioc,   NULL, NULL, 15, 0, ADCx, 0}, /* D12/PC15 */
+    {&gpioc,   NULL, NULL, 14, 0, ADCx, 0}, /* D13/PC14 */
+    {&gpioc,   NULL, NULL, 13, 0, ADCx, 0}, /* D14/PC13 */
 
     /* Bottom header */
 
-    {&gpiob, &timer4, NULL,  7, 2, ADCx}, /* D15/PB7 */
-    {&gpiob, &timer4, NULL,  6, 1, ADCx}, /* D16/PB6 */
-    {&gpiob,   NULL, NULL,  5, 0, ADCx}, /* D17/PB5 */
-    {&gpiob,   NULL, NULL,  4, 0, ADCx}, /* D18/PB4 */
-    {&gpiob,   NULL, NULL,  3, 0, ADCx}, /* D19/PB3 */
-    {&gpioa,   NULL, NULL, 15, 0, ADCx}, /* D20/PA15 */
-    {&gpioa,   NULL, NULL, 14, 0, ADCx}, /* D21/PA14 */
-    {&gpioa,   NULL, NULL, 13, 0, ADCx}, /* D22/PA13 */
-    {&gpioa,   NULL, NULL, 12, 0, ADCx}, /* D23/PA12 */
-    {&gpioa, &timer1, NULL, 11, 4, ADCx}, /* D24/PA11 */
-    {&gpioa, &timer1, NULL, 10, 3, ADCx}, /* D25/PA10 */
-    {&gpioa, &timer1, NULL,  9, 2, ADCx}, /* D26/PA9 */
-    {&gpioa, &timer1, NULL,  8, 1, ADCx}, /* D27/PA8 */
-    {&gpiob,   NULL, NULL, 15, 0, ADCx}, /* D28/PB15 */
-    {&gpiob,   NULL, NULL, 14, 0, ADCx}, /* D29/PB14 */
-    {&gpiob,   NULL, NULL, 13, 0, ADCx}, /* D30/PB13 */
-    {&gpiob,   NULL, NULL, 12, 0, ADCx}, /* D31/PB12 */
-    {&gpiob, &timer4, NULL,  8, 3, ADCx}, /* D32/PB8 */
-    {&gpiob, &timer3, &adc1,  1, 4,    9}, /* D33/PB1 */
+    {&gpiob, &timer4, NULL,  7, 2, ADCx, 0}, /* D15/PB7 */
+    {&gpiob, &timer4, NULL,  6, 1, ADCx, 0}, /* D16/PB6 */
+    {&gpiob,   NULL, NULL,  5, 0, ADCx, 0}, /* D17/PB5 */
+    {&gpiob,   NULL, NULL,  4, 0, ADCx, 0}, /* D18/PB4 */
+    {&gpiob,   NULL, NULL,  3, 0, ADCx, 0}, /* D19/PB3 */
+    {&gpioa,   NULL, NULL, 15, 0, ADCx, 0}, /* D20/PA15 */
+    {&gpioa,   NULL, NULL, 14, 0, ADCx, 0}, /* D21/PA14 */
+    {&gpioa,   NULL, NULL, 13, 0, ADCx, 0}, /* D22/PA13 */
+    {&gpioa,   NULL, NULL, 12, 0, ADCx, 0}, /* D23/PA12 */
+    {&gpioa, &timer1, NULL, 11, 4, ADCx, 0}, /* D24/PA11 */
+    {&gpioa, &timer1, NULL, 10, 3, ADCx, 0}, /* D25/PA10 */
+    {&gpioa, &timer1, NULL,  9, 2, ADCx, 0}, /* D26/PA9 */
+    {&gpioa, &timer1, NULL,  8, 1, ADCx, 0}, /* D27/PA8 */
+    {&gpiob,   NULL, NULL, 15, 0, ADCx, 0}, /* D28/PB15 */
+    {&gpiob,   NULL, NULL, 14, 0, ADCx, 0}, /* D29/PB14 */
+    {&gpiob,   NULL, NULL, 13, 0, ADCx, 0}, /* D30/PB13 */
+    {&gpiob,   NULL, NULL, 12, 0, ADCx, 0}, /* D31/PB12 */
+    {&gpiob, &timer4, NULL,  8, 3, ADCx, 0}, /* D32/PB8 */
+    {&gpiob, &timer3, &adc1,  1, 4,    9, 0}, /* D33/PB1 */
 };
-#pragma GCC diagnostic pop
 
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
     3, 4, 5, 8, 9, 10, 11, 15, 16, 25, 26, 27
diff --git a/STM32F1/variants/maple_ret6/board.cpp b/STM32F1/variants/maple_ret6/board.cpp
index dfec977ba..82127ff88 100644
--- a/STM32F1/variants/maple_ret6/board.cpp
+++ b/STM32F1/variants/maple_ret6/board.cpp
@@ -69,8 +69,6 @@ void boardInit(void) {
 // - ADC device, or NULL if none
 // - ADC channel, or ADCx if none
 
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 /*
     gpio_dev *gpio_device;      GPIO device 
@@ -84,68 +82,67 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
 	/* Top header */
 
-	{ &gpioa, &timer2, &adc1, 3, 4, 3 }, /* D0/PA3 */
-	{ &gpioa, &timer2, &adc1, 2, 3, 2 }, /* D1/PA2 */
-	{ &gpioa, &timer2, &adc1, 0, 1, 0 }, /* D2/PA0 */
-	{ &gpioa, &timer2, &adc1, 1, 2, 1 }, /* D3/PA1 */
-	{ &gpiob, NULL, NULL, 5, 0, ADCx }, /* D4/PB5 */
-	{ &gpiob, &timer4, NULL, 6, 1, ADCx }, /* D5/PB6 */
-	{ &gpioa, &timer1, NULL, 8, 1, ADCx }, /* D6/PA8 */
-	{ &gpioa, &timer1, NULL, 9, 2, ADCx }, /* D7/PA9 */
-	{ &gpioa, &timer1, NULL, 10, 3, ADCx }, /* D8/PA10 */
-	{ &gpiob, &timer4, NULL, 7, 2, ADCx }, /* D9/PB7 */
-	{ &gpioa, NULL, &adc1, 4, 0, 4 }, /* D10/PA4 */
-	{ &gpioa, &timer3, &adc1, 7, 2, 7 }, /* D11/PA7 */
-	{ &gpioa, &timer3, &adc1, 6, 1, 6 }, /* D12/PA6 */
-	{ &gpioa, NULL, &adc1, 5, 0, 5 }, /* D13/PA5 (LED) */
-	{ &gpiob, &timer4, NULL, 8, 3, ADCx }, /* D14/PB8 */
+	{ &gpioa, &timer2, &adc1, 3, 4, 3, 0}, /* D0/PA3 */
+	{ &gpioa, &timer2, &adc1, 2, 3, 2, 0}, /* D1/PA2 */
+	{ &gpioa, &timer2, &adc1, 0, 1, 0, 0}, /* D2/PA0 */
+	{ &gpioa, &timer2, &adc1, 1, 2, 1, 0}, /* D3/PA1 */
+	{ &gpiob, NULL, NULL, 5, 0, ADCx, 0}, /* D4/PB5 */
+	{ &gpiob, &timer4, NULL, 6, 1, ADCx, 0}, /* D5/PB6 */
+	{ &gpioa, &timer1, NULL, 8, 1, ADCx, 0}, /* D6/PA8 */
+	{ &gpioa, &timer1, NULL, 9, 2, ADCx, 0}, /* D7/PA9 */
+	{ &gpioa, &timer1, NULL, 10, 3, ADCx, 0}, /* D8/PA10 */
+	{ &gpiob, &timer4, NULL, 7, 2, ADCx, 0}, /* D9/PB7 */
+	{ &gpioa, NULL, &adc1, 4, 0, 4, 0}, /* D10/PA4 */
+	{ &gpioa, &timer3, &adc1, 7, 2, 7, 0}, /* D11/PA7 */
+	{ &gpioa, &timer3, &adc1, 6, 1, 6, 0}, /* D12/PA6 */
+	{ &gpioa, NULL, &adc1, 5, 0, 5, 0}, /* D13/PA5 (LED) */
+	{ &gpiob, &timer4, NULL, 8, 3, ADCx, 0}, /* D14/PB8 */
 
 	/* Little header */
 
-	{ &gpioc, NULL, &adc1, 0, 0, 10 }, /* D15/PC0 */
-	{ &gpioc, NULL, &adc1, 1, 0, 11 }, /* D16/PC1 */
-	{ &gpioc, NULL, &adc1, 2, 0, 12 }, /* D17/PC2 */
-	{ &gpioc, NULL, &adc1, 3, 0, 13 }, /* D18/PC3 */
-	{ &gpioc, NULL, &adc1, 4, 0, 14 }, /* D19/PC4 */
-	{ &gpioc, NULL, &adc1, 5, 0, 15 }, /* D20/PC5 */
+	{ &gpioc, NULL, &adc1, 0, 0, 10, 0}, /* D15/PC0 */
+	{ &gpioc, NULL, &adc1, 1, 0, 11, 0}, /* D16/PC1 */
+	{ &gpioc, NULL, &adc1, 2, 0, 12, 0}, /* D17/PC2 */
+	{ &gpioc, NULL, &adc1, 3, 0, 13, 0}, /* D18/PC3 */
+	{ &gpioc, NULL, &adc1, 4, 0, 14, 0}, /* D19/PC4 */
+	{ &gpioc, NULL, &adc1, 5, 0, 15, 0}, /* D20/PC5 */
 
 	/* External header */
 
-	{ &gpioc, NULL, NULL, 13, 0, ADCx }, /* D21/PC13 */
-	{ &gpioc, NULL, NULL, 14, 0, ADCx }, /* D22/PC14 */
-	{ &gpioc, NULL, NULL, 15, 0, ADCx }, /* D23/PC15 */
-	{ &gpiob, &timer4, NULL, 9, 4, ADCx }, /* D24/PB9 */
-	{ &gpiod, NULL, NULL, 2, 0, ADCx }, /* D25/PD2 */
-	{ &gpioc, NULL, NULL, 10, 0, ADCx }, /* D26/PC10 */
-	{ &gpiob, &timer3, &adc1, 0, 3, 8 }, /* D27/PB0 */
-	{ &gpiob, &timer3, &adc1, 1, 4, 9 }, /* D28/PB1 */
-	{ &gpiob, NULL, NULL, 10, 0, ADCx }, /* D29/PB10 */
-	{ &gpiob, NULL, NULL, 11, 0, ADCx }, /* D30/PB11 */
-	{ &gpiob, NULL, NULL, 12, 0, ADCx }, /* D31/PB12 */
-	{ &gpiob, NULL, NULL, 13, 0, ADCx }, /* D32/PB13 */
-	{ &gpiob, NULL, NULL, 14, 0, ADCx }, /* D33/PB14 */
-	{ &gpiob, NULL, NULL, 15, 0, ADCx }, /* D34/PB15 */
-	{ &gpioc, &timer8, NULL, 6, 1, ADCx }, /* D35/PC6 */
-	{ &gpioc, &timer8, NULL, 7, 2, ADCx }, /* D36/PC7 */
-	{ &gpioc, &timer8, NULL, 8, 3, ADCx }, /* D37/PC8 */
-	{ &gpioc, &timer8, NULL, 9, 4, ADCx }, /* D38/PC9 (BUT) */
+	{ &gpioc, NULL, NULL, 13, 0, ADCx, 0}, /* D21/PC13 */
+	{ &gpioc, NULL, NULL, 14, 0, ADCx, 0}, /* D22/PC14 */
+	{ &gpioc, NULL, NULL, 15, 0, ADCx, 0}, /* D23/PC15 */
+	{ &gpiob, &timer4, NULL, 9, 4, ADCx, 0}, /* D24/PB9 */
+	{ &gpiod, NULL, NULL, 2, 0, ADCx, 0}, /* D25/PD2 */
+	{ &gpioc, NULL, NULL, 10, 0, ADCx, 0}, /* D26/PC10 */
+	{ &gpiob, &timer3, &adc1, 0, 3, 8, 0}, /* D27/PB0 */
+	{ &gpiob, &timer3, &adc1, 1, 4, 9, 0}, /* D28/PB1 */
+	{ &gpiob, NULL, NULL, 10, 0, ADCx, 0}, /* D29/PB10 */
+	{ &gpiob, NULL, NULL, 11, 0, ADCx, 0}, /* D30/PB11 */
+	{ &gpiob, NULL, NULL, 12, 0, ADCx, 0}, /* D31/PB12 */
+	{ &gpiob, NULL, NULL, 13, 0, ADCx, 0}, /* D32/PB13 */
+	{ &gpiob, NULL, NULL, 14, 0, ADCx, 0}, /* D33/PB14 */
+	{ &gpiob, NULL, NULL, 15, 0, ADCx, 0}, /* D34/PB15 */
+	{ &gpioc, &timer8, NULL, 6, 1, ADCx, 0}, /* D35/PC6 */
+	{ &gpioc, &timer8, NULL, 7, 2, ADCx, 0}, /* D36/PC7 */
+	{ &gpioc, &timer8, NULL, 8, 3, ADCx, 0}, /* D37/PC8 */
+	{ &gpioc, &timer8, NULL, 9, 4, ADCx, 0}, /* D38/PC9 (BUT) */
 
 	/* JTAG header */
 
-	{ &gpioa, NULL, NULL, 13, 0, ADCx }, /* D39/PA13 */
-	{ &gpioa, NULL, NULL, 14, 0, ADCx }, /* D40/PA14 */
-	{ &gpioa, NULL, NULL, 15, 0, ADCx }, /* D41/PA15 */
-	{ &gpiob, NULL, NULL, 3, 0, ADCx }, /* D42/PB3  */
-	{ &gpiob, NULL, NULL, 4, 0, ADCx }, /* D43/PB4  */
+	{ &gpioa, NULL, NULL, 13, 0, ADCx, 0}, /* D39/PA13 */
+	{ &gpioa, NULL, NULL, 14, 0, ADCx, 0}, /* D40/PA14 */
+	{ &gpioa, NULL, NULL, 15, 0, ADCx, 0}, /* D41/PA15 */
+	{ &gpiob, NULL, NULL, 3, 0, ADCx, 0}, /* D42/PB3  */
+	{ &gpiob, NULL, NULL, 4, 0, ADCx, 0}, /* D43/PB4  */
 
-	{ &gpioc, NULL, NULL, 11, 0, ADCx }, /* D44/PC11 UART4_RX/SDIO_D3 */
-	{ &gpioc, NULL, NULL, 12, 0, ADCx }, /* D45/PC12 UART5_TX/SDIO_CK */
+	{ &gpioc, NULL, NULL, 11, 0, ADCx, 0}, /* D44/PC11 UART4_RX/SDIO_D3 */
+	{ &gpioc, NULL, NULL, 12, 0, ADCx, 0}, /* D45/PC12 UART5_TX/SDIO_CK */
 
-	{ &gpiod, NULL, NULL, 0, 0, ADCx }, /* PD0 OSC_IN */
-	{ &gpiod, NULL, NULL, 1, 0, ADCx }, /* PD1  OSC_OUT */
-	{ &gpiob, NULL, NULL, 2, 0, ADCx }, /* PB2  */
+	{ &gpiod, NULL, NULL, 0, 0, ADCx, 0}, /* PD0 OSC_IN */
+	{ &gpiod, NULL, NULL, 1, 0, ADCx, 0}, /* PD1  OSC_OUT */
+	{ &gpiob, NULL, NULL, 2, 0, ADCx, 0}, /* PB2  */
 };
-#pragma GCC diagnostic pop
 
 /*  Basically everything that is defined as having a timer us PWM */
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
diff --git a/STM32F1/variants/microduino/board.cpp b/STM32F1/variants/microduino/board.cpp
index d7b4a97d1..51c80248d 100644
--- a/STM32F1/variants/microduino/board.cpp
+++ b/STM32F1/variants/microduino/board.cpp
@@ -51,42 +51,39 @@ void boardInit(void) {
 #endif
 }
 
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
 
-    {&gpioa, &timer1, NULL, 10, 3, ADCx}, /* D0(RxD0)/PA10 */
-    {&gpioa, &timer1, NULL,  9, 2, ADCx}, /* D1(TxD1)/PA9 */
-    {&gpiob,   NULL, NULL, 11, 0, ADCx}, /* D2/PB11 */
-    {&gpiob,   NULL, NULL, 10, 0, ADCx}, /* D3/PB10 */
-    {&gpioa, &timer1, NULL,  8, 1, ADCx}, /* D4/PA8 */
-    {&gpioa,   NULL, NULL, 13, 0, ADCx}, /* D5/PA13 */
-    {&gpioa,   NULL, NULL, 14, 0, ADCx}, /* D6/PA14 */
-    {&gpioa,   NULL, NULL, 15, 0, ADCx}, /* D7/PA15 */
-    {&gpiob,   NULL, NULL,  3, 0, ADCx}, /* D8/PB3 */
-    {&gpiob,   NULL, NULL,  4, 0, ADCx}, /* D9/PB4 */
-    {&gpioa,   NULL, &adc1,  4, 0,    4}, /* D10/PA4 */
-    {&gpioa, &timer3, &adc1,  7, 2,    7}, /* D11/PA7 */
-    {&gpioa, &timer3, &adc1,  6, 1,    6}, /* D12/PA6 */
-    {&gpioa,   NULL, &adc1,  5, 0,    5}, /* D13/PA5 */
-
-    {&gpioa, &timer2, &adc1,  0, 1,    0}, /* D14(A0)/PA0 */
-    {&gpioa, &timer2, &adc1,  1, 2,    1}, /* D15(A1)/PA1 */
-    {&gpioa, &timer2, &adc1,  2, 3,    2}, /* D16(A2)/PA2 */
-    {&gpioa, &timer2, &adc1,  3, 4,    3}, /* D17(A3)/PA3 */
-    {&gpiob, &timer4, NULL,  7, 2, ADCx}, /* D18(A4)/PB7 */
-    {&gpiob, &timer4, NULL,  6, 1, ADCx}, /* D19(A5)/PB6 */
-    {&gpiob, &timer3, &adc1,  0, 3,    8}, /* D20(A6)/PB0 */
-    {&gpiob, &timer3, &adc1,  1, 4,    9}, /* D21(A7)/PB1 */
-
-    {&gpioa,   NULL, NULL, 12, 0, ADCx}, /* D22/PA12/USB D+ */
-    {&gpioa, &timer1, NULL, 11, 4, ADCx}, /* D23/PA11/USB D- */
+    {&gpioa, &timer1, NULL, 10, 3, ADCx, 0}, /* D0(RxD0)/PA10 */
+    {&gpioa, &timer1, NULL,  9, 2, ADCx, 0}, /* D1(TxD1)/PA9 */
+    {&gpiob,   NULL, NULL, 11, 0, ADCx, 0}, /* D2/PB11 */
+    {&gpiob,   NULL, NULL, 10, 0, ADCx, 0}, /* D3/PB10 */
+    {&gpioa, &timer1, NULL,  8, 1, ADCx, 0}, /* D4/PA8 */
+    {&gpioa,   NULL, NULL, 13, 0, ADCx, 0}, /* D5/PA13 */
+    {&gpioa,   NULL, NULL, 14, 0, ADCx, 0}, /* D6/PA14 */
+    {&gpioa,   NULL, NULL, 15, 0, ADCx, 0}, /* D7/PA15 */
+    {&gpiob,   NULL, NULL,  3, 0, ADCx, 0}, /* D8/PB3 */
+    {&gpiob,   NULL, NULL,  4, 0, ADCx, 0}, /* D9/PB4 */
+    {&gpioa,   NULL, &adc1,  4, 0,    4, 0}, /* D10/PA4 */
+    {&gpioa, &timer3, &adc1,  7, 2,    7, 0}, /* D11/PA7 */
+    {&gpioa, &timer3, &adc1,  6, 1,    6, 0}, /* D12/PA6 */
+    {&gpioa,   NULL, &adc1,  5, 0,    5, 0}, /* D13/PA5 */
+
+    {&gpioa, &timer2, &adc1,  0, 1,    0, 0}, /* D14(A0)/PA0 */
+    {&gpioa, &timer2, &adc1,  1, 2,    1, 0}, /* D15(A1)/PA1 */
+    {&gpioa, &timer2, &adc1,  2, 3,    2, 0}, /* D16(A2)/PA2 */
+    {&gpioa, &timer2, &adc1,  3, 4,    3, 0}, /* D17(A3)/PA3 */
+    {&gpiob, &timer4, NULL,  7, 2, ADCx, 0}, /* D18(A4)/PB7 */
+    {&gpiob, &timer4, NULL,  6, 1, ADCx, 0}, /* D19(A5)/PB6 */
+    {&gpiob, &timer3, &adc1,  0, 3,    8, 0}, /* D20(A6)/PB0 */
+    {&gpiob, &timer3, &adc1,  1, 4,    9, 0}, /* D21(A7)/PB1 */
+
+    {&gpioa,   NULL, NULL, 12, 0, ADCx, 0}, /* D22/PA12/USB D+ */
+    {&gpioa, &timer1, NULL, 11, 4, ADCx, 0}, /* D23/PA11/USB D- */
 
     // FIXME: find out which pin is the button, if any
-    {&gpiob,   NULL, NULL,  8, 0, ADCx}, /* D24/PB8??/Button */
+    {&gpiob,   NULL, NULL,  8, 0, ADCx, 0}, /* D24/PB8??/Button */
 };
-#pragma GCC diagnostic pop
 
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
     0, 1, 4, 11, 12, 14, 15, 16, 17, 18, 19, 20, 21, 23
diff --git a/STM32F1/variants/nucleo_f103rb/board.cpp b/STM32F1/variants/nucleo_f103rb/board.cpp
index 9754a2d43..5e2672cfc 100644
--- a/STM32F1/variants/nucleo_f103rb/board.cpp
+++ b/STM32F1/variants/nucleo_f103rb/board.cpp
@@ -93,65 +93,62 @@ rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSI_DIV_2, &pll_data};
 
 //       0    1    3      4    2     5
 //       0    1    2      4    2     5
-#pragma GCC diagnostic push
-#pragma GCC diagnostic ignored "-Wmissing-field-initializers"
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
     /* Arduino-like header, right connectors */
-    {&gpioa, NULL,   &adc1,   3,  0,    3}, /*  D0/PA3 */
-    {&gpioa, NULL,   &adc1,   2,  0,    2}, /*  D1/PA2 */
-    {&gpioa, &timer1, NULL,  10,  3, ADCx}, /*  D2/PA10 */
-    {&gpiob, &timer2, NULL,   3,  2, ADCx}, /*  D3/PB3  */
-    {&gpiob, &timer3, NULL,   5,  2, ADCx}, /*  D4/PB5 */
-    {&gpiob, &timer3, NULL,   4,  1, ADCx}, /*  D5/PB4  */
-    {&gpiob, &timer2, NULL,  10,  3, ADCx}, /*  D6/PB10 */
-    {&gpioa, &timer1, NULL,   8,  1, ADCx}, /*  D7/PA8 */
+    {&gpioa, NULL,   &adc1,   3,  0,    3, 0}, /*  D0/PA3 */
+    {&gpioa, NULL,   &adc1,   2,  0,    2, 0}, /*  D1/PA2 */
+    {&gpioa, &timer1, NULL,  10,  3, ADCx, 0}, /*  D2/PA10 */
+    {&gpiob, &timer2, NULL,   3,  2, ADCx, 0}, /*  D3/PB3  */
+    {&gpiob, &timer3, NULL,   5,  2, ADCx, 0}, /*  D4/PB5 */
+    {&gpiob, &timer3, NULL,   4,  1, ADCx, 0}, /*  D5/PB4  */
+    {&gpiob, &timer2, NULL,  10,  3, ADCx, 0}, /*  D6/PB10 */
+    {&gpioa, &timer1, NULL,   8,  1, ADCx, 0}, /*  D7/PA8 */
                    
-    {&gpioa, &timer1, NULL,   9,  2, ADCx}, /*  D8/PA9  */
-    {&gpioc, NULL,   NULL,   7,  0, ADCx}, /*  D9/PC7  */
-    {&gpiob, &timer4, NULL,   6,  1, ADCx}, /*  D10/PB6 */
-    {&gpioa, NULL,   &adc1,   7,  0,    7}, /*  D11/PA7 */
-    {&gpioa, NULL,   &adc1,   6,  0, 	  6}, /*  D12/PA6 */
-    {&gpioa, NULL,   NULL,   5,  0, ADCx}, /*  D13/PA5 LED - no &adc12_IN5 !*/
-    {&gpiob, &timer4, NULL,   9,  4, ADCx}, /*  D14/PB9 */
-    {&gpiob, &timer4, NULL,   8,  3, ADCx}, /*  D15/PB8 */
+    {&gpioa, &timer1, NULL,   9,  2, ADCx, 0}, /*  D8/PA9  */
+    {&gpioc, NULL,   NULL,   7,  0, ADCx, 0}, /*  D9/PC7  */
+    {&gpiob, &timer4, NULL,   6,  1, ADCx, 0}, /*  D10/PB6 */
+    {&gpioa, NULL,   &adc1,   7,  0,    7, 0}, /*  D11/PA7 */
+    {&gpioa, NULL,   &adc1,   6,  0, 	  6, 0}, /*  D12/PA6 */
+    {&gpioa, NULL,   NULL,   5,  0, ADCx, 0}, /*  D13/PA5 LED - no &adc12_IN5 !*/
+    {&gpiob, &timer4, NULL,   9,  4, ADCx, 0}, /*  D14/PB9 */
+    {&gpiob, &timer4, NULL,   8,  3, ADCx, 0}, /*  D15/PB8 */
                    
-    {&gpioa, NULL,   &adc1,   0,  0,    0}, /*  D16/A0/PA0 */
-    {&gpioa, NULL,   &adc1,   1,  0,    1}, /*  D17/A1/PA1 */
-    {&gpioa, NULL,   &adc1,   4,  0,    4}, /*  D18/A2/PA4 */
-    {&gpiob, &timer3, &adc1,   0,  3,    8}, /*  D19/A3/PB0 */
-    {&gpioc, NULL,   &adc1,   1,  0,   11}, /*  D20/A4/PC1 */
-    {&gpioc, NULL,   &adc1,   0,  0,   10}, /*  D21/A5/PC0 */
+    {&gpioa, NULL,   &adc1,   0,  0,    0, 0}, /*  D16/A0/PA0 */
+    {&gpioa, NULL,   &adc1,   1,  0,    1, 0}, /*  D17/A1/PA1 */
+    {&gpioa, NULL,   &adc1,   4,  0,    4, 0}, /*  D18/A2/PA4 */
+    {&gpiob, &timer3, &adc1,   0,  3,    8, 0}, /*  D19/A3/PB0 */
+    {&gpioc, NULL,   &adc1,   1,  0,   11, 0}, /*  D20/A4/PC1 */
+    {&gpioc, NULL,   &adc1,   0,  0,   10, 0}, /*  D21/A5/PC0 */
                    
-    {&gpioc, NULL,   NULL,  10,  0, ADCx}, /*  D22/PC10 */
-	{&gpioc, NULL,   NULL,  12,  0, ADCx}, /*  D23/PC12 */
-    {&gpiob, &timer4, NULL,   7,  2, ADCx}, /*  D24/PB7 */
-    {&gpioc, NULL,   NULL,  13,  0, ADCx}, /*  D25/PC13 USER BLUE BUTTON */
-    {&gpioc, NULL,   NULL,  14,  0, ADCx}, /*  D26/PC14 */
-    {&gpioc, NULL,   NULL,  15,  0, ADCx}, /*  D27/PC15 */
-    {&gpioc, NULL,   &adc1,   2,  0,   12}, /*  D28/PC2 */
-    {&gpioc, NULL,   &adc1,   3,  0,   13}, /*  D29/PC3 */
-    {&gpioc, NULL,   NULL,  11,  0, ADCx}, /*  D30/PC11 */
-    {&gpiod, NULL,   NULL,   2,  0, ADCx}, /*  D31/PD2 */
-    {&gpioc, NULL,   NULL,   9,  0, ADCx}, /*  D32/PC9 */
-    {&gpioc, NULL,   NULL,   8,  0, ADCx}, /*  D33/PC8 */
-    {&gpioc, NULL,   NULL,   6,  0, ADCx}, /*  D34/PC6 */
-    {&gpioc, NULL,   &adc1,   5,  0,   15}, /*  D35/PC5 */
-    {&gpioa, NULL,   NULL,  12,  0, ADCx}, /*  D36/PA12 */
-    {&gpioa, &timer1, NULL,  11,  4, ADCx}, /*  D37/PA11 */
-    {&gpiob, NULL,   NULL,  12,  0, ADCx}, /*  D38/PB12 */
-    {&gpiob, &timer2, NULL,  11,  4, ADCx}, /*  D39/PB11 PWM-not working?*/
-    {&gpiob, NULL,   NULL,  2,   0, ADCx}, /*  D40/PB2 BOOT1 !!*/
-    {&gpiob, &timer3, &adc1,   1,  4,    9}, /*  D41/PB1 */
-    {&gpiob, NULL,   NULL,  15,  0, ADCx}, /*  D42/PB15 */
-    {&gpiob, NULL,   NULL,  14,  0, ADCx}, /*  D43/PB14 */
-    {&gpiob, NULL,   NULL,  13,  0, ADCx}, /*  D44/PB13 */
-    {&gpioc, NULL,   &adc1,   4,  0,   14}, /*  D45/PC4 */
-  //  PMAP_ROW(&gpioa,  13,   NULL,  0, NULL, ADCx), /* D41/PA13 do not use*/
-   // PMAP_ROW(&gpioa,  14,   NULL,  0, NULL, ADCx), /* D42/PA14  do not use*/
-   // PMAP_ROW(&gpioa,  15,   &timer2,  1, NULL, ADCx), /* D43/PA15 do not use*/
+    {&gpioc, NULL,   NULL,  10,  0, ADCx, 0}, /*  D22/PC10 */
+	{&gpioc, NULL,   NULL,  12,  0, ADCx, 0}, /*  D23/PC12 */
+    {&gpiob, &timer4, NULL,   7,  2, ADCx, 0}, /*  D24/PB7 */
+    {&gpioc, NULL,   NULL,  13,  0, ADCx, 0}, /*  D25/PC13 USER BLUE BUTTON */
+    {&gpioc, NULL,   NULL,  14,  0, ADCx, 0}, /*  D26/PC14 */
+    {&gpioc, NULL,   NULL,  15,  0, ADCx, 0}, /*  D27/PC15 */
+    {&gpioc, NULL,   &adc1,   2,  0,   12, 0}, /*  D28/PC2 */
+    {&gpioc, NULL,   &adc1,   3,  0,   13, 0}, /*  D29/PC3 */
+    {&gpioc, NULL,   NULL,  11,  0, ADCx, 0}, /*  D30/PC11 */
+    {&gpiod, NULL,   NULL,   2,  0, ADCx, 0}, /*  D31/PD2 */
+    {&gpioc, NULL,   NULL,   9,  0, ADCx, 0}, /*  D32/PC9 */
+    {&gpioc, NULL,   NULL,   8,  0, ADCx, 0}, /*  D33/PC8 */
+    {&gpioc, NULL,   NULL,   6,  0, ADCx, 0}, /*  D34/PC6 */
+    {&gpioc, NULL,   &adc1,   5,  0,   15, 0}, /*  D35/PC5 */
+    {&gpioa, NULL,   NULL,  12,  0, ADCx, 0}, /*  D36/PA12 */
+    {&gpioa, &timer1, NULL,  11,  4, ADCx, 0}, /*  D37/PA11 */
+    {&gpiob, NULL,   NULL,  12,  0, ADCx, 0}, /*  D38/PB12 */
+    {&gpiob, &timer2, NULL,  11,  4, ADCx, 0}, /*  D39/PB11 PWM-not working?*/
+    {&gpiob, NULL,   NULL,  2,   0, ADCx, 0}, /*  D40/PB2 BOOT1 !!*/
+    {&gpiob, &timer3, &adc1,   1,  4,    9, 0}, /*  D41/PB1 */
+    {&gpiob, NULL,   NULL,  15,  0, ADCx, 0}, /*  D42/PB15 */
+    {&gpiob, NULL,   NULL,  14,  0, ADCx, 0}, /*  D43/PB14 */
+    {&gpiob, NULL,   NULL,  13,  0, ADCx, 0}, /*  D44/PB13 */
+    {&gpioc, NULL,   &adc1,   4,  0,   14, 0}, /*  D45/PC4 */
+  //  PMAP_ROW(&gpioa,  13,   NULL,  0, NULL, ADCx, 0), /* D41/PA13 do not use*/
+   // PMAP_ROW(&gpioa,  14,   NULL,  0, NULL, ADCx, 0), /* D42/PA14  do not use*/
+   // PMAP_ROW(&gpioa,  15,   &timer2,  1, NULL, ADCx, 0), /* D43/PA15 do not use*/
 };
-#pragma GCC diagnostic pop
 
 // Array of pins you can use for pwmWrite(). Keep it in Flash because
 // it doesn't change, and so we don't waste RAM.
diff --git a/STM32F3/cores/maple/wirish/boards_private.h b/STM32F3/cores/maple/wirish/boards_private.h
index 49867ca77..332843ddf 100644
--- a/STM32F3/cores/maple/wirish/boards_private.h
+++ b/STM32F3/cores/maple/wirish/boards_private.h
@@ -42,7 +42,7 @@
 
 /* Makes the PIN_MAP rows more human-readable. */
 #define PMAP_ROW(gpio_dev, gpio_bit, timer_dev, timer_ch, adc_dev, adc_ch) \
-    { gpio_dev, timer_dev, adc_dev, gpio_bit, timer_ch, adc_ch }
+    { gpio_dev, timer_dev, adc_dev, gpio_bit, timer_ch, adc_ch, 0}
 
 namespace wirish {
     namespace priv {

From 048f15a2db84c44a55ec53d61121b348ce116619 Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Fri, 17 Nov 2017 11:16:48 +0100
Subject: [PATCH 235/307] Fixed a comment

---
 STM32F1/variants/nucleo_f103rb/board.cpp | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/STM32F1/variants/nucleo_f103rb/board.cpp b/STM32F1/variants/nucleo_f103rb/board.cpp
index 5e2672cfc..a70a188ca 100644
--- a/STM32F1/variants/nucleo_f103rb/board.cpp
+++ b/STM32F1/variants/nucleo_f103rb/board.cpp
@@ -145,9 +145,9 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
     {&gpiob, NULL,   NULL,  14,  0, ADCx, 0}, /*  D43/PB14 */
     {&gpiob, NULL,   NULL,  13,  0, ADCx, 0}, /*  D44/PB13 */
     {&gpioc, NULL,   &adc1,   4,  0,   14, 0}, /*  D45/PC4 */
-  //  PMAP_ROW(&gpioa,  13,   NULL,  0, NULL, ADCx, 0), /* D41/PA13 do not use*/
-   // PMAP_ROW(&gpioa,  14,   NULL,  0, NULL, ADCx, 0), /* D42/PA14  do not use*/
-   // PMAP_ROW(&gpioa,  15,   &timer2,  1, NULL, ADCx, 0), /* D43/PA15 do not use*/
+  //  PMAP_ROW(&gpioa,  13,   NULL,  0, NULL, ADCx), /* D41/PA13 do not use*/
+   // PMAP_ROW(&gpioa,  14,   NULL,  0, NULL, ADCx), /* D42/PA14  do not use*/
+   // PMAP_ROW(&gpioa,  15,   &timer2,  1, NULL, ADCx), /* D43/PA15 do not use*/
 };
 
 // Array of pins you can use for pwmWrite(). Keep it in Flash because

From 719ab20a5fb1bd6cc77e300fe32278a48c7ee83f Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Fri, 17 Nov 2017 14:44:01 +0100
Subject: [PATCH 236/307] Rollback on __attribute__((unused)) for pulseIn()

---
 STM32F1/cores/maple/stm32f1/wiring_pulse_f1.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/cores/maple/stm32f1/wiring_pulse_f1.cpp b/STM32F1/cores/maple/stm32f1/wiring_pulse_f1.cpp
index d9287b07b..9ca4d7fb8 100644
--- a/STM32F1/cores/maple/stm32f1/wiring_pulse_f1.cpp
+++ b/STM32F1/cores/maple/stm32f1/wiring_pulse_f1.cpp
@@ -26,7 +26,7 @@
   * to be slighly more accurate the maxLoops variable really needs to take into account the loop setup code, but its probably as good as necessary
   *
   */
-uint32_t pulseIn( uint32_t pin, uint32_t state __attribute__((unused)), uint32_t timeout )
+uint32_t pulseIn( uint32_t pin, uint32_t state, uint32_t timeout )
 {
    // cache the port and bit of the pin in order to speed up the
    // pulse width measuring loop and achieve finer resolution.  calling

From b64029f1db45e22f639bd3b882285dc06a0ed01c Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Sat, 18 Nov 2017 12:37:11 +0100
Subject: [PATCH 237/307] Rollback WireBase.begin()

---
 STM32F1/libraries/Wire/WireBase.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/libraries/Wire/WireBase.cpp b/STM32F1/libraries/Wire/WireBase.cpp
index eaa7f91ad..220d845d7 100644
--- a/STM32F1/libraries/Wire/WireBase.cpp
+++ b/STM32F1/libraries/Wire/WireBase.cpp
@@ -41,7 +41,7 @@
 #include "WireBase.h"
 #include "wirish.h"
 
-void WireBase::begin(uint8 self_addr __attribute__((unused))) {
+void WireBase::begin(uint8 self_addr) {
     tx_buf_idx = 0;
     tx_buf_overflow = false;
     rx_buf_idx = 0;

From 4a84203917deb692d65175c7c07c83893732861b Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Sat, 18 Nov 2017 21:08:20 +0100
Subject: [PATCH 238/307] Modified pulseIn() to use the state parameter

---
 .../cores/maple/stm32f1/wiring_pulse_f1.cpp   | 19 ++++++++++---------
 1 file changed, 10 insertions(+), 9 deletions(-)

diff --git a/STM32F1/cores/maple/stm32f1/wiring_pulse_f1.cpp b/STM32F1/cores/maple/stm32f1/wiring_pulse_f1.cpp
index 9ca4d7fb8..32ecc07d0 100644
--- a/STM32F1/cores/maple/stm32f1/wiring_pulse_f1.cpp
+++ b/STM32F1/cores/maple/stm32f1/wiring_pulse_f1.cpp
@@ -1,5 +1,6 @@
 #include <wiring_pulse.h>
 #include "boards.h"
+#include "variant.h"
 /* Measures the length (in microseconds) of a pulse on the pin; state is HIGH
  * or LOW, the type of pulse to measure.  Works on pulses from 2-3 microseconds
  * to 3 minutes in length, but must be called at least a few dozen microseconds
@@ -28,13 +29,13 @@
   */
 uint32_t pulseIn( uint32_t pin, uint32_t state, uint32_t timeout )
 {
-   // cache the port and bit of the pin in order to speed up the
+   // cache the reg map and bit of the pin in order to speed up the
    // pulse width measuring loop and achieve finer resolution.  calling
    // digitalRead() instead yields much coarser resolution.
  
-	gpio_dev *dev=PIN_MAP[pin].gpio_device;
-	uint32_t bit = (1U << PIN_MAP[pin].gpio_bit);
-   
+   const gpio_reg_map * const regs = digitalPinToPort(pin)->regs;
+   const uint32_t bit = digitalPinToBitMask(pin);
+   const uint32_t stateMask = (state ? bit:0);
 
    uint32_t width = 0; // keep initialization out of time critical area
    
@@ -45,23 +46,23 @@ uint32_t pulseIn( uint32_t pin, uint32_t state, uint32_t timeout )
    volatile uint32_t dummyWidth=0;
    
    // wait for any previous pulse to end
-   while ( (dev->regs->IDR & bit)  == bit)   {
+   while ((regs->IDR & bit) == stateMask)   {
       if (numloops++ == maxloops)  {
          return 0;
       }
-	   dummyWidth++;
+      dummyWidth++;
    }
    
    // wait for the pulse to start
-   while ((dev->regs->IDR & bit) != bit)   {
+   while ((regs->IDR & bit) != stateMask)   {
       if (numloops++ == maxloops) {
          return 0;
       }
-	  dummyWidth++;
+      dummyWidth++;
    }
    
    // wait for the pulse to stop
-   while ((dev->regs->IDR & bit) == bit) {
+   while ((regs->IDR & bit) == stateMask) {
       if (numloops++ == maxloops)  {
          return 0;
       }

From 0f6d90943adcfe12ddd69a998d47e5dc2dabb566 Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Sun, 19 Nov 2017 09:39:29 +0100
Subject: [PATCH 239/307] Caching IDR pointer

---
 STM32F1/cores/maple/stm32f1/wiring_pulse_f1.cpp | 10 +++++-----
 1 file changed, 5 insertions(+), 5 deletions(-)

diff --git a/STM32F1/cores/maple/stm32f1/wiring_pulse_f1.cpp b/STM32F1/cores/maple/stm32f1/wiring_pulse_f1.cpp
index 32ecc07d0..5a5d8358e 100644
--- a/STM32F1/cores/maple/stm32f1/wiring_pulse_f1.cpp
+++ b/STM32F1/cores/maple/stm32f1/wiring_pulse_f1.cpp
@@ -29,11 +29,11 @@
   */
 uint32_t pulseIn( uint32_t pin, uint32_t state, uint32_t timeout )
 {
-   // cache the reg map and bit of the pin in order to speed up the
+   // cache the IDR address and bit of the pin in order to speed up the
    // pulse width measuring loop and achieve finer resolution.  calling
    // digitalRead() instead yields much coarser resolution.
  
-   const gpio_reg_map * const regs = digitalPinToPort(pin)->regs;
+   __io uint32_t * const idr = portInputRegister(digitalPinToPort(pin));
    const uint32_t bit = digitalPinToBitMask(pin);
    const uint32_t stateMask = (state ? bit:0);
 
@@ -46,7 +46,7 @@ uint32_t pulseIn( uint32_t pin, uint32_t state, uint32_t timeout )
    volatile uint32_t dummyWidth=0;
    
    // wait for any previous pulse to end
-   while ((regs->IDR & bit) == stateMask)   {
+   while ((*idr & bit) == stateMask)   {
       if (numloops++ == maxloops)  {
          return 0;
       }
@@ -54,7 +54,7 @@ uint32_t pulseIn( uint32_t pin, uint32_t state, uint32_t timeout )
    }
    
    // wait for the pulse to start
-   while ((regs->IDR & bit) != stateMask)   {
+   while ((*idr & bit) != stateMask)   {
       if (numloops++ == maxloops) {
          return 0;
       }
@@ -62,7 +62,7 @@ uint32_t pulseIn( uint32_t pin, uint32_t state, uint32_t timeout )
    }
    
    // wait for the pulse to stop
-   while ((regs->IDR & bit) == stateMask) {
+   while ((*idr & bit) == stateMask) {
       if (numloops++ == maxloops)  {
          return 0;
       }

From e961f5bb18971c6b84f2b25986e5b3030ce7d3cd Mon Sep 17 00:00:00 2001
From: topin89 <topin89@mail.ru>
Date: Tue, 21 Nov 2017 16:48:45 +0300
Subject: [PATCH 240/307] Update HardwareTimer.h documentation.

"attachInterrupt" and "attachInterrupt" functions can attach ISRs to channel 0,
which is overflow interrupt (update interrupt in RMs).
---
 STM32F1/cores/maple/HardwareTimer.h | 6 ++++--
 1 file changed, 4 insertions(+), 2 deletions(-)

diff --git a/STM32F1/cores/maple/HardwareTimer.h b/STM32F1/cores/maple/HardwareTimer.h
index d5356ca21..bb40dba0f 100644
--- a/STM32F1/cores/maple/HardwareTimer.h
+++ b/STM32F1/cores/maple/HardwareTimer.h
@@ -177,7 +177,8 @@ class HardwareTimer {
      * This interrupt handler will be called when the timer's counter
      * reaches the given channel compare value.
      *
-     * @param channel the channel to attach the ISR to, from 1 to 4.
+     * @param channel the channel to attach the ISR to, from 0 to 4.
+     *   Channel 0 is for overflow interrupt (update interrupt).
      * @param handler The ISR to attach to the given channel.
      * @see voidFuncPtr
      */
@@ -189,7 +190,8 @@ class HardwareTimer {
      *
      * The handler will no longer be called by this timer.
      *
-     * @param channel the channel whose interrupt to detach, from 1 to 4.
+     * @param channel the channel whose interrupt to detach, from 0 to 4.
+     *   Channel 0 is for overflow interrupt (update interrupt).
      * @see HardwareTimer::attachInterrupt()
      */
     void detachInterrupt(int channel);

From 023fdfb0e9cb6acf367a1fe6b8bccafd815efc8b Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Sun, 26 Nov 2017 10:37:22 +0100
Subject: [PATCH 241/307] Update TimerInterrupts.ino

- replace deprecated function
---
 .../Maple/TimerInterrupts/TimerInterrupts.ino  | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)

diff --git a/STM32F1/libraries/A_STM32_Examples/examples/Maple/TimerInterrupts/TimerInterrupts.ino b/STM32F1/libraries/A_STM32_Examples/examples/Maple/TimerInterrupts/TimerInterrupts.ino
index e973358bc..38eb7d0ee 100644
--- a/STM32F1/libraries/A_STM32_Examples/examples/Maple/TimerInterrupts/TimerInterrupts.ino
+++ b/STM32F1/libraries/A_STM32_Examples/examples/Maple/TimerInterrupts/TimerInterrupts.ino
@@ -32,24 +32,24 @@ void setup()
     pinMode(BUTTON_PIN, INPUT_PULLUP);
 
     // Setup LED Timer
-    Timer2.setChannel1Mode(TIMER_OUTPUTCOMPARE);
+    Timer2.setMode(TIMER_CH1, TIMER_OUTPUTCOMPARE);
     Timer2.setPeriod(LED_RATE); // in microseconds
-    Timer2.setCompare1(1);      // overflow might be small
-    Timer2.attachCompare1Interrupt(handler_led);
+    Timer2.setCompare(TIMER_CH1, 1);      // overflow might be small
+    Timer2.attachInterrupt(TIMER_CH1, handler_led);
 
     // Setup Counting Timers
-    Timer3.setChannel1Mode(TIMER_OUTPUTCOMPARE);
-    Timer4.setChannel1Mode(TIMER_OUTPUTCOMPARE);
+    Timer3.setMode(TIMER_CH1, TIMER_OUTPUTCOMPARE);
+    Timer4.setMode(TIMER_CH1, TIMER_OUTPUTCOMPARE);
     Timer3.pause();
     Timer4.pause();
     Timer3.setCount(0);
     Timer4.setCount(0);
     Timer3.setOverflow(30000);
     Timer4.setOverflow(30000);
-    Timer3.setCompare1(1000);   // somewhere in the middle
-    Timer4.setCompare1(1000);   
-    Timer3.attachCompare1Interrupt(handler1);
-    Timer4.attachCompare1Interrupt(handler2);
+    Timer3.setCompare(TIMER_CH1, 1000);   // somewhere in the middle
+    Timer4.setCompare(TIMER_CH1, 1000);   
+    Timer3.attachInterrupt(TIMER_CH1, handler1);
+    Timer4.attachInterrupt(TIMER_CH1, handler2);
     Timer3.resume();
     Timer4.resume();
 

From bee82cb7c62be8b109a88c097d79fb9dc98ee206 Mon Sep 17 00:00:00 2001
From: victorpv <victor_pv@hotmail.com>
Date: Sun, 26 Nov 2017 09:29:15 -0600
Subject: [PATCH 242/307] Correct a bug in FreeRTOS

As listed in https://www.freertos.org/a00104.html#mailing_list:
"The definition of the StaticTask_t structure is incorrect if INCLUDE_xTaskAbortDelay is set to 1, or the MPU is used. The corrected structure definition can be obtained from here."
https://sourceforge.net/p/freertos/code/HEAD/tree/trunk/FreeRTOS/Source/include/FreeRTOS.h#l978
---
 STM32F1/libraries/FreeRTOS900/utility/FreeRTOS.h | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/STM32F1/libraries/FreeRTOS900/utility/FreeRTOS.h b/STM32F1/libraries/FreeRTOS900/utility/FreeRTOS.h
index f81172dbe..6838f4746 100644
--- a/STM32F1/libraries/FreeRTOS900/utility/FreeRTOS.h
+++ b/STM32F1/libraries/FreeRTOS900/utility/FreeRTOS.h
@@ -948,6 +948,9 @@ typedef struct xSTATIC_TCB
 	#if( ( configSUPPORT_STATIC_ALLOCATION == 1 ) && ( configSUPPORT_DYNAMIC_ALLOCATION == 1 ) )
 		uint8_t			uxDummy20;
 	#endif
+	#if( INCLUDE_xTaskAbortDelay == 1 )
+		uint8_t ucDummy21;
+	#endif
 
 } StaticTask_t;
 

From aebb14f26cd8fa90ad3a187085f165f46b7867de Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Fri, 1 Dec 2017 16:54:16 +0100
Subject: [PATCH 243/307] Rollback to master

---
 STM32F1/cores/maple/boards_private.h          |   2 +-
 STM32F1/variants/STM32VLD/board.cpp           | 109 ++++----
 STM32F1/variants/generic_gd32f103c/board.cpp  |  75 +++---
 STM32F1/variants/generic_stm32f103c/board.cpp |  76 +++---
 STM32F1/variants/generic_stm32f103r/board.cpp | 109 ++++----
 .../variants/generic_stm32f103r8/board.cpp    | 105 ++++----
 STM32F1/variants/generic_stm32f103t/board.cpp |  49 ++--
 STM32F1/variants/generic_stm32f103v/board.cpp | 167 ++++++-------
 STM32F1/variants/generic_stm32f103z/board.cpp | 234 +++++++++---------
 STM32F1/variants/hytiny_stm32f103t/board.cpp  |  49 ++--
 STM32F1/variants/maple_mini/board.cpp         |  70 +++---
 STM32F1/variants/maple_ret6/board.cpp         | 100 ++++----
 STM32F1/variants/microduino/board.cpp         |  54 ++--
 STM32F1/variants/nucleo_f103rb/board.cpp      |  94 +++----
 STM32F3/cores/maple/wirish/boards_private.h   |   2 +-
 15 files changed, 654 insertions(+), 641 deletions(-)

diff --git a/STM32F1/cores/maple/boards_private.h b/STM32F1/cores/maple/boards_private.h
index 332843ddf..49867ca77 100644
--- a/STM32F1/cores/maple/boards_private.h
+++ b/STM32F1/cores/maple/boards_private.h
@@ -42,7 +42,7 @@
 
 /* Makes the PIN_MAP rows more human-readable. */
 #define PMAP_ROW(gpio_dev, gpio_bit, timer_dev, timer_ch, adc_dev, adc_ch) \
-    { gpio_dev, timer_dev, adc_dev, gpio_bit, timer_ch, adc_ch, 0}
+    { gpio_dev, timer_dev, adc_dev, gpio_bit, timer_ch, adc_ch }
 
 namespace wirish {
     namespace priv {
diff --git a/STM32F1/variants/STM32VLD/board.cpp b/STM32F1/variants/STM32VLD/board.cpp
index 182e8f721..1cecbd932 100644
--- a/STM32F1/variants/STM32VLD/board.cpp
+++ b/STM32F1/variants/STM32VLD/board.cpp
@@ -51,66 +51,67 @@ void boardInit(void) {
 }
 
 // Note. See the enum of pin names in board.h
+
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
 
-    {&gpioa, &timer2, &adc1,  0, 1,    0, 0}, /* PA0 */
-    {&gpioa, &timer2, &adc1,  1, 2,    1, 0}, /* PA1 */
-    {&gpioa, &timer2, &adc1,  2, 3,    2, 0}, /* PA2 */
-    {&gpioa, &timer2, &adc1,  3, 4,    3, 0}, /* PA3 */
-    {&gpioa,   	NULL, &adc1,  4, 0,    4, 0}, /* PA4 */
-    {&gpioa,   	NULL, &adc1,  5, 0,    5, 0}, /* PA5 */
-    {&gpioa, &timer3, &adc1,  6, 1,    6, 0}, /* PA6 */
-    {&gpioa, &timer3, &adc1,  7, 2,    7, 0}, /* PA7 */
-    {&gpioa, &timer1, NULL,  8, 1, ADCx, 0}, /* PA8 */
-    {&gpioa, &timer1, NULL,  9, 2, ADCx, 0}, /* PA9 */
-    {&gpioa, &timer1, NULL, 10, 3, ADCx, 0}, /* PA10 */
-    {&gpioa,	NULL, NULL, 11, 0, ADCx, 0}, /* PA11 */
-    {&gpioa,   	NULL, NULL, 12, 0, ADCx, 0}, /* PA12 */
-    {&gpioa,   	NULL, NULL, 13, 0, ADCx, 0}, /* PA13 */
-    {&gpioa,   	NULL, NULL, 14, 0, ADCx, 0}, /* PA14 */
-    {&gpioa,   	NULL, NULL, 15, 0, ADCx, 0}, /* PA15 */
+    {&gpioa, &timer2, &adc1,  0, 1,    0}, /* PA0 */
+    {&gpioa, &timer2, &adc1,  1, 2,    1}, /* PA1 */
+    {&gpioa, &timer2, &adc1,  2, 3,    2}, /* PA2 */	
+    {&gpioa, &timer2, &adc1,  3, 4,    3}, /* PA3 */
+    {&gpioa,   	NULL, &adc1,  4, 0,    4}, /* PA4 */
+    {&gpioa,   	NULL, &adc1,  5, 0,    5}, /* PA5 */
+    {&gpioa, &timer3, &adc1,  6, 1,    6}, /* PA6 */
+    {&gpioa, &timer3, &adc1,  7, 2,    7}, /* PA7 */
+    {&gpioa, &timer1, NULL,  8, 1, ADCx}, /* PA8 */	
+    {&gpioa, &timer1, NULL,  9, 2, ADCx}, /* PA9 */	
+    {&gpioa, &timer1, NULL, 10, 3, ADCx}, /* PA10 */
+    {&gpioa,	NULL, NULL, 11, 0, ADCx}, /* PA11 */
+    {&gpioa,   	NULL, NULL, 12, 0, ADCx}, /* PA12 */	
+    {&gpioa,   	NULL, NULL, 13, 0, ADCx}, /* PA13 */	
+    {&gpioa,   	NULL, NULL, 14, 0, ADCx}, /* PA14 */
+    {&gpioa,   	NULL, NULL, 15, 0, ADCx}, /* PA15 */
 	
-    {&gpiob, &timer3, &adc1,  0, 3,    8, 0}, /* PB0 */
-    {&gpiob, &timer3, &adc1,  1, 4,    9, 0}, /* PB1 */
-    {&gpiob,   	NULL, NULL,  2, 0, ADCx, 0}, /* PB2 */
-    {&gpiob,   	NULL, NULL,  3, 0, ADCx, 0}, /* PB3 */
-    {&gpiob,   NULL, NULL,  4, 0, ADCx, 0}, /* PB4 */
-    {&gpiob,   NULL, NULL,  5, 0, ADCx, 0}, /* PB5 */
-    {&gpiob, &timer4, NULL,  6, 1, ADCx, 0}, /* PB6 */
-    {&gpiob, &timer4, NULL,  7, 2, ADCx, 0}, /* PB7 */
-    {&gpiob, &timer4, NULL,  8, 3, ADCx, 0}, /* PB8 */
-    {&gpiob, &timer4, NULL,  9, 4, ADCx, 0}, /* PB9 */
-    {&gpiob,   NULL, NULL, 10, 0, ADCx, 0}, /* PB10 */
-    {&gpiob,   NULL, NULL, 11, 0, ADCx, 0}, /* PB11 */
-    {&gpiob,   NULL, NULL, 12, 0, ADCx, 0}, /* PB12 */
-    {&gpiob,   NULL, NULL, 13, 0, ADCx, 0}, /* PB13 */
-    {&gpiob,   NULL, NULL, 14, 0, ADCx, 0}, /* PB14 */
-    {&gpiob,   NULL, NULL, 15, 0, ADCx, 0}, /* PB15 */
+    {&gpiob, &timer3, &adc1,  0, 3,    8}, /* PB0 */	
+    {&gpiob, &timer3, &adc1,  1, 4,    9}, /* PB1 */
+    {&gpiob,   	NULL, NULL,  2, 0, ADCx}, /* PB2 */
+    {&gpiob,   	NULL, NULL,  3, 0, ADCx}, /* PB3 */
+    {&gpiob,   NULL, NULL,  4, 0, ADCx}, /* PB4 */
+    {&gpiob,   NULL, NULL,  5, 0, ADCx}, /* PB5 */
+    {&gpiob, &timer4, NULL,  6, 1, ADCx}, /* PB6 */
+    {&gpiob, &timer4, NULL,  7, 2, ADCx}, /* PB7 */	
+    {&gpiob, &timer4, NULL,  8, 3, ADCx}, /* PB8 */	
+    {&gpiob, &timer4, NULL,  9, 4, ADCx}, /* PB9 */	
+    {&gpiob,   NULL, NULL, 10, 0, ADCx}, /* PB10 */	
+    {&gpiob,   NULL, NULL, 11, 0, ADCx}, /* PB11 */
+    {&gpiob,   NULL, NULL, 12, 0, ADCx}, /* PB12 */
+    {&gpiob,   NULL, NULL, 13, 0, ADCx}, /* PB13 */
+    {&gpiob,   NULL, NULL, 14, 0, ADCx}, /* PB14 */
+    {&gpiob,   NULL, NULL, 15, 0, ADCx}, /* PB15 */
 
 /* Andy Hull - the R8 is similar to the C8 but exposes more GPIO as follows */
-    {&gpioc,   NULL, &adc1, 0, 0, 10, 0},  /* PC0 */
-    {&gpioc,   NULL, &adc1, 1, 0, 11, 0},  /* PC1 */
-    {&gpioc,   NULL, &adc1, 2, 0, 12, 0},  /* PC2 */
-    {&gpioc,   NULL, &adc1, 3, 0, 13, 0},  /* PC3 */
-    {&gpioc,   NULL, &adc1, 4, 0, 14, 0},  /* PC4 */
-    {&gpioc,   NULL, &adc1, 5, 0, 15, 0},  /* PC5 */
-
-    {&gpioc,   NULL, NULL, 6, 0, ADCx, 0},  /* PC6 */
-    {&gpioc,   NULL, NULL, 7, 0, ADCx, 0},  /* PC7 */
-    {&gpioc,   NULL, NULL, 8, 0, ADCx, 0},  /* PC8 */
-    {&gpioc,   NULL, NULL, 9, 0, ADCx, 0},  /* PC9 */
-
-    {&gpioc,   NULL, NULL, 10, 0, ADCx, 0}, /* PC10 */
-    {&gpioc,   NULL, NULL, 11, 0, ADCx, 0}, /* PC11 */
-    {&gpioc,   NULL, NULL, 12, 0, ADCx, 0}, /* PC12 */
-    {&gpioc,   NULL, NULL, 13, 0, ADCx, 0}, /* PC13 */
-    {&gpioc,   NULL, NULL, 14, 0, ADCx, 0}, /* PC14 */
-    {&gpioc,   NULL, NULL, 15, 0, ADCx, 0}, /* PC15 */
-
-    {&gpiod,   NULL, NULL, 0, 0, ADCx, 0},  /* PD2 */
-	{&gpiod,   NULL, NULL, 1, 0, ADCx, 0},  /* PD2 */
-	{&gpiod,   NULL, NULL, 2, 0, ADCx, 0},  /* PD2 */
+    {&gpioc,   NULL, &adc1, 0, 0, 10},  /* PC0 */
+    {&gpioc,   NULL, &adc1, 1, 0, 11},  /* PC1 */
+    {&gpioc,   NULL, &adc1, 2, 0, 12},  /* PC2 */
+    {&gpioc,   NULL, &adc1, 3, 0, 13},  /* PC3 */
+    {&gpioc,   NULL, &adc1, 4, 0, 14},  /* PC4 */
+    {&gpioc,   NULL, &adc1, 5, 0, 15},  /* PC5 */
+
+    {&gpioc,   NULL, NULL, 6, 0, ADCx},  /* PC6 */
+    {&gpioc,   NULL, NULL, 7, 0, ADCx},  /* PC7 */
+    {&gpioc,   NULL, NULL, 8, 0, ADCx},  /* PC8 */
+    {&gpioc,   NULL, NULL, 9, 0, ADCx},  /* PC9 */
+
+    {&gpioc,   NULL, NULL, 10, 0, ADCx}, /* PC10 */
+    {&gpioc,   NULL, NULL, 11, 0, ADCx}, /* PC11 */
+    {&gpioc,   NULL, NULL, 12, 0, ADCx}, /* PC12 */
+    {&gpioc,   NULL, NULL, 13, 0, ADCx}, /* PC13 */	
+    {&gpioc,   NULL, NULL, 14, 0, ADCx}, /* PC14 */
+    {&gpioc,   NULL, NULL, 15, 0, ADCx}, /* PC15 */
+
+    {&gpiod,   NULL, NULL, 0, 0, ADCx},  /* PD2 */
+	{&gpiod,   NULL, NULL, 1, 0, ADCx},  /* PD2 */
+	{&gpiod,   NULL, NULL, 2, 0, ADCx},  /* PD2 */
 };
 
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
diff --git a/STM32F1/variants/generic_gd32f103c/board.cpp b/STM32F1/variants/generic_gd32f103c/board.cpp
index da22d526b..8b136f2a1 100644
--- a/STM32F1/variants/generic_gd32f103c/board.cpp
+++ b/STM32F1/variants/generic_gd32f103c/board.cpp
@@ -51,46 +51,49 @@ void boardInit(void) {
 }
 
 // Note. See the enum of pin names in board.h
+
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
 
-    {&gpioa, &timer2, &adc1,  0, 1,    0, 0}, /* PA0 */
-    {&gpioa, &timer2, &adc1,  1, 2,    1, 0}, /* PA1 */
-    {&gpioa, &timer2, &adc1,  2, 3,    2, 0}, /* PA2 */
-    {&gpioa, &timer2, &adc1,  3, 4,    3, 0}, /* PA3 */
-    {&gpioa,   NULL, &adc1,  4, 0,    4, 0}, /* PA4 */
-    {&gpioa,   NULL, &adc1,  5, 0,    5, 0}, /* PA5 */
-    {&gpioa, &timer3, &adc1,  6, 1,    6, 0}, /* PA6 */
-    {&gpioa, &timer3, &adc1,  7, 2,    7, 0}, /* PA7 */
-    {&gpioa, &timer1, NULL,  8, 1, ADCx, 0}, /* PA8 */
-    {&gpioa, &timer1, NULL,  9, 2, ADCx, 0}, /* PA9 */
-    {&gpioa, &timer1, NULL, 10, 3, ADCx, 0}, /* PA10 */
-    {&gpioa, &timer1, NULL, 11, 4, ADCx, 0}, /* PA11 */
-    {&gpioa,   NULL, NULL, 12, 0, ADCx, 0}, /* PA12 */
-    {&gpioa,   NULL, NULL, 13, 0, ADCx, 0}, /* PA13 */
-    {&gpioa,   NULL, NULL, 14, 0, ADCx, 0}, /* PA14 */
-    {&gpioa,   NULL, NULL, 15, 0, ADCx, 0}, /* PA15 */
+    {&gpioa, &timer2, &adc1,  0, 1,    0}, /* PA0 */
+    {&gpioa, &timer2, &adc1,  1, 2,    1}, /* PA1 */
+    {&gpioa, &timer2, &adc1,  2, 3,    2}, /* PA2 */	
+    {&gpioa, &timer2, &adc1,  3, 4,    3}, /* PA3 */
+    {&gpioa,   NULL, &adc1,  4, 0,    4}, /* PA4 */
+    {&gpioa,   NULL, &adc1,  5, 0,    5}, /* PA5 */
+    {&gpioa, &timer3, &adc1,  6, 1,    6}, /* PA6 */
+    {&gpioa, &timer3, &adc1,  7, 2,    7}, /* PA7 */
+    {&gpioa, &timer1, NULL,  8, 1, ADCx}, /* PA8 */	
+    {&gpioa, &timer1, NULL,  9, 2, ADCx}, /* PA9 */	
+    {&gpioa, &timer1, NULL, 10, 3, ADCx}, /* PA10 */
+    {&gpioa, &timer1, NULL, 11, 4, ADCx}, /* PA11 */
+    {&gpioa,   NULL, NULL, 12, 0, ADCx}, /* PA12 */	
+    {&gpioa,   NULL, NULL, 13, 0, ADCx}, /* PA13 */	
+    {&gpioa,   NULL, NULL, 14, 0, ADCx}, /* PA14 */
+    {&gpioa,   NULL, NULL, 15, 0, ADCx}, /* PA15 */
 	
-    {&gpiob, &timer3, &adc1,  0, 3,    8, 0}, /* PB0 */
-    {&gpiob, &timer3, &adc1,  1, 4,    9, 0}, /* PB1 */
-    {&gpiob,   NULL, NULL,  2, 0, ADCx, 0}, /* PB2 */
-    {&gpiob,   NULL, NULL,  3, 0, ADCx, 0}, /* PB3 */
-    {&gpiob,   NULL, NULL,  4, 0, ADCx, 0}, /* PB4 */
-    {&gpiob,   NULL, NULL,  5, 0, ADCx, 0}, /* PB5 */
-    {&gpiob, &timer4, NULL,  6, 1, ADCx, 0}, /* PB6 */
-    {&gpiob, &timer4, NULL,  7, 2, ADCx, 0}, /* PB7 */
-    {&gpiob, &timer4, NULL,  8, 3, ADCx, 0}, /* PB8 */
-    {&gpiob, &timer4, NULL,  9, 4, ADCx, 0}, /* PB9 */
-    {&gpiob,   NULL, NULL, 10, 0, ADCx, 0}, /* PB10 */
-    {&gpiob,   NULL, NULL, 11, 0, ADCx, 0}, /* PB11 */
-    {&gpiob,   NULL, NULL, 12, 0, ADCx, 0}, /* PB12 */
-    {&gpiob,   NULL, NULL, 13, 0, ADCx, 0}, /* PB13 */
-    {&gpiob,   NULL, NULL, 14, 0, ADCx, 0}, /* PB14 */
-    {&gpiob,   NULL, NULL, 15, 0, ADCx, 0}, /* PB15 */
-
-    {&gpioc,   NULL, NULL, 13, 0, ADCx, 0}, /* PC13 */
-    {&gpioc,   NULL, NULL, 14, 0, ADCx, 0}, /* PC14 */
-    {&gpioc,   NULL, NULL, 15, 0, ADCx, 0}, /* PC15 */
+    {&gpiob, &timer3, &adc1,  0, 3,    8}, /* PB0 */	
+    {&gpiob, &timer3, &adc1,  1, 4,    9}, /* PB1 */
+    {&gpiob,   NULL, NULL,  2, 0, ADCx}, /* PB2 */
+    {&gpiob,   NULL, NULL,  3, 0, ADCx}, /* PB3 */
+    {&gpiob,   NULL, NULL,  4, 0, ADCx}, /* PB4 */
+    {&gpiob,   NULL, NULL,  5, 0, ADCx}, /* PB5 */
+    {&gpiob, &timer4, NULL,  6, 1, ADCx}, /* PB6 */
+    {&gpiob, &timer4, NULL,  7, 2, ADCx}, /* PB7 */	
+    {&gpiob, &timer4, NULL,  8, 3, ADCx}, /* PB8 */	
+    {&gpiob, &timer4, NULL,  9, 4, ADCx}, /* PB9 */	
+    {&gpiob,   NULL, NULL, 10, 0, ADCx}, /* PB10 */	
+    {&gpiob,   NULL, NULL, 11, 0, ADCx}, /* PB11 */
+    {&gpiob,   NULL, NULL, 12, 0, ADCx}, /* PB12 */
+    {&gpiob,   NULL, NULL, 13, 0, ADCx}, /* PB13 */
+    {&gpiob,   NULL, NULL, 14, 0, ADCx}, /* PB14 */
+    {&gpiob,   NULL, NULL, 15, 0, ADCx}, /* PB15 */
+
+    {&gpioc,   NULL, NULL, 13, 0, ADCx}, /* PC13 */	
+    {&gpioc,   NULL, NULL, 14, 0, ADCx}, /* PC14 */
+    {&gpioc,   NULL, NULL, 15, 0, ADCx}, /* PC15 */
+
+
 
 };
 
diff --git a/STM32F1/variants/generic_stm32f103c/board.cpp b/STM32F1/variants/generic_stm32f103c/board.cpp
index 7b33ba858..7102adb9c 100644
--- a/STM32F1/variants/generic_stm32f103c/board.cpp
+++ b/STM32F1/variants/generic_stm32f103c/board.cpp
@@ -51,46 +51,50 @@ void boardInit(void) {
 }
 
 // Note. See the enum of pin names in board.h
+
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
 
-    {&gpioa, &timer2, &adc1,  0, 1,    0, 0}, /* PA0 */
-    {&gpioa, &timer2, &adc1,  1, 2,    1, 0}, /* PA1 */
-    {&gpioa, &timer2, &adc1,  2, 3,    2, 0}, /* PA2 */
-    {&gpioa, &timer2, &adc1,  3, 4,    3, 0}, /* PA3 */
-    {&gpioa,   NULL, &adc1,  4, 0,    4, 0}, /* PA4 */
-    {&gpioa,   NULL, &adc1,  5, 0,    5, 0}, /* PA5 */
-    {&gpioa, &timer3, &adc1,  6, 1,    6, 0}, /* PA6 */
-    {&gpioa, &timer3, &adc1,  7, 2,    7, 0}, /* PA7 */
-    {&gpioa, &timer1, NULL,  8, 1, ADCx, 0}, /* PA8 */
-    {&gpioa, &timer1, NULL,  9, 2, ADCx, 0}, /* PA9 */
-    {&gpioa, &timer1, NULL, 10, 3, ADCx, 0}, /* PA10 */
-    {&gpioa, &timer1, NULL, 11, 4, ADCx, 0}, /* PA11 */
-    {&gpioa,   NULL, NULL, 12, 0, ADCx, 0}, /* PA12 */
-    {&gpioa,   NULL, NULL, 13, 0, ADCx, 0}, /* PA13 */
-    {&gpioa,   NULL, NULL, 14, 0, ADCx, 0}, /* PA14 */
-    {&gpioa,   NULL, NULL, 15, 0, ADCx, 0}, /* PA15 */
+    {&gpioa, &timer2, &adc1,  0, 1,    0}, /* PA0 */
+    {&gpioa, &timer2, &adc1,  1, 2,    1}, /* PA1 */
+    {&gpioa, &timer2, &adc1,  2, 3,    2}, /* PA2 */	
+    {&gpioa, &timer2, &adc1,  3, 4,    3}, /* PA3 */
+    {&gpioa,   NULL, &adc1,  4, 0,    4}, /* PA4 */
+    {&gpioa,   NULL, &adc1,  5, 0,    5}, /* PA5 */
+    {&gpioa, &timer3, &adc1,  6, 1,    6}, /* PA6 */
+    {&gpioa, &timer3, &adc1,  7, 2,    7}, /* PA7 */
+    {&gpioa, &timer1, NULL,  8, 1, ADCx}, /* PA8 */	
+    {&gpioa, &timer1, NULL,  9, 2, ADCx}, /* PA9 */	
+    {&gpioa, &timer1, NULL, 10, 3, ADCx}, /* PA10 */
+    {&gpioa, &timer1, NULL, 11, 4, ADCx}, /* PA11 */
+    {&gpioa,   NULL, NULL, 12, 0, ADCx}, /* PA12 */	
+    {&gpioa,   NULL, NULL, 13, 0, ADCx}, /* PA13 */	
+    {&gpioa,   NULL, NULL, 14, 0, ADCx}, /* PA14 */
+    {&gpioa,   NULL, NULL, 15, 0, ADCx}, /* PA15 */
 	
-    {&gpiob, &timer3, &adc1,  0, 3,    8, 0}, /* PB0 */
-    {&gpiob, &timer3, &adc1,  1, 4,    9, 0}, /* PB1 */
-    {&gpiob,   NULL, NULL,  2, 0, ADCx, 0}, /* PB2 */
-    {&gpiob,   NULL, NULL,  3, 0, ADCx, 0}, /* PB3 */
-    {&gpiob,   NULL, NULL,  4, 0, ADCx, 0}, /* PB4 */
-    {&gpiob,   NULL, NULL,  5, 0, ADCx, 0}, /* PB5 */
-    {&gpiob, &timer4, NULL,  6, 1, ADCx, 0}, /* PB6 */
-    {&gpiob, &timer4, NULL,  7, 2, ADCx, 0}, /* PB7 */
-    {&gpiob, &timer4, NULL,  8, 3, ADCx, 0}, /* PB8 */
-    {&gpiob, &timer4, NULL,  9, 4, ADCx, 0}, /* PB9 */
-    {&gpiob,   NULL, NULL, 10, 0, ADCx, 0}, /* PB10 */
-    {&gpiob,   NULL, NULL, 11, 0, ADCx, 0}, /* PB11 */
-    {&gpiob,   NULL, NULL, 12, 0, ADCx, 0}, /* PB12 */
-    {&gpiob,   NULL, NULL, 13, 0, ADCx, 0}, /* PB13 */
-    {&gpiob,   NULL, NULL, 14, 0, ADCx, 0}, /* PB14 */
-    {&gpiob,   NULL, NULL, 15, 0, ADCx, 0}, /* PB15 */
-
-    {&gpioc,   NULL, NULL, 13, 0, ADCx, 0}, /* PC13 */
-    {&gpioc,   NULL, NULL, 14, 0, ADCx, 0}, /* PC14 */
-    {&gpioc,   NULL, NULL, 15, 0, ADCx, 0}, /* PC15 */
+    {&gpiob, &timer3, &adc1,  0, 3,    8}, /* PB0 */	
+    {&gpiob, &timer3, &adc1,  1, 4,    9}, /* PB1 */
+    {&gpiob,   NULL, NULL,  2, 0, ADCx}, /* PB2 */
+    {&gpiob,   NULL, NULL,  3, 0, ADCx}, /* PB3 */
+    {&gpiob,   NULL, NULL,  4, 0, ADCx}, /* PB4 */
+    {&gpiob,   NULL, NULL,  5, 0, ADCx}, /* PB5 */
+    {&gpiob, &timer4, NULL,  6, 1, ADCx}, /* PB6 */
+    {&gpiob, &timer4, NULL,  7, 2, ADCx}, /* PB7 */	
+    {&gpiob, &timer4, NULL,  8, 3, ADCx}, /* PB8 */	
+    {&gpiob, &timer4, NULL,  9, 4, ADCx}, /* PB9 */	
+    {&gpiob,   NULL, NULL, 10, 0, ADCx}, /* PB10 */	
+    {&gpiob,   NULL, NULL, 11, 0, ADCx}, /* PB11 */
+    {&gpiob,   NULL, NULL, 12, 0, ADCx}, /* PB12 */
+    {&gpiob,   NULL, NULL, 13, 0, ADCx}, /* PB13 */
+    {&gpiob,   NULL, NULL, 14, 0, ADCx}, /* PB14 */
+    {&gpiob,   NULL, NULL, 15, 0, ADCx}, /* PB15 */
+
+    {&gpioc,   NULL, NULL, 13, 0, ADCx}, /* PC13 */	
+    {&gpioc,   NULL, NULL, 14, 0, ADCx}, /* PC14 */
+    {&gpioc,   NULL, NULL, 15, 0, ADCx}, /* PC15 */
+
+
+
 };
 
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
diff --git a/STM32F1/variants/generic_stm32f103r/board.cpp b/STM32F1/variants/generic_stm32f103r/board.cpp
index e564425d0..3e3589c23 100644
--- a/STM32F1/variants/generic_stm32f103r/board.cpp
+++ b/STM32F1/variants/generic_stm32f103r/board.cpp
@@ -69,6 +69,7 @@ void boardInit(void) {
 // - Timer channel (1 to 4, for PWM), or 0 if none
 // - ADC device, or NULL if none
 // - ADC channel, or ADCx if none
+
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 /*
     gpio_dev *gpio_device;      GPIO device 
@@ -80,61 +81,61 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 	uint8 pinMode; 				mode specific by pinMode call (Roger Clark added to optimize compatibility with Arduino API
 */
 
-    {&gpioa, &timer2, &adc1,  0, 1,    0, 0}, /* PA0 */
-    {&gpioa, &timer2, &adc1,  1, 2,    1, 0}, /* PA1 */
-	{&gpioa, &timer2, &adc1,  2, 3,    2, 0}, /* PA2 */
-    {&gpioa, &timer2, &adc1,  3, 4,    3, 0}, /* PA3 */
-	{&gpioa,   NULL, &adc1,  4, 0,    4, 0}, /* PA4 */
-    {&gpioa,   NULL, &adc1,  5, 0,    5, 0}, /* PA5 */
-    {&gpioa, &timer3, &adc1,  6, 1,    6, 0}, /* PA6 */
-    {&gpioa, &timer3, &adc1,  7, 2,    7, 0}, /* PA7 */
-    {&gpioa, &timer1, NULL,  8, 1, ADCx, 0}, /* PA8 */
-    {&gpioa, &timer1, NULL,  9, 2, ADCx, 0}, /* PA9 */
-    {&gpioa, &timer1, NULL, 10, 3, ADCx, 0}, /* PA10 */
-    {&gpioa,   NULL, NULL, 11, 0, ADCx, 0}, /* PA11 */
-    {&gpioa,   NULL, NULL, 12, 0, ADCx, 0}, /* PA12 */
-    {&gpioa,   NULL, NULL, 13, 0, ADCx, 0}, /* PA13 */
-    {&gpioa,   NULL, NULL, 14, 0, ADCx, 0}, /* PA14 */
-    {&gpioa,   NULL, NULL, 15, 0, ADCx, 0}, /* PA15 */
+    {&gpioa, &timer2, &adc1,  0, 1,    0}, /* PA0 */
+    {&gpioa, &timer2, &adc1,  1, 2,    1}, /* PA1 */
+	{&gpioa, &timer2, &adc1,  2, 3,    2}, /* PA2 */
+    {&gpioa, &timer2, &adc1,  3, 4,    3}, /* PA3 */
+	{&gpioa,   NULL, &adc1,  4, 0,    4}, /* PA4 */	
+    {&gpioa,   NULL, &adc1,  5, 0,    5}, /* PA5 */
+    {&gpioa, &timer3, &adc1,  6, 1,    6}, /* PA6 */
+    {&gpioa, &timer3, &adc1,  7, 2,    7}, /* PA7 */
+    {&gpioa, &timer1, NULL,  8, 1, ADCx}, /* PA8 */
+    {&gpioa, &timer1, NULL,  9, 2, ADCx}, /* PA9 */
+    {&gpioa, &timer1, NULL, 10, 3, ADCx}, /* PA10 */
+    {&gpioa,   NULL, NULL, 11, 0, ADCx}, /* PA11 */
+    {&gpioa,   NULL, NULL, 12, 0, ADCx}, /* PA12 */	
+    {&gpioa,   NULL, NULL, 13, 0, ADCx}, /* PA13 */
+    {&gpioa,   NULL, NULL, 14, 0, ADCx}, /* PA14 */
+    {&gpioa,   NULL, NULL, 15, 0, ADCx}, /* PA15 */
 	
-	{&gpiob, &timer3, &adc1,  0, 3,    8, 0}, /* PB0 */
-	{&gpiob, &timer3, &adc1,  1, 4,    9, 0}, /* PB1 */
-	{&gpiob,   NULL, NULL,  2, 0, ADCx, 0}, /* PB2  */
-	{&gpiob,   NULL, NULL,  3, 0, ADCx, 0}, /* PB3  */
-    {&gpiob,   NULL, NULL,  4, 0, ADCx, 0}, /* PB4  */
-    {&gpiob,   NULL, NULL,  5, 0, ADCx, 0}, /* PB5 */
-    {&gpiob, &timer4, NULL,  6, 1, ADCx, 0}, /* PB6 */
-    {&gpiob, &timer4, NULL,  7, 2, ADCx, 0}, /* PB7 */
-    {&gpiob, &timer4, NULL,  8, 3, ADCx, 0}, /* PB8 */
-	{&gpiob,   NULL, NULL,  9, 0, ADCx, 0}, /* PB9 */
-    {&gpiob,   NULL, NULL, 10, 0, ADCx, 0}, /* PB10 */
-    {&gpiob,   NULL, NULL, 11, 0, ADCx, 0}, /* PB11 */
-    {&gpiob,   NULL, NULL, 12, 0, ADCx, 0}, /* PB12 */
-    {&gpiob,   NULL, NULL, 13, 0, ADCx, 0}, /* PB13 */
-    {&gpiob,   NULL, NULL, 14, 0, ADCx, 0}, /* PB14 */
-    {&gpiob,   NULL, NULL, 15, 0, ADCx, 0}, /* PB15 */
-
-
-    {&gpioc,   NULL, &adc1,  0, 0,   10, 0}, /* PC0 */
-    {&gpioc,   NULL, &adc1,  1, 0,   11, 0}, /* PC1 */
-    {&gpioc,   NULL, &adc1,  2, 0,   12, 0}, /* PC2 */
-    {&gpioc,   NULL, &adc1,  3, 0,   13, 0}, /* PC3 */
-    {&gpioc,   NULL, &adc1,  4, 0,   14, 0}, /* PC4 */
-    {&gpioc,   NULL, &adc1,  5, 0,   15, 0}, /* PC5 */
-    {&gpioc, &timer8, NULL,  6, 1, ADCx, 0}, /* PC6 */
-	{&gpioc, &timer8, NULL,  7, 2, ADCx, 0}, /* PC7 */
-    {&gpioc, &timer8, NULL,  8, 3, ADCx, 0}, /* PC8 */
-    {&gpioc, &timer8, NULL,  9, 4, ADCx, 0}, /* PC9 */
-    {&gpioc,   NULL, NULL, 10, 0, ADCx, 0}, /* PC10 UART4_TX/SDIO_D2 */
-    {&gpioc,   NULL, NULL, 11, 0, ADCx, 0}, /* PC11 UART4_RX/SDIO_D3 */
-    {&gpioc,   NULL, NULL, 12, 0, ADCx, 0}, /* PC12 UART5_TX/SDIO_CK */
-    {&gpioc,   NULL, NULL, 13, 0, ADCx, 0}, /* PC13 TAMPER-RTC */
-    {&gpioc,   NULL, NULL, 14, 0, ADCx, 0}, /* PC14 OSC32_IN */
-    {&gpioc,   NULL, NULL, 15, 0, ADCx, 0}, /* PC15 OSC32_OUT */
-
-	{&gpiod,   NULL, NULL,   0, 0, ADCx, 0} , /* PD0 OSC_IN */
-	{&gpiod,   NULL, NULL,   1, 0, ADCx, 0} , /* PD1  OSC_OUT */
-	{&gpiod,   NULL, NULL,   2, 0, ADCx, 0} , /* PD2  TIM3_ETR/UART5_RX SDIO_CMD */
+	{&gpiob, &timer3, &adc1,  0, 3,    8}, /* PB0 */
+	{&gpiob, &timer3, &adc1,  1, 4,    9}, /* PB1 */
+	{&gpiob,   NULL, NULL,  2, 0, ADCx}, /* PB2  */	
+	{&gpiob,   NULL, NULL,  3, 0, ADCx}, /* PB3  */
+    {&gpiob,   NULL, NULL,  4, 0, ADCx}, /* PB4  */
+    {&gpiob,   NULL, NULL,  5, 0, ADCx}, /* PB5 */
+    {&gpiob, &timer4, NULL,  6, 1, ADCx}, /* PB6 */
+    {&gpiob, &timer4, NULL,  7, 2, ADCx}, /* PB7 */
+    {&gpiob, &timer4, NULL,  8, 3, ADCx}, /* PB8 */
+	{&gpiob,   NULL, NULL,  9, 0, ADCx}, /* PB9 */
+    {&gpiob,   NULL, NULL, 10, 0, ADCx}, /* PB10 */
+    {&gpiob,   NULL, NULL, 11, 0, ADCx}, /* PB11 */
+    {&gpiob,   NULL, NULL, 12, 0, ADCx}, /* PB12 */
+    {&gpiob,   NULL, NULL, 13, 0, ADCx}, /* PB13 */
+    {&gpiob,   NULL, NULL, 14, 0, ADCx}, /* PB14 */
+    {&gpiob,   NULL, NULL, 15, 0, ADCx}, /* PB15 */
+
+
+    {&gpioc,   NULL, &adc1,  0, 0,   10}, /* PC0 */
+    {&gpioc,   NULL, &adc1,  1, 0,   11}, /* PC1 */
+    {&gpioc,   NULL, &adc1,  2, 0,   12}, /* PC2 */
+    {&gpioc,   NULL, &adc1,  3, 0,   13}, /* PC3 */
+    {&gpioc,   NULL, &adc1,  4, 0,   14}, /* PC4 */
+    {&gpioc,   NULL, &adc1,  5, 0,   15}, /* PC5 */
+    {&gpioc, &timer8, NULL,  6, 1, ADCx}, /* PC6 */	
+	{&gpioc, &timer8, NULL,  7, 2, ADCx}, /* PC7 */
+    {&gpioc, &timer8, NULL,  8, 3, ADCx}, /* PC8 */
+    {&gpioc, &timer8, NULL,  9, 4, ADCx}, /* PC9 */
+    {&gpioc,   NULL, NULL, 10, 0, ADCx}, /* PC10 UART4_TX/SDIO_D2 */
+    {&gpioc,   NULL, NULL, 11, 0, ADCx}, /* PC11 UART4_RX/SDIO_D3 */
+    {&gpioc,   NULL, NULL, 12, 0, ADCx}, /* PC12 UART5_TX/SDIO_CK */	
+    {&gpioc,   NULL, NULL, 13, 0, ADCx}, /* PC13 TAMPER-RTC */
+    {&gpioc,   NULL, NULL, 14, 0, ADCx}, /* PC14 OSC32_IN */
+    {&gpioc,   NULL, NULL, 15, 0, ADCx}, /* PC15 OSC32_OUT */
+
+	{&gpiod,   NULL, NULL,   0, 0, ADCx} , /* PD0 OSC_IN */
+	{&gpiod,   NULL, NULL,   1, 0, ADCx} , /* PD1  OSC_OUT */
+	{&gpiod,   NULL, NULL,   2, 0, ADCx} , /* PD2  TIM3_ETR/UART5_RX SDIO_CMD */
 };
 
 /*  Basically everything that is defined as having a timer us PWM */
diff --git a/STM32F1/variants/generic_stm32f103r8/board.cpp b/STM32F1/variants/generic_stm32f103r8/board.cpp
index f667d2fe7..05f85a5cc 100644
--- a/STM32F1/variants/generic_stm32f103r8/board.cpp
+++ b/STM32F1/variants/generic_stm32f103r8/board.cpp
@@ -51,64 +51,65 @@ void boardInit(void) {
 }
 
 // Note. See the enum of pin names in board.h
+
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
 
-    {&gpioa, &timer2, &adc1,  0, 1,    0, 0}, /* PA0 */
-    {&gpioa, &timer2, &adc1,  1, 2,    1, 0}, /* PA1 */
-    {&gpioa, &timer2, &adc1,  2, 3,    2, 0}, /* PA2 */
-    {&gpioa, &timer2, &adc1,  3, 4,    3, 0}, /* PA3 */
-    {&gpioa,   NULL, &adc1,  4, 0,    4, 0}, /* PA4 */
-    {&gpioa,   NULL, &adc1,  5, 0,    5, 0}, /* PA5 */
-    {&gpioa, &timer3, &adc1,  6, 1,    6, 0}, /* PA6 */
-    {&gpioa, &timer3, &adc1,  7, 2,    7, 0}, /* PA7 */
-    {&gpioa, &timer1, NULL,  8, 1, ADCx, 0}, /* PA8 */
-    {&gpioa, &timer1, NULL,  9, 2, ADCx, 0}, /* PA9 */
-    {&gpioa, &timer1, NULL, 10, 3, ADCx, 0}, /* PA10 */
-    {&gpioa, &timer1, NULL, 11, 4, ADCx, 0}, /* PA11 */
-    {&gpioa,   NULL, NULL, 12, 0, ADCx, 0}, /* PA12 */
-    {&gpioa,   NULL, NULL, 13, 0, ADCx, 0}, /* PA13 */
-    {&gpioa,   NULL, NULL, 14, 0, ADCx, 0}, /* PA14 */
-    {&gpioa,   NULL, NULL, 15, 0, ADCx, 0}, /* PA15 */
+    {&gpioa, &timer2, &adc1,  0, 1,    0}, /* PA0 */
+    {&gpioa, &timer2, &adc1,  1, 2,    1}, /* PA1 */
+    {&gpioa, &timer2, &adc1,  2, 3,    2}, /* PA2 */	
+    {&gpioa, &timer2, &adc1,  3, 4,    3}, /* PA3 */
+    {&gpioa,   NULL, &adc1,  4, 0,    4}, /* PA4 */
+    {&gpioa,   NULL, &adc1,  5, 0,    5}, /* PA5 */
+    {&gpioa, &timer3, &adc1,  6, 1,    6}, /* PA6 */
+    {&gpioa, &timer3, &adc1,  7, 2,    7}, /* PA7 */
+    {&gpioa, &timer1, NULL,  8, 1, ADCx}, /* PA8 */	
+    {&gpioa, &timer1, NULL,  9, 2, ADCx}, /* PA9 */	
+    {&gpioa, &timer1, NULL, 10, 3, ADCx}, /* PA10 */
+    {&gpioa, &timer1, NULL, 11, 4, ADCx}, /* PA11 */
+    {&gpioa,   NULL, NULL, 12, 0, ADCx}, /* PA12 */	
+    {&gpioa,   NULL, NULL, 13, 0, ADCx}, /* PA13 */	
+    {&gpioa,   NULL, NULL, 14, 0, ADCx}, /* PA14 */
+    {&gpioa,   NULL, NULL, 15, 0, ADCx}, /* PA15 */
 	
-    {&gpiob, &timer3, &adc1,  0, 3,    8, 0}, /* PB0 */
-    {&gpiob, &timer3, &adc1,  1, 4,    9, 0}, /* PB1 */
-    {&gpiob,   NULL, NULL,  2, 0, ADCx, 0}, /* PB2 */
-    {&gpiob,   NULL, NULL,  3, 0, ADCx, 0}, /* PB3 */
-    {&gpiob,   NULL, NULL,  4, 0, ADCx, 0}, /* PB4 */
-    {&gpiob,   NULL, NULL,  5, 0, ADCx, 0}, /* PB5 */
-    {&gpiob, &timer4, NULL,  6, 1, ADCx, 0}, /* PB6 */
-    {&gpiob, &timer4, NULL,  7, 2, ADCx, 0}, /* PB7 */
-    {&gpiob, &timer4, NULL,  8, 3, ADCx, 0}, /* PB8 */
-    {&gpiob, &timer4, NULL,  9, 4, ADCx, 0}, /* PB9 */
-    {&gpiob,   NULL, NULL, 10, 0, ADCx, 0}, /* PB10 */
-    {&gpiob,   NULL, NULL, 11, 0, ADCx, 0}, /* PB11 */
-    {&gpiob,   NULL, NULL, 12, 0, ADCx, 0}, /* PB12 */
-    {&gpiob,   NULL, NULL, 13, 0, ADCx, 0}, /* PB13 */
-    {&gpiob,   NULL, NULL, 14, 0, ADCx, 0}, /* PB14 */
-    {&gpiob,   NULL, NULL, 15, 0, ADCx, 0}, /* PB15 */
+    {&gpiob, &timer3, &adc1,  0, 3,    8}, /* PB0 */	
+    {&gpiob, &timer3, &adc1,  1, 4,    9}, /* PB1 */
+    {&gpiob,   NULL, NULL,  2, 0, ADCx}, /* PB2 */
+    {&gpiob,   NULL, NULL,  3, 0, ADCx}, /* PB3 */
+    {&gpiob,   NULL, NULL,  4, 0, ADCx}, /* PB4 */
+    {&gpiob,   NULL, NULL,  5, 0, ADCx}, /* PB5 */
+    {&gpiob, &timer4, NULL,  6, 1, ADCx}, /* PB6 */
+    {&gpiob, &timer4, NULL,  7, 2, ADCx}, /* PB7 */	
+    {&gpiob, &timer4, NULL,  8, 3, ADCx}, /* PB8 */	
+    {&gpiob, &timer4, NULL,  9, 4, ADCx}, /* PB9 */	
+    {&gpiob,   NULL, NULL, 10, 0, ADCx}, /* PB10 */	
+    {&gpiob,   NULL, NULL, 11, 0, ADCx}, /* PB11 */
+    {&gpiob,   NULL, NULL, 12, 0, ADCx}, /* PB12 */
+    {&gpiob,   NULL, NULL, 13, 0, ADCx}, /* PB13 */
+    {&gpiob,   NULL, NULL, 14, 0, ADCx}, /* PB14 */
+    {&gpiob,   NULL, NULL, 15, 0, ADCx}, /* PB15 */
 
 /* Andy Hull - the R8 is similar to the C8 but exposes more GPIO as follows */
-    {&gpioc,   NULL, &adc1, 0, 0, 10, 0},  /* PC0 */
-    {&gpioc,   NULL, &adc1, 1, 0, 11, 0},  /* PC1 */
-    {&gpioc,   NULL, &adc1, 2, 0, 12, 0},  /* PC2 */
-    {&gpioc,   NULL, &adc1, 3, 0, 13, 0},  /* PC3 */
-    {&gpioc,   NULL, &adc1, 4, 0, 14, 0},  /* PC4 */
-    {&gpioc,   NULL, &adc1, 5, 0, 15, 0},  /* PC5 */
-
-    {&gpioc,   NULL, NULL, 6, 0, ADCx, 0},  /* PC6 */
-    {&gpioc,   NULL, NULL, 7, 0, ADCx, 0},  /* PC7 */
-    {&gpioc,   NULL, NULL, 8, 0, ADCx, 0},  /* PC8 */
-    {&gpioc,   NULL, NULL, 9, 0, ADCx, 0},  /* PC9 */
-
-    {&gpioc,   NULL, NULL, 10, 0, ADCx, 0}, /* PC10 */
-    {&gpioc,   NULL, NULL, 11, 0, ADCx, 0}, /* PC11 */
-    {&gpioc,   NULL, NULL, 12, 0, ADCx, 0}, /* PC12 */
-    {&gpioc,   NULL, NULL, 13, 0, ADCx, 0}, /* PC13 */
-    {&gpioc,   NULL, NULL, 14, 0, ADCx, 0}, /* PC14 */
-    {&gpioc,   NULL, NULL, 15, 0, ADCx, 0}, /* PC15 */
-
-    {&gpiod,   NULL, NULL, 2, 0, ADCx, 0},  /* PD2 */
+    {&gpioc,   NULL, &adc1, 0, 0, 10},  /* PC0 */
+    {&gpioc,   NULL, &adc1, 1, 0, 11},  /* PC1 */
+    {&gpioc,   NULL, &adc1, 2, 0, 12},  /* PC2 */
+    {&gpioc,   NULL, &adc1, 3, 0, 13},  /* PC3 */
+    {&gpioc,   NULL, &adc1, 4, 0, 14},  /* PC4 */
+    {&gpioc,   NULL, &adc1, 5, 0, 15},  /* PC5 */
+
+    {&gpioc,   NULL, NULL, 6, 0, ADCx},  /* PC6 */
+    {&gpioc,   NULL, NULL, 7, 0, ADCx},  /* PC7 */
+    {&gpioc,   NULL, NULL, 8, 0, ADCx},  /* PC8 */
+    {&gpioc,   NULL, NULL, 9, 0, ADCx},  /* PC9 */
+
+    {&gpioc,   NULL, NULL, 10, 0, ADCx}, /* PC10 */
+    {&gpioc,   NULL, NULL, 11, 0, ADCx}, /* PC11 */
+    {&gpioc,   NULL, NULL, 12, 0, ADCx}, /* PC12 */
+    {&gpioc,   NULL, NULL, 13, 0, ADCx}, /* PC13 */	
+    {&gpioc,   NULL, NULL, 14, 0, ADCx}, /* PC14 */
+    {&gpioc,   NULL, NULL, 15, 0, ADCx}, /* PC15 */
+
+    {&gpiod,   NULL, NULL, 2, 0, ADCx},  /* PD2 */
 };
 
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
diff --git a/STM32F1/variants/generic_stm32f103t/board.cpp b/STM32F1/variants/generic_stm32f103t/board.cpp
index 85c252c4d..e7a1dc0e0 100644
--- a/STM32F1/variants/generic_stm32f103t/board.cpp
+++ b/STM32F1/variants/generic_stm32f103t/board.cpp
@@ -51,34 +51,35 @@ void boardInit(void) {
 }
 
 // Note. See the enum of pin names in board.h
+
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
 
-    {&gpioa, &timer2, &adc1,  0, 1,    0, 0}, /* PA0 */
-    {&gpioa, &timer2, &adc1,  1, 2,    1, 0}, /* PA1 */
-    {&gpioa, &timer2, &adc1,  2, 3,    2, 0}, /* PA2 */
-    {&gpioa, &timer2, &adc1,  3, 4,    3, 0}, /* PA3 */
-    {&gpioa,   NULL, &adc1,  4, 0,    4, 0}, /* PA4 */
-    {&gpioa,   NULL, &adc1,  5, 0,    5, 0}, /* PA5 */
-    {&gpioa, &timer3, &adc1,  6, 1,    6, 0}, /* PA6 */
-    {&gpioa, &timer3, &adc1,  7, 2,    7, 0}, /* PA7 */
-    {&gpioa, &timer1, NULL,  8, 1, ADCx, 0}, /* PA8 */
-    {&gpioa, &timer1, NULL,  9, 2, ADCx, 0}, /* PA9 */
-    {&gpioa, &timer1, NULL, 10, 3, ADCx, 0}, /* PA10 */
-    {&gpioa, &timer1, NULL, 11, 4, ADCx, 0}, /* PA11 */
-    {&gpioa,   NULL, NULL, 12, 0, ADCx, 0}, /* PA12 */
-    {&gpioa,   NULL, NULL, 13, 0, ADCx, 0}, /* PA13 */
-    {&gpioa,   NULL, NULL, 14, 0, ADCx, 0}, /* PA14 */
-    {&gpioa,   NULL, NULL, 15, 0, ADCx, 0}, /* PA15 */
+    {&gpioa, &timer2, &adc1,  0, 1,    0}, /* PA0 */
+    {&gpioa, &timer2, &adc1,  1, 2,    1}, /* PA1 */
+    {&gpioa, &timer2, &adc1,  2, 3,    2}, /* PA2 */	
+    {&gpioa, &timer2, &adc1,  3, 4,    3}, /* PA3 */
+    {&gpioa,   NULL, &adc1,  4, 0,    4}, /* PA4 */
+    {&gpioa,   NULL, &adc1,  5, 0,    5}, /* PA5 */
+    {&gpioa, &timer3, &adc1,  6, 1,    6}, /* PA6 */
+    {&gpioa, &timer3, &adc1,  7, 2,    7}, /* PA7 */
+    {&gpioa, &timer1, NULL,  8, 1, ADCx}, /* PA8 */	
+    {&gpioa, &timer1, NULL,  9, 2, ADCx}, /* PA9 */	
+    {&gpioa, &timer1, NULL, 10, 3, ADCx}, /* PA10 */
+    {&gpioa, &timer1, NULL, 11, 4, ADCx}, /* PA11 */
+    {&gpioa,   NULL, NULL, 12, 0, ADCx}, /* PA12 */	
+    {&gpioa,   NULL, NULL, 13, 0, ADCx}, /* PA13 */	
+    {&gpioa,   NULL, NULL, 14, 0, ADCx}, /* PA14 */
+    {&gpioa,   NULL, NULL, 15, 0, ADCx}, /* PA15 */
 	
-    {&gpiob, &timer3, &adc1,  0, 3,    8, 0}, /* PB0 */
-    {&gpiob, &timer3, &adc1,  1, 4,    9, 0}, /* PB1 */
-    {&gpiob,   NULL, NULL,  2, 0, ADCx, 0}, /* PB2 */
-    {&gpiob,   NULL, NULL,  3, 0, ADCx, 0}, /* PB3 */
-    {&gpiob,   NULL, NULL,  4, 0, ADCx, 0}, /* PB4 */
-    {&gpiob,   NULL, NULL,  5, 0, ADCx, 0}, /* PB5 */
-    {&gpiob, &timer4, NULL,  6, 1, ADCx, 0}, /* PB6 */
-    {&gpiob, &timer4, NULL,  7, 2, ADCx, 0}, /* PB7 */
+    {&gpiob, &timer3, &adc1,  0, 3,    8}, /* PB0 */	
+    {&gpiob, &timer3, &adc1,  1, 4,    9}, /* PB1 */
+    {&gpiob,   NULL, NULL,  2, 0, ADCx}, /* PB2 */
+    {&gpiob,   NULL, NULL,  3, 0, ADCx}, /* PB3 */
+    {&gpiob,   NULL, NULL,  4, 0, ADCx}, /* PB4 */
+    {&gpiob,   NULL, NULL,  5, 0, ADCx}, /* PB5 */
+    {&gpiob, &timer4, NULL,  6, 1, ADCx}, /* PB6 */
+    {&gpiob, &timer4, NULL,  7, 2, ADCx}, /* PB7 */	
 };
 
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
diff --git a/STM32F1/variants/generic_stm32f103v/board.cpp b/STM32F1/variants/generic_stm32f103v/board.cpp
index a6b31655e..9c137725a 100644
--- a/STM32F1/variants/generic_stm32f103v/board.cpp
+++ b/STM32F1/variants/generic_stm32f103v/board.cpp
@@ -68,6 +68,7 @@ void boardInit(void) {
 // - Timer channel (1 to 4, for PWM), or 0 if none
 // - ADC device, or NULL if none
 // - ADC channel, or ADCx if none
+
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 /*
     gpio_dev *gpio_device;      GPIO device 
@@ -78,91 +79,91 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
     uint8 adc_channel;          Pin ADC channel, or ADCx if none. 
 */
 
-    {&gpioa, &timer2, &adc1,  0, 1,    0, 0}, /* PA0 */
-    {&gpioa, &timer2, &adc1,  1, 2,    1, 0}, /* PA1 */
-	{&gpioa, &timer2, &adc1,  2, 3,    2, 0}, /* PA2 */
-    {&gpioa, &timer2, &adc1,  3, 4,    3, 0}, /* PA3 */
-	{&gpioa,   NULL, &adc1,  4, 0,    4, 0}, /* PA4 */
-    {&gpioa,   NULL, &adc1,  5, 0,    5, 0}, /* PA5 */
-    {&gpioa, &timer3, &adc1,  6, 1,    6, 0}, /* PA6 */
-    {&gpioa, &timer3, &adc1,  7, 2,    7, 0}, /* PA7 */
-    {&gpioa, &timer1, NULL,  8, 1, ADCx, 0}, /* PA8 */
-    {&gpioa, &timer1, NULL,  9, 2, ADCx, 0}, /* PA9 */
-    {&gpioa, &timer1, NULL, 10, 3, ADCx, 0}, /* PA10 */
-    {&gpioa,   NULL, NULL, 11, 0, ADCx, 0}, /* PA11 */ //Could have &timer1_CH4, but is also CAN_RX and USBDM
-    {&gpioa,   NULL, NULL, 12, 0, ADCx, 0}, /* PA12 */ //Could have &timer1_ETR, but is also CAN_TX and USBDP
-    {&gpioa,   NULL, NULL, 13, 0, ADCx, 0}, /* PA13 */
-    {&gpioa,   NULL, NULL, 14, 0, ADCx, 0}, /* PA14 */
-    {&gpioa,   NULL, NULL, 15, 0, ADCx, 0}, /* PA15 */ //SPI3_NSS
+    {&gpioa, &timer2, &adc1,  0, 1,    0}, /* PA0 */
+    {&gpioa, &timer2, &adc1,  1, 2,    1}, /* PA1 */
+	{&gpioa, &timer2, &adc1,  2, 3,    2}, /* PA2 */
+    {&gpioa, &timer2, &adc1,  3, 4,    3}, /* PA3 */
+	{&gpioa,   NULL, &adc1,  4, 0,    4}, /* PA4 */	
+    {&gpioa,   NULL, &adc1,  5, 0,    5}, /* PA5 */
+    {&gpioa, &timer3, &adc1,  6, 1,    6}, /* PA6 */
+    {&gpioa, &timer3, &adc1,  7, 2,    7}, /* PA7 */
+    {&gpioa, &timer1, NULL,  8, 1, ADCx}, /* PA8 */
+    {&gpioa, &timer1, NULL,  9, 2, ADCx}, /* PA9 */
+    {&gpioa, &timer1, NULL, 10, 3, ADCx}, /* PA10 */
+    {&gpioa,   NULL, NULL, 11, 0, ADCx}, /* PA11 */ //Could have &timer1_CH4, but is also CAN_RX and USBDM 
+    {&gpioa,   NULL, NULL, 12, 0, ADCx}, /* PA12 */ //Could have &timer1_ETR, but is also CAN_TX and USBDP
+    {&gpioa,   NULL, NULL, 13, 0, ADCx}, /* PA13 */
+    {&gpioa,   NULL, NULL, 14, 0, ADCx}, /* PA14 */
+    {&gpioa,   NULL, NULL, 15, 0, ADCx}, /* PA15 */ //SPI3_NSS 
 	
-	{&gpiob, &timer3, &adc1,  0, 3,    8, 0}, /* PB0 */
-	{&gpiob, &timer3, &adc1,  1, 4,    9, 0}, /* PB1 */
+	{&gpiob, &timer3, &adc1,  0, 3,    8}, /* PB0 */ 
+	{&gpiob, &timer3, &adc1,  1, 4,    9}, /* PB1 */
 	/* NOTE PB2 is not included as its Boot 1 */
-	{&gpiob,   NULL, NULL,  3, 0, ADCx, 0}, /* PB3  */ //JTDO, SPI3_SCK / I2S3_CK/
-    {&gpiob,   NULL, NULL,  4, 0, ADCx, 0}, /* PB4  */ //NJTRST, SPI3_MISO
-    {&gpiob,   NULL, NULL,  5, 0, ADCx, 0}, /* PB5 */ //I2C1_SMBA/ SPI3_MOSI
-    {&gpiob, &timer4, NULL,  6, 1, ADCx, 0}, /* PB6 */ //I2C1_SCL(9)
-    {&gpiob, &timer4, NULL,  7, 2, ADCx, 0}, /* PB7 */ //I2C1_SDA(9) / FSMC_NADV
-    {&gpiob, &timer4, NULL,  8, 3, ADCx, 0}, /* PB8 */ //SDIO_D4
-	{&gpiob, &timer4, NULL,  9, 4, ADCx, 0}, /* PB9 */ //SDIO_D5
-    {&gpiob,   NULL, NULL, 10, 0, ADCx, 0}, /* PB10 */ //I2C2_SCL/USART3_TX
-    {&gpiob,   NULL, NULL, 11, 0, ADCx, 0}, /* PB11 */ //I2C2_SDA/USART3_RX
-    {&gpiob,   NULL, NULL, 12, 0, ADCx, 0}, /* PB12 */ //SPI2_NSS/I2S2_WS/I2C2_SMBA/USART3_CK
-    {&gpiob,   NULL, NULL, 13, 0, ADCx, 0}, /* PB13 */ //SPI2_SCK/I2S2_CK/USART3_CTS
-    {&gpiob,   NULL, NULL, 14, 0, ADCx, 0}, /* PB14 */ //SPI2_MISO/TIM1_CH2N/USART3_RTS
-    {&gpiob,   NULL, NULL, 15, 0, ADCx, 0}, /* PB15 */ //SPI2_MOSI/I2S2_SD
-
-
-    {&gpioc,   NULL, &adc1,  0, 0,   10, 0}, /* PC0 */
-    {&gpioc,   NULL, &adc1,  1, 0,   11, 0}, /* PC1 */
-    {&gpioc,   NULL, &adc1,  2, 0,   12, 0}, /* PC2 */
-    {&gpioc,   NULL, &adc1,  3, 0,   13, 0}, /* PC3 */
-    {&gpioc,   NULL, &adc1,  4, 0,   14, 0}, /* PC4 */
-    {&gpioc,   NULL, &adc1,  5, 0,   15, 0}, /* PC5 */
-    {&gpioc, &timer8, NULL,  6, 1, ADCx, 0}, /* PC6 I2S2_MCK/SDIO_D6*/
-	{&gpioc, &timer8, NULL,  7, 2, ADCx, 0}, /* PC7 I2S3_MCK/SDIO_D7*/
-    {&gpioc, &timer8, NULL,  8, 3, ADCx, 0}, /* PC8 SDIO_D0*/
-    {&gpioc, &timer8, NULL,  9, 4, ADCx, 0}, /* PC9 SDIO_D1*/
-    {&gpioc,   NULL, NULL, 10, 0, ADCx, 0}, /* PC10 UART4_TX/SDIO_D2 */
-    {&gpioc,   NULL, NULL, 11, 0, ADCx, 0}, /* PC11 UART4_RX/SDIO_D3 */
-    {&gpioc,   NULL, NULL, 12, 0, ADCx, 0}, /* PC12 UART5_TX/SDIO_CK */
-    {&gpioc,   NULL, NULL, 13, 0, ADCx, 0}, /* PC13 TAMPER-RTC/ Limited output*/
-    {&gpioc,   NULL, NULL, 14, 0, ADCx, 0}, /* PC14 OSC32_IN/ Limited output*/
-    {&gpioc,   NULL, NULL, 15, 0, ADCx, 0}, /* PC15 OSC32_OUT/ Limited output*/
-
-	{&gpiod,   NULL, NULL,   0, 0, ADCx, 0} , /* PD0 OSC_IN */
-	{&gpiod,   NULL, NULL,   1, 0, ADCx, 0} , /* PD1  OSC_OUT */
-	{&gpiod,   NULL, NULL,   2, 0, ADCx, 0} , /* PD2  TIM3_ETR/UART5_RX SDIO_CMD */
-	{&gpiod,   NULL, NULL,   3, 0, ADCx, 0} , /* PD3  FSMC_CLK */
-	{&gpiod,   NULL, NULL,   4, 0, ADCx, 0} , /* PD4  FSMC_NOE */
-	{&gpiod,   NULL, NULL,   5, 0, ADCx, 0} , /* PD5  FSMC_NWE */
-	{&gpiod,   NULL, NULL,   6, 0, ADCx, 0} , /* PD6  FSMC_NWAIT */
-	{&gpiod,   NULL, NULL,   7, 0, ADCx, 0} , /* PD7  FSMC_NE1/FSMC_NCE2 */
-	{&gpiod,   NULL, NULL,   8, 0, ADCx, 0} , /* PD8  FSMC_D13 */
-	{&gpiod,   NULL, NULL,   9, 0, ADCx, 0} , /* PD9  FSMC_D14 */
-	{&gpiod,   NULL, NULL,  10, 0, ADCx, 0} , /* PD10  FSMC_D15 */
-	{&gpiod,   NULL, NULL,  11, 0, ADCx, 0} , /* PD11  FSMC_A16 */
-	{&gpiod,   NULL, NULL,  12, 0, ADCx, 0} , /* PD12  FSMC_A17 */
-	{&gpiod,   NULL, NULL,  13, 0, ADCx, 0} , /* PD13  FSMC_A18 */	
-	{&gpiod,   NULL, NULL,  14, 0, ADCx, 0} , /* PD14  FSMC_D0 */
-	{&gpiod,   NULL, NULL,  15, 0, ADCx, 0} , /* PD15  FSMC_D1 */
+	{&gpiob,   NULL, NULL,  3, 0, ADCx}, /* PB3  */ //JTDO, SPI3_SCK / I2S3_CK/
+    {&gpiob,   NULL, NULL,  4, 0, ADCx}, /* PB4  */ //NJTRST, SPI3_MISO
+    {&gpiob,   NULL, NULL,  5, 0, ADCx}, /* PB5 */ //I2C1_SMBA/ SPI3_MOSI
+    {&gpiob, &timer4, NULL,  6, 1, ADCx}, /* PB6 */ //I2C1_SCL(9)
+    {&gpiob, &timer4, NULL,  7, 2, ADCx}, /* PB7 */ //I2C1_SDA(9) / FSMC_NADV
+    {&gpiob, &timer4, NULL,  8, 3, ADCx}, /* PB8 */ //SDIO_D4
+	{&gpiob, &timer4, NULL,  9, 4, ADCx}, /* PB9 */ //SDIO_D5
+    {&gpiob,   NULL, NULL, 10, 0, ADCx}, /* PB10 */ //I2C2_SCL/USART3_TX
+    {&gpiob,   NULL, NULL, 11, 0, ADCx}, /* PB11 */ //I2C2_SDA/USART3_RX
+    {&gpiob,   NULL, NULL, 12, 0, ADCx}, /* PB12 */ //SPI2_NSS/I2S2_WS/I2C2_SMBA/USART3_CK
+    {&gpiob,   NULL, NULL, 13, 0, ADCx}, /* PB13 */ //SPI2_SCK/I2S2_CK/USART3_CTS
+    {&gpiob,   NULL, NULL, 14, 0, ADCx}, /* PB14 */ //SPI2_MISO/TIM1_CH2N/USART3_RTS
+    {&gpiob,   NULL, NULL, 15, 0, ADCx}, /* PB15 */ //SPI2_MOSI/I2S2_SD
+
+
+    {&gpioc,   NULL, &adc1,  0, 0,   10}, /* PC0 */
+    {&gpioc,   NULL, &adc1,  1, 0,   11}, /* PC1 */
+    {&gpioc,   NULL, &adc1,  2, 0,   12}, /* PC2 */
+    {&gpioc,   NULL, &adc1,  3, 0,   13}, /* PC3 */
+    {&gpioc,   NULL, &adc1,  4, 0,   14}, /* PC4 */
+    {&gpioc,   NULL, &adc1,  5, 0,   15}, /* PC5 */
+    {&gpioc, &timer8, NULL,  6, 1, ADCx}, /* PC6 I2S2_MCK/SDIO_D6*/	
+	{&gpioc, &timer8, NULL,  7, 2, ADCx}, /* PC7 I2S3_MCK/SDIO_D7*/
+    {&gpioc, &timer8, NULL,  8, 3, ADCx}, /* PC8 SDIO_D0*/
+    {&gpioc, &timer8, NULL,  9, 4, ADCx}, /* PC9 SDIO_D1*/
+    {&gpioc,   NULL, NULL, 10, 0, ADCx}, /* PC10 UART4_TX/SDIO_D2 */
+    {&gpioc,   NULL, NULL, 11, 0, ADCx}, /* PC11 UART4_RX/SDIO_D3 */
+    {&gpioc,   NULL, NULL, 12, 0, ADCx}, /* PC12 UART5_TX/SDIO_CK */	
+    {&gpioc,   NULL, NULL, 13, 0, ADCx}, /* PC13 TAMPER-RTC/ Limited output*/
+    {&gpioc,   NULL, NULL, 14, 0, ADCx}, /* PC14 OSC32_IN/ Limited output*/
+    {&gpioc,   NULL, NULL, 15, 0, ADCx}, /* PC15 OSC32_OUT/ Limited output*/
+
+	{&gpiod,   NULL, NULL,   0, 0, ADCx} , /* PD0 OSC_IN */
+	{&gpiod,   NULL, NULL,   1, 0, ADCx} , /* PD1  OSC_OUT */
+	{&gpiod,   NULL, NULL,   2, 0, ADCx} , /* PD2  TIM3_ETR/UART5_RX SDIO_CMD */
+	{&gpiod,   NULL, NULL,   3, 0, ADCx} , /* PD3  FSMC_CLK */
+	{&gpiod,   NULL, NULL,   4, 0, ADCx} , /* PD4  FSMC_NOE */
+	{&gpiod,   NULL, NULL,   5, 0, ADCx} , /* PD5  FSMC_NWE */
+	{&gpiod,   NULL, NULL,   6, 0, ADCx} , /* PD6  FSMC_NWAIT */
+	{&gpiod,   NULL, NULL,   7, 0, ADCx} , /* PD7  FSMC_NE1/FSMC_NCE2 */
+	{&gpiod,   NULL, NULL,   8, 0, ADCx} , /* PD8  FSMC_D13 */
+	{&gpiod,   NULL, NULL,   9, 0, ADCx} , /* PD9  FSMC_D14 */
+	{&gpiod,   NULL, NULL,  10, 0, ADCx} , /* PD10  FSMC_D15 */
+	{&gpiod,   NULL, NULL,  11, 0, ADCx} , /* PD11  FSMC_A16 */
+	{&gpiod,   NULL, NULL,  12, 0, ADCx} , /* PD12  FSMC_A17 */
+	{&gpiod,   NULL, NULL,  13, 0, ADCx} , /* PD13  FSMC_A18 */	
+	{&gpiod,   NULL, NULL,  14, 0, ADCx} , /* PD14  FSMC_D0 */
+	{&gpiod,   NULL, NULL,  15, 0, ADCx} , /* PD15  FSMC_D1 */
 	
-	{&gpioe,   NULL, NULL,   0, 0, ADCx, 0} , /* PE0  TIM4_ETR / FSMC_NBL0 */
-	{&gpioe,   NULL, NULL,   1, 0, ADCx, 0} , /* PE1  FSMC_NBL1 */
-	{&gpioe,   NULL, NULL,   2, 0, ADCx, 0} , /* PE2  TRACECK/ FSMC_A23 */
-	{&gpioe,   NULL, NULL,   3, 0, ADCx, 0} , /* PE3  TRACED0/FSMC_A19 */
-	{&gpioe,   NULL, NULL,   4, 0, ADCx, 0} , /* PE4  TRACED1/FSMC_A20 */
-	{&gpioe,   NULL, NULL,   5, 0, ADCx, 0} , /* PE5  TRACED2/FSMC_A21 */
-	{&gpioe,   NULL, NULL,   6, 0, ADCx, 0} , /* PE6  TRACED3/FSMC_A22 */
-	{&gpioe,   NULL, NULL,   7, 0, ADCx, 0} , /* PE7  FSMC_D4 */
-	{&gpioe,   NULL, NULL,   8, 0, ADCx, 0} , /* PE8  FSMC_D5 */
-	{&gpioe,   NULL, NULL,   9, 0, ADCx, 0} , /* PE9  FSMC_D6 */
-	{&gpioe,   NULL, NULL,  10, 0, ADCx, 0} , /* PE10 FSMC_D7 */
-	{&gpioe,   NULL, NULL,  11, 0, ADCx, 0} , /* PE11 FSMC_D8 */
-	{&gpioe,   NULL, NULL,  12, 0, ADCx, 0} , /* PE12 FSMC_D9 */
-	{&gpioe,   NULL, NULL,  13, 0, ADCx, 0} , /* PE13 FSMC_D10 */	
-	{&gpioe,   NULL, NULL,  14, 0, ADCx, 0} , /* PE14 FSMC_D11 */
-	{&gpioe,   NULL, NULL,  15, 0, ADCx, 0} , /* PE15 FSMC_D12 */	
+	{&gpioe,   NULL, NULL,   0, 0, ADCx} , /* PE0  TIM4_ETR / FSMC_NBL0 */
+	{&gpioe,   NULL, NULL,   1, 0, ADCx} , /* PE1  FSMC_NBL1 */
+	{&gpioe,   NULL, NULL,   2, 0, ADCx} , /* PE2  TRACECK/ FSMC_A23 */
+	{&gpioe,   NULL, NULL,   3, 0, ADCx} , /* PE3  TRACED0/FSMC_A19 */
+	{&gpioe,   NULL, NULL,   4, 0, ADCx} , /* PE4  TRACED1/FSMC_A20 */
+	{&gpioe,   NULL, NULL,   5, 0, ADCx} , /* PE5  TRACED2/FSMC_A21 */
+	{&gpioe,   NULL, NULL,   6, 0, ADCx} , /* PE6  TRACED3/FSMC_A22 */
+	{&gpioe,   NULL, NULL,   7, 0, ADCx} , /* PE7  FSMC_D4 */
+	{&gpioe,   NULL, NULL,   8, 0, ADCx} , /* PE8  FSMC_D5 */
+	{&gpioe,   NULL, NULL,   9, 0, ADCx} , /* PE9  FSMC_D6 */
+	{&gpioe,   NULL, NULL,  10, 0, ADCx} , /* PE10 FSMC_D7 */
+	{&gpioe,   NULL, NULL,  11, 0, ADCx} , /* PE11 FSMC_D8 */
+	{&gpioe,   NULL, NULL,  12, 0, ADCx} , /* PE12 FSMC_D9 */
+	{&gpioe,   NULL, NULL,  13, 0, ADCx} , /* PE13 FSMC_D10 */	
+	{&gpioe,   NULL, NULL,  14, 0, ADCx} , /* PE14 FSMC_D11 */
+	{&gpioe,   NULL, NULL,  15, 0, ADCx} , /* PE15 FSMC_D12 */	
 	
 };
 
@@ -195,4 +196,4 @@ extern const uint8 boardUsedPins[BOARD_NR_USED_PINS] __FLASH__ = {
 	DEFINE_HWSERIAL(Serial2, 3);
 	DEFINE_HWSERIAL_UART(Serial3, 4);
 	DEFINE_HWSERIAL_UART(Serial4, 5);
-#endif
+#endif
\ No newline at end of file
diff --git a/STM32F1/variants/generic_stm32f103z/board.cpp b/STM32F1/variants/generic_stm32f103z/board.cpp
index 0d112a32b..830479e96 100644
--- a/STM32F1/variants/generic_stm32f103z/board.cpp
+++ b/STM32F1/variants/generic_stm32f103z/board.cpp
@@ -80,126 +80,126 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 	uint8 pinMode; 				mode specific by pinMode call (Roger Clark added to optimize compatibility with Arduino API
 */
 
-    {&gpioa, &timer2, &adc1,  0, 1,    0, 0}, /* PA0 */
-    {&gpioa, &timer2, &adc1,  1, 2,    1, 0}, /* PA1 */
-	{&gpioa, &timer2, &adc1,  2, 3,    2, 0}, /* PA2 */
-    {&gpioa, &timer2, &adc1,  3, 4,    3, 0}, /* PA3 */
-	{&gpioa,   NULL, &adc1,  4, 0,    4, 0}, /* PA4 */
-    {&gpioa,   NULL, &adc1,  5, 0,    5, 0}, /* PA5 */
-    {&gpioa, &timer3, &adc1,  6, 1,    6, 0}, /* PA6 */
-    {&gpioa, &timer3, &adc1,  7, 2,    7, 0}, /* PA7 */
-    {&gpioa, &timer1, NULL,  8, 1, ADCx, 0}, /* PA8 */
-    {&gpioa, &timer1, NULL,  9, 2, ADCx, 0}, /* PA9 */
-    {&gpioa, &timer1, NULL, 10, 3, ADCx, 0}, /* PA10 */
-    {&gpioa,   NULL, NULL, 11, 0, ADCx, 0}, /* PA11 */
-    {&gpioa,   NULL, NULL, 12, 0, ADCx, 0}, /* PA12 */
-    {&gpioa,   NULL, NULL, 13, 0, ADCx, 0}, /* PA13 */
-    {&gpioa,   NULL, NULL, 14, 0, ADCx, 0}, /* PA14 */
-    {&gpioa,   NULL, NULL, 15, 0, ADCx, 0}, /* PA15 */
+    {&gpioa, &timer2, &adc1,  0, 1,    0}, /* PA0 */
+    {&gpioa, &timer2, &adc1,  1, 2,    1}, /* PA1 */
+	{&gpioa, &timer2, &adc1,  2, 3,    2}, /* PA2 */
+    {&gpioa, &timer2, &adc1,  3, 4,    3}, /* PA3 */
+	{&gpioa,   NULL, &adc1,  4, 0,    4}, /* PA4 */	
+    {&gpioa,   NULL, &adc1,  5, 0,    5}, /* PA5 */
+    {&gpioa, &timer3, &adc1,  6, 1,    6}, /* PA6 */
+    {&gpioa, &timer3, &adc1,  7, 2,    7}, /* PA7 */
+    {&gpioa, &timer1, NULL,  8, 1, ADCx}, /* PA8 */
+    {&gpioa, &timer1, NULL,  9, 2, ADCx}, /* PA9 */
+    {&gpioa, &timer1, NULL, 10, 3, ADCx}, /* PA10 */
+    {&gpioa,   NULL, NULL, 11, 0, ADCx}, /* PA11 */
+    {&gpioa,   NULL, NULL, 12, 0, ADCx}, /* PA12 */	
+    {&gpioa,   NULL, NULL, 13, 0, ADCx}, /* PA13 */
+    {&gpioa,   NULL, NULL, 14, 0, ADCx}, /* PA14 */
+    {&gpioa,   NULL, NULL, 15, 0, ADCx}, /* PA15 */
 	
-	{&gpiob, &timer3, &adc1,  0, 3,    8, 0}, /* PB0 */
-	{&gpiob, &timer3, &adc1,  1, 4,    9, 0}, /* PB1 */
-	{&gpiob, &timer3, &adc1,  2, 4,    9, 0}, /* PB2 */
-	{&gpiob,   NULL, NULL,  3, 0, ADCx, 0}, /* PB3  */
-    {&gpiob,   NULL, NULL,  4, 0, ADCx, 0}, /* PB4  */
-    {&gpiob,   NULL, NULL,  5, 0, ADCx, 0}, /* PB5 */
-    {&gpiob, &timer4, NULL,  6, 1, ADCx, 0}, /* PB6 */
-    {&gpiob, &timer4, NULL,  7, 2, ADCx, 0}, /* PB7 */
-    {&gpiob, &timer4, NULL,  8, 3, ADCx, 0}, /* PB8 */
-	{&gpiob, &timer4, NULL,  9, 4, ADCx, 0}, /* PB9 */
-    {&gpiob,   NULL, NULL, 10, 0, ADCx, 0}, /* PB10 */
-    {&gpiob,   NULL, NULL, 11, 0, ADCx, 0}, /* PB11 */
-    {&gpiob,   NULL, NULL, 12, 0, ADCx, 0}, /* PB12 */
-    {&gpiob,   NULL, NULL, 13, 0, ADCx, 0}, /* PB13 */
-    {&gpiob,   NULL, NULL, 14, 0, ADCx, 0}, /* PB14 */
-    {&gpiob,   NULL, NULL, 15, 0, ADCx, 0}, /* PB15 */
-
-
-    {&gpioc,   NULL, &adc1,  0, 0,   10, 0}, /* PC0 */
-    {&gpioc,   NULL, &adc1,  1, 0,   11, 0}, /* PC1 */
-    {&gpioc,   NULL, &adc1,  2, 0,   12, 0}, /* PC2 */
-    {&gpioc,   NULL, &adc1,  3, 0,   13, 0}, /* PC3 */
-    {&gpioc,   NULL, &adc1,  4, 0,   14, 0}, /* PC4 */
-    {&gpioc,   NULL, &adc1,  5, 0,   15, 0}, /* PC5 */
-    {&gpioc, &timer8, NULL,  6, 1, ADCx, 0}, /* PC6 */
-	{&gpioc, &timer8, NULL,  7, 2, ADCx, 0}, /* PC7 */
-    {&gpioc, &timer8, NULL,  8, 3, ADCx, 0}, /* PC8 */
-    {&gpioc, &timer8, NULL,  9, 4, ADCx, 0}, /* PC9 */
-    {&gpioc,   NULL, NULL, 10, 0, ADCx, 0}, /* PC10 UART4_TX/SDIO_D2 */
-    {&gpioc,   NULL, NULL, 11, 0, ADCx, 0}, /* PC11 UART4_RX/SDIO_D3 */
-    {&gpioc,   NULL, NULL, 12, 0, ADCx, 0}, /* PC12 UART5_TX/SDIO_CK */
-    {&gpioc,   NULL, NULL, 13, 0, ADCx, 0}, /* PC13 TAMPER-RTC */
-    {&gpioc,   NULL, NULL, 14, 0, ADCx, 0}, /* PC14 OSC32_IN */
-    {&gpioc,   NULL, NULL, 15, 0, ADCx, 0}, /* PC15 OSC32_OUT */
-
-	{&gpiod,   NULL, NULL,   0, 0, ADCx, 0} , /* PD0 OSC_IN */
-	{&gpiod,   NULL, NULL,   1, 0, ADCx, 0} , /* PD1  OSC_OUT */
-	{&gpiod,   NULL, NULL,   2, 0, ADCx, 0} , /* PD2  TIM3_ETR/UART5_RX SDIO_CMD */
+	{&gpiob, &timer3, &adc1,  0, 3,    8}, /* PB0 */
+	{&gpiob, &timer3, &adc1,  1, 4,    9}, /* PB1 */
+	{&gpiob, &timer3, &adc1,  2, 4,    9}, /* PB2 */
+	{&gpiob,   NULL, NULL,  3, 0, ADCx}, /* PB3  */
+    {&gpiob,   NULL, NULL,  4, 0, ADCx}, /* PB4  */
+    {&gpiob,   NULL, NULL,  5, 0, ADCx}, /* PB5 */
+    {&gpiob, &timer4, NULL,  6, 1, ADCx}, /* PB6 */
+    {&gpiob, &timer4, NULL,  7, 2, ADCx}, /* PB7 */
+    {&gpiob, &timer4, NULL,  8, 3, ADCx}, /* PB8 */
+	{&gpiob, &timer4, NULL,  9, 4, ADCx}, /* PB9 */
+    {&gpiob,   NULL, NULL, 10, 0, ADCx}, /* PB10 */
+    {&gpiob,   NULL, NULL, 11, 0, ADCx}, /* PB11 */
+    {&gpiob,   NULL, NULL, 12, 0, ADCx}, /* PB12 */
+    {&gpiob,   NULL, NULL, 13, 0, ADCx}, /* PB13 */
+    {&gpiob,   NULL, NULL, 14, 0, ADCx}, /* PB14 */
+    {&gpiob,   NULL, NULL, 15, 0, ADCx}, /* PB15 */
+
+
+    {&gpioc,   NULL, &adc1,  0, 0,   10}, /* PC0 */
+    {&gpioc,   NULL, &adc1,  1, 0,   11}, /* PC1 */
+    {&gpioc,   NULL, &adc1,  2, 0,   12}, /* PC2 */
+    {&gpioc,   NULL, &adc1,  3, 0,   13}, /* PC3 */
+    {&gpioc,   NULL, &adc1,  4, 0,   14}, /* PC4 */
+    {&gpioc,   NULL, &adc1,  5, 0,   15}, /* PC5 */
+    {&gpioc, &timer8, NULL,  6, 1, ADCx}, /* PC6 */	
+	{&gpioc, &timer8, NULL,  7, 2, ADCx}, /* PC7 */
+    {&gpioc, &timer8, NULL,  8, 3, ADCx}, /* PC8 */
+    {&gpioc, &timer8, NULL,  9, 4, ADCx}, /* PC9 */
+    {&gpioc,   NULL, NULL, 10, 0, ADCx}, /* PC10 UART4_TX/SDIO_D2 */
+    {&gpioc,   NULL, NULL, 11, 0, ADCx}, /* PC11 UART4_RX/SDIO_D3 */
+    {&gpioc,   NULL, NULL, 12, 0, ADCx}, /* PC12 UART5_TX/SDIO_CK */	
+    {&gpioc,   NULL, NULL, 13, 0, ADCx}, /* PC13 TAMPER-RTC */
+    {&gpioc,   NULL, NULL, 14, 0, ADCx}, /* PC14 OSC32_IN */
+    {&gpioc,   NULL, NULL, 15, 0, ADCx}, /* PC15 OSC32_OUT */
+
+	{&gpiod,   NULL, NULL,   0, 0, ADCx} , /* PD0 OSC_IN */
+	{&gpiod,   NULL, NULL,   1, 0, ADCx} , /* PD1  OSC_OUT */
+	{&gpiod,   NULL, NULL,   2, 0, ADCx} , /* PD2  TIM3_ETR/UART5_RX SDIO_CMD */
 	
-	{&gpiod,   NULL, NULL,   3, 0, ADCx, 0} , /* PD3  FSMC_CLK */
-	{&gpiod,   NULL, NULL,   4, 0, ADCx, 0} , /* PD4  FSMC_NOE */
-	{&gpiod,   NULL, NULL,   5, 0, ADCx, 0} , /* PD5  FSMC_NWE */
-	{&gpiod,   NULL, NULL,   6, 0, ADCx, 0} , /* PD6  FSMC_NWAIT */
-	{&gpiod,   NULL, NULL,   7, 0, ADCx, 0} , /* PD7  FSMC_NE1/FSMC_NCE2 */
-	{&gpiod,   NULL, NULL,   8, 0, ADCx, 0} , /* PD8  FSMC_D13 */
-	{&gpiod,   NULL, NULL,   9, 0, ADCx, 0} , /* PD9  FSMC_D14 */
-	{&gpiod,   NULL, NULL,  10, 0, ADCx, 0} , /* PD10  FSMC_D15 */
-	{&gpiod,   NULL, NULL,  11, 0, ADCx, 0} , /* PD11  FSMC_A16 */
-	{&gpiod,   NULL, NULL,  12, 0, ADCx, 0} , /* PD12  FSMC_A17 */
-	{&gpiod,   NULL, NULL,  13, 0, ADCx, 0} , /* PD13  FSMC_A18 */	
-	{&gpiod,   NULL, NULL,  14, 0, ADCx, 0} , /* PD14  FSMC_D0 */
-	{&gpiod,   NULL, NULL,  15, 0, ADCx, 0} , /* PD15  FSMC_D1 */
+	{&gpiod,   NULL, NULL,   3, 0, ADCx} , /* PD3  FSMC_CLK */
+	{&gpiod,   NULL, NULL,   4, 0, ADCx} , /* PD4  FSMC_NOE */
+	{&gpiod,   NULL, NULL,   5, 0, ADCx} , /* PD5  FSMC_NWE */
+	{&gpiod,   NULL, NULL,   6, 0, ADCx} , /* PD6  FSMC_NWAIT */
+	{&gpiod,   NULL, NULL,   7, 0, ADCx} , /* PD7  FSMC_NE1/FSMC_NCE2 */
+	{&gpiod,   NULL, NULL,   8, 0, ADCx} , /* PD8  FSMC_D13 */
+	{&gpiod,   NULL, NULL,   9, 0, ADCx} , /* PD9  FSMC_D14 */
+	{&gpiod,   NULL, NULL,  10, 0, ADCx} , /* PD10  FSMC_D15 */
+	{&gpiod,   NULL, NULL,  11, 0, ADCx} , /* PD11  FSMC_A16 */
+	{&gpiod,   NULL, NULL,  12, 0, ADCx} , /* PD12  FSMC_A17 */
+	{&gpiod,   NULL, NULL,  13, 0, ADCx} , /* PD13  FSMC_A18 */	
+	{&gpiod,   NULL, NULL,  14, 0, ADCx} , /* PD14  FSMC_D0 */
+	{&gpiod,   NULL, NULL,  15, 0, ADCx} , /* PD15  FSMC_D1 */
 	
-	{&gpioe,   NULL, NULL,   0, 0, ADCx, 0} , /* PE0   */
-	{&gpioe,   NULL, NULL,   1, 0, ADCx, 0} , /* PE1   */
-	{&gpioe,   NULL, NULL,   2, 0, ADCx, 0} , /* PE2   */
-	{&gpioe,   NULL, NULL,   3, 0, ADCx, 0} , /* PE3   */
-	{&gpioe,   NULL, NULL,   4, 0, ADCx, 0} , /* PE4   */
-	{&gpioe,   NULL, NULL,   5, 0, ADCx, 0} , /* PE5   */
-	{&gpioe,   NULL, NULL,   6, 0, ADCx, 0} , /* PE6   */
-	{&gpioe,   NULL, NULL,   7, 0, ADCx, 0} , /* PE7   */
-	{&gpioe,   NULL, NULL,   8, 0, ADCx, 0} , /* PE8   */
-	{&gpioe,   NULL, NULL,   9, 0, ADCx, 0} , /* PE9   */
-	{&gpioe,   NULL, NULL,  10, 0, ADCx, 0} , /* PE10  */
-	{&gpioe,   NULL, NULL,  11, 0, ADCx, 0} , /* PE11  */
-	{&gpioe,   NULL, NULL,  12, 0, ADCx, 0} , /* PE12  */
-	{&gpioe,   NULL, NULL,  13, 0, ADCx, 0} , /* PE13  */	
-	{&gpioe,   NULL, NULL,  14, 0, ADCx, 0} , /* PE14  */
-	{&gpioe,   NULL, NULL,  15, 0, ADCx, 0} , /* PE15  */	
-
-	{&gpiof,   NULL, NULL,   0, 0, ADCx, 0} , /* PF0   */
-	{&gpiof,   NULL, NULL,   1, 0, ADCx, 0} , /* PF1   */
-	{&gpiof,   NULL, NULL,   2, 0, ADCx, 0} , /* PF2   */
-	{&gpiof,   NULL, NULL,   3, 0, ADCx, 0} , /* PF3   */
-	{&gpiof,   NULL, NULL,   4, 0, ADCx, 0} , /* PF4   */
-	{&gpiof,   NULL, NULL,   5, 0, ADCx, 0} , /* PF5   */
-	{&gpiof,   NULL, NULL,   6, 0, ADCx, 0} , /* PF6   */
-	{&gpiof,   NULL, NULL,   7, 0, ADCx, 0} , /* PF7   */
-	{&gpiof,   NULL, NULL,   8, 0, ADCx, 0} , /* PF8   */
-	{&gpiof,   NULL, NULL,   9, 0, ADCx, 0} , /* PF9   */
-	{&gpiof,   NULL, NULL,  10, 0, ADCx, 0} , /* PF10  */
-	{&gpiof,   NULL, NULL,  11, 0, ADCx, 0} , /* PF11  */
-	{&gpiof,   NULL, NULL,  12, 0, ADCx, 0} , /* PF12  */
-	{&gpiof,   NULL, NULL,  13, 0, ADCx, 0} , /* PF13  */	
-	{&gpiof,   NULL, NULL,  14, 0, ADCx, 0} , /* PF14  */
-	{&gpiof,   NULL, NULL,  15, 0, ADCx, 0} , /* PF15  */		
+	{&gpioe,   NULL, NULL,   0, 0, ADCx} , /* PE0   */
+	{&gpioe,   NULL, NULL,   1, 0, ADCx} , /* PE1   */
+	{&gpioe,   NULL, NULL,   2, 0, ADCx} , /* PE2   */
+	{&gpioe,   NULL, NULL,   3, 0, ADCx} , /* PE3   */
+	{&gpioe,   NULL, NULL,   4, 0, ADCx} , /* PE4   */
+	{&gpioe,   NULL, NULL,   5, 0, ADCx} , /* PE5   */
+	{&gpioe,   NULL, NULL,   6, 0, ADCx} , /* PE6   */
+	{&gpioe,   NULL, NULL,   7, 0, ADCx} , /* PE7   */
+	{&gpioe,   NULL, NULL,   8, 0, ADCx} , /* PE8   */
+	{&gpioe,   NULL, NULL,   9, 0, ADCx} , /* PE9   */
+	{&gpioe,   NULL, NULL,  10, 0, ADCx} , /* PE10  */
+	{&gpioe,   NULL, NULL,  11, 0, ADCx} , /* PE11  */
+	{&gpioe,   NULL, NULL,  12, 0, ADCx} , /* PE12  */
+	{&gpioe,   NULL, NULL,  13, 0, ADCx} , /* PE13  */	
+	{&gpioe,   NULL, NULL,  14, 0, ADCx} , /* PE14  */
+	{&gpioe,   NULL, NULL,  15, 0, ADCx} , /* PE15  */	
+
+	{&gpiof,   NULL, NULL,   0, 0, ADCx} , /* PF0   */
+	{&gpiof,   NULL, NULL,   1, 0, ADCx} , /* PF1   */
+	{&gpiof,   NULL, NULL,   2, 0, ADCx} , /* PF2   */
+	{&gpiof,   NULL, NULL,   3, 0, ADCx} , /* PF3   */
+	{&gpiof,   NULL, NULL,   4, 0, ADCx} , /* PF4   */
+	{&gpiof,   NULL, NULL,   5, 0, ADCx} , /* PF5   */
+	{&gpiof,   NULL, NULL,   6, 0, ADCx} , /* PF6   */
+	{&gpiof,   NULL, NULL,   7, 0, ADCx} , /* PF7   */
+	{&gpiof,   NULL, NULL,   8, 0, ADCx} , /* PF8   */
+	{&gpiof,   NULL, NULL,   9, 0, ADCx} , /* PF9   */
+	{&gpiof,   NULL, NULL,  10, 0, ADCx} , /* PF10  */
+	{&gpiof,   NULL, NULL,  11, 0, ADCx} , /* PF11  */
+	{&gpiof,   NULL, NULL,  12, 0, ADCx} , /* PF12  */
+	{&gpiof,   NULL, NULL,  13, 0, ADCx} , /* PF13  */	
+	{&gpiof,   NULL, NULL,  14, 0, ADCx} , /* PF14  */
+	{&gpiof,   NULL, NULL,  15, 0, ADCx} , /* PF15  */		
 	
-	{&gpiog,   NULL, NULL,   0, 0, ADCx, 0} , /* PG0   */
-	{&gpiog,   NULL, NULL,   1, 0, ADCx, 0} , /* PG1   */
-	{&gpiog,   NULL, NULL,   2, 0, ADCx, 0} , /* PG2   */
-	{&gpiog,   NULL, NULL,   3, 0, ADCx, 0} , /* PG3   */
-	{&gpiog,   NULL, NULL,   4, 0, ADCx, 0} , /* PG4   */
-	{&gpiog,   NULL, NULL,   5, 0, ADCx, 0} , /* PG5   */
-	{&gpiog,   NULL, NULL,   6, 0, ADCx, 0} , /* PG6   */
-	{&gpiog,   NULL, NULL,   7, 0, ADCx, 0} , /* PG7   */
-	{&gpiog,   NULL, NULL,   8, 0, ADCx, 0} , /* PG8   */
-	{&gpiog,   NULL, NULL,   9, 0, ADCx, 0} , /* PG9   */
-	{&gpiog,   NULL, NULL,  10, 0, ADCx, 0} , /* PG10  */
-	{&gpiog,   NULL, NULL,  11, 0, ADCx, 0} , /* PG11  */
-	{&gpiog,   NULL, NULL,  12, 0, ADCx, 0} , /* PG12  */
-	{&gpiog,   NULL, NULL,  13, 0, ADCx, 0} , /* PG13  */	
-	{&gpiog,   NULL, NULL,  14, 0, ADCx, 0} , /* PG14  */
-	{&gpiog,   NULL, NULL,  15, 0, ADCx, 0}  /* PG15  */		
+	{&gpiog,   NULL, NULL,   0, 0, ADCx} , /* PG0   */
+	{&gpiog,   NULL, NULL,   1, 0, ADCx} , /* PG1   */
+	{&gpiog,   NULL, NULL,   2, 0, ADCx} , /* PG2   */
+	{&gpiog,   NULL, NULL,   3, 0, ADCx} , /* PG3   */
+	{&gpiog,   NULL, NULL,   4, 0, ADCx} , /* PG4   */
+	{&gpiog,   NULL, NULL,   5, 0, ADCx} , /* PG5   */
+	{&gpiog,   NULL, NULL,   6, 0, ADCx} , /* PG6   */
+	{&gpiog,   NULL, NULL,   7, 0, ADCx} , /* PG7   */
+	{&gpiog,   NULL, NULL,   8, 0, ADCx} , /* PG8   */
+	{&gpiog,   NULL, NULL,   9, 0, ADCx} , /* PG9   */
+	{&gpiog,   NULL, NULL,  10, 0, ADCx} , /* PG10  */
+	{&gpiog,   NULL, NULL,  11, 0, ADCx} , /* PG11  */
+	{&gpiog,   NULL, NULL,  12, 0, ADCx} , /* PG12  */
+	{&gpiog,   NULL, NULL,  13, 0, ADCx} , /* PG13  */	
+	{&gpiog,   NULL, NULL,  14, 0, ADCx} , /* PG14  */
+	{&gpiog,   NULL, NULL,  15, 0, ADCx}  /* PG15  */		
 };
 
 /*  Basically everything that is defined as having a timer us PWM */
@@ -231,4 +231,4 @@ extern const uint8 boardUsedPins[BOARD_NR_USED_PINS] __FLASH__ = {
 	DEFINE_HWSERIAL(Serial2, 3);
 	DEFINE_HWSERIAL_UART(Serial3, 4);
 	DEFINE_HWSERIAL_UART(Serial4, 5);
-#endif
+#endif
\ No newline at end of file
diff --git a/STM32F1/variants/hytiny_stm32f103t/board.cpp b/STM32F1/variants/hytiny_stm32f103t/board.cpp
index b3fdd9b88..f1fb44f07 100644
--- a/STM32F1/variants/hytiny_stm32f103t/board.cpp
+++ b/STM32F1/variants/hytiny_stm32f103t/board.cpp
@@ -51,34 +51,35 @@ void boardInit(void) {
 }
 
 // Note. See the enum of pin names in board.h
+
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
 
-    {&gpioa, &timer2, &adc1,  0, 1,    0, 0}, /* PA0 */
-    {&gpioa, &timer2, &adc1,  1, 2,    1, 0}, /* PA1 */
-    {&gpioa, &timer2, &adc1,  2, 3,    2, 0}, /* PA2 */
-    {&gpioa, &timer2, &adc1,  3, 4,    3, 0}, /* PA3 */
-    {&gpioa,   NULL, &adc1,  4, 0,    4, 0}, /* PA4 */
-    {&gpioa,   NULL, &adc1,  5, 0,    5, 0}, /* PA5 */
-    {&gpioa, &timer3, &adc1,  6, 1,    6, 0}, /* PA6 */
-    {&gpioa, &timer3, &adc1,  7, 2,    7, 0}, /* PA7 */
-    {&gpioa, &timer1, NULL,  8, 1, ADCx, 0}, /* PA8 */
-    {&gpioa, &timer1, NULL,  9, 2, ADCx, 0}, /* PA9 */
-    {&gpioa, &timer1, NULL, 10, 3, ADCx, 0}, /* PA10 */
-    {&gpioa, &timer1, NULL, 11, 4, ADCx, 0}, /* PA11 */
-    {&gpioa,   NULL, NULL, 12, 0, ADCx, 0}, /* PA12 */
-    {&gpioa,   NULL, NULL, 13, 0, ADCx, 0}, /* PA13 */
-    {&gpioa,   NULL, NULL, 14, 0, ADCx, 0}, /* PA14 */
-    {&gpioa,   NULL, NULL, 15, 0, ADCx, 0}, /* PA15 */
+    {&gpioa, &timer2, &adc1,  0, 1,    0}, /* PA0 */
+    {&gpioa, &timer2, &adc1,  1, 2,    1}, /* PA1 */
+    {&gpioa, &timer2, &adc1,  2, 3,    2}, /* PA2 */	
+    {&gpioa, &timer2, &adc1,  3, 4,    3}, /* PA3 */
+    {&gpioa,   NULL, &adc1,  4, 0,    4}, /* PA4 */
+    {&gpioa,   NULL, &adc1,  5, 0,    5}, /* PA5 */
+    {&gpioa, &timer3, &adc1,  6, 1,    6}, /* PA6 */
+    {&gpioa, &timer3, &adc1,  7, 2,    7}, /* PA7 */
+    {&gpioa, &timer1, NULL,  8, 1, ADCx}, /* PA8 */	
+    {&gpioa, &timer1, NULL,  9, 2, ADCx}, /* PA9 */	
+    {&gpioa, &timer1, NULL, 10, 3, ADCx}, /* PA10 */
+    {&gpioa, &timer1, NULL, 11, 4, ADCx}, /* PA11 */
+    {&gpioa,   NULL, NULL, 12, 0, ADCx}, /* PA12 */	
+    {&gpioa,   NULL, NULL, 13, 0, ADCx}, /* PA13 */	
+    {&gpioa,   NULL, NULL, 14, 0, ADCx}, /* PA14 */
+    {&gpioa,   NULL, NULL, 15, 0, ADCx}, /* PA15 */
 	
-    {&gpiob, &timer3, &adc1,  0, 3,    8, 0}, /* PB0 */
-    {&gpiob, &timer3, &adc1,  1, 4,    9, 0}, /* PB1 */
-    {&gpiob,   NULL, NULL,  2, 0, ADCx, 0}, /* PB2 */
-    {&gpiob,   NULL, NULL,  3, 0, ADCx, 0}, /* PB3 */
-    {&gpiob,   NULL, NULL,  4, 0, ADCx, 0}, /* PB4 */
-    {&gpiob,   NULL, NULL,  5, 0, ADCx, 0}, /* PB5 */
-    {&gpiob, &timer4, NULL,  6, 1, ADCx, 0}, /* PB6 */
-    {&gpiob, &timer4, NULL,  7, 2, ADCx, 0}, /* PB7 */
+    {&gpiob, &timer3, &adc1,  0, 3,    8}, /* PB0 */	
+    {&gpiob, &timer3, &adc1,  1, 4,    9}, /* PB1 */
+    {&gpiob,   NULL, NULL,  2, 0, ADCx}, /* PB2 */
+    {&gpiob,   NULL, NULL,  3, 0, ADCx}, /* PB3 */
+    {&gpiob,   NULL, NULL,  4, 0, ADCx}, /* PB4 */
+    {&gpiob,   NULL, NULL,  5, 0, ADCx}, /* PB5 */
+    {&gpiob, &timer4, NULL,  6, 1, ADCx}, /* PB6 */
+    {&gpiob, &timer4, NULL,  7, 2, ADCx}, /* PB7 */	
 
 };
 
diff --git a/STM32F1/variants/maple_mini/board.cpp b/STM32F1/variants/maple_mini/board.cpp
index 72faa17fb..f49b33682 100644
--- a/STM32F1/variants/maple_mini/board.cpp
+++ b/STM32F1/variants/maple_mini/board.cpp
@@ -54,43 +54,43 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
     /* Top header */
 
-    {&gpiob,   NULL, NULL, 11, 0, ADCx, 0}, /* D0/PB11 */
-    {&gpiob,   NULL, NULL, 10, 0, ADCx, 0}, /* D1/PB10 */
-    {&gpiob,   NULL, NULL,  2, 0, ADCx, 0}, /* D2/PB2 */
-    {&gpiob, &timer3, &adc1,  0, 3,    8, 0}, /* D3/PB0 */
-    {&gpioa, &timer3, &adc1,  7, 2,    7, 0}, /* D4/PA7 */
-    {&gpioa, &timer3, &adc1,  6, 1,    6, 0}, /* D5/PA6 */
-    {&gpioa,   NULL, &adc1,  5, 0,    5, 0}, /* D6/PA5 */
-    {&gpioa,   NULL, &adc1,  4, 0,    4, 0}, /* D7/PA4 */
-    {&gpioa, &timer2, &adc1,  3, 4,    3, 0}, /* D8/PA3 */
-    {&gpioa, &timer2, &adc1,  2, 3,    2, 0}, /* D9/PA2 */
-    {&gpioa, &timer2, &adc1,  1, 2,    1, 0}, /* D10/PA1 */
-    {&gpioa, &timer2, &adc1,  0, 1,    0, 0}, /* D11/PA0 */
-    {&gpioc,   NULL, NULL, 15, 0, ADCx, 0}, /* D12/PC15 */
-    {&gpioc,   NULL, NULL, 14, 0, ADCx, 0}, /* D13/PC14 */
-    {&gpioc,   NULL, NULL, 13, 0, ADCx, 0}, /* D14/PC13 */
+    {&gpiob,   NULL, NULL, 11, 0, ADCx}, /* D0/PB11 */
+    {&gpiob,   NULL, NULL, 10, 0, ADCx}, /* D1/PB10 */
+    {&gpiob,   NULL, NULL,  2, 0, ADCx}, /* D2/PB2 */
+    {&gpiob, &timer3, &adc1,  0, 3,    8}, /* D3/PB0 */
+    {&gpioa, &timer3, &adc1,  7, 2,    7}, /* D4/PA7 */
+    {&gpioa, &timer3, &adc1,  6, 1,    6}, /* D5/PA6 */
+    {&gpioa,   NULL, &adc1,  5, 0,    5}, /* D6/PA5 */
+    {&gpioa,   NULL, &adc1,  4, 0,    4}, /* D7/PA4 */
+    {&gpioa, &timer2, &adc1,  3, 4,    3}, /* D8/PA3 */
+    {&gpioa, &timer2, &adc1,  2, 3,    2}, /* D9/PA2 */
+    {&gpioa, &timer2, &adc1,  1, 2,    1}, /* D10/PA1 */
+    {&gpioa, &timer2, &adc1,  0, 1,    0}, /* D11/PA0 */
+    {&gpioc,   NULL, NULL, 15, 0, ADCx}, /* D12/PC15 */
+    {&gpioc,   NULL, NULL, 14, 0, ADCx}, /* D13/PC14 */
+    {&gpioc,   NULL, NULL, 13, 0, ADCx}, /* D14/PC13 */
 
     /* Bottom header */
 
-    {&gpiob, &timer4, NULL,  7, 2, ADCx, 0}, /* D15/PB7 */
-    {&gpiob, &timer4, NULL,  6, 1, ADCx, 0}, /* D16/PB6 */
-    {&gpiob,   NULL, NULL,  5, 0, ADCx, 0}, /* D17/PB5 */
-    {&gpiob,   NULL, NULL,  4, 0, ADCx, 0}, /* D18/PB4 */
-    {&gpiob,   NULL, NULL,  3, 0, ADCx, 0}, /* D19/PB3 */
-    {&gpioa,   NULL, NULL, 15, 0, ADCx, 0}, /* D20/PA15 */
-    {&gpioa,   NULL, NULL, 14, 0, ADCx, 0}, /* D21/PA14 */
-    {&gpioa,   NULL, NULL, 13, 0, ADCx, 0}, /* D22/PA13 */
-    {&gpioa,   NULL, NULL, 12, 0, ADCx, 0}, /* D23/PA12 */
-    {&gpioa, &timer1, NULL, 11, 4, ADCx, 0}, /* D24/PA11 */
-    {&gpioa, &timer1, NULL, 10, 3, ADCx, 0}, /* D25/PA10 */
-    {&gpioa, &timer1, NULL,  9, 2, ADCx, 0}, /* D26/PA9 */
-    {&gpioa, &timer1, NULL,  8, 1, ADCx, 0}, /* D27/PA8 */
-    {&gpiob,   NULL, NULL, 15, 0, ADCx, 0}, /* D28/PB15 */
-    {&gpiob,   NULL, NULL, 14, 0, ADCx, 0}, /* D29/PB14 */
-    {&gpiob,   NULL, NULL, 13, 0, ADCx, 0}, /* D30/PB13 */
-    {&gpiob,   NULL, NULL, 12, 0, ADCx, 0}, /* D31/PB12 */
-    {&gpiob, &timer4, NULL,  8, 3, ADCx, 0}, /* D32/PB8 */
-    {&gpiob, &timer3, &adc1,  1, 4,    9, 0}, /* D33/PB1 */
+    {&gpiob, &timer4, NULL,  7, 2, ADCx}, /* D15/PB7 */
+    {&gpiob, &timer4, NULL,  6, 1, ADCx}, /* D16/PB6 */
+    {&gpiob,   NULL, NULL,  5, 0, ADCx}, /* D17/PB5 */
+    {&gpiob,   NULL, NULL,  4, 0, ADCx}, /* D18/PB4 */
+    {&gpiob,   NULL, NULL,  3, 0, ADCx}, /* D19/PB3 */
+    {&gpioa,   NULL, NULL, 15, 0, ADCx}, /* D20/PA15 */
+    {&gpioa,   NULL, NULL, 14, 0, ADCx}, /* D21/PA14 */
+    {&gpioa,   NULL, NULL, 13, 0, ADCx}, /* D22/PA13 */
+    {&gpioa,   NULL, NULL, 12, 0, ADCx}, /* D23/PA12 */
+    {&gpioa, &timer1, NULL, 11, 4, ADCx}, /* D24/PA11 */
+    {&gpioa, &timer1, NULL, 10, 3, ADCx}, /* D25/PA10 */
+    {&gpioa, &timer1, NULL,  9, 2, ADCx}, /* D26/PA9 */
+    {&gpioa, &timer1, NULL,  8, 1, ADCx}, /* D27/PA8 */
+    {&gpiob,   NULL, NULL, 15, 0, ADCx}, /* D28/PB15 */
+    {&gpiob,   NULL, NULL, 14, 0, ADCx}, /* D29/PB14 */
+    {&gpiob,   NULL, NULL, 13, 0, ADCx}, /* D30/PB13 */
+    {&gpiob,   NULL, NULL, 12, 0, ADCx}, /* D31/PB12 */
+    {&gpiob, &timer4, NULL,  8, 3, ADCx}, /* D32/PB8 */
+    {&gpiob, &timer3, &adc1,  1, 4,    9}, /* D33/PB1 */
 };
 
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
@@ -125,4 +125,4 @@ DEFINE_HWSERIAL(Serial1, 1);
 DEFINE_HWSERIAL(Serial2, 2);
 DEFINE_HWSERIAL(Serial3, 3);
 		
-	
+	
\ No newline at end of file
diff --git a/STM32F1/variants/maple_ret6/board.cpp b/STM32F1/variants/maple_ret6/board.cpp
index 82127ff88..fb9277985 100644
--- a/STM32F1/variants/maple_ret6/board.cpp
+++ b/STM32F1/variants/maple_ret6/board.cpp
@@ -82,66 +82,66 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
 	/* Top header */
 
-	{ &gpioa, &timer2, &adc1, 3, 4, 3, 0}, /* D0/PA3 */
-	{ &gpioa, &timer2, &adc1, 2, 3, 2, 0}, /* D1/PA2 */
-	{ &gpioa, &timer2, &adc1, 0, 1, 0, 0}, /* D2/PA0 */
-	{ &gpioa, &timer2, &adc1, 1, 2, 1, 0}, /* D3/PA1 */
-	{ &gpiob, NULL, NULL, 5, 0, ADCx, 0}, /* D4/PB5 */
-	{ &gpiob, &timer4, NULL, 6, 1, ADCx, 0}, /* D5/PB6 */
-	{ &gpioa, &timer1, NULL, 8, 1, ADCx, 0}, /* D6/PA8 */
-	{ &gpioa, &timer1, NULL, 9, 2, ADCx, 0}, /* D7/PA9 */
-	{ &gpioa, &timer1, NULL, 10, 3, ADCx, 0}, /* D8/PA10 */
-	{ &gpiob, &timer4, NULL, 7, 2, ADCx, 0}, /* D9/PB7 */
-	{ &gpioa, NULL, &adc1, 4, 0, 4, 0}, /* D10/PA4 */
-	{ &gpioa, &timer3, &adc1, 7, 2, 7, 0}, /* D11/PA7 */
-	{ &gpioa, &timer3, &adc1, 6, 1, 6, 0}, /* D12/PA6 */
-	{ &gpioa, NULL, &adc1, 5, 0, 5, 0}, /* D13/PA5 (LED) */
-	{ &gpiob, &timer4, NULL, 8, 3, ADCx, 0}, /* D14/PB8 */
+	{ &gpioa, &timer2, &adc1, 3, 4, 3 }, /* D0/PA3 */
+	{ &gpioa, &timer2, &adc1, 2, 3, 2 }, /* D1/PA2 */
+	{ &gpioa, &timer2, &adc1, 0, 1, 0 }, /* D2/PA0 */
+	{ &gpioa, &timer2, &adc1, 1, 2, 1 }, /* D3/PA1 */
+	{ &gpiob, NULL, NULL, 5, 0, ADCx }, /* D4/PB5 */
+	{ &gpiob, &timer4, NULL, 6, 1, ADCx }, /* D5/PB6 */
+	{ &gpioa, &timer1, NULL, 8, 1, ADCx }, /* D6/PA8 */
+	{ &gpioa, &timer1, NULL, 9, 2, ADCx }, /* D7/PA9 */
+	{ &gpioa, &timer1, NULL, 10, 3, ADCx }, /* D8/PA10 */
+	{ &gpiob, &timer4, NULL, 7, 2, ADCx }, /* D9/PB7 */
+	{ &gpioa, NULL, &adc1, 4, 0, 4 }, /* D10/PA4 */
+	{ &gpioa, &timer3, &adc1, 7, 2, 7 }, /* D11/PA7 */
+	{ &gpioa, &timer3, &adc1, 6, 1, 6 }, /* D12/PA6 */
+	{ &gpioa, NULL, &adc1, 5, 0, 5 }, /* D13/PA5 (LED) */
+	{ &gpiob, &timer4, NULL, 8, 3, ADCx }, /* D14/PB8 */
 
 	/* Little header */
 
-	{ &gpioc, NULL, &adc1, 0, 0, 10, 0}, /* D15/PC0 */
-	{ &gpioc, NULL, &adc1, 1, 0, 11, 0}, /* D16/PC1 */
-	{ &gpioc, NULL, &adc1, 2, 0, 12, 0}, /* D17/PC2 */
-	{ &gpioc, NULL, &adc1, 3, 0, 13, 0}, /* D18/PC3 */
-	{ &gpioc, NULL, &adc1, 4, 0, 14, 0}, /* D19/PC4 */
-	{ &gpioc, NULL, &adc1, 5, 0, 15, 0}, /* D20/PC5 */
+	{ &gpioc, NULL, &adc1, 0, 0, 10 }, /* D15/PC0 */
+	{ &gpioc, NULL, &adc1, 1, 0, 11 }, /* D16/PC1 */
+	{ &gpioc, NULL, &adc1, 2, 0, 12 }, /* D17/PC2 */
+	{ &gpioc, NULL, &adc1, 3, 0, 13 }, /* D18/PC3 */
+	{ &gpioc, NULL, &adc1, 4, 0, 14 }, /* D19/PC4 */
+	{ &gpioc, NULL, &adc1, 5, 0, 15 }, /* D20/PC5 */
 
 	/* External header */
 
-	{ &gpioc, NULL, NULL, 13, 0, ADCx, 0}, /* D21/PC13 */
-	{ &gpioc, NULL, NULL, 14, 0, ADCx, 0}, /* D22/PC14 */
-	{ &gpioc, NULL, NULL, 15, 0, ADCx, 0}, /* D23/PC15 */
-	{ &gpiob, &timer4, NULL, 9, 4, ADCx, 0}, /* D24/PB9 */
-	{ &gpiod, NULL, NULL, 2, 0, ADCx, 0}, /* D25/PD2 */
-	{ &gpioc, NULL, NULL, 10, 0, ADCx, 0}, /* D26/PC10 */
-	{ &gpiob, &timer3, &adc1, 0, 3, 8, 0}, /* D27/PB0 */
-	{ &gpiob, &timer3, &adc1, 1, 4, 9, 0}, /* D28/PB1 */
-	{ &gpiob, NULL, NULL, 10, 0, ADCx, 0}, /* D29/PB10 */
-	{ &gpiob, NULL, NULL, 11, 0, ADCx, 0}, /* D30/PB11 */
-	{ &gpiob, NULL, NULL, 12, 0, ADCx, 0}, /* D31/PB12 */
-	{ &gpiob, NULL, NULL, 13, 0, ADCx, 0}, /* D32/PB13 */
-	{ &gpiob, NULL, NULL, 14, 0, ADCx, 0}, /* D33/PB14 */
-	{ &gpiob, NULL, NULL, 15, 0, ADCx, 0}, /* D34/PB15 */
-	{ &gpioc, &timer8, NULL, 6, 1, ADCx, 0}, /* D35/PC6 */
-	{ &gpioc, &timer8, NULL, 7, 2, ADCx, 0}, /* D36/PC7 */
-	{ &gpioc, &timer8, NULL, 8, 3, ADCx, 0}, /* D37/PC8 */
-	{ &gpioc, &timer8, NULL, 9, 4, ADCx, 0}, /* D38/PC9 (BUT) */
+	{ &gpioc, NULL, NULL, 13, 0, ADCx }, /* D21/PC13 */
+	{ &gpioc, NULL, NULL, 14, 0, ADCx }, /* D22/PC14 */
+	{ &gpioc, NULL, NULL, 15, 0, ADCx }, /* D23/PC15 */
+	{ &gpiob, &timer4, NULL, 9, 4, ADCx }, /* D24/PB9 */
+	{ &gpiod, NULL, NULL, 2, 0, ADCx }, /* D25/PD2 */
+	{ &gpioc, NULL, NULL, 10, 0, ADCx }, /* D26/PC10 */
+	{ &gpiob, &timer3, &adc1, 0, 3, 8 }, /* D27/PB0 */
+	{ &gpiob, &timer3, &adc1, 1, 4, 9 }, /* D28/PB1 */
+	{ &gpiob, NULL, NULL, 10, 0, ADCx }, /* D29/PB10 */
+	{ &gpiob, NULL, NULL, 11, 0, ADCx }, /* D30/PB11 */
+	{ &gpiob, NULL, NULL, 12, 0, ADCx }, /* D31/PB12 */
+	{ &gpiob, NULL, NULL, 13, 0, ADCx }, /* D32/PB13 */
+	{ &gpiob, NULL, NULL, 14, 0, ADCx }, /* D33/PB14 */
+	{ &gpiob, NULL, NULL, 15, 0, ADCx }, /* D34/PB15 */
+	{ &gpioc, &timer8, NULL, 6, 1, ADCx }, /* D35/PC6 */
+	{ &gpioc, &timer8, NULL, 7, 2, ADCx }, /* D36/PC7 */
+	{ &gpioc, &timer8, NULL, 8, 3, ADCx }, /* D37/PC8 */
+	{ &gpioc, &timer8, NULL, 9, 4, ADCx }, /* D38/PC9 (BUT) */
 
 	/* JTAG header */
 
-	{ &gpioa, NULL, NULL, 13, 0, ADCx, 0}, /* D39/PA13 */
-	{ &gpioa, NULL, NULL, 14, 0, ADCx, 0}, /* D40/PA14 */
-	{ &gpioa, NULL, NULL, 15, 0, ADCx, 0}, /* D41/PA15 */
-	{ &gpiob, NULL, NULL, 3, 0, ADCx, 0}, /* D42/PB3  */
-	{ &gpiob, NULL, NULL, 4, 0, ADCx, 0}, /* D43/PB4  */
+	{ &gpioa, NULL, NULL, 13, 0, ADCx }, /* D39/PA13 */
+	{ &gpioa, NULL, NULL, 14, 0, ADCx }, /* D40/PA14 */
+	{ &gpioa, NULL, NULL, 15, 0, ADCx }, /* D41/PA15 */
+	{ &gpiob, NULL, NULL, 3, 0, ADCx }, /* D42/PB3  */
+	{ &gpiob, NULL, NULL, 4, 0, ADCx }, /* D43/PB4  */
 
-	{ &gpioc, NULL, NULL, 11, 0, ADCx, 0}, /* D44/PC11 UART4_RX/SDIO_D3 */
-	{ &gpioc, NULL, NULL, 12, 0, ADCx, 0}, /* D45/PC12 UART5_TX/SDIO_CK */
+	{ &gpioc, NULL, NULL, 11, 0, ADCx }, /* D44/PC11 UART4_RX/SDIO_D3 */
+	{ &gpioc, NULL, NULL, 12, 0, ADCx }, /* D45/PC12 UART5_TX/SDIO_CK */
 
-	{ &gpiod, NULL, NULL, 0, 0, ADCx, 0}, /* PD0 OSC_IN */
-	{ &gpiod, NULL, NULL, 1, 0, ADCx, 0}, /* PD1  OSC_OUT */
-	{ &gpiob, NULL, NULL, 2, 0, ADCx, 0}, /* PB2  */
+	{ &gpiod, NULL, NULL, 0, 0, ADCx }, /* PD0 OSC_IN */
+	{ &gpiod, NULL, NULL, 1, 0, ADCx }, /* PD1  OSC_OUT */
+	{ &gpiob, NULL, NULL, 2, 0, ADCx }, /* PB2  */
 };
 
 /*  Basically everything that is defined as having a timer us PWM */
@@ -175,4 +175,4 @@ DEFINE_HWSERIAL(Serial1, 1);
 DEFINE_HWSERIAL(Serial2, 2);
 DEFINE_HWSERIAL(Serial3, 3);
 DEFINE_HWSERIAL_UART(Serial4, 4);
-DEFINE_HWSERIAL_UART(Serial5, 5);
+DEFINE_HWSERIAL_UART(Serial5, 5);
\ No newline at end of file
diff --git a/STM32F1/variants/microduino/board.cpp b/STM32F1/variants/microduino/board.cpp
index 51c80248d..2a002887b 100644
--- a/STM32F1/variants/microduino/board.cpp
+++ b/STM32F1/variants/microduino/board.cpp
@@ -54,35 +54,35 @@ void boardInit(void) {
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
 
-    {&gpioa, &timer1, NULL, 10, 3, ADCx, 0}, /* D0(RxD0)/PA10 */
-    {&gpioa, &timer1, NULL,  9, 2, ADCx, 0}, /* D1(TxD1)/PA9 */
-    {&gpiob,   NULL, NULL, 11, 0, ADCx, 0}, /* D2/PB11 */
-    {&gpiob,   NULL, NULL, 10, 0, ADCx, 0}, /* D3/PB10 */
-    {&gpioa, &timer1, NULL,  8, 1, ADCx, 0}, /* D4/PA8 */
-    {&gpioa,   NULL, NULL, 13, 0, ADCx, 0}, /* D5/PA13 */
-    {&gpioa,   NULL, NULL, 14, 0, ADCx, 0}, /* D6/PA14 */
-    {&gpioa,   NULL, NULL, 15, 0, ADCx, 0}, /* D7/PA15 */
-    {&gpiob,   NULL, NULL,  3, 0, ADCx, 0}, /* D8/PB3 */
-    {&gpiob,   NULL, NULL,  4, 0, ADCx, 0}, /* D9/PB4 */
-    {&gpioa,   NULL, &adc1,  4, 0,    4, 0}, /* D10/PA4 */
-    {&gpioa, &timer3, &adc1,  7, 2,    7, 0}, /* D11/PA7 */
-    {&gpioa, &timer3, &adc1,  6, 1,    6, 0}, /* D12/PA6 */
-    {&gpioa,   NULL, &adc1,  5, 0,    5, 0}, /* D13/PA5 */
-
-    {&gpioa, &timer2, &adc1,  0, 1,    0, 0}, /* D14(A0)/PA0 */
-    {&gpioa, &timer2, &adc1,  1, 2,    1, 0}, /* D15(A1)/PA1 */
-    {&gpioa, &timer2, &adc1,  2, 3,    2, 0}, /* D16(A2)/PA2 */
-    {&gpioa, &timer2, &adc1,  3, 4,    3, 0}, /* D17(A3)/PA3 */
-    {&gpiob, &timer4, NULL,  7, 2, ADCx, 0}, /* D18(A4)/PB7 */
-    {&gpiob, &timer4, NULL,  6, 1, ADCx, 0}, /* D19(A5)/PB6 */
-    {&gpiob, &timer3, &adc1,  0, 3,    8, 0}, /* D20(A6)/PB0 */
-    {&gpiob, &timer3, &adc1,  1, 4,    9, 0}, /* D21(A7)/PB1 */
-
-    {&gpioa,   NULL, NULL, 12, 0, ADCx, 0}, /* D22/PA12/USB D+ */
-    {&gpioa, &timer1, NULL, 11, 4, ADCx, 0}, /* D23/PA11/USB D- */
+    {&gpioa, &timer1, NULL, 10, 3, ADCx}, /* D0(RxD0)/PA10 */
+    {&gpioa, &timer1, NULL,  9, 2, ADCx}, /* D1(TxD1)/PA9 */
+    {&gpiob,   NULL, NULL, 11, 0, ADCx}, /* D2/PB11 */
+    {&gpiob,   NULL, NULL, 10, 0, ADCx}, /* D3/PB10 */
+    {&gpioa, &timer1, NULL,  8, 1, ADCx}, /* D4/PA8 */
+    {&gpioa,   NULL, NULL, 13, 0, ADCx}, /* D5/PA13 */
+    {&gpioa,   NULL, NULL, 14, 0, ADCx}, /* D6/PA14 */
+    {&gpioa,   NULL, NULL, 15, 0, ADCx}, /* D7/PA15 */
+    {&gpiob,   NULL, NULL,  3, 0, ADCx}, /* D8/PB3 */
+    {&gpiob,   NULL, NULL,  4, 0, ADCx}, /* D9/PB4 */
+    {&gpioa,   NULL, &adc1,  4, 0,    4}, /* D10/PA4 */
+    {&gpioa, &timer3, &adc1,  7, 2,    7}, /* D11/PA7 */
+    {&gpioa, &timer3, &adc1,  6, 1,    6}, /* D12/PA6 */
+    {&gpioa,   NULL, &adc1,  5, 0,    5}, /* D13/PA5 */
+
+    {&gpioa, &timer2, &adc1,  0, 1,    0}, /* D14(A0)/PA0 */
+    {&gpioa, &timer2, &adc1,  1, 2,    1}, /* D15(A1)/PA1 */
+    {&gpioa, &timer2, &adc1,  2, 3,    2}, /* D16(A2)/PA2 */
+    {&gpioa, &timer2, &adc1,  3, 4,    3}, /* D17(A3)/PA3 */
+    {&gpiob, &timer4, NULL,  7, 2, ADCx}, /* D18(A4)/PB7 */
+    {&gpiob, &timer4, NULL,  6, 1, ADCx}, /* D19(A5)/PB6 */
+    {&gpiob, &timer3, &adc1,  0, 3,    8}, /* D20(A6)/PB0 */
+    {&gpiob, &timer3, &adc1,  1, 4,    9}, /* D21(A7)/PB1 */
+
+    {&gpioa,   NULL, NULL, 12, 0, ADCx}, /* D22/PA12/USB D+ */
+    {&gpioa, &timer1, NULL, 11, 4, ADCx}, /* D23/PA11/USB D- */
 
     // FIXME: find out which pin is the button, if any
-    {&gpiob,   NULL, NULL,  8, 0, ADCx, 0}, /* D24/PB8??/Button */
+    {&gpiob,   NULL, NULL,  8, 0, ADCx}, /* D24/PB8??/Button */
 };
 
 extern const uint8 boardPWMPins[BOARD_NR_PWM_PINS] __FLASH__ = {
diff --git a/STM32F1/variants/nucleo_f103rb/board.cpp b/STM32F1/variants/nucleo_f103rb/board.cpp
index a70a188ca..9f3e08ae7 100644
--- a/STM32F1/variants/nucleo_f103rb/board.cpp
+++ b/STM32F1/variants/nucleo_f103rb/board.cpp
@@ -96,55 +96,55 @@ rcc_pll_cfg w_board_pll_cfg = {RCC_PLLSRC_HSI_DIV_2, &pll_data};
 extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 
     /* Arduino-like header, right connectors */
-    {&gpioa, NULL,   &adc1,   3,  0,    3, 0}, /*  D0/PA3 */
-    {&gpioa, NULL,   &adc1,   2,  0,    2, 0}, /*  D1/PA2 */
-    {&gpioa, &timer1, NULL,  10,  3, ADCx, 0}, /*  D2/PA10 */
-    {&gpiob, &timer2, NULL,   3,  2, ADCx, 0}, /*  D3/PB3  */
-    {&gpiob, &timer3, NULL,   5,  2, ADCx, 0}, /*  D4/PB5 */
-    {&gpiob, &timer3, NULL,   4,  1, ADCx, 0}, /*  D5/PB4  */
-    {&gpiob, &timer2, NULL,  10,  3, ADCx, 0}, /*  D6/PB10 */
-    {&gpioa, &timer1, NULL,   8,  1, ADCx, 0}, /*  D7/PA8 */
+    {&gpioa, NULL,   &adc1,   3,  0,    3}, /*  D0/PA3 */
+    {&gpioa, NULL,   &adc1,   2,  0,    2}, /*  D1/PA2 */
+    {&gpioa, &timer1, NULL,  10,  3, ADCx}, /*  D2/PA10 */
+    {&gpiob, &timer2, NULL,   3,  2, ADCx}, /*  D3/PB3  */
+    {&gpiob, &timer3, NULL,   5,  2, ADCx}, /*  D4/PB5 */
+    {&gpiob, &timer3, NULL,   4,  1, ADCx}, /*  D5/PB4  */
+    {&gpiob, &timer2, NULL,  10,  3, ADCx}, /*  D6/PB10 */
+    {&gpioa, &timer1, NULL,   8,  1, ADCx}, /*  D7/PA8 */
                    
-    {&gpioa, &timer1, NULL,   9,  2, ADCx, 0}, /*  D8/PA9  */
-    {&gpioc, NULL,   NULL,   7,  0, ADCx, 0}, /*  D9/PC7  */
-    {&gpiob, &timer4, NULL,   6,  1, ADCx, 0}, /*  D10/PB6 */
-    {&gpioa, NULL,   &adc1,   7,  0,    7, 0}, /*  D11/PA7 */
-    {&gpioa, NULL,   &adc1,   6,  0, 	  6, 0}, /*  D12/PA6 */
-    {&gpioa, NULL,   NULL,   5,  0, ADCx, 0}, /*  D13/PA5 LED - no &adc12_IN5 !*/
-    {&gpiob, &timer4, NULL,   9,  4, ADCx, 0}, /*  D14/PB9 */
-    {&gpiob, &timer4, NULL,   8,  3, ADCx, 0}, /*  D15/PB8 */
+    {&gpioa, &timer1, NULL,   9,  2, ADCx}, /*  D8/PA9  */
+    {&gpioc, NULL,   NULL,   7,  0, ADCx}, /*  D9/PC7  */
+    {&gpiob, &timer4, NULL,   6,  1, ADCx}, /*  D10/PB6 */
+    {&gpioa, NULL,   &adc1,   7,  0,    7}, /*  D11/PA7 */
+    {&gpioa, NULL,   &adc1,   6,  0, 	  6}, /*  D12/PA6 */
+    {&gpioa, NULL,   NULL,   5,  0, ADCx}, /*  D13/PA5 LED - no &adc12_IN5 !*/
+    {&gpiob, &timer4, NULL,   9,  4, ADCx}, /*  D14/PB9 */
+    {&gpiob, &timer4, NULL,   8,  3, ADCx}, /*  D15/PB8 */
                    
-    {&gpioa, NULL,   &adc1,   0,  0,    0, 0}, /*  D16/A0/PA0 */
-    {&gpioa, NULL,   &adc1,   1,  0,    1, 0}, /*  D17/A1/PA1 */
-    {&gpioa, NULL,   &adc1,   4,  0,    4, 0}, /*  D18/A2/PA4 */
-    {&gpiob, &timer3, &adc1,   0,  3,    8, 0}, /*  D19/A3/PB0 */
-    {&gpioc, NULL,   &adc1,   1,  0,   11, 0}, /*  D20/A4/PC1 */
-    {&gpioc, NULL,   &adc1,   0,  0,   10, 0}, /*  D21/A5/PC0 */
+    {&gpioa, NULL,   &adc1,   0,  0,    0}, /*  D16/A0/PA0 */
+    {&gpioa, NULL,   &adc1,   1,  0,    1}, /*  D17/A1/PA1 */
+    {&gpioa, NULL,   &adc1,   4,  0,    4}, /*  D18/A2/PA4 */
+    {&gpiob, &timer3, &adc1,   0,  3,    8}, /*  D19/A3/PB0 */
+    {&gpioc, NULL,   &adc1,   1,  0,   11}, /*  D20/A4/PC1 */
+    {&gpioc, NULL,   &adc1,   0,  0,   10}, /*  D21/A5/PC0 */
                    
-    {&gpioc, NULL,   NULL,  10,  0, ADCx, 0}, /*  D22/PC10 */
-	{&gpioc, NULL,   NULL,  12,  0, ADCx, 0}, /*  D23/PC12 */
-    {&gpiob, &timer4, NULL,   7,  2, ADCx, 0}, /*  D24/PB7 */
-    {&gpioc, NULL,   NULL,  13,  0, ADCx, 0}, /*  D25/PC13 USER BLUE BUTTON */
-    {&gpioc, NULL,   NULL,  14,  0, ADCx, 0}, /*  D26/PC14 */
-    {&gpioc, NULL,   NULL,  15,  0, ADCx, 0}, /*  D27/PC15 */
-    {&gpioc, NULL,   &adc1,   2,  0,   12, 0}, /*  D28/PC2 */
-    {&gpioc, NULL,   &adc1,   3,  0,   13, 0}, /*  D29/PC3 */
-    {&gpioc, NULL,   NULL,  11,  0, ADCx, 0}, /*  D30/PC11 */
-    {&gpiod, NULL,   NULL,   2,  0, ADCx, 0}, /*  D31/PD2 */
-    {&gpioc, NULL,   NULL,   9,  0, ADCx, 0}, /*  D32/PC9 */
-    {&gpioc, NULL,   NULL,   8,  0, ADCx, 0}, /*  D33/PC8 */
-    {&gpioc, NULL,   NULL,   6,  0, ADCx, 0}, /*  D34/PC6 */
-    {&gpioc, NULL,   &adc1,   5,  0,   15, 0}, /*  D35/PC5 */
-    {&gpioa, NULL,   NULL,  12,  0, ADCx, 0}, /*  D36/PA12 */
-    {&gpioa, &timer1, NULL,  11,  4, ADCx, 0}, /*  D37/PA11 */
-    {&gpiob, NULL,   NULL,  12,  0, ADCx, 0}, /*  D38/PB12 */
-    {&gpiob, &timer2, NULL,  11,  4, ADCx, 0}, /*  D39/PB11 PWM-not working?*/
-    {&gpiob, NULL,   NULL,  2,   0, ADCx, 0}, /*  D40/PB2 BOOT1 !!*/
-    {&gpiob, &timer3, &adc1,   1,  4,    9, 0}, /*  D41/PB1 */
-    {&gpiob, NULL,   NULL,  15,  0, ADCx, 0}, /*  D42/PB15 */
-    {&gpiob, NULL,   NULL,  14,  0, ADCx, 0}, /*  D43/PB14 */
-    {&gpiob, NULL,   NULL,  13,  0, ADCx, 0}, /*  D44/PB13 */
-    {&gpioc, NULL,   &adc1,   4,  0,   14, 0}, /*  D45/PC4 */
+    {&gpioc, NULL,   NULL,  10,  0, ADCx}, /*  D22/PC10 */
+	{&gpioc, NULL,   NULL,  12,  0, ADCx}, /*  D23/PC12 */
+    {&gpiob, &timer4, NULL,   7,  2, ADCx}, /*  D24/PB7 */
+    {&gpioc, NULL,   NULL,  13,  0, ADCx}, /*  D25/PC13 USER BLUE BUTTON */
+    {&gpioc, NULL,   NULL,  14,  0, ADCx}, /*  D26/PC14 */
+    {&gpioc, NULL,   NULL,  15,  0, ADCx}, /*  D27/PC15 */
+    {&gpioc, NULL,   &adc1,   2,  0,   12}, /*  D28/PC2 */
+    {&gpioc, NULL,   &adc1,   3,  0,   13}, /*  D29/PC3 */
+    {&gpioc, NULL,   NULL,  11,  0, ADCx}, /*  D30/PC11 */
+    {&gpiod, NULL,   NULL,   2,  0, ADCx}, /*  D31/PD2 */
+    {&gpioc, NULL,   NULL,   9,  0, ADCx}, /*  D32/PC9 */
+    {&gpioc, NULL,   NULL,   8,  0, ADCx}, /*  D33/PC8 */
+    {&gpioc, NULL,   NULL,   6,  0, ADCx}, /*  D34/PC6 */
+    {&gpioc, NULL,   &adc1,   5,  0,   15}, /*  D35/PC5 */
+    {&gpioa, NULL,   NULL,  12,  0, ADCx}, /*  D36/PA12 */
+    {&gpioa, &timer1, NULL,  11,  4, ADCx}, /*  D37/PA11 */
+    {&gpiob, NULL,   NULL,  12,  0, ADCx}, /*  D38/PB12 */
+    {&gpiob, &timer2, NULL,  11,  4, ADCx}, /*  D39/PB11 PWM-not working?*/
+    {&gpiob, NULL,   NULL,  2,   0, ADCx}, /*  D40/PB2 BOOT1 !!*/
+    {&gpiob, &timer3, &adc1,   1,  4,    9}, /*  D41/PB1 */
+    {&gpiob, NULL,   NULL,  15,  0, ADCx}, /*  D42/PB15 */
+    {&gpiob, NULL,   NULL,  14,  0, ADCx}, /*  D43/PB14 */
+    {&gpiob, NULL,   NULL,  13,  0, ADCx}, /*  D44/PB13 */
+    {&gpioc, NULL,   &adc1,   4,  0,   14}, /*  D45/PC4 */
   //  PMAP_ROW(&gpioa,  13,   NULL,  0, NULL, ADCx), /* D41/PA13 do not use*/
    // PMAP_ROW(&gpioa,  14,   NULL,  0, NULL, ADCx), /* D42/PA14  do not use*/
    // PMAP_ROW(&gpioa,  15,   &timer2,  1, NULL, ADCx), /* D43/PA15 do not use*/
@@ -256,4 +256,4 @@ MOSI alternate functions on the GPIO ports.
    DEFINE_HWSERIAL(Serial, 3);// Use HW Serial 2 as "Serial"
    DEFINE_HWSERIAL(Serial1, 2);
    DEFINE_HWSERIAL(Serial2, 1);
-#endif
+#endif
\ No newline at end of file
diff --git a/STM32F3/cores/maple/wirish/boards_private.h b/STM32F3/cores/maple/wirish/boards_private.h
index 332843ddf..49867ca77 100644
--- a/STM32F3/cores/maple/wirish/boards_private.h
+++ b/STM32F3/cores/maple/wirish/boards_private.h
@@ -42,7 +42,7 @@
 
 /* Makes the PIN_MAP rows more human-readable. */
 #define PMAP_ROW(gpio_dev, gpio_bit, timer_dev, timer_ch, adc_dev, adc_ch) \
-    { gpio_dev, timer_dev, adc_dev, gpio_bit, timer_ch, adc_ch, 0}
+    { gpio_dev, timer_dev, adc_dev, gpio_bit, timer_ch, adc_ch }
 
 namespace wirish {
     namespace priv {

From 95dde2ec1017a2ee42561194d8d01a9d69b66957 Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Fri, 1 Dec 2017 17:17:28 +0100
Subject: [PATCH 244/307] Removed pinMode from PIN_MAP

---
 STM32F1/cores/maple/wirish_types.h            | 1 -
 STM32F1/variants/generic_stm32f103r/board.cpp | 1 -
 STM32F1/variants/generic_stm32f103z/board.cpp | 3 +--
 STM32F1/variants/maple_ret6/board.cpp         | 3 +--
 4 files changed, 2 insertions(+), 6 deletions(-)

diff --git a/STM32F1/cores/maple/wirish_types.h b/STM32F1/cores/maple/wirish_types.h
index 195cda83a..14fb692fd 100644
--- a/STM32F1/cores/maple/wirish_types.h
+++ b/STM32F1/cores/maple/wirish_types.h
@@ -55,7 +55,6 @@ typedef struct stm32_pin_info {
     uint8 gpio_bit;             /**< Pin's GPIO port bit. */
     uint8 timer_channel;        /**< Timer channel, or 0 if none. */
     uint8 adc_channel;          /**< Pin ADC channel, or ADCx if none. */
-	uint8 pinMode; 				/**< mode specific by pinMode call (Roger Clark added to optimize compatibility with Arduino API*/
 } stm32_pin_info;
 
 /**
diff --git a/STM32F1/variants/generic_stm32f103r/board.cpp b/STM32F1/variants/generic_stm32f103r/board.cpp
index 3e3589c23..891e4e944 100644
--- a/STM32F1/variants/generic_stm32f103r/board.cpp
+++ b/STM32F1/variants/generic_stm32f103r/board.cpp
@@ -78,7 +78,6 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
     uint8 gpio_bit;             Pin's GPIO port bit. 
     uint8 timer_channel;        Timer channel, or 0 if none. 
     uint8 adc_channel;          Pin ADC channel, or ADCx if none. 
-	uint8 pinMode; 				mode specific by pinMode call (Roger Clark added to optimize compatibility with Arduino API
 */
 
     {&gpioa, &timer2, &adc1,  0, 1,    0}, /* PA0 */
diff --git a/STM32F1/variants/generic_stm32f103z/board.cpp b/STM32F1/variants/generic_stm32f103z/board.cpp
index 830479e96..500f9b86d 100644
--- a/STM32F1/variants/generic_stm32f103z/board.cpp
+++ b/STM32F1/variants/generic_stm32f103z/board.cpp
@@ -77,7 +77,6 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
     uint8 gpio_bit;             Pin's GPIO port bit. 
     uint8 timer_channel;        Timer channel, or 0 if none. 
     uint8 adc_channel;          Pin ADC channel, or ADCx if none. 
-	uint8 pinMode; 				mode specific by pinMode call (Roger Clark added to optimize compatibility with Arduino API
 */
 
     {&gpioa, &timer2, &adc1,  0, 1,    0}, /* PA0 */
@@ -231,4 +230,4 @@ extern const uint8 boardUsedPins[BOARD_NR_USED_PINS] __FLASH__ = {
 	DEFINE_HWSERIAL(Serial2, 3);
 	DEFINE_HWSERIAL_UART(Serial3, 4);
 	DEFINE_HWSERIAL_UART(Serial4, 5);
-#endif
\ No newline at end of file
+#endif
diff --git a/STM32F1/variants/maple_ret6/board.cpp b/STM32F1/variants/maple_ret6/board.cpp
index fb9277985..2b4e2e49d 100644
--- a/STM32F1/variants/maple_ret6/board.cpp
+++ b/STM32F1/variants/maple_ret6/board.cpp
@@ -77,7 +77,6 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
     uint8 gpio_bit;             Pin's GPIO port bit. 
     uint8 timer_channel;        Timer channel, or 0 if none. 
     uint8 adc_channel;          Pin ADC channel, or ADCx if none. 
-	uint8 pinMode; 				mode specific by pinMode call (Roger Clark added to optimize compatibility with Arduino API
 */
 
 	/* Top header */
@@ -175,4 +174,4 @@ DEFINE_HWSERIAL(Serial1, 1);
 DEFINE_HWSERIAL(Serial2, 2);
 DEFINE_HWSERIAL(Serial3, 3);
 DEFINE_HWSERIAL_UART(Serial4, 4);
-DEFINE_HWSERIAL_UART(Serial5, 5);
\ No newline at end of file
+DEFINE_HWSERIAL_UART(Serial5, 5);

From 595b128cac7b087c3ee96ea662e690f9f38a1520 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sun, 3 Dec 2017 14:39:35 +1100
Subject: [PATCH 245/307] Modification to allow SSD1306 example to compile,
 following changes to Wire to use HWire by default. Note this code is only
 known to compile , it may not work with the SSD1306 display

---
 .../Adafruit_SSD1306_STM32.cpp                | 20 +++++++++----------
 .../Adafruit_SSD1306/Adafruit_SSD1306_STM32.h |  4 ++--
 2 files changed, 12 insertions(+), 12 deletions(-)

diff --git a/STM32F1/libraries/Adafruit_SSD1306/Adafruit_SSD1306_STM32.cpp b/STM32F1/libraries/Adafruit_SSD1306/Adafruit_SSD1306_STM32.cpp
index 349203915..d70aa13f4 100644
--- a/STM32F1/libraries/Adafruit_SSD1306/Adafruit_SSD1306_STM32.cpp
+++ b/STM32F1/libraries/Adafruit_SSD1306/Adafruit_SSD1306_STM32.cpp
@@ -22,10 +22,10 @@ All text above, and the splash screen below must be included in any redistributi
 //#endif
 #include <stdlib.h>
 
-//#include <HWIRE.h>
-#include <HardWire.h>
+//#include <Wire.h>
+#include <Wire.h>
 //HardWire HWIRE(1,I2C_FAST_MODE); // I2c1
-HardWire HWIRE(2,I2C_FAST_MODE); // I2c2
+//HardWire HWIRE(2,I2C_FAST_MODE); // I2c2
 #include "Adafruit_GFX.h"
 #include "Adafruit_SSD1306_STM32.h"
 
@@ -197,7 +197,7 @@ void Adafruit_SSD1306::begin(uint8_t vccstate, uint8_t i2caddr, bool reset) {
   else
   {
     // I2C Init
-    HWIRE.begin();
+    Wire.begin();
       
 #ifdef __SAM3X8E__
     // Force 400 KHz I2C, rawr! (Uses pins 20, 21 for SDA, SCL)
@@ -359,10 +359,10 @@ void Adafruit_SSD1306::ssd1306_command(uint8_t c) {
   {
     // I2C
     uint8_t control = 0x00;   // Co = 0, D/C = 0
-    HWIRE.beginTransmission(_i2caddr);
+    Wire.beginTransmission(_i2caddr);
     WIRE_WRITE(control);
     WIRE_WRITE(c);
-    HWIRE.endTransmission();
+    Wire.endTransmission();
   }
 }
 
@@ -473,10 +473,10 @@ void Adafruit_SSD1306::ssd1306_data(uint8_t c) {
   {
     // I2C
     uint8_t control = 0x40;   // Co = 0, D/C = 1
-    HWIRE.beginTransmission(_i2caddr);
+    Wire.beginTransmission(_i2caddr);
     WIRE_WRITE(control);
     WIRE_WRITE(c);
-    HWIRE.endTransmission();
+    Wire.endTransmission();
   }
 }
 
@@ -525,14 +525,14 @@ void Adafruit_SSD1306::display(void) {
     // I2C
     for (uint16_t i=0; i<(SSD1306_LCDWIDTH*SSD1306_LCDHEIGHT/8); i++) {
       // send a bunch of data in one xmission
-      HWIRE.beginTransmission(_i2caddr);
+      Wire.beginTransmission(_i2caddr);
       WIRE_WRITE(0x40);
       for (uint8_t x=0; x<16; x++) {
   WIRE_WRITE(buffer[i]);
   i++;
       }
       i--;
-      HWIRE.endTransmission();
+      Wire.endTransmission();
     }
 /*
 #ifndef __SAM3X8E__
diff --git a/STM32F1/libraries/Adafruit_SSD1306/Adafruit_SSD1306_STM32.h b/STM32F1/libraries/Adafruit_SSD1306/Adafruit_SSD1306_STM32.h
index 0686d763f..f91ff1b0e 100644
--- a/STM32F1/libraries/Adafruit_SSD1306/Adafruit_SSD1306_STM32.h
+++ b/STM32F1/libraries/Adafruit_SSD1306/Adafruit_SSD1306_STM32.h
@@ -18,10 +18,10 @@ All text above, and the splash screen must be included in any redistribution
 
 #if ARDUINO >= 100
  #include "Arduino.h"
- #define WIRE_WRITE HWIRE.write
+ #define WIRE_WRITE Wire.write
 #else
  #include "WProgram.h"
-  #define WIRE_WRITE HWIRE.send
+  #define WIRE_WRITE Wire.send
 #endif
 /*
 #ifdef __SAM3X8E__

From dbfb68cf916f044c83b2bd42aa9aaaf78641a705 Mon Sep 17 00:00:00 2001
From: aster94 <enzo.gib@gmail.com>
Date: Wed, 6 Dec 2017 21:52:00 +0100
Subject: [PATCH 246/307] Add files via upload

---
 STM32F1/libraries/Wire/SoftWire.cpp | 40 ++++++++++++++---------------
 STM32F1/libraries/Wire/SoftWire.h   | 12 ++++-----
 STM32F1/libraries/Wire/Wire.cpp     | 18 ++++++-------
 STM32F1/libraries/Wire/Wire.h       | 16 ++++++------
 4 files changed, 43 insertions(+), 43 deletions(-)

diff --git a/STM32F1/libraries/Wire/SoftWire.cpp b/STM32F1/libraries/Wire/SoftWire.cpp
index 781bb976f..4e3cdd587 100644
--- a/STM32F1/libraries/Wire/SoftWire.cpp
+++ b/STM32F1/libraries/Wire/SoftWire.cpp
@@ -25,7 +25,7 @@
  *****************************************************************************/
 
 /**
- * @file Wire.cpp
+ * @file SoftWire.cpp
  * @author Trystan Jones <crenn6977@gmail.com>
  * @brief Wire library, uses the WireBase to create the primary interface
  *        while keeping low level interactions invisible to the user.
@@ -54,7 +54,7 @@
  * - always start with i2c_delay rather than end
  */
 
-void TwoWire::set_scl(bool state) {
+void SoftWire::set_scl(bool state) {
     I2C_DELAY(this->i2c_delay);
 
 	gpio_write_bit(sclDevice,sclBit, state);
@@ -65,30 +65,30 @@ void TwoWire::set_scl(bool state) {
     }
 }
 
-void TwoWire::set_sda(bool state) {
+void SoftWire::set_sda(bool state) {
 	I2C_DELAY(this->i2c_delay);
 	gpio_write_bit(sdaDevice,sdaBit, state);
     //digitalWrite(this->sda_pin, state);
 }
 
-void TwoWire::i2c_start() {
+void SoftWire::i2c_start() {
     set_sda(LOW);
     set_scl(LOW);
 }
 
-void TwoWire::i2c_stop() {
+void SoftWire::i2c_stop() {
     set_sda(LOW);
     set_scl(HIGH);
     set_sda(HIGH);
 }
 
-void TwoWire::i2c_repeated_start() {
+void SoftWire::i2c_repeated_start() {
     set_sda(HIGH);
     set_scl(HIGH);
     set_sda(LOW);
 }
 
-bool TwoWire::i2c_get_ack() {
+bool SoftWire::i2c_get_ack() {
     set_scl(LOW);
     set_sda(HIGH);
     set_scl(HIGH);
@@ -98,19 +98,19 @@ bool TwoWire::i2c_get_ack() {
     return ret;
 }
 
-void TwoWire::i2c_send_ack() {
+void SoftWire::i2c_send_ack() {
     set_sda(LOW);
     set_scl(HIGH);
     set_scl(LOW);
 }
 
-void TwoWire::i2c_send_nack() {
+void SoftWire::i2c_send_nack() {
     set_sda(HIGH);
     set_scl(HIGH);
     set_scl(LOW);
 }
 
-uint8 TwoWire::i2c_shift_in() {
+uint8 SoftWire::i2c_shift_in() {
     uint8 data = 0;
     set_sda(HIGH);
 
@@ -124,7 +124,7 @@ uint8 TwoWire::i2c_shift_in() {
     return data;
 }
 
-void TwoWire::i2c_shift_out(uint8 val) {
+void SoftWire::i2c_shift_out(uint8 val) {
     int i;
     for (i = 0; i < 8; i++) {
         set_sda(!!(val & (1 << (7 - i)) ) );
@@ -134,7 +134,7 @@ void TwoWire::i2c_shift_out(uint8 val) {
 }
 
 //process needs to be updated for repeated start.
-uint8 TwoWire::process(uint8 stop) {
+uint8 SoftWire::process(uint8 stop) {
     itc_msg.xferred = 0;
 
     uint8 sla_addr = (itc_msg.addr << 1);
@@ -183,18 +183,18 @@ uint8 TwoWire::process(uint8 stop) {
 }
 
 // For compatibility with legacy code
-uint8 TwoWire::process(){
+uint8 SoftWire::process(){
 	return process(true);
 }
 
 // TODO: Add in Error Handling if pins is out of range for other Maples
 // TODO: Make delays more capable
-TwoWire::TwoWire(uint8 scl, uint8 sda, uint8 delay) : i2c_delay(delay) {
+SoftWire::SoftWire(uint8 scl, uint8 sda, uint8 delay) : i2c_delay(delay) {
     this->scl_pin=scl;
     this->sda_pin=sda;
 }
 
-void TwoWire::begin(uint8 self_addr) {
+void SoftWire::begin(uint8 self_addr) {
     tx_buf_idx = 0;
     tx_buf_overflow = false;
     rx_buf_idx = 0;
@@ -210,7 +210,7 @@ void TwoWire::begin(uint8 self_addr) {
     set_sda(HIGH);
 }
 
-void TwoWire::end()
+void SoftWire::end()
 {
 	if (this->scl_pin)
 	{
@@ -222,7 +222,7 @@ void TwoWire::end()
 	}
 }
 
-void TwoWire::setClock(uint32_t frequencyHz)
+void SoftWire::setClock(uint32_t frequencyHz)
 {
 	switch(frequencyHz)
 	{
@@ -236,11 +236,11 @@ void TwoWire::setClock(uint32_t frequencyHz)
 	}
 }
 
-TwoWire::~TwoWire() {
+SoftWire::~SoftWire() {
     this->scl_pin=0;
     this->sda_pin=0;
 }
 
 // Declare the instance that the users of the library can use
-//TwoWire Wire(SCL, SDA, SOFT_STANDARD);
-//TwoWire Wire(PB6, PB7, SOFT_FAST);
+//SoftWire Wire(SCL, SDA, SOFT_STANDARD);
+//SoftWire Wire(PB6, PB7, SOFT_FAST);
diff --git a/STM32F1/libraries/Wire/SoftWire.h b/STM32F1/libraries/Wire/SoftWire.h
index 136dc3d8c..b5c43dba3 100644
--- a/STM32F1/libraries/Wire/SoftWire.h
+++ b/STM32F1/libraries/Wire/SoftWire.h
@@ -25,7 +25,7 @@
  *****************************************************************************/
 
 /**
- * @file Wire.h
+ * @file SoftWire.h
  * @author Trystan Jones <crenn6977@gmail.com>
  * @brief Wire library, uses the WireBase to create the primary interface
  *        while keeping low level interactions invisible to the user.
@@ -60,7 +60,7 @@
 
 
 
-class TwoWire : public WireBase {
+class SoftWire : public WireBase {
  public:
     uint8 		i2c_delay;
     uint8       scl_pin;
@@ -136,7 +136,7 @@ class TwoWire : public WireBase {
      * Accept pin numbers for SCL and SDA lines. Set the delay needed
      * to create the timing for I2C's Standard Mode and Fast Mode.
      */
-    TwoWire(uint8 scl=SCL, uint8 sda=SDA, uint8 delay=SOFT_STANDARD);
+    SoftWire(uint8 scl=SCL, uint8 sda=SDA, uint8 delay=SOFT_STANDARD);
 
     /*
      * Sets pins SDA and SCL to OUPTUT_OPEN_DRAIN, joining I2C bus as
@@ -155,9 +155,9 @@ class TwoWire : public WireBase {
     /*
      * If object is destroyed, set pin numbers to 0.
      */
-    ~TwoWire();
+    ~SoftWire();
 };
 
-//extern TwoWire Wire;
+//extern SoftWire Wire;
 
-#endif // _WIRE_H_
+#endif // _SOFTWIRE_H_
diff --git a/STM32F1/libraries/Wire/Wire.cpp b/STM32F1/libraries/Wire/Wire.cpp
index a026e2ef7..dbf4c663b 100644
--- a/STM32F1/libraries/Wire/Wire.cpp
+++ b/STM32F1/libraries/Wire/Wire.cpp
@@ -25,7 +25,7 @@
  *****************************************************************************/
 
 /**
- * @file HardWire.cpp
+ * @file TwoWire.cpp
  * @author Trystan Jones <crenn6977@gmail.com>
  * @brief Wire library, uses the hardware I2C available in the Maple to
  *        interact with I2C slave devices.
@@ -38,7 +38,7 @@
 
 #include "Wire.h"
 
-uint8 HardWire::process(uint8 stop) {
+uint8 TwoWire::process(uint8 stop) {
     int8 res = i2c_master_xfer(sel_hard, &itc_msg, 1, 0);
     if (res == I2C_ERROR_PROTOCOL) {
         if (sel_hard->error_flags & I2C_SR1_AF) { /* NACK */
@@ -55,12 +55,12 @@ uint8 HardWire::process(uint8 stop) {
     return res;
 }
 
-uint8 HardWire::process(){
+uint8 TwoWire::process(){
 	return process(true);
 }
 
 // TODO: Add in Error Handling if devsel is out of range for other Maples
-HardWire::HardWire(uint8 dev_sel, uint8 flags) {
+TwoWire::TwoWire(uint8 dev_sel, uint8 flags) {
     if (dev_sel == 1) {
         sel_hard = I2C1;
     } else if (dev_sel == 2) {
@@ -71,21 +71,21 @@ HardWire::HardWire(uint8 dev_sel, uint8 flags) {
     dev_flags = flags;
 }
 
-HardWire::~HardWire() {
+TwoWire::~TwoWire() {
     i2c_disable(sel_hard);
     sel_hard = 0;
 }
 
-void HardWire::begin(uint8 self_addr) {
+void TwoWire::begin(uint8 self_addr) {
     i2c_master_enable(sel_hard, dev_flags);
 }
 
-void HardWire::end() {
+void TwoWire::end() {
     i2c_disable(sel_hard);
     sel_hard = 0;
 }
 
-void HardWire::setClock(uint32_t frequencyHz)
+void TwoWire::setClock(uint32_t frequencyHz)
 {
 	switch(frequencyHz)
 	{
@@ -103,4 +103,4 @@ void HardWire::setClock(uint32_t frequencyHz)
 	}
 }
 
-HardWire Wire(1);
+TwoWire Wire(1);
diff --git a/STM32F1/libraries/Wire/Wire.h b/STM32F1/libraries/Wire/Wire.h
index 88d4a1bd4..f235aec57 100644
--- a/STM32F1/libraries/Wire/Wire.h
+++ b/STM32F1/libraries/Wire/Wire.h
@@ -25,7 +25,7 @@
  *****************************************************************************/
 
 /**
- * @file HardWire.h
+ * @file TwoWire.h
  * @author Trystan Jones <crenn6977@gmail.com>
  * @brief Wire library, uses the hardware I2C available in the Maple to
  *        interact with I2C slave devices.
@@ -36,14 +36,14 @@
  * users easy interaction with the I2C Hardware in a familiar method.
  */
 
-#ifndef _HARDWIRE_H_
-#define _HARDWIRE_H_
+#ifndef _TWOWIRE_H_
+#define _TWOWIRE_H_
 
 #include "WireBase.h"
 #include "wirish.h"
 #include <libmaple/i2c.h>
 
-class HardWire : public WireBase {
+class TwoWire : public WireBase {
 private:
     i2c_dev* sel_hard;
     uint8    dev_flags;
@@ -59,7 +59,7 @@ class HardWire : public WireBase {
      * Check if devsel is within range and enable selected I2C interface with
      * passed flags
      */
-    HardWire(uint8, uint8 = 0);
+    TwoWire(uint8, uint8 = 0);
 	
 	/*
 	 * Shuts down (disables) the hardware I2C
@@ -70,9 +70,9 @@ class HardWire : public WireBase {
     /*
      * Disables the I2C device and remove the device address.
      */
-    ~HardWire();
+    ~TwoWire();
 
     void begin(uint8 = 0x00);
 };
-extern HardWire Wire;
-#endif // _HARDWIRE_H_
+extern TwoWire Wire;
+#endif // _TWOWIRE_H_

From 98ed731df9fdf2516a1cb11c428807379d4763a7 Mon Sep 17 00:00:00 2001
From: aster94 <enzo.gib@gmail.com>
Date: Thu, 7 Dec 2017 20:09:30 +0100
Subject: [PATCH 247/307] Add files via upload

---
 .../examples/i2c_scanner_softwire/i2c_scanner_softwire.ino    | 2 +-
 STM32F1/libraries/Wire/rules.mk                               | 4 ++++
 2 files changed, 5 insertions(+), 1 deletion(-)

diff --git a/STM32F1/libraries/Wire/examples/i2c_scanner_softwire/i2c_scanner_softwire.ino b/STM32F1/libraries/Wire/examples/i2c_scanner_softwire/i2c_scanner_softwire.ino
index 0b4580a1e..f6bf6854e 100644
--- a/STM32F1/libraries/Wire/examples/i2c_scanner_softwire/i2c_scanner_softwire.ino
+++ b/STM32F1/libraries/Wire/examples/i2c_scanner_softwire/i2c_scanner_softwire.ino
@@ -5,7 +5,7 @@
 
 #include <SoftWire.h>
 
-TwoWire SWire(PB6, PB7, SOFT_FAST);
+SoftWire SWire(PB6, PB7, SOFT_FAST);
 
 
 void setup() {
diff --git a/STM32F1/libraries/Wire/rules.mk b/STM32F1/libraries/Wire/rules.mk
index e16f4db93..2b333327a 100644
--- a/STM32F1/libraries/Wire/rules.mk
+++ b/STM32F1/libraries/Wire/rules.mk
@@ -1,3 +1,7 @@
+#this makefile may not work since HardWire has been changed to the default Wire (TwoWire)
+#anyway this file should be useless
+
+
 # Standard things
 sp := $(sp).x
 dirstack_$(sp) := $(d)

From 2604eb6be242f76416bc89b7129f95f4b4a8598e Mon Sep 17 00:00:00 2001
From: aster94 <enzo.gib@gmail.com>
Date: Thu, 7 Dec 2017 20:10:35 +0100
Subject: [PATCH 248/307] Add files via upload

---
 STM32F1/libraries/OLED_I2C/OLED_I2C.h              | 2 +-
 STM32F1/libraries/OLED_I2C/hardware/arm/HW_STM32.h | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/STM32F1/libraries/OLED_I2C/OLED_I2C.h b/STM32F1/libraries/OLED_I2C/OLED_I2C.h
index 4bde83f28..abad639c3 100644
--- a/STM32F1/libraries/OLED_I2C/OLED_I2C.h
+++ b/STM32F1/libraries/OLED_I2C/OLED_I2C.h
@@ -87,7 +87,7 @@
  */
 #elif defined (__STM32F1__)
 #include "Arduino.h"
-//#include <HardWire.h>
+//#include <Wire.h>
 #include "hardware/arm/HW_STM32_defines.h"
 #endif
 
diff --git a/STM32F1/libraries/OLED_I2C/hardware/arm/HW_STM32.h b/STM32F1/libraries/OLED_I2C/hardware/arm/HW_STM32.h
index 25967c7ca..a892c43c7 100644
--- a/STM32F1/libraries/OLED_I2C/hardware/arm/HW_STM32.h
+++ b/STM32F1/libraries/OLED_I2C/hardware/arm/HW_STM32.h
@@ -1,7 +1,7 @@
 #include "Wire.h"
 #define WIRE_WRITE HWIRE.write
 
- HardWire HWIRE(2,I2C_FAST_MODE); // stupid compiler
+ TwoWire WIRE(2,I2C_FAST_MODE); // stupid compiler
 
 void OLED::_convert_float(char *buf, double num, int width, byte prec)
 {

From acc6cbc371963e9a500b5069223093ac07b5c187 Mon Sep 17 00:00:00 2001
From: aster94 <enzo.gib@gmail.com>
Date: Thu, 7 Dec 2017 20:11:17 +0100
Subject: [PATCH 249/307] Add files via upload

---
 .../libraries/Adafruit_SSD1306/Adafruit_SSD1306_STM32.cpp   | 6 +++---
 STM32F1/libraries/Adafruit_SSD1306/STM32 README.txt         | 6 +++---
 .../ssd1306_128x64_i2c_STM32/ssd1306_128x64_i2c_STM32.ino   | 2 +-
 3 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/STM32F1/libraries/Adafruit_SSD1306/Adafruit_SSD1306_STM32.cpp b/STM32F1/libraries/Adafruit_SSD1306/Adafruit_SSD1306_STM32.cpp
index d70aa13f4..34215da02 100644
--- a/STM32F1/libraries/Adafruit_SSD1306/Adafruit_SSD1306_STM32.cpp
+++ b/STM32F1/libraries/Adafruit_SSD1306/Adafruit_SSD1306_STM32.cpp
@@ -22,10 +22,10 @@ All text above, and the splash screen below must be included in any redistributi
 //#endif
 #include <stdlib.h>
 
-//#include <Wire.h>
+
 #include <Wire.h>
-//HardWire HWIRE(1,I2C_FAST_MODE); // I2c1
-//HardWire HWIRE(2,I2C_FAST_MODE); // I2c2
+//TwoWire WIRE(1,I2C_FAST_MODE); // I2c1
+//TwoWire WIRE(2,I2C_FAST_MODE); // I2c2
 #include "Adafruit_GFX.h"
 #include "Adafruit_SSD1306_STM32.h"
 
diff --git a/STM32F1/libraries/Adafruit_SSD1306/STM32 README.txt b/STM32F1/libraries/Adafruit_SSD1306/STM32 README.txt
index 54705cf10..518aabe39 100644
--- a/STM32F1/libraries/Adafruit_SSD1306/STM32 README.txt	
+++ b/STM32F1/libraries/Adafruit_SSD1306/STM32 README.txt	
@@ -1,6 +1,6 @@
 STM32 adaption by Matthias Diro, 25.03.2015
 Things to know:
-This adaption uses hardware I2C (hardwire.h), Port: I2c2. SDA=0, SCL=1 on maple mini
+This adaption uses hardware I2C (now Wire.h), Port: I2c2. SDA=0, SCL=1 on maple mini
 To change it to Port I2C1: 
-//HardWire HWIRE(1,I2C_FAST_MODE); // I2c1
-HardWire HWIRE(2,I2C_FAST_MODE); // I2c2
\ No newline at end of file
+//TwoWire WIRE(1,I2C_FAST_MODE); // I2c1
+TwoWire WIRE(2,I2C_FAST_MODE); // I2c2
\ No newline at end of file
diff --git a/STM32F1/libraries/Adafruit_SSD1306/examples/ssd1306_128x64_i2c_STM32/ssd1306_128x64_i2c_STM32.ino b/STM32F1/libraries/Adafruit_SSD1306/examples/ssd1306_128x64_i2c_STM32/ssd1306_128x64_i2c_STM32.ino
index b11bdc0ce..5b68b3fa0 100644
--- a/STM32F1/libraries/Adafruit_SSD1306/examples/ssd1306_128x64_i2c_STM32/ssd1306_128x64_i2c_STM32.ino
+++ b/STM32F1/libraries/Adafruit_SSD1306/examples/ssd1306_128x64_i2c_STM32/ssd1306_128x64_i2c_STM32.ino
@@ -1,7 +1,7 @@
 /*
 STM32 adaption by Matthias Diro, tested with maple mini and heltec OLED 12864 I2c; adress: 0x3C (SPI should work, but I didn't own one)
 Things to know:
- This adaption uses hardware I2C (hardwire.h), Port: I2c2. SDA=0, SCL=1 on maple mini
+ This adaption uses hardware I2C (now Wire.h), Port: I2c2. SDA=0, SCL=1 on maple mini
  further details: STM32_README.txt
 */
 /*********************************************************************

From 4ffdce29fe7bfc24b67acf1e4dbacbcd89b203a8 Mon Sep 17 00:00:00 2001
From: aster94 <enzo.gib@gmail.com>
Date: Fri, 8 Dec 2017 10:32:59 +0100
Subject: [PATCH 250/307] Add files via upload

---
 STM32F1/libraries/Wire/SoftWire.h           |   2 +-
 STM32F1/libraries/Wire/Wire.h               |   4 +-
 STM32F1/libraries/Wire/keywords.txt         |  17 +++
 STM32F1/libraries/Wire/utility/WireBase.cpp | 145 ++++++++++++++++++++
 STM32F1/libraries/Wire/utility/WireBase.h   | 145 ++++++++++++++++++++
 5 files changed, 310 insertions(+), 3 deletions(-)
 create mode 100644 STM32F1/libraries/Wire/keywords.txt
 create mode 100644 STM32F1/libraries/Wire/utility/WireBase.cpp
 create mode 100644 STM32F1/libraries/Wire/utility/WireBase.h

diff --git a/STM32F1/libraries/Wire/SoftWire.h b/STM32F1/libraries/Wire/SoftWire.h
index b5c43dba3..c42bca44a 100644
--- a/STM32F1/libraries/Wire/SoftWire.h
+++ b/STM32F1/libraries/Wire/SoftWire.h
@@ -40,7 +40,7 @@
 #ifndef _SOFTWIRE_H_
 #define _SOFTWIRE_H_
 
-#include "WireBase.h"
+#include "utility/WireBase.h"
 #include "wirish.h"
 
 /*
diff --git a/STM32F1/libraries/Wire/Wire.h b/STM32F1/libraries/Wire/Wire.h
index f235aec57..ab05d4216 100644
--- a/STM32F1/libraries/Wire/Wire.h
+++ b/STM32F1/libraries/Wire/Wire.h
@@ -25,7 +25,7 @@
  *****************************************************************************/
 
 /**
- * @file TwoWire.h
+ * @file Wire.h
  * @author Trystan Jones <crenn6977@gmail.com>
  * @brief Wire library, uses the hardware I2C available in the Maple to
  *        interact with I2C slave devices.
@@ -39,7 +39,7 @@
 #ifndef _TWOWIRE_H_
 #define _TWOWIRE_H_
 
-#include "WireBase.h"
+#include "utility/WireBase.h"
 #include "wirish.h"
 #include <libmaple/i2c.h>
 
diff --git a/STM32F1/libraries/Wire/keywords.txt b/STM32F1/libraries/Wire/keywords.txt
new file mode 100644
index 000000000..3fddb6fe5
--- /dev/null
+++ b/STM32F1/libraries/Wire/keywords.txt
@@ -0,0 +1,17 @@
+#######################################
+# Datatypes (KEYWORD1)
+#######################################
+TwoWire		KEYWORD1
+SoftWire	KEYWORD1
+
+#######################################
+# Methods and Functions (KEYWORD2)
+#######################################
+
+
+
+#######################################
+# Constants (LITERAL1)
+#######################################
+SOFT_STANDARD	LITERAL1
+SOFT_FAST		LITERAL1
\ No newline at end of file
diff --git a/STM32F1/libraries/Wire/utility/WireBase.cpp b/STM32F1/libraries/Wire/utility/WireBase.cpp
new file mode 100644
index 000000000..220d845d7
--- /dev/null
+++ b/STM32F1/libraries/Wire/utility/WireBase.cpp
@@ -0,0 +1,145 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 LeafLabs LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file WireBase.cpp
+ * @author Trystan Jones <crenn6977@gmail.com>
+ * @brief Wire library, following the majority of the interface from Arduino.
+ *        Provides a 'standard' interface to I2C (two-wire) communication for
+ *        derived classes.
+ */
+
+/*
+ * Library created by crenn to allow a system which would provide users the
+ * 'standardised' Arduino method for interfacing with I2C devices regardless of
+ * whether it is I2C hardware or emulating software.
+ */
+
+#include "WireBase.h"
+#include "wirish.h"
+
+void WireBase::begin(uint8 self_addr) {
+    tx_buf_idx = 0;
+    tx_buf_overflow = false;
+    rx_buf_idx = 0;
+    rx_buf_len = 0;
+}
+
+void WireBase::beginTransmission(uint8 slave_address) {
+    itc_msg.addr = slave_address;
+    itc_msg.data = &tx_buf[tx_buf_idx];
+    itc_msg.length = 0;
+    itc_msg.flags = 0;
+}
+
+void WireBase::beginTransmission(int slave_address) {
+    beginTransmission((uint8)slave_address);
+}
+
+uint8 WireBase::endTransmission(bool stop) {
+    uint8 retVal;
+    if (tx_buf_overflow) {
+        return EDATA;
+    }
+    retVal = process(stop);// Changed so that the return value from process is returned by this function see also the return line below
+    tx_buf_idx = 0;
+    tx_buf_overflow = false;
+    return retVal;//SUCCESS;
+}
+
+uint8 WireBase::endTransmission(){
+    endTransmission(true);
+}
+
+//TODO: Add the ability to queue messages (adding a boolean to end of function
+// call, allows for the Arduino style to stay while also giving the flexibility
+// to bulk send
+uint8 WireBase::requestFrom(uint8 address, int num_bytes) {
+    if (num_bytes > BUFFER_LENGTH) {
+        num_bytes = BUFFER_LENGTH;
+    }
+    itc_msg.addr = address;
+    itc_msg.flags = I2C_MSG_READ;
+    itc_msg.length = num_bytes;
+    itc_msg.data = &rx_buf[rx_buf_idx];
+    process();
+    rx_buf_len += itc_msg.xferred;
+    itc_msg.flags = 0;
+    return rx_buf_len;
+}
+
+uint8 WireBase::requestFrom(int address, int numBytes) {
+    return WireBase::requestFrom((uint8)address, numBytes);
+}
+
+void WireBase::write(uint8 value) {
+    if (tx_buf_idx == BUFFER_LENGTH) {
+        tx_buf_overflow = true;
+        return;
+    }
+    tx_buf[tx_buf_idx++] = value;
+    itc_msg.length++;
+}
+
+void WireBase::write(uint8* buf, int len) {
+    for (uint8 i = 0; i < len; i++) {
+        write(buf[i]);
+    }
+}
+
+void WireBase::write(int value) {
+    write((uint8)value);
+}
+
+void WireBase::write(int* buf, int len) {
+    write((uint8*)buf, (uint8)len);
+}
+
+void WireBase::write(char* buf) {
+    uint8 *ptr = (uint8*)buf;
+    while (*ptr) {
+        write(*ptr);
+        ptr++;
+    }
+}
+
+uint8 WireBase::available() {
+    return rx_buf_len - rx_buf_idx;
+}
+
+uint8 WireBase::read() {
+    if (rx_buf_idx == rx_buf_len) {
+        rx_buf_idx = 0;
+        rx_buf_len = 0;
+        return 0;
+    } else if (rx_buf_idx == (rx_buf_len-1)) {
+        uint8 temp = rx_buf[rx_buf_idx];
+        rx_buf_idx = 0;
+        rx_buf_len = 0;
+        return temp;
+    }
+    return rx_buf[rx_buf_idx++];
+}
diff --git a/STM32F1/libraries/Wire/utility/WireBase.h b/STM32F1/libraries/Wire/utility/WireBase.h
new file mode 100644
index 000000000..72facded6
--- /dev/null
+++ b/STM32F1/libraries/Wire/utility/WireBase.h
@@ -0,0 +1,145 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 LeafLabs LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file WireBase.h
+ * @author Trystan Jones <crenn6977@gmail.com>
+ * @brief Wire library, following the majority of the interface from Arduino.
+ *        Provides a 'standard' interface to I2C (two-wire) communication for
+ *        derived classes.
+ */
+
+/*
+ * Library created by crenn to allow a system which would provide users the
+ * 'standardised' Arduino method for interfacing with I2C devices regardless of
+ * whether it is I2C hardware or emulating software.
+ */
+
+#ifndef _WIREBASE_H_
+#define _WIREBASE_H_
+
+#include "wirish.h"
+#include <libmaple/i2c.h>
+
+#define BUFFER_LENGTH 32
+
+/* return codes from endTransmission() */
+#define SUCCESS   0        /* transmission was successful */
+#define EDATA     1        /* too much data */
+#define ENACKADDR 2        /* received nack on transmit of address */
+#define ENACKTRNS 3        /* received nack on transmit of data */
+#define EOTHER    4        /* other error */
+
+class WireBase { // Abstraction is awesome!
+protected:
+    i2c_msg itc_msg;
+    uint8 rx_buf[BUFFER_LENGTH];      /* receive buffer */
+    uint8 rx_buf_idx;               /* first unread idx in rx_buf */
+    uint8 rx_buf_len;               /* number of bytes read */
+
+    uint8 tx_buf[BUFFER_LENGTH];      /* transmit buffer */
+    uint8 tx_buf_idx;  // next idx available in tx_buf, -1 overflow
+    boolean tx_buf_overflow;
+
+    // Force derived classes to define process function
+    virtual uint8 process(uint8) = 0;
+    virtual uint8 process() = 0;
+public:
+    WireBase() {}
+    ~WireBase() {}
+
+    /*
+     * Initialises the class interface
+     */
+    // Allow derived classes to overwrite begin function
+    virtual void begin(uint8 = 0x00);
+
+    /*
+     * Sets up the transmission message to be processed
+     */
+    void beginTransmission(uint8);
+
+    /*
+     * Allow only 8 bit addresses to be used
+     */
+    void beginTransmission(int);
+
+    /*
+     * Call the process function to process the message if the TX
+     * buffer has not overflowed.
+     */
+    uint8 endTransmission(bool);
+    uint8 endTransmission(void);
+
+    /*
+     * Request bytes from a slave device and process the request,
+     * storing into the receiving buffer.
+     */
+    uint8 requestFrom(uint8, int);
+
+    /*
+     * Allow only 8 bit addresses to be used when requesting bytes
+     */
+    uint8 requestFrom(int, int);
+
+    /*
+     * Stack up bytes to be sent when transmitting
+     */
+    void write(uint8);
+
+    /*
+     * Stack up bytes from the array to be sent when transmitting
+     */
+    void write(uint8*, int);
+
+    /*
+     * Ensure that a sending data will only be 8-bit bytes
+     */
+    void write(int);
+
+    /*
+     * Ensure that an array sending data will only be 8-bit bytes
+     */
+    void write(int*, int);
+
+    /*
+     * Stack up bytes from a string to be sent when transmitting
+     */
+    void write(char*);
+
+    /*
+     * Return the amount of bytes that is currently in the receiving buffer
+     */
+    uint8 available();
+
+    /*
+     * Return the value of byte in the receiving buffer that is currently being
+     * pointed to
+     */
+    uint8 read();
+};
+
+#endif // _WIREBASE_H_

From 848602e0d6aa45cee6581848878579db34f69a0f Mon Sep 17 00:00:00 2001
From: aster94 <enzo.gib@gmail.com>
Date: Fri, 8 Dec 2017 10:36:00 +0100
Subject: [PATCH 251/307] Delete WireBase.h

---
 STM32F1/libraries/Wire/WireBase.h | 145 ------------------------------
 1 file changed, 145 deletions(-)
 delete mode 100644 STM32F1/libraries/Wire/WireBase.h

diff --git a/STM32F1/libraries/Wire/WireBase.h b/STM32F1/libraries/Wire/WireBase.h
deleted file mode 100644
index 72facded6..000000000
--- a/STM32F1/libraries/Wire/WireBase.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 LeafLabs LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file WireBase.h
- * @author Trystan Jones <crenn6977@gmail.com>
- * @brief Wire library, following the majority of the interface from Arduino.
- *        Provides a 'standard' interface to I2C (two-wire) communication for
- *        derived classes.
- */
-
-/*
- * Library created by crenn to allow a system which would provide users the
- * 'standardised' Arduino method for interfacing with I2C devices regardless of
- * whether it is I2C hardware or emulating software.
- */
-
-#ifndef _WIREBASE_H_
-#define _WIREBASE_H_
-
-#include "wirish.h"
-#include <libmaple/i2c.h>
-
-#define BUFFER_LENGTH 32
-
-/* return codes from endTransmission() */
-#define SUCCESS   0        /* transmission was successful */
-#define EDATA     1        /* too much data */
-#define ENACKADDR 2        /* received nack on transmit of address */
-#define ENACKTRNS 3        /* received nack on transmit of data */
-#define EOTHER    4        /* other error */
-
-class WireBase { // Abstraction is awesome!
-protected:
-    i2c_msg itc_msg;
-    uint8 rx_buf[BUFFER_LENGTH];      /* receive buffer */
-    uint8 rx_buf_idx;               /* first unread idx in rx_buf */
-    uint8 rx_buf_len;               /* number of bytes read */
-
-    uint8 tx_buf[BUFFER_LENGTH];      /* transmit buffer */
-    uint8 tx_buf_idx;  // next idx available in tx_buf, -1 overflow
-    boolean tx_buf_overflow;
-
-    // Force derived classes to define process function
-    virtual uint8 process(uint8) = 0;
-    virtual uint8 process() = 0;
-public:
-    WireBase() {}
-    ~WireBase() {}
-
-    /*
-     * Initialises the class interface
-     */
-    // Allow derived classes to overwrite begin function
-    virtual void begin(uint8 = 0x00);
-
-    /*
-     * Sets up the transmission message to be processed
-     */
-    void beginTransmission(uint8);
-
-    /*
-     * Allow only 8 bit addresses to be used
-     */
-    void beginTransmission(int);
-
-    /*
-     * Call the process function to process the message if the TX
-     * buffer has not overflowed.
-     */
-    uint8 endTransmission(bool);
-    uint8 endTransmission(void);
-
-    /*
-     * Request bytes from a slave device and process the request,
-     * storing into the receiving buffer.
-     */
-    uint8 requestFrom(uint8, int);
-
-    /*
-     * Allow only 8 bit addresses to be used when requesting bytes
-     */
-    uint8 requestFrom(int, int);
-
-    /*
-     * Stack up bytes to be sent when transmitting
-     */
-    void write(uint8);
-
-    /*
-     * Stack up bytes from the array to be sent when transmitting
-     */
-    void write(uint8*, int);
-
-    /*
-     * Ensure that a sending data will only be 8-bit bytes
-     */
-    void write(int);
-
-    /*
-     * Ensure that an array sending data will only be 8-bit bytes
-     */
-    void write(int*, int);
-
-    /*
-     * Stack up bytes from a string to be sent when transmitting
-     */
-    void write(char*);
-
-    /*
-     * Return the amount of bytes that is currently in the receiving buffer
-     */
-    uint8 available();
-
-    /*
-     * Return the value of byte in the receiving buffer that is currently being
-     * pointed to
-     */
-    uint8 read();
-};
-
-#endif // _WIREBASE_H_

From 558108d63e1490bc9977643b3a6e037a6ed07124 Mon Sep 17 00:00:00 2001
From: aster94 <enzo.gib@gmail.com>
Date: Fri, 8 Dec 2017 10:36:15 +0100
Subject: [PATCH 252/307] Delete WireBase.cpp

---
 STM32F1/libraries/Wire/WireBase.cpp | 145 ----------------------------
 1 file changed, 145 deletions(-)
 delete mode 100644 STM32F1/libraries/Wire/WireBase.cpp

diff --git a/STM32F1/libraries/Wire/WireBase.cpp b/STM32F1/libraries/Wire/WireBase.cpp
deleted file mode 100644
index 220d845d7..000000000
--- a/STM32F1/libraries/Wire/WireBase.cpp
+++ /dev/null
@@ -1,145 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 LeafLabs LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file WireBase.cpp
- * @author Trystan Jones <crenn6977@gmail.com>
- * @brief Wire library, following the majority of the interface from Arduino.
- *        Provides a 'standard' interface to I2C (two-wire) communication for
- *        derived classes.
- */
-
-/*
- * Library created by crenn to allow a system which would provide users the
- * 'standardised' Arduino method for interfacing with I2C devices regardless of
- * whether it is I2C hardware or emulating software.
- */
-
-#include "WireBase.h"
-#include "wirish.h"
-
-void WireBase::begin(uint8 self_addr) {
-    tx_buf_idx = 0;
-    tx_buf_overflow = false;
-    rx_buf_idx = 0;
-    rx_buf_len = 0;
-}
-
-void WireBase::beginTransmission(uint8 slave_address) {
-    itc_msg.addr = slave_address;
-    itc_msg.data = &tx_buf[tx_buf_idx];
-    itc_msg.length = 0;
-    itc_msg.flags = 0;
-}
-
-void WireBase::beginTransmission(int slave_address) {
-    beginTransmission((uint8)slave_address);
-}
-
-uint8 WireBase::endTransmission(bool stop) {
-    uint8 retVal;
-    if (tx_buf_overflow) {
-        return EDATA;
-    }
-    retVal = process(stop);// Changed so that the return value from process is returned by this function see also the return line below
-    tx_buf_idx = 0;
-    tx_buf_overflow = false;
-    return retVal;//SUCCESS;
-}
-
-uint8 WireBase::endTransmission(){
-    endTransmission(true);
-}
-
-//TODO: Add the ability to queue messages (adding a boolean to end of function
-// call, allows for the Arduino style to stay while also giving the flexibility
-// to bulk send
-uint8 WireBase::requestFrom(uint8 address, int num_bytes) {
-    if (num_bytes > BUFFER_LENGTH) {
-        num_bytes = BUFFER_LENGTH;
-    }
-    itc_msg.addr = address;
-    itc_msg.flags = I2C_MSG_READ;
-    itc_msg.length = num_bytes;
-    itc_msg.data = &rx_buf[rx_buf_idx];
-    process();
-    rx_buf_len += itc_msg.xferred;
-    itc_msg.flags = 0;
-    return rx_buf_len;
-}
-
-uint8 WireBase::requestFrom(int address, int numBytes) {
-    return WireBase::requestFrom((uint8)address, numBytes);
-}
-
-void WireBase::write(uint8 value) {
-    if (tx_buf_idx == BUFFER_LENGTH) {
-        tx_buf_overflow = true;
-        return;
-    }
-    tx_buf[tx_buf_idx++] = value;
-    itc_msg.length++;
-}
-
-void WireBase::write(uint8* buf, int len) {
-    for (uint8 i = 0; i < len; i++) {
-        write(buf[i]);
-    }
-}
-
-void WireBase::write(int value) {
-    write((uint8)value);
-}
-
-void WireBase::write(int* buf, int len) {
-    write((uint8*)buf, (uint8)len);
-}
-
-void WireBase::write(char* buf) {
-    uint8 *ptr = (uint8*)buf;
-    while (*ptr) {
-        write(*ptr);
-        ptr++;
-    }
-}
-
-uint8 WireBase::available() {
-    return rx_buf_len - rx_buf_idx;
-}
-
-uint8 WireBase::read() {
-    if (rx_buf_idx == rx_buf_len) {
-        rx_buf_idx = 0;
-        rx_buf_len = 0;
-        return 0;
-    } else if (rx_buf_idx == (rx_buf_len-1)) {
-        uint8 temp = rx_buf[rx_buf_idx];
-        rx_buf_idx = 0;
-        rx_buf_len = 0;
-        return temp;
-    }
-    return rx_buf[rx_buf_idx++];
-}

From 2d8af307dcf110d9bfeb82756f7fbe49ef3ef96f Mon Sep 17 00:00:00 2001
From: aster94 <enzo.gib@gmail.com>
Date: Fri, 8 Dec 2017 10:36:53 +0100
Subject: [PATCH 253/307] Add files via upload

---
 STM32F1/libraries/Wire/keywords.txt | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/STM32F1/libraries/Wire/keywords.txt b/STM32F1/libraries/Wire/keywords.txt
index 3fddb6fe5..4234cc5e6 100644
--- a/STM32F1/libraries/Wire/keywords.txt
+++ b/STM32F1/libraries/Wire/keywords.txt
@@ -14,4 +14,5 @@ SoftWire	KEYWORD1
 # Constants (LITERAL1)
 #######################################
 SOFT_STANDARD	LITERAL1
-SOFT_FAST		LITERAL1
\ No newline at end of file
+SOFT_FAST	LITERAL1
+I2C_FAST_MODE	LITERAL1
\ No newline at end of file

From b82911742f648970b277a5672f5b003029cbfd81 Mon Sep 17 00:00:00 2001
From: aster94 <enzo.gib@gmail.com>
Date: Fri, 8 Dec 2017 10:37:26 +0100
Subject: [PATCH 254/307] Delete i2c_scanner_hardwire.ino

---
 .../i2c_scanner_hardwire.ino                  | 76 -------------------
 1 file changed, 76 deletions(-)
 delete mode 100644 STM32F1/libraries/Wire/examples/i2c_scanner_hardwire/i2c_scanner_hardwire.ino

diff --git a/STM32F1/libraries/Wire/examples/i2c_scanner_hardwire/i2c_scanner_hardwire.ino b/STM32F1/libraries/Wire/examples/i2c_scanner_hardwire/i2c_scanner_hardwire.ino
deleted file mode 100644
index d2b3bd430..000000000
--- a/STM32F1/libraries/Wire/examples/i2c_scanner_hardwire/i2c_scanner_hardwire.ino
+++ /dev/null
@@ -1,76 +0,0 @@
-// --------------------------------------
-// i2c_scanner
-//
-// Version 1
-//    This program (or code that looks like it)
-//    can be found in many places.
-//    For example on the Arduino.cc forum.
-//    The original author is not know.
-// Version 2, Juni 2012, Using Arduino 1.0.1
-//     Adapted to be as simple as possible by Arduino.cc user Krodal
-// Version 3, Feb 26  2013
-//    V3 by louarnold
-// Version 4, March 3, 2013, Using Arduino 1.0.3
-//    by Arduino.cc user Krodal.
-//    Changes by louarnold removed.
-//    Scanning addresses changed from 0...127 to 1...119,
-//    according to the i2c scanner by Nick Gammon
-//    http://www.gammon.com.au/forum/?id=10896
-// Version 5, March 28, 2013
-//    As version 4, but address scans now to 127.
-//    A sensor seems to use address 120.
-// Version 6, August 1, 2015
-//    Modified to support HardWire for STM32duino
-//
-// This sketch tests the standard 7-bit addresses
-// Devices with higher bit address might not be seen properly.
-//
-
-#include <Wire.h>
-
-HardWire HWire(1, I2C_FAST_MODE); // I2c1
-
-void setup() {
-  Serial.begin(115200);
-  HWire.begin();
-  Serial.println("\nI2C Scanner");
-}
-
-
-void loop() {
-  byte error, address;
-  int nDevices;
-
-  Serial.println("Scanning...");
-
-  nDevices = 0;
-  for(address = 1; address < 127; address++) {
-    // The i2c_scanner uses the return value of
-    // the Write.endTransmisstion to see if
-    // a device did acknowledge to the address.
-
-    HWire.beginTransmission(address);
-    error = HWire.endTransmission();
-    
-    if (error == 0) {
-      Serial.print("I2C device found at address 0x");
-      if (address < 16) 
-        Serial.print("0");
-      Serial.println(address, HEX);
-
-      nDevices++;
-    }
-    else if (error == 4) {
-      Serial.print("Unknown error at address 0x");
-      if (address < 16) 
-        Serial.print("0");
-      Serial.println(address, HEX);
-    }    
-  }
-  if (nDevices == 0)
-    Serial.println("No I2C devices found");
-  else
-    Serial.println("done");
-
-  delay(5000);           // wait 5 seconds for next scan
-}
\ No newline at end of file

From e2a62de0346d469a324603155256f9ac3ee93695 Mon Sep 17 00:00:00 2001
From: aster94 <enzo.gib@gmail.com>
Date: Fri, 8 Dec 2017 10:39:53 +0100
Subject: [PATCH 255/307] Update i2c_scanner_wire.ino

---
 .../Wire/examples/i2c_scanner_wire/i2c_scanner_wire.ino     | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

diff --git a/STM32F1/libraries/Wire/examples/i2c_scanner_wire/i2c_scanner_wire.ino b/STM32F1/libraries/Wire/examples/i2c_scanner_wire/i2c_scanner_wire.ino
index 30224d2ca..0367b4eaa 100644
--- a/STM32F1/libraries/Wire/examples/i2c_scanner_wire/i2c_scanner_wire.ino
+++ b/STM32F1/libraries/Wire/examples/i2c_scanner_wire/i2c_scanner_wire.ino
@@ -26,6 +26,10 @@
 
 #include <Wire.h>
 
+//use IIC2
+//TwoWire WIRE2 (2,I2C_FAST_MODE);
+//#define Wire WIRE2
+
 
 void setup() {
 
@@ -71,4 +75,4 @@ void loop() {
     Serial.println("done");
 
   delay(5000);           // wait 5 seconds for next scan
-}
\ No newline at end of file
+}

From f66b9f10f387e468e3cfb96517beb17911941b3d Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sun, 10 Dec 2017 17:07:57 +1100
Subject: [PATCH 256/307] Hopefully fixed problem with tone() blocking when it
 should be non-blocking

---
 STM32F1/cores/maple/tone.cpp | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/STM32F1/cores/maple/tone.cpp b/STM32F1/cores/maple/tone.cpp
index 45cfa0eec..b249a784a 100644
--- a/STM32F1/cores/maple/tone.cpp
+++ b/STM32F1/cores/maple/tone.cpp
@@ -186,7 +186,8 @@ void tone(uint32_t pin, uint32_t freq, uint32_t duration) {
       pinMode(tone_pin, INPUT);
 
    }
-   while(tone_nhw) ; // blocks till duration elapsed
+   
+   //while(tone_nhw) ; // blocks till duration elapsed
 }
 
 ////////////////////////////////////////////////////////////////////////////////

From 87d1b1fdb7505d9605ccb58dee80a3311a300248 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Sun, 10 Dec 2017 09:35:48 +0100
Subject: [PATCH 257/307] Create new file "atomic.h"

as discussed here: https://github.com/rogerclarkmelbourne/Arduino_STM32/issues/403, taken from http://www.stm32duino.com/viewtopic.php?f=3&t=258&start=10
---
 .../system/libmaple/include/libmaple/atomic.h | 69 +++++++++++++++++++
 1 file changed, 69 insertions(+)
 create mode 100644 STM32F1/system/libmaple/include/libmaple/atomic.h

diff --git a/STM32F1/system/libmaple/include/libmaple/atomic.h b/STM32F1/system/libmaple/include/libmaple/atomic.h
new file mode 100644
index 000000000..db5e48975
--- /dev/null
+++ b/STM32F1/system/libmaple/include/libmaple/atomic.h
@@ -0,0 +1,69 @@
+/*
+* This is port of Dean Camera's ATOMIC_BLOCK macros for AVR to ARM Cortex M3 
+* v1.0
+* Mark Pendrith, Nov 27, 2012.
+*
+* From Mark:
+* >When I ported the macros I emailed Dean to ask what attribution would be
+* >appropriate, and here is his response:
+* >
+* >>Mark,
+* >>I think it's great that you've ported the macros; consider them
+* >>public domain, to do with whatever you wish. I hope you find them useful.
+* >>
+* >>Cheers!
+* >>- Dean 
+*/
+
+#ifndef _CORTEX_M3_ATOMIC_H_
+#define _CORTEX_M3_ATOMIC_H_
+
+static __inline__ uint32_t __get_primask(void) \
+{ uint32_t primask = 0; \
+  __asm__ volatile ("MRS %[result], PRIMASK\n\t":[result]"=r"(primask)::); \
+  return primask; } // returns 0 if interrupts enabled, 1 if disabled
+
+static __inline__ void __set_primask(uint32_t setval) \
+{ __asm__ volatile ("MSR PRIMASK, %[value]\n\t""dmb\n\t""dsb\n\t""isb\n\t"::[value]"r"(setval):); \
+  __asm__ volatile ("" ::: "memory");}
+
+static __inline__ uint32_t __iSeiRetVal(void) \
+{ __asm__ volatile ("CPSIE i\n\t""dmb\n\t""dsb\n\t""isb\n\t"); \
+  __asm__ volatile ("" ::: "memory"); return 1; }
+
+static __inline__ uint32_t __iCliRetVal(void) \
+{ __asm__ volatile ("CPSID i\n\t""dmb\n\t""dsb\n\t""isb\n\t"); \
+  __asm__ volatile ("" ::: "memory"); return 1; }
+
+static __inline__ void    __iSeiParam(const uint32_t *__s) \
+{ __asm__ volatile ("CPSIE i\n\t""dmb\n\t""dsb\n\t""isb\n\t"); \
+  __asm__ volatile ("" ::: "memory"); (void)__s; }
+
+static __inline__ void    __iCliParam(const uint32_t *__s) \
+{ __asm__ volatile ("CPSID i\n\t""dmb\n\t""dsb\n\t""isb\n\t"); \
+  __asm__ volatile ("" ::: "memory"); (void)__s; }
+
+static __inline__ void    __iRestore(const  uint32_t *__s) \
+{ __set_primask(*__s); __asm__ volatile ("dmb\n\t""dsb\n\t""isb\n\t"); \
+  __asm__ volatile ("" ::: "memory"); }
+
+
+#define ATOMIC_BLOCK(type) \
+for ( type, __ToDo = __iCliRetVal(); __ToDo ; __ToDo = 0 )
+
+#define ATOMIC_RESTORESTATE \
+uint32_t primask_save __attribute__((__cleanup__(__iRestore))) = __get_primask()
+
+#define ATOMIC_FORCEON \
+uint32_t primask_save __attribute__((__cleanup__(__iSeiParam))) = 0
+
+#define NONATOMIC_BLOCK(type) \
+for ( type, __ToDo = __iSeiRetVal(); __ToDo ;  __ToDo = 0 )
+   
+#define NONATOMIC_RESTORESTATE \
+uint32_t primask_save __attribute__((__cleanup__(__iRestore))) = __get_primask()
+
+#define NONATOMIC_FORCEOFF \
+uint32_t primask_save __attribute__((__cleanup__(__iCliParam))) = 0
+
+#endif

From 1cc4f791914c20e4c562c8778ba3b41e3a0063d7 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Mon, 11 Dec 2017 09:05:38 +1100
Subject: [PATCH 258/307] Moved atomic.h for better AVR compatibility

---
 STM32F1/system/libmaple/include/util/atomic.h | 69 +++++++++++++++++++
 1 file changed, 69 insertions(+)
 create mode 100644 STM32F1/system/libmaple/include/util/atomic.h

diff --git a/STM32F1/system/libmaple/include/util/atomic.h b/STM32F1/system/libmaple/include/util/atomic.h
new file mode 100644
index 000000000..db5e48975
--- /dev/null
+++ b/STM32F1/system/libmaple/include/util/atomic.h
@@ -0,0 +1,69 @@
+/*
+* This is port of Dean Camera's ATOMIC_BLOCK macros for AVR to ARM Cortex M3 
+* v1.0
+* Mark Pendrith, Nov 27, 2012.
+*
+* From Mark:
+* >When I ported the macros I emailed Dean to ask what attribution would be
+* >appropriate, and here is his response:
+* >
+* >>Mark,
+* >>I think it's great that you've ported the macros; consider them
+* >>public domain, to do with whatever you wish. I hope you find them useful.
+* >>
+* >>Cheers!
+* >>- Dean 
+*/
+
+#ifndef _CORTEX_M3_ATOMIC_H_
+#define _CORTEX_M3_ATOMIC_H_
+
+static __inline__ uint32_t __get_primask(void) \
+{ uint32_t primask = 0; \
+  __asm__ volatile ("MRS %[result], PRIMASK\n\t":[result]"=r"(primask)::); \
+  return primask; } // returns 0 if interrupts enabled, 1 if disabled
+
+static __inline__ void __set_primask(uint32_t setval) \
+{ __asm__ volatile ("MSR PRIMASK, %[value]\n\t""dmb\n\t""dsb\n\t""isb\n\t"::[value]"r"(setval):); \
+  __asm__ volatile ("" ::: "memory");}
+
+static __inline__ uint32_t __iSeiRetVal(void) \
+{ __asm__ volatile ("CPSIE i\n\t""dmb\n\t""dsb\n\t""isb\n\t"); \
+  __asm__ volatile ("" ::: "memory"); return 1; }
+
+static __inline__ uint32_t __iCliRetVal(void) \
+{ __asm__ volatile ("CPSID i\n\t""dmb\n\t""dsb\n\t""isb\n\t"); \
+  __asm__ volatile ("" ::: "memory"); return 1; }
+
+static __inline__ void    __iSeiParam(const uint32_t *__s) \
+{ __asm__ volatile ("CPSIE i\n\t""dmb\n\t""dsb\n\t""isb\n\t"); \
+  __asm__ volatile ("" ::: "memory"); (void)__s; }
+
+static __inline__ void    __iCliParam(const uint32_t *__s) \
+{ __asm__ volatile ("CPSID i\n\t""dmb\n\t""dsb\n\t""isb\n\t"); \
+  __asm__ volatile ("" ::: "memory"); (void)__s; }
+
+static __inline__ void    __iRestore(const  uint32_t *__s) \
+{ __set_primask(*__s); __asm__ volatile ("dmb\n\t""dsb\n\t""isb\n\t"); \
+  __asm__ volatile ("" ::: "memory"); }
+
+
+#define ATOMIC_BLOCK(type) \
+for ( type, __ToDo = __iCliRetVal(); __ToDo ; __ToDo = 0 )
+
+#define ATOMIC_RESTORESTATE \
+uint32_t primask_save __attribute__((__cleanup__(__iRestore))) = __get_primask()
+
+#define ATOMIC_FORCEON \
+uint32_t primask_save __attribute__((__cleanup__(__iSeiParam))) = 0
+
+#define NONATOMIC_BLOCK(type) \
+for ( type, __ToDo = __iSeiRetVal(); __ToDo ;  __ToDo = 0 )
+   
+#define NONATOMIC_RESTORESTATE \
+uint32_t primask_save __attribute__((__cleanup__(__iRestore))) = __get_primask()
+
+#define NONATOMIC_FORCEOFF \
+uint32_t primask_save __attribute__((__cleanup__(__iCliParam))) = 0
+
+#endif

From 63f4162c6cbc23b5467ce7ced2bcf5d2bf0bf385 Mon Sep 17 00:00:00 2001
From: Thomas Friedrichsmeier <thomas.friedrichsmeier@ruhr-uni-bochum.de>
Date: Tue, 12 Dec 2017 10:58:22 +0100
Subject: [PATCH 259/307] Fix compilation with -std=gnu++11

See https://github.com/rogerclarkmelbourne/Arduino_STM32/issues/402
---
 STM32F1/libraries/STM32ADC/src/STM32ADC.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/STM32F1/libraries/STM32ADC/src/STM32ADC.h b/STM32F1/libraries/STM32ADC/src/STM32ADC.h
index fd0588f5e..685eeb1d7 100644
--- a/STM32F1/libraries/STM32ADC/src/STM32ADC.h
+++ b/STM32F1/libraries/STM32ADC/src/STM32ADC.h
@@ -152,7 +152,7 @@ class STM32ADC{
     voidFuncPtr _DMA_int;
     voidFuncPtr _ADC_int;
     voidFuncPtr _AWD_int;
-    static const float _AverageSlope = 4.3; // mV/oC   //4.0 to 4.6
-    static const float _V25 = 1.43; //Volts //1.34 - 1.52
+    static constexpr float _AverageSlope = 4.3; // mV/oC   //4.0 to 4.6
+    static constexpr float _V25 = 1.43; //Volts //1.34 - 1.52
 
 };

From 951d0acf178b28d52919fb777874d90603c88883 Mon Sep 17 00:00:00 2001
From: victorpv <victor_pv@hotmail.com>
Date: Sat, 16 Dec 2017 17:25:57 -0600
Subject: [PATCH 260/307] Adding PB2 as in the Generic R and Z versions.

---
 STM32F1/variants/generic_stm32f103v/board.cpp | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/STM32F1/variants/generic_stm32f103v/board.cpp b/STM32F1/variants/generic_stm32f103v/board.cpp
index 9c137725a..c24140e1e 100644
--- a/STM32F1/variants/generic_stm32f103v/board.cpp
+++ b/STM32F1/variants/generic_stm32f103v/board.cpp
@@ -98,7 +98,7 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 	
 	{&gpiob, &timer3, &adc1,  0, 3,    8}, /* PB0 */ 
 	{&gpiob, &timer3, &adc1,  1, 4,    9}, /* PB1 */
-	/* NOTE PB2 is not included as its Boot 1 */
+	{&gpiob,   NULL, NULL,  2, 0, ADCx}, /* PB2  */	
 	{&gpiob,   NULL, NULL,  3, 0, ADCx}, /* PB3  */ //JTDO, SPI3_SCK / I2S3_CK/
     {&gpiob,   NULL, NULL,  4, 0, ADCx}, /* PB4  */ //NJTRST, SPI3_MISO
     {&gpiob,   NULL, NULL,  5, 0, ADCx}, /* PB5 */ //I2C1_SMBA/ SPI3_MOSI
@@ -196,4 +196,4 @@ extern const uint8 boardUsedPins[BOARD_NR_USED_PINS] __FLASH__ = {
 	DEFINE_HWSERIAL(Serial2, 3);
 	DEFINE_HWSERIAL_UART(Serial3, 4);
 	DEFINE_HWSERIAL_UART(Serial4, 5);
-#endif
\ No newline at end of file
+#endif

From e64dbc2d473a671f59f87655249247e34d026ef8 Mon Sep 17 00:00:00 2001
From: victorpv <victor_pv@hotmail.com>
Date: Sat, 16 Dec 2017 17:28:00 -0600
Subject: [PATCH 261/307] Add PB2 to enums as in the R and Z Generic boards

Can be used for output
---
 STM32F1/variants/generic_stm32f103v/board/board.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/STM32F1/variants/generic_stm32f103v/board/board.h b/STM32F1/variants/generic_stm32f103v/board/board.h
index 3bb680a78..ccd5ecf84 100644
--- a/STM32F1/variants/generic_stm32f103v/board/board.h
+++ b/STM32F1/variants/generic_stm32f103v/board/board.h
@@ -124,10 +124,10 @@
  * write code using low-level GPIO functionality. */
 enum {
 PA0,PA1,PA2,PA3,PA4,PA5,PA6,PA7,PA8,PA9,PA10,PA11,PA12,PA13,PA14,PA15,
-PB0,PB1,PB3,PB4,PB5,PB6,PB7,PB8,PB9,PB10,PB11,PB12,PB13,PB14,PB15,
+PB0,PB1,PB2,PB3,PB4,PB5,PB6,PB7,PB8,PB9,PB10,PB11,PB12,PB13,PB14,PB15,
 PC0,PC1,PC2,PC3,PC4,PC5,PC6,PC7,PC8,PC9,PC10,PC11,PC12,PC13,PC14,PC15,
 PD0,PD1,PD2,PD3,PD4,PD5,PD6,PD7,PD8,PD9,PD10,PD11,PD12,PD13,PD14,PD15,
 PE0,PE1,PE2,PE3,PE4,PE5,PE6,PE7,PE8,PE9,PE10,PE11,PE12,PE13,PE14,PE15,
-};/* Note PB2 is skipped as this is Boot1 and is not going to be much use as its likely to be pulled permanently low */
+};
 
 #endif

From 09812b48630ff59613cbe1e813b0766f08394296 Mon Sep 17 00:00:00 2001
From: victorpv <victor_pv@hotmail.com>
Date: Sun, 17 Dec 2017 15:20:07 -0600
Subject: [PATCH 262/307] Add comment to PB2 pin about boot1 function.

---
 STM32F1/variants/generic_stm32f103v/board.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/variants/generic_stm32f103v/board.cpp b/STM32F1/variants/generic_stm32f103v/board.cpp
index c24140e1e..d5596a2b5 100644
--- a/STM32F1/variants/generic_stm32f103v/board.cpp
+++ b/STM32F1/variants/generic_stm32f103v/board.cpp
@@ -98,7 +98,7 @@ extern const stm32_pin_info PIN_MAP[BOARD_NR_GPIO_PINS] = {
 	
 	{&gpiob, &timer3, &adc1,  0, 3,    8}, /* PB0 */ 
 	{&gpiob, &timer3, &adc1,  1, 4,    9}, /* PB1 */
-	{&gpiob,   NULL, NULL,  2, 0, ADCx}, /* PB2  */	
+	{&gpiob,   NULL, NULL,  2, 0, ADCx}, /* PB2  */	// Boot1 pin. It affects boot mode (flash, RAM, ROM)
 	{&gpiob,   NULL, NULL,  3, 0, ADCx}, /* PB3  */ //JTDO, SPI3_SCK / I2S3_CK/
     {&gpiob,   NULL, NULL,  4, 0, ADCx}, /* PB4  */ //NJTRST, SPI3_MISO
     {&gpiob,   NULL, NULL,  5, 0, ADCx}, /* PB5 */ //I2C1_SMBA/ SPI3_MOSI

From 066dacf797c4ab42d99b9cb9ea1468ed6e6118f4 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Fri, 29 Dec 2017 08:58:57 +0100
Subject: [PATCH 263/307] Update wirish_debug.cpp

reserve SWD lines only for debug
---
 STM32F1/cores/maple/stm32f1/wirish_debug.cpp | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/cores/maple/stm32f1/wirish_debug.cpp b/STM32F1/cores/maple/stm32f1/wirish_debug.cpp
index f0576165e..8f6cc98ee 100644
--- a/STM32F1/cores/maple/stm32f1/wirish_debug.cpp
+++ b/STM32F1/cores/maple/stm32f1/wirish_debug.cpp
@@ -37,5 +37,5 @@ void disableDebugPorts(void) {
 }
 
 void enableDebugPorts(void) {
-    afio_cfg_debug_ports(AFIO_DEBUG_FULL_SWJ);
+    afio_cfg_debug_ports(AFIO_DEBUG_SW_ONLY);
 }

From 63f784ff6f4823d754c0f270ce55a17931456079 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Tue, 2 Jan 2018 16:19:31 +0100
Subject: [PATCH 264/307] Update HW_STM32.h

remove static directive
---
 STM32F1/libraries/OLED_I2C/hardware/arm/HW_STM32.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/libraries/OLED_I2C/hardware/arm/HW_STM32.h b/STM32F1/libraries/OLED_I2C/hardware/arm/HW_STM32.h
index a892c43c7..20c1a16e5 100644
--- a/STM32F1/libraries/OLED_I2C/hardware/arm/HW_STM32.h
+++ b/STM32F1/libraries/OLED_I2C/hardware/arm/HW_STM32.h
@@ -109,7 +109,7 @@ void OLED::update()
 			twi->TWI_THR = scrbuf[b];
 			while ((twi->TWI_SR & TWI_SR_TXRDY) != TWI_SR_TXRDY) {};
              */
-            static byte aa=scrbuf[b];
+            byte aa=scrbuf[b];
             WIRE_WRITE(aa);
           
 		}

From 8540c6b08b20a5cd36964c6d1668269edbd2b5c5 Mon Sep 17 00:00:00 2001
From: BlackBrix-Editor <35255671+BlackBrix-Editor@users.noreply.github.com>
Date: Tue, 9 Jan 2018 11:23:16 +0100
Subject: [PATCH 265/307] option XTAL16M for boards with 16MHz-crystal

tested on STM32F103VE only but surely can be used on other STM32F103xC, STM32F103xD, STM32F103xE with the same clock PLL structure
---
 STM32F1/variants/generic_stm32f103v/wirish/boards.cpp | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/STM32F1/variants/generic_stm32f103v/wirish/boards.cpp b/STM32F1/variants/generic_stm32f103v/wirish/boards.cpp
index 254666f68..ddeaa57e8 100644
--- a/STM32F1/variants/generic_stm32f103v/wirish/boards.cpp
+++ b/STM32F1/variants/generic_stm32f103v/wirish/boards.cpp
@@ -130,6 +130,12 @@ static void setup_clocks(void) {
     wirish::priv::board_setup_clock_prescalers();
     rcc_configure_pll(&wirish::priv::w_board_pll_cfg);
 
+#ifdef XTAL16M
+    // 16MHz crystal (HSE)  
+    // in this case we additionally set the Bit 17 (PLLXTPRE=1)  =>  then HSE clock is divided by 2 before PLL entry
+    RCC_BASE->CFGR |= RCC_CFGR_PLLXTPRE;
+#endif
+    
     // Enable the PLL, and wait until it's ready.
     rcc_turn_on_clk(RCC_CLK_PLL);
     while(!rcc_is_clk_ready(RCC_CLK_PLL))

From d54de1cbb011fb2f4273a365340b2b3a29f23b6e Mon Sep 17 00:00:00 2001
From: BlackBrix-Editor <35255671+BlackBrix-Editor@users.noreply.github.com>
Date: Tue, 9 Jan 2018 12:21:48 +0100
Subject: [PATCH 266/307] corrected RAM-length = 48kByte for STM32F103VC

---
 STM32F1/variants/generic_stm32f103v/ld/stm32f103vc.ld | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/variants/generic_stm32f103v/ld/stm32f103vc.ld b/STM32F1/variants/generic_stm32f103v/ld/stm32f103vc.ld
index 7efca5d77..6079807f5 100644
--- a/STM32F1/variants/generic_stm32f103v/ld/stm32f103vc.ld
+++ b/STM32F1/variants/generic_stm32f103v/ld/stm32f103vc.ld
@@ -16,7 +16,7 @@
  */
 MEMORY
 {
-  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 64K
+  ram (rwx) : ORIGIN = 0x20000000, LENGTH = 48K
   rom (rx)  : ORIGIN = 0x08000000, LENGTH = 256K
 }
 

From 514cf856aae4e0f391c318d7677b53b4b04270a2 Mon Sep 17 00:00:00 2001
From: stevstrong <stevestrong@online.de>
Date: Thu, 18 Jan 2018 11:39:03 +0100
Subject: [PATCH 267/307] Update boards.txt

added error LED pin for generic F103C
---
 STM32F1/boards.txt | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/STM32F1/boards.txt b/STM32F1/boards.txt
index 49c12932a..cb9416a9c 100644
--- a/STM32F1/boards.txt
+++ b/STM32F1/boards.txt
@@ -346,6 +346,8 @@ genericSTM32F103C.build.variant=generic_stm32f103c
 genericSTM32F103C.build.vect=VECT_TAB_ADDR=0x8000000
 genericSTM32F103C.build.core=maple
 genericSTM32F103C.build.board=GENERIC_STM32F103C
+genericSTM32F103C.build.error_led_port=GPIOC
+genericSTM32F103C.build.error_led_pin=13
 genericSTM32F103C.upload.use_1200bps_touch=false
 genericSTM32F103C.upload.file_type=bin
 genericSTM32F103C.upload.auto_reset=true

From 9cd2f3a74366835930c4f3ba94193fc9db42ad10 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Sun, 21 Jan 2018 15:34:24 +1100
Subject: [PATCH 268/307] Manually committed changes from
 https://github.com/rogerclarkmelbourne/Arduino_STM32/pull/401, as that PR
 included changes to permissions on unrelated files in the tools

---
 STM32F1/cores/maple/libmaple/usb/stm32f1/usb.c        | 8 ++++++++
 STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c | 9 +++++++--
 STM32F1/system/libmaple/include/libmaple/usb.h        | 2 ++
 3 files changed, 17 insertions(+), 2 deletions(-)

diff --git a/STM32F1/cores/maple/libmaple/usb/stm32f1/usb.c b/STM32F1/cores/maple/libmaple/usb/stm32f1/usb.c
index f837eb64b..0feb745eb 100644
--- a/STM32F1/cores/maple/libmaple/usb/stm32f1/usb.c
+++ b/STM32F1/cores/maple/libmaple/usb/stm32f1/usb.c
@@ -120,6 +120,12 @@ static void usb_suspend(void) {
     USBLIB->state = USB_SUSPENDED;
 }
 
+void usb_power_off(void) {
+    USB_BASE->CNTR = USB_CNTR_FRES;
+    USB_BASE->ISTR = 0;
+    USB_BASE->CNTR = USB_CNTR_FRES + USB_CNTR_PDWN;
+}
+
 static void usb_resume_init(void) {
     uint16 cntr;
 
@@ -268,6 +274,7 @@ static void handle_out0(void);
 
 static void dispatch_ctr_lp() {
     uint16 istr;
+
     while (((istr = USB_BASE->ISTR) & USB_ISTR_CTR) != 0) {
         /* TODO WTF, figure this out: RM0008 says CTR is read-only,
          * but ST's firmware claims it's clear-only, and emphasizes
@@ -288,6 +295,7 @@ static void dispatch_ctr_lp() {
     }
 }
 
+
 /* FIXME Dataflow on endpoint 0 RX/TX status is based off of ST's
  * code, and is ugly/confusing in its use of SaveRState/SaveTState.
  * Fixing this requires filling in handle_in0(), handle_setup0(),
diff --git a/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c b/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c
index cba050f54..1f0b626a8 100644
--- a/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c
+++ b/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c
@@ -80,7 +80,6 @@ static uint8* usbGetConfigDescriptor(uint16 length);
 static uint8* usbGetStringDescriptor(uint16 length);
 static void usbSetConfiguration(void);
 static void usbSetDeviceAddress(void);
-
 /*
  * Descriptors
  */
@@ -392,6 +391,8 @@ void usb_cdcacm_enable(gpio_dev *disc_dev, uint8 disc_bit) {
 	}
 	
     /* Initialize the USB peripheral. */
+    /* One of the callbacks that will automatically happen from this will be to usbInit(),
+       which will power up the USB peripheral. */
     usb_init_usblib(USBLIB, ep_int_in, ep_int_out);
 }
 
@@ -403,6 +404,9 @@ void usb_cdcacm_disable(gpio_dev *disc_dev, uint8 disc_bit) {
 	{
 		gpio_write_bit(disc_dev, disc_bit, 1);
 	}
+    /* Powerdown the USB peripheral. It gets powered up again with usbInit(), which
+       gets called when usb_cdcacm_enable() is called. */
+    usb_power_off(); 
 }
 
 void usb_cdcacm_putc(char ch) {
@@ -644,7 +648,8 @@ static uint8* vcomGetSetLineCoding(uint16 length) {
 static void usbInit(void) {
     pInformation->Current_Configuration = 0;
 
-    USB_BASE->CNTR = USB_CNTR_FRES;
+    // Reset and power up the peripheral.
+    USB_BASE->CNTR = USB_CNTR_FRES; 
 
     USBLIB->irq_mask = 0;
     USB_BASE->CNTR = USBLIB->irq_mask;
diff --git a/STM32F1/system/libmaple/include/libmaple/usb.h b/STM32F1/system/libmaple/include/libmaple/usb.h
index ea24030d4..1ea06e9de 100644
--- a/STM32F1/system/libmaple/include/libmaple/usb.h
+++ b/STM32F1/system/libmaple/include/libmaple/usb.h
@@ -157,6 +157,8 @@ typedef struct usblib_dev {
 
 extern usblib_dev *USBLIB;
 
+void usb_power_off(void);
+
 void usb_init_usblib(usblib_dev *dev,
                      void (**ep_int_in)(void),
                      void (**ep_int_out)(void));

From 0f78c266ed2c571e9e48e4236b3721c88752f4db Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Thu, 14 Dec 2017 16:32:59 +0100
Subject: [PATCH 269/307] Added Wire_slave.h (no actual i2c slave
 implementation yet)

---
 STM32F1/libraries/Wire/Wire_slave.h           |   1 +
 STM32F1/libraries/Wire/library.properties     |  10 +
 .../SFRRanger_reader/SFRRanger_reader.ino     |  87 ++
 .../digital_potentiometer.ino                 |  38 +
 .../i2c_libmaple_slave/i2c_libmaple_slave.ino | 122 +++
 .../examples/master_reader/master_reader.ino  |  32 +
 .../examples/master_writer/master_writer.ino  |  31 +
 .../slave_receiver/slave_receiver.ino         |  38 +
 .../examples/slave_sender/slave_sender.ino    |  32 +
 .../libraries/WireSlave/library.properties    |  11 +
 STM32F1/libraries/WireSlave/src/Wire.h        |   1 +
 STM32F1/libraries/WireSlave/src/Wire.h.gch    | Bin 0 -> 1819056 bytes
 .../libraries/WireSlave/src/Wire_slave.cpp    | 106 +++
 STM32F1/libraries/WireSlave/src/Wire_slave.h  |  78 ++
 .../libraries/WireSlave/src/Wire_slave.h.gch  | Bin 0 -> 9475 bytes
 STM32F1/libraries/WireSlave/src/i2c_slave.c   | 789 ++++++++++++++++++
 .../libraries/WireSlave/src/i2c_slave.h.gch   | Bin 0 -> 9475 bytes
 .../WireSlave/src/libmaple/i2c_common_slave.h | 110 +++
 .../WireSlave/src/libmaple/i2c_slave.h        | 475 +++++++++++
 .../WireSlave/src/libmaple/i2c_slave.h.gch    | Bin 0 -> 9475 bytes
 .../WireSlave/src/utility/WireBase_slave.cpp  | 145 ++++
 .../WireSlave/src/utility/WireBase_slave.h    | 145 ++++
 .../src/utility/WireBase_slave.h.gch          | Bin 0 -> 9475 bytes
 23 files changed, 2251 insertions(+)
 create mode 100644 STM32F1/libraries/Wire/Wire_slave.h
 create mode 100644 STM32F1/libraries/Wire/library.properties
 create mode 100644 STM32F1/libraries/WireSlave/examples/SFRRanger_reader/SFRRanger_reader.ino
 create mode 100644 STM32F1/libraries/WireSlave/examples/digital_potentiometer/digital_potentiometer.ino
 create mode 100644 STM32F1/libraries/WireSlave/examples/i2c_libmaple_slave/i2c_libmaple_slave.ino
 create mode 100644 STM32F1/libraries/WireSlave/examples/master_reader/master_reader.ino
 create mode 100644 STM32F1/libraries/WireSlave/examples/master_writer/master_writer.ino
 create mode 100644 STM32F1/libraries/WireSlave/examples/slave_receiver/slave_receiver.ino
 create mode 100644 STM32F1/libraries/WireSlave/examples/slave_sender/slave_sender.ino
 create mode 100644 STM32F1/libraries/WireSlave/library.properties
 create mode 100644 STM32F1/libraries/WireSlave/src/Wire.h
 create mode 100644 STM32F1/libraries/WireSlave/src/Wire.h.gch
 create mode 100644 STM32F1/libraries/WireSlave/src/Wire_slave.cpp
 create mode 100644 STM32F1/libraries/WireSlave/src/Wire_slave.h
 create mode 100644 STM32F1/libraries/WireSlave/src/Wire_slave.h.gch
 create mode 100644 STM32F1/libraries/WireSlave/src/i2c_slave.c
 create mode 100644 STM32F1/libraries/WireSlave/src/i2c_slave.h.gch
 create mode 100644 STM32F1/libraries/WireSlave/src/libmaple/i2c_common_slave.h
 create mode 100644 STM32F1/libraries/WireSlave/src/libmaple/i2c_slave.h
 create mode 100644 STM32F1/libraries/WireSlave/src/libmaple/i2c_slave.h.gch
 create mode 100644 STM32F1/libraries/WireSlave/src/utility/WireBase_slave.cpp
 create mode 100644 STM32F1/libraries/WireSlave/src/utility/WireBase_slave.h
 create mode 100644 STM32F1/libraries/WireSlave/src/utility/WireBase_slave.h.gch

diff --git a/STM32F1/libraries/Wire/Wire_slave.h b/STM32F1/libraries/Wire/Wire_slave.h
new file mode 100644
index 000000000..21b4102bd
--- /dev/null
+++ b/STM32F1/libraries/Wire/Wire_slave.h
@@ -0,0 +1 @@
+#error "Something is trying to include Wire.h when Wire_Slave.h is already included, they are mutually exclusive"
diff --git a/STM32F1/libraries/Wire/library.properties b/STM32F1/libraries/Wire/library.properties
new file mode 100644
index 000000000..1129fa3fb
--- /dev/null
+++ b/STM32F1/libraries/Wire/library.properties
@@ -0,0 +1,10 @@
+name=Wire
+version=1.0
+author=Arduino
+maintainer=Arduino <info@arduino.cc>
+sentence=Allows the communication between devices or sensors connected via Two Wire Interface Bus.
+paragraph=
+category=Communication
+url=http://www.arduino.cc/en/Reference/Wire
+architectures=STM32F1
+include=Wire.h
diff --git a/STM32F1/libraries/WireSlave/examples/SFRRanger_reader/SFRRanger_reader.ino b/STM32F1/libraries/WireSlave/examples/SFRRanger_reader/SFRRanger_reader.ino
new file mode 100644
index 000000000..5537eca56
--- /dev/null
+++ b/STM32F1/libraries/WireSlave/examples/SFRRanger_reader/SFRRanger_reader.ino
@@ -0,0 +1,87 @@
+// I2C SRF10 or SRF08 Devantech Ultrasonic Ranger Finder
+// by Nicholas Zambetti <http://www.zambetti.com>
+// and James Tichenor <http://www.jamestichenor.net>
+
+// Demonstrates use of the Wire library reading data from the
+// Devantech Utrasonic Rangers SFR08 and SFR10
+
+// Created 29 April 2006
+
+// This example code is in the public domain.
+
+
+#include <Wire_slave.h>
+
+void setup()
+{
+  Wire.begin();                // join i2c bus (address optional for master)
+  Serial.begin(9600);          // start serial communication at 9600bps
+}
+
+int reading = 0;
+
+void loop()
+{
+  // step 1: instruct sensor to read echoes
+  Wire.beginTransmission(112); // transmit to device #112 (0x70)
+                               // the address specified in the datasheet is 224 (0xE0)
+                               // but i2c adressing uses the high 7 bits so it's 112
+  Wire.write(byte(0x00));      // sets register pointer to the command register (0x00)
+  Wire.write(byte(0x50));      // command sensor to measure in "inches" (0x50)
+                               // use 0x51 for centimeters
+                               // use 0x52 for ping microseconds
+  Wire.endTransmission();      // stop transmitting
+
+  // step 2: wait for readings to happen
+  delay(70);                   // datasheet suggests at least 65 milliseconds
+
+  // step 3: instruct sensor to return a particular echo reading
+  Wire.beginTransmission(112); // transmit to device #112
+  Wire.write(byte(0x02));      // sets register pointer to echo #1 register (0x02)
+  Wire.endTransmission();      // stop transmitting
+
+  // step 4: request reading from sensor
+  Wire.requestFrom(112, 2);    // request 2 bytes from slave device #112
+
+  // step 5: receive reading from sensor
+  if(2 <= Wire.available())    // if two bytes were received
+  {
+    reading = Wire.read();  // receive high byte (overwrites previous reading)
+    reading = reading << 8;    // shift high byte to be high 8 bits
+    reading |= Wire.read(); // receive low byte as lower 8 bits
+    Serial.println(reading);   // print the reading
+  }
+
+  delay(250);                  // wait a bit since people have to read the output :)
+}
+
+
+/*
+
+// The following code changes the address of a Devantech Ultrasonic Range Finder (SRF10 or SRF08)
+// usage: changeAddress(0x70, 0xE6);
+
+void changeAddress(byte oldAddress, byte newAddress)
+{
+  Wire.beginTransmission(oldAddress);
+  Wire.write(byte(0x00));
+  Wire.write(byte(0xA0));
+  Wire.endTransmission();
+
+  Wire.beginTransmission(oldAddress);
+  Wire.write(byte(0x00));
+  Wire.write(byte(0xAA));
+  Wire.endTransmission();
+
+  Wire.beginTransmission(oldAddress);
+  Wire.write(byte(0x00));
+  Wire.write(byte(0xA5));
+  Wire.endTransmission();
+
+  Wire.beginTransmission(oldAddress);
+  Wire.write(byte(0x00));
+  Wire.write(newAddress);
+  Wire.endTransmission();
+}
+
+*/
diff --git a/STM32F1/libraries/WireSlave/examples/digital_potentiometer/digital_potentiometer.ino b/STM32F1/libraries/WireSlave/examples/digital_potentiometer/digital_potentiometer.ino
new file mode 100644
index 000000000..8830ada12
--- /dev/null
+++ b/STM32F1/libraries/WireSlave/examples/digital_potentiometer/digital_potentiometer.ino
@@ -0,0 +1,38 @@
+// I2C Digital Potentiometer
+// by Nicholas Zambetti <http://www.zambetti.com>
+// and Shawn Bonkowski <http://people.interaction-ivrea.it/s.bonkowski/>
+
+// Demonstrates use of the Wire library
+// Controls AD5171 digital potentiometer via I2C/TWI
+
+// Created 31 March 2006
+
+// This example code is in the public domain.
+
+// This example code is in the public domain.
+
+
+#include <Wire_slave.h>
+
+void setup()
+{
+  Wire.begin(); // join i2c bus (address optional for master)
+}
+
+byte val = 0;
+
+void loop()
+{
+  Wire.beginTransmission(44); // transmit to device #44 (0x2c)
+                              // device address is specified in datasheet
+  Wire.write(byte(0x00));            // sends instruction byte
+  Wire.write(val);             // sends potentiometer value byte
+  Wire.endTransmission();     // stop transmitting
+
+  val++;        // increment value
+  if(val == 64) // if reached 64th position (max)
+  {
+    val = 0;    // start over from lowest value
+  }
+  delay(500);
+}
diff --git a/STM32F1/libraries/WireSlave/examples/i2c_libmaple_slave/i2c_libmaple_slave.ino b/STM32F1/libraries/WireSlave/examples/i2c_libmaple_slave/i2c_libmaple_slave.ino
new file mode 100644
index 000000000..23456e40a
--- /dev/null
+++ b/STM32F1/libraries/WireSlave/examples/i2c_libmaple_slave/i2c_libmaple_slave.ino
@@ -0,0 +1,122 @@
+/*
+* i2c_slave example.cpp
+*
+*  You can use this sketch in combination with master_writer.pde
+*
+*  Created on: 4 Sep 2012
+*      Author: Barry Carter <barry.carter@gmail.com>
+*/
+#include <Arduino.h>
+#include <libmaple/i2c.h>
+
+#define USE_BUFFERED_EXAMPLE 1
+
+i2c_msg msg;
+uint8 buffer[255];
+char* const bufferAsChar = (char*)buffer; // ready type casted alias
+
+volatile bool newMessage = false;
+
+void funcrx(i2c_msg *msg __attribute__((unused))){
+  // Received length will be in msg->length
+  newMessage = true;
+}
+
+#if USE_BUFFERED_EXAMPLE == 1
+/* We ARE using a buffer to transmit the data out.
+* Make sure you fill the buffer with the data AND you set the length correctly
+*/
+void functx(i2c_msg *msg){
+  // Cheeky. We are using the received byte of the data which is currently in
+  // byte 0 to echo it back to the master device
+  //msg->data[0] = 0x01;    // We are re-using the rx buffer here to echo the request back
+  msg->data[1] = 0x02;
+  msg->data[2] = 0x03;
+  msg->data[3] = 0x04;
+  msg->data[4] = 0x05;
+  msg->length = 5;
+}
+
+#else
+
+/* We are NOT using the buffered data transmission
+* We will get this callback for each outgoing packet. Make sure to call i2c_write
+* Strickly speaking, we should be sending a NACk on the last byte we want to send
+* but for this test example I am going to assume the master will NACK it when it
+* wants to stop.
+*/
+void functx(i2c_msg *msg){
+  i2c_write(I2C1, msg->data[0]);
+}
+
+#endif
+
+// #define Serial Serial1
+
+void setup() {
+  Serial.begin(115200);
+  while(!Serial)
+    ;
+  Serial.println("I2C Slave example");
+
+  // attach the buffer
+  msg.data = buffer;
+
+  /* Init slave mode. Enables master too
+  * We are going to configure the slave device to
+  *  - enable fast I2C (400khz)
+  *  - dual addresses (can have 2 addresses per module)
+  * general call (accepts data writes to 0x00 on a broadcast basis)
+  *
+  * If the buffered example is enabled, then we also enable the
+  * buffer for rx and tx.
+  * Note you can independently enable/disable RX and TX buffers to
+  * allow a buffered read and direct writes. Useful if you don't know how
+  * much the master will read.
+  */
+  #if USE_BUFFERED_EXAMPLE == 1
+  i2c_slave_enable(I2C1, I2C_FAST_MODE | I2C_SLAVE_DUAL_ADDRESS | I2C_SLAVE_GENERAL_CALL | I2C_SLAVE_USE_RX_BUFFER | I2C_SLAVE_USE_TX_BUFFER);
+  #else
+  i2c_slave_enable(I2C1, I2C_FAST_MODE | I2C_SLAVE_DUAL_ADDRESS | I2C_SLAVE_GENERAL_CALL);
+  #endif
+
+  // attach  receive handler
+  i2c_slave_attach_recv_handler(I2C1, &msg, funcrx);
+  // attach transmit handler
+  i2c_slave_attach_transmit_handler(I2C1, &msg, functx);
+
+  // set addresss to 4
+  i2c_slave_set_own_address(I2C1, 4);
+}
+
+void loop() {
+  static uint32_t lastMessage = millis();
+
+  // This is potentially dangerous.
+  // We're reading from the live buffer, the content can change
+  // in the middle of Serial.println
+
+  if (newMessage && strlen(bufferAsChar)==6) {
+    for (int i=0; i<5; i++) {
+      // Print as char
+      Serial.print(bufferAsChar[i]);
+    }
+    // Print as byte
+    Serial.println(buffer[5]);
+    lastMessage = millis();
+    newMessage = false;
+  } else {
+    if(newMessage && strlen(bufferAsChar)!=6) {
+      // this also happends on the line "x is 0"
+      Serial.print("Bad data received:");
+      Serial.println(bufferAsChar);
+      Serial.print("strlen:");
+      Serial.println(strlen(bufferAsChar));
+      newMessage = false;
+    } else
+    if(millis() - lastMessage > 3000){
+      Serial.println("Nothing received in 3 seconds.");
+      lastMessage = millis();
+    }
+  }
+}
diff --git a/STM32F1/libraries/WireSlave/examples/master_reader/master_reader.ino b/STM32F1/libraries/WireSlave/examples/master_reader/master_reader.ino
new file mode 100644
index 000000000..4b45d1289
--- /dev/null
+++ b/STM32F1/libraries/WireSlave/examples/master_reader/master_reader.ino
@@ -0,0 +1,32 @@
+// Wire Master Reader
+// by Nicholas Zambetti <http://www.zambetti.com>
+
+// Demonstrates use of the Wire library
+// Reads data from an I2C/TWI slave device
+// Refer to the "Wire Slave Sender" example for use with this
+
+// Created 29 March 2006
+
+// This example code is in the public domain.
+
+
+#include <Wire_slave.h>
+
+void setup()
+{
+  Wire.begin();        // join i2c bus (address optional for master)
+  Serial.begin(9600);  // start serial for output
+}
+
+void loop()
+{
+  Wire.requestFrom(2, 6);    // request 6 bytes from slave device #2
+
+  while(Wire.available())    // slave may send less than requested
+  {
+    char c = Wire.read(); // receive a byte as character
+    Serial.print(c);         // print the character
+  }
+
+  delay(500);
+}
diff --git a/STM32F1/libraries/WireSlave/examples/master_writer/master_writer.ino b/STM32F1/libraries/WireSlave/examples/master_writer/master_writer.ino
new file mode 100644
index 000000000..f997473a7
--- /dev/null
+++ b/STM32F1/libraries/WireSlave/examples/master_writer/master_writer.ino
@@ -0,0 +1,31 @@
+// Wire Master Writer
+// by Nicholas Zambetti <http://www.zambetti.com>
+
+// Demonstrates use of the Wire library
+// Writes data to an I2C/TWI slave device
+// Refer to the "Wire Slave Receiver" example for use with this
+
+// Created 29 March 2006
+
+// This example code is in the public domain.
+
+
+#include <Wire_slave.h>
+
+void setup()
+{
+  Wire.begin(); // join i2c bus (address optional for master)
+}
+
+byte x = 0;
+
+void loop()
+{
+  Wire.beginTransmission(4); // transmit to device #4
+  Wire.write("x is ");        // sends five bytes
+  Wire.write(x);              // sends one byte
+  Wire.endTransmission();    // stop transmitting
+
+  x++;
+  delay(500);
+}
diff --git a/STM32F1/libraries/WireSlave/examples/slave_receiver/slave_receiver.ino b/STM32F1/libraries/WireSlave/examples/slave_receiver/slave_receiver.ino
new file mode 100644
index 000000000..b430c2539
--- /dev/null
+++ b/STM32F1/libraries/WireSlave/examples/slave_receiver/slave_receiver.ino
@@ -0,0 +1,38 @@
+// Wire Slave Receiver
+// by Nicholas Zambetti <http://www.zambetti.com>
+
+// Demonstrates use of the Wire library
+// Receives data as an I2C/TWI slave device
+// Refer to the "Wire Master Writer" example for use with this
+
+// Created 29 March 2006
+
+// This example code is in the public domain.
+
+
+#include <Wire_slave.h>
+
+void setup()
+{
+  Wire.begin(4);                // join i2c bus with address #4
+  Wire.onReceive(receiveEvent); // register event
+  Serial.begin(9600);           // start serial for output
+}
+
+void loop()
+{
+  delay(100);
+}
+
+// function that executes whenever data is received from master
+// this function is registered as an event, see setup()
+void receiveEvent(int howMany)
+{
+  while(1 < Wire.available()) // loop through all but the last
+  {
+    char c = Wire.read(); // receive byte as a character
+    Serial.print(c);         // print the character
+  }
+  int x = Wire.read();    // receive byte as an integer
+  Serial.println(x);         // print the integer
+}
diff --git a/STM32F1/libraries/WireSlave/examples/slave_sender/slave_sender.ino b/STM32F1/libraries/WireSlave/examples/slave_sender/slave_sender.ino
new file mode 100644
index 000000000..fcdac14b3
--- /dev/null
+++ b/STM32F1/libraries/WireSlave/examples/slave_sender/slave_sender.ino
@@ -0,0 +1,32 @@
+// Wire Slave Sender
+// by Nicholas Zambetti <http://www.zambetti.com>
+
+// Demonstrates use of the Wire library
+// Sends data as an I2C/TWI slave device
+// Refer to the "Wire Master Reader" example for use with this
+
+// Created 29 March 2006
+
+// This example code is in the public domain.
+
+
+#include <Wire_slave.h>
+
+void setup()
+{
+  Wire.begin(2);                // join i2c bus with address #2
+  Wire.onRequest(requestEvent); // register event
+}
+
+void loop()
+{
+  delay(100);
+}
+
+// function that executes whenever data is requested by master
+// this function is registered as an event, see setup()
+void requestEvent()
+{
+  Wire.write("hello "); // respond with message of 6 bytes
+                       // as expected by master
+}
diff --git a/STM32F1/libraries/WireSlave/library.properties b/STM32F1/libraries/WireSlave/library.properties
new file mode 100644
index 000000000..2a1c387b2
--- /dev/null
+++ b/STM32F1/libraries/WireSlave/library.properties
@@ -0,0 +1,11 @@
+name=Wire_Slave
+version=1.0
+author=
+email=
+sentence=Wire with slave support
+paragraph=Experimental Wire with slave support
+url=
+architectures=STM32F1
+maintainer=
+category=Communication
+include=src/Wire_Slave.h
diff --git a/STM32F1/libraries/WireSlave/src/Wire.h b/STM32F1/libraries/WireSlave/src/Wire.h
new file mode 100644
index 000000000..ede963b37
--- /dev/null
+++ b/STM32F1/libraries/WireSlave/src/Wire.h
@@ -0,0 +1 @@
+#error "Something is trying to include Wire_slave.h when Wire.h is already included, they are mutually exclusive"
diff --git a/STM32F1/libraries/WireSlave/src/Wire.h.gch b/STM32F1/libraries/WireSlave/src/Wire.h.gch
new file mode 100644
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HcmV?d00001

diff --git a/STM32F1/libraries/WireSlave/src/Wire_slave.cpp b/STM32F1/libraries/WireSlave/src/Wire_slave.cpp
new file mode 100644
index 000000000..93cc55f09
--- /dev/null
+++ b/STM32F1/libraries/WireSlave/src/Wire_slave.cpp
@@ -0,0 +1,106 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 LeafLabs LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file TwoWire.cpp
+ * @author Trystan Jones <crenn6977@gmail.com>
+ * @brief Wire library, uses the hardware I2C available in the Maple to
+ *        interact with I2C slave devices.
+ */
+
+/*
+ * Library created by crenn to use the new WireBase system and allow Arduino
+ * users easy interaction with the I2C Hardware in a familiar method.
+ */
+
+#include "Wire_slave.h"
+
+uint8 TwoWire::process(uint8 stop) {
+    int8 res = i2c_master_xfer(sel_hard, &itc_msg, 1, 0);
+    if (res == I2C_ERROR_PROTOCOL) {
+        if (sel_hard->error_flags & I2C_SR1_AF) { /* NACK */
+            res = (sel_hard->error_flags & I2C_SR1_ADDR ? ENACKADDR :
+                                                          ENACKTRNS);
+        } else if (sel_hard->error_flags & I2C_SR1_OVR) { /* Over/Underrun */
+            res = EDATA;
+        } else { /* Bus or Arbitration error */
+            res = EOTHER;
+        }
+        i2c_disable(sel_hard);
+        i2c_master_enable(sel_hard, (I2C_BUS_RESET | dev_flags));
+    }
+    return res;
+}
+
+uint8 TwoWire::process(){
+	return process(true);
+}
+
+// TODO: Add in Error Handling if devsel is out of range for other Maples
+TwoWire::TwoWire(uint8 dev_sel, uint8 flags) {
+    if (dev_sel == 1) {
+        sel_hard = I2C1;
+    } else if (dev_sel == 2) {
+        sel_hard = I2C2;
+    } else {
+        ASSERT(1);
+    }
+    dev_flags = flags;
+}
+
+TwoWire::~TwoWire() {
+    i2c_disable(sel_hard);
+    sel_hard = 0;
+}
+
+void TwoWire::begin(uint8 self_addr) {
+    i2c_master_enable(sel_hard, dev_flags);
+}
+
+void TwoWire::end() {
+    i2c_disable(sel_hard);
+    sel_hard = 0;
+}
+
+void TwoWire::setClock(uint32_t frequencyHz)
+{
+	switch(frequencyHz)
+	{
+		case 400000:
+			dev_flags |= I2C_FAST_MODE;// set FAST_MODE bit
+			break;
+		case 100000:
+		default:
+			dev_flags &= ~I2C_FAST_MODE;// clear FAST_MODE bit
+			break;
+	}
+	if (sel_hard->regs->CR1 & I2C_CR1_PE){
+	    i2c_disable(sel_hard);
+	    i2c_master_enable(sel_hard, dev_flags);
+	}
+}
+
+TwoWire Wire(1);
diff --git a/STM32F1/libraries/WireSlave/src/Wire_slave.h b/STM32F1/libraries/WireSlave/src/Wire_slave.h
new file mode 100644
index 000000000..dbe2a4ea5
--- /dev/null
+++ b/STM32F1/libraries/WireSlave/src/Wire_slave.h
@@ -0,0 +1,78 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 LeafLabs LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file Wire.h
+ * @author Trystan Jones <crenn6977@gmail.com>
+ * @brief Wire library, uses the hardware I2C available in the Maple to
+ *        interact with I2C slave devices.
+ */
+
+/*
+ * Library created by crenn to use the new WireBase system and allow Arduino
+ * users easy interaction with the I2C Hardware in a familiar method.
+ */
+
+#ifndef _TWOWIRE_H_
+#define _TWOWIRE_H_
+
+#include "utility/WireBase_slave.h"
+#include "wirish.h"
+#include <libmaple/i2c_slave.h>
+
+class TwoWire : public WireBase {
+private:
+    i2c_dev* sel_hard;
+    uint8    dev_flags;
+protected:
+    /*
+     * Processes the incoming I2C message defined by WireBase to the
+     * hardware. If an error occured, restart the I2C device.
+     */
+    uint8 process(uint8);
+    uint8 process();
+public:
+    /*
+     * Check if devsel is within range and enable selected I2C interface with
+     * passed flags
+     */
+    TwoWire(uint8, uint8 = 0);
+
+	/*
+	 * Shuts down (disables) the hardware I2C
+	 */
+	void end();
+
+	void setClock(uint32_t frequencyHz);
+    /*
+     * Disables the I2C device and remove the device address.
+     */
+    ~TwoWire();
+
+    void begin(uint8 = 0x00);
+};
+extern TwoWire Wire;
+#endif // _TWOWIRE_H_
diff --git a/STM32F1/libraries/WireSlave/src/Wire_slave.h.gch b/STM32F1/libraries/WireSlave/src/Wire_slave.h.gch
new file mode 100644
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diff --git a/STM32F1/libraries/WireSlave/src/i2c_slave.c b/STM32F1/libraries/WireSlave/src/i2c_slave.c
new file mode 100644
index 000000000..770cd3a63
--- /dev/null
+++ b/STM32F1/libraries/WireSlave/src/i2c_slave.c
@@ -0,0 +1,789 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Perry Hung.
+ * Copyright (c) 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/i2c.c
+ * @author Perry Hung <perry@leaflabs.com>
+ * @author Barry Carter <barry.carter@gmail.com>
+ * @brief Inter-Integrated Circuit (I2C) support.
+ *
+ * Master and Slave supported
+ * I2C slave support added 2012 by Barry Carter. barry.carter@gmail.com, headfuzz.co.uk
+ */
+
+#include "libmaple/i2c_common_slave.h"
+
+#include "i2c_private.h"
+
+
+#include "libmaple/i2c_slave.h"
+#include <libmaple/libmaple.h>
+#include <libmaple/rcc.h>
+#include <libmaple/gpio.h>
+#include <libmaple/nvic.h>
+#include <libmaple/systick.h>
+
+#include <string.h>
+
+static inline int32 wait_for_state_change(i2c_dev *dev,
+                                          i2c_state state,
+                                          uint32 timeout);
+static void set_ccr_trise(i2c_dev *dev, uint32 flags);
+
+/**
+ * @brief Fill data register with slave address
+ * @param dev I2C device
+ * @param addr Slave address
+ * @param rw Read/write bit
+ */
+static inline void i2c_send_slave_addr(i2c_dev *dev, uint32 addr, uint32 rw) {
+    dev->regs->DR = (addr << 1) | rw;
+}
+
+/*
+ * Simple debugging trail. Define I2C_DEBUG to turn on.
+ */
+#ifdef I2C_DEBUG
+
+#define NR_CRUMBS       128
+static struct crumb crumbs[NR_CRUMBS];
+static uint32 cur_crumb = 0;
+
+static inline void i2c_drop_crumb(uint32 event, uint32 arg0, uint32 arg1) {
+    if (cur_crumb < NR_CRUMBS) {
+        struct crumb *crumb = &crumbs[cur_crumb++];
+        crumb->event = event;
+        crumb->arg0 = arg0;
+        crumb->arg1 = arg1;
+    }
+}
+#define I2C_CRUMB(event, arg0, arg1) i2c_drop_crumb(event, arg0, arg1)
+
+#else
+#define I2C_CRUMB(event, arg0, arg1)
+#endif
+
+struct crumb {
+    uint32 event;
+    uint32 arg0;
+    uint32 arg1;
+};
+
+enum {
+    IRQ_ENTRY           = 1,
+    TXE_ONLY            = 2,
+    TXE_BTF             = 3,
+    STOP_SENT           = 4,
+    TEST                = 5,
+    RX_ADDR_START       = 6,
+    RX_ADDR_STOP        = 7,
+    RXNE_ONLY           = 8,
+    RXNE_SENDING        = 9,
+    RXNE_START_SENT     = 10,
+    RXNE_STOP_SENT      = 11,
+    RXNE_DONE           = 12,
+    ERROR_ENTRY         = 13,
+};
+
+/**
+ * @brief Reset an I2C bus.
+ *
+ * Reset is accomplished by clocking out pulses until any hung slaves
+ * release SDA and SCL, then generating a START condition, then a STOP
+ * condition.
+ *
+ * @param dev I2C device
+ */
+void i2c_bus_reset(const i2c_dev *dev) {
+    /* Release both lines */
+    i2c_master_release_bus(dev);
+
+    /*
+     * Make sure the bus is free by clocking it until any slaves release the
+     * bus.
+     */
+    while (!gpio_read_bit(sda_port(dev), dev->sda_pin)) {
+        /* Wait for any clock stretching to finish */
+        while (!gpio_read_bit(scl_port(dev), dev->scl_pin))
+            ;
+        delay_us(10);
+
+        /* Pull low */
+        gpio_write_bit(scl_port(dev), dev->scl_pin, 0);
+        delay_us(10);
+
+        /* Release high again */
+        gpio_write_bit(scl_port(dev), dev->scl_pin, 1);
+        delay_us(10);
+    }
+
+    /* Generate start then stop condition */
+    gpio_write_bit(sda_port(dev), dev->sda_pin, 0);
+    delay_us(10);
+    gpio_write_bit(scl_port(dev), dev->scl_pin, 0);
+    delay_us(10);
+    gpio_write_bit(scl_port(dev), dev->scl_pin, 1);
+    delay_us(10);
+    gpio_write_bit(sda_port(dev), dev->sda_pin, 1);
+}
+
+/**
+ * @brief Initialize an I2C device and reset its registers to their
+ *        default values.
+ * @param dev Device to initialize.
+ */
+void i2c_init(i2c_dev *dev) {
+    rcc_reset_dev(dev->clk_id);
+    rcc_clk_enable(dev->clk_id);
+    _i2c_irq_priority_fixup(dev);
+}
+
+/* Hack for deprecated bit of STM32F1 functionality */
+#ifndef _I2C_HAVE_DEPRECATED_I2C_REMAP
+#define _i2c_handle_remap(dev, flags) ((void)0)
+#endif
+
+/**
+ * @brief Initialize an I2C device as bus master
+ * @param dev Device to enable
+ * @param flags Bitwise or of the following I2C options:
+ *              I2C_FAST_MODE: 400 khz operation,
+ *              I2C_DUTY_16_9: 16/9 Tlow/Thigh duty cycle (only applicable for
+ *                             fast mode),
+ *              I2C_BUS_RESET: Reset the bus and clock out any hung slaves on
+ *                             initialization,
+ *              I2C_10BIT_ADDRESSING: Enable 10-bit addressing,
+ *              I2C_REMAP: (deprecated, STM32F1 only) Remap I2C1 to SCL/PB8
+ *                         SDA/PB9.
+ */
+void i2c_master_enable(i2c_dev *dev, uint32 flags) {
+    /* PE must be disabled to configure the device */
+    ASSERT(!(dev->regs->CR1 & I2C_CR1_PE));
+
+    /* Ugh */
+    _i2c_handle_remap(dev, flags);
+
+    /* Reset the bus. Clock out any hung slaves. */
+    if (flags & I2C_BUS_RESET) {
+        i2c_bus_reset(dev);
+    }
+
+    /* Turn on clock and set GPIO modes */
+    i2c_init(dev);
+    i2c_config_gpios(dev);
+
+    /* Configure clock and rise time */
+    set_ccr_trise(dev, flags);
+
+    /* Enable event and buffer interrupts */
+    nvic_irq_enable(dev->ev_nvic_line);
+    nvic_irq_enable(dev->er_nvic_line);
+    i2c_enable_irq(dev, I2C_IRQ_EVENT | I2C_IRQ_BUFFER | I2C_IRQ_ERROR);
+
+    /* Configure the slave unit */
+    if (flags & I2C_SLAVE_DUAL_ADDRESS) {
+        i2c_slave_dual_address_enable(dev);
+    }
+
+    if (flags & I2C_SLAVE_GENERAL_CALL) {
+        i2c_slave_general_call_enable(dev);
+    }
+
+    /* store all of the flags */
+    dev->config_flags = flags;
+
+    /* Make it go! */
+    i2c_peripheral_enable(dev);
+    i2c_enable_ack(dev);
+
+    dev->state = I2C_STATE_IDLE;
+}
+
+/**
+ * @brief Initialize an I2C device as slave (and master)
+ * @param dev Device to enable
+ * @param flags Bitwise or of the following I2C options:
+ *              I2C_FAST_MODE: 400 khz operation,
+ *              I2C_DUTY_16_9: 16/9 Tlow/Thigh duty cycle (only applicable for
+ *                             fast mode),
+ *              I2C_BUS_RESET: Reset the bus and clock out any hung slaves on
+ *                             initialization,
+ *              I2C_10BIT_ADDRESSING: Enable 10-bit addressing,
+ *              I2C_REMAP: (deprecated, STM32F1 only) Remap I2C1 to SCL/PB8
+ *                         SDA/PB9.
+ *              I2C_SLAVE_DUAL_ADDRESS: Slave can respond on 2 i2C addresses
+ *              I2C_SLAVE_GENERAL_CALL: SLA+W broadcast to all general call
+ *                                      listeners on bus. Addr 0x00
+ *              I2C_SLAVE_USE_RX_BUFFER: Use a buffer to receive the incoming
+ *                                       data. Callback at end of recv
+ *              I2C_SLAVE_USE_TX_BUFFER: Use a buffer to transmit data.
+ *                                       Callback will be called before tx
+ */
+void i2c_slave_enable(i2c_dev *dev, uint32 flags) {
+    i2c_disable(dev);
+    i2c_master_enable(dev, dev->config_flags | flags);
+}
+
+/**
+ * @brief Process an i2c transaction.
+ *
+ * Transactions are composed of one or more i2c_msg's, and may be read
+ * or write tranfers.  Multiple i2c_msg's will generate a repeated
+ * start in between messages.
+ *
+ * @param dev I2C device
+ * @param msgs Messages to send/receive
+ * @param num Number of messages to send/receive
+ * @param timeout Bus idle timeout in milliseconds before aborting the
+ *                transfer.  0 denotes no timeout.
+ * @return 0 on success,
+ *         I2C_ERROR_PROTOCOL if there was a protocol error,
+ *         I2C_ERROR_TIMEOUT if the transfer timed out.
+ */
+int32 i2c_master_xfer(i2c_dev *dev,
+                      i2c_msg *msgs,
+                      uint16 num,
+                      uint32 timeout) {
+    int32 rc;
+
+    ASSERT(dev->state == I2C_STATE_IDLE);
+
+    dev->msg = msgs;
+    dev->msgs_left = num;
+    dev->timestamp = systick_uptime();
+    dev->state = I2C_STATE_BUSY;
+
+    i2c_enable_irq(dev, I2C_IRQ_EVENT);
+    i2c_start_condition(dev);
+
+    rc = wait_for_state_change(dev, I2C_STATE_XFER_DONE, timeout);
+    if (rc < 0) {
+        goto out;
+    }
+
+    dev->state = I2C_STATE_IDLE;
+out:
+    return rc;
+}
+
+/**
+ * @brief Wait for an I2C event, or time out in case of error.
+ * @param dev I2C device
+ * @param state I2C_state state to wait for
+ * @param timeout Timeout, in milliseconds
+ * @return 0 if target state is reached, a negative value on error.
+ */
+static inline int32 wait_for_state_change(i2c_dev *dev,
+                                          i2c_state state,
+                                          uint32 timeout) {
+    i2c_state tmp;
+
+    while (1) {
+        tmp = dev->state;
+
+        if (tmp == I2C_STATE_ERROR) {
+            return I2C_STATE_ERROR;
+        }
+
+        if (tmp == state) {
+            return 0;
+        }
+
+        if (timeout) {
+            if (systick_uptime() > (dev->timestamp + timeout)) {
+                /* TODO: overflow? */
+                /* TODO: racy? */
+                return I2C_ERROR_TIMEOUT;
+            }
+        }
+    }
+}
+
+/*
+ * Private API
+ */
+
+/*
+ * IRQ handler for I2C master. Handles transmission/reception.
+ */
+void _i2c_irq_handler(i2c_dev *dev) {
+    /* WTFs:
+     * - Where is I2C_MSG_10BIT_ADDR handled?
+     */
+    i2c_msg *msg = dev->msg;
+
+    uint8 read = msg->flags & I2C_MSG_READ;
+
+    uint32 sr1 = dev->regs->SR1;
+    uint32 sr2 = dev->regs->SR2;
+    I2C_CRUMB(IRQ_ENTRY, sr1, sr2);
+
+    /*
+     * Reset timeout counter
+     */
+    dev->timestamp = systick_uptime();
+
+    /*
+     * Add Slave support
+     */
+
+    /* Check to see if MSL master slave bit is set */
+    if ((sr2 & I2C_SR2_MSL) != I2C_SR2_MSL) { /* 0 = slave mode 1 = master */
+
+        /* Check for address match */
+        if (sr1 & I2C_SR1_ADDR) {
+            /* Find out which address was matched */
+            /* Check the general call address first */
+            if (sr2 & I2C_SR2_GENCALL) {
+                dev->i2c_slave_msg->addr = 0;
+            }
+            /* We matched the secondary address */
+            else if (sr2 & I2C_SR2_DUALF) {
+                dev->i2c_slave_msg->addr = dev->regs->OAR2 & 0xFE;
+            }
+            /* We matched the primary address */
+            else if ((sr2 & I2C_SR2_DUALF) != I2C_SR2_DUALF) {
+                dev->i2c_slave_msg->addr = dev->regs->OAR1 & 0xFE;
+            }
+            /* Shouldn't get here */
+            else {
+                dev->i2c_slave_msg->addr = -1; /* uh oh */
+            }
+
+            /* if we have buffered io */
+            if ((dev->config_flags & I2C_SLAVE_USE_RX_BUFFER) ||
+                (dev->config_flags & I2C_SLAVE_USE_TX_BUFFER)) {
+
+                /* if receiving then this would be a repeated start
+                 *
+                 *if we have some bytes already
+                 */
+                if ((dev->state == I2C_STATE_SL_RX) &&
+                    (dev->i2c_slave_msg->xferred > 0)  &&
+                    (dev->config_flags & I2C_SLAVE_USE_RX_BUFFER)) {
+                    /* Call the callback with the contents of the data */
+                    if (dev->i2c_slave_recv_callback != NULL) {
+                        (*(dev->i2c_slave_recv_callback))(dev->i2c_slave_msg);
+                    }
+                }
+
+                /* Reset the message back to defaults.
+                 * We are starting a new message
+                 */
+                dev->i2c_slave_msg->flags = 0;
+                dev->i2c_slave_msg->length = 0;
+                dev->i2c_slave_msg->xferred = 0;
+                dev->msgs_left = 0;
+                dev->timestamp = systick_uptime();
+
+                /* We have been addressed with SLA+R so
+                 * the master wants us to transmit
+                 */
+                if ((sr1 & I2C_SR1_TXE) &&
+                    (dev->config_flags & I2C_SLAVE_USE_TX_BUFFER)) {
+                    /* Call the transmit callback so it can populate the msg
+                     * data with the bytes to go
+                     */
+                    if (dev->i2c_slave_transmit_callback != NULL) {
+                        (*(dev->i2c_slave_transmit_callback))(dev->i2c_slave_msg);
+                    }
+                }
+                dev->state = I2C_STATE_BUSY;
+            }
+
+            sr1 = sr2 = 0;
+        }
+
+         /* EV3: Master requesting data from slave. Transmit a byte*/
+        if (sr1 & I2C_SR1_TXE) {
+            if (dev->config_flags & I2C_SLAVE_USE_TX_BUFFER) {
+                if (dev->i2c_slave_msg->xferred >= dev->i2c_slave_msg->length) {
+                    /* End of the transmit buffer? If so we NACK */
+                    i2c_disable_ack(dev);
+                    /* We have to either issue a STOP or write something here.
+                     * STOP here seems to screw up some masters,
+                     * For now padding with 0
+                     */
+                    i2c_write(dev, 0);
+                    /*i2c_stop_condition(dev); // This is causing bus lockups way more than it should !? Seems some I2C master devices freak out here*/
+                }
+                else
+                {
+                    /* NACk the last byte */
+                    if (dev->i2c_slave_msg->xferred == dev->i2c_slave_msg->length-1) {
+                        i2c_disable_ack(dev);
+                    }
+                    else {
+                        i2c_enable_ack(dev);
+                    }
+                    i2c_write(dev, dev->i2c_slave_msg->data[dev->i2c_slave_msg->xferred++]);
+                }
+            }
+            else
+            {
+                /* Call the callback to get the data we need.
+                 * The callback is expected to write using i2c_write(...)
+                 * If the slave is going to terminate the transfer, this function should
+                 * also do a NACK on the last byte!
+                 */
+                if (dev->i2c_slave_transmit_callback != NULL) (*(dev->i2c_slave_transmit_callback))(dev->i2c_slave_msg);
+            }
+
+            dev->state = I2C_STATE_BUSY;
+            sr1 = sr2 = 0;
+        }
+
+        /* EV2: Slave received data from a master. Get from DR */
+        if (sr1 & I2C_SR1_RXNE) {
+            if (dev->config_flags & I2C_SLAVE_USE_RX_BUFFER) {
+                /* Fill the buffer with the contents of the data register */
+                /* These is potential for buffer overflow here, so we should
+                 * really store the size of the array. This is expensive in
+                 * the ISR so left out for now. We must trust the implementor!
+                 */
+                dev->i2c_slave_msg->data[dev->i2c_slave_msg->xferred++] = dev->regs->DR;
+                dev->i2c_slave_msg->length++;
+            }
+            else  {
+                /* Call the callback with the contents of the data */
+                dev->i2c_slave_msg->data[0] = dev->regs->DR;
+                if (dev->i2c_slave_recv_callback != NULL) (*(dev->i2c_slave_recv_callback))(dev->i2c_slave_msg);
+            }
+            dev->state = I2C_STATE_SL_RX;
+            sr1 = sr2 = 0;
+        }
+
+        /* EV4: Slave has detected a STOP condition on the bus */
+        if (sr1 & I2C_SR1_STOPF) {
+            dev->regs->CR1 |= I2C_CR1_PE;
+
+            if ((dev->config_flags & I2C_SLAVE_USE_RX_BUFFER) ||
+                (dev->config_flags & I2C_SLAVE_USE_TX_BUFFER)) {
+
+                /* The callback with the data will happen on a NACK of the last data byte.
+                 * This is handled in the error IRQ (AF bit)
+                 */
+                /* Handle the case where the master misbehaves by sending no NACK */
+                if (dev->state != I2C_STATE_IDLE) {
+                    if (dev->state == I2C_STATE_SL_RX) {
+                        if (dev->i2c_slave_recv_callback != NULL) (*(dev->i2c_slave_recv_callback))(dev->i2c_slave_msg);
+                    }
+                    else {
+                        if (dev->i2c_slave_transmit_callback != NULL) (*(dev->i2c_slave_transmit_callback))(dev->i2c_slave_msg);
+                    }
+                }
+            }
+
+            sr1 = sr2 = 0;
+            dev->state = I2C_STATE_IDLE;
+        }
+
+        return;
+    }
+
+    /*
+     * EV5: Start condition sent
+     */
+    if (sr1 & I2C_SR1_SB) {
+        msg->xferred = 0;
+        i2c_enable_irq(dev, I2C_IRQ_BUFFER);
+
+        /*
+         * Master receiver
+         */
+        if (read) {
+            i2c_enable_ack(dev);
+        }
+
+        i2c_send_slave_addr(dev, msg->addr, read);
+        sr1 = sr2 = 0;
+    }
+
+    /*
+     * EV6: Slave address sent
+     */
+    if (sr1 & I2C_SR1_ADDR) {
+        /*
+         * Special case event EV6_1 for master receiver.
+         * Generate NACK and restart/stop condition after ADDR
+         * is cleared.
+         */
+        if (read) {
+            if (msg->length == 1) {
+                i2c_disable_ack(dev);
+                if (dev->msgs_left > 1) {
+                    i2c_start_condition(dev);
+                    I2C_CRUMB(RX_ADDR_START, 0, 0);
+                } else {
+                    i2c_stop_condition(dev);
+                    I2C_CRUMB(RX_ADDR_STOP, 0, 0);
+                }
+            }
+        } else {
+            /*
+             * Master transmitter: write first byte to fill shift
+             * register.  We should get another TXE interrupt
+             * immediately to fill DR again.
+             */
+            if (msg->length > 1) {
+                i2c_write(dev, msg->data[msg->xferred++]);
+            } else if (msg->length == 0) { /* We're just sending an address */
+                i2c_stop_condition(dev);
+              /*
+               * Turn off event interrupts to keep BTF from firing until
+               * the end of the stop condition. Why on earth they didn't
+               * have a start/stop condition request clear BTF is beyond
+               * me.
+               */
+              i2c_disable_irq(dev, I2C_IRQ_EVENT);
+              I2C_CRUMB(STOP_SENT, 0, 0);
+              dev->state = I2C_STATE_XFER_DONE;
+            } /* else we're just sending one byte */
+        }
+        sr1 = sr2 = 0;
+    }
+
+    /*
+     * EV8: Master transmitter
+     * Transmit buffer empty, but we haven't finished transmitting the last
+     * byte written.
+     */
+    if ((sr1 & I2C_SR1_TXE) && !(sr1 & I2C_SR1_BTF)) {
+        I2C_CRUMB(TXE_ONLY, 0, 0);
+        if (dev->msgs_left) {
+            i2c_write(dev, msg->data[msg->xferred++]);
+            if (msg->xferred == msg->length) {
+                /*
+                 * End of this message. Turn off TXE/RXNE and wait for
+                 * BTF to send repeated start or stop condition.
+                 */
+                i2c_disable_irq(dev, I2C_IRQ_BUFFER);
+                dev->msgs_left--;
+            }
+        } else {
+            /*
+             * This should be impossible...
+             */
+            ASSERT(0);
+        }
+        sr1 = sr2 = 0;
+    }
+
+    /*
+     * EV8_2: Master transmitter
+     * Last byte sent, program repeated start/stop
+     */
+    if ((sr1 & I2C_SR1_TXE) && (sr1 & I2C_SR1_BTF)) {
+        I2C_CRUMB(TXE_BTF, 0, 0);
+        if (dev->msgs_left) {
+            I2C_CRUMB(TEST, 0, 0);
+            /*
+             * Repeated start insanity: We can't disable ITEVTEN or else SB
+             * won't interrupt, but if we don't disable ITEVTEN, BTF will
+             * continually interrupt us. What the fuck ST?
+             */
+            i2c_start_condition(dev);
+            while (!(dev->regs->SR1 & I2C_SR1_SB))
+                ;
+            dev->msg++;
+        } else {
+            i2c_stop_condition(dev);
+
+            /*
+             * Turn off event interrupts to keep BTF from firing until
+             * the end of the stop condition. Why on earth they didn't
+             * have a start/stop condition request clear BTF is beyond
+             * me.
+             */
+            i2c_disable_irq(dev, I2C_IRQ_EVENT);
+            I2C_CRUMB(STOP_SENT, 0, 0);
+            dev->state = I2C_STATE_XFER_DONE;
+        }
+        sr1 = sr2 = 0;
+    }
+
+    /*
+     * EV7: Master Receiver
+     */
+    if (sr1 & I2C_SR1_RXNE) {
+        I2C_CRUMB(RXNE_ONLY, 0, 0);
+        msg->data[msg->xferred++] = dev->regs->DR;
+
+        /*
+         * EV7_1: Second to last byte in the reception? Set NACK and generate
+         * stop/restart condition in time for the last byte. We'll get one more
+         * RXNE interrupt before shutting things down.
+         */
+        if (msg->xferred == (msg->length - 1)) {
+            i2c_disable_ack(dev);
+            if (dev->msgs_left > 2) {
+                i2c_start_condition(dev);
+                I2C_CRUMB(RXNE_START_SENT, 0, 0);
+            } else {
+                i2c_stop_condition(dev);
+                I2C_CRUMB(RXNE_STOP_SENT, 0, 0);
+            }
+        } else if (msg->xferred == msg->length) {
+            dev->msgs_left--;
+            if (dev->msgs_left == 0) {
+                /*
+                 * We're done.
+                 */
+                I2C_CRUMB(RXNE_DONE, 0, 0);
+                dev->state = I2C_STATE_XFER_DONE;
+            } else {
+                dev->msg++;
+            }
+        }
+    }
+}
+
+/*
+ * Interrupt handler for I2C error conditions. Aborts any pending I2C
+ * transactions.
+ */
+void _i2c_irq_error_handler(i2c_dev *dev) {
+    I2C_CRUMB(ERROR_ENTRY, dev->regs->SR1, dev->regs->SR2);
+
+    dev->error_flags = dev->regs->SR1 & (I2C_SR1_BERR |
+                                         I2C_SR1_ARLO |
+                                         I2C_SR1_AF |
+                                         I2C_SR1_OVR);
+
+    /* Are we in slave mode? */
+    if ((dev->regs->SR2 & I2C_SR2_MSL) != I2C_SR2_MSL) {
+        /* Check to see if the master device did a NAK on the last bit
+         * This is perfectly valid for a master to do this on the bus.
+         * We ignore this. Any further error processing takes us into dead
+         * loop waiting for the stop condition that will never arrive
+         */
+        if (dev->regs->SR1 & I2C_SR1_AF) {
+            /* Clear flags */
+            dev->regs->SR1 = 0;
+            dev->regs->SR2 = 0;
+            /* We need to write something to CR1 to clear the flag.
+             * This isn't really mentioned but seems important */
+            i2c_enable_ack(dev);
+
+            if (dev->state == I2C_STATE_SL_RX &&
+                dev->config_flags & I2C_SLAVE_USE_RX_BUFFER &&
+                dev->i2c_slave_msg->xferred > 0) {
+                /* Call the callback with the contents of the data */
+                if (dev->i2c_slave_recv_callback != NULL) (*(dev->i2c_slave_recv_callback))(dev->i2c_slave_msg);
+            }
+
+            dev->state = I2C_STATE_IDLE;
+            return;
+        }
+        /* Catch any other strange errors while in slave mode.
+         * I have seen BERR caused by an over fast master device
+         * as well as several overflows and arbitration failures.
+         * We are going to reset SR flags and carry on at this point which
+         * is not the best thing to do, but stops the bus locking up completely
+         * If we carry on below and send the stop bit, the code spins forever */
+        /* Clear flags */
+        dev->regs->SR1 = 0;
+        dev->regs->SR2 = 0;
+        dev->state = I2C_STATE_IDLE;
+        return;
+    }
+
+    /* Clear flags */
+    dev->regs->SR1 = 0;
+    dev->regs->SR2 = 0;
+
+    i2c_stop_condition(dev);
+    i2c_disable_irq(dev, I2C_IRQ_BUFFER | I2C_IRQ_EVENT | I2C_IRQ_ERROR);
+    dev->state = I2C_STATE_ERROR;
+}
+
+/*
+ * CCR/TRISE configuration helper
+ */
+static void set_ccr_trise(i2c_dev *dev, uint32 flags) {
+    uint32 ccr     = 0;
+    uint32 trise   = 0;
+    uint32 clk_mhz = _i2c_bus_clk(dev);
+    uint32 clk_hz  = clk_mhz * (1000 * 1000);
+
+    i2c_set_input_clk(dev, clk_mhz);
+
+    if (flags & I2C_FAST_MODE) {
+        ccr |= I2C_CCR_FS;
+
+        if (flags & I2C_DUTY_16_9) {
+            /* Tlow/Thigh = 16/9 */
+            ccr |= I2C_CCR_DUTY_16_9;
+            ccr |= clk_hz / (400000 * 25);
+        } else {
+            /* Tlow/Thigh = 2 */
+            ccr |= clk_hz / (400000 * 3);
+        }
+
+        trise = (300 * clk_mhz / 1000) + 1;
+    } else {
+        /* Tlow/Thigh = 1 */
+        ccr = clk_hz / (100000 * 2);
+        trise = clk_mhz + 1;
+    }
+
+    /* Set minimum required value if CCR < 1*/
+    if ((ccr & I2C_CCR_CCR) == 0) {
+        ccr |= 0x1;
+    }
+
+    i2c_set_clk_control(dev, ccr);
+    i2c_set_trise(dev, trise);
+}
+
+
+/**
+ * @brief callback for when the device acts as a slave. If using an rx buffer, this is triggered
+ * after the last byte, otherwise it is called for every incoming packet.
+ * @param dev I2C device
+ * @param msg The dev_msg to pass to the slave init code
+ * @param func The function pointer to call
+ */
+void i2c_slave_attach_recv_handler(i2c_dev *dev, i2c_msg *msg, i2c_slave_recv_callback_func func) {
+    dev->i2c_slave_recv_callback = func;
+    dev->i2c_slave_msg = msg;
+    msg->xferred = 0;
+}
+
+
+/**
+ * @brief callback for when the device acts as a slave. If using a tx buffer, this is triggered
+ * after the device is successsfully addressed with SLA+R.
+ * @param dev I2C device
+ * @param msg The dev_msg to pass to the slave init code
+ * @param func The function pointer to call
+ */
+void i2c_slave_attach_transmit_handler(i2c_dev *dev, i2c_msg *msg, i2c_slave_transmit_callback_func func) {
+    dev->i2c_slave_transmit_callback = func;
+    dev->i2c_slave_msg = msg;
+    msg->xferred = 0;
+}
diff --git a/STM32F1/libraries/WireSlave/src/i2c_slave.h.gch b/STM32F1/libraries/WireSlave/src/i2c_slave.h.gch
new file mode 100644
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diff --git a/STM32F1/libraries/WireSlave/src/libmaple/i2c_common_slave.h b/STM32F1/libraries/WireSlave/src/libmaple/i2c_common_slave.h
new file mode 100644
index 000000000..605c66375
--- /dev/null
+++ b/STM32F1/libraries/WireSlave/src/libmaple/i2c_common_slave.h
@@ -0,0 +1,110 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Perry Hung (from <libmaple/i2c.h>).
+ * Copyright (c) 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/include/libmaple/i2c_common.h
+ * @author Marti Bolivar <mbolivar@leaflabs.com>
+ * @brief This file is an implementation detail
+ *
+ * CONTENTS UNSTABLE. The existence of this file is an implementation
+ * detail.  Never include it directly.  If you need something from
+ * here, include <libmaple/i2c.h> instead.
+ *
+ * I2C slave support added 2012 by Barry Carter. barry.carter@gmail.com, headfuzz.co.uk
+ *
+ */
+
+#ifndef _LIBMAPLE_I2C_COMMON_H_
+#define _LIBMAPLE_I2C_COMMON_H_
+
+#include <libmaple/libmaple_types.h>
+#include <libmaple/nvic.h>
+#include <libmaple/rcc.h>
+
+struct gpio_dev;
+struct i2c_reg_map;
+struct i2c_msg;
+
+/** I2C device states */
+typedef enum i2c_state {
+    I2C_STATE_DISABLED          = 0, /**< Disabled */
+    I2C_STATE_IDLE              = 1, /**< Idle */
+    I2C_STATE_XFER_DONE         = 2, /**< Done with transfer */
+    I2C_STATE_BUSY              = 3, /**< Busy */
+    I2C_STATE_SL_RX             = 4, /**< Slave receiving */
+    I2C_STATE_ERROR             = -1 /**< Error occurred */
+} i2c_state;
+
+typedef void (*i2c_slave_recv_callback_func)(struct i2c_msg *);
+typedef void (*i2c_slave_transmit_callback_func)(struct i2c_msg *);
+/**
+ * @brief I2C device type.
+ */
+typedef struct i2c_dev {
+    struct i2c_reg_map *regs;   /**< Register map */
+    struct i2c_msg *msg;        /**< Messages */
+    uint32 error_flags;         /**< Error flags, set on I2C error condition */
+    volatile uint32 timestamp;  /**< For internal use */
+
+    /**
+     * @brief Deprecated. Use .scl_port or .sda_port instead.
+     * If non-null, this will be used as SDA, SCL pins' GPIO port. If
+     * null, then .sda_port will be used for SDA, and .sda_port for
+     * SDA. */
+    struct gpio_dev *gpio_port;
+
+    /**
+     * @brief SDA GPIO device (but see .gpio_port).
+     */
+    struct gpio_dev *sda_port;
+
+    /**
+     * @brief SCL GPIO device (but see .gpio_port).
+     */
+    struct gpio_dev *scl_port;
+
+    uint16 msgs_left;           /**< Messages left */
+    uint8 sda_pin;              /**< SDA bit on gpio_port */
+    uint8 scl_pin;              /**< SCL bit on gpio_port */
+    rcc_clk_id clk_id;          /**< RCC clock information */
+    nvic_irq_num ev_nvic_line;  /**< Event IRQ number */
+    nvic_irq_num er_nvic_line;  /**< Error IRQ number */
+    volatile i2c_state state;   /**< Device state */
+    uint32 config_flags;        /**< Configuration flags */
+
+    /*
+     * Slave implementation. Callback functions in this struct allow
+     * for a separate callback function for each I2C unit available onboard
+     */
+    i2c_slave_transmit_callback_func i2c_slave_transmit_callback;
+    i2c_slave_recv_callback_func i2c_slave_recv_callback;
+
+    struct i2c_msg *i2c_slave_msg; /* the message that the i2c slave will use */
+
+} i2c_dev;
+
+#endif
diff --git a/STM32F1/libraries/WireSlave/src/libmaple/i2c_slave.h b/STM32F1/libraries/WireSlave/src/libmaple/i2c_slave.h
new file mode 100644
index 000000000..1f290c2a6
--- /dev/null
+++ b/STM32F1/libraries/WireSlave/src/libmaple/i2c_slave.h
@@ -0,0 +1,475 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Perry Hung.
+ * Copyright (c) 2012 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/include/libmaple/i2c.h
+ * @brief Inter-Integrated Circuit (I2C) peripheral support
+ *
+ * Supports Master and Slave.
+ *  Master Usage notes:
+ *
+ * - Enable an I2C device with i2c_master_enable().
+ * - Initialize an array of struct i2c_msg to suit the bus
+ *   transactions (reads/writes) you wish to perform.
+ * - Call i2c_master_xfer() to do the work.
+ *
+ * Slave Usage notes:
+ * - Enable I2C slave by calling i2c_slave_enable().
+ *   Check flags for usage. Enabling master also enabled slave.
+ * - initialise the i2c_msg struct and the data buffer
+ * - initialise the callback functions
+ *
+ * I2C slave support added 2012 by Barry Carter. barry.carter@gmail.com, headfuzz.co.uk
+ */
+
+#ifndef _LIBMAPLE_I2C_H_
+#define _LIBMAPLE_I2C_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+/*
+ * Series header must provide:
+ *
+ * - uint32 _i2c_bus_clk(i2c_dev*): Clock frequency of dev's bus, in
+ *   MHz. (This is for internal use only).
+ *
+ * - (optional) _I2C_HAVE_IRQ_FIXUP: Leave undefined, or define to 1.
+ *   This is for internal use only. It's a hack to work around a
+ *   silicon bug related to I2C IRQ pre-emption on some targets. If 1,
+ *   the series header must also declare and implement a routine with
+ *   this signature (it may also be provided as a macro):
+ *
+ *       void _i2c_irq_priority_fixup(i2c_dev*)
+ *
+ *   This will be called by i2c_enable_irq() before actually enabling
+ *   I2C interrupts.
+ *
+ * - Reg. map base pointers, device pointer declarations.
+ */
+
+ /* Roger clark. Replaced with line below #include <series/i2c.h>*/
+#include "libmaple/i2c_common_slave.h"
+#include "stm32f1/include/series/i2c.h"
+
+#include <libmaple/libmaple_types.h>
+#include <libmaple/rcc.h>
+#include <libmaple/nvic.h>
+#include <libmaple/gpio.h>
+
+/** I2C register map type */
+typedef struct i2c_reg_map {
+    __io uint32 CR1;            /**< Control register 1 */
+    __io uint32 CR2;            /**< Control register 2 */
+    __io uint32 OAR1;           /**< Own address register 1 */
+    __io uint32 OAR2;           /**< Own address register 2 */
+    __io uint32 DR;             /**< Data register */
+    __io uint32 SR1;            /**< Status register 1 */
+    __io uint32 SR2;            /**< Status register 2 */
+    __io uint32 CCR;            /**< Clock control register */
+    __io uint32 TRISE;          /**< TRISE (rise time) register */
+} i2c_reg_map;
+
+/**
+ * @brief I2C message type
+ */
+typedef struct i2c_msg {
+    uint16 addr;                /**< Address */
+
+#define I2C_MSG_READ            0x1
+#define I2C_MSG_10BIT_ADDR      0x2
+    /**
+     * Bitwise OR of:
+     * - I2C_MSG_READ (write is default)
+     * - I2C_MSG_10BIT_ADDR (7-bit is default) */
+    uint16 flags;
+
+    uint16 length;              /**< Message length */
+    uint16 xferred;             /**< Messages transferred */
+    uint8 *data;                /**< Data */
+} i2c_msg;
+
+/*
+ * Register bit definitions
+ */
+
+/* Control register 1 */
+
+#define I2C_CR1_SWRST           (1U << 15)    // Software reset
+#define I2C_CR1_ALERT           (1U << 13)    // SMBus alert
+#define I2C_CR1_PEC             (1U << 12)    // Packet error checking
+#define I2C_CR1_POS             (1U << 11)    // Acknowledge/PEC position
+#define I2C_CR1_ACK             (1U << 10)    // Acknowledge enable
+#define I2C_CR1_STOP            (1U << 9)     // Stop generation
+#define I2C_CR1_START           (1U << 8)     // Start generation
+#define I2C_CR1_NOSTRETCH       (1U << 7)     // Clock stretching disable
+#define I2C_CR1_ENGC            (1U << 6)     // General call enable
+#define I2C_CR1_ENPEC           (1U << 5)     // PEC enable
+#define I2C_CR1_ENARP           (1U << 4)     // ARP enable
+#define I2C_CR1_SMBTYPE         (1U << 3)     // SMBus type
+#define I2C_CR1_SMBTYPE_DEVICE  (0U << 3)     //     SMBus type: device
+#define I2C_CR1_SMBTYPE_HOST    (1U << 3)     //     SMBus type: host
+#define I2C_CR1_SMBUS           (1U << 1)     // SMBus mode
+#define I2C_CR1_SMBUS_I2C       (0U << 1)     //     SMBus mode: I2C
+#define I2C_CR1_SMBUS_SMBUS     (1U << 1)     //     SMBus mode: SMBus
+#define I2C_CR1_PE              (1U << 0)     // Peripheral Enable
+
+/* Control register 2 */
+
+#define I2C_CR2_LAST            (1U << 12)    // DMA last transfer
+#define I2C_CR2_DMAEN           (1U << 11)    // DMA requests enable
+#define I2C_CR2_ITBUFEN         (1U << 10)    // Buffer interrupt enable
+#define I2C_CR2_ITEVTEN         (1U << 9)     // Event interupt enable
+#define I2C_CR2_ITERREN         (1U << 8)     // Error interupt enable
+#define I2C_CR2_FREQ            0x3F          // Peripheral input frequency
+
+/* Own address register 1 */
+
+#define I2C_OAR1_ADDMODE        (1U << 15)    // Addressing mode
+#define I2C_OAR1_ADDMODE_7_BIT  (0U << 15)    //     Addressing mode: 7-bit
+#define I2C_OAR1_ADDMODE_10_BIT (1U << 15)    //     Addressing mode: 10-bit
+#define I2C_OAR1_ADD            0x3FF         // Interface address
+
+/* Own address register 2 */
+
+#define I2C_OAR2_ADD2           0xFE          // Interface address
+#define I2C_OAR2_ENDUAL         1U            // Dual addressing mode enable
+
+/* Status register 1 */
+
+#define I2C_SR1_SMBALERT        (1U << 15)    // SMBus alert
+#define I2C_SR1_TIMEOUT         (1U << 14)    // Timeout or Tlow error
+#define I2C_SR1_PECERR          (1U << 12)    // PEC Error in reception
+#define I2C_SR1_OVR             (1U << 11)    // Overrun/underrun
+#define I2C_SR1_AF              (1U << 10)    // Acknowledge failure
+#define I2C_SR1_ARLO            (1U << 9)     // Arbitration lost
+#define I2C_SR1_BERR            (1U << 8)     // Bus error
+#define I2C_SR1_TXE             (1U << 7)     // Data register empty
+#define I2C_SR1_RXNE            (1U << 6)     // Data register not empty
+#define I2C_SR1_STOPF           (1U << 4)     // Stop detection
+#define I2C_SR1_ADD10           (1U << 3)     // 10-bit header sent
+#define I2C_SR1_BTF             (1U << 2)     // Byte transfer finished
+#define I2C_SR1_ADDR            (1U << 1)     // Address sent/matched
+#define I2C_SR1_SB              (1U << 0)     // Start bit
+
+/* Status register 2 */
+
+#define I2C_SR2_PEC             0xFF00        // Packet error checking register
+#define I2C_SR2_DUALF           (1U << 7)     // Dual flag
+#define I2C_SR2_SMBHOST         (1U << 6)     // SMBus host header
+#define I2C_SR2_SMBDEFAULT      (1U << 5)     // SMBus device default address
+#define I2C_SR2_GENCALL         (1U << 4)     // General call address
+#define I2C_SR2_TRA             (1U << 2)     // Transmitter/receiver
+#define I2C_SR2_BUSY            (1U << 1)     // Bus busy
+#define I2C_SR2_MSL             (1U << 0)     // Master/slave
+
+/* Clock control register */
+
+#define I2C_CCR_FS              (1U << 15)    // Fast mode selection
+#define I2C_CCR_DUTY            (1U << 14)    // Fast mode duty cycle
+#define I2C_CCR_DUTY_2_1        (0U << 14)    //     Fast mode duty: 2/1
+#define I2C_CCR_DUTY_16_9       (1U << 14)    //     Fast mode duty: 16/9
+#define I2C_CCR_CCR             0xFFF         // Clock control bits
+
+/*
+ * Convenience routines
+ */
+
+/* Main I2C API */
+
+/* I2C enable options */
+#define I2C_FAST_MODE           0x1           // 400 khz
+#define I2C_DUTY_16_9           0x2           // 16/9 duty ratio
+/* Flag 0x4 is reserved; DO NOT USE. */
+#define I2C_BUS_RESET           0x8           // Perform a bus reset
+#define I2C_SLAVE_USE_RX_BUFFER 0x10          // Use a buffered message when doing a slave recv
+#define I2C_SLAVE_USE_TX_BUFFER 0x20          // Use a buffered message when doing a slave transmit
+#define I2C_SLAVE_DUAL_ADDRESS  0x40          // Enable the dual slave address scheme
+#define I2C_SLAVE_GENERAL_CALL  0x80          // Enable the general call on address 0x00
+void i2c_master_enable(i2c_dev *dev, uint32 flags);
+void i2c_slave_enable(i2c_dev *dev, uint32 flags);
+
+#define I2C_ERROR_PROTOCOL      (-1)
+#define I2C_ERROR_TIMEOUT       (-2)
+int32 i2c_master_xfer(i2c_dev *dev, i2c_msg *msgs, uint16 num, uint32 timeout);
+
+void i2c_bus_reset(const i2c_dev *dev);
+
+/**
+ * @brief Disable an I2C device
+ *
+ * This function disables the corresponding peripheral and marks dev's
+ * state as I2C_STATE_DISABLED.
+ *
+ * @param dev Device to disable.
+ */
+static inline void i2c_disable(i2c_dev *dev) {
+    dev->regs->CR1 &= ~I2C_CR1_PE;
+    dev->state = I2C_STATE_DISABLED;
+}
+
+/* Start/stop conditions */
+
+/**
+ * @brief Generate a start condition on the bus.
+ * @param dev I2C device
+ */
+static inline void i2c_start_condition(i2c_dev *dev) {
+    uint32 cr1;
+    while ((cr1 = dev->regs->CR1) & (I2C_CR1_START |
+                                     I2C_CR1_STOP  |
+                                     I2C_CR1_PEC)) {
+        ;
+    }
+    dev->regs->CR1 |= I2C_CR1_START;
+}
+
+/**
+ * @brief Generate a stop condition on the bus
+ * @param dev I2C device
+ */
+static inline void i2c_stop_condition(i2c_dev *dev) {
+    uint32 cr1;
+    while ((cr1 = dev->regs->CR1) & (I2C_CR1_START |
+                                     I2C_CR1_STOP  |
+                                     I2C_CR1_PEC)) {
+        ;
+    }
+    dev->regs->CR1 |= I2C_CR1_STOP;
+    while ((cr1 = dev->regs->CR1) & (I2C_CR1_START |
+                                     I2C_CR1_STOP  |
+                                     I2C_CR1_PEC)) {
+        ;
+    }
+
+}
+
+/* IRQ enable/disable */
+
+#ifndef _I2C_HAVE_IRQ_FIXUP
+/* The series header provides this if _I2C_HAVE_IRQ_FIXUP is defined,
+ * but we need it either way. */
+#define _i2c_irq_priority_fixup(dev) ((void)0)
+#endif
+
+#define I2C_IRQ_ERROR              I2C_CR2_ITERREN
+#define I2C_IRQ_EVENT              I2C_CR2_ITEVTEN
+#define I2C_IRQ_BUFFER             I2C_CR2_ITBUFEN
+/**
+ * @brief Enable one or more I2C interrupts
+ * @param dev I2C device
+ * @param irqs Bitwise or of:
+ *             I2C_IRQ_ERROR (error interrupt),
+ *             I2C_IRQ_EVENT (event interrupt), and
+ *             I2C_IRQ_BUFFER (buffer interrupt).
+ */
+static inline void i2c_enable_irq(i2c_dev *dev, uint32 irqs) {
+    _i2c_irq_priority_fixup(dev);
+    dev->regs->CR2 |= irqs;
+}
+
+/**
+ * @brief Disable one or more I2C interrupts
+ * @param dev I2C device
+ * @param irqs Bitwise or of:
+ *             I2C_IRQ_ERROR (error interrupt),
+ *             I2C_IRQ_EVENT (event interrupt), and
+ *             I2C_IRQ_BUFFER (buffer interrupt).
+ */
+static inline void i2c_disable_irq(i2c_dev *dev, uint32 irqs) {
+    dev->regs->CR2 &= ~irqs;
+}
+
+/* ACK/NACK */
+
+/**
+ * @brief Enable I2C acknowledgment
+ * @param dev I2C device
+ */
+static inline void i2c_enable_ack(i2c_dev *dev) {
+    dev->regs->CR1 |= I2C_CR1_ACK;
+}
+
+/**
+ * @brief Disable I2C acknowledgment
+ * @param dev I2C device
+ */
+static inline void i2c_disable_ack(i2c_dev *dev) {
+    dev->regs->CR1 &= ~I2C_CR1_ACK;
+}
+
+/* GPIO control */
+
+/**
+ * @brief Configure device GPIOs.
+ *
+ * Configure GPIO bits dev->sda_pin and dev->scl_pin on GPIO device
+ * dev->gpio_port for use with I2C device dev.
+ *
+ * @param dev I2C Device
+ * @see i2c_release_gpios()
+ */
+extern void i2c_config_gpios(const i2c_dev *dev);
+
+/**
+ * @brief Release GPIOs controlling an I2C bus
+ *
+ * Releases the I2C bus controlled by dev as master, and disconnects
+ * GPIO bits dev->sda_pin and dev->scl_pin on GPIO device
+ * dev->gpio_port from I2C device dev.
+ *
+ * @param dev I2C device
+ * @see i2c_config_gpios()
+ */
+extern void i2c_master_release_bus(const i2c_dev *dev);
+
+/* Miscellaneous low-level routines */
+
+void i2c_init(i2c_dev *dev);
+
+/**
+ * @brief Turn on an I2C peripheral
+ * @param dev Device to enable
+ */
+static inline void i2c_peripheral_enable(i2c_dev *dev) {
+    dev->regs->CR1 |= I2C_CR1_PE;
+}
+
+/**
+ * @brief Turn off an I2C peripheral
+ * @param dev Device to turn off
+ */
+static inline void i2c_peripheral_disable(i2c_dev *dev) {
+    dev->regs->CR1 &= ~I2C_CR1_PE;
+}
+
+/**
+ * @brief Fill transmit register
+ * @param dev I2C device
+ * @param byte Byte to write
+ */
+static inline void i2c_write(i2c_dev *dev, uint8 byte) {
+    dev->regs->DR = byte;
+}
+
+/**
+ * @brief Set input clock frequency, in MHz
+ * @param dev I2C device
+ * @param freq Frequency, in MHz. This must be at least 2, and at most
+ *             the APB frequency of dev's bus. (For example, if
+ *             rcc_dev_clk(dev) == RCC_APB1, freq must be at most
+ *             PCLK1, in MHz). There is an additional limit of 46 MHz.
+ */
+static inline void i2c_set_input_clk(i2c_dev *dev, uint32 freq) {
+#define I2C_MAX_FREQ_MHZ 46
+    ASSERT(2 <= freq && freq <= _i2c_bus_clk(dev) && freq <= I2C_MAX_FREQ_MHZ);
+    uint32 cr2 = dev->regs->CR2;
+    cr2 &= ~I2C_CR2_FREQ;
+    cr2 |= freq;
+    dev->regs->CR2 = freq;
+#undef I2C_MAX_FREQ_MHZ
+}
+
+/**
+ * @brief Set I2C clock control register.
+ *
+ * See the chip reference manual for the details.
+ *
+ * @param dev I2C device
+ * @param val Value to use for clock control register (in
+ *            Fast/Standard mode)
+ */
+static inline void i2c_set_clk_control(i2c_dev *dev, uint32 val) {
+    uint32 ccr = dev->regs->CCR;
+    ccr &= ~I2C_CCR_CCR;
+    ccr |= val;
+    dev->regs->CCR = ccr;
+}
+
+/**
+ * @brief Set SCL rise time
+ * @param dev I2C device
+ * @param trise Maximum rise time in fast/standard mode (see chip
+ *              reference manual for the relevant formulas).
+ */
+static inline void i2c_set_trise(i2c_dev *dev, uint32 trise) {
+    dev->regs->TRISE = trise;
+}
+
+/*
+ * Slave support
+ */
+
+/**
+ * @brief Enable Dual addressing mode to allow peripheral to have 2 addresses
+ * @param dev I2C device
+  */
+static inline void i2c_slave_dual_address_enable(i2c_dev *dev) {
+    dev->regs->OAR2 |= I2C_OAR2_ENDUAL;
+}
+
+/**
+ * @brief Enable General Call to allow the  unit to respond on addr 0x00
+ * @param dev I2C device
+  */
+static inline void i2c_slave_general_call_enable(i2c_dev *dev) {
+    dev->regs->CR1 |= I2C_CR1_ENGC;
+}
+
+/* callback functions */
+/* Callback handler for data received over the bus */
+void i2c_slave_attach_recv_handler(i2c_dev *dev, i2c_msg *msg, i2c_slave_recv_callback_func func);
+
+/* Callback handler for data being requested over the bus
+ * The callback function must call i2c_write to get the data over the bus
+ */
+void i2c_slave_attach_transmit_handler(i2c_dev *dev, i2c_msg *msg, i2c_slave_transmit_callback_func func);
+
+/**
+ * @brief Set the primary I2c slave address
+ * @param dev I2C device
+ * @param address the 8 or 10 bit i2c address
+  */
+static inline void i2c_slave_set_own_address(i2c_dev *dev, uint16 address) {
+    dev->regs->OAR1 = address <<1;
+}
+
+/**
+ * @brief Set the secondary I2c slave address
+ * @param dev I2C device
+ * @param address the 8 or 10 bit i2c address
+  */
+static inline void i2c_slave_set_own_address2(i2c_dev *dev, uint16 address) {
+dev->regs->OAR2 = (address <<1 ) | I2C_OAR2_ENDUAL;
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/STM32F1/libraries/WireSlave/src/libmaple/i2c_slave.h.gch b/STM32F1/libraries/WireSlave/src/libmaple/i2c_slave.h.gch
new file mode 100644
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diff --git a/STM32F1/libraries/WireSlave/src/utility/WireBase_slave.cpp b/STM32F1/libraries/WireSlave/src/utility/WireBase_slave.cpp
new file mode 100644
index 000000000..a30921179
--- /dev/null
+++ b/STM32F1/libraries/WireSlave/src/utility/WireBase_slave.cpp
@@ -0,0 +1,145 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 LeafLabs LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file WireBase.cpp
+ * @author Trystan Jones <crenn6977@gmail.com>
+ * @brief Wire library, following the majority of the interface from Arduino.
+ *        Provides a 'standard' interface to I2C (two-wire) communication for
+ *        derived classes.
+ */
+
+/*
+ * Library created by crenn to allow a system which would provide users the
+ * 'standardised' Arduino method for interfacing with I2C devices regardless of
+ * whether it is I2C hardware or emulating software.
+ */
+
+#include "WireBase_slave.h"
+#include "wirish.h"
+
+void WireBase::begin(uint8 self_addr) {
+    tx_buf_idx = 0;
+    tx_buf_overflow = false;
+    rx_buf_idx = 0;
+    rx_buf_len = 0;
+}
+
+void WireBase::beginTransmission(uint8 slave_address) {
+    itc_msg.addr = slave_address;
+    itc_msg.data = &tx_buf[tx_buf_idx];
+    itc_msg.length = 0;
+    itc_msg.flags = 0;
+}
+
+void WireBase::beginTransmission(int slave_address) {
+    beginTransmission((uint8)slave_address);
+}
+
+uint8 WireBase::endTransmission(bool stop) {
+    uint8 retVal;
+    if (tx_buf_overflow) {
+        return EDATA;
+    }
+    retVal = process(stop);// Changed so that the return value from process is returned by this function see also the return line below
+    tx_buf_idx = 0;
+    tx_buf_overflow = false;
+    return retVal;//SUCCESS;
+}
+
+uint8 WireBase::endTransmission(){
+    endTransmission(true);
+}
+
+//TODO: Add the ability to queue messages (adding a boolean to end of function
+// call, allows for the Arduino style to stay while also giving the flexibility
+// to bulk send
+uint8 WireBase::requestFrom(uint8 address, int num_bytes) {
+    if (num_bytes > BUFFER_LENGTH) {
+        num_bytes = BUFFER_LENGTH;
+    }
+    itc_msg.addr = address;
+    itc_msg.flags = I2C_MSG_READ;
+    itc_msg.length = num_bytes;
+    itc_msg.data = &rx_buf[rx_buf_idx];
+    process();
+    rx_buf_len += itc_msg.xferred;
+    itc_msg.flags = 0;
+    return rx_buf_len;
+}
+
+uint8 WireBase::requestFrom(int address, int numBytes) {
+    return WireBase::requestFrom((uint8)address, numBytes);
+}
+
+void WireBase::write(uint8 value) {
+    if (tx_buf_idx == BUFFER_LENGTH) {
+        tx_buf_overflow = true;
+        return;
+    }
+    tx_buf[tx_buf_idx++] = value;
+    itc_msg.length++;
+}
+
+void WireBase::write(uint8* buf, int len) {
+    for (uint8 i = 0; i < len; i++) {
+        write(buf[i]);
+    }
+}
+
+void WireBase::write(int value) {
+    write((uint8)value);
+}
+
+void WireBase::write(int* buf, int len) {
+    write((uint8*)buf, (uint8)len);
+}
+
+void WireBase::write(char* buf) {
+    uint8 *ptr = (uint8*)buf;
+    while (*ptr) {
+        write(*ptr);
+        ptr++;
+    }
+}
+
+uint8 WireBase::available() {
+    return rx_buf_len - rx_buf_idx;
+}
+
+uint8 WireBase::read() {
+    if (rx_buf_idx == rx_buf_len) {
+        rx_buf_idx = 0;
+        rx_buf_len = 0;
+        return 0;
+    } else if (rx_buf_idx == (rx_buf_len-1)) {
+        uint8 temp = rx_buf[rx_buf_idx];
+        rx_buf_idx = 0;
+        rx_buf_len = 0;
+        return temp;
+    }
+    return rx_buf[rx_buf_idx++];
+}
diff --git a/STM32F1/libraries/WireSlave/src/utility/WireBase_slave.h b/STM32F1/libraries/WireSlave/src/utility/WireBase_slave.h
new file mode 100644
index 000000000..31f3f8cee
--- /dev/null
+++ b/STM32F1/libraries/WireSlave/src/utility/WireBase_slave.h
@@ -0,0 +1,145 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 LeafLabs LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file WireBase.h
+ * @author Trystan Jones <crenn6977@gmail.com>
+ * @brief Wire library, following the majority of the interface from Arduino.
+ *        Provides a 'standard' interface to I2C (two-wire) communication for
+ *        derived classes.
+ */
+
+/*
+ * Library created by crenn to allow a system which would provide users the
+ * 'standardised' Arduino method for interfacing with I2C devices regardless of
+ * whether it is I2C hardware or emulating software.
+ */
+
+#ifndef _WIREBASE_H_
+#define _WIREBASE_H_
+
+#include "wirish.h"
+#include <libmaple/i2c_slave.h>
+
+#define BUFFER_LENGTH 32
+
+/* return codes from endTransmission() */
+#define SUCCESS   0        /* transmission was successful */
+#define EDATA     1        /* too much data */
+#define ENACKADDR 2        /* received nack on transmit of address */
+#define ENACKTRNS 3        /* received nack on transmit of data */
+#define EOTHER    4        /* other error */
+
+class WireBase { // Abstraction is awesome!
+protected:
+    i2c_msg itc_msg;
+    uint8 rx_buf[BUFFER_LENGTH];      /* receive buffer */
+    uint8 rx_buf_idx;               /* first unread idx in rx_buf */
+    uint8 rx_buf_len;               /* number of bytes read */
+
+    uint8 tx_buf[BUFFER_LENGTH];      /* transmit buffer */
+    uint8 tx_buf_idx;  // next idx available in tx_buf, -1 overflow
+    boolean tx_buf_overflow;
+
+    // Force derived classes to define process function
+    virtual uint8 process(uint8) = 0;
+    virtual uint8 process() = 0;
+public:
+    WireBase() {}
+    ~WireBase() {}
+
+    /*
+     * Initialises the class interface
+     */
+    // Allow derived classes to overwrite begin function
+    virtual void begin(uint8 = 0x00);
+
+    /*
+     * Sets up the transmission message to be processed
+     */
+    void beginTransmission(uint8);
+
+    /*
+     * Allow only 8 bit addresses to be used
+     */
+    void beginTransmission(int);
+
+    /*
+     * Call the process function to process the message if the TX
+     * buffer has not overflowed.
+     */
+    uint8 endTransmission(bool);
+    uint8 endTransmission(void);
+
+    /*
+     * Request bytes from a slave device and process the request,
+     * storing into the receiving buffer.
+     */
+    uint8 requestFrom(uint8, int);
+
+    /*
+     * Allow only 8 bit addresses to be used when requesting bytes
+     */
+    uint8 requestFrom(int, int);
+
+    /*
+     * Stack up bytes to be sent when transmitting
+     */
+    void write(uint8);
+
+    /*
+     * Stack up bytes from the array to be sent when transmitting
+     */
+    void write(uint8*, int);
+
+    /*
+     * Ensure that a sending data will only be 8-bit bytes
+     */
+    void write(int);
+
+    /*
+     * Ensure that an array sending data will only be 8-bit bytes
+     */
+    void write(int*, int);
+
+    /*
+     * Stack up bytes from a string to be sent when transmitting
+     */
+    void write(char*);
+
+    /*
+     * Return the amount of bytes that is currently in the receiving buffer
+     */
+    uint8 available();
+
+    /*
+     * Return the value of byte in the receiving buffer that is currently being
+     * pointed to
+     */
+    uint8 read();
+};
+
+#endif // _WIREBASE_H_
diff --git a/STM32F1/libraries/WireSlave/src/utility/WireBase_slave.h.gch b/STM32F1/libraries/WireSlave/src/utility/WireBase_slave.h.gch
new file mode 100644
index 0000000000000000000000000000000000000000..5a6345078e7abad4b9211a296cfa52568e2ed238
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From 4157ef37a1ebbb8dd24560158074974663d3b189 Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Thu, 14 Dec 2017 16:41:43 +0100
Subject: [PATCH 270/307] Removed some accidental adds

---
 STM32F1/libraries/Wire/Wire_slave.h           |   2 +-
 STM32F1/libraries/WireSlave/src/Wire.h        |   2 +-
 STM32F1/libraries/WireSlave/src/Wire.h.gch    | Bin 1819056 -> 0 bytes
 .../libraries/WireSlave/src/Wire_slave.h.gch  | Bin 9475 -> 0 bytes
 .../libraries/WireSlave/src/i2c_slave.h.gch   | Bin 9475 -> 0 bytes
 .../WireSlave/src/libmaple/i2c_slave.h.gch    | Bin 9475 -> 0 bytes
 .../src/utility/WireBase_slave.h.gch          | Bin 9475 -> 0 bytes
 7 files changed, 2 insertions(+), 2 deletions(-)
 delete mode 100644 STM32F1/libraries/WireSlave/src/Wire.h.gch
 delete mode 100644 STM32F1/libraries/WireSlave/src/Wire_slave.h.gch
 delete mode 100644 STM32F1/libraries/WireSlave/src/i2c_slave.h.gch
 delete mode 100644 STM32F1/libraries/WireSlave/src/libmaple/i2c_slave.h.gch
 delete mode 100644 STM32F1/libraries/WireSlave/src/utility/WireBase_slave.h.gch

diff --git a/STM32F1/libraries/Wire/Wire_slave.h b/STM32F1/libraries/Wire/Wire_slave.h
index 21b4102bd..ede963b37 100644
--- a/STM32F1/libraries/Wire/Wire_slave.h
+++ b/STM32F1/libraries/Wire/Wire_slave.h
@@ -1 +1 @@
-#error "Something is trying to include Wire.h when Wire_Slave.h is already included, they are mutually exclusive"
+#error "Something is trying to include Wire_slave.h when Wire.h is already included, they are mutually exclusive"
diff --git a/STM32F1/libraries/WireSlave/src/Wire.h b/STM32F1/libraries/WireSlave/src/Wire.h
index ede963b37..2d3ce7049 100644
--- a/STM32F1/libraries/WireSlave/src/Wire.h
+++ b/STM32F1/libraries/WireSlave/src/Wire.h
@@ -1 +1 @@
-#error "Something is trying to include Wire_slave.h when Wire.h is already included, they are mutually exclusive"
+#error "Something is trying to include Wire.h when Wire_slave.h is already included, they are mutually exclusive"
diff --git a/STM32F1/libraries/WireSlave/src/Wire.h.gch b/STM32F1/libraries/WireSlave/src/Wire.h.gch
deleted file mode 100644
index b29a5ea9fd8851ea75533c42ff77077972caf5ce..0000000000000000000000000000000000000000
GIT binary patch
literal 0
HcmV?d00001

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From 730711b80aced608f59020803335e6b2dc482053 Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Thu, 14 Dec 2017 16:45:55 +0100
Subject: [PATCH 271/307] Made sure Wire_slave.h is included first

---
 .../WireSlave/examples/i2c_libmaple_slave/i2c_libmaple_slave.ino | 1 +
 1 file changed, 1 insertion(+)

diff --git a/STM32F1/libraries/WireSlave/examples/i2c_libmaple_slave/i2c_libmaple_slave.ino b/STM32F1/libraries/WireSlave/examples/i2c_libmaple_slave/i2c_libmaple_slave.ino
index 23456e40a..51e2dcc5a 100644
--- a/STM32F1/libraries/WireSlave/examples/i2c_libmaple_slave/i2c_libmaple_slave.ino
+++ b/STM32F1/libraries/WireSlave/examples/i2c_libmaple_slave/i2c_libmaple_slave.ino
@@ -6,6 +6,7 @@
 *  Created on: 4 Sep 2012
 *      Author: Barry Carter <barry.carter@gmail.com>
 */
+#include <Wire_slave.h>
 #include <Arduino.h>
 #include <libmaple/i2c.h>
 

From 3425506d1983c7ae41153f80a8ba7651b25492fc Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Thu, 14 Dec 2017 17:30:35 +0100
Subject: [PATCH 272/307] spellcheccck

---
 STM32F1/libraries/WireSlave/library.properties | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/libraries/WireSlave/library.properties b/STM32F1/libraries/WireSlave/library.properties
index 2a1c387b2..fd24ab1df 100644
--- a/STM32F1/libraries/WireSlave/library.properties
+++ b/STM32F1/libraries/WireSlave/library.properties
@@ -8,4 +8,4 @@ url=
 architectures=STM32F1
 maintainer=
 category=Communication
-include=src/Wire_Slave.h
+include=src/Wire_slave.h

From c4fdf5aa63a787ce9a28ddebfab9428e7681a65b Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Thu, 14 Dec 2017 21:04:54 +0100
Subject: [PATCH 273/307] keywords.txt Copied from ArduinoCore-sam (Due)

---
 STM32F1/libraries/WireSlave/keywords.txt | 31 ++++++++++++++++++++++++
 1 file changed, 31 insertions(+)
 create mode 100644 STM32F1/libraries/WireSlave/keywords.txt

diff --git a/STM32F1/libraries/WireSlave/keywords.txt b/STM32F1/libraries/WireSlave/keywords.txt
new file mode 100644
index 000000000..47ffd52d0
--- /dev/null
+++ b/STM32F1/libraries/WireSlave/keywords.txt
@@ -0,0 +1,31 @@
+#######################################
+# Syntax Coloring Map For Wire
+#######################################
+
+#######################################
+# Datatypes (KEYWORD1)
+#######################################
+
+#######################################
+# Methods and Functions (KEYWORD2)
+#######################################
+
+begin	KEYWORD2
+setClock	KEYWORD2
+beginTransmission	KEYWORD2
+endTransmission	KEYWORD2
+requestFrom	KEYWORD2
+onReceive	KEYWORD2
+onRequest	KEYWORD2
+
+#######################################
+# Instances (KEYWORD2)
+#######################################
+
+Wire	KEYWORD2
+Wire1	KEYWORD2
+
+#######################################
+# Constants (LITERAL1)
+#######################################
+

From 56e95f2773f10b1dad148d1c5e3f93b45c5b9cd2 Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Thu, 14 Dec 2017 22:03:09 +0100
Subject: [PATCH 274/307] Steals any reference to Wire.h and redirects it to
 Wire_slave.h. This way we don't need to alter third party libraries. Note
 that Wire_slave.h must be included **before** the real Wire.h for this to
 work.

---
 STM32F1/libraries/WireSlave/src/Wire.h | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/STM32F1/libraries/WireSlave/src/Wire.h b/STM32F1/libraries/WireSlave/src/Wire.h
index 2d3ce7049..0a47d0322 100644
--- a/STM32F1/libraries/WireSlave/src/Wire.h
+++ b/STM32F1/libraries/WireSlave/src/Wire.h
@@ -1 +1,4 @@
-#error "Something is trying to include Wire.h when Wire_slave.h is already included, they are mutually exclusive"
+#pragma once
+#include "Wire_slave.h"
+
+//#error "Something is trying to include Wire.h when Wire_slave.h is already included, they are mutually exclusive"

From 6fe4a55922a30cef5f03c6a12897a682d12cf44d Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Fri, 15 Dec 2017 11:56:01 +0100
Subject: [PATCH 275/307] Added SoftWire.h

---
 STM32F1/libraries/Wire/library.properties | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/libraries/Wire/library.properties b/STM32F1/libraries/Wire/library.properties
index 1129fa3fb..2d822fedb 100644
--- a/STM32F1/libraries/Wire/library.properties
+++ b/STM32F1/libraries/Wire/library.properties
@@ -7,4 +7,4 @@ paragraph=
 category=Communication
 url=http://www.arduino.cc/en/Reference/Wire
 architectures=STM32F1
-include=Wire.h
+include=Wire.h,SoftWire.h

From c65ec99a8d206aada5fbdc4be83e6f099c9c2a5e Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Fri, 15 Dec 2017 13:19:37 +0100
Subject: [PATCH 276/307] Updated library.properties

---
 STM32F1/libraries/Wire/library.properties | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/STM32F1/libraries/Wire/library.properties b/STM32F1/libraries/Wire/library.properties
index 2d822fedb..06b7aee78 100644
--- a/STM32F1/libraries/Wire/library.properties
+++ b/STM32F1/libraries/Wire/library.properties
@@ -1,7 +1,7 @@
 name=Wire
 version=1.0
-author=Arduino
-maintainer=Arduino <info@arduino.cc>
+author=Roger Clark
+maintainer=
 sentence=Allows the communication between devices or sensors connected via Two Wire Interface Bus.
 paragraph=
 category=Communication

From 987102c8d2d23ee09498c2b9ba36cba1057409a3 Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Fri, 15 Dec 2017 16:00:54 +0100
Subject: [PATCH 277/307] Temporarily removed not yet functioning examples

---
 .../slave_receiver/slave_receiver.ino         | 38 -------------------
 .../examples/slave_sender/slave_sender.ino    | 32 ----------------
 2 files changed, 70 deletions(-)
 delete mode 100644 STM32F1/libraries/WireSlave/examples/slave_receiver/slave_receiver.ino
 delete mode 100644 STM32F1/libraries/WireSlave/examples/slave_sender/slave_sender.ino

diff --git a/STM32F1/libraries/WireSlave/examples/slave_receiver/slave_receiver.ino b/STM32F1/libraries/WireSlave/examples/slave_receiver/slave_receiver.ino
deleted file mode 100644
index b430c2539..000000000
--- a/STM32F1/libraries/WireSlave/examples/slave_receiver/slave_receiver.ino
+++ /dev/null
@@ -1,38 +0,0 @@
-// Wire Slave Receiver
-// by Nicholas Zambetti <http://www.zambetti.com>
-
-// Demonstrates use of the Wire library
-// Receives data as an I2C/TWI slave device
-// Refer to the "Wire Master Writer" example for use with this
-
-// Created 29 March 2006
-
-// This example code is in the public domain.
-
-
-#include <Wire_slave.h>
-
-void setup()
-{
-  Wire.begin(4);                // join i2c bus with address #4
-  Wire.onReceive(receiveEvent); // register event
-  Serial.begin(9600);           // start serial for output
-}
-
-void loop()
-{
-  delay(100);
-}
-
-// function that executes whenever data is received from master
-// this function is registered as an event, see setup()
-void receiveEvent(int howMany)
-{
-  while(1 < Wire.available()) // loop through all but the last
-  {
-    char c = Wire.read(); // receive byte as a character
-    Serial.print(c);         // print the character
-  }
-  int x = Wire.read();    // receive byte as an integer
-  Serial.println(x);         // print the integer
-}
diff --git a/STM32F1/libraries/WireSlave/examples/slave_sender/slave_sender.ino b/STM32F1/libraries/WireSlave/examples/slave_sender/slave_sender.ino
deleted file mode 100644
index fcdac14b3..000000000
--- a/STM32F1/libraries/WireSlave/examples/slave_sender/slave_sender.ino
+++ /dev/null
@@ -1,32 +0,0 @@
-// Wire Slave Sender
-// by Nicholas Zambetti <http://www.zambetti.com>
-
-// Demonstrates use of the Wire library
-// Sends data as an I2C/TWI slave device
-// Refer to the "Wire Master Reader" example for use with this
-
-// Created 29 March 2006
-
-// This example code is in the public domain.
-
-
-#include <Wire_slave.h>
-
-void setup()
-{
-  Wire.begin(2);                // join i2c bus with address #2
-  Wire.onRequest(requestEvent); // register event
-}
-
-void loop()
-{
-  delay(100);
-}
-
-// function that executes whenever data is requested by master
-// this function is registered as an event, see setup()
-void requestEvent()
-{
-  Wire.write("hello "); // respond with message of 6 bytes
-                       // as expected by master
-}

From 78f8a90a2df3f408cab28764d35113a06263295e Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Tue, 19 Dec 2017 23:46:32 +0100
Subject: [PATCH 278/307] Fixed a master/slave mode mixup. Turns out that
 (sr2&I2C_SR2_MSL)!=I2C_SR2_MSL indicates slave mode after master has
 requested, and received, data.

"MSL - Cleared by hardware after detecting a Stop condition on the bus or a loss of arbitration
(ARLO=1), or by hardware when PE=0." -RM0008
---
 STM32F1/libraries/WireSlave/src/i2c_slave.c | 17 +++++++++--------
 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/STM32F1/libraries/WireSlave/src/i2c_slave.c b/STM32F1/libraries/WireSlave/src/i2c_slave.c
index 770cd3a63..865949b36 100644
--- a/STM32F1/libraries/WireSlave/src/i2c_slave.c
+++ b/STM32F1/libraries/WireSlave/src/i2c_slave.c
@@ -70,6 +70,12 @@ static inline void i2c_send_slave_addr(i2c_dev *dev, uint32 addr, uint32 rw) {
 #ifdef I2C_DEBUG
 
 #define NR_CRUMBS       128
+struct crumb {
+    uint32 event;
+    uint32 arg0;
+    uint32 arg1;
+    uint32 arg2; // filler to make the data fit GDB memory dump screen
+};
 static struct crumb crumbs[NR_CRUMBS];
 static uint32 cur_crumb = 0;
 
@@ -79,6 +85,7 @@ static inline void i2c_drop_crumb(uint32 event, uint32 arg0, uint32 arg1) {
         crumb->event = event;
         crumb->arg0 = arg0;
         crumb->arg1 = arg1;
+        crumb->arg2 = cur_crumb-1;
     }
 }
 #define I2C_CRUMB(event, arg0, arg1) i2c_drop_crumb(event, arg0, arg1)
@@ -87,12 +94,6 @@ static inline void i2c_drop_crumb(uint32 event, uint32 arg0, uint32 arg1) {
 #define I2C_CRUMB(event, arg0, arg1)
 #endif
 
-struct crumb {
-    uint32 event;
-    uint32 arg0;
-    uint32 arg1;
-};
-
 enum {
     IRQ_ENTRY           = 1,
     TXE_ONLY            = 2,
@@ -351,8 +352,8 @@ void _i2c_irq_handler(i2c_dev *dev) {
      * Add Slave support
      */
 
-    /* Check to see if MSL master slave bit is set */
-    if ((sr2 & I2C_SR2_MSL) != I2C_SR2_MSL) { /* 0 = slave mode 1 = master */
+    /* Check to see if in slave mode */
+    if (dev->config_flags&(I2C_SLAVE_DUAL_ADDRESS|I2C_SLAVE_GENERAL_CALL)) {
 
         /* Check for address match */
         if (sr1 & I2C_SR1_ADDR) {

From b46b7461f401a2b51259fb76b350b5748b2f564a Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Fri, 22 Dec 2017 18:52:12 +0100
Subject: [PATCH 279/307] Merged with Wire implementation from
 stm32duino/Arduino_Core_STM32

---
 .../SFRRanger_reader/SFRRanger_reader.ino     |   2 +-
 .../i2c_libmaple_slave_reader.ino}            |   5 -
 .../i2c_scanner_wire/i2c_scanner_wire.ino     |  78 +++
 .../examples/master_reader/master_reader.ino  |   4 +-
 .../WireSlave/examples/selftest1/code.cpp     |  68 ++
 .../examples/selftest1/selftest1.ino          |  16 +
 .../slave_receiver/slave_receiver.ino         |  37 ++
 .../examples/slave_sender/slave_sender.ino    |  32 +
 .../libraries/WireSlave/src/Wire_slave.cpp    | 591 +++++++++++++++---
 STM32F1/libraries/WireSlave/src/Wire_slave.h  | 209 +++++--
 .../libraries/WireSlave/src/Wire_slave.h.gch  | Bin 0 -> 9475 bytes
 STM32F1/libraries/WireSlave/src/i2c_slave.c   |  15 +-
 .../WireSlave/src/utility/WireBase_slave.cpp  | 145 -----
 .../WireSlave/src/utility/WireBase_slave.h    | 145 -----
 14 files changed, 888 insertions(+), 459 deletions(-)
 rename STM32F1/libraries/WireSlave/examples/{i2c_libmaple_slave/i2c_libmaple_slave.ino => i2c_libmaple_slave_reader/i2c_libmaple_slave_reader.ino} (97%)
 create mode 100644 STM32F1/libraries/WireSlave/examples/i2c_scanner_wire/i2c_scanner_wire.ino
 create mode 100644 STM32F1/libraries/WireSlave/examples/selftest1/code.cpp
 create mode 100644 STM32F1/libraries/WireSlave/examples/selftest1/selftest1.ino
 create mode 100644 STM32F1/libraries/WireSlave/examples/slave_receiver/slave_receiver.ino
 create mode 100644 STM32F1/libraries/WireSlave/examples/slave_sender/slave_sender.ino
 create mode 100644 STM32F1/libraries/WireSlave/src/Wire_slave.h.gch
 delete mode 100644 STM32F1/libraries/WireSlave/src/utility/WireBase_slave.cpp
 delete mode 100644 STM32F1/libraries/WireSlave/src/utility/WireBase_slave.h

diff --git a/STM32F1/libraries/WireSlave/examples/SFRRanger_reader/SFRRanger_reader.ino b/STM32F1/libraries/WireSlave/examples/SFRRanger_reader/SFRRanger_reader.ino
index 5537eca56..9409bb10e 100644
--- a/STM32F1/libraries/WireSlave/examples/SFRRanger_reader/SFRRanger_reader.ino
+++ b/STM32F1/libraries/WireSlave/examples/SFRRanger_reader/SFRRanger_reader.ino
@@ -15,7 +15,7 @@
 void setup()
 {
   Wire.begin();                // join i2c bus (address optional for master)
-  Serial.begin(9600);          // start serial communication at 9600bps
+  Serial.begin(115200);        // start serial communication at 9600bps
 }
 
 int reading = 0;
diff --git a/STM32F1/libraries/WireSlave/examples/i2c_libmaple_slave/i2c_libmaple_slave.ino b/STM32F1/libraries/WireSlave/examples/i2c_libmaple_slave_reader/i2c_libmaple_slave_reader.ino
similarity index 97%
rename from STM32F1/libraries/WireSlave/examples/i2c_libmaple_slave/i2c_libmaple_slave.ino
rename to STM32F1/libraries/WireSlave/examples/i2c_libmaple_slave_reader/i2c_libmaple_slave_reader.ino
index 51e2dcc5a..a63ff3c98 100644
--- a/STM32F1/libraries/WireSlave/examples/i2c_libmaple_slave/i2c_libmaple_slave.ino
+++ b/STM32F1/libraries/WireSlave/examples/i2c_libmaple_slave_reader/i2c_libmaple_slave_reader.ino
@@ -8,7 +8,6 @@
 */
 #include <Wire_slave.h>
 #include <Arduino.h>
-#include <libmaple/i2c.h>
 
 #define USE_BUFFERED_EXAMPLE 1
 
@@ -52,12 +51,8 @@ void functx(i2c_msg *msg){
 
 #endif
 
-// #define Serial Serial1
-
 void setup() {
   Serial.begin(115200);
-  while(!Serial)
-    ;
   Serial.println("I2C Slave example");
 
   // attach the buffer
diff --git a/STM32F1/libraries/WireSlave/examples/i2c_scanner_wire/i2c_scanner_wire.ino b/STM32F1/libraries/WireSlave/examples/i2c_scanner_wire/i2c_scanner_wire.ino
new file mode 100644
index 000000000..44af4dc1d
--- /dev/null
+++ b/STM32F1/libraries/WireSlave/examples/i2c_scanner_wire/i2c_scanner_wire.ino
@@ -0,0 +1,78 @@
+// --------------------------------------
+// i2c_scanner
+//
+// Version 1
+//    This program (or code that looks like it)
+//    can be found in many places.
+//    For example on the Arduino.cc forum.
+//    The original author is not know.
+// Version 2, Juni 2012, Using Arduino 1.0.1
+//     Adapted to be as simple as possible by Arduino.cc user Krodal
+// Version 3, Feb 26  2013
+//    V3 by louarnold
+// Version 4, March 3, 2013, Using Arduino 1.0.3
+//    by Arduino.cc user Krodal.
+//    Changes by louarnold removed.
+//    Scanning addresses changed from 0...127 to 1...119,
+//    according to the i2c scanner by Nick Gammon
+//    http://www.gammon.com.au/forum/?id=10896
+// Version 5, March 28, 2013
+//    As version 4, but address scans now to 127.
+//    A sensor seems to use address 120.
+//
+// This sketch tests the standard 7-bit addresses
+// Devices with higher bit address might not be seen properly.
+//
+
+#include <Wire_slave.h>
+
+//use IIC2
+//TwoWire WIRE2 (2,I2C_FAST_MODE);
+//#define Wire WIRE2
+
+
+void setup() {
+
+  Serial.begin(115200);
+  Wire.begin();
+  Serial.println("\nI2C Scanner");
+}
+
+
+void loop() {
+  byte error, address;
+  int nDevices;
+
+  Serial.println("Scanning...");
+
+  nDevices = 0;
+  for(address = 1; address < 127; address++) {
+    // The i2c_scanner uses the return value of
+    // the Write.endTransmisstion to see if
+    // a device did acknowledge to the address.
+
+    Wire.beginTransmission(address);
+    error = Wire.endTransmission();
+    
+    if (error == 0) {
+      Serial.print("I2C device found at address 0x");
+      if (address < 16) 
+        Serial.print("0");
+      Serial.println(address, HEX);
+
+      nDevices++;
+    }
+    else if (error == 4) {
+      Serial.print("Unknown error at address 0x");
+      if (address < 16) 
+        Serial.print("0");
+      Serial.println(address, HEX);
+    }    
+  }
+  if (nDevices == 0)
+    Serial.println("No I2C devices found");
+  else
+    Serial.println("done");
+
+  delay(5000);           // wait 5 seconds for next scan
+}
diff --git a/STM32F1/libraries/WireSlave/examples/master_reader/master_reader.ino b/STM32F1/libraries/WireSlave/examples/master_reader/master_reader.ino
index 4b45d1289..bd914e368 100644
--- a/STM32F1/libraries/WireSlave/examples/master_reader/master_reader.ino
+++ b/STM32F1/libraries/WireSlave/examples/master_reader/master_reader.ino
@@ -15,12 +15,12 @@
 void setup()
 {
   Wire.begin();        // join i2c bus (address optional for master)
-  Serial.begin(9600);  // start serial for output
+  Serial.begin(115200);  // start serial for output
 }
 
 void loop()
 {
-  Wire.requestFrom(2, 6);    // request 6 bytes from slave device #2
+  Wire.requestFrom(8, 6);    // request 6 bytes from slave device #8
 
   while(Wire.available())    // slave may send less than requested
   {
diff --git a/STM32F1/libraries/WireSlave/examples/selftest1/code.cpp b/STM32F1/libraries/WireSlave/examples/selftest1/code.cpp
new file mode 100644
index 000000000..d2bce8c61
--- /dev/null
+++ b/STM32F1/libraries/WireSlave/examples/selftest1/code.cpp
@@ -0,0 +1,68 @@
+// Wire Slave Receiver
+// by Nicholas Zambetti <http://www.zambetti.com>
+
+// Demonstrates use of the Wire library
+// Receives data as an I2C/TWI slave device
+// Refer to the "Wire Master Writer" example for use with this
+
+// Created 29 March 2006
+
+// This example code is in the public domain.
+
+#include <Wire_slave.h>
+//#define Serial Serial1
+
+#define MasterWire Wire
+#define SlaveWire Wire1
+#define ENABLE_SLAVE
+#define ENABLE_MASTER
+
+void receiveEvent(int howMany);
+
+void setup(){
+  Serial.begin(115200);         // start serial for output
+  
+  #ifdef ENABLE_MASTER
+  MasterWire.begin();     // join i2c bus #1 as master
+  Serial.println("Done with MasterWire.begin ");
+  #endif
+
+  #ifdef ENABLE_SLAVE
+  SlaveWire.begin(4);     // join i2c bus #2 as slave with address #4
+  Serial.println("Done with SlaveWire.begin ");
+  #endif
+
+  #ifdef ENABLE_SLAVE
+  SlaveWire.onReceive(receiveEvent); // register event
+  #endif
+}
+
+void loop(){
+  #ifdef ENABLE_MASTER
+  static byte x = 0;
+  Serial.print("Master writing ");
+  Serial.println(x);
+  
+  MasterWire.beginTransmission(4); // transmit to device #4
+  MasterWire.write("x is ");       // sends five bytes
+  MasterWire.write(x);             // sends one byte
+  MasterWire.endTransmission();    // stop transmitting
+
+  x++;
+  #endif
+  delay(500);
+}
+
+// function that executes whenever data is received from master
+// this function is registered as an event, see setup()
+// Note that it is not advicable to call Serial.print() from within an ISR
+void receiveEvent(int howMany){
+  //Serial.print("Slave receving ");
+  while(1 < SlaveWire.available()){ // loop through all but the last
+    char c = SlaveWire.read(); // receive byte as a character
+    Serial.print(c);         // print the character
+  }
+  int x = SlaveWire.read();    // receive byte as an integer
+  Serial.println(x);         // print the integer
+}
+
diff --git a/STM32F1/libraries/WireSlave/examples/selftest1/selftest1.ino b/STM32F1/libraries/WireSlave/examples/selftest1/selftest1.ino
new file mode 100644
index 000000000..58f1e5c2c
--- /dev/null
+++ b/STM32F1/libraries/WireSlave/examples/selftest1/selftest1.ino
@@ -0,0 +1,16 @@
+// Wire Slave Receiver
+// by Nicholas Zambetti <http://www.zambetti.com>
+
+// Demonstrates use of the Wire library
+// Receives data as an I2C/TWI slave device
+// Refer to the "Wire Master Writer" example for use with this
+
+// Created 29 March 2006
+
+// This example code is in the public domain.
+
+// The code is temporarily moved to the code.cpp.
+// This makes it possible to set breakpoints in eclipse IDE.
+// I'm sure that there is an Eclipse configuration that makes it 
+// possible for it to detect .ino files as .cpp, but I'm lazy
+
diff --git a/STM32F1/libraries/WireSlave/examples/slave_receiver/slave_receiver.ino b/STM32F1/libraries/WireSlave/examples/slave_receiver/slave_receiver.ino
new file mode 100644
index 000000000..5d71b9a20
--- /dev/null
+++ b/STM32F1/libraries/WireSlave/examples/slave_receiver/slave_receiver.ino
@@ -0,0 +1,37 @@
+// Wire Slave Receiver
+// by Nicholas Zambetti <http://www.zambetti.com>
+
+// Demonstrates use of the Wire library
+// Receives data as an I2C/TWI slave device
+// Refer to the "Wire Master Writer" example for use with this
+
+// Created 29 March 2006
+
+// This example code is in the public domain.
+
+
+#include <Wire_slave.h>
+#define Serial Serial1
+
+void setup(){
+  Serial.begin(115200);         // start serial for output
+
+  Wire.begin(4);                // join i2c bus with address #4
+  Wire.onReceive(receiveEvent); // register event
+}
+
+void loop(){
+  delay(100);
+}
+
+// function that executes whenever data is received from master
+// this function is registered as an event, see setup()
+// Note that it is not advicable to call Serial.print() from within an ISR
+void receiveEvent(int howMany){
+  while(1 < Wire.available()){ // loop through all but the last
+    char c = Wire.read(); // receive byte as a character
+    Serial.print(c);         // print the character
+  }
+  int x = Wire.read();    // receive byte as an integer
+  Serial.println(x);         // print the integer
+}
diff --git a/STM32F1/libraries/WireSlave/examples/slave_sender/slave_sender.ino b/STM32F1/libraries/WireSlave/examples/slave_sender/slave_sender.ino
new file mode 100644
index 000000000..75add4a00
--- /dev/null
+++ b/STM32F1/libraries/WireSlave/examples/slave_sender/slave_sender.ino
@@ -0,0 +1,32 @@
+// Wire Slave Sender
+// by Nicholas Zambetti <http://www.zambetti.com>
+
+// Demonstrates use of the Wire library
+// Sends data as an I2C/TWI slave device
+// Refer to the "Wire Master Reader" example for use with this
+
+// Created 29 March 2006
+
+// This example code is in the public domain.
+
+
+#include <Wire_slave.h>
+
+void setup()
+{
+  Wire.begin(8);                // join i2c bus with address #8
+  Wire.onRequest(requestEvent); // register event
+}
+
+void loop()
+{
+  delay(100);
+}
+
+// function that executes whenever data is requested by master
+// this function is registered as an event, see setup()
+void requestEvent()
+{
+  Wire.write("hello "); // respond with message of 6 bytes
+                        // as expected by master
+}
diff --git a/STM32F1/libraries/WireSlave/src/Wire_slave.cpp b/STM32F1/libraries/WireSlave/src/Wire_slave.cpp
index 93cc55f09..75e753f5c 100644
--- a/STM32F1/libraries/WireSlave/src/Wire_slave.cpp
+++ b/STM32F1/libraries/WireSlave/src/Wire_slave.cpp
@@ -1,106 +1,523 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 LeafLabs LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
+/*
+  TwoWire.cpp - TWI/I2C library for Wiring & Arduino
+  Copyright (c) 2006 Nicholas Zambetti.  All right reserved.
 
-/**
- * @file TwoWire.cpp
- * @author Trystan Jones <crenn6977@gmail.com>
- * @brief Wire library, uses the hardware I2C available in the Maple to
- *        interact with I2C slave devices.
- */
+  This library is free software; you can redistribute it and/or
+  modify it under the terms of the GNU Lesser General Public
+  License as published by the Free Software Foundation; either
+  version 2.1 of the License, or (at your option) any later version.
 
-/*
- * Library created by crenn to use the new WireBase system and allow Arduino
- * users easy interaction with the I2C Hardware in a familiar method.
+  This library is distributed in the hope that it will be useful,
+  but WITHOUT ANY WARRANTY; without even the implied warranty of
+  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+  Lesser General Public License for more details.
+
+  You should have received a copy of the GNU Lesser General Public
+  License along with this library; if not, write to the Free Software
+  Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+
+  Modified 2012 by Todd Krein (todd@krein.org) to implement repeated starts
  */
 
+extern "C" {
+  #include <stdlib.h>
+  #include <string.h>
+  #include <inttypes.h>
+}
+
 #include "Wire_slave.h"
+#include "wirish.h"
+#include <libmaple/i2c_slave.h>
 
-uint8 TwoWire::process(uint8 stop) {
-    int8 res = i2c_master_xfer(sel_hard, &itc_msg, 1, 0);
-    if (res == I2C_ERROR_PROTOCOL) {
-        if (sel_hard->error_flags & I2C_SR1_AF) { /* NACK */
-            res = (sel_hard->error_flags & I2C_SR1_ADDR ? ENACKADDR :
-                                                          ENACKTRNS);
-        } else if (sel_hard->error_flags & I2C_SR1_OVR) { /* Over/Underrun */
-            res = EDATA;
-        } else { /* Bus or Arbitration error */
-            res = EOTHER;
-        }
-        i2c_disable(sel_hard);
-        i2c_master_enable(sel_hard, (I2C_BUS_RESET | dev_flags));
-    }
-    return res;
+#define BUFFER_LENGTH 32
+
+#define MASTER_ADDRESS 0x33
+// Constructors ////////////////////////////////////////////////////////////////
+
+TwoWire::TwoWire(i2c_dev* i2cDevice) :
+  sel_hard(i2cDevice),
+  rxBuffer(nullptr),
+  rxBufferAllocated(0),
+  rxBufferIndex(0),
+  rxBufferLength(0),
+  txBuffer(nullptr),
+  txBufferAllocated(0),
+  txBufferIndex(0),
+  txBufferLength(0),
+  transmitting(false),
+  master(true),
+  dev_flags(0),
+  itc_msg(),
+  itc_slave_msg(),
+  user_onRequest(nullptr),
+  user_onReceive(nullptr) {
 }
 
-uint8 TwoWire::process(){
-	return process(true);
+// Public Methods //////////////////////////////////////////////////////////////
+
+void TwoWire::begin(void) {
+  begin(MASTER_ADDRESS);
 }
 
-// TODO: Add in Error Handling if devsel is out of range for other Maples
-TwoWire::TwoWire(uint8 dev_sel, uint8 flags) {
-    if (dev_sel == 1) {
-        sel_hard = I2C1;
-    } else if (dev_sel == 2) {
-        sel_hard = I2C2;
-    } else {
-        ASSERT(1);
+void TwoWire::begin(uint8_t address){
+
+  rxBufferIndex = 0;
+  rxBufferLength = 0;
+  allocateRxBuffer(BUFFER_LENGTH);
+
+  txBufferIndex = 0;
+  txBufferLength = 0;
+  allocateTxBuffer(BUFFER_LENGTH);
+
+  transmitting = 0;
+
+  master = (address == MASTER_ADDRESS);
+
+  // Set default speed to 100KHz
+  if (master) {
+    dev_flags = 0;
+    i2c_master_enable(sel_hard, dev_flags);
+  } else {
+    // TODO: I2C_SLAVE_DUAL_ADDRESS ?
+    dev_flags =  I2C_SLAVE_GENERAL_CALL | I2C_SLAVE_USE_RX_BUFFER |
+                 I2C_SLAVE_USE_TX_BUFFER;
+
+    itc_slave_msg.addr = address;
+    itc_slave_msg.flags = 0;
+    itc_slave_msg.data = rxBuffer;
+    itc_slave_msg.length = 0;
+    itc_slave_msg.flags = 0;
+
+    // TODO why does enable only work before setting IRS and address?
+    i2c_slave_enable(sel_hard, dev_flags);
+
+    if (sel_hard==I2C1){
+      // attach  receive handler
+      i2c_slave_attach_recv_handler(sel_hard, &itc_slave_msg, onReceiveService1);
+      // attach transmit handler
+      i2c_slave_attach_transmit_handler(sel_hard, &itc_slave_msg, onRequestService1);
+    }
+    #if WIRE_INTERFACES_COUNT > 1
+    else if (sel_hard==I2C2){
+      // attach  receive handler
+      i2c_slave_attach_recv_handler(sel_hard, &itc_slave_msg, onReceiveService2);
+      // attach transmit handler
+      i2c_slave_attach_transmit_handler(sel_hard, &itc_slave_msg, onRequestService2);
     }
-    dev_flags = flags;
+    #endif
+
+    i2c_slave_set_own_address(sel_hard, address);
+  }
 }
 
-TwoWire::~TwoWire() {
-    i2c_disable(sel_hard);
-    sel_hard = 0;
+void TwoWire::begin(int address) {
+  begin((uint8_t) address);
 }
 
-void TwoWire::begin(uint8 self_addr) {
+void TwoWire::end(void) {
+  free(txBuffer);
+  txBuffer = nullptr;
+  txBufferAllocated = 0;
+  free(rxBuffer);
+  rxBuffer = nullptr;
+  rxBufferAllocated = 0;
+  i2c_peripheral_disable(sel_hard);
+  i2c_master_release_bus(sel_hard); // TODO is this required?
+}
+
+void TwoWire::setClock(uint32_t frequencyHz) {
+  switch (frequencyHz) {
+  case 400000:
+    dev_flags |= I2C_FAST_MODE; // set FAST_MODE bit
+    break;
+  case 100000:
+  default:
+    dev_flags &= ~I2C_FAST_MODE; // clear FAST_MODE bit
+    break;
+  }
+  if (sel_hard->regs->CR1 & I2C_CR1_PE){
+    i2c_disable(sel_hard);
     i2c_master_enable(sel_hard, dev_flags);
+  }
 }
 
-void TwoWire::end() {
+uint8 TwoWire::process(bool stop) {
+  int8 res = i2c_master_xfer(sel_hard, &itc_msg, 1, 0);
+
+  if (res == I2C_ERROR_PROTOCOL) {
+    if (sel_hard->error_flags & I2C_SR1_AF) { /* NACK */
+      res = (sel_hard->error_flags & I2C_SR1_ADDR ? ENACKADDR : ENACKTRNS);
+    } else if (sel_hard->error_flags & I2C_SR1_OVR) { /* Over/Underrun */
+      res = EDATA;
+    } else { /* Bus or Arbitration error */
+      res = EOTHER;
+    }
     i2c_disable(sel_hard);
-    sel_hard = 0;
-}
-
-void TwoWire::setClock(uint32_t frequencyHz)
-{
-	switch(frequencyHz)
-	{
-		case 400000:
-			dev_flags |= I2C_FAST_MODE;// set FAST_MODE bit
-			break;
-		case 100000:
-		default:
-			dev_flags &= ~I2C_FAST_MODE;// clear FAST_MODE bit
-			break;
-	}
-	if (sel_hard->regs->CR1 & I2C_CR1_PE){
-	    i2c_disable(sel_hard);
-	    i2c_master_enable(sel_hard, dev_flags);
-	}
-}
-
-TwoWire Wire(1);
+    i2c_master_enable(sel_hard, (I2C_BUS_RESET | dev_flags));
+  }
+
+  return res;
+}
+
+//TODO: Add the ability to queue messages (adding a boolean to end of function
+// call, allows for the Arduino style to stay while also giving the flexibility
+// to bulk send
+uint8 TwoWire::requestFrom(uint8_t address, uint8_t num_bytes,
+    uint32_t iaddress, uint8_t isize, uint8_t sendStop) {
+
+  ASSERT(master);
+
+  allocateRxBuffer(num_bytes);
+  // error if no memory block available to allocate the buffer
+  if (rxBuffer == nullptr) {
+    return EDATA;
+  }
+
+  // reset tx buffer iterator vars
+  rxBufferIndex = 0;
+  rxBufferLength = 0;
+
+  if (num_bytes > BUFFER_LENGTH) {
+    num_bytes = BUFFER_LENGTH;
+  }
+
+  itc_msg.addr = address;
+  itc_msg.flags = I2C_MSG_READ;
+  itc_msg.length = num_bytes;
+  itc_msg.data = &rxBuffer[rxBufferIndex];
+  process(sendStop); // TODO deal with to the return value
+
+  // TODO handle iaddress & isize
+  rxBufferLength += itc_msg.xferred;
+  itc_msg.flags = 0;
+
+  return rxBufferLength;
+}
+
+uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity,
+    uint8_t sendStop) {
+  // TODO shouldn't this set flag |= I2C_MSG_10BIT_ADDR ???
+  return requestFrom((uint8_t) address, (uint8_t) quantity, (uint32_t) 0,
+      (uint8_t) 0, sendStop);
+}
+
+uint8_t TwoWire::requestFrom(uint8_t address, uint8_t quantity) {
+  return requestFrom((uint8_t) address, (uint8_t) quantity, (uint32_t) 0,
+      (uint8_t) 0, (uint8_t) true);
+}
+
+uint8_t TwoWire::requestFrom(int address, int quantity) {
+  return requestFrom((uint8_t) address, (uint8_t) quantity, (uint32_t) 0,
+      (uint8_t) 0, (uint8_t) true);
+}
+
+uint8_t TwoWire::requestFrom(int address, int quantity,
+    int sendStop) {
+  return requestFrom((uint8_t) address, (uint8_t) quantity, (uint32_t) 0,
+      (uint8_t) 0, (bool) sendStop);
+}
+
+void TwoWire::beginTransmission(uint8_t address) {
+
+  // indicate that we are transmitting
+  transmitting = 1;
+
+  // reset tx buffer iterator vars
+  txBufferIndex = 0;
+  txBufferLength = 0;
+
+  itc_msg.addr = address;
+  itc_msg.data = &txBuffer[txBufferIndex];
+  itc_msg.length = 0;
+  itc_msg.flags = 0;
+
+}
+
+void TwoWire::beginTransmission(int address) {
+  beginTransmission((uint8_t) address);
+}
+
+//
+//	Originally, 'endTransmission' was an f(void) function.
+//	It has been modified to take one parameter indicating
+//	whether or not a STOP should be performed on the bus.
+//	Calling endTransmission(false) allows a sketch to
+//	perform a repeated start.
+//
+//	WARNING: Nothing in the library keeps track of whether
+//	the bus tenure has been properly ended with a STOP. It
+//	is very possible to leave the bus in a hung state if
+//	no call to endTransmission(true) is made. Some I2C
+//	devices will behave oddly if they do not see a STOP.
+//
+uint8_t TwoWire::endTransmission(uint8_t sendStop) {
+  //UNUSED(sendStop);
+  int8_t ret = 4;
+
+  if (master == true) {
+
+    itc_msg.data = txBuffer;
+    itc_msg.length = txBufferLength;
+    itc_msg.flags = 0;
+    ret = process(sendStop); // Changed so that the return value from process is returned by this function see also the return line below
+    txBufferIndex = 0;
+
+    // reset Tx buffer
+    resetTxBuffer(); // TODO why? isn't this just unesssesary?
+
+    // reset tx buffer iterator vars
+    txBufferIndex = 0;
+    txBufferLength = 0;
+
+    // indicate that we are done transmitting
+    transmitting = 0;
+  }
+
+  return ret;
+}
+
+//	This provides backwards compatibility with the original
+//	definition, and expected behaviour, of endTransmission
+//
+
+uint8_t TwoWire::endTransmission(void) {
+  return endTransmission(true);
+}
+
+// must be called in:
+// slave tx event callback
+// or after beginTransmission(address)
+size_t TwoWire::write(uint8_t data) {
+  if (!transmitting && master) {
+    return 0;
+  } else {
+    // in master transmitter mode or slave tx event callback
+    allocateTxBuffer(txBufferLength + 1);
+    // error if no memory block available to allocate the buffer
+    if (txBuffer == nullptr) {
+      setWriteError();
+      return 0;
+    }
+    // put byte in tx buffer
+    txBuffer[txBufferIndex] = data;
+    ++txBufferIndex;
+    // update amount in buffer
+    txBufferLength = txBufferIndex;
+  }
+  return 1;
+}
+
+/**
+ * @brief  This function must be called in slave Tx event callback or after
+ *         beginTransmission() and before endTransmission().
+ * @param  pdata: pointer to the buffer data
+ * @param  quantity: number of bytes to write
+ * @retval number of bytes ready to write.
+ */
+size_t TwoWire::write(const uint8_t *data, size_t quantity) {
+  if (!transmitting && master) {
+    return 0;
+  } else {
+    // in master transmitter mode or slave Tx event callback
+    allocateTxBuffer(txBufferLength + quantity);
+    // error if no memory block available to allocate the buffer
+    if (txBuffer == nullptr) {
+      setWriteError();
+      return 0;
+    }
+    // put bytes in tx buffer
+    memcpy(&(txBuffer[txBufferIndex]), data, quantity);
+    txBufferIndex = txBufferIndex + quantity;
+    // update amount in buffer
+    txBufferLength = txBufferIndex;
+    return quantity;
+  }
+  return 0;
+}
+
+// must be called in:
+// slave rx event callback
+// or after requestFrom(address, numBytes)
+int TwoWire::available(void) {
+  return rxBufferLength - rxBufferIndex;
+}
+
+// must be called in:
+// slave rx event callback
+// or after requestFrom(address, numBytes)
+int TwoWire::read(void) {
+  int value = -1;
+
+  // get each successive byte on each call
+  if (rxBufferIndex < rxBufferLength) {
+    value = rxBuffer[rxBufferIndex];
+    ++rxBufferIndex;
+
+    /* Commented as not I think it is not useful
+     * but kept to show that it is possible to
+     * reset rx buffer when no more data available */
+    /*if(rxBufferIndex == rxBufferLength) {
+     resetRxBuffer();
+     }*/
+  }
+
+  return value;
+}
+
+// must be called in:
+// slave rx event callback
+// or after requestFrom(address, numBytes)
+int TwoWire::peek(void) {
+  int value = -1;
+
+  if (rxBufferIndex < rxBufferLength) {
+    value = rxBuffer[rxBufferIndex];
+  }
+
+  return value;
+}
+
+void TwoWire::flush(void) {
+  rxBufferIndex = 0;
+  rxBufferLength = 0;
+  resetRxBuffer();
+  txBufferIndex = 0;
+  txBufferLength = 0;
+  resetTxBuffer();
+}
+
+// behind the scenes function that is called when data is received
+void __attribute__((always_inline)) TwoWire::onReceiveService(i2c_msg* msg) {
+  // don't bother if user hasn't registered a callback
+  if (!user_onReceive) {
+    return;
+  }
+
+  // don't bother if rx buffer is in use by a master requestFrom() op
+  // i know this drops data, but it allows for slight stupidity
+  // meaning, they may not have read all the master requestFrom() data yet
+  if (rxBufferIndex < rxBufferLength) {
+    return;
+  }
+  // copy twi rx buffer into local read buffer
+  // this enables new reads to happen in parallel
+  //
+  // TODO: Something is strange here, isn't msg->data==rxBuffer? nope, itsnot
+  //
+  memcpy(rxBuffer, msg->data, msg->length);
+  // set rx iterator vars
+  rxBufferIndex = 0;
+  rxBufferLength = msg->length;
+  // alert user program
+  user_onReceive(msg->length);
+}
+
+// behind the scenes function that is called when data is requested
+void __attribute__((always_inline)) TwoWire::onRequestService(i2c_msg* msg) {
+  // don't bother if user hasn't registered a callback
+  if (!user_onRequest) {
+    return;
+  }
+
+  // reset tx buffer iterator vars
+  // !!! this will kill any pending pre-master sendTo() activity
+  txBufferIndex = 0;
+  txBufferLength = 0;
+  // alert user program
+  user_onRequest();
+
+  // update i2c_msg
+  msg->data = txBuffer;
+  msg->length = txBufferLength;
+  msg->xferred = 0;
+}
+
+// sets function called on slave write
+void TwoWire::onReceive(void (*function)(int)) {
+  user_onReceive = function;
+}
+
+// sets function called on slave read
+void TwoWire::onRequest(void (*function)(void)) {
+  user_onRequest = function;
+}
+
+/**
+ * @brief  Allocate the Rx/Tx buffer to the requested length if needed
+ * @note   Minimum allocated size is BUFFER_LENGTH)
+ * @param  length: number of bytes to allocate
+ */
+inline void TwoWire::allocateRxBuffer(size_t length) {
+  // By default we allocate BUFFER_LENGTH bytes. It is the min size of the buffer.
+  if (length < BUFFER_LENGTH) {
+    length = BUFFER_LENGTH;
+  }
+  if (rxBufferAllocated < length) {
+    rxBuffer = (uint8_t *) realloc(rxBuffer, length * sizeof(uint8_t));
+    rxBufferAllocated = (rxBuffer != nullptr) ? length : 0;
+  }
+}
+
+inline void TwoWire::allocateTxBuffer(size_t length) {
+  // By default we allocate BUFFER_LENGTH bytes. It is the min size of the buffer.
+  if (length < BUFFER_LENGTH) {
+    length = BUFFER_LENGTH;
+  }
+  if (txBufferAllocated < length) {
+    txBuffer = (uint8_t *) realloc(txBuffer, length * sizeof(uint8_t));
+    txBufferAllocated = (txBuffer != nullptr) ? length : 0;
+  }
+}
+
+/**
+ * @brief  Reset Rx/Tx buffer content to 0
+ */
+inline void TwoWire::resetRxBuffer(void) {
+  if (rxBuffer != nullptr)
+    memset(rxBuffer, 0, rxBufferAllocated);
+}
+
+inline void TwoWire::resetTxBuffer(void) {
+  if (txBuffer != nullptr)
+    memset(txBuffer, 0, txBufferAllocated);
+}
+
+
+// Preinstantiate Objects //////////////////////////////////////////////////////
+TwoWire& Wire = TwoWire::getInstance(); //SCL:D14 SDA:D15
+#if WIRE_INTERFACES_COUNT > 1
+TwoWire& Wire1 = TwoWire::getInstance1(); //SCL: D1 SDA: D0
+#endif
+
+// Static methods //////////////////////////////////////////////////////////////
+
+TwoWire& TwoWire::getInstance(){
+  static TwoWire instance(I2C1);
+  return instance;
+}
+
+#if WIRE_INTERFACES_COUNT > 1
+TwoWire& TwoWire::getInstance1(){
+  static TwoWire instance(I2C2);
+  return instance;
+}
+#endif
+
+// onRequestServiceX and onReceiveServiceX can't be inline since they
+// are exclusively called via a function pointer
+void TwoWire::onRequestService1(i2c_msg* msg) {
+  Wire.onRequestService(msg);
+}
+
+void TwoWire::onReceiveService1(i2c_msg* msg) {
+  Wire.onReceiveService(msg);
+}
+
+#if WIRE_INTERFACES_COUNT > 1
+void TwoWire::onRequestService2(i2c_msg* msg) {
+  Wire1.onRequestService(msg);
+}
+void TwoWire::onReceiveService2(i2c_msg* msg) {
+  Wire1.onReceiveService(msg);
+}
+#endif
diff --git a/STM32F1/libraries/WireSlave/src/Wire_slave.h b/STM32F1/libraries/WireSlave/src/Wire_slave.h
index dbe2a4ea5..ff71228c6 100644
--- a/STM32F1/libraries/WireSlave/src/Wire_slave.h
+++ b/STM32F1/libraries/WireSlave/src/Wire_slave.h
@@ -1,78 +1,149 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 LeafLabs LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file Wire.h
- * @author Trystan Jones <crenn6977@gmail.com>
- * @brief Wire library, uses the hardware I2C available in the Maple to
- *        interact with I2C slave devices.
- */
-
 /*
- * Library created by crenn to use the new WireBase system and allow Arduino
- * users easy interaction with the I2C Hardware in a familiar method.
+ TwoWire.h - TWI/I2C library for Arduino & Wiring
+ Copyright (c) 2006 Nicholas Zambetti.  All right reserved.
+
+ This library is free software; you can redistribute it and/or
+ modify it under the terms of the GNU Lesser General Public
+ License as published by the Free Software Foundation; either
+ version 2.1 of the License, or (at your option) any later version.
+
+ This library is distributed in the hope that it will be useful,
+ but WITHOUT ANY WARRANTY; without even the implied warranty of
+ MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
+ Lesser General Public License for more details.
+
+ You should have received a copy of the GNU Lesser General Public
+ License along with this library; if not, write to the Free Software
+ Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301  USA
+
+ Modified 2012 by Todd Krein (todd@krein.org) to implement repeated starts
  */
 
-#ifndef _TWOWIRE_H_
-#define _TWOWIRE_H_
+#ifndef TwoWire_h
+#define TwoWire_h
 
-#include "utility/WireBase_slave.h"
-#include "wirish.h"
+#include <inttypes.h>
+#include "Stream.h"
+#include "Arduino.h"
 #include <libmaple/i2c_slave.h>
 
-class TwoWire : public WireBase {
+
+// WIRE_HAS_END means Wire has end()
+#ifndef WIRE_HAS_END
+#define WIRE_HAS_END 1
+#endif
+
+#ifndef WIRE_INTERFACES_COUNT
+#define WIRE_INTERFACES_COUNT 2
+#endif
+
+/* return codes from endTransmission() */
+typedef enum EndTranmissionCodes {
+  SUCCESS = 0, /* transmission was successful */
+  EDATA = 1, /* too much data */
+  ENACKADDR = 2, /* received nack on transmit of address */
+  ENACKTRNS = 3, /* received nack on transmit of data */
+  EOTHER = 4, /* other error */
+} EndTranmissionCodes;
+
+class TwoWire: public Stream {
 private:
-    i2c_dev* sel_hard;
-    uint8    dev_flags;
-protected:
-    /*
-     * Processes the incoming I2C message defined by WireBase to the
-     * hardware. If an error occured, restart the I2C device.
-     */
-    uint8 process(uint8);
-    uint8 process();
+  i2c_dev* sel_hard;
+
+  uint8_t *rxBuffer;  // lazy allocation
+  uint8_t rxBufferAllocated;
+  uint8_t rxBufferIndex;
+  uint8_t rxBufferLength;
+
+  uint8_t *txBuffer; // lazy allocation
+  uint8_t txBufferAllocated;
+  uint8_t txBufferIndex;
+  uint8_t txBufferLength;
+
+  uint8_t transmitting;
+
+  bool master;
+
+  uint8 dev_flags;
+  i2c_msg itc_msg;
+  i2c_msg itc_slave_msg;
+
+  void (*user_onRequest)(void);
+  void (*user_onReceive)(int);
+
+  void allocateRxBuffer(size_t length);
+  void allocateTxBuffer(size_t length);
+
+  void resetRxBuffer(void);
+  void resetTxBuffer(void);
+  uint8 process(bool stop = true); // wrapper for i2c_master_xfer
+
+  inline void __attribute__((always_inline)) onReceiveService(i2c_msg* msg);
+  inline void __attribute__((always_inline)) onRequestService(i2c_msg* msg);
+
+  static void onRequestService1(i2c_msg*);
+  static void onReceiveService1(i2c_msg*);
+  #if WIRE_INTERFACES_COUNT > 1
+  static void onRequestService2(i2c_msg*);
+  static void onReceiveService2(i2c_msg*);
+  #endif
+
+  TwoWire(i2c_dev* i2cDevice);
+  TwoWire() = delete;
+  TwoWire(const TwoWire&) = delete;
+  TwoWire& operator=(const TwoWire&) = delete;
+  TwoWire(TwoWire&&) = delete;
+  TwoWire& operator=(TwoWire&&) = delete;
+
 public:
-    /*
-     * Check if devsel is within range and enable selected I2C interface with
-     * passed flags
-     */
-    TwoWire(uint8, uint8 = 0);
-
-	/*
-	 * Shuts down (disables) the hardware I2C
-	 */
-	void end();
-
-	void setClock(uint32_t frequencyHz);
-    /*
-     * Disables the I2C device and remove the device address.
-     */
-    ~TwoWire();
-
-    void begin(uint8 = 0x00);
+  static TwoWire& getInstance();
+  #if WIRE_INTERFACES_COUNT > 1
+  static TwoWire& getInstance1();
+  #endif
+
+  void begin();
+  void begin(uint8_t);
+  void begin(int);
+  void end();
+  void setClock(uint32_t);
+  void beginTransmission(uint8_t);
+  void beginTransmission(int);
+  uint8_t endTransmission(void);
+  uint8_t endTransmission(uint8_t);
+
+  uint8_t requestFrom(uint8_t, uint8_t);
+  uint8_t requestFrom(uint8_t, uint8_t, uint8_t);
+  uint8_t requestFrom(uint8_t, uint8_t, uint32_t, uint8_t, uint8_t);
+  uint8_t requestFrom(int, int);
+  uint8_t requestFrom(int, int, int);
+
+  virtual size_t write(uint8_t);
+  virtual size_t write(const uint8_t *, size_t);
+  virtual int available(void);
+  virtual int read(void);
+  virtual int peek(void);
+  virtual void flush(void);
+  void onReceive(void (*)(int));
+  void onRequest(void (*)(void));
+
+  inline size_t write(unsigned long n) {
+    return write((uint8_t) n);
+  }
+  inline size_t write(long n) {
+    return write((uint8_t) n);
+  }
+  inline size_t write(unsigned int n) {
+    return write((uint8_t) n);
+  }
+  inline size_t write(int n) {
+    return write((uint8_t) n);
+  }
+  using Print::write;
 };
-extern TwoWire Wire;
-#endif // _TWOWIRE_H_
+
+extern TwoWire& Wire;
+#if WIRE_INTERFACES_COUNT > 1
+extern TwoWire& Wire1;
+#endif
+
+#endif // TwoWire_h
diff --git a/STM32F1/libraries/WireSlave/src/Wire_slave.h.gch b/STM32F1/libraries/WireSlave/src/Wire_slave.h.gch
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zBdS;CcUPrE!#|r-!^LUH_HewijUo<W!6fa=GfNm%v92;f@<xUEE<FpoOCA}>3+mOY
zeqCB0)479K_!-EoQU(cb#y~TiApC*402!K1p!lq-sA|dq;6V1KP^JXHr4pi+PvP;w
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zvqgC<q8$9qQ39dB2f9(3=I8@IM;|FasHPe<K{g846jG;Hi*Da*uDCgCK_3URN;TV7
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z{MCA~>~`p7GIglFE5gw6x<p2f@8W%mFH~vNbly}nFboZQqhoKebv@VIG0vX$lk|Pr
zn-rE0MqsPgMTPmOi5Z*jgpnmemFVh|+6HP8R0cD`ymm}eH@P07(Xb5?O=G%4yj2qF
zEf>cHl2bkI)!b4cNl#H}90#?ypaYm5=-(cw2)bU-KV+CM!!iB@(II47<xRd@`)Lm5
zh&H(@dZcAE3f>we^-un12}X;mVA?9X-J?fE;#_TvhLAtlaw_k)D7x_*hEYvbM);PK
Y;dI<1)bAmJrq!61Ti)JEJwtc@2OMIdI{*Lx

literal 0
HcmV?d00001

diff --git a/STM32F1/libraries/WireSlave/src/i2c_slave.c b/STM32F1/libraries/WireSlave/src/i2c_slave.c
index 865949b36..82ade9a4b 100644
--- a/STM32F1/libraries/WireSlave/src/i2c_slave.c
+++ b/STM32F1/libraries/WireSlave/src/i2c_slave.c
@@ -158,6 +158,7 @@ void i2c_bus_reset(const i2c_dev *dev) {
  * @param dev Device to initialize.
  */
 void i2c_init(i2c_dev *dev) {
+
     rcc_reset_dev(dev->clk_id);
     rcc_clk_enable(dev->clk_id);
     _i2c_irq_priority_fixup(dev);
@@ -197,8 +198,10 @@ void i2c_master_enable(i2c_dev *dev, uint32 flags) {
     i2c_init(dev);
     i2c_config_gpios(dev);
 
-    /* Configure clock and rise time */
-    set_ccr_trise(dev, flags);
+    /* Configure clock and rise time, but only if in master mode */
+    if (!(flags & (I2C_SLAVE_DUAL_ADDRESS|I2C_SLAVE_GENERAL_CALL))) {
+        set_ccr_trise(dev, flags);
+    }
 
     /* Enable event and buffer interrupts */
     nvic_irq_enable(dev->ev_nvic_line);
@@ -245,8 +248,9 @@ void i2c_master_enable(i2c_dev *dev, uint32 flags) {
  *                                       Callback will be called before tx
  */
 void i2c_slave_enable(i2c_dev *dev, uint32 flags) {
+    // TODO: Figure out why i2c_disable(I2C2) causes a crash when I2C1 is enabled
     i2c_disable(dev);
-    i2c_master_enable(dev, dev->config_flags | flags);
+    i2c_master_enable(dev, flags);
 }
 
 /**
@@ -329,7 +333,8 @@ static inline int32 wait_for_state_change(i2c_dev *dev,
  */
 
 /*
- * IRQ handler for I2C master. Handles transmission/reception.
+ * IRQ handler for I2C master and slave.
+ * Handles transmission/reception.
  */
 void _i2c_irq_handler(i2c_dev *dev) {
     /* WTFs:
@@ -676,7 +681,7 @@ void _i2c_irq_error_handler(i2c_dev *dev) {
                                          I2C_SR1_OVR);
 
     /* Are we in slave mode? */
-    if ((dev->regs->SR2 & I2C_SR2_MSL) != I2C_SR2_MSL) {
+    if (dev->config_flags & (I2C_SLAVE_DUAL_ADDRESS|I2C_SLAVE_GENERAL_CALL)) {
         /* Check to see if the master device did a NAK on the last bit
          * This is perfectly valid for a master to do this on the bus.
          * We ignore this. Any further error processing takes us into dead
diff --git a/STM32F1/libraries/WireSlave/src/utility/WireBase_slave.cpp b/STM32F1/libraries/WireSlave/src/utility/WireBase_slave.cpp
deleted file mode 100644
index a30921179..000000000
--- a/STM32F1/libraries/WireSlave/src/utility/WireBase_slave.cpp
+++ /dev/null
@@ -1,145 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 LeafLabs LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file WireBase.cpp
- * @author Trystan Jones <crenn6977@gmail.com>
- * @brief Wire library, following the majority of the interface from Arduino.
- *        Provides a 'standard' interface to I2C (two-wire) communication for
- *        derived classes.
- */
-
-/*
- * Library created by crenn to allow a system which would provide users the
- * 'standardised' Arduino method for interfacing with I2C devices regardless of
- * whether it is I2C hardware or emulating software.
- */
-
-#include "WireBase_slave.h"
-#include "wirish.h"
-
-void WireBase::begin(uint8 self_addr) {
-    tx_buf_idx = 0;
-    tx_buf_overflow = false;
-    rx_buf_idx = 0;
-    rx_buf_len = 0;
-}
-
-void WireBase::beginTransmission(uint8 slave_address) {
-    itc_msg.addr = slave_address;
-    itc_msg.data = &tx_buf[tx_buf_idx];
-    itc_msg.length = 0;
-    itc_msg.flags = 0;
-}
-
-void WireBase::beginTransmission(int slave_address) {
-    beginTransmission((uint8)slave_address);
-}
-
-uint8 WireBase::endTransmission(bool stop) {
-    uint8 retVal;
-    if (tx_buf_overflow) {
-        return EDATA;
-    }
-    retVal = process(stop);// Changed so that the return value from process is returned by this function see also the return line below
-    tx_buf_idx = 0;
-    tx_buf_overflow = false;
-    return retVal;//SUCCESS;
-}
-
-uint8 WireBase::endTransmission(){
-    endTransmission(true);
-}
-
-//TODO: Add the ability to queue messages (adding a boolean to end of function
-// call, allows for the Arduino style to stay while also giving the flexibility
-// to bulk send
-uint8 WireBase::requestFrom(uint8 address, int num_bytes) {
-    if (num_bytes > BUFFER_LENGTH) {
-        num_bytes = BUFFER_LENGTH;
-    }
-    itc_msg.addr = address;
-    itc_msg.flags = I2C_MSG_READ;
-    itc_msg.length = num_bytes;
-    itc_msg.data = &rx_buf[rx_buf_idx];
-    process();
-    rx_buf_len += itc_msg.xferred;
-    itc_msg.flags = 0;
-    return rx_buf_len;
-}
-
-uint8 WireBase::requestFrom(int address, int numBytes) {
-    return WireBase::requestFrom((uint8)address, numBytes);
-}
-
-void WireBase::write(uint8 value) {
-    if (tx_buf_idx == BUFFER_LENGTH) {
-        tx_buf_overflow = true;
-        return;
-    }
-    tx_buf[tx_buf_idx++] = value;
-    itc_msg.length++;
-}
-
-void WireBase::write(uint8* buf, int len) {
-    for (uint8 i = 0; i < len; i++) {
-        write(buf[i]);
-    }
-}
-
-void WireBase::write(int value) {
-    write((uint8)value);
-}
-
-void WireBase::write(int* buf, int len) {
-    write((uint8*)buf, (uint8)len);
-}
-
-void WireBase::write(char* buf) {
-    uint8 *ptr = (uint8*)buf;
-    while (*ptr) {
-        write(*ptr);
-        ptr++;
-    }
-}
-
-uint8 WireBase::available() {
-    return rx_buf_len - rx_buf_idx;
-}
-
-uint8 WireBase::read() {
-    if (rx_buf_idx == rx_buf_len) {
-        rx_buf_idx = 0;
-        rx_buf_len = 0;
-        return 0;
-    } else if (rx_buf_idx == (rx_buf_len-1)) {
-        uint8 temp = rx_buf[rx_buf_idx];
-        rx_buf_idx = 0;
-        rx_buf_len = 0;
-        return temp;
-    }
-    return rx_buf[rx_buf_idx++];
-}
diff --git a/STM32F1/libraries/WireSlave/src/utility/WireBase_slave.h b/STM32F1/libraries/WireSlave/src/utility/WireBase_slave.h
deleted file mode 100644
index 31f3f8cee..000000000
--- a/STM32F1/libraries/WireSlave/src/utility/WireBase_slave.h
+++ /dev/null
@@ -1,145 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 LeafLabs LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file WireBase.h
- * @author Trystan Jones <crenn6977@gmail.com>
- * @brief Wire library, following the majority of the interface from Arduino.
- *        Provides a 'standard' interface to I2C (two-wire) communication for
- *        derived classes.
- */
-
-/*
- * Library created by crenn to allow a system which would provide users the
- * 'standardised' Arduino method for interfacing with I2C devices regardless of
- * whether it is I2C hardware or emulating software.
- */
-
-#ifndef _WIREBASE_H_
-#define _WIREBASE_H_
-
-#include "wirish.h"
-#include <libmaple/i2c_slave.h>
-
-#define BUFFER_LENGTH 32
-
-/* return codes from endTransmission() */
-#define SUCCESS   0        /* transmission was successful */
-#define EDATA     1        /* too much data */
-#define ENACKADDR 2        /* received nack on transmit of address */
-#define ENACKTRNS 3        /* received nack on transmit of data */
-#define EOTHER    4        /* other error */
-
-class WireBase { // Abstraction is awesome!
-protected:
-    i2c_msg itc_msg;
-    uint8 rx_buf[BUFFER_LENGTH];      /* receive buffer */
-    uint8 rx_buf_idx;               /* first unread idx in rx_buf */
-    uint8 rx_buf_len;               /* number of bytes read */
-
-    uint8 tx_buf[BUFFER_LENGTH];      /* transmit buffer */
-    uint8 tx_buf_idx;  // next idx available in tx_buf, -1 overflow
-    boolean tx_buf_overflow;
-
-    // Force derived classes to define process function
-    virtual uint8 process(uint8) = 0;
-    virtual uint8 process() = 0;
-public:
-    WireBase() {}
-    ~WireBase() {}
-
-    /*
-     * Initialises the class interface
-     */
-    // Allow derived classes to overwrite begin function
-    virtual void begin(uint8 = 0x00);
-
-    /*
-     * Sets up the transmission message to be processed
-     */
-    void beginTransmission(uint8);
-
-    /*
-     * Allow only 8 bit addresses to be used
-     */
-    void beginTransmission(int);
-
-    /*
-     * Call the process function to process the message if the TX
-     * buffer has not overflowed.
-     */
-    uint8 endTransmission(bool);
-    uint8 endTransmission(void);
-
-    /*
-     * Request bytes from a slave device and process the request,
-     * storing into the receiving buffer.
-     */
-    uint8 requestFrom(uint8, int);
-
-    /*
-     * Allow only 8 bit addresses to be used when requesting bytes
-     */
-    uint8 requestFrom(int, int);
-
-    /*
-     * Stack up bytes to be sent when transmitting
-     */
-    void write(uint8);
-
-    /*
-     * Stack up bytes from the array to be sent when transmitting
-     */
-    void write(uint8*, int);
-
-    /*
-     * Ensure that a sending data will only be 8-bit bytes
-     */
-    void write(int);
-
-    /*
-     * Ensure that an array sending data will only be 8-bit bytes
-     */
-    void write(int*, int);
-
-    /*
-     * Stack up bytes from a string to be sent when transmitting
-     */
-    void write(char*);
-
-    /*
-     * Return the amount of bytes that is currently in the receiving buffer
-     */
-    uint8 available();
-
-    /*
-     * Return the value of byte in the receiving buffer that is currently being
-     * pointed to
-     */
-    uint8 read();
-};
-
-#endif // _WIREBASE_H_

From 4ad4de080fd87bcdb0f176959bd74c8293ecc3e3 Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Fri, 22 Dec 2017 20:04:24 +0100
Subject: [PATCH 280/307] Saved some 50K flash memory by modifying the
 singleton implementation

---
 STM32F1/libraries/WireSlave/src/Wire_slave.cpp | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/STM32F1/libraries/WireSlave/src/Wire_slave.cpp b/STM32F1/libraries/WireSlave/src/Wire_slave.cpp
index 75e753f5c..2cdb1570c 100644
--- a/STM32F1/libraries/WireSlave/src/Wire_slave.cpp
+++ b/STM32F1/libraries/WireSlave/src/Wire_slave.cpp
@@ -492,14 +492,20 @@ TwoWire& Wire1 = TwoWire::getInstance1(); //SCL: D1 SDA: D0
 // Static methods //////////////////////////////////////////////////////////////
 
 TwoWire& TwoWire::getInstance(){
-  static TwoWire instance(I2C1);
-  return instance;
+  static TwoWire* instance = nullptr;
+  if (!instance) {
+    instance = new TwoWire(I2C1);
+  }
+  return *instance;
 }
 
 #if WIRE_INTERFACES_COUNT > 1
 TwoWire& TwoWire::getInstance1(){
-  static TwoWire instance(I2C2);
-  return instance;
+  static TwoWire* instance = nullptr;
+  if (!instance) {
+    instance = new TwoWire(I2C2);
+  }
+  return *instance;
 }
 #endif
 

From 01c23b6a5828607734f872ddf5861f5df2797175 Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Fri, 22 Dec 2017 20:33:00 +0100
Subject: [PATCH 281/307] Changed type of transmitting to bool (from uint8_t)

---
 STM32F1/libraries/WireSlave/src/Wire_slave.cpp | 6 +++---
 STM32F1/libraries/WireSlave/src/Wire_slave.h   | 2 +-
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/STM32F1/libraries/WireSlave/src/Wire_slave.cpp b/STM32F1/libraries/WireSlave/src/Wire_slave.cpp
index 2cdb1570c..9bb989718 100644
--- a/STM32F1/libraries/WireSlave/src/Wire_slave.cpp
+++ b/STM32F1/libraries/WireSlave/src/Wire_slave.cpp
@@ -69,7 +69,7 @@ void TwoWire::begin(uint8_t address){
   txBufferLength = 0;
   allocateTxBuffer(BUFFER_LENGTH);
 
-  transmitting = 0;
+  transmitting = false;
 
   master = (address == MASTER_ADDRESS);
 
@@ -220,7 +220,7 @@ uint8_t TwoWire::requestFrom(int address, int quantity,
 void TwoWire::beginTransmission(uint8_t address) {
 
   // indicate that we are transmitting
-  transmitting = 1;
+  transmitting = true;
 
   // reset tx buffer iterator vars
   txBufferIndex = 0;
@@ -270,7 +270,7 @@ uint8_t TwoWire::endTransmission(uint8_t sendStop) {
     txBufferLength = 0;
 
     // indicate that we are done transmitting
-    transmitting = 0;
+    transmitting = false;
   }
 
   return ret;
diff --git a/STM32F1/libraries/WireSlave/src/Wire_slave.h b/STM32F1/libraries/WireSlave/src/Wire_slave.h
index ff71228c6..131acebb8 100644
--- a/STM32F1/libraries/WireSlave/src/Wire_slave.h
+++ b/STM32F1/libraries/WireSlave/src/Wire_slave.h
@@ -60,7 +60,7 @@ class TwoWire: public Stream {
   uint8_t txBufferIndex;
   uint8_t txBufferLength;
 
-  uint8_t transmitting;
+  bool transmitting;
 
   bool master;
 

From b9dbeb69d9dee7330435af9b5e30e99be6423265 Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Fri, 29 Dec 2017 12:04:29 +0100
Subject: [PATCH 282/307] Fixed minor example issues

---
 .../i2c_libmaple_slave_reader/i2c_libmaple_slave_reader.ino     | 2 +-
 .../WireSlave/examples/slave_receiver/slave_receiver.ino        | 1 -
 2 files changed, 1 insertion(+), 2 deletions(-)

diff --git a/STM32F1/libraries/WireSlave/examples/i2c_libmaple_slave_reader/i2c_libmaple_slave_reader.ino b/STM32F1/libraries/WireSlave/examples/i2c_libmaple_slave_reader/i2c_libmaple_slave_reader.ino
index a63ff3c98..fd059c121 100644
--- a/STM32F1/libraries/WireSlave/examples/i2c_libmaple_slave_reader/i2c_libmaple_slave_reader.ino
+++ b/STM32F1/libraries/WireSlave/examples/i2c_libmaple_slave_reader/i2c_libmaple_slave_reader.ino
@@ -53,7 +53,7 @@ void functx(i2c_msg *msg){
 
 void setup() {
   Serial.begin(115200);
-  Serial.println("I2C Slave example");
+  Serial.println("libmaple I2C slave reader example");
 
   // attach the buffer
   msg.data = buffer;
diff --git a/STM32F1/libraries/WireSlave/examples/slave_receiver/slave_receiver.ino b/STM32F1/libraries/WireSlave/examples/slave_receiver/slave_receiver.ino
index 5d71b9a20..bf9f255f8 100644
--- a/STM32F1/libraries/WireSlave/examples/slave_receiver/slave_receiver.ino
+++ b/STM32F1/libraries/WireSlave/examples/slave_receiver/slave_receiver.ino
@@ -11,7 +11,6 @@
 
 
 #include <Wire_slave.h>
-#define Serial Serial1
 
 void setup(){
   Serial.begin(115200);         // start serial for output

From 4e820c3649fbe4238bdef67dad393967a76b6873 Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Fri, 29 Dec 2017 12:13:17 +0100
Subject: [PATCH 283/307] Full method signatures in header file. <pet peeve> I
 don't understand why anyone wants to remove useful API information from the
 header file. CPP files describes implementation details, header files
 describes the API. </pet peeve>

---
 STM32F1/libraries/WireSlave/src/Wire_slave.h | 50 ++++++++++----------
 1 file changed, 26 insertions(+), 24 deletions(-)

diff --git a/STM32F1/libraries/WireSlave/src/Wire_slave.h b/STM32F1/libraries/WireSlave/src/Wire_slave.h
index 131acebb8..a99ab412e 100644
--- a/STM32F1/libraries/WireSlave/src/Wire_slave.h
+++ b/STM32F1/libraries/WireSlave/src/Wire_slave.h
@@ -69,7 +69,7 @@ class TwoWire: public Stream {
   i2c_msg itc_slave_msg;
 
   void (*user_onRequest)(void);
-  void (*user_onReceive)(int);
+  void (*user_onReceive)(int quantity);
 
   void allocateRxBuffer(size_t length);
   void allocateTxBuffer(size_t length);
@@ -96,47 +96,49 @@ class TwoWire: public Stream {
   TwoWire& operator=(TwoWire&&) = delete;
 
 public:
+  // return the 'Wire' instance (using I2C1)
   static TwoWire& getInstance();
   #if WIRE_INTERFACES_COUNT > 1
+  // return the 'Wire1' instance (using I2C2)
   static TwoWire& getInstance1();
   #endif
 
-  void begin();
-  void begin(uint8_t);
-  void begin(int);
+  void begin(); // master mode
+  void begin(uint8_t myAddress); //slave mode
+  void begin(int myAddress); //slave mode
   void end();
-  void setClock(uint32_t);
-  void beginTransmission(uint8_t);
-  void beginTransmission(int);
+  void setClock(uint32_t frequencyHz);
+  void beginTransmission(uint8_t slaveAddress);
+  void beginTransmission(int slaveAddress);
   uint8_t endTransmission(void);
-  uint8_t endTransmission(uint8_t);
+  uint8_t endTransmission(uint8_t sendStop);
 
-  uint8_t requestFrom(uint8_t, uint8_t);
-  uint8_t requestFrom(uint8_t, uint8_t, uint8_t);
-  uint8_t requestFrom(uint8_t, uint8_t, uint32_t, uint8_t, uint8_t);
-  uint8_t requestFrom(int, int);
-  uint8_t requestFrom(int, int, int);
+  uint8_t requestFrom(uint8_t slaveAddress, uint8_t quantity);
+  uint8_t requestFrom(uint8_t slaveAddress, uint8_t quantity, uint8_t sendStop);
+  uint8_t requestFrom(uint8_t slaveAddress, uint8_t num_bytes, uint32_t iaddress, uint8_t isize, uint8_t sendStop);
+  uint8_t requestFrom(int slaveAddress, int quantity);
+  uint8_t requestFrom(int slaveAddress, int quantity, int sendStop);
 
-  virtual size_t write(uint8_t);
-  virtual size_t write(const uint8_t *, size_t);
+  virtual size_t write(uint8_t data);
+  virtual size_t write(const uint8_t *data, size_t quantity);
   virtual int available(void);
   virtual int read(void);
   virtual int peek(void);
   virtual void flush(void);
-  void onReceive(void (*)(int));
+  void onReceive(void (*)(int quantity));
   void onRequest(void (*)(void));
 
-  inline size_t write(unsigned long n) {
-    return write((uint8_t) n);
+  inline size_t write(unsigned long data) {
+    return write((uint8_t) data);
   }
-  inline size_t write(long n) {
-    return write((uint8_t) n);
+  inline size_t write(long data) {
+    return write((uint8_t) data);
   }
-  inline size_t write(unsigned int n) {
-    return write((uint8_t) n);
+  inline size_t write(unsigned int data) {
+    return write((uint8_t) data);
   }
-  inline size_t write(int n) {
-    return write((uint8_t) n);
+  inline size_t write(int data) {
+    return write((uint8_t) data);
   }
   using Print::write;
 };

From daf62cafcaf044836945a6d6553180b8da00e927 Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Fri, 29 Dec 2017 12:15:26 +0100
Subject: [PATCH 284/307] Removed a redundant buffer constraint

---
 STM32F1/libraries/WireSlave/src/Wire_slave.cpp | 7 +------
 1 file changed, 1 insertion(+), 6 deletions(-)

diff --git a/STM32F1/libraries/WireSlave/src/Wire_slave.cpp b/STM32F1/libraries/WireSlave/src/Wire_slave.cpp
index 9bb989718..5fb84f5ba 100644
--- a/STM32F1/libraries/WireSlave/src/Wire_slave.cpp
+++ b/STM32F1/libraries/WireSlave/src/Wire_slave.cpp
@@ -177,10 +177,6 @@ uint8 TwoWire::requestFrom(uint8_t address, uint8_t num_bytes,
   rxBufferIndex = 0;
   rxBufferLength = 0;
 
-  if (num_bytes > BUFFER_LENGTH) {
-    num_bytes = BUFFER_LENGTH;
-  }
-
   itc_msg.addr = address;
   itc_msg.flags = I2C_MSG_READ;
   itc_msg.length = num_bytes;
@@ -211,8 +207,7 @@ uint8_t TwoWire::requestFrom(int address, int quantity) {
       (uint8_t) 0, (uint8_t) true);
 }
 
-uint8_t TwoWire::requestFrom(int address, int quantity,
-    int sendStop) {
+uint8_t TwoWire::requestFrom(int address, int quantity, int sendStop) {
   return requestFrom((uint8_t) address, (uint8_t) quantity, (uint32_t) 0,
       (uint8_t) 0, (bool) sendStop);
 }

From 2b6e1398847561b5604b397c245b01535e1168a3 Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Fri, 1 Dec 2017 11:43:42 +0100
Subject: [PATCH 285/307] According to STM32F103 RM0008: TIMx_CCMR1::CC2S=01 ->
 channel is configured as input, IC2 is mapped on TI2.

---
 STM32F1/system/libmaple/include/libmaple/timer.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/STM32F1/system/libmaple/include/libmaple/timer.h b/STM32F1/system/libmaple/include/libmaple/timer.h
index 2c83e5e81..ea7484e71 100644
--- a/STM32F1/system/libmaple/include/libmaple/timer.h
+++ b/STM32F1/system/libmaple/include/libmaple/timer.h
@@ -394,8 +394,8 @@ extern timer_dev timer14;
 #define TIMER_CCMR1_IC2PSC              (0x3 << 10)
 #define TIMER_CCMR1_CC2S                (0x3 << 8)
 #define TIMER_CCMR1_CC2S_OUTPUT         (TIMER_CCMR_CCS_OUTPUT << 8)
-#define TIMER_CCMR1_CC2S_INPUT_TI1      (TIMER_CCMR_CCS_INPUT_TI1 << 8)
-#define TIMER_CCMR1_CC2S_INPUT_TI2      (TIMER_CCMR_CCS_INPUT_TI2 << 8)
+#define TIMER_CCMR1_CC2S_INPUT_TI1      (TIMER_CCMR_CCS_INPUT_TI2 << 8)
+#define TIMER_CCMR1_CC2S_INPUT_TI2      (TIMER_CCMR_CCS_INPUT_TI1 << 8)
 #define TIMER_CCMR1_CC2S_INPUT_TRC      (TIMER_CCMR_CCS_INPUT_TRC << 8)
 #define TIMER_CCMR1_OC1CE               (1U << TIMER_CCMR1_OC1CE_BIT)
 #define TIMER_CCMR1_OC1M                (0x3 << 4)

From 388995efbba555b742ba7652399c05c1ce1678d3 Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Fri, 1 Dec 2017 15:55:27 +0100
Subject: [PATCH 286/307] Adhere to the format of #323

---
 STM32F1/system/libmaple/include/libmaple/timer.h | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/STM32F1/system/libmaple/include/libmaple/timer.h b/STM32F1/system/libmaple/include/libmaple/timer.h
index ea7484e71..64f458f1d 100644
--- a/STM32F1/system/libmaple/include/libmaple/timer.h
+++ b/STM32F1/system/libmaple/include/libmaple/timer.h
@@ -393,10 +393,10 @@ extern timer_dev timer14;
 #define TIMER_CCMR1_OC2FE               (1U << TIMER_CCMR1_OC2FE_BIT)
 #define TIMER_CCMR1_IC2PSC              (0x3 << 10)
 #define TIMER_CCMR1_CC2S                (0x3 << 8)
-#define TIMER_CCMR1_CC2S_OUTPUT         (TIMER_CCMR_CCS_OUTPUT << 8)
-#define TIMER_CCMR1_CC2S_INPUT_TI1      (TIMER_CCMR_CCS_INPUT_TI2 << 8)
-#define TIMER_CCMR1_CC2S_INPUT_TI2      (TIMER_CCMR_CCS_INPUT_TI1 << 8)
-#define TIMER_CCMR1_CC2S_INPUT_TRC      (TIMER_CCMR_CCS_INPUT_TRC << 8)
+#define TIMER_CCMR1_CC2S_OUTPUT         (0x0 << 8)
+#define TIMER_CCMR1_CC2S_INPUT_TI2      (0x1 << 8)
+#define TIMER_CCMR1_CC2S_INPUT_TI1      (0x2 << 8)
+#define TIMER_CCMR1_CC2S_INPUT_TRC      (0x3 << 8)
 #define TIMER_CCMR1_OC1CE               (1U << TIMER_CCMR1_OC1CE_BIT)
 #define TIMER_CCMR1_OC1M                (0x3 << 4)
 #define TIMER_CCMR1_IC1F                (0xF << 4)

From 1b8b05c883b9c3713be7ec8210af903220a58667 Mon Sep 17 00:00:00 2001
From: Lacklustrlabs <lacklustrlabs@gmail.com>
Date: Tue, 23 Jan 2018 13:19:39 +0100
Subject: [PATCH 287/307] Added platform.local.txt and boards.local.txt to
 .gitignore

---
 .gitignore | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/.gitignore b/.gitignore
index 078faf600..ef5aee566 100644
--- a/.gitignore
+++ b/.gitignore
@@ -8,3 +8,5 @@ other/maple-bootloader/*~
 *.o
 *.bak
 *.1
+platform.local.txt
+boards.local.txt

From 495f3b9cb5787038eb4a1ad066576fd75fa0a0dc Mon Sep 17 00:00:00 2001
From: lacklustrlabs <lacklustrlabs@gmail.com>
Date: Wed, 15 Nov 2017 23:23:37 +0100
Subject: [PATCH 288/307] Fixed 'warning: multi-line comment [-Wcomment]'

---
 STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c b/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c
index 1f0b626a8..7ebd03b76 100644
--- a/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c
+++ b/STM32F1/cores/maple/libmaple/usb/stm32f1/usb_cdcacm.c
@@ -62,7 +62,7 @@
 
 #if !(defined(BOARD_maple) || defined(BOARD_maple_RET6) ||      \
       defined(BOARD_maple_mini) || defined(BOARD_maple_native))
-//#warning USB CDC ACM relies on LeafLabs board-specific configuration.\
+//#warning USB CDC ACM relies on LeafLabs board-specific configuration.
 //    You may have problems on non-LeafLabs boards.
 #endif
 

From 6f1429175cb5723e0bf3ec09c89950ae1f5b9cff Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Wed, 24 Jan 2018 07:39:35 +1100
Subject: [PATCH 289/307] Manually committed RTClock files, due to problems
 with PR https://github.com/rogerclarkmelbourne/Arduino_STM32/pull/428

---
 STM32F1/libraries/RTClock/src/RTClock.cpp | 2 +-
 STM32F1/libraries/RTClock/src/RTClock.h   | 2 +-
 2 files changed, 2 insertions(+), 2 deletions(-)

diff --git a/STM32F1/libraries/RTClock/src/RTClock.cpp b/STM32F1/libraries/RTClock/src/RTClock.cpp
index e95bead86..f6907edd1 100755
--- a/STM32F1/libraries/RTClock/src/RTClock.cpp
+++ b/STM32F1/libraries/RTClock/src/RTClock.cpp
@@ -111,7 +111,7 @@ void RTClock::breakTime(time_t timeInput, tm_t & tmm)
 	time /= 60; // now it is hours
 	tmm.hour = time % 24;
 	time /= 24; // now it is days
-	tmm.weekday = ((time + 4) % 7); // Monday is day 1 // + 1;  // Sunday is day 1 
+	tmm.weekday = ((time + 3) % 7); // Monday is day 1
 
 	year = 0;
 	days = 0;
diff --git a/STM32F1/libraries/RTClock/src/RTClock.h b/STM32F1/libraries/RTClock/src/RTClock.h
index 71015a586..1988c9eef 100755
--- a/STM32F1/libraries/RTClock/src/RTClock.h
+++ b/STM32F1/libraries/RTClock/src/RTClock.h
@@ -27,7 +27,7 @@ typedef struct tm_t {
 	uint8_t  year;    // years since 1970
 	uint8_t  month;   // month of a year - [ 1 to 12 ]
 	uint8_t  day;     // day of a month - [ 1 to 31 ]
-	uint8_t  weekday; // day of a week (first day is Sunday) - [ 0 to 6 ]
+	uint8_t  weekday; // day of a week (first day is Monday) - [ 0 to 6 ]
 	uint8_t  pm;      // AM: 0, PM: 1
 	uint8_t  hour;    // hour of a day - [ 0 to 23 ]
 	uint8_t  minute;  // minute of an hour - [ 0 to 59 ]

From 42a5e9f9073e1f3b2a479abc4145a32b8e8c9339 Mon Sep 17 00:00:00 2001
From: Roger Clark <roger@rogerclark.net>
Date: Fri, 2 Feb 2018 09:16:51 +1100
Subject: [PATCH 290/307] Update BOARD_NR_GPIO_PINS for STM32F103V

This fixes problem caused by https://github.com/rogerclarkmelbourne/Arduino_STM32/commit/951d0acf178b28d52919fb777874d90603c88883#diff-3df511e94e3cba57d187bb1322b9f6c6
---
 STM32F1/variants/generic_stm32f103v/board/board.h | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/STM32F1/variants/generic_stm32f103v/board/board.h b/STM32F1/variants/generic_stm32f103v/board/board.h
index ccd5ecf84..e4bd0896c 100644
--- a/STM32F1/variants/generic_stm32f103v/board/board.h
+++ b/STM32F1/variants/generic_stm32f103v/board/board.h
@@ -90,8 +90,9 @@
 #define BOARD_SPI3_MOSI_PIN     PB5
 
 
-/* GPIO A to E = 5 * 16  - BOOT1 not used = 79*/
-#define BOARD_NR_GPIO_PINS      79
+/* GPIO A to E = 5 * 16  = 80*/
+/* value is now 80 as boo1 was added via PR to the pinmap but this value was not increased*/
+#define BOARD_NR_GPIO_PINS      80
 /* Note: NOT 19. The missing one is D38 a.k.a. BOARD_BUTTON_PIN, which
  * isn't broken out to a header and is thus unusable for PWM. */
 #define BOARD_NR_PWM_PINS       19

From bd19064660cd8ce88f36f0468243fcef5e64edaa Mon Sep 17 00:00:00 2001
From: Phonog <jeanmarc.delaplace@gmail.com>
Date: Mon, 31 Oct 2016 22:21:27 +0100
Subject: [PATCH 291/307] Add files via upload

---
 .../examples/HardwareCANexample/Changes.h     |  53 ++
 .../HardwareCANexample/HardwareCANexample.ino | 181 +++++
 STM32F1/libraries/HardwareCAN/keywords.txt    |  40 ++
 .../libraries/HardwareCAN/library.properties  |   9 +
 .../libraries/HardwareCAN/src/HardwareCAN.cpp | 120 ++++
 .../libraries/HardwareCAN/src/HardwareCAN.h   |  68 ++
 .../libraries/HardwareCAN/src/utility/can.c   | 543 +++++++++++++++
 .../libraries/HardwareCAN/src/utility/can.h   | 322 +++++++++
 STM32F1/libraries/rcc.h                       | 641 ++++++++++++++++++
 STM32F1/libraries/rcc_f1.c                    | 174 +++++
 STM32F1/libraries/usb.c                       | 402 +++++++++++
 11 files changed, 2553 insertions(+)
 create mode 100644 STM32F1/libraries/HardwareCAN/examples/HardwareCANexample/Changes.h
 create mode 100644 STM32F1/libraries/HardwareCAN/examples/HardwareCANexample/HardwareCANexample.ino
 create mode 100644 STM32F1/libraries/HardwareCAN/keywords.txt
 create mode 100644 STM32F1/libraries/HardwareCAN/library.properties
 create mode 100644 STM32F1/libraries/HardwareCAN/src/HardwareCAN.cpp
 create mode 100644 STM32F1/libraries/HardwareCAN/src/HardwareCAN.h
 create mode 100644 STM32F1/libraries/HardwareCAN/src/utility/can.c
 create mode 100644 STM32F1/libraries/HardwareCAN/src/utility/can.h
 create mode 100644 STM32F1/libraries/rcc.h
 create mode 100644 STM32F1/libraries/rcc_f1.c
 create mode 100644 STM32F1/libraries/usb.c

diff --git a/STM32F1/libraries/HardwareCAN/examples/HardwareCANexample/Changes.h b/STM32F1/libraries/HardwareCAN/examples/HardwareCANexample/Changes.h
new file mode 100644
index 000000000..1ccd2fe88
--- /dev/null
+++ b/STM32F1/libraries/HardwareCAN/examples/HardwareCANexample/Changes.h
@@ -0,0 +1,53 @@
+#ifdef CHANGES_INCLUDE
+
+****** DETAILS OF THE CHANGES TO BE DONE TO THE CORE TO BE ABLE TO USE THE LIBRARY HardwareCAN   ******
+
+1) History
+The Hardware CAN library was originally published in the Maple Leaflabs forum by X893. 
+I tested it, and found bugs, which I fixed in the code. My fixes are commented with the initials JMD.
+The most important things that missed was to connect the interrupt service routine to the CAN interrupt vector.
+The problem is that in the F1 family, this vector is shared with the USB vector, as is some of the memory. Thus,
+when one wants to use the CAN, the USB becomes unavailable. This is a severe drawback of this chip, but one has to cope with this.
+
+2) Changes performed
+
+2.1) In file C:\ArduinoForSTM32\arduino-1.6.9\hardware\Arduino_STM32-master\STM32F1\cores\maple\libmaple\rcc_f1.c
+inserted 1 line, position 96:
+	[RCC_CAN]	= { .clk_domain = APB1, .line_num = 25 },	//! JMD after X893
+
+2.2) In file C:\ArduinoForSTM32\arduino-1.6.9\hardware\Arduino_STM32-master\STM32F1\system\libmaple\stm32f1\include\series\rcc.h
+inserted 1 line, position 442:
+	RCC_CAN,	//! JMD after X893    
+    
+2.3) In file C:\ArduinoForSTM32\arduino-1.6.9\hardware\Arduino_STM32-master\STM32F1\cores\maple\libmaple\usb\stm32f1\usb.c
+2.3.1) inserted 12 lines, position 186
+// JMD : default ISRs of CAN, to be overridden if HardwareCAN library is used in sketch
+void __attribute__((weak)) USB_HP_CAN_TX_IRQHandler(void) 
+{ ; }      // Dummy ISR
+
+void __irq_usb_hp_can_tx(void)
+{
+  USB_HP_CAN_TX_IRQHandler () ;
+}
+
+uint8 __attribute__((weak)) CAN_RX0_IRQ_Handler(void)
+{ return 1 ; }      // Dummy ISR 
+
+2.3.2) and altered function void __irq_usb_lp_can_rx0(void)
+ Was
+ 
+void __irq_usb_lp_can_rx0(void) {
+    uint16 istr = USB_BASE->ISTR;
+
+    /* Use USB_ISR_MSK to only include code for bits we care about. */
+    
+Becomes
+
+void __irq_usb_lp_can_rx0(void) {
+    uint16 istr = USB_BASE->ISTR;
+
+	if (CAN_RX0_IRQ_Handler())			//! JMD : Call to CAN ISR, returns 1 CAN is active
+		return;							//! JMD
+
+    /* Use USB_ISR_MSK to only include code for bits we care about. */
+ #endif
diff --git a/STM32F1/libraries/HardwareCAN/examples/HardwareCANexample/HardwareCANexample.ino b/STM32F1/libraries/HardwareCAN/examples/HardwareCANexample/HardwareCANexample.ino
new file mode 100644
index 000000000..4e3a9e574
--- /dev/null
+++ b/STM32F1/libraries/HardwareCAN/examples/HardwareCANexample/HardwareCANexample.ino
@@ -0,0 +1,181 @@
+#include <HardwareCAN.h>
+#include "changes.h"
+/*
+ * Example of use of the HardwareCAN library
+ * This application receives two frames containing various data. It also produces data that are sent periodically using another two frames.
+ * Please read the file changes.h to see the changes to be performed to the core in order to use this 
+ */
+// Define the values of the identifiers
+#define GYRO_ID 0x27
+#define JOYSTICK_VALUES_ID 0x5A
+#define TANK_LEVEL_ID 0x78
+#define MOTOR_CONTROL_ID 0x92
+
+// Limit time to flag a CAN error
+#define CAN_TIMEOUT 100           
+#define CAN_DELAY 10        // ms between two processings of incoming messages
+#define CAN_SEND_RATE 200   // ms between two successive sendings
+
+// Message structures. Each message has its own identifier. As many such variables should be defined 
+// as the number of different CAN frames the application has to send. Here, they are two.
+CanMsg msgGyroscope ;
+CanMsg msgMotorControl ;
+
+// Traffic handling data
+int CANquietTime ;          // Quiet time counter to detect no activity on CAN bus
+bool CANError ;             // Indicates that incoming CAN traffic is missing
+int CANsendDivider ;        // Used to send frames once every so many times loop() is called
+
+// Applicaton variables
+int Contents[4] ;           // Contents of the four tanks
+int JoystickX ;             // Setting of the joystick, X axis
+int JoystickY ;             // ... Y axis
+int AngularRate ;           // Output of local gyroscope
+int Throttle  ;             // Motor control value, produced by some local processing
+bool ErreurGyroscope = false ;
+
+// Instanciation of CAN interface
+HardwareCAN canBus(CAN1_BASE);
+
+
+// Note : for the predefined identifiers, please have a look in file can.h
+
+void CANSetup(void)
+{
+  CAN_STATUS Stat ;
+
+  // Initialize the message structures
+  // A CAN structure includes the following fields:
+  msgGyroscope.IDE = CAN_ID_STD;          // Indicates a standard identifier ; CAN_ID_EXT would mean this frame uses an extended identifier
+  msgGyroscope.RTR = CAN_RTR_DATA;        // Indicated this is a data frame, as opposed to a remote frame (would then be CAN_RTR_REMOTE)
+  msgGyroscope.ID = GYRO_ID ;             // Identifier of the frame : 0-2047 (0-0x3ff) for standard idenfiers; 0-0x1fffffff for extended identifiers
+  msgGyroscope.DLC = 3;                   // Number of data bytes to follow
+  msgGyroscope.Data[0] = 0x0;             // Data bytes, there can be 0 to 8 bytes.
+  msgGyroscope.Data[1] = 0x0;
+  msgGyroscope.Data[2] = 0x0;
+  
+  msgMotorControl.IDE = CAN_ID_STD;
+  msgMotorControl.RTR = CAN_RTR_DATA;
+  msgMotorControl.ID = MOTOR_CONTROL_ID ;
+  msgMotorControl.DLC = 2;
+  msgMotorControl.Data[0] = 0x0;
+  msgMotorControl.Data[1] = 0x0;
+
+  // Initialize CAN module
+  canBus.map(CAN_GPIO_PB8_PB9);       // This setting is already wired in the Olimexino-STM32 board
+  Stat = canBus.begin(CAN_SPEED_125, CAN_MODE_NORMAL);    // Other speeds go from 125 kbps to 1000 kbps. CAN allows even more choices.
+
+  canBus.filter(0, 0, 0);
+  canBus.set_irq_mode();              // Use irq mode (recommended), so the handling of incoming messages
+                                      // will be performed at ease in a task or in the loop. The software fifo is 16 cells long, 
+                                      // allowing at least 15 ms before processing the fifo is needed at 125 kbps
+  Stat = canBus.status();
+  if (Stat != CAN_OK)
+     /* Your own error processing here */ ;   // Initialization failed
+}
+
+// Send one frame. Parameter is a pointer to a frame structure (above), that has previously been updated with data.
+// If no mailbox is available, wait until one becomes empty. There are 3 mailboxes.
+CAN_TX_MBX CANsend(CanMsg *pmsg)
+{
+  CAN_TX_MBX mbx;
+
+  do 
+  {
+    mbx = canBus.send(pmsg) ;
+#ifdef USE_MULTITASK
+    vTaskDelay( 1 ) ;                 // Infinite loops are not multitasking-friendly
+#endif
+  }
+  while(mbx == CAN_TX_NO_MBX) ;       // Waiting outbound frames will eventually be sent, unless there is a CAN bus failure.
+  return mbx ;
+}
+
+// Process incoming messages
+// Note : frames are not fully checked for correctness: DLC value is not checked, neither are the IDE and RTR fields. However, the data is guaranteed to be corrrect.
+void ProcessMessages(void)
+{
+  int Pr = 0 ;
+  int i ;
+  
+  CanMsg *r_msg;
+
+  // Loop for every message in the fifo
+  while ((r_msg = canBus.recv()) != NULL)
+  {
+    CANquietTime = 0 ;              // Reset at each received frame
+    CANError = false ;              // Clear CAN silence error
+    switch ( r_msg->ID )
+    {
+      case TANK_LEVEL_ID :                  // This frame contains four 16-bit words, little endian coded
+        for ( i = 0 ; i < 4 ; i++ )
+          Contents[i] = (int)r_msg->Data[2*i] | ((int)r_msg->Data[(2*i)+1]) << 8 ;
+        break ;
+    
+      case JOYSTICK_VALUES_ID :             // This frame contains two 16-bit words, little endian coded
+        Pr = (int)r_msg->Data[0] ;
+        Pr |= (int)r_msg->Data[1] << 8 ;
+        JoystickX = Pr ;
+        
+        Pr = (int)r_msg->Data[2] ;
+        Pr |= (int)r_msg->Data[3] << 8 ;
+        JoystickY = Pr ;
+        break ;
+
+      default :                     // Any frame with a different identifier is ignored
+        break ;
+    }
+    
+    canBus.free();                          // Remove processed message from buffer, whatever the identifier
+#ifdef USE_MULTITASK
+    vTaskDelay( 1 ) ;                       // Infinite loops are not multitasking-friendly
+#endif
+  }
+}
+
+// Send messages
+// Prepare and send 2 frames containing the value of process variables
+// Sending all frames at once is a choice; they could be sent separately, at different times and rates.
+void SendCANmessages(void)
+{
+  // Prepare Gyroscope frame : send angular rate
+  msgGyroscope.Data[0] = AngularRate & 0xff ;
+  msgGyroscope.Data[1] = ( AngularRate >> 8 ) & 0xff ;
+  msgGyroscope.Data[2] = ErreurGyroscope ? 1 : 0 ;
+  CANsend(&msgGyroscope) ;      // Send this frame
+  
+  msgMotorControl.Data[0] = Throttle & 0xff ;
+  msgMotorControl.Data[1] = ( Throttle >> 8 ) & 0xff ;
+  CANsend(&msgMotorControl) ;
+}
+
+// The application program starts here
+void setup() {
+  // put your setup code here, to run once:
+  CANSetup() ;        // Initialize the CAN module and prepare the message structures.
+}
+
+void loop() {
+  // Process incoming messages periodically (should be often enough to avoid overflowing the fifo)
+  ProcessMessages() ;          // Process all incoming messages, update local variables accordingly
+
+  // This is an example of timeout management. Here it is global to all received frames; 
+  // it could be on a frame by frame basis, with as many control variables as the number of frames.
+  CANquietTime++ ; 
+  if ( CANquietTime > CAN_TIMEOUT )
+  {
+    CANquietTime = CAN_TIMEOUT + 1 ;            // To prevent overflowing this variable if silence prolongs...
+    CANError = true ;                           // Flag CAN silence error. Will be cleared at first frame received
+  }
+
+  // Send messages containing variables to publish. Sent less frequently than the processing of incoming frames (here, every 200 ms)
+  CANsendDivider-- ;
+  if ( CANsendDivider < 0 )
+  {
+    CANsendDivider = CAN_SEND_RATE / CAN_DELAY ;
+    SendCANmessages() ;       
+  }
+  delay(CAN_DELAY) ;    // The delay must not be greater than the time to overflow the incoming fifo (here about 15 ms)
+}
+
+
diff --git a/STM32F1/libraries/HardwareCAN/keywords.txt b/STM32F1/libraries/HardwareCAN/keywords.txt
new file mode 100644
index 000000000..6d901e314
--- /dev/null
+++ b/STM32F1/libraries/HardwareCAN/keywords.txt
@@ -0,0 +1,40 @@
+#######################################
+# Syntax Coloring Map For HardwareCAN
+#######################################
+
+#######################################
+# Datatypes (KEYWORD1)
+#######################################
+HardwareCAN 	KEYWORD1
+CanMsg 			KEYWORD1
+CAN_TX_MBX 		KEYWORD1
+
+#######################################
+# Methods and Functions (KEYWORD2)
+#######################################
+release 		KEYWORD2	CAN_Release
+send 			KEYWORD2	CAN_Send
+read 			KEYWORD2	CAN_Read
+recv 			KEYWORD2	CAN_Recieve
+set_pool_mode 	KEYWORD2	CAN_Set_Pool_Mode
+set_irq_mode 	KEYWORD2	CAN_Set_IRQ_Mode
+fifo_ready 		KEYWORD2	CAN_Fifo_Ready
+filter 			KEYWORD2	CAN_Filter
+free 			KEYWORD2	CAN_Free
+available		KEYWORD2	CAN_Available
+
+#######################################
+# Constants (LITERAL1)
+#######################################
+CAN_GPIO_PD0_PD1 	LITERAL1
+CAN_GPIO_PB8_PB9 	LITERAL1
+CAN_FIFO0 			LITERAL1
+CAN_FIFO1 			LITERAL1
+CAN_SPEED_125 		LITERAL1
+CAN_SPEED_250 		LITERAL1
+CAN_SPEED_500 		LITERAL1
+CAN_SPEED_1000 		LITERAL1
+CAN1_BASE 			LITERAL1
+CAN2_BASE 			LITERAL1
+CAN_ID_STD			LITERAL1
+CAN_RTR_DATA		LITERAL1
diff --git a/STM32F1/libraries/HardwareCAN/library.properties b/STM32F1/libraries/HardwareCAN/library.properties
new file mode 100644
index 000000000..9186eb6cc
--- /dev/null
+++ b/STM32F1/libraries/HardwareCAN/library.properties
@@ -0,0 +1,9 @@
+name=HardwareCAN
+version=1.0.0
+author=Maple Leaflabs fixed by JMD
+maintainer=JMD
+sentence=Enables managing CAN communication using the built-in CAN port of the OLIMEX STM32 board.
+paragraph=With this library you can use the built-in CAN port of the OLIMEX STM32. The library handles both standard and extended frames.
+category=Communication
+url=
+architectures=*
\ No newline at end of file
diff --git a/STM32F1/libraries/HardwareCAN/src/HardwareCAN.cpp b/STM32F1/libraries/HardwareCAN/src/HardwareCAN.cpp
new file mode 100644
index 000000000..f113c4d85
--- /dev/null
+++ b/STM32F1/libraries/HardwareCAN/src/HardwareCAN.cpp
@@ -0,0 +1,120 @@
+/**
+ * @brief HardwareCAN "wiring-like" api for CAN
+ */
+
+#include "wirish.h"
+#include "utility/can.h"
+#include "HardwareCAN.h"
+
+/**
+ * @brief Initialize a CAN peripheral
+ * @param freq frequency to run at, must one of the following values:
+ *           - CAN_SPEED_1000
+ *           - CAN_SPEED_500
+ *           - CAN_SPEED_250
+ *           - CAN_SPEED_125
+ */
+CAN_STATUS HardwareCAN::begin(CAN_SPEED speed, uint32 mode)
+{
+/*  Begin Fix JMD
+	if (can_init(Port, CAN_MCR_NART, CAN_SPEED_250) == CAN_OK)	
+		// NART empêche la réémission en cas de perte d'arbitrage d'où trames perdues
+ */
+	Serial.end();						// disable USB interface -- JMD
+	if (can_init(Port, 0, speed) == CAN_OK)
+ // End Fix JMD
+		return can_set_mode(Port, mode);
+	return can_status();
+}
+
+void HardwareCAN::set_pool_mode(void)
+{
+	return can_set_pool_mode(Port);
+}
+
+void HardwareCAN::set_irq_mode(void)
+{
+	return can_set_irq_mode(Port);
+}
+
+CAN_STATUS HardwareCAN::filter(uint8 idx, uint32 id, uint32 mask)
+{
+	return can_filter(Port, idx, CAN_FIFO0, CAN_FILTER_32BIT, CAN_FILTER_MASK, id, mask);
+}
+
+CAN_STATUS HardwareCAN::status(void)
+{
+	return can_status();
+}
+
+CAN_TX_MBX HardwareCAN::send(CanMsg* message)
+{
+	return can_transmit(Port, message);
+}
+
+uint8 HardwareCAN::available(void)
+{
+	return can_rx_available();
+}
+
+CanMsg* HardwareCAN::recv(void)
+{
+	return can_rx_queue_get();
+}
+
+void HardwareCAN::clear(void)
+{
+	can_rx_queue_clear();
+}
+
+void HardwareCAN::free(void)
+{
+	can_rx_queue_free();
+}
+
+void HardwareCAN::cancel(CAN_TX_MBX mbx)
+{
+	can_cancel(Port, mbx);
+}
+
+/**
+ * @brief Initialize a CAN peripheral
+ */
+CAN_STATUS HardwareCAN::begin(void)
+{
+	return begin(CAN_SPEED_250, CAN_MODE_NORMAL);
+}
+
+void HardwareCAN::end(void)
+{
+	can_deinit(Port);
+}
+
+CanMsg* HardwareCAN::read(CAN_FIFO fifo, CanMsg* msg)
+{
+	return can_read(Port, fifo, msg);
+}
+
+void HardwareCAN::release(CAN_FIFO fifo)
+{
+	can_rx_release(Port, fifo);
+}
+
+/**
+ * @brief Initialize a CAN peripheral
+ */
+CAN_STATUS HardwareCAN::map(CAN_GPIO_MAP remap)
+{
+	return can_gpio_map(Port, remap);
+}
+
+uint8 HardwareCAN::fifo_ready(CAN_FIFO fifo)
+{
+	return can_fifo_ready(Port, fifo);
+}
+
+HardwareCAN::HardwareCAN(CAN_Port* CANx)
+{
+	Port = CANx;
+}
+
diff --git a/STM32F1/libraries/HardwareCAN/src/HardwareCAN.h b/STM32F1/libraries/HardwareCAN/src/HardwareCAN.h
new file mode 100644
index 000000000..ccc318f5b
--- /dev/null
+++ b/STM32F1/libraries/HardwareCAN/src/HardwareCAN.h
@@ -0,0 +1,68 @@
+/**
+ * @brief HardwareCAN definitions
+ */
+
+#ifndef _HARDWARECAN_H_
+#define _HARDWARECAN_H_
+
+#include "utility/can.h"
+#include "usb_serial.h"
+
+#define PID_REQUEST		0x7DF
+#define PID_REPLY		0x7E8
+
+#define ENGINE_COOLANT_TEMP	0x05
+#define ENGINE_RPM			0x0C
+#define VEHICLE_SPEED		0x0D
+#define MAF_SENSOR			0x10
+#define O2_VOLTAGE			0x14
+#define THROTTLE			0x11
+
+/**
+ * Defines the possible SPI communication speeds.
+ */
+
+class HardwareCAN
+{
+private:
+public:
+	CAN_Port* Port;
+    HardwareCAN(CAN_Port *CANx_BASE);
+    CAN_STATUS begin(void);
+
+	uint32 MSR(void)
+	{
+		return Port->MSR;
+	}
+
+	uint32 RF0R(void)
+	{
+		return Port->RF0R;
+	}
+
+	void set_pool_mode(void);
+	void set_irq_mode(void);
+
+    CAN_STATUS begin(CAN_SPEED speed, uint32 mode);
+	void end(void);
+
+	CAN_STATUS filter(uint8 idx, uint32 id, uint32 mask);
+	CAN_STATUS map(CAN_GPIO_MAP remap);
+	CAN_STATUS status(void);
+
+	CAN_TX_MBX send(CanMsg* message);
+	void cancel(CAN_TX_MBX mbx);
+
+	uint8 available(void);
+
+	CanMsg* recv(void);
+
+	void free(void);
+	void clear(void);
+
+	uint8 fifo_ready(CAN_FIFO fifo);
+	CanMsg* read(CAN_FIFO fifo, CanMsg* msg);
+	void release(CAN_FIFO fifo);
+};
+
+#endif
diff --git a/STM32F1/libraries/HardwareCAN/src/utility/can.c b/STM32F1/libraries/HardwareCAN/src/utility/can.c
new file mode 100644
index 000000000..0120e0eed
--- /dev/null
+++ b/STM32F1/libraries/HardwareCAN/src/utility/can.c
@@ -0,0 +1,543 @@
+//#include "libmaple.h"
+#include "can.h"
+//#include "rcc.h"
+//#include "gpio.h"
+//#include "nvic.h"
+//#include "usb.h"
+
+/**
+  *	CAN_interrupts
+  */
+
+#define CAN_IT_RQCP0	((uint32)0x00000005) /* Request completed mailbox 0 */
+#define CAN_IT_RQCP1	((uint32)0x00000006) /* Request completed mailbox 1 */
+#define CAN_IT_RQCP2	((uint32)0x00000007) /* Request completed mailbox 2 */
+#define CAN_IT_TME		((uint32)0x00000001) /* Transmit mailbox empty */
+#define CAN_IT_FMP0		((uint32)0x00000002) /* FIFO 0 message pending */
+#define CAN_IT_FF0		((uint32)0x00000004) /* FIFO 0 full */
+#define CAN_IT_FOV0		((uint32)0x00000008) /* FIFO 0 overrun */
+#define CAN_IT_FMP1		((uint32)0x00000010) /* FIFO 1 message pending */
+#define CAN_IT_FF1		((uint32)0x00000020) /* FIFO 1 full */
+#define CAN_IT_FOV1		((uint32)0x00000040) /* FIFO 1 overrun */
+#define CAN_IT_EWG		((uint32)0x00000100) /* Error warning */
+#define CAN_IT_EPV		((uint32)0x00000200) /* Error passive */
+#define CAN_IT_BOF		((uint32)0x00000400) /* Bus-off */
+#define CAN_IT_LEC		((uint32)0x00000800) /* Last error code */
+#define CAN_IT_ERR		((uint32)0x00008000) /* Error */
+#define CAN_IT_WKU		((uint32)0x00010000) /* Wake-up */
+#define CAN_IT_SLK		((uint32)0x00020000) /* Sleep */
+
+/* Time out for INAK bit */
+#define CAN_INAK_TimeOut	((uint32)0x0000FFFF)
+
+/* Time out for SLAK bit */
+#define CAN_SLAK_TimeOut	((uint32)0x0000FFFF)
+
+#define CAN_CONTROL_MASK	(CAN_MCR_TTCM | CAN_MCR_ABOM | CAN_MCR_AWUM | CAN_MCR_NART | CAN_MCR_RFLM | CAN_MCR_TXFP)
+#define CAN_TIMING_MASK		(CAN_BTR_SJW | CAN_BTR_TS2 | CAN_BTR_TS1 | CAN_BTR_BRP)
+#define CAN_MODE_MASK		(CAN_BTR_LBKM | CAN_BTR_SILM)
+
+struct can_speed_info {
+    const uint32 btr;
+};
+
+#define CAN_CLOCK	(36000000UL / 18UL)
+
+static const struct can_speed_info can_speed_table[] = {
+	[CAN_SPEED_125]		= { .btr = (
+		(( 4-1) << CAN_BTR_SJW_POS) |
+		((12-1) << CAN_BTR_TS1_POS) |
+		(( 5-1) << CAN_BTR_TS2_POS) |
+		(CAN_CLOCK / 125000UL - 1)
+		)},
+	[CAN_SPEED_250]		= { .btr = (
+		(( 4-1) << CAN_BTR_SJW_POS) |
+		((12-1) << CAN_BTR_TS1_POS) |
+		(( 5-1) << CAN_BTR_TS2_POS) |
+		(CAN_CLOCK / 250000UL - 1)
+		)},
+	[CAN_SPEED_500]		= { .btr = (
+		(( 4-1) << CAN_BTR_SJW_POS) |
+		((12-1) << CAN_BTR_TS1_POS) |
+		(( 5-1) << CAN_BTR_TS2_POS) |
+		(CAN_CLOCK / 500000UL - 1)
+		)},
+	[CAN_SPEED_1000]	= { .btr = (
+		(( 4-1) << CAN_BTR_SJW_POS) |
+		((12-1) << CAN_BTR_TS1_POS) |
+		(( 5-1) << CAN_BTR_TS2_POS) |
+		(CAN_CLOCK / 1000000UL - 1)
+		)}
+};
+
+CAN_STATUS status;
+CanMsg can_rx_queue[CAN_RX_QUEUE_SIZE];
+
+uint8 can_rx_head;
+uint8 can_rx_tail;
+uint8 can_rx_count;
+uint8 can_rx_lost;
+uint8 can_active = 0;
+
+/**
+  * @brief  Return last operation status
+  */
+CAN_STATUS can_status(void)
+{
+	return status;
+}
+
+/**
+  * @brief  Enter initialization mode
+  */
+CAN_STATUS can_init_enter(CAN_Port* CANx)
+{
+	volatile uint32 wait_ack = 0 ;
+    
+	status = CAN_OK;
+	if ((CANx->MSR & CAN_MSR_INAK) == 0)	// Check for initialization mode already set
+	{
+		CANx->MCR |= CAN_MCR_INRQ;			// Request initialisation
+
+		wait_ack = 0;						// Wait the acknowledge
+		while ((wait_ack != CAN_INAK_TimeOut) && ((CANx->MSR & CAN_MSR_INAK) == 0))
+			wait_ack++;
+		if ((CANx->MSR & CAN_MSR_INAK) == 0)
+			status = CAN_INIT_E_FAILED;		// Timeout
+	}
+	return status;
+}
+
+/**
+  * @brief  Leave initialization mode
+  */
+CAN_STATUS can_init_leave(CAN_Port* CANx)
+{
+	volatile uint32 wait_ack = 0 ;
+
+	status = CAN_OK;
+	if ((CANx->MSR & CAN_MSR_INAK) != 0)	// Check for initialization mode already reset
+	{
+		CANx->MCR &= ~CAN_MCR_INRQ;			// Clear Request initialization
+
+		wait_ack = 0;						// Wait the acknowledge
+		while ((wait_ack != CAN_INAK_TimeOut) && ((CANx->MSR & CAN_MSR_INAK) != 0))
+			wait_ack++;
+		if ((CANx->MSR & CAN_MSR_INAK) != 0)
+			status = CAN_INIT_L_FAILED;
+	}
+	return status;
+}
+
+/**
+  * @brief  Deinitializes the CAN peripheral registers to their default reset values.
+  */
+CAN_STATUS can_deinit(CAN_Port* CANx)
+{
+	if (CANx == CAN1_BASE)
+	{
+		nvic_irq_disable(NVIC_USB_LP_CAN_RX0);	// Disable interrupts
+		nvic_irq_disable(NVIC_USB_HP_CAN_TX);
+		rcc_reset_dev(RCC_CAN);
+		rcc_clk_disable(RCC_CAN);
+		can_active = 0;
+	}
+	return (status = CAN_OK);
+}
+
+/**
+  * @brief  Initialize CAN registers
+  */
+/*
+ *		Bits in control parameter:
+ *			CAN_MCR_TTCM	time triggered communication mode
+ *			CAN_MCR_ABOM	automatic bus-off management
+ *			CAN_MCR_AWUM	automatic wake-up mode
+ *			CAN_MCR_NART	no automatic retransmission
+ *			CAN_MCR_RFLM	receive FIFO locked mode
+ *			CAN_MCR_TXFP	transmit FIFO priority
+ */
+CAN_STATUS can_init(CAN_Port* CANx, uint32 control, uint8 speed)
+{
+	status = CAN_INIT_FAILED;			// default result status
+										// initialize receive message queue
+	can_rx_head = can_rx_tail = can_rx_count = can_rx_lost = 0;
+
+	rcc_reset_dev(RCC_USB);			//! X893
+	rcc_clk_disable(RCC_USB);		//! X893
+//	line_dtr_rts = 0;				//! X893
+	rcc_clk_enable(RCC_AFIO);			// enable clocks for AFIO
+	rcc_clk_enable(RCC_CAN);			// and CAN
+	rcc_reset_dev(RCC_CAN);				// reset CAN interface
+
+	can_active = 1;						// set CAN active flag (for interrupt handler
+
+	CANx->MCR &= ~CAN_MCR_SLEEP;		// reset CAN sleep mode (default after reset)
+
+	if (can_init_enter(CANx) != CAN_OK)	// enter CAN initialization mode
+		return status;					// error, so return
+
+	CANx->MCR &= ~CAN_CONTROL_MASK;		// set mode bits
+	CANx->MCR |= (control & CAN_CONTROL_MASK);
+
+	CANx->BTR &= ~CAN_TIMING_MASK;			// Set the bit timing register
+	CANx->BTR |= (can_speed_table[speed].btr & CAN_TIMING_MASK);
+
+	nvic_irq_enable(NVIC_USB_LP_CAN_RX0);	// Enable interrupts
+    
+	nvic_irq_enable(NVIC_USB_HP_CAN_TX);
+
+	CANx->IER = (CAN_IER_FMPIE0 | CAN_IER_FMPIE1 | CAN_IER_TMEIE);
+
+	if (can_init_leave(CANx) == CAN_OK)
+	{
+		while (!(CANx->TSR & CAN_TSR_TME0));	// Transmit mailbox 0 is empty
+		while (!(CANx->TSR & CAN_TSR_TME1));	// Transmit mailbox 0 is empty
+		while (!(CANx->TSR & CAN_TSR_TME2));	// Transmit mailbox 0 is empty
+	} 
+	return status;
+}
+
+/**
+  * @brief  Set timing calues (CAN_BTR)
+  */
+CAN_STATUS can_set_timing(CAN_Port* CANx, uint32 timing)
+{
+	if (can_init_enter(CANx) == CAN_OK)
+	{
+		CANx->BTR = ((CANx->BTR & ~CAN_TIMING_MASK) | (timing & CAN_TIMING_MASK));
+		can_init_leave(CANx);
+	}
+	return status;
+}
+
+/**
+  * @brief  Set CAN mode
+  * @param CANx pointer to CAN port
+  * @param mode CAN mode
+  */
+CAN_STATUS can_set_mode(CAN_Port* CANx, uint32 mode)
+{
+	if (can_init_enter(CANx) == CAN_OK)
+	{
+		CANx->BTR &= ~CAN_MODE_MASK;
+		CANx->BTR |= (mode & CAN_MODE_MASK);
+		can_init_leave(CANx);
+	}
+	return status;
+}
+
+/**
+  * @brief  Set CAN to GPIO mapping
+  */
+CAN_STATUS can_gpio_map(CAN_Port* CANx, CAN_GPIO_MAP map_mode)
+{
+	rcc_clk_enable(RCC_AFIO);
+
+	status = CAN_INIT_FAILED;
+	if( CANx == CAN1_BASE)
+	{
+		switch(map_mode)
+		{
+		case CAN_GPIO_PB8_PB9:
+			rcc_clk_enable(RCC_GPIOB);
+			afio_remap(AFIO_MAPR_CAN_REMAP_PB8_PB9);
+			gpio_set_mode(GPIOB, 8, GPIO_INPUT_FLOATING);
+			gpio_set_mode(GPIOB, 9, GPIO_AF_OUTPUT_PP);
+			break;
+#if NR_GPIO_PORTS >= 4
+		case CAN_GPIO_PD0_PD1:
+			rcc_clk_enable(RCC_GPIOD);
+			afio_remap(AFIO_MAPR_CAN_REMAP_PD0_PD1);
+			gpio_set_mode(GPIOD, 0, GPIO_INPUT_FLOATING);
+			gpio_set_mode(GPIOD, 1, GPIO_AF_OUTPUT_PP);
+			break;
+#endif
+		default:
+			return status;
+		}
+		status = CAN_OK;
+	}
+	return status;
+}
+
+CAN_STATUS can_filter(CAN_Port* CANx, uint8 filter_idx, CAN_FIFO fifo, CAN_FILTER_SCALE scale, CAN_FILTER_MODE mode, uint32 fr1, uint32 fr2)
+{
+	uint32 mask = ((uint32)0x00000001) << filter_idx;
+
+	CANx->FMR |= CAN_FMR_FINIT;		// Initialization mode for the filter
+	CANx->FA1R &= ~mask;			// Deactivation filter
+
+
+	if (scale == CAN_FILTER_32BIT)
+		CANx->FS1R |= mask;
+	else
+		CANx->FS1R &= ~mask;
+
+	CANx->sFilterRegister[filter_idx].FR1 = fr1;
+	CANx->sFilterRegister[filter_idx].FR2 = fr2;
+
+	if (mode == CAN_FILTER_MASK)
+		CANx->FM1R &= ~mask;
+	else
+		CANx->FM1R |= mask;
+
+	if (fifo == CAN_FIFO0)
+		CANx->FFA1R &= ~mask;
+	else
+		CANx->FFA1R |= mask;
+
+	CANx->FA1R |= mask;
+	CANx->FMR &= ~CAN_FMR_FINIT;
+	return CAN_OK;
+}
+
+/**
+  * @brief  Initiates the transmission of a message.
+  * @param	CANx: where x can be 1 to select the CAN peripheral.
+  * @param	msg: pointer to a structure which contains CAN Id, CAN DLC and CAN datas.
+  * @retval : The number of the mailbox that is used for transmission or CAN_NO_MB if there is no empty mailbox.
+  */
+CAN_TX_MBX can_transmit(CAN_Port* CANx, CanMsg* msg)
+{
+	CAN_TX_MBX mbx;
+	uint32 data;
+
+	/* Select one empty transmit mailbox */
+	if (CANx->TSR & CAN_TSR_TME0)
+		mbx = CAN_TX_MBX0;
+	else if (CANx->TSR & CAN_TSR_TME1)
+		mbx = CAN_TX_MBX1;
+	else if (CANx->TSR & CAN_TSR_TME2)
+		mbx = CAN_TX_MBX2;
+	else
+	{
+		status = CAN_NO_MB;
+		return CAN_TX_NO_MBX;
+	}
+
+    /* Set up the Id */
+    if (msg->IDE == CAN_ID_STD)
+		data = (msg->ID << 21);
+    else
+		data = (msg->ID << 3) | CAN_ID_EXT;
+
+	data |= ((uint32)msg->RTR);
+
+	/* Set up the DLC */
+    CANx->sTxMailBox[mbx].TDTR = (uint32)(msg->DLC & 0x0F);
+
+    /* Set up the data field */
+    CANx->sTxMailBox[mbx].TDLR = (
+		((uint32)msg->Data[3] << 24) | 
+		((uint32)msg->Data[2] << 16) |
+		((uint32)msg->Data[1] << 8) | 
+		((uint32)msg->Data[0])
+		);
+    CANx->sTxMailBox[mbx].TDHR = (
+		((uint32)msg->Data[7] << 24) |
+		((uint32)msg->Data[6] << 16) |
+		((uint32)msg->Data[5] << 8) |
+		((uint32)msg->Data[4])
+		);
+    /* Request transmission */
+    CANx->sTxMailBox[mbx].TIR = (data | CAN_TMIDxR_TXRQ);
+	status = CAN_OK;
+
+	return mbx;
+}
+
+/**
+  * Checks the transmission of a message.
+  * @param CANx: where x can be 1 to select the CAN peripheral.
+  * @param mbx: the number of the mailbox that is used for transmission.
+  * @retval : CAN_TX_OK if the CAN driver transmits the message, CAN_TX_FAILED in an other case.
+  */
+CAN_STATUS can_tx_status(CAN_Port* CANx, CAN_TX_MBX mbx)
+{
+	/* RQCP, TXOK and TME bits */
+	uint8 state = 0;
+
+	switch (mbx)
+	{
+	case CAN_TX_MBX0:
+		state |= (uint8)((CANx->TSR & CAN_TSR_RQCP0) << 2);
+		state |= (uint8)((CANx->TSR & CAN_TSR_TXOK0) >> 0);
+		state |= (uint8)((CANx->TSR & CAN_TSR_TME0) >> 26);
+		break;
+	case CAN_TX_MBX1:
+		state |= (uint8)((CANx->TSR & CAN_TSR_RQCP1) >> 6);
+		state |= (uint8)((CANx->TSR & CAN_TSR_TXOK1) >> 8);
+		state |= (uint8)((CANx->TSR & CAN_TSR_TME1) >> 27);
+		break;
+	case CAN_TX_MBX2:
+		state |= (uint8)((CANx->TSR & CAN_TSR_RQCP2) >> 14);
+		state |= (uint8)((CANx->TSR & CAN_TSR_TXOK2) >> 16);
+		state |= (uint8)((CANx->TSR & CAN_TSR_TME2) >> 28);
+		break;
+	default:
+		status = CAN_TX_FAILED;
+		return status;
+	}
+
+	// state = RQCP TXOK TME
+	switch (state)
+	{
+	/* transmit pending  */
+	case 0x0:
+		status = CAN_TX_PENDING;
+		break;
+	/* transmit failed  */
+	case 0x5:
+		status = CAN_TX_FAILED;
+		break;
+	/* transmit succedeed  */
+	case 0x7:
+		status = CAN_OK;
+		break;
+	default:
+		status = CAN_TX_FAILED;
+		break;
+	}
+	return status;
+}
+
+/**
+  * @brief  Cancels a transmit request.
+  * @param CANx: where x can be 1 to select the CAN peripheral.
+  * @param mbx: Mailbox number.
+  * @retval : None.
+  */
+void can_cancel(CAN_Port* CANx, uint8 mbx)
+{
+	/* abort transmission */
+	switch (mbx)
+	{
+	case 0:
+		CANx->TSR |= CAN_TSR_ABRQ0;
+		break;
+	case 1:
+		CANx->TSR |= CAN_TSR_ABRQ1;
+		break;
+	case 2:
+		CANx->TSR |= CAN_TSR_ABRQ2;
+		break;
+	default:
+		break;
+	}
+}
+
+void can_rx_queue_clear(void)
+{
+	nvic_irq_disable(NVIC_USB_LP_CAN_RX0);
+	can_rx_head = can_rx_tail = can_rx_count = can_rx_lost = 0;
+	nvic_irq_enable(NVIC_USB_LP_CAN_RX0);
+}
+
+uint8 can_rx_available(void)
+{
+	return can_rx_count;
+}
+
+CanMsg* can_rx_queue_get(void)
+{
+	if (can_rx_count == 0)
+		return NULL;
+	return &(can_rx_queue[can_rx_tail]);
+}
+
+void can_rx_queue_free(void)
+{
+	if (can_rx_count > 0)
+	{
+		nvic_irq_disable(NVIC_USB_LP_CAN_RX0);			// JMD problème d'atomicité
+		can_rx_tail = (can_rx_tail == (CAN_RX_QUEUE_SIZE - 1)) ? 0 : (can_rx_tail + 1);
+		--can_rx_count;
+		nvic_irq_enable(NVIC_USB_LP_CAN_RX0);			// fin JMD problème d'atomicité
+	}
+}
+
+CanMsg* can_read(CAN_Port* CANx, CAN_FIFO fifo, CanMsg* msg)
+{
+	uint32 data = CANx->sFIFOMailBox[fifo].RIR;
+
+	/* Get the Id */
+	if (data & CAN_ID_EXT)
+	{
+		msg->ID = 0x1FFFFFFF & (data >> 3);
+		msg->IDE = (uint8)CAN_ID_EXT;
+	}
+	else
+	{
+		msg->ID = 0x000007FF & (data >> 21);
+		msg->IDE = (uint8)CAN_ID_STD;
+	}
+
+	msg->RTR = (uint8)(CAN_RTR_REMOTE & data);
+	msg->DLC = (uint8)(0x0F & CANx->sFIFOMailBox[fifo].RDTR);
+	msg->FMI = (uint8)(0xFF & (CANx->sFIFOMailBox[fifo].RDTR >> 8));
+
+	/* Get the data field */
+	data = CANx->sFIFOMailBox[fifo].RDLR;
+	uint8* p = msg->Data;
+	*p++ = (uint8)0xFF & data;
+	*p++ = (uint8)0xFF & (data >> 8);
+	*p++ = (uint8)0xFF & (data >> 16);
+	*p++ = (uint8)0xFF & (data >> 24);
+
+	data = CANx->sFIFOMailBox[fifo].RDHR;
+	*p++ = (uint8)0xFF & data;
+	*p++ = (uint8)0xFF & (data >> 8);
+	*p++ = (uint8)0xFF & (data >> 16);
+	*p++ = (uint8)0xFF & (data >> 24);
+
+	return msg;
+}
+
+void can_rx_release(CAN_Port* CANx, CAN_FIFO fifo)
+{
+	if (fifo == CAN_FIFO0)
+		CANx->RF0R |= (CAN_RF0R_RFOM0);	// Release FIFO0
+	else
+		CANx->RF1R |= (CAN_RF1R_RFOM1);	// Release FIFO1
+}
+
+void can_rx_read(CAN_Port* CANx, CAN_FIFO fifo)
+{
+	if (can_rx_count < CAN_RX_QUEUE_SIZE)		// read the message
+	{
+		CanMsg* msg = &can_rx_queue[can_rx_head];
+		can_read(CANx, fifo, msg);
+		can_rx_head = (can_rx_head == (CAN_RX_QUEUE_SIZE - 1)) ? 0 : (can_rx_head + 1);
+		can_rx_count++;
+	}
+	else
+		can_rx_lost = 1;						// no place in queue, ignore package
+
+	can_rx_release(CANx, fifo);
+}
+
+uint8 CAN_RX0_IRQ_Handler(void)
+{
+	if (can_active)
+	{
+		while ((CAN1_BASE->RF0R & CAN_RF0R_FMP0) != 0)
+			can_rx_read(CAN1_BASE, CAN_FIFO0);		// message pending FIFO0
+		while ((CAN1_BASE->RF1R & CAN_RF1R_FMP1) != 0)
+			can_rx_read(CAN1_BASE, CAN_FIFO1);		// message pending FIFO1
+	}
+	return can_active;								// return CAN active flag to USB handler
+}
+
+void USB_HP_CAN_TX_IRQHandler (void)
+{
+	if (can_active)
+	{
+		if (CAN1_BASE->TSR & CAN_TSR_RQCP0)
+			CAN1_BASE->TSR |= CAN_TSR_RQCP0;		// reset request complete mbx 0
+		if (CAN1_BASE->TSR & CAN_TSR_RQCP1)
+			CAN1_BASE->TSR |= CAN_TSR_RQCP1;		// reset request complete mbx 1
+		if (CAN1_BASE->TSR & CAN_TSR_RQCP2)
+			CAN1_BASE->TSR |= CAN_TSR_RQCP2;		// reset request complete mbx 2
+	}
+}
diff --git a/STM32F1/libraries/HardwareCAN/src/utility/can.h b/STM32F1/libraries/HardwareCAN/src/utility/can.h
new file mode 100644
index 000000000..576ac36fe
--- /dev/null
+++ b/STM32F1/libraries/HardwareCAN/src/utility/can.h
@@ -0,0 +1,322 @@
+#ifndef _CAN_H_
+#define _CAN_H_
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+//#include "libmaple_types.h"
+#include <libmaple/libmaple_types.h>
+#include <libmaple/gpio.h>
+#include "libmaple/nvic.h"
+#include <libmaple/rcc.h>
+//#include "types.h"
+#include "libmaple/usb.h"
+
+#ifndef CAN_RX_QUEUE_SIZE
+	#define CAN_RX_QUEUE_SIZE 16
+#endif
+
+/* peripheral addresses */
+#define CAN1_BASE		((CAN_Port*)0x40006400)
+#define CAN2_BASE		((CAN_Port*)0x40006800)
+
+
+/* CAN Master Control Register bits */
+#define CAN_MCR_INRQ	((uint32)0x00000001)	/* Initialization request */
+#define CAN_MCR_SLEEP	((uint32)0x00000002)	/* Sleep mode request */
+#define CAN_MCR_TXFP	((uint32)0x00000004)	/* Transmit FIFO priority */
+#define CAN_MCR_RFLM	((uint32)0x00000008)	/* Receive FIFO locked mode */
+#define CAN_MCR_NART	((uint32)0x00000010)	/* No automatic retransmission */
+#define CAN_MCR_AWUM	((uint32)0x00000020)	/* Automatic wake up mode */
+#define CAN_MCR_ABOM	((uint32)0x00000040)	/* Automatic bus-off management */
+#define CAN_MCR_TTCM	((uint32)0x00000080)	/* Time triggered communication mode */
+#define CAN_MCR_RESET	((uint32)0x00008000)	/* bxCAN software master reset */
+#define CAN_MCR_DBF		((uint32)0x00010000)	/* Debug freeze */
+
+/* CAN Master Status Register bits */
+#define CAN_MSR_INAK	((uint32)0x00000001)	/* Initialization acknowledge */
+#define CAN_MSR_SLAK	((uint32)0x00000002)	/* Sleep acknowledge */
+#define CAN_MSR_ERRI	((uint32)0x00000004)	/* Error interrupt */
+#define CAN_MSR_WKUI	((uint32)0x00000008)	/* Wake-up interrupt */
+#define CAN_MSR_SLAKI	((uint32)0x00000010)	/* Sleep acknowledge interrupt */
+#define CAN_MSR_TXM		((uint32)0x00000100)	/* Transmit mode */
+#define CAN_MSR_RXM		((uint32)0x00000200)	/* Receive mode */
+#define CAN_MSR_SAMP	((uint32)0x00000400)	/* Last sample point */
+#define CAN_MSR_RX		((uint32)0x00000800)	/* CAN Rx signal */
+
+/* CAN Transmit Status Register bits */
+#define CAN_TSR_RQCP0	((uint32)0x00000001)    /* Request completed mailbox0 */
+#define CAN_TSR_TXOK0	((uint32)0x00000002)    /* Transmission OK of mailbox0 */
+#define CAN_TSR_ALST0	((uint32)0x00000004)	/* Arbitration Lost for Mailbox0 */
+#define CAN_TSR_TERR0	((uint32)0x00000008)	/* Transmission Error of Mailbox0 */
+#define CAN_TSR_ABRQ0	((uint32)0x00000080)    /* Abort request for mailbox0 */
+#define CAN_TSR_RQCP1	((uint32)0x00000100)    /* Request completed mailbox1 */
+#define CAN_TSR_TXOK1	((uint32)0x00000200)    /* Transmission OK of mailbox1 */
+#define CAN_TSR_ALST1	((uint32)0x00000400)	/* Arbitration Lost for Mailbox1 */
+#define CAN_TSR_TERR1	((uint32)0x00000800)	/* Transmission Error of Mailbox1 */
+#define CAN_TSR_ABRQ1	((uint32)0x00008000)    /* Abort request for mailbox1 */
+#define CAN_TSR_RQCP2	((uint32)0x00010000)    /* Request completed mailbox2 */
+#define CAN_TSR_TXOK2	((uint32)0x00020000)    /* Transmission OK of mailbox2 */
+#define CAN_TSR_ALST2	((uint32)0x00040000)	/* Arbitration Lost for mailbox 2 */
+#define CAN_TSR_TERR2	((uint32)0x00080000)	/* Transmission Error of Mailbox 2 */
+#define CAN_TSR_ABRQ2	((uint32)0x00800000)    /* Abort request for mailbox2 */
+#define CAN_TSR_CODE	((uint32)0x03000000)	/* Mailbox Code */
+#define CAN_TSR_TME		((uint32)0x1C000000)	/* TME[2:0] bits */
+#define CAN_TSR_TME0	((uint32)0x04000000)    /* Transmit mailbox 0 empty */
+#define CAN_TSR_TME1	((uint32)0x08000000)    /* Transmit mailbox 1 empty */
+#define CAN_TSR_TME2	((uint32)0x10000000)    /* Transmit mailbox 2 empty */
+#define CAN_TSR_LOW		((uint32)0xE0000000)	/* LOW[2:0] bits */
+#define CAN_TSR_LOW0	((uint32)0x20000000)	/* Lowest Priority Flag for Mailbox 0 */
+#define CAN_TSR_LOW1	((uint32)0x40000000)	/* Lowest Priority Flag for Mailbox 1 */
+#define CAN_TSR_LOW2	((uint32)0x80000000)	/* Lowest Priority Flag for Mailbox 2 */
+
+/* CAN Receive FIFO 0 Register bits */
+#define CAN_RF0R_FMP0	((uint32)0x00000003)    /* FIFO 0 message pending */
+#define CAN_RF0R_FULL0	((uint32)0x00000008)    /* FIFO 0 full */
+#define CAN_RF0R_FOVR0	((uint32)0x00000010)    /* FIFO 0 overrun */
+#define CAN_RF0R_RFOM0	((uint32)0x00000020)    /* Release FIFO 0 output mailbox */
+
+/* CAN Receive FIFO 1 Register bits */
+#define CAN_RF1R_FMP1	((uint32)0x00000003)    /* FIFO 1 message pending */
+#define CAN_RF1R_FULL1	((uint32)0x00000008)    /* FIFO 1 full */
+#define CAN_RF1R_FOVR1	((uint32)0x00000010)    /* FIFO 1 overrun */
+#define CAN_RF1R_RFOM1	((uint32)0x00000020)    /* Release FIFO 1 output mailbox */
+
+/* CAN Error Status Register bits */
+#define CAN_ESR_EWGF	((uint32)0x00000001)    /* Error warning flag */
+#define CAN_ESR_EPVF	((uint32)0x00000002)    /* Error passive flag */
+#define CAN_ESR_BOFF	((uint32)0x00000004)    /* Bus-off flag */
+
+/* CAN interrupt enable register (CAN_IER) */
+#define CAN_IER_TMEIE	((uint32)0x00000001)	/* Transmit Mailbox Empty Interrupt Enable */
+#define CAN_IER_FMPIE0	((uint32)0x00000002)	/* FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE0	((uint32)0x00000004)	/* FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE0	((uint32)0x00000008)	/* FIFO Overrun Interrupt Enable */
+#define CAN_IER_FMPIE1	((uint32)0x00000010)	/* FIFO Message Pending Interrupt Enable */
+#define CAN_IER_FFIE1	((uint32)0x00000020)	/* FIFO Full Interrupt Enable */
+#define CAN_IER_FOVIE1	((uint32)0x00000040)	/* FIFO Overrun Interrupt Enable */
+#define CAN_IER_EWGIE	((uint32)0x00000100)	/* Error Warning Interrupt Enable */
+#define CAN_IER_EPVIE	((uint32)0x00000200)	/* Error Passive Interrupt Enable */
+#define CAN_IER_BOFIE	((uint32)0x00000400)	/* Bus-Off Interrupt Enable */
+#define CAN_IER_LECIE	((uint32)0x00000800)	/* Last Error Code Interrupt Enable */
+#define CAN_IER_ERRIE	((uint32)0x00008000)	/* Error Interrupt Enable */
+#define CAN_IER_WKUIE	((uint32)0x00010000)	/* Wakeup Interrupt Enable */
+#define CAN_IER_SLKIE	((uint32)0x00020000)	/* Sleep Interrupt Enable */
+
+/* CAN error status register (CAN_ESR) */
+#define CAN_ESR_EWGF	((uint32)0x00000001)	/* Error Warning Flag */
+#define CAN_ESR_EPVF	((uint32)0x00000002)	/* Error Passive Flag */
+#define CAN_ESR_BOFF	((uint32)0x00000004)	/* Bus-Off Flag */
+
+#define CAN_ESR_LEC		((uint32)0x00000070)	/* LEC[2:0] bits (Last Error Code) */
+#define CAN_ESR_LEC_0	((uint32)0x00000010)	/* Bit 0 */
+#define CAN_ESR_LEC_1	((uint32)0x00000020)	/* Bit 1 */
+#define CAN_ESR_LEC_2	((uint32)0x00000040)	/* Bit 2 */
+
+#define CAN_ESR_TEC		((uint32)0x00FF0000)	/* Least significant byte of the 9-bit Transmit Error Counter */
+#define CAN_ESR_REC		((uint32)0xFF000000)	/* Receive Error Counter */
+
+/* CAN bit timing register (CAN_BTR) */
+#define CAN_BTR_SJW_POS	24
+#define CAN_BTR_TS2_POS	20
+#define CAN_BTR_TS1_POS	16
+
+#define CAN_BTR_BRP		((uint32)0x000003FF)	/* Baud Rate Prescaler */
+#define CAN_BTR_TS1 	((uint32)0x000F0000)	/* Time Segment 1 */
+#define CAN_BTR_TS2 	((uint32)0x00700000)	/* Time Segment 2 */
+#define CAN_BTR_SJW 	((uint32)0x03000000)	/* Resynchronization Jump Width */
+#define CAN_BTR_LBKM	((uint32)0x40000000)	/* Loop Back Mode (Debug) */
+#define CAN_BTR_SILM	((uint32)0x80000000)	/* Silent Mode */
+
+
+/* CAN Mailbox Transmit Request */
+#define CAN_TMIDxR_TXRQ	((uint32)0x00000001) /* Transmit mailbox request */
+
+/* CAN Filter Master Register bits */
+#define CAN_FMR_FINIT	((uint32)0x00000001) /* Filter init mode */
+
+
+typedef enum CAN_GPIO_MAP {
+	CAN_GPIO_PB8_PB9,		/* RX to PB8, TX to PB9 */
+	CAN_GPIO_PD0_PD1		/* RX to PD0, TX to PD1 */
+} CAN_GPIO_MAP;
+
+typedef enum CAN_STATUS
+{
+	CAN_OK = 0,
+	CAN_INIT_FAILED,
+	CAN_INIT_E_FAILED,
+	CAN_INIT_L_FAILED,
+	CAN_TX_FAILED,
+	CAN_TX_PENDING,
+	CAN_NO_MB,
+	CAN_FILTER_FULL
+} CAN_STATUS;
+
+typedef enum CAN_TX_MBX
+{
+	CAN_TX_MBX0 = 0,
+	CAN_TX_MBX1 = 1,
+	CAN_TX_MBX2 = 2,
+	CAN_TX_NO_MBX = CAN_NO_MB
+} CAN_TX_MBX;
+
+#define CAN_MODE_NORMAL				((uint32)0x0)				/* normal mode */
+#define CAN_MODE_LOOPBACK			(CAN_BTR_LBKM)				/* loopback mode */
+#define CAN_MODE_SILENT				(CAN_BTR_SILM)				/* silent mode */
+#define CAN_MODE_SILENT_LOOPBACK	(CAN_BTR_LBKM | CAN_BTR_SILM)	/* loopback combined with silent mode */
+
+enum CAN_SPEED {
+	CAN_SPEED_125,
+	CAN_SPEED_250,
+	CAN_SPEED_500,
+	CAN_SPEED_1000,
+};
+
+/**
+  *	CAN_identifier_type 
+  */
+#define CAN_ID_STD	((uint32)0x00)	/* Standard Id */
+#define CAN_ID_EXT	((uint32)0x04)	/* Extended Id */
+
+/**
+  *	CAN_remote_transmission_request 
+  */
+#define CAN_RTR_DATA	((uint32)0x00)  /* Data frame */
+#define CAN_RTR_REMOTE	((uint32)0x02)  /* Remote frame */
+
+/**
+  * CAN_receive_FIFO_number_constants
+  */
+typedef enum {
+	CAN_FIFO0 = 0,
+	CAN_FIFO1 = 1
+} CAN_FIFO;
+
+typedef enum {
+	CAN_FILTER_32BIT	 = 0,
+	CAN_FILTER_16BIT	 = 1
+} CAN_FILTER_SCALE;
+
+typedef enum {
+	CAN_FILTER_MASK		= 0,
+	CAN_FILTER_LIST		= 1
+} CAN_FILTER_MODE;
+/**
+  * @brief Controller Area Network TxMailBox
+  */
+typedef struct
+{
+	volatile uint32 TIR;
+	volatile uint32 TDTR;
+	volatile uint32 TDLR;
+	volatile uint32 TDHR;
+} CAN_TxMailBox_Port;
+
+/**
+  * @brief Controller Area Network FIFOMailBox
+  */
+typedef struct
+{
+	volatile uint32 RIR;
+	volatile uint32 RDTR;
+	volatile uint32 RDLR;
+	volatile uint32 RDHR;
+} CAN_FIFOMailBox_Port;
+
+/**
+  * @brief Controller Area Network FilterRegister
+  */
+typedef struct
+{
+	volatile uint32 FR1;
+	volatile uint32 FR2;
+} CAN_FilterRegister_Port;
+
+typedef struct {
+    volatile uint32 MCR;	// CAN master control register (CAN_MCR)
+    volatile uint32 MSR;	// CAN master status register (CAN_MSR)
+    volatile uint32 TSR;	// CAN transmit status register (CAN_TSR)
+	volatile uint32 RF0R;	// CAN receive FIFO 0 register (CAN_RF0R)
+	volatile uint32 RF1R;	// CAN receive FIFO 1 register (CAN_RF1R)
+	volatile uint32 IER;
+  	volatile uint32 ESR;
+  	volatile uint32 BTR;
+		uint32	RESERVED0[88];
+	CAN_TxMailBox_Port sTxMailBox[3];
+	CAN_FIFOMailBox_Port sFIFOMailBox[2];
+		uint32  RESERVED1[12];
+	volatile uint32 FMR;
+	volatile uint32 FM1R;
+		uint32	RESERVED2;
+	volatile uint32 FS1R;
+		uint32	RESERVED3;
+	volatile uint32	FFA1R;
+		uint32	RESERVED4;
+	volatile uint32	FA1R;
+		uint32	RESERVED5[8];
+	CAN_FilterRegister_Port sFilterRegister[14];
+} CAN_Port;
+
+/** 
+  * @brief  CAN Tx message structure definition  
+  */
+typedef struct
+{
+	uint32 ID;		// CAN ID
+	uint8 IDE;		// CAN_ID_STD for standard and CAN_ID_EXT for extended
+	uint8 RTR;
+	uint8 DLC;
+	uint8 Data[8];
+	uint8 FMI;
+} CanMsg;
+
+/* Functions */
+CAN_STATUS can_init_enter(CAN_Port* CANx);
+CAN_STATUS can_init_leave(CAN_Port* CANx);
+CAN_STATUS can_init(CAN_Port *CANx, uint32 mode, uint8 speed);
+CAN_STATUS can_deinit(CAN_Port* CANx);
+CAN_STATUS can_filter(CAN_Port* CANx, uint8 filter_idx,  CAN_FIFO fifo_number, CAN_FILTER_SCALE scale, CAN_FILTER_MODE mode, uint32 fr1, uint32 fr2);
+CAN_STATUS can_set_timing(CAN_Port* CANx, uint32 timing);
+CAN_STATUS can_set_mode(CAN_Port* CANx, uint32 mode);
+CAN_STATUS can_gpio_map(CAN_Port* CANx, CAN_GPIO_MAP map_mode);
+CAN_STATUS can_status(void);
+void can_cancel(CAN_Port* CANx, uint8 mbx);
+void can_rx_queue_clear(void);
+uint8 can_rx_available(void);
+CanMsg* can_rx_queue_get(void);
+CanMsg* can_read(CAN_Port* CANx, CAN_FIFO fifo, CanMsg* msg);
+void can_rx_release(CAN_Port* CANx, CAN_FIFO fifo);
+void can_rx_queue_free(void);
+CAN_TX_MBX can_transmit(CAN_Port* CANx, CanMsg* msg);
+CAN_STATUS can_tx_status(CAN_Port* CANx, CAN_TX_MBX mbx);
+
+/**
+  * @brief	Set pooling mode
+  */
+static inline void can_set_pool_mode(CAN_Port* CANx)
+{
+	CANx->IER &= ~(CAN_IER_FMPIE0 | CAN_IER_FMPIE1);
+}
+
+/**
+  * @brief	Set interrupt mode
+  */
+static inline void can_set_irq_mode(CAN_Port* CANx)
+{
+	CANx->IER |= (CAN_IER_FMPIE0 | CAN_IER_FMPIE1);
+}
+
+static inline uint8 can_fifo_ready(CAN_Port* CANx, CAN_FIFO fifo)
+{
+	if (fifo == CAN_FIFO0)
+		return (uint8)(CANx->RF0R & CAN_RF0R_FMP0);
+	return (uint8)(CANx->RF1R & CAN_RF1R_FMP1);
+}
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/STM32F1/libraries/rcc.h b/STM32F1/libraries/rcc.h
new file mode 100644
index 000000000..aa9f8d3c9
--- /dev/null
+++ b/STM32F1/libraries/rcc.h
@@ -0,0 +1,641 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Perry Hung.
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/stm32f1/include/series/rcc.h
+ * @brief STM32F1 reset and clock control (RCC) support.
+ */
+
+#ifndef _LIBMAPLE_STM32F1_RCC_H_
+#define _LIBMAPLE_STM32F1_RCC_H_
+
+#ifdef __cplusplus
+extern "C"{
+#endif
+
+#include <libmaple/libmaple_types.h>
+#include <libmaple/bitband.h>
+
+/*
+ * Register map
+ */
+
+/** STM32F1 RCC register map type */
+typedef struct rcc_reg_map {
+    __io uint32 CR;             /**< Clock control register */
+    __io uint32 CFGR;           /**< Clock configuration register */
+    __io uint32 CIR;            /**< Clock interrupt register */
+    __io uint32 APB2RSTR;       /**< APB2 peripheral reset register */
+    __io uint32 APB1RSTR;       /**< APB1 peripheral reset register */
+    __io uint32 AHBENR;         /**< AHB peripheral clock enable register */
+    __io uint32 APB2ENR;        /**< APB2 peripheral clock enable register */
+    __io uint32 APB1ENR;        /**< APB1 peripheral clock enable register */
+    __io uint32 BDCR;           /**< Backup domain control register */
+    __io uint32 CSR;            /**< Control/status register */
+} rcc_reg_map;
+
+#define RCC_BASE                        ((struct rcc_reg_map*)0x40021000)
+
+/*
+ * Register bit definitions
+ */
+
+/* Clock control register */
+
+#define RCC_CR_PLLRDY_BIT               25
+#define RCC_CR_PLLON_BIT                24
+#define RCC_CR_CSSON_BIT                19
+#define RCC_CR_HSEBYP_BIT               18
+#define RCC_CR_HSERDY_BIT               17
+#define RCC_CR_HSEON_BIT                16
+#define RCC_CR_HSIRDY_BIT               1
+#define RCC_CR_HSION_BIT                0
+
+#define RCC_CR_PLLRDY                   (1U << RCC_CR_PLLRDY_BIT)
+#define RCC_CR_PLLON                    (1U << RCC_CR_PLLON_BIT)
+#define RCC_CR_CSSON                    (1U << RCC_CR_CSSON_BIT)
+#define RCC_CR_HSEBYP                   (1U << RCC_CR_HSEBYP_BIT)
+#define RCC_CR_HSERDY                   (1U << RCC_CR_HSERDY_BIT)
+#define RCC_CR_HSEON                    (1U << RCC_CR_HSEON_BIT)
+#define RCC_CR_HSICAL                   (0xFF << 8)
+#define RCC_CR_HSITRIM                  (0x1F << 3)
+#define RCC_CR_HSIRDY                   (1U << RCC_CR_HSIRDY_BIT)
+#define RCC_CR_HSION                    (1U << RCC_CR_HSION_BIT)
+
+/* Clock configuration register */
+
+#define RCC_CFGR_USBPRE_BIT             22
+#define RCC_CFGR_PLLXTPRE_BIT           17
+#define RCC_CFGR_PLLSRC_BIT             16
+
+#define RCC_CFGR_MCO                    (0x3 << 24)
+#define RCC_CFGR_USBPRE                 (0x3 << RCC_CFGR_USBPRE_BIT)
+#define RCC_CFGR_PLLMUL                 (0xF << 18)
+#define RCC_CFGR_PLLXTPRE               (1U << RCC_CFGR_PLLXTPRE_BIT)
+#define RCC_CFGR_PLLSRC                 (1U << RCC_CFGR_PLLSRC_BIT)
+#define RCC_CFGR_ADCPRE                 (0x3 << 14)
+#define RCC_CFGR_PPRE2                  (0x7 << 11)
+#define RCC_CFGR_PPRE1                  (0x7 << 8)
+#define RCC_CFGR_HPRE                   (0xF << 4)
+#define RCC_CFGR_SWS                    (0x3 << 2)
+#define RCC_CFGR_SWS_PLL                (0x2 << 2)
+#define RCC_CFGR_SWS_HSE                (0x1 << 2)
+#define RCC_CFGR_SW                     0x3
+#define RCC_CFGR_SW_PLL                 0x2
+#define RCC_CFGR_SW_HSE                 0x1
+
+/* Clock interrupt register */
+
+#define RCC_CIR_CSSC_BIT                23
+#define RCC_CIR_PLLRDYC_BIT             20
+#define RCC_CIR_HSERDYC_BIT             19
+#define RCC_CIR_HSIRDYC_BIT             18
+#define RCC_CIR_LSERDYC_BIT             17
+#define RCC_CIR_LSIRDYC_BIT             16
+#define RCC_CIR_PLLRDYIE_BIT            12
+#define RCC_CIR_HSERDYIE_BIT            11
+#define RCC_CIR_HSIRDYIE_BIT            10
+#define RCC_CIR_LSERDYIE_BIT            9
+#define RCC_CIR_LSIRDYIE_BIT            8
+#define RCC_CIR_CSSF_BIT                7
+#define RCC_CIR_PLLRDYF_BIT             4
+#define RCC_CIR_HSERDYF_BIT             3
+#define RCC_CIR_HSIRDYF_BIT             2
+#define RCC_CIR_LSERDYF_BIT             1
+#define RCC_CIR_LSIRDYF_BIT             0
+
+#define RCC_CIR_CSSC                    (1U << RCC_CIR_CSSC_BIT)
+#define RCC_CIR_PLLRDYC                 (1U << RCC_CIR_PLLRDYC_BIT)
+#define RCC_CIR_HSERDYC                 (1U << RCC_CIR_HSERDYC_BIT)
+#define RCC_CIR_HSIRDYC                 (1U << RCC_CIR_HSIRDYC_BIT)
+#define RCC_CIR_LSERDYC                 (1U << RCC_CIR_LSERDYC_BIT)
+#define RCC_CIR_LSIRDYC                 (1U << RCC_CIR_LSIRDYC_BIT)
+#define RCC_CIR_PLLRDYIE                (1U << RCC_CIR_PLLRDYIE_BIT)
+#define RCC_CIR_HSERDYIE                (1U << RCC_CIR_HSERDYIE_BIT)
+#define RCC_CIR_HSIRDYIE                (1U << RCC_CIR_HSIRDYIE_BIT)
+#define RCC_CIR_LSERDYIE                (1U << RCC_CIR_LSERDYIE_BIT)
+#define RCC_CIR_LSIRDYIE                (1U << RCC_CIR_LSIRDYIE_BIT)
+#define RCC_CIR_CSSF                    (1U << RCC_CIR_CSSF_BIT)
+#define RCC_CIR_PLLRDYF                 (1U << RCC_CIR_PLLRDYF_BIT)
+#define RCC_CIR_HSERDYF                 (1U << RCC_CIR_HSERDYF_BIT)
+#define RCC_CIR_HSIRDYF                 (1U << RCC_CIR_HSIRDYF_BIT)
+#define RCC_CIR_LSERDYF                 (1U << RCC_CIR_LSERDYF_BIT)
+#define RCC_CIR_LSIRDYF                 (1U << RCC_CIR_LSIRDYF_BIT)
+
+/* APB2 peripheral reset register */
+
+#define RCC_APB2RSTR_TIM11RST_BIT       21
+#define RCC_APB2RSTR_TIM10RST_BIT       20
+#define RCC_APB2RSTR_TIM9RST_BIT        19
+#define RCC_APB2RSTR_ADC3RST_BIT        15
+#define RCC_APB2RSTR_USART1RST_BIT      14
+#define RCC_APB2RSTR_TIM8RST_BIT        13
+#define RCC_APB2RSTR_SPI1RST_BIT        12
+#define RCC_APB2RSTR_TIM1RST_BIT        11
+#define RCC_APB2RSTR_ADC2RST_BIT        10
+#define RCC_APB2RSTR_ADC1RST_BIT        9
+#define RCC_APB2RSTR_IOPGRST_BIT        8
+#define RCC_APB2RSTR_IOPFRST_BIT        7
+#define RCC_APB2RSTR_IOPERST_BIT        6
+#define RCC_APB2RSTR_IOPDRST_BIT        5
+#define RCC_APB2RSTR_IOPCRST_BIT        4
+#define RCC_APB2RSTR_IOPBRST_BIT        3
+#define RCC_APB2RSTR_IOPARST_BIT        2
+#define RCC_APB2RSTR_AFIORST_BIT        0
+
+#define RCC_APB2RSTR_TIM11RST           (1U << RCC_APB2RSTR_TIM11RST_BIT)
+#define RCC_APB2RSTR_TIM10RST           (1U << RCC_APB2RSTR_TIM10RST_BIT)
+#define RCC_APB2RSTR_TIM9RST            (1U << RCC_APB2RSTR_TIM9RST_BIT)
+#define RCC_APB2RSTR_ADC3RST            (1U << RCC_APB2RSTR_ADC3RST_BIT)
+#define RCC_APB2RSTR_USART1RST          (1U << RCC_APB2RSTR_USART1RST_BIT)
+#define RCC_APB2RSTR_TIM8RST            (1U << RCC_APB2RSTR_TIM8RST_BIT)
+#define RCC_APB2RSTR_SPI1RST            (1U << RCC_APB2RSTR_SPI1RST_BIT)
+#define RCC_APB2RSTR_TIM1RST            (1U << RCC_APB2RSTR_TIM1RST_BIT)
+#define RCC_APB2RSTR_ADC2RST            (1U << RCC_APB2RSTR_ADC2RST_BIT)
+#define RCC_APB2RSTR_ADC1RST            (1U << RCC_APB2RSTR_ADC1RST_BIT)
+#define RCC_APB2RSTR_IOPGRST            (1U << RCC_APB2RSTR_IOPGRST_BIT)
+#define RCC_APB2RSTR_IOPFRST            (1U << RCC_APB2RSTR_IOPFRST_BIT)
+#define RCC_APB2RSTR_IOPERST            (1U << RCC_APB2RSTR_IOPERST_BIT)
+#define RCC_APB2RSTR_IOPDRST            (1U << RCC_APB2RSTR_IOPDRST_BIT)
+#define RCC_APB2RSTR_IOPCRST            (1U << RCC_APB2RSTR_IOPCRST_BIT)
+#define RCC_APB2RSTR_IOPBRST            (1U << RCC_APB2RSTR_IOPBRST_BIT)
+#define RCC_APB2RSTR_IOPARST            (1U << RCC_APB2RSTR_IOPARST_BIT)
+#define RCC_APB2RSTR_AFIORST            (1U << RCC_APB2RSTR_AFIORST_BIT)
+
+/* APB1 peripheral reset register */
+
+#define RCC_APB1RSTR_DACRST_BIT         29
+#define RCC_APB1RSTR_PWRRST_BIT         28
+#define RCC_APB1RSTR_BKPRST_BIT         27
+#define RCC_APB1RSTR_CANRST_BIT         25
+#define RCC_APB1RSTR_USBRST_BIT         23
+#define RCC_APB1RSTR_I2C2RST_BIT        22
+#define RCC_APB1RSTR_I2C1RST_BIT        21
+#define RCC_APB1RSTR_UART5RST_BIT       20
+#define RCC_APB1RSTR_UART4RST_BIT       19
+#define RCC_APB1RSTR_USART3RST_BIT      18
+#define RCC_APB1RSTR_USART2RST_BIT      17
+#define RCC_APB1RSTR_SPI3RST_BIT        15
+#define RCC_APB1RSTR_SPI2RST_BIT        14
+#define RCC_APB1RSTR_WWDRST_BIT         11
+#define RCC_APB1RSTR_TIM14RST_BIT       8
+#define RCC_APB1RSTR_TIM13RST_BIT       7
+#define RCC_APB1RSTR_TIM12RST_BIT       6
+#define RCC_APB1RSTR_TIM7RST_BIT        5
+#define RCC_APB1RSTR_TIM6RST_BIT        4
+#define RCC_APB1RSTR_TIM5RST_BIT        3
+#define RCC_APB1RSTR_TIM4RST_BIT        2
+#define RCC_APB1RSTR_TIM3RST_BIT        1
+#define RCC_APB1RSTR_TIM2RST_BIT        0
+
+#define RCC_APB1RSTR_DACRST             (1U << RCC_APB1RSTR_DACRST_BIT)
+#define RCC_APB1RSTR_PWRRST             (1U << RCC_APB1RSTR_PWRRST_BIT)
+#define RCC_APB1RSTR_BKPRST             (1U << RCC_APB1RSTR_BKPRST_BIT)
+#define RCC_APB1RSTR_CANRST             (1U << RCC_APB1RSTR_CANRST_BIT)
+#define RCC_APB1RSTR_USBRST             (1U << RCC_APB1RSTR_USBRST_BIT)
+#define RCC_APB1RSTR_I2C2RST            (1U << RCC_APB1RSTR_I2C2RST_BIT)
+#define RCC_APB1RSTR_I2C1RST            (1U << RCC_APB1RSTR_I2C1RST_BIT)
+#define RCC_APB1RSTR_UART5RST           (1U << RCC_APB1RSTR_UART5RST_BIT)
+#define RCC_APB1RSTR_UART4RST           (1U << RCC_APB1RSTR_UART4RST_BIT)
+#define RCC_APB1RSTR_USART3RST          (1U << RCC_APB1RSTR_USART3RST_BIT)
+#define RCC_APB1RSTR_USART2RST          (1U << RCC_APB1RSTR_USART2RST_BIT)
+#define RCC_APB1RSTR_SPI3RST            (1U << RCC_APB1RSTR_SPI3RST_BIT)
+#define RCC_APB1RSTR_SPI2RST            (1U << RCC_APB1RSTR_SPI2RST_BIT)
+#define RCC_APB1RSTR_WWDRST             (1U << RCC_APB1RSTR_WWDRST_BIT)
+#define RCC_APB1RSTR_TIM14RST           (1U << RCC_APB1RSTR_TIM14RST_BIT)
+#define RCC_APB1RSTR_TIM13RST           (1U << RCC_APB1RSTR_TIM13RST_BIT)
+#define RCC_APB1RSTR_TIM12RST           (1U << RCC_APB1RSTR_TIM12RST_BIT)
+#define RCC_APB1RSTR_TIM7RST            (1U << RCC_APB1RSTR_TIM7RST_BIT)
+#define RCC_APB1RSTR_TIM6RST            (1U << RCC_APB1RSTR_TIM6RST_BIT)
+#define RCC_APB1RSTR_TIM5RST            (1U << RCC_APB1RSTR_TIM5RST_BIT)
+#define RCC_APB1RSTR_TIM4RST            (1U << RCC_APB1RSTR_TIM4RST_BIT)
+#define RCC_APB1RSTR_TIM3RST            (1U << RCC_APB1RSTR_TIM3RST_BIT)
+#define RCC_APB1RSTR_TIM2RST            (1U << RCC_APB1RSTR_TIM2RST_BIT)
+
+/* AHB peripheral clock enable register */
+
+#define RCC_AHBENR_SDIOEN_BIT           10
+#define RCC_AHBENR_FSMCEN_BIT           8
+#define RCC_AHBENR_CRCEN_BIT            7
+#define RCC_AHBENR_FLITFEN_BIT          4
+#define RCC_AHBENR_SRAMEN_BIT           2
+#define RCC_AHBENR_DMA2EN_BIT           1
+#define RCC_AHBENR_DMA1EN_BIT           0
+
+#define RCC_AHBENR_SDIOEN               (1U << RCC_AHBENR_SDIOEN_BIT)
+#define RCC_AHBENR_FSMCEN               (1U << RCC_AHBENR_FSMCEN_BIT)
+#define RCC_AHBENR_CRCEN                (1U << RCC_AHBENR_CRCEN_BIT)
+#define RCC_AHBENR_FLITFEN              (1U << RCC_AHBENR_FLITFEN_BIT)
+#define RCC_AHBENR_SRAMEN               (1U << RCC_AHBENR_SRAMEN_BIT)
+#define RCC_AHBENR_DMA2EN               (1U << RCC_AHBENR_DMA2EN_BIT)
+#define RCC_AHBENR_DMA1EN               (1U << RCC_AHBENR_DMA1EN_BIT)
+
+/* APB2 peripheral clock enable register */
+
+#define RCC_APB2ENR_TIM11EN_BIT         21
+#define RCC_APB2ENR_TIM10EN_BIT         20
+#define RCC_APB2ENR_TIM9EN_BIT          19
+#define RCC_APB2ENR_ADC3EN_BIT          15
+#define RCC_APB2ENR_USART1EN_BIT        14
+#define RCC_APB2ENR_TIM8EN_BIT          13
+#define RCC_APB2ENR_SPI1EN_BIT          12
+#define RCC_APB2ENR_TIM1EN_BIT          11
+#define RCC_APB2ENR_ADC2EN_BIT          10
+#define RCC_APB2ENR_ADC1EN_BIT          9
+#define RCC_APB2ENR_IOPGEN_BIT          8
+#define RCC_APB2ENR_IOPFEN_BIT          7
+#define RCC_APB2ENR_IOPEEN_BIT          6
+#define RCC_APB2ENR_IOPDEN_BIT          5
+#define RCC_APB2ENR_IOPCEN_BIT          4
+#define RCC_APB2ENR_IOPBEN_BIT          3
+#define RCC_APB2ENR_IOPAEN_BIT          2
+#define RCC_APB2ENR_AFIOEN_BIT          0
+
+#define RCC_APB2ENR_TIM11EN             (1U << RCC_APB2ENR_TIM11EN_BIT)
+#define RCC_APB2ENR_TIM10EN             (1U << RCC_APB2ENR_TIM10EN_BIT)
+#define RCC_APB2ENR_TIM9EN              (1U << RCC_APB2ENR_TIM9EN_BIT)
+#define RCC_APB2ENR_ADC3EN              (1U << RCC_APB2ENR_ADC3EN_BIT)
+#define RCC_APB2ENR_USART1EN            (1U << RCC_APB2ENR_USART1EN_BIT)
+#define RCC_APB2ENR_TIM8EN              (1U << RCC_APB2ENR_TIM8EN_BIT)
+#define RCC_APB2ENR_SPI1EN              (1U << RCC_APB2ENR_SPI1EN_BIT)
+#define RCC_APB2ENR_TIM1EN              (1U << RCC_APB2ENR_TIM1EN_BIT)
+#define RCC_APB2ENR_ADC2EN              (1U << RCC_APB2ENR_ADC2EN_BIT)
+#define RCC_APB2ENR_ADC1EN              (1U << RCC_APB2ENR_ADC1EN_BIT)
+#define RCC_APB2ENR_IOPGEN              (1U << RCC_APB2ENR_IOPGEN_BIT)
+#define RCC_APB2ENR_IOPFEN              (1U << RCC_APB2ENR_IOPFEN_BIT)
+#define RCC_APB2ENR_IOPEEN              (1U << RCC_APB2ENR_IOPEEN_BIT)
+#define RCC_APB2ENR_IOPDEN              (1U << RCC_APB2ENR_IOPDEN_BIT)
+#define RCC_APB2ENR_IOPCEN              (1U << RCC_APB2ENR_IOPCEN_BIT)
+#define RCC_APB2ENR_IOPBEN              (1U << RCC_APB2ENR_IOPBEN_BIT)
+#define RCC_APB2ENR_IOPAEN              (1U << RCC_APB2ENR_IOPAEN_BIT)
+#define RCC_APB2ENR_AFIOEN              (1U << RCC_APB2ENR_AFIOEN_BIT)
+
+/* APB1 peripheral clock enable register */
+
+#define RCC_APB1ENR_DACEN_BIT           29
+#define RCC_APB1ENR_PWREN_BIT           28
+#define RCC_APB1ENR_BKPEN_BIT           27
+#define RCC_APB1ENR_CANEN_BIT           25
+#define RCC_APB1ENR_USBEN_BIT           23
+#define RCC_APB1ENR_I2C2EN_BIT          22
+#define RCC_APB1ENR_I2C1EN_BIT          21
+#define RCC_APB1ENR_UART5EN_BIT         20
+#define RCC_APB1ENR_UART4EN_BIT         19
+#define RCC_APB1ENR_USART3EN_BIT        18
+#define RCC_APB1ENR_USART2EN_BIT        17
+#define RCC_APB1ENR_SPI3EN_BIT          15
+#define RCC_APB1ENR_SPI2EN_BIT          14
+#define RCC_APB1ENR_WWDEN_BIT           11
+#define RCC_APB1ENR_TIM14EN_BIT         8
+#define RCC_APB1ENR_TIM13EN_BIT         7
+#define RCC_APB1ENR_TIM12EN_BIT         6
+#define RCC_APB1ENR_TIM7EN_BIT          5
+#define RCC_APB1ENR_TIM6EN_BIT          4
+#define RCC_APB1ENR_TIM5EN_BIT          3
+#define RCC_APB1ENR_TIM4EN_BIT          2
+#define RCC_APB1ENR_TIM3EN_BIT          1
+#define RCC_APB1ENR_TIM2EN_BIT          0
+
+#define RCC_APB1ENR_DACEN               (1U << RCC_APB1ENR_DACEN_BIT)
+#define RCC_APB1ENR_PWREN               (1U << RCC_APB1ENR_PWREN_BIT)
+#define RCC_APB1ENR_BKPEN               (1U << RCC_APB1ENR_BKPEN_BIT)
+#define RCC_APB1ENR_CANEN               (1U << RCC_APB1ENR_CANEN_BIT)
+#define RCC_APB1ENR_USBEN               (1U << RCC_APB1ENR_USBEN_BIT)
+#define RCC_APB1ENR_I2C2EN              (1U << RCC_APB1ENR_I2C2EN_BIT)
+#define RCC_APB1ENR_I2C1EN              (1U << RCC_APB1ENR_I2C1EN_BIT)
+#define RCC_APB1ENR_UART5EN             (1U << RCC_APB1ENR_UART5EN_BIT)
+#define RCC_APB1ENR_UART4EN             (1U << RCC_APB1ENR_UART4EN_BIT)
+#define RCC_APB1ENR_USART3EN            (1U << RCC_APB1ENR_USART3EN_BIT)
+#define RCC_APB1ENR_USART2EN            (1U << RCC_APB1ENR_USART2EN_BIT)
+#define RCC_APB1ENR_SPI3EN              (1U << RCC_APB1ENR_SPI3EN_BIT)
+#define RCC_APB1ENR_SPI2EN              (1U << RCC_APB1ENR_SPI2EN_BIT)
+#define RCC_APB1ENR_WWDEN               (1U << RCC_APB1ENR_WWDEN_BIT)
+#define RCC_APB1ENR_TIM14EN             (1U << RCC_APB1ENR_TIM14EN_BIT)
+#define RCC_APB1ENR_TIM13EN             (1U << RCC_APB1ENR_TIM13EN_BIT)
+#define RCC_APB1ENR_TIM12EN             (1U << RCC_APB1ENR_TIM12EN_BIT)
+#define RCC_APB1ENR_TIM7EN              (1U << RCC_APB1ENR_TIM7EN_BIT)
+#define RCC_APB1ENR_TIM6EN              (1U << RCC_APB1ENR_TIM6EN_BIT)
+#define RCC_APB1ENR_TIM5EN              (1U << RCC_APB1ENR_TIM5EN_BIT)
+#define RCC_APB1ENR_TIM4EN              (1U << RCC_APB1ENR_TIM4EN_BIT)
+#define RCC_APB1ENR_TIM3EN              (1U << RCC_APB1ENR_TIM3EN_BIT)
+#define RCC_APB1ENR_TIM2EN              (1U << RCC_APB1ENR_TIM2EN_BIT)
+
+/* Backup domain control register */
+
+#define RCC_BDCR_BDRST_BIT              16
+#define RCC_BDCR_RTCEN_BIT              15
+#define RCC_BDCR_LSEBYP_BIT             2
+#define RCC_BDCR_LSERDY_BIT             1
+#define RCC_BDCR_LSEON_BIT              0
+
+#define RCC_BDCR_BDRST                  (1U << RCC_BDCR_BDRST_BIT)
+#define RCC_BDCR_RTCEN                  (1U << RCC_BDCR_RTC_BIT)
+#define RCC_BDCR_RTCSEL                 (0x3 << 8)
+#define RCC_BDCR_RTCSEL_NONE            (0x0 << 8)
+#define RCC_BDCR_RTCSEL_LSE             (0x1 << 8)
+#define RCC_BDCR_RTCSEL_LSI             (0x2 << 8) // added to support RTClock
+#define RCC_BDCR_RTCSEL_HSE             (0x3 << 8)
+#define RCC_BDCR_LSEBYP                 (1U << RCC_BDCR_LSEBYP_BIT)
+#define RCC_BDCR_LSERDY                 (1U << RCC_BDCR_LSERDY_BIT)
+#define RCC_BDCR_LSEON                  (1U << RCC_BDCR_LSEON_BIT)
+
+/* Control/status register */
+
+#define RCC_CSR_LPWRRSTF_BIT            31
+#define RCC_CSR_WWDGRSTF_BIT            30
+#define RCC_CSR_IWDGRSTF_BIT            29
+#define RCC_CSR_SFTRSTF_BIT             28
+#define RCC_CSR_PORRSTF_BIT             27
+#define RCC_CSR_PINRSTF_BIT             26
+#define RCC_CSR_RMVF_BIT                24
+#define RCC_CSR_LSIRDY_BIT              1
+#define RCC_CSR_LSION_BIT               0
+
+#define RCC_CSR_LPWRRSTF                (1U << RCC_CSR_LPWRRSTF_BIT)
+#define RCC_CSR_WWDGRSTF                (1U << RCC_CSR_WWDGRSTF_BIT)
+#define RCC_CSR_IWDGRSTF                (1U << RCC_CSR_IWDGRSTF_BIT)
+#define RCC_CSR_SFTRSTF                 (1U << RCC_CSR_SFTRSTF_BIT)
+#define RCC_CSR_PORRSTF                 (1U << RCC_CSR_PORRSTF_BIT)
+#define RCC_CSR_PINRSTF                 (1U << RCC_CSR_PINRSTF_BIT)
+#define RCC_CSR_RMVF                    (1U << RCC_CSR_RMVF_BIT)
+#define RCC_CSR_LSIRDY                  (1U << RCC_CSR_LSIRDY_BIT)
+#define RCC_CSR_LSION                   (1U << RCC_CSR_LSION_BIT)
+
+/*
+ * libmaple-mandated enumeration types.
+ */
+
+/**
+ * @brief STM32F1 rcc_clk_id.
+ */
+typedef enum rcc_clk_id {
+    RCC_ADC1,
+    RCC_ADC2,
+    RCC_ADC3,
+    RCC_AFIO,
+    RCC_BKP,
+    RCC_CRC,
+    RCC_DAC,
+    RCC_DMA1,
+    RCC_DMA2,
+    RCC_FLITF,
+    RCC_FSMC,
+    RCC_GPIOA,
+    RCC_GPIOB,
+    RCC_GPIOC,
+    RCC_GPIOD,
+    RCC_GPIOE,
+    RCC_GPIOF,
+    RCC_GPIOG,
+    RCC_I2C1,
+    RCC_I2C2,
+    RCC_PWR,
+    RCC_SDIO,
+    RCC_SPI1,
+    RCC_SPI2,
+    RCC_SPI3,
+    RCC_SRAM,
+    RCC_TIMER1,
+    RCC_TIMER2,
+    RCC_TIMER3,
+    RCC_TIMER4,
+    RCC_TIMER5,
+    RCC_TIMER6,
+    RCC_TIMER7,
+    RCC_TIMER8,
+    RCC_TIMER9,
+    RCC_TIMER10,
+    RCC_TIMER11,
+    RCC_TIMER12,
+    RCC_TIMER13,
+    RCC_TIMER14,
+    RCC_USART1,
+    RCC_USART2,
+    RCC_USART3,
+    RCC_UART4,
+    RCC_UART5,
+    RCC_USB,
+	RCC_CAN,	//! JMD after X893
+} rcc_clk_id;
+
+/**
+ * @brief STM32F1 PLL clock sources.
+ * @see rcc_configure_pll()
+ */
+typedef enum rcc_pllsrc {
+    RCC_PLLSRC_HSE = (0x1 << 16),
+    RCC_PLLSRC_HSI_DIV_2 = (0x0 << 16)
+} rcc_pllsrc;
+
+/**
+ * @brief STM32F1 clock domains.
+ * @see rcc_dev_clk()
+ */
+typedef enum rcc_clk_domain {
+    RCC_APB1,
+    RCC_APB2,
+    RCC_AHB
+} rcc_clk_domain;
+
+/**
+ * @brief STM32F1 Prescaler identifiers
+ * @see rcc_set_prescaler()
+ */
+typedef enum rcc_prescaler {
+    RCC_PRESCALER_AHB,
+    RCC_PRESCALER_APB1,
+    RCC_PRESCALER_APB2,
+    RCC_PRESCALER_USB,
+    RCC_PRESCALER_ADC
+} rcc_prescaler;
+
+/**
+ * @brief STM32F1 ADC prescaler dividers
+ * @see rcc_set_prescaler()
+ */
+typedef enum rcc_adc_divider {
+    RCC_ADCPRE_PCLK_DIV_2 = 0x0 << 14,
+    RCC_ADCPRE_PCLK_DIV_4 = 0x1 << 14,
+    RCC_ADCPRE_PCLK_DIV_6 = 0x2 << 14,
+    RCC_ADCPRE_PCLK_DIV_8 = 0x3 << 14,
+} rcc_adc_divider;
+
+/**
+ * @brief STM32F1 APB1 prescaler dividers
+ * @see rcc_set_prescaler()
+ */
+typedef enum rcc_apb1_divider {
+    RCC_APB1_HCLK_DIV_1 = 0x0 << 8,
+    RCC_APB1_HCLK_DIV_2 = 0x4 << 8,
+    RCC_APB1_HCLK_DIV_4 = 0x5 << 8,
+    RCC_APB1_HCLK_DIV_8 = 0x6 << 8,
+    RCC_APB1_HCLK_DIV_16 = 0x7 << 8,
+} rcc_apb1_divider;
+
+/**
+ * @brief STM32F1 APB2 prescaler dividers
+ * @see rcc_set_prescaler()
+ */
+typedef enum rcc_apb2_divider {
+    RCC_APB2_HCLK_DIV_1 = 0x0 << 11,
+    RCC_APB2_HCLK_DIV_2 = 0x4 << 11,
+    RCC_APB2_HCLK_DIV_4 = 0x5 << 11,
+    RCC_APB2_HCLK_DIV_8 = 0x6 << 11,
+    RCC_APB2_HCLK_DIV_16 = 0x7 << 11,
+} rcc_apb2_divider;
+
+/**
+ * @brief STM32F1 AHB prescaler dividers
+ * @see rcc_set_prescaler()
+ */
+typedef enum rcc_ahb_divider {
+    RCC_AHB_SYSCLK_DIV_1 = 0x0 << 4,
+    RCC_AHB_SYSCLK_DIV_2 = 0x8 << 4,
+    RCC_AHB_SYSCLK_DIV_4 = 0x9 << 4,
+    RCC_AHB_SYSCLK_DIV_8 = 0xA << 4,
+    RCC_AHB_SYSCLK_DIV_16 = 0xB << 4,
+    RCC_AHB_SYSCLK_DIV_32 = 0xC << 4,
+    RCC_AHB_SYSCLK_DIV_64 = 0xD << 4,
+    RCC_AHB_SYSCLK_DIV_128 = 0xD << 4,
+    RCC_AHB_SYSCLK_DIV_256 = 0xE << 4,
+    RCC_AHB_SYSCLK_DIV_512 = 0xF << 4,
+} rcc_ahb_divider;
+
+/**
+ * @brief STM32F1 USB prescaler dividers
+ * @see rcc_set_prescaler()
+ */
+ /*
+ Set and reset by software to control the USB clock prescaler value. The USB clock
+must be 48MHz. These bits can’t be reset if the USB clock is enabled.
+00: (CK_PLL / 1.5) selected
+01: CK_PLL selected
+ */
+ 
+typedef enum rcc_usb_divider {
+    RCC_USB_SYSCLK_DIV_1 = 0x1 << 22,
+    RCC_USB_SYSCLK_DIV_1_5 = 0x0 << 22,
+    RCC_USB_SYSCLK_DIV_2 = 0x3 << 22,
+    RCC_USB_SYSCLK_DIV_2_5 = 0x2 << 22,
+} rcc_usb_divider;
+
+
+/**
+ * @brief Start the low speed internal oscillator
+ */
+static inline void rcc_start_lsi(void) {
+	*bb_perip(&RCC_BASE->CSR, RCC_CSR_LSION_BIT) = 1;
+	while (*bb_perip(&RCC_BASE->CSR, RCC_CSR_LSIRDY_BIT) == 0);
+}
+
+/**
+ * @brief STM32F1 clock sources.
+ */
+typedef enum rcc_clk {
+    RCC_CLK_PLL    = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) |
+                              RCC_CR_PLLON_BIT), /**< Main PLL, clocked by
+                                                    HSI or HSE. */
+    RCC_CLK_HSE    = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) |
+                              RCC_CR_HSEON_BIT), /**< High speed external. */
+    RCC_CLK_HSI    = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) |
+                              RCC_CR_HSION_BIT), /**< High speed internal. */
+    RCC_CLK_LSE    = (uint16)((offsetof(struct rcc_reg_map, BDCR) << 8) |
+                              RCC_BDCR_LSEON_BIT), /**< Low-speed external
+                                                    * (32.768 KHz). */
+    RCC_CLK_LSI    = (uint16)((offsetof(struct rcc_reg_map, CSR) << 8) |
+                              RCC_CSR_LSION_BIT), /**< Low-speed internal
+                                                   * (approximately 32 KHz). */
+} rcc_clk;
+
+/**
+ * @brief STM32F1 PLL multipliers.
+ */
+typedef enum rcc_pll_multiplier {
+    RCC_PLLMUL_2 = (0x0 << 18),
+    RCC_PLLMUL_3 = (0x1 << 18),
+    RCC_PLLMUL_4 = (0x2 << 18),
+    RCC_PLLMUL_5 = (0x3 << 18),
+    RCC_PLLMUL_6 = (0x4 << 18),
+    RCC_PLLMUL_7 = (0x5 << 18),
+    RCC_PLLMUL_8 = (0x6 << 18),
+    RCC_PLLMUL_9 = (0x7 << 18),
+    RCC_PLLMUL_10 = (0x8 << 18),
+    RCC_PLLMUL_11 = (0x9 << 18),
+    RCC_PLLMUL_12 = (0xA << 18),
+    RCC_PLLMUL_13 = (0xB << 18),
+    RCC_PLLMUL_14 = (0xC << 18),
+    RCC_PLLMUL_15 = (0xD << 18),
+    RCC_PLLMUL_16 = (0xE << 18),
+} rcc_pll_multiplier;
+
+/* FIXME [0.0.13] Just have data point to an rcc_pll_multiplier! */
+/**
+ * @brief Start the low speed external oscillatior
+ */
+static inline void rcc_start_lse(void) {
+	bb_peri_set_bit(&RCC_BASE->BDCR, RCC_BDCR_LSEBYP_BIT, 0);
+	bb_peri_set_bit(&RCC_BASE->BDCR, RCC_BDCR_LSEON_BIT, 1);
+	while (bb_peri_get_bit(&RCC_BASE->BDCR, RCC_BDCR_LSERDY_BIT ) == 0);
+}
+
+/**
+ * @brief STM32F1 PLL configuration values.
+ * Point to one of these with the "data" field in a struct rcc_pll_cfg.
+ * @see struct rcc_pll_cfg.
+ */
+typedef struct stm32f1_rcc_pll_data {
+     rcc_pll_multiplier pll_mul; /**< PLL multiplication factor. */
+} stm32f1_rcc_pll_data;
+
+/*
+ * Deprecated bits.
+ */
+static inline void rcc_start_hse(void) {				// Added to support RTClock
+//	*bb_perip(&RCC_BASE->CR, RCC_CR_HSEON_BIT) = 1;
+	while (bb_peri_get_bit(&RCC_BASE->CR, RCC_CR_HSERDY_BIT) == 0);
+}
+
+/**
+ * @brief Deprecated; STM32F1 only.
+ *
+ * Initialize the clock control system. Initializes the system
+ * clock source to use the PLL driven by an external oscillator.
+ *
+ * @param sysclk_src system clock source, must be PLL
+ * @param pll_src pll clock source, must be HSE
+ * @param pll_mul pll multiplier
+ */
+__deprecated
+void rcc_clk_init(rcc_sysclk_src sysclk_src,
+                  rcc_pllsrc pll_src,
+                  rcc_pll_multiplier pll_mul);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
diff --git a/STM32F1/libraries/rcc_f1.c b/STM32F1/libraries/rcc_f1.c
new file mode 100644
index 000000000..9040a4dc2
--- /dev/null
+++ b/STM32F1/libraries/rcc_f1.c
@@ -0,0 +1,174 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 Perry Hung.
+ * Copyright (c) 2011 LeafLabs, LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be
+ * included in all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/stm32f1/rcc.c
+ * @brief STM32F1 RCC.
+ */
+
+#include <libmaple/rcc.h>
+#include <libmaple/libmaple.h>
+#include <libmaple/bitband.h>
+
+#include "rcc_private.h"
+
+#define APB1                            RCC_APB1
+#define APB2                            RCC_APB2
+#define AHB                             RCC_AHB
+
+/* Device descriptor table, maps rcc_clk_id onto bus and enable/reset
+ * register bit numbers. */
+const struct rcc_dev_info rcc_dev_table[] = {
+    [RCC_GPIOA]  = { .clk_domain = APB2, .line_num = 2 },
+    [RCC_GPIOB]  = { .clk_domain = APB2, .line_num = 3 },
+    [RCC_GPIOC]  = { .clk_domain = APB2, .line_num = 4 },
+    [RCC_GPIOD]  = { .clk_domain = APB2, .line_num = 5 },
+    [RCC_AFIO]   = { .clk_domain = APB2, .line_num = 0 },
+    [RCC_ADC1]   = { .clk_domain = APB2, .line_num = 9 },
+    [RCC_ADC2]   = { .clk_domain = APB2, .line_num = 10 },
+    [RCC_ADC3]   = { .clk_domain = APB2, .line_num = 15 },
+    [RCC_USART1] = { .clk_domain = APB2, .line_num = 14 },
+    [RCC_USART2] = { .clk_domain = APB1, .line_num = 17 },
+    [RCC_USART3] = { .clk_domain = APB1, .line_num = 18 },
+    [RCC_TIMER1] = { .clk_domain = APB2, .line_num = 11 },
+    [RCC_TIMER2] = { .clk_domain = APB1, .line_num = 0 },
+    [RCC_TIMER3] = { .clk_domain = APB1, .line_num = 1 },
+    [RCC_TIMER4] = { .clk_domain = APB1, .line_num = 2 },
+    [RCC_SPI1]   = { .clk_domain = APB2, .line_num = 12 },
+    [RCC_SPI2]   = { .clk_domain = APB1, .line_num = 14 },
+    [RCC_DMA1]   = { .clk_domain = AHB,  .line_num = 0 },
+    [RCC_PWR]    = { .clk_domain = APB1, .line_num = 28},
+    [RCC_BKP]    = { .clk_domain = APB1, .line_num = 27},
+    [RCC_I2C1]   = { .clk_domain = APB1, .line_num = 21 },
+    [RCC_I2C2]   = { .clk_domain = APB1, .line_num = 22 },
+    [RCC_CRC]    = { .clk_domain = AHB,  .line_num = 6},
+    [RCC_FLITF]  = { .clk_domain = AHB,  .line_num = 4},
+    [RCC_SRAM]   = { .clk_domain = AHB,  .line_num = 2},
+    [RCC_USB]    = { .clk_domain = APB1, .line_num = 23},
+#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
+    [RCC_GPIOE]  = { .clk_domain = APB2, .line_num = 6 },
+    [RCC_GPIOF]  = { .clk_domain = APB2, .line_num = 7 },
+    [RCC_GPIOG]  = { .clk_domain = APB2, .line_num = 8 },
+    [RCC_UART4]  = { .clk_domain = APB1, .line_num = 19 },
+    [RCC_UART5]  = { .clk_domain = APB1, .line_num = 20 },
+    [RCC_TIMER5] = { .clk_domain = APB1, .line_num = 3 },
+    [RCC_TIMER6] = { .clk_domain = APB1, .line_num = 4 },
+    [RCC_TIMER7] = { .clk_domain = APB1, .line_num = 5 },
+    [RCC_TIMER8] = { .clk_domain = APB2, .line_num = 13 },
+    [RCC_FSMC]   = { .clk_domain = AHB,  .line_num = 8 },
+    [RCC_DAC]    = { .clk_domain = APB1, .line_num = 29 },
+    [RCC_DMA2]   = { .clk_domain = AHB,  .line_num = 1 },
+    [RCC_SDIO]   = { .clk_domain = AHB,  .line_num = 10 },
+    [RCC_SPI3]   = { .clk_domain = APB1, .line_num = 15 },
+#endif
+#ifdef STM32_XL_DENSITY
+    [RCC_TIMER9]  = { .clk_domain = APB2, .line_num = 19 },
+    [RCC_TIMER10] = { .clk_domain = APB2, .line_num = 20 },
+    [RCC_TIMER11] = { .clk_domain = APB2, .line_num = 21 },
+    [RCC_TIMER12] = { .clk_domain = APB1, .line_num = 6 },
+    [RCC_TIMER13] = { .clk_domain = APB1, .line_num = 7 },
+    [RCC_TIMER14] = { .clk_domain = APB1, .line_num = 8 },
+#endif
+	[RCC_CAN]	= { .clk_domain = APB1, .line_num = 25 },	//! JMD after X893
+};
+
+__deprecated
+void rcc_clk_init(rcc_sysclk_src sysclk_src,
+                  rcc_pllsrc pll_src,
+                  rcc_pll_multiplier pll_mul) {
+    /* Assume that we're going to clock the chip off the PLL, fed by
+     * the HSE */
+    ASSERT(sysclk_src == RCC_CLKSRC_PLL &&
+           pll_src    == RCC_PLLSRC_HSE);
+
+    RCC_BASE->CFGR = pll_src | pll_mul | (0x3<<22);
+
+    /* Turn on, and wait for, HSE. */
+    rcc_turn_on_clk(RCC_CLK_HSE);
+    while (!rcc_is_clk_ready(RCC_CLK_HSE))
+        ;
+
+    /* Do the same for the main PLL. */
+    rcc_turn_on_clk(RCC_CLK_PLL);
+    while(!rcc_is_clk_ready(RCC_CLK_PLL))
+        ;
+
+    /* Finally, switch over to the PLL. */
+    rcc_switch_sysclk(RCC_CLKSRC_PLL);
+}
+
+/* pll_cfg->data must point to a valid struct stm32f1_rcc_pll_data. */
+void rcc_configure_pll(rcc_pll_cfg *pll_cfg) {
+    stm32f1_rcc_pll_data *data = pll_cfg->data;
+    rcc_pll_multiplier pll_mul = data->pll_mul;
+    uint32 cfgr;
+    /* Check that the PLL is disabled. */
+    ASSERT_FAULT(!rcc_is_clk_on(RCC_CLK_PLL));
+
+    cfgr = RCC_BASE->CFGR;
+    cfgr &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL);
+    cfgr |= pll_cfg->pllsrc | pll_mul;
+
+    RCC_BASE->CFGR = cfgr;
+}
+
+void rcc_clk_enable(rcc_clk_id id) {
+    static __io uint32* enable_regs[] = {
+        [APB1] = &RCC_BASE->APB1ENR,
+        [APB2] = &RCC_BASE->APB2ENR,
+        [AHB] = &RCC_BASE->AHBENR,
+    };
+    rcc_do_clk_enable(enable_regs, id);
+}
+
+void rcc_reset_dev(rcc_clk_id id) {
+    static __io uint32* reset_regs[] = {
+        [APB1] = &RCC_BASE->APB1RSTR,
+        [APB2] = &RCC_BASE->APB2RSTR,
+    };
+    rcc_do_reset_dev(reset_regs, id);
+}
+
+void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider) {
+    static const uint32 masks[] = {
+        [RCC_PRESCALER_AHB] = RCC_CFGR_HPRE,
+        [RCC_PRESCALER_APB1] = RCC_CFGR_PPRE1,
+        [RCC_PRESCALER_APB2] = RCC_CFGR_PPRE2,
+        [RCC_PRESCALER_USB] = RCC_CFGR_USBPRE,
+        [RCC_PRESCALER_ADC] = RCC_CFGR_ADCPRE,
+    };
+    rcc_do_set_prescaler(masks, prescaler, divider);
+}
+
+void rcc_clk_disable(rcc_clk_id id) {
+    static __io uint32* enable_regs[] = {
+        [APB1] = &RCC_BASE->APB1ENR,
+        [APB2] = &RCC_BASE->APB2ENR,
+        [AHB] = &RCC_BASE->AHBENR,
+    };
+    rcc_do_clk_disable(enable_regs, id);
+}
\ No newline at end of file
diff --git a/STM32F1/libraries/usb.c b/STM32F1/libraries/usb.c
new file mode 100644
index 000000000..f7965351a
--- /dev/null
+++ b/STM32F1/libraries/usb.c
@@ -0,0 +1,402 @@
+/******************************************************************************
+ * The MIT License
+ *
+ * Copyright (c) 2010 LeafLabs LLC.
+ *
+ * Permission is hereby granted, free of charge, to any person
+ * obtaining a copy of this software and associated documentation
+ * files (the "Software"), to deal in the Software without
+ * restriction, including without limitation the rights to use, copy,
+ * modify, merge, publish, distribute, sublicense, and/or sell copies
+ * of the Software, and to permit persons to whom the Software is
+ * furnished to do so, subject to the following conditions:
+ *
+ * The above copyright notice and this permission notice shall be included in
+ * all copies or substantial portions of the Software.
+ *
+ * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
+ * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
+ * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
+ * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
+ * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
+ * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
+ * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
+ * SOFTWARE.
+ *****************************************************************************/
+
+/**
+ * @file libmaple/usb/stm32f1/usb.c
+ * @brief USB support.
+ *
+ * This is a mess.
+ */
+
+#include <libmaple/usb.h>
+
+#include <libmaple/libmaple.h>
+#include <libmaple/rcc.h>
+
+/* Private headers */
+#include "usb_reg_map.h"
+#include "usb_lib_globals.h"
+
+/* usb_lib headers */
+#include "usb_type.h"
+#include "usb_core.h"
+
+static void dispatch_ctr_lp(void);
+
+/*
+ * usb_lib/ globals
+ */
+
+uint16 SaveTState;              /* caches TX status for later use */
+uint16 SaveRState;              /* caches RX status for later use */
+
+/*
+ * Other state
+ */
+
+typedef enum {
+    RESUME_EXTERNAL,
+    RESUME_INTERNAL,
+    RESUME_LATER,
+    RESUME_WAIT,
+    RESUME_START,
+    RESUME_ON,
+    RESUME_OFF,
+    RESUME_ESOF
+} RESUME_STATE;
+
+struct {
+    volatile RESUME_STATE eState;
+    volatile uint8 bESOFcnt;
+} ResumeS;
+
+static usblib_dev usblib = {
+    .irq_mask = USB_ISR_MSK,
+    .state = USB_UNCONNECTED,
+    .prevState = USB_UNCONNECTED,
+    .clk_id = RCC_USB,
+};
+usblib_dev *USBLIB = &usblib;
+
+/*
+ * Routines
+ */
+
+void usb_init_usblib(usblib_dev *dev,
+                     void (**ep_int_in)(void),
+                     void (**ep_int_out)(void)) {
+    rcc_clk_enable(dev->clk_id);
+
+    dev->ep_int_in = ep_int_in;
+    dev->ep_int_out = ep_int_out;
+
+    /* usb_lib/ declares both and then assumes that pFoo points to Foo
+     * (even though the names don't always match), which is stupid for
+     * all of the obvious reasons, but whatever.  Here we are. */
+    pInformation = &Device_Info;
+    pProperty = &Device_Property;
+    pUser_Standard_Requests = &User_Standard_Requests;
+
+    pInformation->ControlState = 2; /* FIXME [0.0.12] use
+                                       CONTROL_STATE enumerator */
+    pProperty->Init();
+}
+
+static void usb_suspend(void) {
+    uint16 cntr;
+
+    /* TODO decide if read/modify/write is really what we want
+     * (e.g. usb_resume_init() reconfigures CNTR). */
+    cntr = USB_BASE->CNTR;
+    cntr |= USB_CNTR_FSUSP;
+    USB_BASE->CNTR = cntr;
+    cntr |= USB_CNTR_LP_MODE;
+    USB_BASE->CNTR = cntr;
+
+    USBLIB->prevState = USBLIB->state;
+    USBLIB->state = USB_SUSPENDED;
+}
+
+static void usb_resume_init(void) {
+    uint16 cntr;
+
+    cntr = USB_BASE->CNTR;
+    cntr &= ~USB_CNTR_LP_MODE;
+    USB_BASE->CNTR = cntr;
+
+    /* Enable interrupt lines */
+    USB_BASE->CNTR = USB_ISR_MSK;
+}
+
+static void usb_resume(RESUME_STATE eResumeSetVal) {
+    uint16 cntr;
+
+    if (eResumeSetVal != RESUME_ESOF) {
+        ResumeS.eState = eResumeSetVal;
+    }
+
+    switch (ResumeS.eState) {
+    case RESUME_EXTERNAL:
+        usb_resume_init();
+        ResumeS.eState = RESUME_OFF;
+        USBLIB->state = USBLIB->prevState;
+        break;
+    case RESUME_INTERNAL:
+        usb_resume_init();
+        ResumeS.eState = RESUME_START;
+        break;
+    case RESUME_LATER:
+        ResumeS.bESOFcnt = 2;
+        ResumeS.eState = RESUME_WAIT;
+        break;
+    case RESUME_WAIT:
+        ResumeS.bESOFcnt--;
+        if (ResumeS.bESOFcnt == 0) {
+            ResumeS.eState = RESUME_START;
+        }
+        break;
+    case RESUME_START:
+        cntr = USB_BASE->CNTR;
+        cntr |= USB_CNTR_RESUME;
+        USB_BASE->CNTR = cntr;
+        ResumeS.eState = RESUME_ON;
+        ResumeS.bESOFcnt = 10;
+        break;
+    case RESUME_ON:
+        ResumeS.bESOFcnt--;
+        if (ResumeS.bESOFcnt == 0) {
+            cntr = USB_BASE->CNTR;
+            cntr &= ~USB_CNTR_RESUME;
+            USB_BASE->CNTR = cntr;
+            USBLIB->state = USBLIB->prevState;
+            ResumeS.eState = RESUME_OFF;
+        }
+        break;
+    case RESUME_OFF:
+    case RESUME_ESOF:
+    default:
+        ResumeS.eState = RESUME_OFF;
+        break;
+    }
+}
+
+// JMD : default ISRs of CAN, to be overridden if HardwareCAN library is used in sketch
+void __attribute__((weak)) USB_HP_CAN_TX_IRQHandler(void) 
+{ ; }      // Dummy ISR
+
+void __irq_usb_hp_can_tx(void)
+{
+  USB_HP_CAN_TX_IRQHandler () ;
+}
+
+uint8 __attribute__((weak)) CAN_RX0_IRQ_Handler(void)
+{ return 0 ; }      // Dummy ISR 
+
+#define SUSPEND_ENABLED 1
+void __irq_usb_lp_can_rx0(void) {
+    uint16 istr = USB_BASE->ISTR;
+
+	if (CAN_RX0_IRQ_Handler())			//! JMD : Call to CAN ISR, returns 1 CAN is active
+		return;							//! JMD
+
+    /* Use USB_ISR_MSK to only include code for bits we care about. */
+
+#if (USB_ISR_MSK & USB_ISTR_RESET)
+    if (istr & USB_ISTR_RESET & USBLIB->irq_mask) {
+        USB_BASE->ISTR = ~USB_ISTR_RESET;
+        pProperty->Reset();
+    }
+#endif
+
+#if (USB_ISR_MSK & USB_ISTR_PMAOVR)
+    if (istr & ISTR_PMAOVR & USBLIB->irq_mask) {
+        USB_BASE->ISTR = ~USB_ISTR_PMAOVR;
+    }
+#endif
+
+#if (USB_ISR_MSK & USB_ISTR_ERR)
+    if (istr & USB_ISTR_ERR & USBLIB->irq_mask) {
+        USB_BASE->ISTR = ~USB_ISTR_ERR;
+    }
+#endif
+
+#if (USB_ISR_MSK & USB_ISTR_WKUP)
+    if (istr & USB_ISTR_WKUP & USBLIB->irq_mask) {
+        USB_BASE->ISTR = ~(USB_ISTR_WKUP | USB_ISTR_SUSP);
+        usb_resume(RESUME_EXTERNAL);
+    }
+#endif
+
+#if (USB_ISR_MSK & USB_ISTR_SUSP)
+    if (istr & USB_ISTR_SUSP & USBLIB->irq_mask) {
+        /* check if SUSPEND is possible */
+        if (SUSPEND_ENABLED) {
+            usb_suspend();
+        } else {
+            /* if not possible then resume after xx ms */
+            usb_resume(RESUME_LATER);
+        }
+        /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
+        USB_BASE->ISTR = ~(USB_ISTR_WKUP | USB_ISTR_SUSP);
+    }
+#endif
+
+#if (USB_ISR_MSK & USB_ISTR_SOF)
+    if (istr & USB_ISTR_SOF & USBLIB->irq_mask) {
+        USB_BASE->ISTR = ~USB_ISTR_SOF;
+    }
+#endif
+
+#if (USB_ISR_MSK & USB_ISTR_ESOF)
+    if (istr & USB_ISTR_ESOF & USBLIB->irq_mask) {
+        USB_BASE->ISTR = ~USB_ISTR_ESOF;
+        /* resume handling timing is made with ESOFs */
+        usb_resume(RESUME_ESOF); /* request without change of the machine state */
+    }
+#endif
+
+    /*
+     * Service the correct transfer interrupt.
+     */
+
+#if (USB_ISR_MSK & USB_ISTR_CTR)
+    if (istr & USB_ISTR_CTR & USBLIB->irq_mask) {
+        dispatch_ctr_lp();
+    }
+#endif
+}
+
+/*
+ * Auxiliary routines
+ */
+
+static inline uint8 dispatch_endpt_zero(uint16 istr_dir);
+static inline void dispatch_endpt(uint8 ep);
+static inline void set_rx_tx_status0(uint16 rx, uint16 tx);
+
+static void handle_setup0(void);
+static void handle_in0(void);
+static void handle_out0(void);
+
+static void dispatch_ctr_lp() {
+    uint16 istr;
+    while (((istr = USB_BASE->ISTR) & USB_ISTR_CTR) != 0) {
+        /* TODO WTF, figure this out: RM0008 says CTR is read-only,
+         * but ST's firmware claims it's clear-only, and emphasizes
+         * the importance of clearing it in more than one place. */
+        USB_BASE->ISTR = ~USB_ISTR_CTR;
+        uint8 ep_id = istr & USB_ISTR_EP_ID;
+        if (ep_id == 0) {
+            /* TODO figure out why it's OK to break out of the loop
+             * once we're done serving endpoint zero, but not okay if
+             * there are multiple nonzero endpoint transfers to
+             * handle. */
+            if (dispatch_endpt_zero(istr & USB_ISTR_DIR)) {
+                return;
+            }
+        } else {
+            dispatch_endpt(ep_id);
+        }
+    }
+}
+
+/* FIXME Dataflow on endpoint 0 RX/TX status is based off of ST's
+ * code, and is ugly/confusing in its use of SaveRState/SaveTState.
+ * Fixing this requires filling in handle_in0(), handle_setup0(),
+ * handle_out0(). */
+static inline uint8 dispatch_endpt_zero(uint16 istr_dir) {
+    uint32 epr = (uint16)USB_BASE->EP[0];
+
+    if (!(epr & (USB_EP_CTR_TX | USB_EP_SETUP | USB_EP_CTR_RX))) {
+        return 0;
+    }
+
+    /* Cache RX/TX statuses in SaveRState/SaveTState, respectively.
+     * The various handle_foo0() may clobber these values
+     * before we reset them at the end of this routine. */
+    SaveRState = epr & USB_EP_STAT_RX;
+    SaveTState = epr & USB_EP_STAT_TX;
+
+    /* Set actual RX/TX statuses to NAK while we're thinking */
+    set_rx_tx_status0(USB_EP_STAT_RX_NAK, USB_EP_STAT_TX_NAK);
+
+    if (istr_dir == 0) {
+        /* ST RM0008: "If DIR bit=0, CTR_TX bit is set in the USB_EPnR
+         * register related to the interrupting endpoint.  The
+         * interrupting transaction is of IN type (data transmitted by
+         * the USB peripheral to the host PC)." */
+        ASSERT_FAULT(epr & USB_EP_CTR_TX);
+        usb_clear_ctr_tx(USB_EP0);
+        handle_in0();
+    } else {
+        /* RM0008: "If DIR bit=1, CTR_RX bit or both CTR_TX/CTR_RX
+         * are set in the USB_EPnR register related to the
+         * interrupting endpoint. The interrupting transaction is of
+         * OUT type (data received by the USB peripheral from the host
+         * PC) or two pending transactions are waiting to be
+         * processed."
+         *
+         * [mbolivar] Note how the following control flow (which
+         * replicates ST's) doesn't seem to actually handle both
+         * interrupts that are ostensibly pending when both CTR_RX and
+         * CTR_TX are set.
+         *
+         * TODO sort this mess out.
+         */
+        if (epr & USB_EP_CTR_TX) {
+            usb_clear_ctr_tx(USB_EP0);
+            handle_in0();
+        } else {                /* SETUP or CTR_RX */
+            /* SETUP is held constant while CTR_RX is set, so clear it
+             * either way */
+            usb_clear_ctr_rx(USB_EP0);
+            if (epr & USB_EP_SETUP) {
+                handle_setup0();
+            } else {            /* CTR_RX */
+                handle_out0();
+            }
+        }
+    }
+
+    set_rx_tx_status0(SaveRState, SaveTState);
+    return 1;
+}
+
+static inline void dispatch_endpt(uint8 ep) {
+    uint32 epr = USB_BASE->EP[ep];
+    /* If ISTR_CTR is set and the ISTR gave us this EP_ID to handle,
+     * then presumably at least one of CTR_RX and CTR_TX is set, but
+     * again, ST's control flow allows for the possibility of neither.
+     *
+     * TODO try to find out if neither being set is possible. */
+    if (epr & USB_EP_CTR_RX) {
+        usb_clear_ctr_rx(ep);
+        (USBLIB->ep_int_out[ep - 1])();
+    }
+    if (epr & USB_EP_CTR_TX) {
+        usb_clear_ctr_tx(ep);
+        (USBLIB->ep_int_in[ep - 1])();
+    }
+}
+
+static inline void set_rx_tx_status0(uint16 rx, uint16 tx) {
+    usb_set_ep_rx_stat(USB_EP0, rx);
+    usb_set_ep_tx_stat(USB_EP0, tx);
+}
+
+/* TODO Rip out usb_lib/ dependency from the following functions: */
+
+static void handle_setup0(void) {
+    Setup0_Process();
+}
+
+static void handle_in0(void) {
+    In0_Process();
+}
+
+static void handle_out0(void) {
+    Out0_Process();
+}

From 45c64ed5395270acb4f4ee4104efe4197d13e345 Mon Sep 17 00:00:00 2001
From: Phonog <jeanmarc.delaplace@gmail.com>
Date: Mon, 31 Oct 2016 22:33:52 +0100
Subject: [PATCH 292/307] Add files via upload

---
 STM32F1/cores/maple/libmaple/rcc_f1.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/STM32F1/cores/maple/libmaple/rcc_f1.c b/STM32F1/cores/maple/libmaple/rcc_f1.c
index f45f670e1..9040a4dc2 100644
--- a/STM32F1/cores/maple/libmaple/rcc_f1.c
+++ b/STM32F1/cores/maple/libmaple/rcc_f1.c
@@ -93,6 +93,7 @@ const struct rcc_dev_info rcc_dev_table[] = {
     [RCC_TIMER13] = { .clk_domain = APB1, .line_num = 7 },
     [RCC_TIMER14] = { .clk_domain = APB1, .line_num = 8 },
 #endif
+	[RCC_CAN]	= { .clk_domain = APB1, .line_num = 25 },	//! JMD after X893
 };
 
 __deprecated

From 1de91caa6004659221ea24c1e3f5c0d7701f3768 Mon Sep 17 00:00:00 2001
From: Phonog <jeanmarc.delaplace@gmail.com>
Date: Mon, 31 Oct 2016 22:35:35 +0100
Subject: [PATCH 293/307] Add files via upload

---
 STM32F1/system/libmaple/stm32f1/include/series/rcc.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/STM32F1/system/libmaple/stm32f1/include/series/rcc.h b/STM32F1/system/libmaple/stm32f1/include/series/rcc.h
index f40dcbaba..aa9f8d3c9 100644
--- a/STM32F1/system/libmaple/stm32f1/include/series/rcc.h
+++ b/STM32F1/system/libmaple/stm32f1/include/series/rcc.h
@@ -439,6 +439,7 @@ typedef enum rcc_clk_id {
     RCC_UART4,
     RCC_UART5,
     RCC_USB,
+	RCC_CAN,	//! JMD after X893
 } rcc_clk_id;
 
 /**

From fda4706df68656147b6899243696c753c3eb188a Mon Sep 17 00:00:00 2001
From: Phonog <jeanmarc.delaplace@gmail.com>
Date: Mon, 31 Oct 2016 22:37:16 +0100
Subject: [PATCH 294/307] Add files via upload

---
 STM32F1/cores/maple/libmaple/usb/stm32f1/usb.c | 15 +++++++++++++++
 1 file changed, 15 insertions(+)

diff --git a/STM32F1/cores/maple/libmaple/usb/stm32f1/usb.c b/STM32F1/cores/maple/libmaple/usb/stm32f1/usb.c
index 0feb745eb..c4f974914 100644
--- a/STM32F1/cores/maple/libmaple/usb/stm32f1/usb.c
+++ b/STM32F1/cores/maple/libmaple/usb/stm32f1/usb.c
@@ -189,10 +189,25 @@ static void usb_resume(RESUME_STATE eResumeSetVal) {
     }
 }
 
+// JMD : default ISRs of CAN, to be overridden if HardwareCAN library is used in sketch
+void __attribute__((weak)) USB_HP_CAN_TX_IRQHandler(void) 
+{ ; }      // Dummy ISR
+
+void __irq_usb_hp_can_tx(void)
+{
+  USB_HP_CAN_TX_IRQHandler () ;
+}
+
+uint8 __attribute__((weak)) CAN_RX0_IRQ_Handler(void)
+{ return 0 ; }      // Dummy ISR 
+
 #define SUSPEND_ENABLED 1
 void __irq_usb_lp_can_rx0(void) {
     uint16 istr = USB_BASE->ISTR;
 
+	if (CAN_RX0_IRQ_Handler())			//! JMD : Call to CAN ISR, returns 1 CAN is active
+		return;							//! JMD
+
     /* Use USB_ISR_MSK to only include code for bits we care about. */
 
 #if (USB_ISR_MSK & USB_ISTR_RESET)

From dad2e73ed524fe637378b508d33d6bfb10885165 Mon Sep 17 00:00:00 2001
From: megadrifter <megadrifter@gmail.com>
Date: Fri, 16 Dec 2016 09:05:23 +0300
Subject: [PATCH 295/307] added the simplified send example

also added testing sketch for GM LAN.
---
 .../AstraH_CAN_test/AstraH_CAN_test.ino       | 145 ++++++++++++++++++
 .../HardwareCAN_simplified_send1.ino          |  93 +++++++++++
 2 files changed, 238 insertions(+)
 create mode 100644 STM32F1/libraries/HardwareCAN/examples/AstraH_CAN_test/AstraH_CAN_test.ino
 create mode 100644 STM32F1/libraries/HardwareCAN/examples/HardwareCAN_simplified_send1/HardwareCAN_simplified_send1.ino

diff --git a/STM32F1/libraries/HardwareCAN/examples/AstraH_CAN_test/AstraH_CAN_test.ino b/STM32F1/libraries/HardwareCAN/examples/AstraH_CAN_test/AstraH_CAN_test.ino
new file mode 100644
index 000000000..a05576bb9
--- /dev/null
+++ b/STM32F1/libraries/HardwareCAN/examples/AstraH_CAN_test/AstraH_CAN_test.ino
@@ -0,0 +1,145 @@
+#include <HardwareCAN.h>
+/*
+ * Uses STM32duino with Phono patch. Must add 33 and 95 CAN speeds
+ */
+#define BPIN 0
+#define SPIN 1
+byte msgD0 ; // variable to be used in the example.
+
+// Instanciation of CAN interface
+HardwareCAN canBus(CAN1_BASE);
+CanMsg msg ;
+
+void CANSetup(void)
+{
+  CAN_STATUS Stat ;
+
+  // Initialize CAN module
+  canBus.map(CAN_GPIO_PB8_PB9);       // This setting is already wired in the Olimexino-STM32 board
+  Stat = canBus.begin(CAN_SPEED_95, CAN_MODE_NORMAL);    // Other speeds go from 125 kbps to 1000 kbps. CAN allows even more choices.
+
+  canBus.filter(0, 0, 0);
+  canBus.set_irq_mode();              // Use irq mode (recommended), so the handling of incoming messages
+                                      // will be performed at ease in a task or in the loop. The software fifo is 16 cells long, 
+                                      // allowing at least 15 ms before processing the fifo is needed at 125 kbps
+  Stat = canBus.status();
+  if (Stat != CAN_OK)
+     /* Your own error processing here */ ;   // Initialization failed
+}
+
+
+// Send one frame. Parameter is a pointer to a frame structure (above), that has previously been updated with data.
+// If no mailbox is available, wait until one becomes empty. There are 3 mailboxes.
+CAN_TX_MBX CANsend(CanMsg *pmsg) // Should be moved to the library?!
+{
+  CAN_TX_MBX mbx;
+
+  do 
+  {
+    mbx = canBus.send(pmsg) ;
+#ifdef USE_MULTITASK
+    vTaskDelay( 1 ) ;                 // Infinite loops are not multitasking-friendly
+#endif
+  }
+  while(mbx == CAN_TX_NO_MBX) ;       // Waiting outbound frames will eventually be sent, unless there is a CAN bus failure.
+  return mbx ;
+}
+
+// Send message
+// Prepare and send a frame containing some value 
+void SendCANmessage(long id=0x001, byte dlength=8, byte d0=0x00, byte d1=0x00, byte d2=0x00, byte d3=0x00, byte d4=0x00, byte d5=0x00, byte d6=0x00, byte d7=0x00)
+{
+  // Initialize the message structure
+  // A CAN structure includes the following fields:
+  msg.IDE = CAN_ID_STD;          // Indicates a standard identifier ; CAN_ID_EXT would mean this frame uses an extended identifier
+  msg.RTR = CAN_RTR_DATA;        // Indicated this is a data frame, as opposed to a remote frame (would then be CAN_RTR_REMOTE)
+  msg.ID = id ;                  // Identifier of the frame : 0-2047 (0-0x3ff) for standard idenfiers; 0-0x1fffffff for extended identifiers
+  msg.DLC = dlength;                   // Number of data bytes to follow
+
+  // Prepare frame : send something
+  msg.Data[0] = d0 ;
+  msg.Data[1] = d1 ;
+  msg.Data[2] = d2 ;
+  msg.Data[3] = d3 ;
+  msg.Data[4] = d4 ;
+  msg.Data[5] = d5 ;
+  msg.Data[6] = d6 ;
+  msg.Data[7] = d7 ;
+
+  digitalWrite(PC13, LOW);    // turn the onboard LED on
+  CANsend(&msg) ;      // Send this frame
+  delay(180);              
+  digitalWrite(PC13, HIGH);   // turn the LED off 
+  delay(100);  
+}
+
+// The application program starts here
+int bState = 0;         // variable for reading the pushbutton status
+int sState = 0;         // variable for reading the switch status
+byte st = 0x31; // buttot 1 on the CD30MP3
+
+void setup() {
+  // put your setup code here, to run once:
+  CANSetup() ;        // Initialize the CAN module and prepare the message structures.
+  pinMode(PC13, OUTPUT);
+  pinMode(BPIN, INPUT); // input for hardware button
+  pinMode(SPIN, INPUT); // input for hardware switch
+  Serial1.begin(115200);
+  Serial1.println("Hello World!");
+  msgD0 = 0x01;
+  delay(500);
+}
+
+void loop() {
+  bState = digitalRead(BPIN);
+  sState = digitalRead(SPIN);
+  // check if the pushbutton is pressed.
+  // if it is, the buttonState is HIGH:
+  if (bState == HIGH) {
+  long msgID = 0x201 ;
+  SendCANmessage(msgID, 3, 0x01, 0x6f, 0x00) ;       
+  Serial1.println("OK pressed");
+  }
+  
+  // check if the switch is high.
+  // if it is:
+  if (sState == HIGH) {
+    long msgID = 0x201 ;
+      SendCANmessage(msgID, 3, 0x01, st, 0x00) ;
+      Serial1.print("Station changed to ");
+      Serial1.println(st);
+      delay(500);       
+      if (st == 0x39){st=0x31;} else {st++;};
+  }
+// try to read message and output to serial
+CanMsg *r_msg;
+if ((r_msg = canBus.recv()) != NULL){
+  Serial1.print(r_msg->ID);
+  Serial1.print("#");
+  Serial1.print(r_msg->Data[0]);
+  Serial1.print(".");
+  Serial1.print(r_msg->Data[1]);
+  Serial1.print(".");
+  Serial1.print(r_msg->Data[2]);
+  Serial1.print(".");
+  Serial1.print(r_msg->Data[3]);
+  Serial1.print(".");
+  Serial1.print(r_msg->Data[4]);
+  Serial1.print(".");
+  Serial1.print(r_msg->Data[5]);
+  Serial1.print(".");
+  Serial1.print(r_msg->Data[6]);
+  Serial1.print(".");
+  Serial1.println(r_msg->Data[7]);
+if (r_msg->ID == 0x201 and r_msg->Data[0] == 0x01 and r_msg->Data[1] == 0xFF){
+// SETTINGS is pressed!
+  Serial1.println("SETTINGS. Pause for 2 seconds.");
+  digitalWrite(PC13, LOW);    // turn the onboard LED on
+  delay(2000);              
+  digitalWrite(PC13, HIGH);   // turn the LED off 
+  }
+  canBus.free();
+  }
+
+  
+}
diff --git a/STM32F1/libraries/HardwareCAN/examples/HardwareCAN_simplified_send1/HardwareCAN_simplified_send1.ino b/STM32F1/libraries/HardwareCAN/examples/HardwareCAN_simplified_send1/HardwareCAN_simplified_send1.ino
new file mode 100644
index 000000000..17fb07f9b
--- /dev/null
+++ b/STM32F1/libraries/HardwareCAN/examples/HardwareCAN_simplified_send1/HardwareCAN_simplified_send1.ino
@@ -0,0 +1,93 @@
+#include <HardwareCAN.h>
+//#include "changes.h"
+/*
+ * Example of use of the HardwareCAN library
+ * This application sends two times one frame of data and then blinkes 3 times. Then repeats after 2 seconds. 
+ * It also produces data that are sent periodically using another two frames.
+ * 
+ * Please read the file changes.h to see the changes to be performed to the core in order to use this
+ */
+
+byte msgD0 ; // variable to be used in the example.
+
+// Instanciation of CAN interface
+HardwareCAN canBus(CAN1_BASE);
+CanMsg msg ;
+
+void CANSetup(void)
+{
+  CAN_STATUS Stat ;
+
+  // Initialize CAN module
+  canBus.map(CAN_GPIO_PB8_PB9);       // This setting is already wired in the Olimexino-STM32 board
+  Stat = canBus.begin(CAN_SPEED_125, CAN_MODE_NORMAL);    // Other speeds go from 125 kbps to 1000 kbps. CAN allows even more choices.
+
+  canBus.filter(0, 0, 0);
+  canBus.set_irq_mode();              // Use irq mode (recommended), so the handling of incoming messages
+                                      // will be performed at ease in a task or in the loop. The software fifo is 16 cells long, 
+                                      // allowing at least 15 ms before processing the fifo is needed at 125 kbps
+  Stat = canBus.status();
+  if (Stat != CAN_OK)
+     /* Your own error processing here */ ;   // Initialization failed
+}
+
+
+// Send one frame. Parameter is a pointer to a frame structure (above), that has previously been updated with data.
+// If no mailbox is available, wait until one becomes empty. There are 3 mailboxes.
+CAN_TX_MBX CANsend(CanMsg *pmsg) // Should be moved to the library?!
+{
+  CAN_TX_MBX mbx;
+
+  do 
+  {
+    mbx = canBus.send(pmsg) ;
+#ifdef USE_MULTITASK
+    vTaskDelay( 1 ) ;                 // Infinite loops are not multitasking-friendly
+#endif
+  }
+  while(mbx == CAN_TX_NO_MBX) ;       // Waiting outbound frames will eventually be sent, unless there is a CAN bus failure.
+  return mbx ;
+}
+
+// Send message
+// Prepare and send a frame containing some value 
+void SendCANmessage(long id=0x001, byte d0=0x00, byte d1=0x00, byte d2=0x00, byte d3=0x00, byte d4=0x00, byte d5=0x00, byte d6=0x00, byte d7=0x00)
+{
+  // Initialize the message structure
+  // A CAN structure includes the following fields:
+  msg.IDE = CAN_ID_STD;          // Indicates a standard identifier ; CAN_ID_EXT would mean this frame uses an extended identifier
+  msg.RTR = CAN_RTR_DATA;        // Indicated this is a data frame, as opposed to a remote frame (would then be CAN_RTR_REMOTE)
+  msg.ID = id ;                  // Identifier of the frame : 0-2047 (0-0x3ff) for standard idenfiers; 0-0x1fffffff for extended identifiers
+  msg.DLC = 8;                   // Number of data bytes to follow
+
+  // Prepare frame : send something
+  msg.Data[0] = d0 ;
+  msg.Data[1] = d1 ;
+  msg.Data[2] = d2 ;
+  msg.Data[3] = d3 ;
+  msg.Data[4] = d4 ;
+  msg.Data[5] = d5 ;
+  msg.Data[6] = d6 ;
+  msg.Data[7] = d7 ;
+
+  digitalWrite(PC13, LOW);    // turn the onboard LED on
+  CANsend(&msg) ;      // Send this frame
+  delay(180);              
+  digitalWrite(PC13, HIGH);   // turn the LED off 
+  delay(100);  
+}
+
+// The application program starts here
+void setup() {
+  // put your setup code here, to run once:
+  CANSetup() ;        // Initialize the CAN module and prepare the message structures.
+  pinMode(PC13, OUTPUT);
+  msgD0 = 0x01;
+}
+
+void loop() {
+  delay(1000);
+  long msgID = 0x101 ;
+  SendCANmessage(msgID, msgD0) ;       
+  msgD0++;
+}

From cdf8fa653f62388242d9d0d6b2b56258feb119c8 Mon Sep 17 00:00:00 2001
From: megadrifter <megadrifter@gmail.com>
Date: Fri, 16 Dec 2016 09:08:21 +0300
Subject: [PATCH 296/307] Add 33 and 95 kbps speeds

---
 STM32F1/libraries/HardwareCAN/src/HardwareCAN.cpp |  2 ++
 STM32F1/libraries/HardwareCAN/src/utility/can.c   | 12 ++++++++++++
 STM32F1/libraries/HardwareCAN/src/utility/can.h   |  2 ++
 3 files changed, 16 insertions(+)

diff --git a/STM32F1/libraries/HardwareCAN/src/HardwareCAN.cpp b/STM32F1/libraries/HardwareCAN/src/HardwareCAN.cpp
index f113c4d85..f324e865f 100644
--- a/STM32F1/libraries/HardwareCAN/src/HardwareCAN.cpp
+++ b/STM32F1/libraries/HardwareCAN/src/HardwareCAN.cpp
@@ -13,6 +13,8 @@
  *           - CAN_SPEED_500
  *           - CAN_SPEED_250
  *           - CAN_SPEED_125
+ *           - CAN_SPEED_95
+ *           - CAN_SPEED_33
  */
 CAN_STATUS HardwareCAN::begin(CAN_SPEED speed, uint32 mode)
 {
diff --git a/STM32F1/libraries/HardwareCAN/src/utility/can.c b/STM32F1/libraries/HardwareCAN/src/utility/can.c
index 0120e0eed..2f924184a 100644
--- a/STM32F1/libraries/HardwareCAN/src/utility/can.c
+++ b/STM32F1/libraries/HardwareCAN/src/utility/can.c
@@ -44,6 +44,18 @@ struct can_speed_info {
 #define CAN_CLOCK	(36000000UL / 18UL)
 
 static const struct can_speed_info can_speed_table[] = {
+	[CAN_SPEED_33]		= { .btr = (
+		(( 4-1) << CAN_BTR_SJW_POS) |
+		((12-1) << CAN_BTR_TS1_POS) |
+		(( 5-1) << CAN_BTR_TS2_POS) |
+		(CAN_CLOCK / 33000UL - 1)
+		)},
+	[CAN_SPEED_95]		= { .btr = (
+		(( 4-1) << CAN_BTR_SJW_POS) |
+		((12-1) << CAN_BTR_TS1_POS) |
+		(( 5-1) << CAN_BTR_TS2_POS) |
+		(CAN_CLOCK / 95000UL - 1)
+		)},
 	[CAN_SPEED_125]		= { .btr = (
 		(( 4-1) << CAN_BTR_SJW_POS) |
 		((12-1) << CAN_BTR_TS1_POS) |
diff --git a/STM32F1/libraries/HardwareCAN/src/utility/can.h b/STM32F1/libraries/HardwareCAN/src/utility/can.h
index 576ac36fe..972259d3d 100644
--- a/STM32F1/libraries/HardwareCAN/src/utility/can.h
+++ b/STM32F1/libraries/HardwareCAN/src/utility/can.h
@@ -168,6 +168,8 @@ typedef enum CAN_TX_MBX
 #define CAN_MODE_SILENT_LOOPBACK	(CAN_BTR_LBKM | CAN_BTR_SILM)	/* loopback combined with silent mode */
 
 enum CAN_SPEED {
+	CAN_SPEED_33,
+	CAN_SPEED_95,
 	CAN_SPEED_125,
 	CAN_SPEED_250,
 	CAN_SPEED_500,

From 7b21efa2dab378450e109ace3cf44449695c92f0 Mon Sep 17 00:00:00 2001
From: megadrifter <megadrifter@gmail.com>
Date: Fri, 24 Mar 2017 22:36:44 +0300
Subject: [PATCH 297/307] RPM reading example

Example says when you need to shift up or shift down
---
 .../AstraH_CAN_test/AstraH_CAN_test_rpm.ino   | 180 ++++++++++++++++++
 1 file changed, 180 insertions(+)
 create mode 100644 STM32F1/libraries/HardwareCAN/examples/AstraH_CAN_test/AstraH_CAN_test_rpm.ino

diff --git a/STM32F1/libraries/HardwareCAN/examples/AstraH_CAN_test/AstraH_CAN_test_rpm.ino b/STM32F1/libraries/HardwareCAN/examples/AstraH_CAN_test/AstraH_CAN_test_rpm.ino
new file mode 100644
index 000000000..0ea0b3a29
--- /dev/null
+++ b/STM32F1/libraries/HardwareCAN/examples/AstraH_CAN_test/AstraH_CAN_test_rpm.ino
@@ -0,0 +1,180 @@
+#include <HardwareCAN.h>
+/*
+ * Uses STM32duino with Phono patch. Must add 33 and 95 CAN speeds
+ */
+#define BPIN 0 // there is a buttton
+#define SPIN 1 // there is a switch
+#define BUZZERPIN 17 // B1 for buzzer
+
+// Instanciation of CAN interface
+HardwareCAN canBus(CAN1_BASE);
+CanMsg msg ;
+CanMsg *r_msg;
+
+void CANSetup(void)
+{
+  CAN_STATUS Stat ;
+
+  // Initialize CAN module
+  canBus.map(CAN_GPIO_PB8_PB9);       // This setting is already wired in the Olimexino-STM32 board
+  Stat = canBus.begin(CAN_SPEED_33, CAN_MODE_NORMAL);    
+
+  canBus.filter(0, 0, 0);
+  canBus.set_irq_mode();              // Use irq mode (recommended), so the handling of incoming messages
+                                      // will be performed at ease in a task or in the loop. The software fifo is 16 cells long, 
+                                      // allowing at least 15 ms before processing the fifo is needed at 125 kbps
+  Stat = canBus.status();
+  if (Stat != CAN_OK)
+     /* Your own error processing here */ ;   // Initialization failed
+}
+
+
+// Send one frame. Parameter is a pointer to a frame structure (above), that has previously been updated with data.
+// If no mailbox is available, wait until one becomes empty. There are 3 mailboxes.
+CAN_TX_MBX CANsend(CanMsg *pmsg) // Should be moved to the library?!
+{
+  CAN_TX_MBX mbx;
+  do 
+  {
+    mbx = canBus.send(pmsg) ;
+#ifdef USE_MULTITASK
+    vTaskDelay( 1 ) ;                 // Infinite loops are not multitasking-friendly
+#endif
+  }
+  while(mbx == CAN_TX_NO_MBX) ;       // Waiting outbound frames will eventually be sent, unless there is a CAN bus failure.
+  return mbx ;
+}
+
+// Send message
+// Prepare and send a frame containing some value 
+void SendCANmessage(long id=0x001, byte dlength=8, byte d0=0x00, byte d1=0x00, byte d2=0x00, byte d3=0x00, byte d4=0x00, byte d5=0x00, byte d6=0x00, byte d7=0x00)
+{
+  // Initialize the message structure
+  // A CAN structure includes the following fields:
+  msg.IDE = CAN_ID_STD;          // Indicates a standard identifier ; CAN_ID_EXT would mean this frame uses an extended identifier
+  msg.RTR = CAN_RTR_DATA;        // Indicated this is a data frame, as opposed to a remote frame (would then be CAN_RTR_REMOTE)
+  msg.ID = id ;                  // Identifier of the frame : 0-2047 (0-0x3ff) for standard idenfiers; 0-0x1fffffff for extended identifiers
+  msg.DLC = dlength;                   // Number of data bytes to follow
+
+  // Prepare frame : send something
+  msg.Data[0] = d0 ;
+  msg.Data[1] = d1 ;
+  msg.Data[2] = d2 ;
+  msg.Data[3] = d3 ;
+  msg.Data[4] = d4 ;
+  msg.Data[5] = d5 ;
+  msg.Data[6] = d6 ;
+  msg.Data[7] = d7 ;
+
+  digitalWrite(PC13, LOW);    // turn the onboard LED on
+  CANsend(&msg) ;      // Send this frame
+  delay(180);              
+  digitalWrite(PC13, HIGH);   // turn the LED off 
+  delay(100);  
+}
+
+// The application program starts here
+bool bState = 0;         // variable for reading the pushbutton status
+bool sState = 0;         // variable for reading the switch status
+// byte st = 0x31; // buttot 1 on the CD30MP3
+
+void setup() {
+  // put your setup code here, to run once:
+  CANSetup() ;        // Initialize the CAN module and prepare the message structures.
+  pinMode(PC13, OUTPUT); // LED
+  pinMode(BPIN, INPUT); // input for hardware button
+  pinMode(SPIN, INPUT); // input for hardware switch
+
+  Serial.begin(115200);
+  pinMode(BUZZERPIN, OUTPUT);
+  digitalWrite(BUZZERPIN, LOW);
+  
+  Serial1.begin(115200);
+  Serial1.println("Hello World!");
+}
+
+void beep(int times)
+{
+  for (int i=0;i<times;++i)
+  {
+      digitalWrite(BUZZERPIN, HIGH);
+      digitalWrite(PC13, LOW);    // turn the onboard LED on
+      delay(50);
+      digitalWrite(BUZZERPIN, LOW);
+      digitalWrite(PC13, HIGH);   // turn the LED off 
+      delay(100);
+  } 
+  delay(300); // already has a delay, so don't wait after beep!
+}
+
+void loop() {
+  bState = digitalRead(BPIN);
+  sState = digitalRead(SPIN);
+  
+  // check if the pushbutton is pressed.
+  // if it is, the buttonState is HIGH:
+  if (bState == HIGH) {
+  long msgID = 0x201 ;
+  SendCANmessage(msgID, 3, 0x01, 0x6f, 0x00) ;       
+  SendCANmessage(msgID, 3, 0x00, 0x6f, 0x00) ;       
+  Serial1.println("OK pressed");
+  beep(3);
+  }
+  
+  // check if the switch is high.
+  // if it is:
+  if (sState == HIGH) {
+    /* --- Start check RPMs --- */
+    bool gotit = 0; 
+    while ( ( ( r_msg = canBus.recv() ) != NULL ) and (!gotit)  )
+    {
+      if ((r_msg->ID) == 0x108 ) {
+      Serial1.println("Data read at 0x108");
+      byte tt = r_msg->Data[0];
+      byte xx = r_msg->Data[1];
+      byte yy = r_msg->Data[2];
+      int rpm = (xx<<6) + (yy>>2);
+      Serial1.print("rpm = ");
+      Serial1.println(rpm);
+        if (tt&0x20){ /* Throttle on? */
+          Serial1.println("Throttle ON");
+          if (xx > 0x2e) {beep(2); Serial1.println("Shift up!");}
+          if (xx < 0x1c) {beep(1); Serial1.println("Shift down!");}
+        }
+      gotit = 1;
+      }
+    canBus.free();
+	}     
+    /* --- End check RPMs --- */
+  } 
+  else 
+  {
+  // try to read message and output to serial
+  CanMsg *r_msg;
+  if ((r_msg = canBus.recv()) != NULL)
+	  {
+	  Serial1.print(r_msg->ID);
+	  Serial1.print("#");
+	  Serial1.print(r_msg->Data[0]);
+	  Serial1.print(".");
+	  Serial1.print(r_msg->Data[1]);
+	  Serial1.print(".");
+	  Serial1.print(r_msg->Data[2]);
+	  Serial1.print(".");
+	  Serial1.print(r_msg->Data[3]);
+	  Serial1.print(".");
+	  Serial1.print(r_msg->Data[4]);
+	  Serial1.print(".");
+	  Serial1.print(r_msg->Data[5]);
+	  Serial1.print(".");
+	  Serial1.print(r_msg->Data[6]);
+	  Serial1.print(".");
+	  Serial1.println(r_msg->Data[7]);
+	  }
+
+  canBus.free();
+  }
+  
+
+  
+}

From 0fb002de9b35d163e50af813fd2b7ecdaf189455 Mon Sep 17 00:00:00 2001
From: megadrifter <megadrifter@gmail.com>
Date: Thu, 1 Jun 2017 18:49:26 +0300
Subject: [PATCH 298/307] add CAN_GPIO_PA11_PA12

---
 STM32F1/libraries/HardwareCAN/src/utility/can.h | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/STM32F1/libraries/HardwareCAN/src/utility/can.h b/STM32F1/libraries/HardwareCAN/src/utility/can.h
index 972259d3d..19506ea85 100644
--- a/STM32F1/libraries/HardwareCAN/src/utility/can.h
+++ b/STM32F1/libraries/HardwareCAN/src/utility/can.h
@@ -139,7 +139,8 @@ extern "C" {
 
 typedef enum CAN_GPIO_MAP {
 	CAN_GPIO_PB8_PB9,		/* RX to PB8, TX to PB9 */
-	CAN_GPIO_PD0_PD1		/* RX to PD0, TX to PD1 */
+	CAN_GPIO_PD0_PD1,		/* RX to PD0, TX to PD1 */
+	CAN_GPIO_PA11_PA12		/* RX to PA11, TX to PA12 */
 } CAN_GPIO_MAP;
 
 typedef enum CAN_STATUS

From 333560d051a49bd501764a014119260620c79cfc Mon Sep 17 00:00:00 2001
From: megadrifter <megadrifter@gmail.com>
Date: Thu, 1 Jun 2017 18:53:00 +0300
Subject: [PATCH 299/307] add A11-A12 REMAP

---
 STM32F1/libraries/HardwareCAN/src/utility/can.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/STM32F1/libraries/HardwareCAN/src/utility/can.c b/STM32F1/libraries/HardwareCAN/src/utility/can.c
index 2f924184a..ad7a7da59 100644
--- a/STM32F1/libraries/HardwareCAN/src/utility/can.c
+++ b/STM32F1/libraries/HardwareCAN/src/utility/can.c
@@ -257,6 +257,12 @@ CAN_STATUS can_gpio_map(CAN_Port* CANx, CAN_GPIO_MAP map_mode)
 			gpio_set_mode(GPIOB, 8, GPIO_INPUT_FLOATING);
 			gpio_set_mode(GPIOB, 9, GPIO_AF_OUTPUT_PP);
 			break;
+		 case CAN_GPIO_PA11_PA12:
+			 rcc_clk_enable(RCC_GPIOA);
+			 afio_remap(AFIO_MAPR_CAN_REMAP_NONE);
+			 gpio_set_mode(GPIOA, 11, GPIO_INPUT_FLOATING);
+			 gpio_set_mode(GPIOA, 12, GPIO_AF_OUTPUT_PP);
+		 break;
 #if NR_GPIO_PORTS >= 4
 		case CAN_GPIO_PD0_PD1:
 			rcc_clk_enable(RCC_GPIOD);

From 4e2af4f12ed23ee81b3792a5ccac4ea575fcab98 Mon Sep 17 00:00:00 2001
From: megadrifter <megadrifter@gmail.com>
Date: Wed, 7 Jun 2017 19:52:52 +0300
Subject: [PATCH 300/307] add real timer setting as mcs/72

---
 STM32F1/cores/maple/HardwareTimer.h | 12 ++++++++++++
 1 file changed, 12 insertions(+)

diff --git a/STM32F1/cores/maple/HardwareTimer.h b/STM32F1/cores/maple/HardwareTimer.h
index bb40dba0f..d10a8c1f9 100644
--- a/STM32F1/cores/maple/HardwareTimer.h
+++ b/STM32F1/cores/maple/HardwareTimer.h
@@ -142,6 +142,18 @@ class HardwareTimer {
      *                     greater than zero.
      * @return The new overflow value.
      */
+    uint16 setPeriod72(uint32 microseconds);
+    /**
+     * @brief Set the timer's period in microseconds/72.
+     *
+     * Configures the prescaler and overflow values to generate a timer
+     * reload with a period as close to the given number of
+     * microseconds as possible.
+     *
+     * @param microseconds The desired period of the timer.  This must be
+     *                     greater than zero.
+     * @return The new overflow value.
+     */
     uint16 setPeriod(uint32 microseconds);
 
     /**

From ac866ec629ffb3581eff691b8925a725be6e0791 Mon Sep 17 00:00:00 2001
From: megadrifter <megadrifter@gmail.com>
Date: Wed, 7 Jun 2017 19:58:00 +0300
Subject: [PATCH 301/307] add setCycles to use instead of setPeriod

because I neet faster interrupt than 1 microsecond.
---
 STM32F1/cores/maple/HardwareTimer.cpp | 16 ++++++++++++++++
 1 file changed, 16 insertions(+)

diff --git a/STM32F1/cores/maple/HardwareTimer.cpp b/STM32F1/cores/maple/HardwareTimer.cpp
index abf1e623f..321598ff0 100644
--- a/STM32F1/cores/maple/HardwareTimer.cpp
+++ b/STM32F1/cores/maple/HardwareTimer.cpp
@@ -117,6 +117,22 @@ uint16 HardwareTimer::setPeriod(uint32 microseconds) {
     return overflow;
 }
 
+uint16 HardwareTimer::setCycles(uint32 Cycles) {
+    // Not the best way to handle this edge case?
+    if (!Cycles) {
+        this->setPrescaleFactor(1);
+        this->setOverflow(1);
+        return this->getOverflow();
+    }
+
+    uint32 period_cyc = Cycles;
+    uint16 prescaler = (uint16)(period_cyc / MAX_RELOAD + 1);
+    uint16 overflow = (uint16)((period_cyc + (prescaler / 2)) / prescaler);
+    this->setPrescaleFactor(prescaler);
+    this->setOverflow(overflow);
+    return overflow;
+}
+
 void HardwareTimer::setMode(int channel, timer_mode mode) {
     timer_set_mode(this->dev, (uint8)channel, (timer_mode)mode);
 }

From 62911a8d70017b46916ed621da52883ce7d17e20 Mon Sep 17 00:00:00 2001
From: megadrifter <megadrifter@gmail.com>
Date: Wed, 7 Jun 2017 20:01:55 +0300
Subject: [PATCH 302/307] rename to setCycles function

---
 STM32F1/cores/maple/HardwareTimer.h | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/STM32F1/cores/maple/HardwareTimer.h b/STM32F1/cores/maple/HardwareTimer.h
index d10a8c1f9..4de2ebc07 100644
--- a/STM32F1/cores/maple/HardwareTimer.h
+++ b/STM32F1/cores/maple/HardwareTimer.h
@@ -132,19 +132,19 @@ class HardwareTimer {
     void setCount(uint16 val);
 
     /**
-     * @brief Set the timer's period in microseconds.
+     * @brief Set the timer's period in Cycles.
      *
      * Configures the prescaler and overflow values to generate a timer
-     * reload with a period as close to the given number of
-     * microseconds as possible.
+     * reload with a period of given number of
+     * Cycles.
      *
-     * @param microseconds The desired period of the timer.  This must be
+     * @param Cycles The desired period of the timer.  This must be
      *                     greater than zero.
      * @return The new overflow value.
      */
-    uint16 setPeriod72(uint32 microseconds);
+    uint16 setCycles(uint32 Cycles);
     /**
-     * @brief Set the timer's period in microseconds/72.
+     * @brief Set the timer's period in microseconds.
      *
      * Configures the prescaler and overflow values to generate a timer
      * reload with a period as close to the given number of

From 406eea0384fa6dd782ebda7b81bf0f4a4151d9fa Mon Sep 17 00:00:00 2001
From: Drifter <megadrifter@gmail.com>
Date: Thu, 8 Jun 2017 08:53:03 +0300
Subject: [PATCH 303/307] =Add dual CAN example

---
 .../AstraH_CAN_test/AstraH_CAN_test_rpm.ino   | 180 ------------------
 .../examples/STMdualCAN/STMdualCAN.ino        | 123 ++++++++++++
 2 files changed, 123 insertions(+), 180 deletions(-)
 delete mode 100644 STM32F1/libraries/HardwareCAN/examples/AstraH_CAN_test/AstraH_CAN_test_rpm.ino
 create mode 100644 STM32F1/libraries/HardwareCAN/examples/STMdualCAN/STMdualCAN.ino

diff --git a/STM32F1/libraries/HardwareCAN/examples/AstraH_CAN_test/AstraH_CAN_test_rpm.ino b/STM32F1/libraries/HardwareCAN/examples/AstraH_CAN_test/AstraH_CAN_test_rpm.ino
deleted file mode 100644
index 0ea0b3a29..000000000
--- a/STM32F1/libraries/HardwareCAN/examples/AstraH_CAN_test/AstraH_CAN_test_rpm.ino
+++ /dev/null
@@ -1,180 +0,0 @@
-#include <HardwareCAN.h>
-/*
- * Uses STM32duino with Phono patch. Must add 33 and 95 CAN speeds
- */
-#define BPIN 0 // there is a buttton
-#define SPIN 1 // there is a switch
-#define BUZZERPIN 17 // B1 for buzzer
-
-// Instanciation of CAN interface
-HardwareCAN canBus(CAN1_BASE);
-CanMsg msg ;
-CanMsg *r_msg;
-
-void CANSetup(void)
-{
-  CAN_STATUS Stat ;
-
-  // Initialize CAN module
-  canBus.map(CAN_GPIO_PB8_PB9);       // This setting is already wired in the Olimexino-STM32 board
-  Stat = canBus.begin(CAN_SPEED_33, CAN_MODE_NORMAL);    
-
-  canBus.filter(0, 0, 0);
-  canBus.set_irq_mode();              // Use irq mode (recommended), so the handling of incoming messages
-                                      // will be performed at ease in a task or in the loop. The software fifo is 16 cells long, 
-                                      // allowing at least 15 ms before processing the fifo is needed at 125 kbps
-  Stat = canBus.status();
-  if (Stat != CAN_OK)
-     /* Your own error processing here */ ;   // Initialization failed
-}
-
-
-// Send one frame. Parameter is a pointer to a frame structure (above), that has previously been updated with data.
-// If no mailbox is available, wait until one becomes empty. There are 3 mailboxes.
-CAN_TX_MBX CANsend(CanMsg *pmsg) // Should be moved to the library?!
-{
-  CAN_TX_MBX mbx;
-  do 
-  {
-    mbx = canBus.send(pmsg) ;
-#ifdef USE_MULTITASK
-    vTaskDelay( 1 ) ;                 // Infinite loops are not multitasking-friendly
-#endif
-  }
-  while(mbx == CAN_TX_NO_MBX) ;       // Waiting outbound frames will eventually be sent, unless there is a CAN bus failure.
-  return mbx ;
-}
-
-// Send message
-// Prepare and send a frame containing some value 
-void SendCANmessage(long id=0x001, byte dlength=8, byte d0=0x00, byte d1=0x00, byte d2=0x00, byte d3=0x00, byte d4=0x00, byte d5=0x00, byte d6=0x00, byte d7=0x00)
-{
-  // Initialize the message structure
-  // A CAN structure includes the following fields:
-  msg.IDE = CAN_ID_STD;          // Indicates a standard identifier ; CAN_ID_EXT would mean this frame uses an extended identifier
-  msg.RTR = CAN_RTR_DATA;        // Indicated this is a data frame, as opposed to a remote frame (would then be CAN_RTR_REMOTE)
-  msg.ID = id ;                  // Identifier of the frame : 0-2047 (0-0x3ff) for standard idenfiers; 0-0x1fffffff for extended identifiers
-  msg.DLC = dlength;                   // Number of data bytes to follow
-
-  // Prepare frame : send something
-  msg.Data[0] = d0 ;
-  msg.Data[1] = d1 ;
-  msg.Data[2] = d2 ;
-  msg.Data[3] = d3 ;
-  msg.Data[4] = d4 ;
-  msg.Data[5] = d5 ;
-  msg.Data[6] = d6 ;
-  msg.Data[7] = d7 ;
-
-  digitalWrite(PC13, LOW);    // turn the onboard LED on
-  CANsend(&msg) ;      // Send this frame
-  delay(180);              
-  digitalWrite(PC13, HIGH);   // turn the LED off 
-  delay(100);  
-}
-
-// The application program starts here
-bool bState = 0;         // variable for reading the pushbutton status
-bool sState = 0;         // variable for reading the switch status
-// byte st = 0x31; // buttot 1 on the CD30MP3
-
-void setup() {
-  // put your setup code here, to run once:
-  CANSetup() ;        // Initialize the CAN module and prepare the message structures.
-  pinMode(PC13, OUTPUT); // LED
-  pinMode(BPIN, INPUT); // input for hardware button
-  pinMode(SPIN, INPUT); // input for hardware switch
-
-  Serial.begin(115200);
-  pinMode(BUZZERPIN, OUTPUT);
-  digitalWrite(BUZZERPIN, LOW);
-  
-  Serial1.begin(115200);
-  Serial1.println("Hello World!");
-}
-
-void beep(int times)
-{
-  for (int i=0;i<times;++i)
-  {
-      digitalWrite(BUZZERPIN, HIGH);
-      digitalWrite(PC13, LOW);    // turn the onboard LED on
-      delay(50);
-      digitalWrite(BUZZERPIN, LOW);
-      digitalWrite(PC13, HIGH);   // turn the LED off 
-      delay(100);
-  } 
-  delay(300); // already has a delay, so don't wait after beep!
-}
-
-void loop() {
-  bState = digitalRead(BPIN);
-  sState = digitalRead(SPIN);
-  
-  // check if the pushbutton is pressed.
-  // if it is, the buttonState is HIGH:
-  if (bState == HIGH) {
-  long msgID = 0x201 ;
-  SendCANmessage(msgID, 3, 0x01, 0x6f, 0x00) ;       
-  SendCANmessage(msgID, 3, 0x00, 0x6f, 0x00) ;       
-  Serial1.println("OK pressed");
-  beep(3);
-  }
-  
-  // check if the switch is high.
-  // if it is:
-  if (sState == HIGH) {
-    /* --- Start check RPMs --- */
-    bool gotit = 0; 
-    while ( ( ( r_msg = canBus.recv() ) != NULL ) and (!gotit)  )
-    {
-      if ((r_msg->ID) == 0x108 ) {
-      Serial1.println("Data read at 0x108");
-      byte tt = r_msg->Data[0];
-      byte xx = r_msg->Data[1];
-      byte yy = r_msg->Data[2];
-      int rpm = (xx<<6) + (yy>>2);
-      Serial1.print("rpm = ");
-      Serial1.println(rpm);
-        if (tt&0x20){ /* Throttle on? */
-          Serial1.println("Throttle ON");
-          if (xx > 0x2e) {beep(2); Serial1.println("Shift up!");}
-          if (xx < 0x1c) {beep(1); Serial1.println("Shift down!");}
-        }
-      gotit = 1;
-      }
-    canBus.free();
-	}     
-    /* --- End check RPMs --- */
-  } 
-  else 
-  {
-  // try to read message and output to serial
-  CanMsg *r_msg;
-  if ((r_msg = canBus.recv()) != NULL)
-	  {
-	  Serial1.print(r_msg->ID);
-	  Serial1.print("#");
-	  Serial1.print(r_msg->Data[0]);
-	  Serial1.print(".");
-	  Serial1.print(r_msg->Data[1]);
-	  Serial1.print(".");
-	  Serial1.print(r_msg->Data[2]);
-	  Serial1.print(".");
-	  Serial1.print(r_msg->Data[3]);
-	  Serial1.print(".");
-	  Serial1.print(r_msg->Data[4]);
-	  Serial1.print(".");
-	  Serial1.print(r_msg->Data[5]);
-	  Serial1.print(".");
-	  Serial1.print(r_msg->Data[6]);
-	  Serial1.print(".");
-	  Serial1.println(r_msg->Data[7]);
-	  }
-
-  canBus.free();
-  }
-  
-
-  
-}
diff --git a/STM32F1/libraries/HardwareCAN/examples/STMdualCAN/STMdualCAN.ino b/STM32F1/libraries/HardwareCAN/examples/STMdualCAN/STMdualCAN.ino
new file mode 100644
index 000000000..cbeaf8962
--- /dev/null
+++ b/STM32F1/libraries/HardwareCAN/examples/STMdualCAN/STMdualCAN.ino
@@ -0,0 +1,123 @@
+#include <HardwareCAN.h>
+/*
+ *
+ */
+
+#define T_DELAY 10
+// Instanciation of CAN interface
+HardwareCAN canBus(CAN1_BASE);
+CanMsg msg ;
+
+
+void CAN_a_33_Setup(void)
+{
+
+  CAN_STATUS Stat ;
+  afio_init(); // this will restart subsystem and make it work!
+  canBus.map(CAN_GPIO_PA11_PA12);  
+  Stat = canBus.begin(CAN_SPEED_33, CAN_MODE_NORMAL);
+  canBus.filter(0, 0, 0);
+  canBus.set_irq_mode();
+  Stat = canBus.status();
+  if (Stat != CAN_OK)
+  {digitalWrite(PC13, LOW);
+   }
+// /* Your own error processing here */  ;  // Initialization failed
+ }
+
+void CAN_b_95_Setup(void)
+{
+  CAN_STATUS Stat ;
+  canBus.map(CAN_GPIO_PB8_PB9);
+  Stat = canBus.begin(CAN_SPEED_95, CAN_MODE_NORMAL);
+  canBus.filter(0, 0, 0);
+  canBus.set_irq_mode();
+  Stat = canBus.status();
+  if (Stat != CAN_OK)
+  {digitalWrite(PC13, LOW);
+   }
+//     /* Your own error processing here */ ;   // Initialization failed
+//  delay(T_DELAY);
+}
+
+
+CAN_TX_MBX CANsend(CanMsg *pmsg) // Should be moved to the library?!
+{
+  CAN_TX_MBX mbx;
+
+//  do 
+//  {
+    mbx = canBus.send(pmsg) ;
+#ifdef USE_MULTITASK
+    vTaskDelay( 1 ) ;                 // Infinite loops are not multitasking-friendly
+#endif
+//  }
+//  while(mbx == CAN_TX_NO_MBX) ;       // Waiting outbound frames will eventually be sent, unless there is a CAN bus failure.
+  return mbx ;
+}
+
+// Send message
+// Prepare and send a frame containing some value 
+void SendCANmessage(long id=0x001, byte dlength=8, byte d0=0x00, byte d1=0x00, byte d2=0x00, byte d3=0x00, byte d4=0x00, byte d5=0x00, byte d6=0x00, byte d7=0x00)
+{
+  // Initialize the message structure
+  // A CAN structure includes the following fields:
+  msg.IDE = CAN_ID_STD;          // Indicates a standard identifier ; CAN_ID_EXT would mean this frame uses an extended identifier
+  msg.RTR = CAN_RTR_DATA;        // Indicated this is a data frame, as opposed to a remote frame (would then be CAN_RTR_REMOTE)
+  msg.ID = id ;                  // Identifier of the frame : 0-2047 (0-0x3ff) for standard idenfiers; 0-0x1fffffff for extended identifiers
+  msg.DLC = dlength;                   // Number of data bytes to follow
+
+  // Prepare frame : send something
+  msg.Data[0] = d0 ;
+  msg.Data[1] = d1 ;
+  msg.Data[2] = d2 ;
+  msg.Data[3] = d3 ;
+  msg.Data[4] = d4 ;
+  msg.Data[5] = d5 ;
+  msg.Data[6] = d6 ;
+  msg.Data[7] = d7 ;
+
+  digitalWrite(PC13, LOW);    // turn the onboard LED on
+  CANsend(&msg) ;      // Send this frame            
+  digitalWrite(PC13, HIGH);   // turn the LED off 
+  delay(T_DELAY);  
+}
+
+
+// The application program starts here
+byte msgD0 = 0x00;
+void setup() {        // Initialize the CAN module and prepare the message structures.
+  pinMode(PC13, OUTPUT);
+  digitalWrite(PC13, HIGH);
+  delay(10);
+  digitalWrite(PC13, LOW);
+  delay(200);
+  digitalWrite(PC13, HIGH);
+  delay(200);
+
+}
+
+
+void loop() {
+/**/
+	CAN_a_33_Setup();
+	SendCANmessage(0x108,8,0x03,msgD0,msgD0,0x00,msgD0,msgD0,0x00,0x00);       
+	SendCANmessage(0x5e8,8,0x81,msgD0,msgD0,msgD0);
+	delay(30);
+/**/
+	CAN_b_95_Setup();
+	for (byte msgD1=1;msgD1<3;msgD1++)
+	{	    
+		delay(T_DELAY);
+		SendCANmessage(0x201,3,0x01,0xff,msgD0);       
+		delay(T_DELAY);
+		SendCANmessage(0x201,3,0x00,0xff,msgD0);       
+		delay(T_DELAY);
+		SendCANmessage(0x201,3,0x01,0xff,msgD1);       
+		delay(T_DELAY);
+		SendCANmessage(0x201,3,0x00,0xff,msgD1);       
+		delay(T_DELAY);
+	}  
+/**/
+msgD0++;
+}

From a54f4cd738bd5057fa00d362a38ed3306f142631 Mon Sep 17 00:00:00 2001
From: megadrifter <megadrifter@gmail.com>
Date: Wed, 13 Sep 2017 22:59:56 +0300
Subject: [PATCH 304/307] CAN filter corrected by  tjb12345

http://www.stm32duino.com/viewtopic.php?p=34279#p34295
---
 STM32F1/libraries/HardwareCAN/src/utility/can.c | 15 ++++++++++-----
 1 file changed, 10 insertions(+), 5 deletions(-)

diff --git a/STM32F1/libraries/HardwareCAN/src/utility/can.c b/STM32F1/libraries/HardwareCAN/src/utility/can.c
index ad7a7da59..954e6e349 100644
--- a/STM32F1/libraries/HardwareCAN/src/utility/can.c
+++ b/STM32F1/libraries/HardwareCAN/src/utility/can.c
@@ -279,7 +279,7 @@ CAN_STATUS can_gpio_map(CAN_Port* CANx, CAN_GPIO_MAP map_mode)
 	return status;
 }
 
-CAN_STATUS can_filter(CAN_Port* CANx, uint8 filter_idx, CAN_FIFO fifo, CAN_FILTER_SCALE scale, CAN_FILTER_MODE mode, uint32 fr1, uint32 fr2)
+CAN_STATUS can_filter(CAN_Port* CANx, uint8 filter_idx, CAN_FIFO fifo, CAN_FILTER_SCALE scale, CAN_FILTER_MODE mode, uint32 fr1, uint32 fr2, int extID = 0)
 {
 	uint32 mask = ((uint32)0x00000001) << filter_idx;
 
@@ -291,9 +291,15 @@ CAN_STATUS can_filter(CAN_Port* CANx, uint8 filter_idx, CAN_FIFO fifo, CAN_FILTE
 		CANx->FS1R |= mask;
 	else
 		CANx->FS1R &= ~mask;
-
-	CANx->sFilterRegister[filter_idx].FR1 = fr1;
-	CANx->sFilterRegister[filter_idx].FR2 = fr2;
+	if (extID) {
+		CANx->sFilterRegister[filter_idx].FR1 = (fr1 << 3) | CAN_ID_EXT;
+		CANx->sFilterRegister[filter_idx].FR2 = (fr2 << 3) | CAN_ID_EXT;	
+	}
+	else {
+		CANx->sFilterRegister[filter_idx].FR1 = (fr1 << 21);
+		CANx->sFilterRegister[filter_idx].FR2 = (fr2 << 21);	
+	}
+	
 
 	if (mode == CAN_FILTER_MASK)
 		CANx->FM1R &= ~mask;
@@ -309,7 +315,6 @@ CAN_STATUS can_filter(CAN_Port* CANx, uint8 filter_idx, CAN_FIFO fifo, CAN_FILTE
 	CANx->FMR &= ~CAN_FMR_FINIT;
 	return CAN_OK;
 }
-
 /**
   * @brief  Initiates the transmission of a message.
   * @param	CANx: where x can be 1 to select the CAN peripheral.

From 5f1da87809159ad2ca18e644f75d1f9e1b8edb02 Mon Sep 17 00:00:00 2001
From: megadrifter <megadrifter@gmail.com>
Date: Fri, 13 Oct 2017 14:09:31 +0300
Subject: [PATCH 305/307] latest files from Phonog

---
 .../libraries/HardwareCAN/src/utility/can.c   |  65 +-
 .../HardwareCAN/src/utility/can.c.txt         | 591 +++++++++++++++++
 .../libraries/HardwareCAN/src/utility/can.h   |   1 +
 .../HardwareCAN/src/utility/can.temp.c        | 599 ++++++++++++++++++
 4 files changed, 1237 insertions(+), 19 deletions(-)
 create mode 100644 STM32F1/libraries/HardwareCAN/src/utility/can.c.txt
 create mode 100644 STM32F1/libraries/HardwareCAN/src/utility/can.temp.c

diff --git a/STM32F1/libraries/HardwareCAN/src/utility/can.c b/STM32F1/libraries/HardwareCAN/src/utility/can.c
index 954e6e349..324800804 100644
--- a/STM32F1/libraries/HardwareCAN/src/utility/can.c
+++ b/STM32F1/libraries/HardwareCAN/src/utility/can.c
@@ -1,9 +1,4 @@
-//#include "libmaple.h"
 #include "can.h"
-//#include "rcc.h"
-//#include "gpio.h"
-//#include "nvic.h"
-//#include "usb.h"
 
 /**
   *	CAN_interrupts
@@ -85,10 +80,10 @@ static const struct can_speed_info can_speed_table[] = {
 CAN_STATUS status;
 CanMsg can_rx_queue[CAN_RX_QUEUE_SIZE];
 
-uint8 can_rx_head;
-uint8 can_rx_tail;
-uint8 can_rx_count;
-uint8 can_rx_lost;
+// JMD 2017/07/18 -- added volatile to fix queue problems, removed can_rx_count
+volatile uint8 can_rx_head;
+volatile uint8 can_rx_tail;
+volatile uint8 can_rx_lost;
 uint8 can_active = 0;
 
 /**
@@ -149,7 +144,10 @@ CAN_STATUS can_deinit(CAN_Port* CANx)
 	if (CANx == CAN1_BASE)
 	{
 		nvic_irq_disable(NVIC_USB_LP_CAN_RX0);	// Disable interrupts
+		nvic_irq_disable(NVIC_CAN_RX1);
 		nvic_irq_disable(NVIC_USB_HP_CAN_TX);
+		__asm volatile( "dsb" );						// Synchronization of the pipeline to guarantee
+		__asm volatile( "isb" );						// that the protection against interrupts is effective
 		rcc_reset_dev(RCC_CAN);
 		rcc_clk_disable(RCC_CAN);
 		can_active = 0;
@@ -173,11 +171,10 @@ CAN_STATUS can_init(CAN_Port* CANx, uint32 control, uint8 speed)
 {
 	status = CAN_INIT_FAILED;			// default result status
 										// initialize receive message queue
-	can_rx_head = can_rx_tail = can_rx_count = can_rx_lost = 0;
+	can_rx_head = can_rx_tail = can_rx_lost = 0;
 
 	rcc_reset_dev(RCC_USB);			//! X893
 	rcc_clk_disable(RCC_USB);		//! X893
-//	line_dtr_rts = 0;				//! X893
 	rcc_clk_enable(RCC_AFIO);			// enable clocks for AFIO
 	rcc_clk_enable(RCC_CAN);			// and CAN
 	rcc_reset_dev(RCC_CAN);				// reset CAN interface
@@ -196,6 +193,7 @@ CAN_STATUS can_init(CAN_Port* CANx, uint32 control, uint8 speed)
 	CANx->BTR |= (can_speed_table[speed].btr & CAN_TIMING_MASK);
 
 	nvic_irq_enable(NVIC_USB_LP_CAN_RX0);	// Enable interrupts
+	nvic_irq_enable(NVIC_CAN_RX1);
     
 	nvic_irq_enable(NVIC_USB_HP_CAN_TX);
 
@@ -453,30 +451,54 @@ void can_cancel(CAN_Port* CANx, uint8 mbx)
 void can_rx_queue_clear(void)
 {
 	nvic_irq_disable(NVIC_USB_LP_CAN_RX0);
-	can_rx_head = can_rx_tail = can_rx_count = can_rx_lost = 0;
+	nvic_irq_disable(NVIC_CAN_RX1);
+	__asm volatile( "dsb" );						// Synchronization of the pipeline to guarantee
+	__asm volatile( "isb" );						// that the protection against interrupts is effective
+	can_rx_head = can_rx_tail = can_rx_lost = 0;					// JMD 2017/07/18
 	nvic_irq_enable(NVIC_USB_LP_CAN_RX0);
+	nvic_irq_enable(NVIC_CAN_RX1);
 }
 
+// JMD 2017/07/18 -- changed
 uint8 can_rx_available(void)
 {
-	return can_rx_count;
+	if ( can_rx_head >= can_rx_tail )
+		return can_rx_head - can_rx_tail ;
+	else
+		return CAN_RX_QUEUE_SIZE - ( can_rx_tail - can_rx_head ) ;
+}
+
+// JMD 2017/07/18 -- added
+uint8 can_frame_lost(void)
+{
+	if ( can_rx_lost != 0 )
+	{
+		can_rx_lost = 0 ;
+		return 1 ;
+	}
+	return 0 ;
+	
 }
 
 CanMsg* can_rx_queue_get(void)
 {
-	if (can_rx_count == 0)
+	if (can_rx_head == can_rx_tail)			// JMD 2017/07/18 -- changed
 		return NULL;
 	return &(can_rx_queue[can_rx_tail]);
 }
 
+
 void can_rx_queue_free(void)
 {
-	if (can_rx_count > 0)
+	if (can_rx_head != can_rx_tail)			// JMD 2017/07/18 -- changed
 	{
-		nvic_irq_disable(NVIC_USB_LP_CAN_RX0);			// JMD problème d'atomicité
+		nvic_irq_disable(NVIC_USB_LP_CAN_RX0);			// JMD atomicity problem
+		nvic_irq_disable(NVIC_CAN_RX1);
+		__asm volatile( "dsb" );						// Synchronization of the pipeline to guarantee
+		__asm volatile( "isb" );						// that the protection against interrupts is effective
 		can_rx_tail = (can_rx_tail == (CAN_RX_QUEUE_SIZE - 1)) ? 0 : (can_rx_tail + 1);
-		--can_rx_count;
 		nvic_irq_enable(NVIC_USB_LP_CAN_RX0);			// fin JMD problème d'atomicité
+		nvic_irq_enable(NVIC_CAN_RX1);
 	}
 }
 
@@ -527,12 +549,11 @@ void can_rx_release(CAN_Port* CANx, CAN_FIFO fifo)
 
 void can_rx_read(CAN_Port* CANx, CAN_FIFO fifo)
 {
-	if (can_rx_count < CAN_RX_QUEUE_SIZE)		// read the message
+	if (can_rx_available() < CAN_RX_QUEUE_SIZE)		// read the message
 	{
 		CanMsg* msg = &can_rx_queue[can_rx_head];
 		can_read(CANx, fifo, msg);
 		can_rx_head = (can_rx_head == (CAN_RX_QUEUE_SIZE - 1)) ? 0 : (can_rx_head + 1);
-		can_rx_count++;
 	}
 	else
 		can_rx_lost = 1;						// no place in queue, ignore package
@@ -552,6 +573,12 @@ uint8 CAN_RX0_IRQ_Handler(void)
 	return can_active;								// return CAN active flag to USB handler
 }
 
+// Addition JMD: the messages stored in fifo1 must also trigger an interrupt.
+void __irq_can_rx1(void)
+{
+	CAN_RX0_IRQ_Handler() ;
+}
+
 void USB_HP_CAN_TX_IRQHandler (void)
 {
 	if (can_active)
diff --git a/STM32F1/libraries/HardwareCAN/src/utility/can.c.txt b/STM32F1/libraries/HardwareCAN/src/utility/can.c.txt
new file mode 100644
index 000000000..64cedac5e
--- /dev/null
+++ b/STM32F1/libraries/HardwareCAN/src/utility/can.c.txt
@@ -0,0 +1,591 @@
+//#include "libmaple.h"
+#include "can.h"
+//#include "rcc.h"
+//#include "gpio.h"
+//#include "nvic.h"
+//#include "usb.h"
+
+/**
+  *	CAN_interrupts
+  */
+
+#define CAN_IT_RQCP0	((uint32)0x00000005) /* Request completed mailbox 0 */
+#define CAN_IT_RQCP1	((uint32)0x00000006) /* Request completed mailbox 1 */
+#define CAN_IT_RQCP2	((uint32)0x00000007) /* Request completed mailbox 2 */
+#define CAN_IT_TME		((uint32)0x00000001) /* Transmit mailbox empty */
+#define CAN_IT_FMP0		((uint32)0x00000002) /* FIFO 0 message pending */
+#define CAN_IT_FF0		((uint32)0x00000004) /* FIFO 0 full */
+#define CAN_IT_FOV0		((uint32)0x00000008) /* FIFO 0 overrun */
+#define CAN_IT_FMP1		((uint32)0x00000010) /* FIFO 1 message pending */
+#define CAN_IT_FF1		((uint32)0x00000020) /* FIFO 1 full */
+#define CAN_IT_FOV1		((uint32)0x00000040) /* FIFO 1 overrun */
+#define CAN_IT_EWG		((uint32)0x00000100) /* Error warning */
+#define CAN_IT_EPV		((uint32)0x00000200) /* Error passive */
+#define CAN_IT_BOF		((uint32)0x00000400) /* Bus-off */
+#define CAN_IT_LEC		((uint32)0x00000800) /* Last error code */
+#define CAN_IT_ERR		((uint32)0x00008000) /* Error */
+#define CAN_IT_WKU		((uint32)0x00010000) /* Wake-up */
+#define CAN_IT_SLK		((uint32)0x00020000) /* Sleep */
+
+/* Time out for INAK bit */
+#define CAN_INAK_TimeOut	((uint32)0x0000FFFF)
+
+/* Time out for SLAK bit */
+#define CAN_SLAK_TimeOut	((uint32)0x0000FFFF)
+
+#define CAN_CONTROL_MASK	(CAN_MCR_TTCM | CAN_MCR_ABOM | CAN_MCR_AWUM | CAN_MCR_NART | CAN_MCR_RFLM | CAN_MCR_TXFP)
+#define CAN_TIMING_MASK		(CAN_BTR_SJW | CAN_BTR_TS2 | CAN_BTR_TS1 | CAN_BTR_BRP)
+#define CAN_MODE_MASK		(CAN_BTR_LBKM | CAN_BTR_SILM)
+
+struct can_speed_info {
+    const uint32 btr;
+};
+
+#define CAN_CLOCK	(36000000UL / 18UL)
+
+static const struct can_speed_info can_speed_table[] = {
+	[CAN_SPEED_125]		= { .btr = (
+		(( 4-1) << CAN_BTR_SJW_POS) |
+		((12-1) << CAN_BTR_TS1_POS) |
+		(( 5-1) << CAN_BTR_TS2_POS) |
+		(CAN_CLOCK / 125000UL - 1)
+		)},
+	[CAN_SPEED_250]		= { .btr = (
+		(( 4-1) << CAN_BTR_SJW_POS) |
+		((12-1) << CAN_BTR_TS1_POS) |
+		(( 5-1) << CAN_BTR_TS2_POS) |
+		(CAN_CLOCK / 250000UL - 1)
+		)},
+	[CAN_SPEED_500]		= { .btr = (
+		(( 4-1) << CAN_BTR_SJW_POS) |
+		((12-1) << CAN_BTR_TS1_POS) |
+		(( 5-1) << CAN_BTR_TS2_POS) |
+		(CAN_CLOCK / 500000UL - 1)
+		)},
+	[CAN_SPEED_1000]	= { .btr = (
+		(( 4-1) << CAN_BTR_SJW_POS) |
+		((12-1) << CAN_BTR_TS1_POS) |
+		(( 5-1) << CAN_BTR_TS2_POS) |
+		(CAN_CLOCK / 1000000UL - 1)
+		)}
+};
+
+CAN_STATUS status;
+CanMsg can_rx_queue[CAN_RX_QUEUE_SIZE];
+
+// JMD 2017/07/18 -- added volatile to fix queue problems 
+volatile uint8 can_rx_head;
+volatile uint8 can_rx_tail;
+//volatile uint8 can_rx_count;		// JMD 2017/07/18 -- redundant
+volatile uint8 can_rx_lost;
+uint8 can_active = 0;
+
+/**
+  * @brief  Return last operation status
+  */
+CAN_STATUS can_status(void)
+{
+	return status;
+}
+
+/**
+  * @brief  Enter initialization mode
+  */
+CAN_STATUS can_init_enter(CAN_Port* CANx)
+{
+	volatile uint32 wait_ack = 0 ;
+    
+	status = CAN_OK;
+	if ((CANx->MSR & CAN_MSR_INAK) == 0)	// Check for initialization mode already set
+	{
+		CANx->MCR |= CAN_MCR_INRQ;			// Request initialisation
+
+		wait_ack = 0;						// Wait the acknowledge
+		while ((wait_ack != CAN_INAK_TimeOut) && ((CANx->MSR & CAN_MSR_INAK) == 0))
+			wait_ack++;
+		if ((CANx->MSR & CAN_MSR_INAK) == 0)
+			status = CAN_INIT_E_FAILED;		// Timeout
+	}
+	return status;
+}
+
+/**
+  * @brief  Leave initialization mode
+  */
+CAN_STATUS can_init_leave(CAN_Port* CANx)
+{
+	volatile uint32 wait_ack = 0 ;
+
+	status = CAN_OK;
+	if ((CANx->MSR & CAN_MSR_INAK) != 0)	// Check for initialization mode already reset
+	{
+		CANx->MCR &= ~CAN_MCR_INRQ;			// Clear Request initialization
+
+		wait_ack = 0;						// Wait the acknowledge
+		while ((wait_ack != CAN_INAK_TimeOut) && ((CANx->MSR & CAN_MSR_INAK) != 0))
+			wait_ack++;
+		if ((CANx->MSR & CAN_MSR_INAK) != 0)
+			status = CAN_INIT_L_FAILED;
+	}
+	return status;
+}
+
+/**
+  * @brief  Deinitializes the CAN peripheral registers to their default reset values.
+  */
+CAN_STATUS can_deinit(CAN_Port* CANx)
+{
+	if (CANx == CAN1_BASE)
+	{
+		nvic_irq_disable(NVIC_USB_LP_CAN_RX0);	// Disable interrupts
+		nvic_irq_disable(NVIC_CAN_RX1);
+		nvic_irq_disable(NVIC_USB_HP_CAN_TX);
+		__asm volatile( "dsb" );						// Synchronization of the pipeline to guarantee
+		__asm volatile( "isb" );						// that the protection against interrupts is effective
+		rcc_reset_dev(RCC_CAN);
+		rcc_clk_disable(RCC_CAN);
+		can_active = 0;
+	}
+	return (status = CAN_OK);
+}
+
+/**
+  * @brief  Initialize CAN registers
+  */
+/*
+ *		Bits in control parameter:
+ *			CAN_MCR_TTCM	time triggered communication mode
+ *			CAN_MCR_ABOM	automatic bus-off management
+ *			CAN_MCR_AWUM	automatic wake-up mode
+ *			CAN_MCR_NART	no automatic retransmission
+ *			CAN_MCR_RFLM	receive FIFO locked mode
+ *			CAN_MCR_TXFP	transmit FIFO priority
+ */
+CAN_STATUS can_init(CAN_Port* CANx, uint32 control, uint8 speed)
+{
+	status = CAN_INIT_FAILED;			// default result status
+										// initialize receive message queue
+//	can_rx_head = can_rx_tail = can_rx_count = can_rx_lost = 0;		// JMD 2017/07/18
+	can_rx_head = can_rx_tail = can_rx_lost = 0;
+
+	rcc_reset_dev(RCC_USB);			//! X893
+	rcc_clk_disable(RCC_USB);		//! X893
+//	line_dtr_rts = 0;				//! X893
+	rcc_clk_enable(RCC_AFIO);			// enable clocks for AFIO
+	rcc_clk_enable(RCC_CAN);			// and CAN
+	rcc_reset_dev(RCC_CAN);				// reset CAN interface
+
+	can_active = 1;						// set CAN active flag (for interrupt handler
+
+	CANx->MCR &= ~CAN_MCR_SLEEP;		// reset CAN sleep mode (default after reset)
+
+	if (can_init_enter(CANx) != CAN_OK)	// enter CAN initialization mode
+		return status;					// error, so return
+
+	CANx->MCR &= ~CAN_CONTROL_MASK;		// set mode bits
+	CANx->MCR |= (control & CAN_CONTROL_MASK);
+
+	CANx->BTR &= ~CAN_TIMING_MASK;			// Set the bit timing register
+	CANx->BTR |= (can_speed_table[speed].btr & CAN_TIMING_MASK);
+
+	nvic_irq_enable(NVIC_USB_LP_CAN_RX0);	// Enable interrupts
+	nvic_irq_enable(NVIC_CAN_RX1);
+    
+	nvic_irq_enable(NVIC_USB_HP_CAN_TX);
+
+	CANx->IER = (CAN_IER_FMPIE0 | CAN_IER_FMPIE1 | CAN_IER_TMEIE);
+
+	if (can_init_leave(CANx) == CAN_OK)
+	{
+		while (!(CANx->TSR & CAN_TSR_TME0));	// Transmit mailbox 0 is empty
+		while (!(CANx->TSR & CAN_TSR_TME1));	// Transmit mailbox 0 is empty
+		while (!(CANx->TSR & CAN_TSR_TME2));	// Transmit mailbox 0 is empty
+	} 
+	return status;
+}
+
+/**
+  * @brief  Set timing calues (CAN_BTR)
+  */
+CAN_STATUS can_set_timing(CAN_Port* CANx, uint32 timing)
+{
+	if (can_init_enter(CANx) == CAN_OK)
+	{
+		CANx->BTR = ((CANx->BTR & ~CAN_TIMING_MASK) | (timing & CAN_TIMING_MASK));
+		can_init_leave(CANx);
+	}
+	return status;
+}
+
+/**
+  * @brief  Set CAN mode
+  * @param CANx pointer to CAN port
+  * @param mode CAN mode
+  */
+CAN_STATUS can_set_mode(CAN_Port* CANx, uint32 mode)
+{
+	if (can_init_enter(CANx) == CAN_OK)
+	{
+		CANx->BTR &= ~CAN_MODE_MASK;
+		CANx->BTR |= (mode & CAN_MODE_MASK);
+		can_init_leave(CANx);
+	}
+	return status;
+}
+
+/**
+  * @brief  Set CAN to GPIO mapping
+  */
+CAN_STATUS can_gpio_map(CAN_Port* CANx, CAN_GPIO_MAP map_mode)
+{
+	rcc_clk_enable(RCC_AFIO);
+
+	status = CAN_INIT_FAILED;
+	if( CANx == CAN1_BASE)
+	{
+		switch(map_mode)
+		{
+		case CAN_GPIO_PB8_PB9:
+			rcc_clk_enable(RCC_GPIOB);
+			afio_remap(AFIO_MAPR_CAN_REMAP_PB8_PB9);
+			gpio_set_mode(GPIOB, 8, GPIO_INPUT_FLOATING);
+			gpio_set_mode(GPIOB, 9, GPIO_AF_OUTPUT_PP);
+			break;
+#if NR_GPIO_PORTS >= 4
+		case CAN_GPIO_PD0_PD1:
+			rcc_clk_enable(RCC_GPIOD);
+			afio_remap(AFIO_MAPR_CAN_REMAP_PD0_PD1);
+			gpio_set_mode(GPIOD, 0, GPIO_INPUT_FLOATING);
+			gpio_set_mode(GPIOD, 1, GPIO_AF_OUTPUT_PP);
+			break;
+#endif
+		default:
+			return status;
+		}
+		status = CAN_OK;
+	}
+	return status;
+}
+
+CAN_STATUS can_filter(CAN_Port* CANx, uint8 filter_idx, CAN_FIFO fifo, CAN_FILTER_SCALE scale, CAN_FILTER_MODE mode, uint32 fr1, uint32 fr2)
+{
+	uint32 mask = ((uint32)0x00000001) << filter_idx;
+
+	CANx->FMR |= CAN_FMR_FINIT;		// Initialization mode for the filter
+	CANx->FA1R &= ~mask;			// Deactivation filter
+
+
+	if (scale == CAN_FILTER_32BIT)
+		CANx->FS1R |= mask;
+	else
+		CANx->FS1R &= ~mask;
+
+	CANx->sFilterRegister[filter_idx].FR1 = fr1;
+	CANx->sFilterRegister[filter_idx].FR2 = fr2;
+
+	if (mode == CAN_FILTER_MASK)
+		CANx->FM1R &= ~mask;
+	else
+		CANx->FM1R |= mask;
+
+	if (fifo == CAN_FIFO0)
+		CANx->FFA1R &= ~mask;
+	else
+		CANx->FFA1R |= mask;
+
+	CANx->FA1R |= mask;
+	CANx->FMR &= ~CAN_FMR_FINIT;
+	return CAN_OK;
+}
+
+
+/**
+  * @brief  Initiates the transmission of a message.
+  * @param	CANx: where x can be 1 to select the CAN peripheral.
+  * @param	msg: pointer to a structure which contains CAN Id, CAN DLC and CAN datas.
+  * @retval : The number of the mailbox that is used for transmission or CAN_NO_MB if there is no empty mailbox.
+  */
+CAN_TX_MBX can_transmit(CAN_Port* CANx, CanMsg* msg)
+{
+	CAN_TX_MBX mbx;
+	uint32 data;
+
+	/* Select one empty transmit mailbox */
+	if (CANx->TSR & CAN_TSR_TME0)
+		mbx = CAN_TX_MBX0;
+	else if (CANx->TSR & CAN_TSR_TME1)
+		mbx = CAN_TX_MBX1;
+	else if (CANx->TSR & CAN_TSR_TME2)
+		mbx = CAN_TX_MBX2;
+	else
+	{
+		status = CAN_NO_MB;
+		return CAN_TX_NO_MBX;
+	}
+
+    /* Set up the Id */
+    if (msg->IDE == CAN_ID_STD)
+		data = (msg->ID << 21);
+    else
+		data = (msg->ID << 3) | CAN_ID_EXT;
+
+	data |= ((uint32)msg->RTR);
+
+	/* Set up the DLC */
+    CANx->sTxMailBox[mbx].TDTR = (uint32)(msg->DLC & 0x0F);
+
+    /* Set up the data field */
+    CANx->sTxMailBox[mbx].TDLR = (
+		((uint32)msg->Data[3] << 24) | 
+		((uint32)msg->Data[2] << 16) |
+		((uint32)msg->Data[1] << 8) | 
+		((uint32)msg->Data[0])
+		);
+    CANx->sTxMailBox[mbx].TDHR = (
+		((uint32)msg->Data[7] << 24) |
+		((uint32)msg->Data[6] << 16) |
+		((uint32)msg->Data[5] << 8) |
+		((uint32)msg->Data[4])
+		);
+    /* Request transmission */
+    CANx->sTxMailBox[mbx].TIR = (data | CAN_TMIDxR_TXRQ);
+	status = CAN_OK;
+
+	return mbx;
+}
+
+/**
+  * Checks the transmission of a message.
+  * @param CANx: where x can be 1 to select the CAN peripheral.
+  * @param mbx: the number of the mailbox that is used for transmission.
+  * @retval : CAN_TX_OK if the CAN driver transmits the message, CAN_TX_FAILED in an other case.
+  */
+CAN_STATUS can_tx_status(CAN_Port* CANx, CAN_TX_MBX mbx)
+{
+	/* RQCP, TXOK and TME bits */
+	uint8 state = 0;
+
+	switch (mbx)
+	{
+	case CAN_TX_MBX0:
+		state |= (uint8)((CANx->TSR & CAN_TSR_RQCP0) << 2);
+		state |= (uint8)((CANx->TSR & CAN_TSR_TXOK0) >> 0);
+		state |= (uint8)((CANx->TSR & CAN_TSR_TME0) >> 26);
+		break;
+	case CAN_TX_MBX1:
+		state |= (uint8)((CANx->TSR & CAN_TSR_RQCP1) >> 6);
+		state |= (uint8)((CANx->TSR & CAN_TSR_TXOK1) >> 8);
+		state |= (uint8)((CANx->TSR & CAN_TSR_TME1) >> 27);
+		break;
+	case CAN_TX_MBX2:
+		state |= (uint8)((CANx->TSR & CAN_TSR_RQCP2) >> 14);
+		state |= (uint8)((CANx->TSR & CAN_TSR_TXOK2) >> 16);
+		state |= (uint8)((CANx->TSR & CAN_TSR_TME2) >> 28);
+		break;
+	default:
+		status = CAN_TX_FAILED;
+		return status;
+	}
+
+	// state = RQCP TXOK TME
+	switch (state)
+	{
+	/* transmit pending  */
+	case 0x0:
+		status = CAN_TX_PENDING;
+		break;
+	/* transmit failed  */
+	case 0x5:
+		status = CAN_TX_FAILED;
+		break;
+	/* transmit succedeed  */
+	case 0x7:
+		status = CAN_OK;
+		break;
+	default:
+		status = CAN_TX_FAILED;
+		break;
+	}
+	return status;
+}
+
+/**
+  * @brief  Cancels a transmit request.
+  * @param CANx: where x can be 1 to select the CAN peripheral.
+  * @param mbx: Mailbox number.
+  * @retval : None.
+  */
+void can_cancel(CAN_Port* CANx, uint8 mbx)
+{
+	/* abort transmission */
+	switch (mbx)
+	{
+	case 0:
+		CANx->TSR |= CAN_TSR_ABRQ0;
+		break;
+	case 1:
+		CANx->TSR |= CAN_TSR_ABRQ1;
+		break;
+	case 2:
+		CANx->TSR |= CAN_TSR_ABRQ2;
+		break;
+	default:
+		break;
+	}
+}
+
+void can_rx_queue_clear(void)
+{
+	nvic_irq_disable(NVIC_USB_LP_CAN_RX0);
+	nvic_irq_disable(NVIC_CAN_RX1);
+	__asm volatile( "dsb" );						// Synchronization of the pipeline to guarantee
+	__asm volatile( "isb" );						// that the protection against interrupts is effective
+//	can_rx_head = can_rx_tail = can_rx_count = can_rx_lost = 0;		// JMD 2017/07/18
+	can_rx_head = can_rx_tail = can_rx_lost = 0;					// JMD 2017/07/18
+	nvic_irq_enable(NVIC_USB_LP_CAN_RX0);
+	nvic_irq_enable(NVIC_CAN_RX1);
+}
+
+// JMD 2017/07/18 -- removed
+/*
+uint8 can_rx_available(void)
+{
+	return can_rx_count;
+}
+*/
+
+// JMD 2017/07/18 -- added
+uint8 can_rx_available(void)
+{
+	if ( can_rx_head >= can_rx_tail )
+		return can_rx_head - can_rx_tail ;
+	else
+		return CAN_RX_QUEUE_SIZE - ( can_rx_tail - can_rx_head ) ;
+}
+
+// JMD 2017/07/18 -- added
+uint8 can_frame_lost(void)
+{
+	if ( can_rx_lost != 0 )
+	{
+		can_rx_lost = 0 ;
+		return 1 ;
+	}
+	return 0 ;
+	
+}
+
+CanMsg* can_rx_queue_get(void)
+{
+	if (can_rx_head == can_rx_tail)			// JMD 2017/07/18 -- changed
+		return NULL;
+	return &(can_rx_queue[can_rx_tail]);
+}
+
+
+void can_rx_queue_free(void)
+{
+	if (can_rx_head != can_rx_tail)			// JMD 2017/07/18 -- changed
+	{
+		nvic_irq_disable(NVIC_USB_LP_CAN_RX0);			// JMD atomicity problem
+		nvic_irq_disable(NVIC_CAN_RX1);
+		__asm volatile( "dsb" );						// Synchronization of the pipeline to guarantee
+		__asm volatile( "isb" );						// that the protection against interrupts is effective
+		can_rx_tail = (can_rx_tail == (CAN_RX_QUEUE_SIZE - 1)) ? 0 : (can_rx_tail + 1);
+//		--can_rx_count;									// JMD 2017/07/18 -- removed
+		nvic_irq_enable(NVIC_USB_LP_CAN_RX0);			// fin JMD problème d'atomicité
+		nvic_irq_enable(NVIC_CAN_RX1);
+	}
+}
+
+CanMsg* can_read(CAN_Port* CANx, CAN_FIFO fifo, CanMsg* msg)
+{
+	uint32 data = CANx->sFIFOMailBox[fifo].RIR;
+
+	/* Get the Id */
+	if (data & CAN_ID_EXT)
+	{
+		msg->ID = 0x1FFFFFFF & (data >> 3);
+		msg->IDE = (uint8)CAN_ID_EXT;
+	}
+	else
+	{
+		msg->ID = 0x000007FF & (data >> 21);
+		msg->IDE = (uint8)CAN_ID_STD;
+	}
+
+	msg->RTR = (uint8)(CAN_RTR_REMOTE & data);
+	msg->DLC = (uint8)(0x0F & CANx->sFIFOMailBox[fifo].RDTR);
+	msg->FMI = (uint8)(0xFF & (CANx->sFIFOMailBox[fifo].RDTR >> 8));
+
+	/* Get the data field */
+	data = CANx->sFIFOMailBox[fifo].RDLR;
+	uint8* p = msg->Data;
+	*p++ = (uint8)0xFF & data;
+	*p++ = (uint8)0xFF & (data >> 8);
+	*p++ = (uint8)0xFF & (data >> 16);
+	*p++ = (uint8)0xFF & (data >> 24);
+
+	data = CANx->sFIFOMailBox[fifo].RDHR;
+	*p++ = (uint8)0xFF & data;
+	*p++ = (uint8)0xFF & (data >> 8);
+	*p++ = (uint8)0xFF & (data >> 16);
+	*p++ = (uint8)0xFF & (data >> 24);
+
+	return msg;
+}
+
+void can_rx_release(CAN_Port* CANx, CAN_FIFO fifo)
+{
+	if (fifo == CAN_FIFO0)
+		CANx->RF0R |= (CAN_RF0R_RFOM0);	// Release FIFO0
+	else
+		CANx->RF1R |= (CAN_RF1R_RFOM1);	// Release FIFO1
+}
+
+void can_rx_read(CAN_Port* CANx, CAN_FIFO fifo)
+{
+//	if (can_rx_count < CAN_RX_QUEUE_SIZE)		// JMD 2017/07/18
+	if (can_rx_available() < CAN_RX_QUEUE_SIZE)		// read the message
+	{
+		CanMsg* msg = &can_rx_queue[can_rx_head];
+		can_read(CANx, fifo, msg);
+		can_rx_head = (can_rx_head == (CAN_RX_QUEUE_SIZE - 1)) ? 0 : (can_rx_head + 1);
+//		can_rx_count++;						// JMD 2017/07/18 -- removed
+	}
+	else
+		can_rx_lost = 1;						// no place in queue, ignore package
+
+	can_rx_release(CANx, fifo);
+}
+
+uint8 CAN_RX0_IRQ_Handler(void)
+{
+	if (can_active)
+	{
+		while ((CAN1_BASE->RF0R & CAN_RF0R_FMP0) != 0)
+			can_rx_read(CAN1_BASE, CAN_FIFO0);		// message pending FIFO0
+		while ((CAN1_BASE->RF1R & CAN_RF1R_FMP1) != 0)
+			can_rx_read(CAN1_BASE, CAN_FIFO1);		// message pending FIFO1
+	}
+	return can_active;								// return CAN active flag to USB handler
+}
+
+// Addition JMD: the messages stored in fifo1 must also trigger an interrupt.
+void __irq_can_rx1(void)
+{
+	CAN_RX0_IRQ_Handler() ;
+}
+
+void USB_HP_CAN_TX_IRQHandler (void)
+{
+	if (can_active)
+	{
+		if (CAN1_BASE->TSR & CAN_TSR_RQCP0)
+			CAN1_BASE->TSR |= CAN_TSR_RQCP0;		// reset request complete mbx 0
+		if (CAN1_BASE->TSR & CAN_TSR_RQCP1)
+			CAN1_BASE->TSR |= CAN_TSR_RQCP1;		// reset request complete mbx 1
+		if (CAN1_BASE->TSR & CAN_TSR_RQCP2)
+			CAN1_BASE->TSR |= CAN_TSR_RQCP2;		// reset request complete mbx 2
+	}
+}
diff --git a/STM32F1/libraries/HardwareCAN/src/utility/can.h b/STM32F1/libraries/HardwareCAN/src/utility/can.h
index 19506ea85..1f2966243 100644
--- a/STM32F1/libraries/HardwareCAN/src/utility/can.h
+++ b/STM32F1/libraries/HardwareCAN/src/utility/can.h
@@ -288,6 +288,7 @@ CAN_STATUS can_status(void);
 void can_cancel(CAN_Port* CANx, uint8 mbx);
 void can_rx_queue_clear(void);
 uint8 can_rx_available(void);
+uint8 can_frame_lost(void);
 CanMsg* can_rx_queue_get(void);
 CanMsg* can_read(CAN_Port* CANx, CAN_FIFO fifo, CanMsg* msg);
 void can_rx_release(CAN_Port* CANx, CAN_FIFO fifo);
diff --git a/STM32F1/libraries/HardwareCAN/src/utility/can.temp.c b/STM32F1/libraries/HardwareCAN/src/utility/can.temp.c
new file mode 100644
index 000000000..e9b270c81
--- /dev/null
+++ b/STM32F1/libraries/HardwareCAN/src/utility/can.temp.c
@@ -0,0 +1,599 @@
+Skip to content
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+ Watch 3  Star 2  Fork 363 megadrifter/Arduino_STM32
+forked from Phonog/Arduino_STM32
+ Code  Pull requests 0  Projects 0 Insights 
+Branch: megadrifter-GM… Find file Copy pathArduino_STM32/STM32F1/libraries/HardwareCAN/src/utility/can.c
+a9807d2  9 days ago
+@megadrifter megadrifter CAN filter corrected by tjb12345
+2 contributors @megadrifter @Phonog
+RawBlameHistory     
+567 lines (500 sloc)  14.3 KB
+#include "can.h"
+
+/**
+  *	CAN_interrupts
+  */
+
+#define CAN_IT_RQCP0	((uint32)0x00000005) /* Request completed mailbox 0 */
+#define CAN_IT_RQCP1	((uint32)0x00000006) /* Request completed mailbox 1 */
+#define CAN_IT_RQCP2	((uint32)0x00000007) /* Request completed mailbox 2 */
+#define CAN_IT_TME		((uint32)0x00000001) /* Transmit mailbox empty */
+#define CAN_IT_FMP0		((uint32)0x00000002) /* FIFO 0 message pending */
+#define CAN_IT_FF0		((uint32)0x00000004) /* FIFO 0 full */
+#define CAN_IT_FOV0		((uint32)0x00000008) /* FIFO 0 overrun */
+#define CAN_IT_FMP1		((uint32)0x00000010) /* FIFO 1 message pending */
+#define CAN_IT_FF1		((uint32)0x00000020) /* FIFO 1 full */
+#define CAN_IT_FOV1		((uint32)0x00000040) /* FIFO 1 overrun */
+#define CAN_IT_EWG		((uint32)0x00000100) /* Error warning */
+#define CAN_IT_EPV		((uint32)0x00000200) /* Error passive */
+#define CAN_IT_BOF		((uint32)0x00000400) /* Bus-off */
+#define CAN_IT_LEC		((uint32)0x00000800) /* Last error code */
+#define CAN_IT_ERR		((uint32)0x00008000) /* Error */
+#define CAN_IT_WKU		((uint32)0x00010000) /* Wake-up */
+#define CAN_IT_SLK		((uint32)0x00020000) /* Sleep */
+
+/* Time out for INAK bit */
+#define CAN_INAK_TimeOut	((uint32)0x0000FFFF)
+
+/* Time out for SLAK bit */
+#define CAN_SLAK_TimeOut	((uint32)0x0000FFFF)
+
+#define CAN_CONTROL_MASK	(CAN_MCR_TTCM | CAN_MCR_ABOM | CAN_MCR_AWUM | CAN_MCR_NART | CAN_MCR_RFLM | CAN_MCR_TXFP)
+#define CAN_TIMING_MASK		(CAN_BTR_SJW | CAN_BTR_TS2 | CAN_BTR_TS1 | CAN_BTR_BRP)
+#define CAN_MODE_MASK		(CAN_BTR_LBKM | CAN_BTR_SILM)
+
+struct can_speed_info {
+    const uint32 btr;
+};
+
+#define CAN_CLOCK	(36000000UL / 18UL)
+
+static const struct can_speed_info can_speed_table[] = {
+	[CAN_SPEED_125]		= { .btr = (
+		(( 4-1) << CAN_BTR_SJW_POS) |
+		((12-1) << CAN_BTR_TS1_POS) |
+		(( 5-1) << CAN_BTR_TS2_POS) |
+		(CAN_CLOCK / 125000UL - 1)
+		)},
+	[CAN_SPEED_250]		= { .btr = (
+		(( 4-1) << CAN_BTR_SJW_POS) |
+		((12-1) << CAN_BTR_TS1_POS) |
+		(( 5-1) << CAN_BTR_TS2_POS) |
+		(CAN_CLOCK / 250000UL - 1)
+		)},
+	[CAN_SPEED_500]		= { .btr = (
+		(( 4-1) << CAN_BTR_SJW_POS) |
+		((12-1) << CAN_BTR_TS1_POS) |
+		(( 5-1) << CAN_BTR_TS2_POS) |
+		(CAN_CLOCK / 500000UL - 1)
+		)},
+	[CAN_SPEED_1000]	= { .btr = (
+		(( 4-1) << CAN_BTR_SJW_POS) |
+		((12-1) << CAN_BTR_TS1_POS) |
+		(( 5-1) << CAN_BTR_TS2_POS) |
+		(CAN_CLOCK / 1000000UL - 1)
+		)}
+};
+
+CAN_STATUS status;
+CanMsg can_rx_queue[CAN_RX_QUEUE_SIZE];
+
+// JMD 2017/07/18 -- added volatile to fix queue problems, removed can_rx_count
+volatile uint8 can_rx_head;
+volatile uint8 can_rx_tail;
+volatile uint8 can_rx_lost;
+uint8 can_active = 0;
+
+/**
+  * @brief  Return last operation status
+  */
+CAN_STATUS can_status(void)
+{
+	return status;
+}
+
+/**
+  * @brief  Enter initialization mode
+  */
+CAN_STATUS can_init_enter(CAN_Port* CANx)
+{
+	volatile uint32 wait_ack = 0 ;
+    
+	status = CAN_OK;
+	if ((CANx->MSR & CAN_MSR_INAK) == 0)	// Check for initialization mode already set
+	{
+		CANx->MCR |= CAN_MCR_INRQ;			// Request initialisation
+
+		wait_ack = 0;						// Wait the acknowledge
+		while ((wait_ack != CAN_INAK_TimeOut) && ((CANx->MSR & CAN_MSR_INAK) == 0))
+			wait_ack++;
+		if ((CANx->MSR & CAN_MSR_INAK) == 0)
+			status = CAN_INIT_E_FAILED;		// Timeout
+	}
+	return status;
+}
+
+/**
+  * @brief  Leave initialization mode
+  */
+CAN_STATUS can_init_leave(CAN_Port* CANx)
+{
+	volatile uint32 wait_ack = 0 ;
+
+	status = CAN_OK;
+	if ((CANx->MSR & CAN_MSR_INAK) != 0)	// Check for initialization mode already reset
+	{
+		CANx->MCR &= ~CAN_MCR_INRQ;			// Clear Request initialization
+
+		wait_ack = 0;						// Wait the acknowledge
+		while ((wait_ack != CAN_INAK_TimeOut) && ((CANx->MSR & CAN_MSR_INAK) != 0))
+			wait_ack++;
+		if ((CANx->MSR & CAN_MSR_INAK) != 0)
+			status = CAN_INIT_L_FAILED;
+	}
+	return status;
+}
+
+/**
+  * @brief  Deinitializes the CAN peripheral registers to their default reset values.
+  */
+CAN_STATUS can_deinit(CAN_Port* CANx)
+{
+	if (CANx == CAN1_BASE)
+	{
+		nvic_irq_disable(NVIC_USB_LP_CAN_RX0);	// Disable interrupts
+		nvic_irq_disable(NVIC_CAN_RX1);
+		nvic_irq_disable(NVIC_USB_HP_CAN_TX);
+		__asm volatile( "dsb" );						// Synchronization of the pipeline to guarantee
+		__asm volatile( "isb" );						// that the protection against interrupts is effective
+		rcc_reset_dev(RCC_CAN);
+		rcc_clk_disable(RCC_CAN);
+		can_active = 0;
+	}
+	return (status = CAN_OK);
+}
+
+/**
+  * @brief  Initialize CAN registers
+  */
+/*
+ *		Bits in control parameter:
+ *			CAN_MCR_TTCM	time triggered communication mode
+ *			CAN_MCR_ABOM	automatic bus-off management
+ *			CAN_MCR_AWUM	automatic wake-up mode
+ *			CAN_MCR_NART	no automatic retransmission
+ *			CAN_MCR_RFLM	receive FIFO locked mode
+ *			CAN_MCR_TXFP	transmit FIFO priority
+ */
+CAN_STATUS can_init(CAN_Port* CANx, uint32 control, uint8 speed)
+{
+	status = CAN_INIT_FAILED;			// default result status
+										// initialize receive message queue
+	can_rx_head = can_rx_tail = can_rx_lost = 0;
+
+	rcc_reset_dev(RCC_USB);			//! X893
+	rcc_clk_disable(RCC_USB);		//! X893
+	rcc_clk_enable(RCC_AFIO);			// enable clocks for AFIO
+	rcc_clk_enable(RCC_CAN);			// and CAN
+	rcc_reset_dev(RCC_CAN);				// reset CAN interface
+
+	can_active = 1;						// set CAN active flag (for interrupt handler
+
+	CANx->MCR &= ~CAN_MCR_SLEEP;		// reset CAN sleep mode (default after reset)
+
+	if (can_init_enter(CANx) != CAN_OK)	// enter CAN initialization mode
+		return status;					// error, so return
+
+	CANx->MCR &= ~CAN_CONTROL_MASK;		// set mode bits
+	CANx->MCR |= (control & CAN_CONTROL_MASK);
+
+	CANx->BTR &= ~CAN_TIMING_MASK;			// Set the bit timing register
+	CANx->BTR |= (can_speed_table[speed].btr & CAN_TIMING_MASK);
+
+	nvic_irq_enable(NVIC_USB_LP_CAN_RX0);	// Enable interrupts
+	nvic_irq_enable(NVIC_CAN_RX1);
+    
+	nvic_irq_enable(NVIC_USB_HP_CAN_TX);
+
+	CANx->IER = (CAN_IER_FMPIE0 | CAN_IER_FMPIE1 | CAN_IER_TMEIE);
+
+	if (can_init_leave(CANx) == CAN_OK)
+	{
+		while (!(CANx->TSR & CAN_TSR_TME0));	// Transmit mailbox 0 is empty
+		while (!(CANx->TSR & CAN_TSR_TME1));	// Transmit mailbox 0 is empty
+		while (!(CANx->TSR & CAN_TSR_TME2));	// Transmit mailbox 0 is empty
+	} 
+	return status;
+}
+
+/**
+  * @brief  Set timing calues (CAN_BTR)
+  */
+CAN_STATUS can_set_timing(CAN_Port* CANx, uint32 timing)
+{
+	if (can_init_enter(CANx) == CAN_OK)
+	{
+		CANx->BTR = ((CANx->BTR & ~CAN_TIMING_MASK) | (timing & CAN_TIMING_MASK));
+		can_init_leave(CANx);
+	}
+	return status;
+}
+
+/**
+  * @brief  Set CAN mode
+  * @param CANx pointer to CAN port
+  * @param mode CAN mode
+  */
+CAN_STATUS can_set_mode(CAN_Port* CANx, uint32 mode)
+{
+	if (can_init_enter(CANx) == CAN_OK)
+	{
+		CANx->BTR &= ~CAN_MODE_MASK;
+		CANx->BTR |= (mode & CAN_MODE_MASK);
+		can_init_leave(CANx);
+	}
+	return status;
+}
+
+/**
+  * @brief  Set CAN to GPIO mapping
+  */
+CAN_STATUS can_gpio_map(CAN_Port* CANx, CAN_GPIO_MAP map_mode)
+{
+	rcc_clk_enable(RCC_AFIO);
+
+	status = CAN_INIT_FAILED;
+	if( CANx == CAN1_BASE)
+	{
+		switch(map_mode)
+		{
+		case CAN_GPIO_PB8_PB9:
+			rcc_clk_enable(RCC_GPIOB);
+			afio_remap(AFIO_MAPR_CAN_REMAP_PB8_PB9);
+			gpio_set_mode(GPIOB, 8, GPIO_INPUT_FLOATING);
+			gpio_set_mode(GPIOB, 9, GPIO_AF_OUTPUT_PP);
+			break;
+		 case CAN_GPIO_PA11_PA12:
+			 rcc_clk_enable(RCC_GPIOA);
+			 afio_remap(AFIO_MAPR_CAN_REMAP_NONE);
+			 gpio_set_mode(GPIOA, 11, GPIO_INPUT_FLOATING);
+			 gpio_set_mode(GPIOA, 12, GPIO_AF_OUTPUT_PP);
+		 break;
+#if NR_GPIO_PORTS >= 4
+		case CAN_GPIO_PD0_PD1:
+			rcc_clk_enable(RCC_GPIOD);
+			afio_remap(AFIO_MAPR_CAN_REMAP_PD0_PD1);
+			gpio_set_mode(GPIOD, 0, GPIO_INPUT_FLOATING);
+			gpio_set_mode(GPIOD, 1, GPIO_AF_OUTPUT_PP);
+			break;
+#endif
+		default:
+			return status;
+		}
+		status = CAN_OK;
+	}
+	return status;
+}
+
+CAN_STATUS can_filter(CAN_Port* CANx, uint8 filter_idx, CAN_FIFO fifo, CAN_FILTER_SCALE scale, CAN_FILTER_MODE mode, uint32 fr1, uint32 fr2, int extID = 0)
+{
+	uint32 mask = ((uint32)0x00000001) << filter_idx;
+
+	CANx->FMR |= CAN_FMR_FINIT;		// Initialization mode for the filter
+	CANx->FA1R &= ~mask;			// Deactivation filter
+
+
+	if (scale == CAN_FILTER_32BIT)
+		CANx->FS1R |= mask;
+	else
+		CANx->FS1R &= ~mask;
+	if (extID) {
+		CANx->sFilterRegister[filter_idx].FR1 = (fr1 << 3) | CAN_ID_EXT;
+		CANx->sFilterRegister[filter_idx].FR2 = (fr2 << 3) | CAN_ID_EXT;	
+	}
+	else {
+		CANx->sFilterRegister[filter_idx].FR1 = (fr1 << 21);
+		CANx->sFilterRegister[filter_idx].FR2 = (fr2 << 21);	
+	}
+	if (mode == CAN_FILTER_MASK)
+		CANx->FM1R &= ~mask;
+	else
+		CANx->FM1R |= mask;
+
+	if (fifo == CAN_FIFO0)
+		CANx->FFA1R &= ~mask;
+	else
+		CANx->FFA1R |= mask;
+
+	CANx->FA1R |= mask;
+	CANx->FMR &= ~CAN_FMR_FINIT;
+	return CAN_OK;
+}
+
+
+/**
+  * @brief  Initiates the transmission of a message.
+  * @param	CANx: where x can be 1 to select the CAN peripheral.
+  * @param	msg: pointer to a structure which contains CAN Id, CAN DLC and CAN datas.
+  * @retval : The number of the mailbox that is used for transmission or CAN_NO_MB if there is no empty mailbox.
+  */
+CAN_TX_MBX can_transmit(CAN_Port* CANx, CanMsg* msg)
+{
+	CAN_TX_MBX mbx;
+	uint32 data;
+
+	/* Select one empty transmit mailbox */
+	if (CANx->TSR & CAN_TSR_TME0)
+		mbx = CAN_TX_MBX0;
+	else if (CANx->TSR & CAN_TSR_TME1)
+		mbx = CAN_TX_MBX1;
+	else if (CANx->TSR & CAN_TSR_TME2)
+		mbx = CAN_TX_MBX2;
+	else
+	{
+		status = CAN_NO_MB;
+		return CAN_TX_NO_MBX;
+	}
+
+    /* Set up the Id */
+    if (msg->IDE == CAN_ID_STD)
+		data = (msg->ID << 21);
+    else
+		data = (msg->ID << 3) | CAN_ID_EXT;
+
+	data |= ((uint32)msg->RTR);
+
+	/* Set up the DLC */
+    CANx->sTxMailBox[mbx].TDTR = (uint32)(msg->DLC & 0x0F);
+
+    /* Set up the data field */
+    CANx->sTxMailBox[mbx].TDLR = (
+		((uint32)msg->Data[3] << 24) | 
+		((uint32)msg->Data[2] << 16) |
+		((uint32)msg->Data[1] << 8) | 
+		((uint32)msg->Data[0])
+		);
+    CANx->sTxMailBox[mbx].TDHR = (
+		((uint32)msg->Data[7] << 24) |
+		((uint32)msg->Data[6] << 16) |
+		((uint32)msg->Data[5] << 8) |
+		((uint32)msg->Data[4])
+		);
+    /* Request transmission */
+    CANx->sTxMailBox[mbx].TIR = (data | CAN_TMIDxR_TXRQ);
+	status = CAN_OK;
+
+	return mbx;
+}
+
+/**
+  * Checks the transmission of a message.
+  * @param CANx: where x can be 1 to select the CAN peripheral.
+  * @param mbx: the number of the mailbox that is used for transmission.
+  * @retval : CAN_TX_OK if the CAN driver transmits the message, CAN_TX_FAILED in an other case.
+  */
+CAN_STATUS can_tx_status(CAN_Port* CANx, CAN_TX_MBX mbx)
+{
+	/* RQCP, TXOK and TME bits */
+	uint8 state = 0;
+
+	switch (mbx)
+	{
+	case CAN_TX_MBX0:
+		state |= (uint8)((CANx->TSR & CAN_TSR_RQCP0) << 2);
+		state |= (uint8)((CANx->TSR & CAN_TSR_TXOK0) >> 0);
+		state |= (uint8)((CANx->TSR & CAN_TSR_TME0) >> 26);
+		break;
+	case CAN_TX_MBX1:
+		state |= (uint8)((CANx->TSR & CAN_TSR_RQCP1) >> 6);
+		state |= (uint8)((CANx->TSR & CAN_TSR_TXOK1) >> 8);
+		state |= (uint8)((CANx->TSR & CAN_TSR_TME1) >> 27);
+		break;
+	case CAN_TX_MBX2:
+		state |= (uint8)((CANx->TSR & CAN_TSR_RQCP2) >> 14);
+		state |= (uint8)((CANx->TSR & CAN_TSR_TXOK2) >> 16);
+		state |= (uint8)((CANx->TSR & CAN_TSR_TME2) >> 28);
+		break;
+	default:
+		status = CAN_TX_FAILED;
+		return status;
+	}
+
+	// state = RQCP TXOK TME
+	switch (state)
+	{
+	/* transmit pending  */
+	case 0x0:
+		status = CAN_TX_PENDING;
+		break;
+	/* transmit failed  */
+	case 0x5:
+		status = CAN_TX_FAILED;
+		break;
+	/* transmit succedeed  */
+	case 0x7:
+		status = CAN_OK;
+		break;
+	default:
+		status = CAN_TX_FAILED;
+		break;
+	}
+	return status;
+}
+
+/**
+  * @brief  Cancels a transmit request.
+  * @param CANx: where x can be 1 to select the CAN peripheral.
+  * @param mbx: Mailbox number.
+  * @retval : None.
+  */
+void can_cancel(CAN_Port* CANx, uint8 mbx)
+{
+	/* abort transmission */
+	switch (mbx)
+	{
+	case 0:
+		CANx->TSR |= CAN_TSR_ABRQ0;
+		break;
+	case 1:
+		CANx->TSR |= CAN_TSR_ABRQ1;
+		break;
+	case 2:
+		CANx->TSR |= CAN_TSR_ABRQ2;
+		break;
+	default:
+		break;
+	}
+}
+
+void can_rx_queue_clear(void)
+{
+	nvic_irq_disable(NVIC_USB_LP_CAN_RX0);
+	nvic_irq_disable(NVIC_CAN_RX1);
+	__asm volatile( "dsb" );						// Synchronization of the pipeline to guarantee
+	__asm volatile( "isb" );						// that the protection against interrupts is effective
+	can_rx_head = can_rx_tail = can_rx_lost = 0;					// JMD 2017/07/18
+	nvic_irq_enable(NVIC_USB_LP_CAN_RX0);
+	nvic_irq_enable(NVIC_CAN_RX1);
+}
+
+// JMD 2017/07/18 -- changed
+uint8 can_rx_available(void)
+{
+	if ( can_rx_head >= can_rx_tail )
+		return can_rx_head - can_rx_tail ;
+	else
+		return CAN_RX_QUEUE_SIZE - ( can_rx_tail - can_rx_head ) ;
+}
+
+// JMD 2017/07/18 -- added
+uint8 can_frame_lost(void)
+{
+	if ( can_rx_lost != 0 )
+	{
+		can_rx_lost = 0 ;
+		return 1 ;
+	}
+	return 0 ;
+	
+}
+
+CanMsg* can_rx_queue_get(void)
+{
+	if (can_rx_head == can_rx_tail)			// JMD 2017/07/18 -- changed
+		return NULL;
+	return &(can_rx_queue[can_rx_tail]);
+}
+
+
+void can_rx_queue_free(void)
+{
+	if (can_rx_head != can_rx_tail)			// JMD 2017/07/18 -- changed
+	{
+		nvic_irq_disable(NVIC_USB_LP_CAN_RX0);			// JMD atomicity problem
+		nvic_irq_disable(NVIC_CAN_RX1);
+		__asm volatile( "dsb" );						// Synchronization of the pipeline to guarantee
+		__asm volatile( "isb" );						// that the protection against interrupts is effective
+		can_rx_tail = (can_rx_tail == (CAN_RX_QUEUE_SIZE - 1)) ? 0 : (can_rx_tail + 1);
+		nvic_irq_enable(NVIC_USB_LP_CAN_RX0);			// fin JMD problème d'atomicité
+		nvic_irq_enable(NVIC_CAN_RX1);
+	}
+}
+
+CanMsg* can_read(CAN_Port* CANx, CAN_FIFO fifo, CanMsg* msg)
+{
+	uint32 data = CANx->sFIFOMailBox[fifo].RIR;
+
+	/* Get the Id */
+	if (data & CAN_ID_EXT)
+	{
+		msg->ID = 0x1FFFFFFF & (data >> 3);
+		msg->IDE = (uint8)CAN_ID_EXT;
+	}
+	else
+	{
+		msg->ID = 0x000007FF & (data >> 21);
+		msg->IDE = (uint8)CAN_ID_STD;
+	}
+
+	msg->RTR = (uint8)(CAN_RTR_REMOTE & data);
+	msg->DLC = (uint8)(0x0F & CANx->sFIFOMailBox[fifo].RDTR);
+	msg->FMI = (uint8)(0xFF & (CANx->sFIFOMailBox[fifo].RDTR >> 8));
+
+	/* Get the data field */
+	data = CANx->sFIFOMailBox[fifo].RDLR;
+	uint8* p = msg->Data;
+	*p++ = (uint8)0xFF & data;
+	*p++ = (uint8)0xFF & (data >> 8);
+	*p++ = (uint8)0xFF & (data >> 16);
+	*p++ = (uint8)0xFF & (data >> 24);
+
+	data = CANx->sFIFOMailBox[fifo].RDHR;
+	*p++ = (uint8)0xFF & data;
+	*p++ = (uint8)0xFF & (data >> 8);
+	*p++ = (uint8)0xFF & (data >> 16);
+	*p++ = (uint8)0xFF & (data >> 24);
+
+	return msg;
+}
+
+void can_rx_release(CAN_Port* CANx, CAN_FIFO fifo)
+{
+	if (fifo == CAN_FIFO0)
+		CANx->RF0R |= (CAN_RF0R_RFOM0);	// Release FIFO0
+	else
+		CANx->RF1R |= (CAN_RF1R_RFOM1);	// Release FIFO1
+}
+
+void can_rx_read(CAN_Port* CANx, CAN_FIFO fifo)
+{
+	if (can_rx_available() < CAN_RX_QUEUE_SIZE)		// read the message
+	{
+		CanMsg* msg = &can_rx_queue[can_rx_head];
+		can_read(CANx, fifo, msg);
+		can_rx_head = (can_rx_head == (CAN_RX_QUEUE_SIZE - 1)) ? 0 : (can_rx_head + 1);
+	}
+	else
+		can_rx_lost = 1;						// no place in queue, ignore package
+
+	can_rx_release(CANx, fifo);
+}
+
+uint8 CAN_RX0_IRQ_Handler(void)
+{
+	if (can_active)
+	{
+		while ((CAN1_BASE->RF0R & CAN_RF0R_FMP0) != 0)
+			can_rx_read(CAN1_BASE, CAN_FIFO0);		// message pending FIFO0
+		while ((CAN1_BASE->RF1R & CAN_RF1R_FMP1) != 0)
+			can_rx_read(CAN1_BASE, CAN_FIFO1);		// message pending FIFO1
+	}
+	return can_active;								// return CAN active flag to USB handler
+}
+
+// Addition JMD: the messages stored in fifo1 must also trigger an interrupt.
+void __irq_can_rx1(void)
+{
+	CAN_RX0_IRQ_Handler() ;
+}
+
+void USB_HP_CAN_TX_IRQHandler (void)
+{
+	if (can_active)
+	{
+		if (CAN1_BASE->TSR & CAN_TSR_RQCP0)
+			CAN1_BASE->TSR |= CAN_TSR_RQCP0;		// reset request complete mbx 0
+		if (CAN1_BASE->TSR & CAN_TSR_RQCP1)
+			CAN1_BASE->TSR |= CAN_TSR_RQCP1;		// reset request complete mbx 1
+		if (CAN1_BASE->TSR & CAN_TSR_RQCP2)
+			CAN1_BASE->TSR |= CAN_TSR_RQCP2;		// reset request complete mbx 2
+	}
+}

From 0ade473ecee8489d5634f5d3b2a6f96b1a9dee3f Mon Sep 17 00:00:00 2001
From: megadrifter <megadrifter@gmail.com>
Date: Fri, 13 Oct 2017 14:11:25 +0300
Subject: [PATCH 306/307] latest files from Phonog

---
 STM32F1/libraries/HardwareCAN/src/HardwareCAN.cpp | 5 +++++
 STM32F1/libraries/HardwareCAN/src/HardwareCAN.h   | 1 +
 2 files changed, 6 insertions(+)

diff --git a/STM32F1/libraries/HardwareCAN/src/HardwareCAN.cpp b/STM32F1/libraries/HardwareCAN/src/HardwareCAN.cpp
index f324e865f..8a9933215 100644
--- a/STM32F1/libraries/HardwareCAN/src/HardwareCAN.cpp
+++ b/STM32F1/libraries/HardwareCAN/src/HardwareCAN.cpp
@@ -59,6 +59,11 @@ uint8 HardwareCAN::available(void)
 	return can_rx_available();
 }
 
+uint8 HardwareCAN::frame_lost(void)
+{
+	return can_frame_lost() ;
+}
+
 CanMsg* HardwareCAN::recv(void)
 {
 	return can_rx_queue_get();
diff --git a/STM32F1/libraries/HardwareCAN/src/HardwareCAN.h b/STM32F1/libraries/HardwareCAN/src/HardwareCAN.h
index ccc318f5b..944187e14 100644
--- a/STM32F1/libraries/HardwareCAN/src/HardwareCAN.h
+++ b/STM32F1/libraries/HardwareCAN/src/HardwareCAN.h
@@ -54,6 +54,7 @@ class HardwareCAN
 	void cancel(CAN_TX_MBX mbx);
 
 	uint8 available(void);
+	uint8 frame_lost(void);
 
 	CanMsg* recv(void);
 

From 0c050b8c57bd75e0d9cfa4a0bf385df23e183af5 Mon Sep 17 00:00:00 2001
From: Lacklustrlabs <lacklustrlabs@gmail.com>
Date: Sat, 27 Jan 2018 17:20:14 +0100
Subject: [PATCH 307/307] Post rebase fixup

---
 STM32F1/cores/maple/HardwareTimer.h           |   1 +
 .../AstraH_CAN_test/AstraH_CAN_test.ino       |   7 +-
 .../HardwareCAN_simplified_send1.ino          |   7 +-
 .../examples/HardwareCANexample/Changes.h     |   2 +-
 .../HardwareCANexample/HardwareCANexample.ino |  11 +-
 .../examples/STMdualCAN/STMdualCAN.ino        |   4 +
 .../libraries/HardwareCAN/library.properties  |   3 +-
 .../libraries/HardwareCAN/src/HardwareCAN.cpp |   4 +-
 .../libraries/HardwareCAN/src/HardwareCAN.h   |  12 +-
 .../libraries/HardwareCAN/src/utility/can.c   |   6 +-
 .../HardwareCAN/src/utility/can.c.txt         | 591 ----------------
 .../libraries/HardwareCAN/src/utility/can.h   |   3 +-
 .../HardwareCAN/src/utility/can.temp.c        | 599 ----------------
 STM32F1/libraries/rcc.h                       | 641 ------------------
 STM32F1/libraries/rcc_f1.c                    | 174 -----
 STM32F1/libraries/usb.c                       | 402 -----------
 16 files changed, 36 insertions(+), 2431 deletions(-)
 delete mode 100644 STM32F1/libraries/HardwareCAN/src/utility/can.c.txt
 delete mode 100644 STM32F1/libraries/HardwareCAN/src/utility/can.temp.c
 delete mode 100644 STM32F1/libraries/rcc.h
 delete mode 100644 STM32F1/libraries/rcc_f1.c
 delete mode 100644 STM32F1/libraries/usb.c

diff --git a/STM32F1/cores/maple/HardwareTimer.h b/STM32F1/cores/maple/HardwareTimer.h
index 4de2ebc07..5be5ee7a3 100644
--- a/STM32F1/cores/maple/HardwareTimer.h
+++ b/STM32F1/cores/maple/HardwareTimer.h
@@ -143,6 +143,7 @@ class HardwareTimer {
      * @return The new overflow value.
      */
     uint16 setCycles(uint32 Cycles);
+
     /**
      * @brief Set the timer's period in microseconds.
      *
diff --git a/STM32F1/libraries/HardwareCAN/examples/AstraH_CAN_test/AstraH_CAN_test.ino b/STM32F1/libraries/HardwareCAN/examples/AstraH_CAN_test/AstraH_CAN_test.ino
index a05576bb9..ff7c55bb4 100644
--- a/STM32F1/libraries/HardwareCAN/examples/AstraH_CAN_test/AstraH_CAN_test.ino
+++ b/STM32F1/libraries/HardwareCAN/examples/AstraH_CAN_test/AstraH_CAN_test.ino
@@ -23,8 +23,9 @@ void CANSetup(void)
                                       // will be performed at ease in a task or in the loop. The software fifo is 16 cells long, 
                                       // allowing at least 15 ms before processing the fifo is needed at 125 kbps
   Stat = canBus.status();
-  if (Stat != CAN_OK)
+  if (Stat != CAN_OK) {
      /* Your own error processing here */ ;   // Initialization failed
+  }
 }
 
 
@@ -79,6 +80,10 @@ int sState = 0;         // variable for reading the switch status
 byte st = 0x31; // buttot 1 on the CD30MP3
 
 void setup() {
+#ifdef SERIAL_USB
+  Serial.end(); // Disable USB !!!
+#endif
+	
   // put your setup code here, to run once:
   CANSetup() ;        // Initialize the CAN module and prepare the message structures.
   pinMode(PC13, OUTPUT);
diff --git a/STM32F1/libraries/HardwareCAN/examples/HardwareCAN_simplified_send1/HardwareCAN_simplified_send1.ino b/STM32F1/libraries/HardwareCAN/examples/HardwareCAN_simplified_send1/HardwareCAN_simplified_send1.ino
index 17fb07f9b..e20fd80d7 100644
--- a/STM32F1/libraries/HardwareCAN/examples/HardwareCAN_simplified_send1/HardwareCAN_simplified_send1.ino
+++ b/STM32F1/libraries/HardwareCAN/examples/HardwareCAN_simplified_send1/HardwareCAN_simplified_send1.ino
@@ -27,8 +27,9 @@ void CANSetup(void)
                                       // will be performed at ease in a task or in the loop. The software fifo is 16 cells long, 
                                       // allowing at least 15 ms before processing the fifo is needed at 125 kbps
   Stat = canBus.status();
-  if (Stat != CAN_OK)
+  if (Stat != CAN_OK) {
      /* Your own error processing here */ ;   // Initialization failed
+  }
 }
 
 
@@ -79,6 +80,10 @@ void SendCANmessage(long id=0x001, byte d0=0x00, byte d1=0x00, byte d2=0x00, byt
 
 // The application program starts here
 void setup() {
+#ifdef SERIAL_USB
+  Serial.end(); // Disable USB !!!
+#endif
+  
   // put your setup code here, to run once:
   CANSetup() ;        // Initialize the CAN module and prepare the message structures.
   pinMode(PC13, OUTPUT);
diff --git a/STM32F1/libraries/HardwareCAN/examples/HardwareCANexample/Changes.h b/STM32F1/libraries/HardwareCAN/examples/HardwareCANexample/Changes.h
index 1ccd2fe88..207704784 100644
--- a/STM32F1/libraries/HardwareCAN/examples/HardwareCANexample/Changes.h
+++ b/STM32F1/libraries/HardwareCAN/examples/HardwareCANexample/Changes.h
@@ -31,7 +31,7 @@ void __irq_usb_hp_can_tx(void)
 }
 
 uint8 __attribute__((weak)) CAN_RX0_IRQ_Handler(void)
-{ return 1 ; }      // Dummy ISR 
+{ return 0 ; }      // Dummy ISR 
 
 2.3.2) and altered function void __irq_usb_lp_can_rx0(void)
  Was
diff --git a/STM32F1/libraries/HardwareCAN/examples/HardwareCANexample/HardwareCANexample.ino b/STM32F1/libraries/HardwareCAN/examples/HardwareCANexample/HardwareCANexample.ino
index 4e3a9e574..0c0a8ecec 100644
--- a/STM32F1/libraries/HardwareCAN/examples/HardwareCANexample/HardwareCANexample.ino
+++ b/STM32F1/libraries/HardwareCAN/examples/HardwareCANexample/HardwareCANexample.ino
@@ -1,5 +1,5 @@
 #include <HardwareCAN.h>
-#include "changes.h"
+#include "Changes.h"
 /*
  * Example of use of the HardwareCAN library
  * This application receives two frames containing various data. It also produces data that are sent periodically using another two frames.
@@ -70,8 +70,9 @@ void CANSetup(void)
                                       // will be performed at ease in a task or in the loop. The software fifo is 16 cells long, 
                                       // allowing at least 15 ms before processing the fifo is needed at 125 kbps
   Stat = canBus.status();
-  if (Stat != CAN_OK)
+  if (Stat != CAN_OK) {
      /* Your own error processing here */ ;   // Initialization failed
+  }
 }
 
 // Send one frame. Parameter is a pointer to a frame structure (above), that has previously been updated with data.
@@ -151,6 +152,10 @@ void SendCANmessages(void)
 
 // The application program starts here
 void setup() {
+#ifdef SERIAL_USB
+  Serial.end(); // Disable USB !!!
+#endif
+  
   // put your setup code here, to run once:
   CANSetup() ;        // Initialize the CAN module and prepare the message structures.
 }
@@ -178,4 +183,4 @@ void loop() {
   delay(CAN_DELAY) ;    // The delay must not be greater than the time to overflow the incoming fifo (here about 15 ms)
 }
 
-
+
diff --git a/STM32F1/libraries/HardwareCAN/examples/STMdualCAN/STMdualCAN.ino b/STM32F1/libraries/HardwareCAN/examples/STMdualCAN/STMdualCAN.ino
index cbeaf8962..c120395e0 100644
--- a/STM32F1/libraries/HardwareCAN/examples/STMdualCAN/STMdualCAN.ino
+++ b/STM32F1/libraries/HardwareCAN/examples/STMdualCAN/STMdualCAN.ino
@@ -87,6 +87,10 @@ void SendCANmessage(long id=0x001, byte dlength=8, byte d0=0x00, byte d1=0x00, b
 // The application program starts here
 byte msgD0 = 0x00;
 void setup() {        // Initialize the CAN module and prepare the message structures.
+#ifdef SERIAL_USB
+  Serial.end(); // Disable USB !!!
+#endif
+  
   pinMode(PC13, OUTPUT);
   digitalWrite(PC13, HIGH);
   delay(10);
diff --git a/STM32F1/libraries/HardwareCAN/library.properties b/STM32F1/libraries/HardwareCAN/library.properties
index 9186eb6cc..3623c3daa 100644
--- a/STM32F1/libraries/HardwareCAN/library.properties
+++ b/STM32F1/libraries/HardwareCAN/library.properties
@@ -6,4 +6,5 @@ sentence=Enables managing CAN communication using the built-in CAN port of the O
 paragraph=With this library you can use the built-in CAN port of the OLIMEX STM32. The library handles both standard and extended frames.
 category=Communication
 url=
-architectures=*
\ No newline at end of file
+includes=src/HardwareCAN.h
+architectures=STM32F1
diff --git a/STM32F1/libraries/HardwareCAN/src/HardwareCAN.cpp b/STM32F1/libraries/HardwareCAN/src/HardwareCAN.cpp
index 8a9933215..010008acd 100644
--- a/STM32F1/libraries/HardwareCAN/src/HardwareCAN.cpp
+++ b/STM32F1/libraries/HardwareCAN/src/HardwareCAN.cpp
@@ -39,9 +39,9 @@ void HardwareCAN::set_irq_mode(void)
 	return can_set_irq_mode(Port);
 }
 
-CAN_STATUS HardwareCAN::filter(uint8 idx, uint32 id, uint32 mask)
+CAN_STATUS HardwareCAN::filter(uint8 idx, uint32 id, uint32 mask, int ext_id)
 {
-	return can_filter(Port, idx, CAN_FIFO0, CAN_FILTER_32BIT, CAN_FILTER_MASK, id, mask);
+	return can_filter(Port, idx, CAN_FIFO0, CAN_FILTER_32BIT, CAN_FILTER_MASK, id, mask, ext_id);
 }
 
 CAN_STATUS HardwareCAN::status(void)
diff --git a/STM32F1/libraries/HardwareCAN/src/HardwareCAN.h b/STM32F1/libraries/HardwareCAN/src/HardwareCAN.h
index 944187e14..c8a10e8fb 100644
--- a/STM32F1/libraries/HardwareCAN/src/HardwareCAN.h
+++ b/STM32F1/libraries/HardwareCAN/src/HardwareCAN.h
@@ -8,16 +8,6 @@
 #include "utility/can.h"
 #include "usb_serial.h"
 
-#define PID_REQUEST		0x7DF
-#define PID_REPLY		0x7E8
-
-#define ENGINE_COOLANT_TEMP	0x05
-#define ENGINE_RPM			0x0C
-#define VEHICLE_SPEED		0x0D
-#define MAF_SENSOR			0x10
-#define O2_VOLTAGE			0x14
-#define THROTTLE			0x11
-
 /**
  * Defines the possible SPI communication speeds.
  */
@@ -46,7 +36,7 @@ class HardwareCAN
     CAN_STATUS begin(CAN_SPEED speed, uint32 mode);
 	void end(void);
 
-	CAN_STATUS filter(uint8 idx, uint32 id, uint32 mask);
+	CAN_STATUS filter(uint8 idx, uint32 id, uint32 mask, int ext_id = 0);
 	CAN_STATUS map(CAN_GPIO_MAP remap);
 	CAN_STATUS status(void);
 
diff --git a/STM32F1/libraries/HardwareCAN/src/utility/can.c b/STM32F1/libraries/HardwareCAN/src/utility/can.c
index 324800804..862685fc9 100644
--- a/STM32F1/libraries/HardwareCAN/src/utility/can.c
+++ b/STM32F1/libraries/HardwareCAN/src/utility/can.c
@@ -277,7 +277,7 @@ CAN_STATUS can_gpio_map(CAN_Port* CANx, CAN_GPIO_MAP map_mode)
 	return status;
 }
 
-CAN_STATUS can_filter(CAN_Port* CANx, uint8 filter_idx, CAN_FIFO fifo, CAN_FILTER_SCALE scale, CAN_FILTER_MODE mode, uint32 fr1, uint32 fr2, int extID = 0)
+CAN_STATUS can_filter(CAN_Port* CANx, uint8 filter_idx, CAN_FIFO fifo, CAN_FILTER_SCALE scale, CAN_FILTER_MODE mode, uint32 fr1, uint32 fr2, int extID)
 {
 	uint32 mask = ((uint32)0x00000001) << filter_idx;
 
@@ -561,7 +561,7 @@ void can_rx_read(CAN_Port* CANx, CAN_FIFO fifo)
 	can_rx_release(CANx, fifo);
 }
 
-uint8 CAN_RX0_IRQ_Handler(void)
+uint8 __attribute__ ((interrupt)) CAN_RX0_IRQ_Handler(void)
 {
 	if (can_active)
 	{
@@ -579,7 +579,7 @@ void __irq_can_rx1(void)
 	CAN_RX0_IRQ_Handler() ;
 }
 
-void USB_HP_CAN_TX_IRQHandler (void)
+void __attribute__ ((interrupt)) USB_HP_CAN_TX_IRQHandler(void)
 {
 	if (can_active)
 	{
diff --git a/STM32F1/libraries/HardwareCAN/src/utility/can.c.txt b/STM32F1/libraries/HardwareCAN/src/utility/can.c.txt
deleted file mode 100644
index 64cedac5e..000000000
--- a/STM32F1/libraries/HardwareCAN/src/utility/can.c.txt
+++ /dev/null
@@ -1,591 +0,0 @@
-//#include "libmaple.h"
-#include "can.h"
-//#include "rcc.h"
-//#include "gpio.h"
-//#include "nvic.h"
-//#include "usb.h"
-
-/**
-  *	CAN_interrupts
-  */
-
-#define CAN_IT_RQCP0	((uint32)0x00000005) /* Request completed mailbox 0 */
-#define CAN_IT_RQCP1	((uint32)0x00000006) /* Request completed mailbox 1 */
-#define CAN_IT_RQCP2	((uint32)0x00000007) /* Request completed mailbox 2 */
-#define CAN_IT_TME		((uint32)0x00000001) /* Transmit mailbox empty */
-#define CAN_IT_FMP0		((uint32)0x00000002) /* FIFO 0 message pending */
-#define CAN_IT_FF0		((uint32)0x00000004) /* FIFO 0 full */
-#define CAN_IT_FOV0		((uint32)0x00000008) /* FIFO 0 overrun */
-#define CAN_IT_FMP1		((uint32)0x00000010) /* FIFO 1 message pending */
-#define CAN_IT_FF1		((uint32)0x00000020) /* FIFO 1 full */
-#define CAN_IT_FOV1		((uint32)0x00000040) /* FIFO 1 overrun */
-#define CAN_IT_EWG		((uint32)0x00000100) /* Error warning */
-#define CAN_IT_EPV		((uint32)0x00000200) /* Error passive */
-#define CAN_IT_BOF		((uint32)0x00000400) /* Bus-off */
-#define CAN_IT_LEC		((uint32)0x00000800) /* Last error code */
-#define CAN_IT_ERR		((uint32)0x00008000) /* Error */
-#define CAN_IT_WKU		((uint32)0x00010000) /* Wake-up */
-#define CAN_IT_SLK		((uint32)0x00020000) /* Sleep */
-
-/* Time out for INAK bit */
-#define CAN_INAK_TimeOut	((uint32)0x0000FFFF)
-
-/* Time out for SLAK bit */
-#define CAN_SLAK_TimeOut	((uint32)0x0000FFFF)
-
-#define CAN_CONTROL_MASK	(CAN_MCR_TTCM | CAN_MCR_ABOM | CAN_MCR_AWUM | CAN_MCR_NART | CAN_MCR_RFLM | CAN_MCR_TXFP)
-#define CAN_TIMING_MASK		(CAN_BTR_SJW | CAN_BTR_TS2 | CAN_BTR_TS1 | CAN_BTR_BRP)
-#define CAN_MODE_MASK		(CAN_BTR_LBKM | CAN_BTR_SILM)
-
-struct can_speed_info {
-    const uint32 btr;
-};
-
-#define CAN_CLOCK	(36000000UL / 18UL)
-
-static const struct can_speed_info can_speed_table[] = {
-	[CAN_SPEED_125]		= { .btr = (
-		(( 4-1) << CAN_BTR_SJW_POS) |
-		((12-1) << CAN_BTR_TS1_POS) |
-		(( 5-1) << CAN_BTR_TS2_POS) |
-		(CAN_CLOCK / 125000UL - 1)
-		)},
-	[CAN_SPEED_250]		= { .btr = (
-		(( 4-1) << CAN_BTR_SJW_POS) |
-		((12-1) << CAN_BTR_TS1_POS) |
-		(( 5-1) << CAN_BTR_TS2_POS) |
-		(CAN_CLOCK / 250000UL - 1)
-		)},
-	[CAN_SPEED_500]		= { .btr = (
-		(( 4-1) << CAN_BTR_SJW_POS) |
-		((12-1) << CAN_BTR_TS1_POS) |
-		(( 5-1) << CAN_BTR_TS2_POS) |
-		(CAN_CLOCK / 500000UL - 1)
-		)},
-	[CAN_SPEED_1000]	= { .btr = (
-		(( 4-1) << CAN_BTR_SJW_POS) |
-		((12-1) << CAN_BTR_TS1_POS) |
-		(( 5-1) << CAN_BTR_TS2_POS) |
-		(CAN_CLOCK / 1000000UL - 1)
-		)}
-};
-
-CAN_STATUS status;
-CanMsg can_rx_queue[CAN_RX_QUEUE_SIZE];
-
-// JMD 2017/07/18 -- added volatile to fix queue problems 
-volatile uint8 can_rx_head;
-volatile uint8 can_rx_tail;
-//volatile uint8 can_rx_count;		// JMD 2017/07/18 -- redundant
-volatile uint8 can_rx_lost;
-uint8 can_active = 0;
-
-/**
-  * @brief  Return last operation status
-  */
-CAN_STATUS can_status(void)
-{
-	return status;
-}
-
-/**
-  * @brief  Enter initialization mode
-  */
-CAN_STATUS can_init_enter(CAN_Port* CANx)
-{
-	volatile uint32 wait_ack = 0 ;
-    
-	status = CAN_OK;
-	if ((CANx->MSR & CAN_MSR_INAK) == 0)	// Check for initialization mode already set
-	{
-		CANx->MCR |= CAN_MCR_INRQ;			// Request initialisation
-
-		wait_ack = 0;						// Wait the acknowledge
-		while ((wait_ack != CAN_INAK_TimeOut) && ((CANx->MSR & CAN_MSR_INAK) == 0))
-			wait_ack++;
-		if ((CANx->MSR & CAN_MSR_INAK) == 0)
-			status = CAN_INIT_E_FAILED;		// Timeout
-	}
-	return status;
-}
-
-/**
-  * @brief  Leave initialization mode
-  */
-CAN_STATUS can_init_leave(CAN_Port* CANx)
-{
-	volatile uint32 wait_ack = 0 ;
-
-	status = CAN_OK;
-	if ((CANx->MSR & CAN_MSR_INAK) != 0)	// Check for initialization mode already reset
-	{
-		CANx->MCR &= ~CAN_MCR_INRQ;			// Clear Request initialization
-
-		wait_ack = 0;						// Wait the acknowledge
-		while ((wait_ack != CAN_INAK_TimeOut) && ((CANx->MSR & CAN_MSR_INAK) != 0))
-			wait_ack++;
-		if ((CANx->MSR & CAN_MSR_INAK) != 0)
-			status = CAN_INIT_L_FAILED;
-	}
-	return status;
-}
-
-/**
-  * @brief  Deinitializes the CAN peripheral registers to their default reset values.
-  */
-CAN_STATUS can_deinit(CAN_Port* CANx)
-{
-	if (CANx == CAN1_BASE)
-	{
-		nvic_irq_disable(NVIC_USB_LP_CAN_RX0);	// Disable interrupts
-		nvic_irq_disable(NVIC_CAN_RX1);
-		nvic_irq_disable(NVIC_USB_HP_CAN_TX);
-		__asm volatile( "dsb" );						// Synchronization of the pipeline to guarantee
-		__asm volatile( "isb" );						// that the protection against interrupts is effective
-		rcc_reset_dev(RCC_CAN);
-		rcc_clk_disable(RCC_CAN);
-		can_active = 0;
-	}
-	return (status = CAN_OK);
-}
-
-/**
-  * @brief  Initialize CAN registers
-  */
-/*
- *		Bits in control parameter:
- *			CAN_MCR_TTCM	time triggered communication mode
- *			CAN_MCR_ABOM	automatic bus-off management
- *			CAN_MCR_AWUM	automatic wake-up mode
- *			CAN_MCR_NART	no automatic retransmission
- *			CAN_MCR_RFLM	receive FIFO locked mode
- *			CAN_MCR_TXFP	transmit FIFO priority
- */
-CAN_STATUS can_init(CAN_Port* CANx, uint32 control, uint8 speed)
-{
-	status = CAN_INIT_FAILED;			// default result status
-										// initialize receive message queue
-//	can_rx_head = can_rx_tail = can_rx_count = can_rx_lost = 0;		// JMD 2017/07/18
-	can_rx_head = can_rx_tail = can_rx_lost = 0;
-
-	rcc_reset_dev(RCC_USB);			//! X893
-	rcc_clk_disable(RCC_USB);		//! X893
-//	line_dtr_rts = 0;				//! X893
-	rcc_clk_enable(RCC_AFIO);			// enable clocks for AFIO
-	rcc_clk_enable(RCC_CAN);			// and CAN
-	rcc_reset_dev(RCC_CAN);				// reset CAN interface
-
-	can_active = 1;						// set CAN active flag (for interrupt handler
-
-	CANx->MCR &= ~CAN_MCR_SLEEP;		// reset CAN sleep mode (default after reset)
-
-	if (can_init_enter(CANx) != CAN_OK)	// enter CAN initialization mode
-		return status;					// error, so return
-
-	CANx->MCR &= ~CAN_CONTROL_MASK;		// set mode bits
-	CANx->MCR |= (control & CAN_CONTROL_MASK);
-
-	CANx->BTR &= ~CAN_TIMING_MASK;			// Set the bit timing register
-	CANx->BTR |= (can_speed_table[speed].btr & CAN_TIMING_MASK);
-
-	nvic_irq_enable(NVIC_USB_LP_CAN_RX0);	// Enable interrupts
-	nvic_irq_enable(NVIC_CAN_RX1);
-    
-	nvic_irq_enable(NVIC_USB_HP_CAN_TX);
-
-	CANx->IER = (CAN_IER_FMPIE0 | CAN_IER_FMPIE1 | CAN_IER_TMEIE);
-
-	if (can_init_leave(CANx) == CAN_OK)
-	{
-		while (!(CANx->TSR & CAN_TSR_TME0));	// Transmit mailbox 0 is empty
-		while (!(CANx->TSR & CAN_TSR_TME1));	// Transmit mailbox 0 is empty
-		while (!(CANx->TSR & CAN_TSR_TME2));	// Transmit mailbox 0 is empty
-	} 
-	return status;
-}
-
-/**
-  * @brief  Set timing calues (CAN_BTR)
-  */
-CAN_STATUS can_set_timing(CAN_Port* CANx, uint32 timing)
-{
-	if (can_init_enter(CANx) == CAN_OK)
-	{
-		CANx->BTR = ((CANx->BTR & ~CAN_TIMING_MASK) | (timing & CAN_TIMING_MASK));
-		can_init_leave(CANx);
-	}
-	return status;
-}
-
-/**
-  * @brief  Set CAN mode
-  * @param CANx pointer to CAN port
-  * @param mode CAN mode
-  */
-CAN_STATUS can_set_mode(CAN_Port* CANx, uint32 mode)
-{
-	if (can_init_enter(CANx) == CAN_OK)
-	{
-		CANx->BTR &= ~CAN_MODE_MASK;
-		CANx->BTR |= (mode & CAN_MODE_MASK);
-		can_init_leave(CANx);
-	}
-	return status;
-}
-
-/**
-  * @brief  Set CAN to GPIO mapping
-  */
-CAN_STATUS can_gpio_map(CAN_Port* CANx, CAN_GPIO_MAP map_mode)
-{
-	rcc_clk_enable(RCC_AFIO);
-
-	status = CAN_INIT_FAILED;
-	if( CANx == CAN1_BASE)
-	{
-		switch(map_mode)
-		{
-		case CAN_GPIO_PB8_PB9:
-			rcc_clk_enable(RCC_GPIOB);
-			afio_remap(AFIO_MAPR_CAN_REMAP_PB8_PB9);
-			gpio_set_mode(GPIOB, 8, GPIO_INPUT_FLOATING);
-			gpio_set_mode(GPIOB, 9, GPIO_AF_OUTPUT_PP);
-			break;
-#if NR_GPIO_PORTS >= 4
-		case CAN_GPIO_PD0_PD1:
-			rcc_clk_enable(RCC_GPIOD);
-			afio_remap(AFIO_MAPR_CAN_REMAP_PD0_PD1);
-			gpio_set_mode(GPIOD, 0, GPIO_INPUT_FLOATING);
-			gpio_set_mode(GPIOD, 1, GPIO_AF_OUTPUT_PP);
-			break;
-#endif
-		default:
-			return status;
-		}
-		status = CAN_OK;
-	}
-	return status;
-}
-
-CAN_STATUS can_filter(CAN_Port* CANx, uint8 filter_idx, CAN_FIFO fifo, CAN_FILTER_SCALE scale, CAN_FILTER_MODE mode, uint32 fr1, uint32 fr2)
-{
-	uint32 mask = ((uint32)0x00000001) << filter_idx;
-
-	CANx->FMR |= CAN_FMR_FINIT;		// Initialization mode for the filter
-	CANx->FA1R &= ~mask;			// Deactivation filter
-
-
-	if (scale == CAN_FILTER_32BIT)
-		CANx->FS1R |= mask;
-	else
-		CANx->FS1R &= ~mask;
-
-	CANx->sFilterRegister[filter_idx].FR1 = fr1;
-	CANx->sFilterRegister[filter_idx].FR2 = fr2;
-
-	if (mode == CAN_FILTER_MASK)
-		CANx->FM1R &= ~mask;
-	else
-		CANx->FM1R |= mask;
-
-	if (fifo == CAN_FIFO0)
-		CANx->FFA1R &= ~mask;
-	else
-		CANx->FFA1R |= mask;
-
-	CANx->FA1R |= mask;
-	CANx->FMR &= ~CAN_FMR_FINIT;
-	return CAN_OK;
-}
-
-
-/**
-  * @brief  Initiates the transmission of a message.
-  * @param	CANx: where x can be 1 to select the CAN peripheral.
-  * @param	msg: pointer to a structure which contains CAN Id, CAN DLC and CAN datas.
-  * @retval : The number of the mailbox that is used for transmission or CAN_NO_MB if there is no empty mailbox.
-  */
-CAN_TX_MBX can_transmit(CAN_Port* CANx, CanMsg* msg)
-{
-	CAN_TX_MBX mbx;
-	uint32 data;
-
-	/* Select one empty transmit mailbox */
-	if (CANx->TSR & CAN_TSR_TME0)
-		mbx = CAN_TX_MBX0;
-	else if (CANx->TSR & CAN_TSR_TME1)
-		mbx = CAN_TX_MBX1;
-	else if (CANx->TSR & CAN_TSR_TME2)
-		mbx = CAN_TX_MBX2;
-	else
-	{
-		status = CAN_NO_MB;
-		return CAN_TX_NO_MBX;
-	}
-
-    /* Set up the Id */
-    if (msg->IDE == CAN_ID_STD)
-		data = (msg->ID << 21);
-    else
-		data = (msg->ID << 3) | CAN_ID_EXT;
-
-	data |= ((uint32)msg->RTR);
-
-	/* Set up the DLC */
-    CANx->sTxMailBox[mbx].TDTR = (uint32)(msg->DLC & 0x0F);
-
-    /* Set up the data field */
-    CANx->sTxMailBox[mbx].TDLR = (
-		((uint32)msg->Data[3] << 24) | 
-		((uint32)msg->Data[2] << 16) |
-		((uint32)msg->Data[1] << 8) | 
-		((uint32)msg->Data[0])
-		);
-    CANx->sTxMailBox[mbx].TDHR = (
-		((uint32)msg->Data[7] << 24) |
-		((uint32)msg->Data[6] << 16) |
-		((uint32)msg->Data[5] << 8) |
-		((uint32)msg->Data[4])
-		);
-    /* Request transmission */
-    CANx->sTxMailBox[mbx].TIR = (data | CAN_TMIDxR_TXRQ);
-	status = CAN_OK;
-
-	return mbx;
-}
-
-/**
-  * Checks the transmission of a message.
-  * @param CANx: where x can be 1 to select the CAN peripheral.
-  * @param mbx: the number of the mailbox that is used for transmission.
-  * @retval : CAN_TX_OK if the CAN driver transmits the message, CAN_TX_FAILED in an other case.
-  */
-CAN_STATUS can_tx_status(CAN_Port* CANx, CAN_TX_MBX mbx)
-{
-	/* RQCP, TXOK and TME bits */
-	uint8 state = 0;
-
-	switch (mbx)
-	{
-	case CAN_TX_MBX0:
-		state |= (uint8)((CANx->TSR & CAN_TSR_RQCP0) << 2);
-		state |= (uint8)((CANx->TSR & CAN_TSR_TXOK0) >> 0);
-		state |= (uint8)((CANx->TSR & CAN_TSR_TME0) >> 26);
-		break;
-	case CAN_TX_MBX1:
-		state |= (uint8)((CANx->TSR & CAN_TSR_RQCP1) >> 6);
-		state |= (uint8)((CANx->TSR & CAN_TSR_TXOK1) >> 8);
-		state |= (uint8)((CANx->TSR & CAN_TSR_TME1) >> 27);
-		break;
-	case CAN_TX_MBX2:
-		state |= (uint8)((CANx->TSR & CAN_TSR_RQCP2) >> 14);
-		state |= (uint8)((CANx->TSR & CAN_TSR_TXOK2) >> 16);
-		state |= (uint8)((CANx->TSR & CAN_TSR_TME2) >> 28);
-		break;
-	default:
-		status = CAN_TX_FAILED;
-		return status;
-	}
-
-	// state = RQCP TXOK TME
-	switch (state)
-	{
-	/* transmit pending  */
-	case 0x0:
-		status = CAN_TX_PENDING;
-		break;
-	/* transmit failed  */
-	case 0x5:
-		status = CAN_TX_FAILED;
-		break;
-	/* transmit succedeed  */
-	case 0x7:
-		status = CAN_OK;
-		break;
-	default:
-		status = CAN_TX_FAILED;
-		break;
-	}
-	return status;
-}
-
-/**
-  * @brief  Cancels a transmit request.
-  * @param CANx: where x can be 1 to select the CAN peripheral.
-  * @param mbx: Mailbox number.
-  * @retval : None.
-  */
-void can_cancel(CAN_Port* CANx, uint8 mbx)
-{
-	/* abort transmission */
-	switch (mbx)
-	{
-	case 0:
-		CANx->TSR |= CAN_TSR_ABRQ0;
-		break;
-	case 1:
-		CANx->TSR |= CAN_TSR_ABRQ1;
-		break;
-	case 2:
-		CANx->TSR |= CAN_TSR_ABRQ2;
-		break;
-	default:
-		break;
-	}
-}
-
-void can_rx_queue_clear(void)
-{
-	nvic_irq_disable(NVIC_USB_LP_CAN_RX0);
-	nvic_irq_disable(NVIC_CAN_RX1);
-	__asm volatile( "dsb" );						// Synchronization of the pipeline to guarantee
-	__asm volatile( "isb" );						// that the protection against interrupts is effective
-//	can_rx_head = can_rx_tail = can_rx_count = can_rx_lost = 0;		// JMD 2017/07/18
-	can_rx_head = can_rx_tail = can_rx_lost = 0;					// JMD 2017/07/18
-	nvic_irq_enable(NVIC_USB_LP_CAN_RX0);
-	nvic_irq_enable(NVIC_CAN_RX1);
-}
-
-// JMD 2017/07/18 -- removed
-/*
-uint8 can_rx_available(void)
-{
-	return can_rx_count;
-}
-*/
-
-// JMD 2017/07/18 -- added
-uint8 can_rx_available(void)
-{
-	if ( can_rx_head >= can_rx_tail )
-		return can_rx_head - can_rx_tail ;
-	else
-		return CAN_RX_QUEUE_SIZE - ( can_rx_tail - can_rx_head ) ;
-}
-
-// JMD 2017/07/18 -- added
-uint8 can_frame_lost(void)
-{
-	if ( can_rx_lost != 0 )
-	{
-		can_rx_lost = 0 ;
-		return 1 ;
-	}
-	return 0 ;
-	
-}
-
-CanMsg* can_rx_queue_get(void)
-{
-	if (can_rx_head == can_rx_tail)			// JMD 2017/07/18 -- changed
-		return NULL;
-	return &(can_rx_queue[can_rx_tail]);
-}
-
-
-void can_rx_queue_free(void)
-{
-	if (can_rx_head != can_rx_tail)			// JMD 2017/07/18 -- changed
-	{
-		nvic_irq_disable(NVIC_USB_LP_CAN_RX0);			// JMD atomicity problem
-		nvic_irq_disable(NVIC_CAN_RX1);
-		__asm volatile( "dsb" );						// Synchronization of the pipeline to guarantee
-		__asm volatile( "isb" );						// that the protection against interrupts is effective
-		can_rx_tail = (can_rx_tail == (CAN_RX_QUEUE_SIZE - 1)) ? 0 : (can_rx_tail + 1);
-//		--can_rx_count;									// JMD 2017/07/18 -- removed
-		nvic_irq_enable(NVIC_USB_LP_CAN_RX0);			// fin JMD problème d'atomicité
-		nvic_irq_enable(NVIC_CAN_RX1);
-	}
-}
-
-CanMsg* can_read(CAN_Port* CANx, CAN_FIFO fifo, CanMsg* msg)
-{
-	uint32 data = CANx->sFIFOMailBox[fifo].RIR;
-
-	/* Get the Id */
-	if (data & CAN_ID_EXT)
-	{
-		msg->ID = 0x1FFFFFFF & (data >> 3);
-		msg->IDE = (uint8)CAN_ID_EXT;
-	}
-	else
-	{
-		msg->ID = 0x000007FF & (data >> 21);
-		msg->IDE = (uint8)CAN_ID_STD;
-	}
-
-	msg->RTR = (uint8)(CAN_RTR_REMOTE & data);
-	msg->DLC = (uint8)(0x0F & CANx->sFIFOMailBox[fifo].RDTR);
-	msg->FMI = (uint8)(0xFF & (CANx->sFIFOMailBox[fifo].RDTR >> 8));
-
-	/* Get the data field */
-	data = CANx->sFIFOMailBox[fifo].RDLR;
-	uint8* p = msg->Data;
-	*p++ = (uint8)0xFF & data;
-	*p++ = (uint8)0xFF & (data >> 8);
-	*p++ = (uint8)0xFF & (data >> 16);
-	*p++ = (uint8)0xFF & (data >> 24);
-
-	data = CANx->sFIFOMailBox[fifo].RDHR;
-	*p++ = (uint8)0xFF & data;
-	*p++ = (uint8)0xFF & (data >> 8);
-	*p++ = (uint8)0xFF & (data >> 16);
-	*p++ = (uint8)0xFF & (data >> 24);
-
-	return msg;
-}
-
-void can_rx_release(CAN_Port* CANx, CAN_FIFO fifo)
-{
-	if (fifo == CAN_FIFO0)
-		CANx->RF0R |= (CAN_RF0R_RFOM0);	// Release FIFO0
-	else
-		CANx->RF1R |= (CAN_RF1R_RFOM1);	// Release FIFO1
-}
-
-void can_rx_read(CAN_Port* CANx, CAN_FIFO fifo)
-{
-//	if (can_rx_count < CAN_RX_QUEUE_SIZE)		// JMD 2017/07/18
-	if (can_rx_available() < CAN_RX_QUEUE_SIZE)		// read the message
-	{
-		CanMsg* msg = &can_rx_queue[can_rx_head];
-		can_read(CANx, fifo, msg);
-		can_rx_head = (can_rx_head == (CAN_RX_QUEUE_SIZE - 1)) ? 0 : (can_rx_head + 1);
-//		can_rx_count++;						// JMD 2017/07/18 -- removed
-	}
-	else
-		can_rx_lost = 1;						// no place in queue, ignore package
-
-	can_rx_release(CANx, fifo);
-}
-
-uint8 CAN_RX0_IRQ_Handler(void)
-{
-	if (can_active)
-	{
-		while ((CAN1_BASE->RF0R & CAN_RF0R_FMP0) != 0)
-			can_rx_read(CAN1_BASE, CAN_FIFO0);		// message pending FIFO0
-		while ((CAN1_BASE->RF1R & CAN_RF1R_FMP1) != 0)
-			can_rx_read(CAN1_BASE, CAN_FIFO1);		// message pending FIFO1
-	}
-	return can_active;								// return CAN active flag to USB handler
-}
-
-// Addition JMD: the messages stored in fifo1 must also trigger an interrupt.
-void __irq_can_rx1(void)
-{
-	CAN_RX0_IRQ_Handler() ;
-}
-
-void USB_HP_CAN_TX_IRQHandler (void)
-{
-	if (can_active)
-	{
-		if (CAN1_BASE->TSR & CAN_TSR_RQCP0)
-			CAN1_BASE->TSR |= CAN_TSR_RQCP0;		// reset request complete mbx 0
-		if (CAN1_BASE->TSR & CAN_TSR_RQCP1)
-			CAN1_BASE->TSR |= CAN_TSR_RQCP1;		// reset request complete mbx 1
-		if (CAN1_BASE->TSR & CAN_TSR_RQCP2)
-			CAN1_BASE->TSR |= CAN_TSR_RQCP2;		// reset request complete mbx 2
-	}
-}
diff --git a/STM32F1/libraries/HardwareCAN/src/utility/can.h b/STM32F1/libraries/HardwareCAN/src/utility/can.h
index 1f2966243..357464fc9 100644
--- a/STM32F1/libraries/HardwareCAN/src/utility/can.h
+++ b/STM32F1/libraries/HardwareCAN/src/utility/can.h
@@ -280,7 +280,8 @@ CAN_STATUS can_init_enter(CAN_Port* CANx);
 CAN_STATUS can_init_leave(CAN_Port* CANx);
 CAN_STATUS can_init(CAN_Port *CANx, uint32 mode, uint8 speed);
 CAN_STATUS can_deinit(CAN_Port* CANx);
-CAN_STATUS can_filter(CAN_Port* CANx, uint8 filter_idx,  CAN_FIFO fifo_number, CAN_FILTER_SCALE scale, CAN_FILTER_MODE mode, uint32 fr1, uint32 fr2);
+CAN_STATUS can_filter(CAN_Port* CANx, uint8 filter_idx,  CAN_FIFO fifo_number, CAN_FILTER_SCALE scale, CAN_FILTER_MODE mode, uint32 fr1, uint32 fr2, int extID);
+
 CAN_STATUS can_set_timing(CAN_Port* CANx, uint32 timing);
 CAN_STATUS can_set_mode(CAN_Port* CANx, uint32 mode);
 CAN_STATUS can_gpio_map(CAN_Port* CANx, CAN_GPIO_MAP map_mode);
diff --git a/STM32F1/libraries/HardwareCAN/src/utility/can.temp.c b/STM32F1/libraries/HardwareCAN/src/utility/can.temp.c
deleted file mode 100644
index e9b270c81..000000000
--- a/STM32F1/libraries/HardwareCAN/src/utility/can.temp.c
+++ /dev/null
@@ -1,599 +0,0 @@
-Skip to content
-Features
-Business
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-Sign in or Sign up
- Watch 3  Star 2  Fork 363 megadrifter/Arduino_STM32
-forked from Phonog/Arduino_STM32
- Code  Pull requests 0  Projects 0 Insights 
-Branch: megadrifter-GM… Find file Copy pathArduino_STM32/STM32F1/libraries/HardwareCAN/src/utility/can.c
-a9807d2  9 days ago
-@megadrifter megadrifter CAN filter corrected by tjb12345
-2 contributors @megadrifter @Phonog
-RawBlameHistory     
-567 lines (500 sloc)  14.3 KB
-#include "can.h"
-
-/**
-  *	CAN_interrupts
-  */
-
-#define CAN_IT_RQCP0	((uint32)0x00000005) /* Request completed mailbox 0 */
-#define CAN_IT_RQCP1	((uint32)0x00000006) /* Request completed mailbox 1 */
-#define CAN_IT_RQCP2	((uint32)0x00000007) /* Request completed mailbox 2 */
-#define CAN_IT_TME		((uint32)0x00000001) /* Transmit mailbox empty */
-#define CAN_IT_FMP0		((uint32)0x00000002) /* FIFO 0 message pending */
-#define CAN_IT_FF0		((uint32)0x00000004) /* FIFO 0 full */
-#define CAN_IT_FOV0		((uint32)0x00000008) /* FIFO 0 overrun */
-#define CAN_IT_FMP1		((uint32)0x00000010) /* FIFO 1 message pending */
-#define CAN_IT_FF1		((uint32)0x00000020) /* FIFO 1 full */
-#define CAN_IT_FOV1		((uint32)0x00000040) /* FIFO 1 overrun */
-#define CAN_IT_EWG		((uint32)0x00000100) /* Error warning */
-#define CAN_IT_EPV		((uint32)0x00000200) /* Error passive */
-#define CAN_IT_BOF		((uint32)0x00000400) /* Bus-off */
-#define CAN_IT_LEC		((uint32)0x00000800) /* Last error code */
-#define CAN_IT_ERR		((uint32)0x00008000) /* Error */
-#define CAN_IT_WKU		((uint32)0x00010000) /* Wake-up */
-#define CAN_IT_SLK		((uint32)0x00020000) /* Sleep */
-
-/* Time out for INAK bit */
-#define CAN_INAK_TimeOut	((uint32)0x0000FFFF)
-
-/* Time out for SLAK bit */
-#define CAN_SLAK_TimeOut	((uint32)0x0000FFFF)
-
-#define CAN_CONTROL_MASK	(CAN_MCR_TTCM | CAN_MCR_ABOM | CAN_MCR_AWUM | CAN_MCR_NART | CAN_MCR_RFLM | CAN_MCR_TXFP)
-#define CAN_TIMING_MASK		(CAN_BTR_SJW | CAN_BTR_TS2 | CAN_BTR_TS1 | CAN_BTR_BRP)
-#define CAN_MODE_MASK		(CAN_BTR_LBKM | CAN_BTR_SILM)
-
-struct can_speed_info {
-    const uint32 btr;
-};
-
-#define CAN_CLOCK	(36000000UL / 18UL)
-
-static const struct can_speed_info can_speed_table[] = {
-	[CAN_SPEED_125]		= { .btr = (
-		(( 4-1) << CAN_BTR_SJW_POS) |
-		((12-1) << CAN_BTR_TS1_POS) |
-		(( 5-1) << CAN_BTR_TS2_POS) |
-		(CAN_CLOCK / 125000UL - 1)
-		)},
-	[CAN_SPEED_250]		= { .btr = (
-		(( 4-1) << CAN_BTR_SJW_POS) |
-		((12-1) << CAN_BTR_TS1_POS) |
-		(( 5-1) << CAN_BTR_TS2_POS) |
-		(CAN_CLOCK / 250000UL - 1)
-		)},
-	[CAN_SPEED_500]		= { .btr = (
-		(( 4-1) << CAN_BTR_SJW_POS) |
-		((12-1) << CAN_BTR_TS1_POS) |
-		(( 5-1) << CAN_BTR_TS2_POS) |
-		(CAN_CLOCK / 500000UL - 1)
-		)},
-	[CAN_SPEED_1000]	= { .btr = (
-		(( 4-1) << CAN_BTR_SJW_POS) |
-		((12-1) << CAN_BTR_TS1_POS) |
-		(( 5-1) << CAN_BTR_TS2_POS) |
-		(CAN_CLOCK / 1000000UL - 1)
-		)}
-};
-
-CAN_STATUS status;
-CanMsg can_rx_queue[CAN_RX_QUEUE_SIZE];
-
-// JMD 2017/07/18 -- added volatile to fix queue problems, removed can_rx_count
-volatile uint8 can_rx_head;
-volatile uint8 can_rx_tail;
-volatile uint8 can_rx_lost;
-uint8 can_active = 0;
-
-/**
-  * @brief  Return last operation status
-  */
-CAN_STATUS can_status(void)
-{
-	return status;
-}
-
-/**
-  * @brief  Enter initialization mode
-  */
-CAN_STATUS can_init_enter(CAN_Port* CANx)
-{
-	volatile uint32 wait_ack = 0 ;
-    
-	status = CAN_OK;
-	if ((CANx->MSR & CAN_MSR_INAK) == 0)	// Check for initialization mode already set
-	{
-		CANx->MCR |= CAN_MCR_INRQ;			// Request initialisation
-
-		wait_ack = 0;						// Wait the acknowledge
-		while ((wait_ack != CAN_INAK_TimeOut) && ((CANx->MSR & CAN_MSR_INAK) == 0))
-			wait_ack++;
-		if ((CANx->MSR & CAN_MSR_INAK) == 0)
-			status = CAN_INIT_E_FAILED;		// Timeout
-	}
-	return status;
-}
-
-/**
-  * @brief  Leave initialization mode
-  */
-CAN_STATUS can_init_leave(CAN_Port* CANx)
-{
-	volatile uint32 wait_ack = 0 ;
-
-	status = CAN_OK;
-	if ((CANx->MSR & CAN_MSR_INAK) != 0)	// Check for initialization mode already reset
-	{
-		CANx->MCR &= ~CAN_MCR_INRQ;			// Clear Request initialization
-
-		wait_ack = 0;						// Wait the acknowledge
-		while ((wait_ack != CAN_INAK_TimeOut) && ((CANx->MSR & CAN_MSR_INAK) != 0))
-			wait_ack++;
-		if ((CANx->MSR & CAN_MSR_INAK) != 0)
-			status = CAN_INIT_L_FAILED;
-	}
-	return status;
-}
-
-/**
-  * @brief  Deinitializes the CAN peripheral registers to their default reset values.
-  */
-CAN_STATUS can_deinit(CAN_Port* CANx)
-{
-	if (CANx == CAN1_BASE)
-	{
-		nvic_irq_disable(NVIC_USB_LP_CAN_RX0);	// Disable interrupts
-		nvic_irq_disable(NVIC_CAN_RX1);
-		nvic_irq_disable(NVIC_USB_HP_CAN_TX);
-		__asm volatile( "dsb" );						// Synchronization of the pipeline to guarantee
-		__asm volatile( "isb" );						// that the protection against interrupts is effective
-		rcc_reset_dev(RCC_CAN);
-		rcc_clk_disable(RCC_CAN);
-		can_active = 0;
-	}
-	return (status = CAN_OK);
-}
-
-/**
-  * @brief  Initialize CAN registers
-  */
-/*
- *		Bits in control parameter:
- *			CAN_MCR_TTCM	time triggered communication mode
- *			CAN_MCR_ABOM	automatic bus-off management
- *			CAN_MCR_AWUM	automatic wake-up mode
- *			CAN_MCR_NART	no automatic retransmission
- *			CAN_MCR_RFLM	receive FIFO locked mode
- *			CAN_MCR_TXFP	transmit FIFO priority
- */
-CAN_STATUS can_init(CAN_Port* CANx, uint32 control, uint8 speed)
-{
-	status = CAN_INIT_FAILED;			// default result status
-										// initialize receive message queue
-	can_rx_head = can_rx_tail = can_rx_lost = 0;
-
-	rcc_reset_dev(RCC_USB);			//! X893
-	rcc_clk_disable(RCC_USB);		//! X893
-	rcc_clk_enable(RCC_AFIO);			// enable clocks for AFIO
-	rcc_clk_enable(RCC_CAN);			// and CAN
-	rcc_reset_dev(RCC_CAN);				// reset CAN interface
-
-	can_active = 1;						// set CAN active flag (for interrupt handler
-
-	CANx->MCR &= ~CAN_MCR_SLEEP;		// reset CAN sleep mode (default after reset)
-
-	if (can_init_enter(CANx) != CAN_OK)	// enter CAN initialization mode
-		return status;					// error, so return
-
-	CANx->MCR &= ~CAN_CONTROL_MASK;		// set mode bits
-	CANx->MCR |= (control & CAN_CONTROL_MASK);
-
-	CANx->BTR &= ~CAN_TIMING_MASK;			// Set the bit timing register
-	CANx->BTR |= (can_speed_table[speed].btr & CAN_TIMING_MASK);
-
-	nvic_irq_enable(NVIC_USB_LP_CAN_RX0);	// Enable interrupts
-	nvic_irq_enable(NVIC_CAN_RX1);
-    
-	nvic_irq_enable(NVIC_USB_HP_CAN_TX);
-
-	CANx->IER = (CAN_IER_FMPIE0 | CAN_IER_FMPIE1 | CAN_IER_TMEIE);
-
-	if (can_init_leave(CANx) == CAN_OK)
-	{
-		while (!(CANx->TSR & CAN_TSR_TME0));	// Transmit mailbox 0 is empty
-		while (!(CANx->TSR & CAN_TSR_TME1));	// Transmit mailbox 0 is empty
-		while (!(CANx->TSR & CAN_TSR_TME2));	// Transmit mailbox 0 is empty
-	} 
-	return status;
-}
-
-/**
-  * @brief  Set timing calues (CAN_BTR)
-  */
-CAN_STATUS can_set_timing(CAN_Port* CANx, uint32 timing)
-{
-	if (can_init_enter(CANx) == CAN_OK)
-	{
-		CANx->BTR = ((CANx->BTR & ~CAN_TIMING_MASK) | (timing & CAN_TIMING_MASK));
-		can_init_leave(CANx);
-	}
-	return status;
-}
-
-/**
-  * @brief  Set CAN mode
-  * @param CANx pointer to CAN port
-  * @param mode CAN mode
-  */
-CAN_STATUS can_set_mode(CAN_Port* CANx, uint32 mode)
-{
-	if (can_init_enter(CANx) == CAN_OK)
-	{
-		CANx->BTR &= ~CAN_MODE_MASK;
-		CANx->BTR |= (mode & CAN_MODE_MASK);
-		can_init_leave(CANx);
-	}
-	return status;
-}
-
-/**
-  * @brief  Set CAN to GPIO mapping
-  */
-CAN_STATUS can_gpio_map(CAN_Port* CANx, CAN_GPIO_MAP map_mode)
-{
-	rcc_clk_enable(RCC_AFIO);
-
-	status = CAN_INIT_FAILED;
-	if( CANx == CAN1_BASE)
-	{
-		switch(map_mode)
-		{
-		case CAN_GPIO_PB8_PB9:
-			rcc_clk_enable(RCC_GPIOB);
-			afio_remap(AFIO_MAPR_CAN_REMAP_PB8_PB9);
-			gpio_set_mode(GPIOB, 8, GPIO_INPUT_FLOATING);
-			gpio_set_mode(GPIOB, 9, GPIO_AF_OUTPUT_PP);
-			break;
-		 case CAN_GPIO_PA11_PA12:
-			 rcc_clk_enable(RCC_GPIOA);
-			 afio_remap(AFIO_MAPR_CAN_REMAP_NONE);
-			 gpio_set_mode(GPIOA, 11, GPIO_INPUT_FLOATING);
-			 gpio_set_mode(GPIOA, 12, GPIO_AF_OUTPUT_PP);
-		 break;
-#if NR_GPIO_PORTS >= 4
-		case CAN_GPIO_PD0_PD1:
-			rcc_clk_enable(RCC_GPIOD);
-			afio_remap(AFIO_MAPR_CAN_REMAP_PD0_PD1);
-			gpio_set_mode(GPIOD, 0, GPIO_INPUT_FLOATING);
-			gpio_set_mode(GPIOD, 1, GPIO_AF_OUTPUT_PP);
-			break;
-#endif
-		default:
-			return status;
-		}
-		status = CAN_OK;
-	}
-	return status;
-}
-
-CAN_STATUS can_filter(CAN_Port* CANx, uint8 filter_idx, CAN_FIFO fifo, CAN_FILTER_SCALE scale, CAN_FILTER_MODE mode, uint32 fr1, uint32 fr2, int extID = 0)
-{
-	uint32 mask = ((uint32)0x00000001) << filter_idx;
-
-	CANx->FMR |= CAN_FMR_FINIT;		// Initialization mode for the filter
-	CANx->FA1R &= ~mask;			// Deactivation filter
-
-
-	if (scale == CAN_FILTER_32BIT)
-		CANx->FS1R |= mask;
-	else
-		CANx->FS1R &= ~mask;
-	if (extID) {
-		CANx->sFilterRegister[filter_idx].FR1 = (fr1 << 3) | CAN_ID_EXT;
-		CANx->sFilterRegister[filter_idx].FR2 = (fr2 << 3) | CAN_ID_EXT;	
-	}
-	else {
-		CANx->sFilterRegister[filter_idx].FR1 = (fr1 << 21);
-		CANx->sFilterRegister[filter_idx].FR2 = (fr2 << 21);	
-	}
-	if (mode == CAN_FILTER_MASK)
-		CANx->FM1R &= ~mask;
-	else
-		CANx->FM1R |= mask;
-
-	if (fifo == CAN_FIFO0)
-		CANx->FFA1R &= ~mask;
-	else
-		CANx->FFA1R |= mask;
-
-	CANx->FA1R |= mask;
-	CANx->FMR &= ~CAN_FMR_FINIT;
-	return CAN_OK;
-}
-
-
-/**
-  * @brief  Initiates the transmission of a message.
-  * @param	CANx: where x can be 1 to select the CAN peripheral.
-  * @param	msg: pointer to a structure which contains CAN Id, CAN DLC and CAN datas.
-  * @retval : The number of the mailbox that is used for transmission or CAN_NO_MB if there is no empty mailbox.
-  */
-CAN_TX_MBX can_transmit(CAN_Port* CANx, CanMsg* msg)
-{
-	CAN_TX_MBX mbx;
-	uint32 data;
-
-	/* Select one empty transmit mailbox */
-	if (CANx->TSR & CAN_TSR_TME0)
-		mbx = CAN_TX_MBX0;
-	else if (CANx->TSR & CAN_TSR_TME1)
-		mbx = CAN_TX_MBX1;
-	else if (CANx->TSR & CAN_TSR_TME2)
-		mbx = CAN_TX_MBX2;
-	else
-	{
-		status = CAN_NO_MB;
-		return CAN_TX_NO_MBX;
-	}
-
-    /* Set up the Id */
-    if (msg->IDE == CAN_ID_STD)
-		data = (msg->ID << 21);
-    else
-		data = (msg->ID << 3) | CAN_ID_EXT;
-
-	data |= ((uint32)msg->RTR);
-
-	/* Set up the DLC */
-    CANx->sTxMailBox[mbx].TDTR = (uint32)(msg->DLC & 0x0F);
-
-    /* Set up the data field */
-    CANx->sTxMailBox[mbx].TDLR = (
-		((uint32)msg->Data[3] << 24) | 
-		((uint32)msg->Data[2] << 16) |
-		((uint32)msg->Data[1] << 8) | 
-		((uint32)msg->Data[0])
-		);
-    CANx->sTxMailBox[mbx].TDHR = (
-		((uint32)msg->Data[7] << 24) |
-		((uint32)msg->Data[6] << 16) |
-		((uint32)msg->Data[5] << 8) |
-		((uint32)msg->Data[4])
-		);
-    /* Request transmission */
-    CANx->sTxMailBox[mbx].TIR = (data | CAN_TMIDxR_TXRQ);
-	status = CAN_OK;
-
-	return mbx;
-}
-
-/**
-  * Checks the transmission of a message.
-  * @param CANx: where x can be 1 to select the CAN peripheral.
-  * @param mbx: the number of the mailbox that is used for transmission.
-  * @retval : CAN_TX_OK if the CAN driver transmits the message, CAN_TX_FAILED in an other case.
-  */
-CAN_STATUS can_tx_status(CAN_Port* CANx, CAN_TX_MBX mbx)
-{
-	/* RQCP, TXOK and TME bits */
-	uint8 state = 0;
-
-	switch (mbx)
-	{
-	case CAN_TX_MBX0:
-		state |= (uint8)((CANx->TSR & CAN_TSR_RQCP0) << 2);
-		state |= (uint8)((CANx->TSR & CAN_TSR_TXOK0) >> 0);
-		state |= (uint8)((CANx->TSR & CAN_TSR_TME0) >> 26);
-		break;
-	case CAN_TX_MBX1:
-		state |= (uint8)((CANx->TSR & CAN_TSR_RQCP1) >> 6);
-		state |= (uint8)((CANx->TSR & CAN_TSR_TXOK1) >> 8);
-		state |= (uint8)((CANx->TSR & CAN_TSR_TME1) >> 27);
-		break;
-	case CAN_TX_MBX2:
-		state |= (uint8)((CANx->TSR & CAN_TSR_RQCP2) >> 14);
-		state |= (uint8)((CANx->TSR & CAN_TSR_TXOK2) >> 16);
-		state |= (uint8)((CANx->TSR & CAN_TSR_TME2) >> 28);
-		break;
-	default:
-		status = CAN_TX_FAILED;
-		return status;
-	}
-
-	// state = RQCP TXOK TME
-	switch (state)
-	{
-	/* transmit pending  */
-	case 0x0:
-		status = CAN_TX_PENDING;
-		break;
-	/* transmit failed  */
-	case 0x5:
-		status = CAN_TX_FAILED;
-		break;
-	/* transmit succedeed  */
-	case 0x7:
-		status = CAN_OK;
-		break;
-	default:
-		status = CAN_TX_FAILED;
-		break;
-	}
-	return status;
-}
-
-/**
-  * @brief  Cancels a transmit request.
-  * @param CANx: where x can be 1 to select the CAN peripheral.
-  * @param mbx: Mailbox number.
-  * @retval : None.
-  */
-void can_cancel(CAN_Port* CANx, uint8 mbx)
-{
-	/* abort transmission */
-	switch (mbx)
-	{
-	case 0:
-		CANx->TSR |= CAN_TSR_ABRQ0;
-		break;
-	case 1:
-		CANx->TSR |= CAN_TSR_ABRQ1;
-		break;
-	case 2:
-		CANx->TSR |= CAN_TSR_ABRQ2;
-		break;
-	default:
-		break;
-	}
-}
-
-void can_rx_queue_clear(void)
-{
-	nvic_irq_disable(NVIC_USB_LP_CAN_RX0);
-	nvic_irq_disable(NVIC_CAN_RX1);
-	__asm volatile( "dsb" );						// Synchronization of the pipeline to guarantee
-	__asm volatile( "isb" );						// that the protection against interrupts is effective
-	can_rx_head = can_rx_tail = can_rx_lost = 0;					// JMD 2017/07/18
-	nvic_irq_enable(NVIC_USB_LP_CAN_RX0);
-	nvic_irq_enable(NVIC_CAN_RX1);
-}
-
-// JMD 2017/07/18 -- changed
-uint8 can_rx_available(void)
-{
-	if ( can_rx_head >= can_rx_tail )
-		return can_rx_head - can_rx_tail ;
-	else
-		return CAN_RX_QUEUE_SIZE - ( can_rx_tail - can_rx_head ) ;
-}
-
-// JMD 2017/07/18 -- added
-uint8 can_frame_lost(void)
-{
-	if ( can_rx_lost != 0 )
-	{
-		can_rx_lost = 0 ;
-		return 1 ;
-	}
-	return 0 ;
-	
-}
-
-CanMsg* can_rx_queue_get(void)
-{
-	if (can_rx_head == can_rx_tail)			// JMD 2017/07/18 -- changed
-		return NULL;
-	return &(can_rx_queue[can_rx_tail]);
-}
-
-
-void can_rx_queue_free(void)
-{
-	if (can_rx_head != can_rx_tail)			// JMD 2017/07/18 -- changed
-	{
-		nvic_irq_disable(NVIC_USB_LP_CAN_RX0);			// JMD atomicity problem
-		nvic_irq_disable(NVIC_CAN_RX1);
-		__asm volatile( "dsb" );						// Synchronization of the pipeline to guarantee
-		__asm volatile( "isb" );						// that the protection against interrupts is effective
-		can_rx_tail = (can_rx_tail == (CAN_RX_QUEUE_SIZE - 1)) ? 0 : (can_rx_tail + 1);
-		nvic_irq_enable(NVIC_USB_LP_CAN_RX0);			// fin JMD problème d'atomicité
-		nvic_irq_enable(NVIC_CAN_RX1);
-	}
-}
-
-CanMsg* can_read(CAN_Port* CANx, CAN_FIFO fifo, CanMsg* msg)
-{
-	uint32 data = CANx->sFIFOMailBox[fifo].RIR;
-
-	/* Get the Id */
-	if (data & CAN_ID_EXT)
-	{
-		msg->ID = 0x1FFFFFFF & (data >> 3);
-		msg->IDE = (uint8)CAN_ID_EXT;
-	}
-	else
-	{
-		msg->ID = 0x000007FF & (data >> 21);
-		msg->IDE = (uint8)CAN_ID_STD;
-	}
-
-	msg->RTR = (uint8)(CAN_RTR_REMOTE & data);
-	msg->DLC = (uint8)(0x0F & CANx->sFIFOMailBox[fifo].RDTR);
-	msg->FMI = (uint8)(0xFF & (CANx->sFIFOMailBox[fifo].RDTR >> 8));
-
-	/* Get the data field */
-	data = CANx->sFIFOMailBox[fifo].RDLR;
-	uint8* p = msg->Data;
-	*p++ = (uint8)0xFF & data;
-	*p++ = (uint8)0xFF & (data >> 8);
-	*p++ = (uint8)0xFF & (data >> 16);
-	*p++ = (uint8)0xFF & (data >> 24);
-
-	data = CANx->sFIFOMailBox[fifo].RDHR;
-	*p++ = (uint8)0xFF & data;
-	*p++ = (uint8)0xFF & (data >> 8);
-	*p++ = (uint8)0xFF & (data >> 16);
-	*p++ = (uint8)0xFF & (data >> 24);
-
-	return msg;
-}
-
-void can_rx_release(CAN_Port* CANx, CAN_FIFO fifo)
-{
-	if (fifo == CAN_FIFO0)
-		CANx->RF0R |= (CAN_RF0R_RFOM0);	// Release FIFO0
-	else
-		CANx->RF1R |= (CAN_RF1R_RFOM1);	// Release FIFO1
-}
-
-void can_rx_read(CAN_Port* CANx, CAN_FIFO fifo)
-{
-	if (can_rx_available() < CAN_RX_QUEUE_SIZE)		// read the message
-	{
-		CanMsg* msg = &can_rx_queue[can_rx_head];
-		can_read(CANx, fifo, msg);
-		can_rx_head = (can_rx_head == (CAN_RX_QUEUE_SIZE - 1)) ? 0 : (can_rx_head + 1);
-	}
-	else
-		can_rx_lost = 1;						// no place in queue, ignore package
-
-	can_rx_release(CANx, fifo);
-}
-
-uint8 CAN_RX0_IRQ_Handler(void)
-{
-	if (can_active)
-	{
-		while ((CAN1_BASE->RF0R & CAN_RF0R_FMP0) != 0)
-			can_rx_read(CAN1_BASE, CAN_FIFO0);		// message pending FIFO0
-		while ((CAN1_BASE->RF1R & CAN_RF1R_FMP1) != 0)
-			can_rx_read(CAN1_BASE, CAN_FIFO1);		// message pending FIFO1
-	}
-	return can_active;								// return CAN active flag to USB handler
-}
-
-// Addition JMD: the messages stored in fifo1 must also trigger an interrupt.
-void __irq_can_rx1(void)
-{
-	CAN_RX0_IRQ_Handler() ;
-}
-
-void USB_HP_CAN_TX_IRQHandler (void)
-{
-	if (can_active)
-	{
-		if (CAN1_BASE->TSR & CAN_TSR_RQCP0)
-			CAN1_BASE->TSR |= CAN_TSR_RQCP0;		// reset request complete mbx 0
-		if (CAN1_BASE->TSR & CAN_TSR_RQCP1)
-			CAN1_BASE->TSR |= CAN_TSR_RQCP1;		// reset request complete mbx 1
-		if (CAN1_BASE->TSR & CAN_TSR_RQCP2)
-			CAN1_BASE->TSR |= CAN_TSR_RQCP2;		// reset request complete mbx 2
-	}
-}
diff --git a/STM32F1/libraries/rcc.h b/STM32F1/libraries/rcc.h
deleted file mode 100644
index aa9f8d3c9..000000000
--- a/STM32F1/libraries/rcc.h
+++ /dev/null
@@ -1,641 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- * Copyright (c) 2011 LeafLabs, LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file libmaple/stm32f1/include/series/rcc.h
- * @brief STM32F1 reset and clock control (RCC) support.
- */
-
-#ifndef _LIBMAPLE_STM32F1_RCC_H_
-#define _LIBMAPLE_STM32F1_RCC_H_
-
-#ifdef __cplusplus
-extern "C"{
-#endif
-
-#include <libmaple/libmaple_types.h>
-#include <libmaple/bitband.h>
-
-/*
- * Register map
- */
-
-/** STM32F1 RCC register map type */
-typedef struct rcc_reg_map {
-    __io uint32 CR;             /**< Clock control register */
-    __io uint32 CFGR;           /**< Clock configuration register */
-    __io uint32 CIR;            /**< Clock interrupt register */
-    __io uint32 APB2RSTR;       /**< APB2 peripheral reset register */
-    __io uint32 APB1RSTR;       /**< APB1 peripheral reset register */
-    __io uint32 AHBENR;         /**< AHB peripheral clock enable register */
-    __io uint32 APB2ENR;        /**< APB2 peripheral clock enable register */
-    __io uint32 APB1ENR;        /**< APB1 peripheral clock enable register */
-    __io uint32 BDCR;           /**< Backup domain control register */
-    __io uint32 CSR;            /**< Control/status register */
-} rcc_reg_map;
-
-#define RCC_BASE                        ((struct rcc_reg_map*)0x40021000)
-
-/*
- * Register bit definitions
- */
-
-/* Clock control register */
-
-#define RCC_CR_PLLRDY_BIT               25
-#define RCC_CR_PLLON_BIT                24
-#define RCC_CR_CSSON_BIT                19
-#define RCC_CR_HSEBYP_BIT               18
-#define RCC_CR_HSERDY_BIT               17
-#define RCC_CR_HSEON_BIT                16
-#define RCC_CR_HSIRDY_BIT               1
-#define RCC_CR_HSION_BIT                0
-
-#define RCC_CR_PLLRDY                   (1U << RCC_CR_PLLRDY_BIT)
-#define RCC_CR_PLLON                    (1U << RCC_CR_PLLON_BIT)
-#define RCC_CR_CSSON                    (1U << RCC_CR_CSSON_BIT)
-#define RCC_CR_HSEBYP                   (1U << RCC_CR_HSEBYP_BIT)
-#define RCC_CR_HSERDY                   (1U << RCC_CR_HSERDY_BIT)
-#define RCC_CR_HSEON                    (1U << RCC_CR_HSEON_BIT)
-#define RCC_CR_HSICAL                   (0xFF << 8)
-#define RCC_CR_HSITRIM                  (0x1F << 3)
-#define RCC_CR_HSIRDY                   (1U << RCC_CR_HSIRDY_BIT)
-#define RCC_CR_HSION                    (1U << RCC_CR_HSION_BIT)
-
-/* Clock configuration register */
-
-#define RCC_CFGR_USBPRE_BIT             22
-#define RCC_CFGR_PLLXTPRE_BIT           17
-#define RCC_CFGR_PLLSRC_BIT             16
-
-#define RCC_CFGR_MCO                    (0x3 << 24)
-#define RCC_CFGR_USBPRE                 (0x3 << RCC_CFGR_USBPRE_BIT)
-#define RCC_CFGR_PLLMUL                 (0xF << 18)
-#define RCC_CFGR_PLLXTPRE               (1U << RCC_CFGR_PLLXTPRE_BIT)
-#define RCC_CFGR_PLLSRC                 (1U << RCC_CFGR_PLLSRC_BIT)
-#define RCC_CFGR_ADCPRE                 (0x3 << 14)
-#define RCC_CFGR_PPRE2                  (0x7 << 11)
-#define RCC_CFGR_PPRE1                  (0x7 << 8)
-#define RCC_CFGR_HPRE                   (0xF << 4)
-#define RCC_CFGR_SWS                    (0x3 << 2)
-#define RCC_CFGR_SWS_PLL                (0x2 << 2)
-#define RCC_CFGR_SWS_HSE                (0x1 << 2)
-#define RCC_CFGR_SW                     0x3
-#define RCC_CFGR_SW_PLL                 0x2
-#define RCC_CFGR_SW_HSE                 0x1
-
-/* Clock interrupt register */
-
-#define RCC_CIR_CSSC_BIT                23
-#define RCC_CIR_PLLRDYC_BIT             20
-#define RCC_CIR_HSERDYC_BIT             19
-#define RCC_CIR_HSIRDYC_BIT             18
-#define RCC_CIR_LSERDYC_BIT             17
-#define RCC_CIR_LSIRDYC_BIT             16
-#define RCC_CIR_PLLRDYIE_BIT            12
-#define RCC_CIR_HSERDYIE_BIT            11
-#define RCC_CIR_HSIRDYIE_BIT            10
-#define RCC_CIR_LSERDYIE_BIT            9
-#define RCC_CIR_LSIRDYIE_BIT            8
-#define RCC_CIR_CSSF_BIT                7
-#define RCC_CIR_PLLRDYF_BIT             4
-#define RCC_CIR_HSERDYF_BIT             3
-#define RCC_CIR_HSIRDYF_BIT             2
-#define RCC_CIR_LSERDYF_BIT             1
-#define RCC_CIR_LSIRDYF_BIT             0
-
-#define RCC_CIR_CSSC                    (1U << RCC_CIR_CSSC_BIT)
-#define RCC_CIR_PLLRDYC                 (1U << RCC_CIR_PLLRDYC_BIT)
-#define RCC_CIR_HSERDYC                 (1U << RCC_CIR_HSERDYC_BIT)
-#define RCC_CIR_HSIRDYC                 (1U << RCC_CIR_HSIRDYC_BIT)
-#define RCC_CIR_LSERDYC                 (1U << RCC_CIR_LSERDYC_BIT)
-#define RCC_CIR_LSIRDYC                 (1U << RCC_CIR_LSIRDYC_BIT)
-#define RCC_CIR_PLLRDYIE                (1U << RCC_CIR_PLLRDYIE_BIT)
-#define RCC_CIR_HSERDYIE                (1U << RCC_CIR_HSERDYIE_BIT)
-#define RCC_CIR_HSIRDYIE                (1U << RCC_CIR_HSIRDYIE_BIT)
-#define RCC_CIR_LSERDYIE                (1U << RCC_CIR_LSERDYIE_BIT)
-#define RCC_CIR_LSIRDYIE                (1U << RCC_CIR_LSIRDYIE_BIT)
-#define RCC_CIR_CSSF                    (1U << RCC_CIR_CSSF_BIT)
-#define RCC_CIR_PLLRDYF                 (1U << RCC_CIR_PLLRDYF_BIT)
-#define RCC_CIR_HSERDYF                 (1U << RCC_CIR_HSERDYF_BIT)
-#define RCC_CIR_HSIRDYF                 (1U << RCC_CIR_HSIRDYF_BIT)
-#define RCC_CIR_LSERDYF                 (1U << RCC_CIR_LSERDYF_BIT)
-#define RCC_CIR_LSIRDYF                 (1U << RCC_CIR_LSIRDYF_BIT)
-
-/* APB2 peripheral reset register */
-
-#define RCC_APB2RSTR_TIM11RST_BIT       21
-#define RCC_APB2RSTR_TIM10RST_BIT       20
-#define RCC_APB2RSTR_TIM9RST_BIT        19
-#define RCC_APB2RSTR_ADC3RST_BIT        15
-#define RCC_APB2RSTR_USART1RST_BIT      14
-#define RCC_APB2RSTR_TIM8RST_BIT        13
-#define RCC_APB2RSTR_SPI1RST_BIT        12
-#define RCC_APB2RSTR_TIM1RST_BIT        11
-#define RCC_APB2RSTR_ADC2RST_BIT        10
-#define RCC_APB2RSTR_ADC1RST_BIT        9
-#define RCC_APB2RSTR_IOPGRST_BIT        8
-#define RCC_APB2RSTR_IOPFRST_BIT        7
-#define RCC_APB2RSTR_IOPERST_BIT        6
-#define RCC_APB2RSTR_IOPDRST_BIT        5
-#define RCC_APB2RSTR_IOPCRST_BIT        4
-#define RCC_APB2RSTR_IOPBRST_BIT        3
-#define RCC_APB2RSTR_IOPARST_BIT        2
-#define RCC_APB2RSTR_AFIORST_BIT        0
-
-#define RCC_APB2RSTR_TIM11RST           (1U << RCC_APB2RSTR_TIM11RST_BIT)
-#define RCC_APB2RSTR_TIM10RST           (1U << RCC_APB2RSTR_TIM10RST_BIT)
-#define RCC_APB2RSTR_TIM9RST            (1U << RCC_APB2RSTR_TIM9RST_BIT)
-#define RCC_APB2RSTR_ADC3RST            (1U << RCC_APB2RSTR_ADC3RST_BIT)
-#define RCC_APB2RSTR_USART1RST          (1U << RCC_APB2RSTR_USART1RST_BIT)
-#define RCC_APB2RSTR_TIM8RST            (1U << RCC_APB2RSTR_TIM8RST_BIT)
-#define RCC_APB2RSTR_SPI1RST            (1U << RCC_APB2RSTR_SPI1RST_BIT)
-#define RCC_APB2RSTR_TIM1RST            (1U << RCC_APB2RSTR_TIM1RST_BIT)
-#define RCC_APB2RSTR_ADC2RST            (1U << RCC_APB2RSTR_ADC2RST_BIT)
-#define RCC_APB2RSTR_ADC1RST            (1U << RCC_APB2RSTR_ADC1RST_BIT)
-#define RCC_APB2RSTR_IOPGRST            (1U << RCC_APB2RSTR_IOPGRST_BIT)
-#define RCC_APB2RSTR_IOPFRST            (1U << RCC_APB2RSTR_IOPFRST_BIT)
-#define RCC_APB2RSTR_IOPERST            (1U << RCC_APB2RSTR_IOPERST_BIT)
-#define RCC_APB2RSTR_IOPDRST            (1U << RCC_APB2RSTR_IOPDRST_BIT)
-#define RCC_APB2RSTR_IOPCRST            (1U << RCC_APB2RSTR_IOPCRST_BIT)
-#define RCC_APB2RSTR_IOPBRST            (1U << RCC_APB2RSTR_IOPBRST_BIT)
-#define RCC_APB2RSTR_IOPARST            (1U << RCC_APB2RSTR_IOPARST_BIT)
-#define RCC_APB2RSTR_AFIORST            (1U << RCC_APB2RSTR_AFIORST_BIT)
-
-/* APB1 peripheral reset register */
-
-#define RCC_APB1RSTR_DACRST_BIT         29
-#define RCC_APB1RSTR_PWRRST_BIT         28
-#define RCC_APB1RSTR_BKPRST_BIT         27
-#define RCC_APB1RSTR_CANRST_BIT         25
-#define RCC_APB1RSTR_USBRST_BIT         23
-#define RCC_APB1RSTR_I2C2RST_BIT        22
-#define RCC_APB1RSTR_I2C1RST_BIT        21
-#define RCC_APB1RSTR_UART5RST_BIT       20
-#define RCC_APB1RSTR_UART4RST_BIT       19
-#define RCC_APB1RSTR_USART3RST_BIT      18
-#define RCC_APB1RSTR_USART2RST_BIT      17
-#define RCC_APB1RSTR_SPI3RST_BIT        15
-#define RCC_APB1RSTR_SPI2RST_BIT        14
-#define RCC_APB1RSTR_WWDRST_BIT         11
-#define RCC_APB1RSTR_TIM14RST_BIT       8
-#define RCC_APB1RSTR_TIM13RST_BIT       7
-#define RCC_APB1RSTR_TIM12RST_BIT       6
-#define RCC_APB1RSTR_TIM7RST_BIT        5
-#define RCC_APB1RSTR_TIM6RST_BIT        4
-#define RCC_APB1RSTR_TIM5RST_BIT        3
-#define RCC_APB1RSTR_TIM4RST_BIT        2
-#define RCC_APB1RSTR_TIM3RST_BIT        1
-#define RCC_APB1RSTR_TIM2RST_BIT        0
-
-#define RCC_APB1RSTR_DACRST             (1U << RCC_APB1RSTR_DACRST_BIT)
-#define RCC_APB1RSTR_PWRRST             (1U << RCC_APB1RSTR_PWRRST_BIT)
-#define RCC_APB1RSTR_BKPRST             (1U << RCC_APB1RSTR_BKPRST_BIT)
-#define RCC_APB1RSTR_CANRST             (1U << RCC_APB1RSTR_CANRST_BIT)
-#define RCC_APB1RSTR_USBRST             (1U << RCC_APB1RSTR_USBRST_BIT)
-#define RCC_APB1RSTR_I2C2RST            (1U << RCC_APB1RSTR_I2C2RST_BIT)
-#define RCC_APB1RSTR_I2C1RST            (1U << RCC_APB1RSTR_I2C1RST_BIT)
-#define RCC_APB1RSTR_UART5RST           (1U << RCC_APB1RSTR_UART5RST_BIT)
-#define RCC_APB1RSTR_UART4RST           (1U << RCC_APB1RSTR_UART4RST_BIT)
-#define RCC_APB1RSTR_USART3RST          (1U << RCC_APB1RSTR_USART3RST_BIT)
-#define RCC_APB1RSTR_USART2RST          (1U << RCC_APB1RSTR_USART2RST_BIT)
-#define RCC_APB1RSTR_SPI3RST            (1U << RCC_APB1RSTR_SPI3RST_BIT)
-#define RCC_APB1RSTR_SPI2RST            (1U << RCC_APB1RSTR_SPI2RST_BIT)
-#define RCC_APB1RSTR_WWDRST             (1U << RCC_APB1RSTR_WWDRST_BIT)
-#define RCC_APB1RSTR_TIM14RST           (1U << RCC_APB1RSTR_TIM14RST_BIT)
-#define RCC_APB1RSTR_TIM13RST           (1U << RCC_APB1RSTR_TIM13RST_BIT)
-#define RCC_APB1RSTR_TIM12RST           (1U << RCC_APB1RSTR_TIM12RST_BIT)
-#define RCC_APB1RSTR_TIM7RST            (1U << RCC_APB1RSTR_TIM7RST_BIT)
-#define RCC_APB1RSTR_TIM6RST            (1U << RCC_APB1RSTR_TIM6RST_BIT)
-#define RCC_APB1RSTR_TIM5RST            (1U << RCC_APB1RSTR_TIM5RST_BIT)
-#define RCC_APB1RSTR_TIM4RST            (1U << RCC_APB1RSTR_TIM4RST_BIT)
-#define RCC_APB1RSTR_TIM3RST            (1U << RCC_APB1RSTR_TIM3RST_BIT)
-#define RCC_APB1RSTR_TIM2RST            (1U << RCC_APB1RSTR_TIM2RST_BIT)
-
-/* AHB peripheral clock enable register */
-
-#define RCC_AHBENR_SDIOEN_BIT           10
-#define RCC_AHBENR_FSMCEN_BIT           8
-#define RCC_AHBENR_CRCEN_BIT            7
-#define RCC_AHBENR_FLITFEN_BIT          4
-#define RCC_AHBENR_SRAMEN_BIT           2
-#define RCC_AHBENR_DMA2EN_BIT           1
-#define RCC_AHBENR_DMA1EN_BIT           0
-
-#define RCC_AHBENR_SDIOEN               (1U << RCC_AHBENR_SDIOEN_BIT)
-#define RCC_AHBENR_FSMCEN               (1U << RCC_AHBENR_FSMCEN_BIT)
-#define RCC_AHBENR_CRCEN                (1U << RCC_AHBENR_CRCEN_BIT)
-#define RCC_AHBENR_FLITFEN              (1U << RCC_AHBENR_FLITFEN_BIT)
-#define RCC_AHBENR_SRAMEN               (1U << RCC_AHBENR_SRAMEN_BIT)
-#define RCC_AHBENR_DMA2EN               (1U << RCC_AHBENR_DMA2EN_BIT)
-#define RCC_AHBENR_DMA1EN               (1U << RCC_AHBENR_DMA1EN_BIT)
-
-/* APB2 peripheral clock enable register */
-
-#define RCC_APB2ENR_TIM11EN_BIT         21
-#define RCC_APB2ENR_TIM10EN_BIT         20
-#define RCC_APB2ENR_TIM9EN_BIT          19
-#define RCC_APB2ENR_ADC3EN_BIT          15
-#define RCC_APB2ENR_USART1EN_BIT        14
-#define RCC_APB2ENR_TIM8EN_BIT          13
-#define RCC_APB2ENR_SPI1EN_BIT          12
-#define RCC_APB2ENR_TIM1EN_BIT          11
-#define RCC_APB2ENR_ADC2EN_BIT          10
-#define RCC_APB2ENR_ADC1EN_BIT          9
-#define RCC_APB2ENR_IOPGEN_BIT          8
-#define RCC_APB2ENR_IOPFEN_BIT          7
-#define RCC_APB2ENR_IOPEEN_BIT          6
-#define RCC_APB2ENR_IOPDEN_BIT          5
-#define RCC_APB2ENR_IOPCEN_BIT          4
-#define RCC_APB2ENR_IOPBEN_BIT          3
-#define RCC_APB2ENR_IOPAEN_BIT          2
-#define RCC_APB2ENR_AFIOEN_BIT          0
-
-#define RCC_APB2ENR_TIM11EN             (1U << RCC_APB2ENR_TIM11EN_BIT)
-#define RCC_APB2ENR_TIM10EN             (1U << RCC_APB2ENR_TIM10EN_BIT)
-#define RCC_APB2ENR_TIM9EN              (1U << RCC_APB2ENR_TIM9EN_BIT)
-#define RCC_APB2ENR_ADC3EN              (1U << RCC_APB2ENR_ADC3EN_BIT)
-#define RCC_APB2ENR_USART1EN            (1U << RCC_APB2ENR_USART1EN_BIT)
-#define RCC_APB2ENR_TIM8EN              (1U << RCC_APB2ENR_TIM8EN_BIT)
-#define RCC_APB2ENR_SPI1EN              (1U << RCC_APB2ENR_SPI1EN_BIT)
-#define RCC_APB2ENR_TIM1EN              (1U << RCC_APB2ENR_TIM1EN_BIT)
-#define RCC_APB2ENR_ADC2EN              (1U << RCC_APB2ENR_ADC2EN_BIT)
-#define RCC_APB2ENR_ADC1EN              (1U << RCC_APB2ENR_ADC1EN_BIT)
-#define RCC_APB2ENR_IOPGEN              (1U << RCC_APB2ENR_IOPGEN_BIT)
-#define RCC_APB2ENR_IOPFEN              (1U << RCC_APB2ENR_IOPFEN_BIT)
-#define RCC_APB2ENR_IOPEEN              (1U << RCC_APB2ENR_IOPEEN_BIT)
-#define RCC_APB2ENR_IOPDEN              (1U << RCC_APB2ENR_IOPDEN_BIT)
-#define RCC_APB2ENR_IOPCEN              (1U << RCC_APB2ENR_IOPCEN_BIT)
-#define RCC_APB2ENR_IOPBEN              (1U << RCC_APB2ENR_IOPBEN_BIT)
-#define RCC_APB2ENR_IOPAEN              (1U << RCC_APB2ENR_IOPAEN_BIT)
-#define RCC_APB2ENR_AFIOEN              (1U << RCC_APB2ENR_AFIOEN_BIT)
-
-/* APB1 peripheral clock enable register */
-
-#define RCC_APB1ENR_DACEN_BIT           29
-#define RCC_APB1ENR_PWREN_BIT           28
-#define RCC_APB1ENR_BKPEN_BIT           27
-#define RCC_APB1ENR_CANEN_BIT           25
-#define RCC_APB1ENR_USBEN_BIT           23
-#define RCC_APB1ENR_I2C2EN_BIT          22
-#define RCC_APB1ENR_I2C1EN_BIT          21
-#define RCC_APB1ENR_UART5EN_BIT         20
-#define RCC_APB1ENR_UART4EN_BIT         19
-#define RCC_APB1ENR_USART3EN_BIT        18
-#define RCC_APB1ENR_USART2EN_BIT        17
-#define RCC_APB1ENR_SPI3EN_BIT          15
-#define RCC_APB1ENR_SPI2EN_BIT          14
-#define RCC_APB1ENR_WWDEN_BIT           11
-#define RCC_APB1ENR_TIM14EN_BIT         8
-#define RCC_APB1ENR_TIM13EN_BIT         7
-#define RCC_APB1ENR_TIM12EN_BIT         6
-#define RCC_APB1ENR_TIM7EN_BIT          5
-#define RCC_APB1ENR_TIM6EN_BIT          4
-#define RCC_APB1ENR_TIM5EN_BIT          3
-#define RCC_APB1ENR_TIM4EN_BIT          2
-#define RCC_APB1ENR_TIM3EN_BIT          1
-#define RCC_APB1ENR_TIM2EN_BIT          0
-
-#define RCC_APB1ENR_DACEN               (1U << RCC_APB1ENR_DACEN_BIT)
-#define RCC_APB1ENR_PWREN               (1U << RCC_APB1ENR_PWREN_BIT)
-#define RCC_APB1ENR_BKPEN               (1U << RCC_APB1ENR_BKPEN_BIT)
-#define RCC_APB1ENR_CANEN               (1U << RCC_APB1ENR_CANEN_BIT)
-#define RCC_APB1ENR_USBEN               (1U << RCC_APB1ENR_USBEN_BIT)
-#define RCC_APB1ENR_I2C2EN              (1U << RCC_APB1ENR_I2C2EN_BIT)
-#define RCC_APB1ENR_I2C1EN              (1U << RCC_APB1ENR_I2C1EN_BIT)
-#define RCC_APB1ENR_UART5EN             (1U << RCC_APB1ENR_UART5EN_BIT)
-#define RCC_APB1ENR_UART4EN             (1U << RCC_APB1ENR_UART4EN_BIT)
-#define RCC_APB1ENR_USART3EN            (1U << RCC_APB1ENR_USART3EN_BIT)
-#define RCC_APB1ENR_USART2EN            (1U << RCC_APB1ENR_USART2EN_BIT)
-#define RCC_APB1ENR_SPI3EN              (1U << RCC_APB1ENR_SPI3EN_BIT)
-#define RCC_APB1ENR_SPI2EN              (1U << RCC_APB1ENR_SPI2EN_BIT)
-#define RCC_APB1ENR_WWDEN               (1U << RCC_APB1ENR_WWDEN_BIT)
-#define RCC_APB1ENR_TIM14EN             (1U << RCC_APB1ENR_TIM14EN_BIT)
-#define RCC_APB1ENR_TIM13EN             (1U << RCC_APB1ENR_TIM13EN_BIT)
-#define RCC_APB1ENR_TIM12EN             (1U << RCC_APB1ENR_TIM12EN_BIT)
-#define RCC_APB1ENR_TIM7EN              (1U << RCC_APB1ENR_TIM7EN_BIT)
-#define RCC_APB1ENR_TIM6EN              (1U << RCC_APB1ENR_TIM6EN_BIT)
-#define RCC_APB1ENR_TIM5EN              (1U << RCC_APB1ENR_TIM5EN_BIT)
-#define RCC_APB1ENR_TIM4EN              (1U << RCC_APB1ENR_TIM4EN_BIT)
-#define RCC_APB1ENR_TIM3EN              (1U << RCC_APB1ENR_TIM3EN_BIT)
-#define RCC_APB1ENR_TIM2EN              (1U << RCC_APB1ENR_TIM2EN_BIT)
-
-/* Backup domain control register */
-
-#define RCC_BDCR_BDRST_BIT              16
-#define RCC_BDCR_RTCEN_BIT              15
-#define RCC_BDCR_LSEBYP_BIT             2
-#define RCC_BDCR_LSERDY_BIT             1
-#define RCC_BDCR_LSEON_BIT              0
-
-#define RCC_BDCR_BDRST                  (1U << RCC_BDCR_BDRST_BIT)
-#define RCC_BDCR_RTCEN                  (1U << RCC_BDCR_RTC_BIT)
-#define RCC_BDCR_RTCSEL                 (0x3 << 8)
-#define RCC_BDCR_RTCSEL_NONE            (0x0 << 8)
-#define RCC_BDCR_RTCSEL_LSE             (0x1 << 8)
-#define RCC_BDCR_RTCSEL_LSI             (0x2 << 8) // added to support RTClock
-#define RCC_BDCR_RTCSEL_HSE             (0x3 << 8)
-#define RCC_BDCR_LSEBYP                 (1U << RCC_BDCR_LSEBYP_BIT)
-#define RCC_BDCR_LSERDY                 (1U << RCC_BDCR_LSERDY_BIT)
-#define RCC_BDCR_LSEON                  (1U << RCC_BDCR_LSEON_BIT)
-
-/* Control/status register */
-
-#define RCC_CSR_LPWRRSTF_BIT            31
-#define RCC_CSR_WWDGRSTF_BIT            30
-#define RCC_CSR_IWDGRSTF_BIT            29
-#define RCC_CSR_SFTRSTF_BIT             28
-#define RCC_CSR_PORRSTF_BIT             27
-#define RCC_CSR_PINRSTF_BIT             26
-#define RCC_CSR_RMVF_BIT                24
-#define RCC_CSR_LSIRDY_BIT              1
-#define RCC_CSR_LSION_BIT               0
-
-#define RCC_CSR_LPWRRSTF                (1U << RCC_CSR_LPWRRSTF_BIT)
-#define RCC_CSR_WWDGRSTF                (1U << RCC_CSR_WWDGRSTF_BIT)
-#define RCC_CSR_IWDGRSTF                (1U << RCC_CSR_IWDGRSTF_BIT)
-#define RCC_CSR_SFTRSTF                 (1U << RCC_CSR_SFTRSTF_BIT)
-#define RCC_CSR_PORRSTF                 (1U << RCC_CSR_PORRSTF_BIT)
-#define RCC_CSR_PINRSTF                 (1U << RCC_CSR_PINRSTF_BIT)
-#define RCC_CSR_RMVF                    (1U << RCC_CSR_RMVF_BIT)
-#define RCC_CSR_LSIRDY                  (1U << RCC_CSR_LSIRDY_BIT)
-#define RCC_CSR_LSION                   (1U << RCC_CSR_LSION_BIT)
-
-/*
- * libmaple-mandated enumeration types.
- */
-
-/**
- * @brief STM32F1 rcc_clk_id.
- */
-typedef enum rcc_clk_id {
-    RCC_ADC1,
-    RCC_ADC2,
-    RCC_ADC3,
-    RCC_AFIO,
-    RCC_BKP,
-    RCC_CRC,
-    RCC_DAC,
-    RCC_DMA1,
-    RCC_DMA2,
-    RCC_FLITF,
-    RCC_FSMC,
-    RCC_GPIOA,
-    RCC_GPIOB,
-    RCC_GPIOC,
-    RCC_GPIOD,
-    RCC_GPIOE,
-    RCC_GPIOF,
-    RCC_GPIOG,
-    RCC_I2C1,
-    RCC_I2C2,
-    RCC_PWR,
-    RCC_SDIO,
-    RCC_SPI1,
-    RCC_SPI2,
-    RCC_SPI3,
-    RCC_SRAM,
-    RCC_TIMER1,
-    RCC_TIMER2,
-    RCC_TIMER3,
-    RCC_TIMER4,
-    RCC_TIMER5,
-    RCC_TIMER6,
-    RCC_TIMER7,
-    RCC_TIMER8,
-    RCC_TIMER9,
-    RCC_TIMER10,
-    RCC_TIMER11,
-    RCC_TIMER12,
-    RCC_TIMER13,
-    RCC_TIMER14,
-    RCC_USART1,
-    RCC_USART2,
-    RCC_USART3,
-    RCC_UART4,
-    RCC_UART5,
-    RCC_USB,
-	RCC_CAN,	//! JMD after X893
-} rcc_clk_id;
-
-/**
- * @brief STM32F1 PLL clock sources.
- * @see rcc_configure_pll()
- */
-typedef enum rcc_pllsrc {
-    RCC_PLLSRC_HSE = (0x1 << 16),
-    RCC_PLLSRC_HSI_DIV_2 = (0x0 << 16)
-} rcc_pllsrc;
-
-/**
- * @brief STM32F1 clock domains.
- * @see rcc_dev_clk()
- */
-typedef enum rcc_clk_domain {
-    RCC_APB1,
-    RCC_APB2,
-    RCC_AHB
-} rcc_clk_domain;
-
-/**
- * @brief STM32F1 Prescaler identifiers
- * @see rcc_set_prescaler()
- */
-typedef enum rcc_prescaler {
-    RCC_PRESCALER_AHB,
-    RCC_PRESCALER_APB1,
-    RCC_PRESCALER_APB2,
-    RCC_PRESCALER_USB,
-    RCC_PRESCALER_ADC
-} rcc_prescaler;
-
-/**
- * @brief STM32F1 ADC prescaler dividers
- * @see rcc_set_prescaler()
- */
-typedef enum rcc_adc_divider {
-    RCC_ADCPRE_PCLK_DIV_2 = 0x0 << 14,
-    RCC_ADCPRE_PCLK_DIV_4 = 0x1 << 14,
-    RCC_ADCPRE_PCLK_DIV_6 = 0x2 << 14,
-    RCC_ADCPRE_PCLK_DIV_8 = 0x3 << 14,
-} rcc_adc_divider;
-
-/**
- * @brief STM32F1 APB1 prescaler dividers
- * @see rcc_set_prescaler()
- */
-typedef enum rcc_apb1_divider {
-    RCC_APB1_HCLK_DIV_1 = 0x0 << 8,
-    RCC_APB1_HCLK_DIV_2 = 0x4 << 8,
-    RCC_APB1_HCLK_DIV_4 = 0x5 << 8,
-    RCC_APB1_HCLK_DIV_8 = 0x6 << 8,
-    RCC_APB1_HCLK_DIV_16 = 0x7 << 8,
-} rcc_apb1_divider;
-
-/**
- * @brief STM32F1 APB2 prescaler dividers
- * @see rcc_set_prescaler()
- */
-typedef enum rcc_apb2_divider {
-    RCC_APB2_HCLK_DIV_1 = 0x0 << 11,
-    RCC_APB2_HCLK_DIV_2 = 0x4 << 11,
-    RCC_APB2_HCLK_DIV_4 = 0x5 << 11,
-    RCC_APB2_HCLK_DIV_8 = 0x6 << 11,
-    RCC_APB2_HCLK_DIV_16 = 0x7 << 11,
-} rcc_apb2_divider;
-
-/**
- * @brief STM32F1 AHB prescaler dividers
- * @see rcc_set_prescaler()
- */
-typedef enum rcc_ahb_divider {
-    RCC_AHB_SYSCLK_DIV_1 = 0x0 << 4,
-    RCC_AHB_SYSCLK_DIV_2 = 0x8 << 4,
-    RCC_AHB_SYSCLK_DIV_4 = 0x9 << 4,
-    RCC_AHB_SYSCLK_DIV_8 = 0xA << 4,
-    RCC_AHB_SYSCLK_DIV_16 = 0xB << 4,
-    RCC_AHB_SYSCLK_DIV_32 = 0xC << 4,
-    RCC_AHB_SYSCLK_DIV_64 = 0xD << 4,
-    RCC_AHB_SYSCLK_DIV_128 = 0xD << 4,
-    RCC_AHB_SYSCLK_DIV_256 = 0xE << 4,
-    RCC_AHB_SYSCLK_DIV_512 = 0xF << 4,
-} rcc_ahb_divider;
-
-/**
- * @brief STM32F1 USB prescaler dividers
- * @see rcc_set_prescaler()
- */
- /*
- Set and reset by software to control the USB clock prescaler value. The USB clock
-must be 48MHz. These bits can’t be reset if the USB clock is enabled.
-00: (CK_PLL / 1.5) selected
-01: CK_PLL selected
- */
- 
-typedef enum rcc_usb_divider {
-    RCC_USB_SYSCLK_DIV_1 = 0x1 << 22,
-    RCC_USB_SYSCLK_DIV_1_5 = 0x0 << 22,
-    RCC_USB_SYSCLK_DIV_2 = 0x3 << 22,
-    RCC_USB_SYSCLK_DIV_2_5 = 0x2 << 22,
-} rcc_usb_divider;
-
-
-/**
- * @brief Start the low speed internal oscillator
- */
-static inline void rcc_start_lsi(void) {
-	*bb_perip(&RCC_BASE->CSR, RCC_CSR_LSION_BIT) = 1;
-	while (*bb_perip(&RCC_BASE->CSR, RCC_CSR_LSIRDY_BIT) == 0);
-}
-
-/**
- * @brief STM32F1 clock sources.
- */
-typedef enum rcc_clk {
-    RCC_CLK_PLL    = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) |
-                              RCC_CR_PLLON_BIT), /**< Main PLL, clocked by
-                                                    HSI or HSE. */
-    RCC_CLK_HSE    = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) |
-                              RCC_CR_HSEON_BIT), /**< High speed external. */
-    RCC_CLK_HSI    = (uint16)((offsetof(struct rcc_reg_map, CR) << 8) |
-                              RCC_CR_HSION_BIT), /**< High speed internal. */
-    RCC_CLK_LSE    = (uint16)((offsetof(struct rcc_reg_map, BDCR) << 8) |
-                              RCC_BDCR_LSEON_BIT), /**< Low-speed external
-                                                    * (32.768 KHz). */
-    RCC_CLK_LSI    = (uint16)((offsetof(struct rcc_reg_map, CSR) << 8) |
-                              RCC_CSR_LSION_BIT), /**< Low-speed internal
-                                                   * (approximately 32 KHz). */
-} rcc_clk;
-
-/**
- * @brief STM32F1 PLL multipliers.
- */
-typedef enum rcc_pll_multiplier {
-    RCC_PLLMUL_2 = (0x0 << 18),
-    RCC_PLLMUL_3 = (0x1 << 18),
-    RCC_PLLMUL_4 = (0x2 << 18),
-    RCC_PLLMUL_5 = (0x3 << 18),
-    RCC_PLLMUL_6 = (0x4 << 18),
-    RCC_PLLMUL_7 = (0x5 << 18),
-    RCC_PLLMUL_8 = (0x6 << 18),
-    RCC_PLLMUL_9 = (0x7 << 18),
-    RCC_PLLMUL_10 = (0x8 << 18),
-    RCC_PLLMUL_11 = (0x9 << 18),
-    RCC_PLLMUL_12 = (0xA << 18),
-    RCC_PLLMUL_13 = (0xB << 18),
-    RCC_PLLMUL_14 = (0xC << 18),
-    RCC_PLLMUL_15 = (0xD << 18),
-    RCC_PLLMUL_16 = (0xE << 18),
-} rcc_pll_multiplier;
-
-/* FIXME [0.0.13] Just have data point to an rcc_pll_multiplier! */
-/**
- * @brief Start the low speed external oscillatior
- */
-static inline void rcc_start_lse(void) {
-	bb_peri_set_bit(&RCC_BASE->BDCR, RCC_BDCR_LSEBYP_BIT, 0);
-	bb_peri_set_bit(&RCC_BASE->BDCR, RCC_BDCR_LSEON_BIT, 1);
-	while (bb_peri_get_bit(&RCC_BASE->BDCR, RCC_BDCR_LSERDY_BIT ) == 0);
-}
-
-/**
- * @brief STM32F1 PLL configuration values.
- * Point to one of these with the "data" field in a struct rcc_pll_cfg.
- * @see struct rcc_pll_cfg.
- */
-typedef struct stm32f1_rcc_pll_data {
-     rcc_pll_multiplier pll_mul; /**< PLL multiplication factor. */
-} stm32f1_rcc_pll_data;
-
-/*
- * Deprecated bits.
- */
-static inline void rcc_start_hse(void) {				// Added to support RTClock
-//	*bb_perip(&RCC_BASE->CR, RCC_CR_HSEON_BIT) = 1;
-	while (bb_peri_get_bit(&RCC_BASE->CR, RCC_CR_HSERDY_BIT) == 0);
-}
-
-/**
- * @brief Deprecated; STM32F1 only.
- *
- * Initialize the clock control system. Initializes the system
- * clock source to use the PLL driven by an external oscillator.
- *
- * @param sysclk_src system clock source, must be PLL
- * @param pll_src pll clock source, must be HSE
- * @param pll_mul pll multiplier
- */
-__deprecated
-void rcc_clk_init(rcc_sysclk_src sysclk_src,
-                  rcc_pllsrc pll_src,
-                  rcc_pll_multiplier pll_mul);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif
diff --git a/STM32F1/libraries/rcc_f1.c b/STM32F1/libraries/rcc_f1.c
deleted file mode 100644
index 9040a4dc2..000000000
--- a/STM32F1/libraries/rcc_f1.c
+++ /dev/null
@@ -1,174 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 Perry Hung.
- * Copyright (c) 2011 LeafLabs, LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be
- * included in all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file libmaple/stm32f1/rcc.c
- * @brief STM32F1 RCC.
- */
-
-#include <libmaple/rcc.h>
-#include <libmaple/libmaple.h>
-#include <libmaple/bitband.h>
-
-#include "rcc_private.h"
-
-#define APB1                            RCC_APB1
-#define APB2                            RCC_APB2
-#define AHB                             RCC_AHB
-
-/* Device descriptor table, maps rcc_clk_id onto bus and enable/reset
- * register bit numbers. */
-const struct rcc_dev_info rcc_dev_table[] = {
-    [RCC_GPIOA]  = { .clk_domain = APB2, .line_num = 2 },
-    [RCC_GPIOB]  = { .clk_domain = APB2, .line_num = 3 },
-    [RCC_GPIOC]  = { .clk_domain = APB2, .line_num = 4 },
-    [RCC_GPIOD]  = { .clk_domain = APB2, .line_num = 5 },
-    [RCC_AFIO]   = { .clk_domain = APB2, .line_num = 0 },
-    [RCC_ADC1]   = { .clk_domain = APB2, .line_num = 9 },
-    [RCC_ADC2]   = { .clk_domain = APB2, .line_num = 10 },
-    [RCC_ADC3]   = { .clk_domain = APB2, .line_num = 15 },
-    [RCC_USART1] = { .clk_domain = APB2, .line_num = 14 },
-    [RCC_USART2] = { .clk_domain = APB1, .line_num = 17 },
-    [RCC_USART3] = { .clk_domain = APB1, .line_num = 18 },
-    [RCC_TIMER1] = { .clk_domain = APB2, .line_num = 11 },
-    [RCC_TIMER2] = { .clk_domain = APB1, .line_num = 0 },
-    [RCC_TIMER3] = { .clk_domain = APB1, .line_num = 1 },
-    [RCC_TIMER4] = { .clk_domain = APB1, .line_num = 2 },
-    [RCC_SPI1]   = { .clk_domain = APB2, .line_num = 12 },
-    [RCC_SPI2]   = { .clk_domain = APB1, .line_num = 14 },
-    [RCC_DMA1]   = { .clk_domain = AHB,  .line_num = 0 },
-    [RCC_PWR]    = { .clk_domain = APB1, .line_num = 28},
-    [RCC_BKP]    = { .clk_domain = APB1, .line_num = 27},
-    [RCC_I2C1]   = { .clk_domain = APB1, .line_num = 21 },
-    [RCC_I2C2]   = { .clk_domain = APB1, .line_num = 22 },
-    [RCC_CRC]    = { .clk_domain = AHB,  .line_num = 6},
-    [RCC_FLITF]  = { .clk_domain = AHB,  .line_num = 4},
-    [RCC_SRAM]   = { .clk_domain = AHB,  .line_num = 2},
-    [RCC_USB]    = { .clk_domain = APB1, .line_num = 23},
-#if defined(STM32_HIGH_DENSITY) || defined(STM32_XL_DENSITY)
-    [RCC_GPIOE]  = { .clk_domain = APB2, .line_num = 6 },
-    [RCC_GPIOF]  = { .clk_domain = APB2, .line_num = 7 },
-    [RCC_GPIOG]  = { .clk_domain = APB2, .line_num = 8 },
-    [RCC_UART4]  = { .clk_domain = APB1, .line_num = 19 },
-    [RCC_UART5]  = { .clk_domain = APB1, .line_num = 20 },
-    [RCC_TIMER5] = { .clk_domain = APB1, .line_num = 3 },
-    [RCC_TIMER6] = { .clk_domain = APB1, .line_num = 4 },
-    [RCC_TIMER7] = { .clk_domain = APB1, .line_num = 5 },
-    [RCC_TIMER8] = { .clk_domain = APB2, .line_num = 13 },
-    [RCC_FSMC]   = { .clk_domain = AHB,  .line_num = 8 },
-    [RCC_DAC]    = { .clk_domain = APB1, .line_num = 29 },
-    [RCC_DMA2]   = { .clk_domain = AHB,  .line_num = 1 },
-    [RCC_SDIO]   = { .clk_domain = AHB,  .line_num = 10 },
-    [RCC_SPI3]   = { .clk_domain = APB1, .line_num = 15 },
-#endif
-#ifdef STM32_XL_DENSITY
-    [RCC_TIMER9]  = { .clk_domain = APB2, .line_num = 19 },
-    [RCC_TIMER10] = { .clk_domain = APB2, .line_num = 20 },
-    [RCC_TIMER11] = { .clk_domain = APB2, .line_num = 21 },
-    [RCC_TIMER12] = { .clk_domain = APB1, .line_num = 6 },
-    [RCC_TIMER13] = { .clk_domain = APB1, .line_num = 7 },
-    [RCC_TIMER14] = { .clk_domain = APB1, .line_num = 8 },
-#endif
-	[RCC_CAN]	= { .clk_domain = APB1, .line_num = 25 },	//! JMD after X893
-};
-
-__deprecated
-void rcc_clk_init(rcc_sysclk_src sysclk_src,
-                  rcc_pllsrc pll_src,
-                  rcc_pll_multiplier pll_mul) {
-    /* Assume that we're going to clock the chip off the PLL, fed by
-     * the HSE */
-    ASSERT(sysclk_src == RCC_CLKSRC_PLL &&
-           pll_src    == RCC_PLLSRC_HSE);
-
-    RCC_BASE->CFGR = pll_src | pll_mul | (0x3<<22);
-
-    /* Turn on, and wait for, HSE. */
-    rcc_turn_on_clk(RCC_CLK_HSE);
-    while (!rcc_is_clk_ready(RCC_CLK_HSE))
-        ;
-
-    /* Do the same for the main PLL. */
-    rcc_turn_on_clk(RCC_CLK_PLL);
-    while(!rcc_is_clk_ready(RCC_CLK_PLL))
-        ;
-
-    /* Finally, switch over to the PLL. */
-    rcc_switch_sysclk(RCC_CLKSRC_PLL);
-}
-
-/* pll_cfg->data must point to a valid struct stm32f1_rcc_pll_data. */
-void rcc_configure_pll(rcc_pll_cfg *pll_cfg) {
-    stm32f1_rcc_pll_data *data = pll_cfg->data;
-    rcc_pll_multiplier pll_mul = data->pll_mul;
-    uint32 cfgr;
-    /* Check that the PLL is disabled. */
-    ASSERT_FAULT(!rcc_is_clk_on(RCC_CLK_PLL));
-
-    cfgr = RCC_BASE->CFGR;
-    cfgr &= ~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMUL);
-    cfgr |= pll_cfg->pllsrc | pll_mul;
-
-    RCC_BASE->CFGR = cfgr;
-}
-
-void rcc_clk_enable(rcc_clk_id id) {
-    static __io uint32* enable_regs[] = {
-        [APB1] = &RCC_BASE->APB1ENR,
-        [APB2] = &RCC_BASE->APB2ENR,
-        [AHB] = &RCC_BASE->AHBENR,
-    };
-    rcc_do_clk_enable(enable_regs, id);
-}
-
-void rcc_reset_dev(rcc_clk_id id) {
-    static __io uint32* reset_regs[] = {
-        [APB1] = &RCC_BASE->APB1RSTR,
-        [APB2] = &RCC_BASE->APB2RSTR,
-    };
-    rcc_do_reset_dev(reset_regs, id);
-}
-
-void rcc_set_prescaler(rcc_prescaler prescaler, uint32 divider) {
-    static const uint32 masks[] = {
-        [RCC_PRESCALER_AHB] = RCC_CFGR_HPRE,
-        [RCC_PRESCALER_APB1] = RCC_CFGR_PPRE1,
-        [RCC_PRESCALER_APB2] = RCC_CFGR_PPRE2,
-        [RCC_PRESCALER_USB] = RCC_CFGR_USBPRE,
-        [RCC_PRESCALER_ADC] = RCC_CFGR_ADCPRE,
-    };
-    rcc_do_set_prescaler(masks, prescaler, divider);
-}
-
-void rcc_clk_disable(rcc_clk_id id) {
-    static __io uint32* enable_regs[] = {
-        [APB1] = &RCC_BASE->APB1ENR,
-        [APB2] = &RCC_BASE->APB2ENR,
-        [AHB] = &RCC_BASE->AHBENR,
-    };
-    rcc_do_clk_disable(enable_regs, id);
-}
\ No newline at end of file
diff --git a/STM32F1/libraries/usb.c b/STM32F1/libraries/usb.c
deleted file mode 100644
index f7965351a..000000000
--- a/STM32F1/libraries/usb.c
+++ /dev/null
@@ -1,402 +0,0 @@
-/******************************************************************************
- * The MIT License
- *
- * Copyright (c) 2010 LeafLabs LLC.
- *
- * Permission is hereby granted, free of charge, to any person
- * obtaining a copy of this software and associated documentation
- * files (the "Software"), to deal in the Software without
- * restriction, including without limitation the rights to use, copy,
- * modify, merge, publish, distribute, sublicense, and/or sell copies
- * of the Software, and to permit persons to whom the Software is
- * furnished to do so, subject to the following conditions:
- *
- * The above copyright notice and this permission notice shall be included in
- * all copies or substantial portions of the Software.
- *
- * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
- * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
- * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
- * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
- * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
- * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
- * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
- * SOFTWARE.
- *****************************************************************************/
-
-/**
- * @file libmaple/usb/stm32f1/usb.c
- * @brief USB support.
- *
- * This is a mess.
- */
-
-#include <libmaple/usb.h>
-
-#include <libmaple/libmaple.h>
-#include <libmaple/rcc.h>
-
-/* Private headers */
-#include "usb_reg_map.h"
-#include "usb_lib_globals.h"
-
-/* usb_lib headers */
-#include "usb_type.h"
-#include "usb_core.h"
-
-static void dispatch_ctr_lp(void);
-
-/*
- * usb_lib/ globals
- */
-
-uint16 SaveTState;              /* caches TX status for later use */
-uint16 SaveRState;              /* caches RX status for later use */
-
-/*
- * Other state
- */
-
-typedef enum {
-    RESUME_EXTERNAL,
-    RESUME_INTERNAL,
-    RESUME_LATER,
-    RESUME_WAIT,
-    RESUME_START,
-    RESUME_ON,
-    RESUME_OFF,
-    RESUME_ESOF
-} RESUME_STATE;
-
-struct {
-    volatile RESUME_STATE eState;
-    volatile uint8 bESOFcnt;
-} ResumeS;
-
-static usblib_dev usblib = {
-    .irq_mask = USB_ISR_MSK,
-    .state = USB_UNCONNECTED,
-    .prevState = USB_UNCONNECTED,
-    .clk_id = RCC_USB,
-};
-usblib_dev *USBLIB = &usblib;
-
-/*
- * Routines
- */
-
-void usb_init_usblib(usblib_dev *dev,
-                     void (**ep_int_in)(void),
-                     void (**ep_int_out)(void)) {
-    rcc_clk_enable(dev->clk_id);
-
-    dev->ep_int_in = ep_int_in;
-    dev->ep_int_out = ep_int_out;
-
-    /* usb_lib/ declares both and then assumes that pFoo points to Foo
-     * (even though the names don't always match), which is stupid for
-     * all of the obvious reasons, but whatever.  Here we are. */
-    pInformation = &Device_Info;
-    pProperty = &Device_Property;
-    pUser_Standard_Requests = &User_Standard_Requests;
-
-    pInformation->ControlState = 2; /* FIXME [0.0.12] use
-                                       CONTROL_STATE enumerator */
-    pProperty->Init();
-}
-
-static void usb_suspend(void) {
-    uint16 cntr;
-
-    /* TODO decide if read/modify/write is really what we want
-     * (e.g. usb_resume_init() reconfigures CNTR). */
-    cntr = USB_BASE->CNTR;
-    cntr |= USB_CNTR_FSUSP;
-    USB_BASE->CNTR = cntr;
-    cntr |= USB_CNTR_LP_MODE;
-    USB_BASE->CNTR = cntr;
-
-    USBLIB->prevState = USBLIB->state;
-    USBLIB->state = USB_SUSPENDED;
-}
-
-static void usb_resume_init(void) {
-    uint16 cntr;
-
-    cntr = USB_BASE->CNTR;
-    cntr &= ~USB_CNTR_LP_MODE;
-    USB_BASE->CNTR = cntr;
-
-    /* Enable interrupt lines */
-    USB_BASE->CNTR = USB_ISR_MSK;
-}
-
-static void usb_resume(RESUME_STATE eResumeSetVal) {
-    uint16 cntr;
-
-    if (eResumeSetVal != RESUME_ESOF) {
-        ResumeS.eState = eResumeSetVal;
-    }
-
-    switch (ResumeS.eState) {
-    case RESUME_EXTERNAL:
-        usb_resume_init();
-        ResumeS.eState = RESUME_OFF;
-        USBLIB->state = USBLIB->prevState;
-        break;
-    case RESUME_INTERNAL:
-        usb_resume_init();
-        ResumeS.eState = RESUME_START;
-        break;
-    case RESUME_LATER:
-        ResumeS.bESOFcnt = 2;
-        ResumeS.eState = RESUME_WAIT;
-        break;
-    case RESUME_WAIT:
-        ResumeS.bESOFcnt--;
-        if (ResumeS.bESOFcnt == 0) {
-            ResumeS.eState = RESUME_START;
-        }
-        break;
-    case RESUME_START:
-        cntr = USB_BASE->CNTR;
-        cntr |= USB_CNTR_RESUME;
-        USB_BASE->CNTR = cntr;
-        ResumeS.eState = RESUME_ON;
-        ResumeS.bESOFcnt = 10;
-        break;
-    case RESUME_ON:
-        ResumeS.bESOFcnt--;
-        if (ResumeS.bESOFcnt == 0) {
-            cntr = USB_BASE->CNTR;
-            cntr &= ~USB_CNTR_RESUME;
-            USB_BASE->CNTR = cntr;
-            USBLIB->state = USBLIB->prevState;
-            ResumeS.eState = RESUME_OFF;
-        }
-        break;
-    case RESUME_OFF:
-    case RESUME_ESOF:
-    default:
-        ResumeS.eState = RESUME_OFF;
-        break;
-    }
-}
-
-// JMD : default ISRs of CAN, to be overridden if HardwareCAN library is used in sketch
-void __attribute__((weak)) USB_HP_CAN_TX_IRQHandler(void) 
-{ ; }      // Dummy ISR
-
-void __irq_usb_hp_can_tx(void)
-{
-  USB_HP_CAN_TX_IRQHandler () ;
-}
-
-uint8 __attribute__((weak)) CAN_RX0_IRQ_Handler(void)
-{ return 0 ; }      // Dummy ISR 
-
-#define SUSPEND_ENABLED 1
-void __irq_usb_lp_can_rx0(void) {
-    uint16 istr = USB_BASE->ISTR;
-
-	if (CAN_RX0_IRQ_Handler())			//! JMD : Call to CAN ISR, returns 1 CAN is active
-		return;							//! JMD
-
-    /* Use USB_ISR_MSK to only include code for bits we care about. */
-
-#if (USB_ISR_MSK & USB_ISTR_RESET)
-    if (istr & USB_ISTR_RESET & USBLIB->irq_mask) {
-        USB_BASE->ISTR = ~USB_ISTR_RESET;
-        pProperty->Reset();
-    }
-#endif
-
-#if (USB_ISR_MSK & USB_ISTR_PMAOVR)
-    if (istr & ISTR_PMAOVR & USBLIB->irq_mask) {
-        USB_BASE->ISTR = ~USB_ISTR_PMAOVR;
-    }
-#endif
-
-#if (USB_ISR_MSK & USB_ISTR_ERR)
-    if (istr & USB_ISTR_ERR & USBLIB->irq_mask) {
-        USB_BASE->ISTR = ~USB_ISTR_ERR;
-    }
-#endif
-
-#if (USB_ISR_MSK & USB_ISTR_WKUP)
-    if (istr & USB_ISTR_WKUP & USBLIB->irq_mask) {
-        USB_BASE->ISTR = ~(USB_ISTR_WKUP | USB_ISTR_SUSP);
-        usb_resume(RESUME_EXTERNAL);
-    }
-#endif
-
-#if (USB_ISR_MSK & USB_ISTR_SUSP)
-    if (istr & USB_ISTR_SUSP & USBLIB->irq_mask) {
-        /* check if SUSPEND is possible */
-        if (SUSPEND_ENABLED) {
-            usb_suspend();
-        } else {
-            /* if not possible then resume after xx ms */
-            usb_resume(RESUME_LATER);
-        }
-        /* clear of the ISTR bit must be done after setting of CNTR_FSUSP */
-        USB_BASE->ISTR = ~(USB_ISTR_WKUP | USB_ISTR_SUSP);
-    }
-#endif
-
-#if (USB_ISR_MSK & USB_ISTR_SOF)
-    if (istr & USB_ISTR_SOF & USBLIB->irq_mask) {
-        USB_BASE->ISTR = ~USB_ISTR_SOF;
-    }
-#endif
-
-#if (USB_ISR_MSK & USB_ISTR_ESOF)
-    if (istr & USB_ISTR_ESOF & USBLIB->irq_mask) {
-        USB_BASE->ISTR = ~USB_ISTR_ESOF;
-        /* resume handling timing is made with ESOFs */
-        usb_resume(RESUME_ESOF); /* request without change of the machine state */
-    }
-#endif
-
-    /*
-     * Service the correct transfer interrupt.
-     */
-
-#if (USB_ISR_MSK & USB_ISTR_CTR)
-    if (istr & USB_ISTR_CTR & USBLIB->irq_mask) {
-        dispatch_ctr_lp();
-    }
-#endif
-}
-
-/*
- * Auxiliary routines
- */
-
-static inline uint8 dispatch_endpt_zero(uint16 istr_dir);
-static inline void dispatch_endpt(uint8 ep);
-static inline void set_rx_tx_status0(uint16 rx, uint16 tx);
-
-static void handle_setup0(void);
-static void handle_in0(void);
-static void handle_out0(void);
-
-static void dispatch_ctr_lp() {
-    uint16 istr;
-    while (((istr = USB_BASE->ISTR) & USB_ISTR_CTR) != 0) {
-        /* TODO WTF, figure this out: RM0008 says CTR is read-only,
-         * but ST's firmware claims it's clear-only, and emphasizes
-         * the importance of clearing it in more than one place. */
-        USB_BASE->ISTR = ~USB_ISTR_CTR;
-        uint8 ep_id = istr & USB_ISTR_EP_ID;
-        if (ep_id == 0) {
-            /* TODO figure out why it's OK to break out of the loop
-             * once we're done serving endpoint zero, but not okay if
-             * there are multiple nonzero endpoint transfers to
-             * handle. */
-            if (dispatch_endpt_zero(istr & USB_ISTR_DIR)) {
-                return;
-            }
-        } else {
-            dispatch_endpt(ep_id);
-        }
-    }
-}
-
-/* FIXME Dataflow on endpoint 0 RX/TX status is based off of ST's
- * code, and is ugly/confusing in its use of SaveRState/SaveTState.
- * Fixing this requires filling in handle_in0(), handle_setup0(),
- * handle_out0(). */
-static inline uint8 dispatch_endpt_zero(uint16 istr_dir) {
-    uint32 epr = (uint16)USB_BASE->EP[0];
-
-    if (!(epr & (USB_EP_CTR_TX | USB_EP_SETUP | USB_EP_CTR_RX))) {
-        return 0;
-    }
-
-    /* Cache RX/TX statuses in SaveRState/SaveTState, respectively.
-     * The various handle_foo0() may clobber these values
-     * before we reset them at the end of this routine. */
-    SaveRState = epr & USB_EP_STAT_RX;
-    SaveTState = epr & USB_EP_STAT_TX;
-
-    /* Set actual RX/TX statuses to NAK while we're thinking */
-    set_rx_tx_status0(USB_EP_STAT_RX_NAK, USB_EP_STAT_TX_NAK);
-
-    if (istr_dir == 0) {
-        /* ST RM0008: "If DIR bit=0, CTR_TX bit is set in the USB_EPnR
-         * register related to the interrupting endpoint.  The
-         * interrupting transaction is of IN type (data transmitted by
-         * the USB peripheral to the host PC)." */
-        ASSERT_FAULT(epr & USB_EP_CTR_TX);
-        usb_clear_ctr_tx(USB_EP0);
-        handle_in0();
-    } else {
-        /* RM0008: "If DIR bit=1, CTR_RX bit or both CTR_TX/CTR_RX
-         * are set in the USB_EPnR register related to the
-         * interrupting endpoint. The interrupting transaction is of
-         * OUT type (data received by the USB peripheral from the host
-         * PC) or two pending transactions are waiting to be
-         * processed."
-         *
-         * [mbolivar] Note how the following control flow (which
-         * replicates ST's) doesn't seem to actually handle both
-         * interrupts that are ostensibly pending when both CTR_RX and
-         * CTR_TX are set.
-         *
-         * TODO sort this mess out.
-         */
-        if (epr & USB_EP_CTR_TX) {
-            usb_clear_ctr_tx(USB_EP0);
-            handle_in0();
-        } else {                /* SETUP or CTR_RX */
-            /* SETUP is held constant while CTR_RX is set, so clear it
-             * either way */
-            usb_clear_ctr_rx(USB_EP0);
-            if (epr & USB_EP_SETUP) {
-                handle_setup0();
-            } else {            /* CTR_RX */
-                handle_out0();
-            }
-        }
-    }
-
-    set_rx_tx_status0(SaveRState, SaveTState);
-    return 1;
-}
-
-static inline void dispatch_endpt(uint8 ep) {
-    uint32 epr = USB_BASE->EP[ep];
-    /* If ISTR_CTR is set and the ISTR gave us this EP_ID to handle,
-     * then presumably at least one of CTR_RX and CTR_TX is set, but
-     * again, ST's control flow allows for the possibility of neither.
-     *
-     * TODO try to find out if neither being set is possible. */
-    if (epr & USB_EP_CTR_RX) {
-        usb_clear_ctr_rx(ep);
-        (USBLIB->ep_int_out[ep - 1])();
-    }
-    if (epr & USB_EP_CTR_TX) {
-        usb_clear_ctr_tx(ep);
-        (USBLIB->ep_int_in[ep - 1])();
-    }
-}
-
-static inline void set_rx_tx_status0(uint16 rx, uint16 tx) {
-    usb_set_ep_rx_stat(USB_EP0, rx);
-    usb_set_ep_tx_stat(USB_EP0, tx);
-}
-
-/* TODO Rip out usb_lib/ dependency from the following functions: */
-
-static void handle_setup0(void) {
-    Setup0_Process();
-}
-
-static void handle_in0(void) {
-    In0_Process();
-}
-
-static void handle_out0(void) {
-    Out0_Process();
-}