From 8293d64dd2a1370660ba01bbdfc8486f25a3fde2 Mon Sep 17 00:00:00 2001 From: Michael Bear <38406045+mjbear@users.noreply.github.com> Date: Thu, 12 Feb 2026 21:02:16 -0500 Subject: [PATCH 1/5] Regenerate sros sh lag keys in alphabetical order --- tests/alcatel_sros/show_lag/show_lag.yml | 200 +++++++++++------------ 1 file changed, 100 insertions(+), 100 deletions(-) diff --git a/tests/alcatel_sros/show_lag/show_lag.yml b/tests/alcatel_sros/show_lag/show_lag.yml index b3cf0f7ae8..a0a6ef43da 100644 --- a/tests/alcatel_sros/show_lag/show_lag.yml +++ b/tests/alcatel_sros/show_lag/show_lag.yml @@ -1,219 +1,219 @@ --- parsed_sample: - - lag_id: "1" - adm: "up" + - adm: "up" + lag_id: "1" + mc_act_stdby: "N/A" opr: "up" - weighted: "No" threshold: "0" up_count: "2" + weighted: "No" + - adm: "up" + lag_id: "2" mc_act_stdby: "N/A" - - lag_id: "2" - adm: "up" opr: "up" - weighted: "No" threshold: "0" up_count: "2" + weighted: "No" + - adm: "up" + lag_id: "3" mc_act_stdby: "N/A" - - lag_id: "3" - adm: "up" opr: "up" - weighted: "No" threshold: "0" up_count: "1" - mc_act_stdby: "N/A" - - lag_id: "4" - adm: "down" - opr: "down" weighted: "No" - threshold: "0" - up_count: "0" + - adm: "down" + lag_id: "4" mc_act_stdby: "N/A" - - lag_id: "5" - adm: "down" opr: "down" - weighted: "No" threshold: "0" up_count: "0" + weighted: "No" + - adm: "down" + lag_id: "5" mc_act_stdby: "N/A" - - lag_id: "10" - adm: "down" opr: "down" - weighted: "No" threshold: "0" up_count: "0" + weighted: "No" + - adm: "down" + lag_id: "10" mc_act_stdby: "N/A" - - lag_id: "20" - adm: "up" opr: "down" - weighted: "No" threshold: "0" up_count: "0" + weighted: "No" + - adm: "up" + lag_id: "20" mc_act_stdby: "standby" - - lag_id: "70" - adm: "down" opr: "down" - weighted: "No" threshold: "0" up_count: "0" + weighted: "No" + - adm: "down" + lag_id: "70" mc_act_stdby: "N/A" - - lag_id: "80" - adm: "up" opr: "down" - weighted: "No" threshold: "0" up_count: "0" + weighted: "No" + - adm: "up" + lag_id: "80" mc_act_stdby: "N/A" - - lag_id: "90" - adm: "down" opr: "down" - weighted: "No" threshold: "0" up_count: "0" - mc_act_stdby: "N/A" - - lag_id: "100" - adm: "up" - opr: "up" weighted: "No" + - adm: "down" + lag_id: "90" + mc_act_stdby: "N/A" + opr: "down" threshold: "0" - up_count: "1" + up_count: "0" + weighted: "No" + - adm: "up" + lag_id: "100" mc_act_stdby: "N/A" - - lag_id: "101" - adm: "up" opr: "up" - weighted: "No" threshold: "0" up_count: "1" + weighted: "No" + - adm: "up" + lag_id: "101" mc_act_stdby: "N/A" - - lag_id: "102" - adm: "up" opr: "up" - weighted: "No" threshold: "0" up_count: "1" + weighted: "No" + - adm: "up" + lag_id: "102" mc_act_stdby: "N/A" - - lag_id: "103" - adm: "up" opr: "up" - weighted: "No" threshold: "0" up_count: "1" + weighted: "No" + - adm: "up" + lag_id: "103" mc_act_stdby: "active" - - lag_id: "104" - adm: "up" opr: "up" - weighted: "No" threshold: "0" up_count: "1" + weighted: "No" + - adm: "up" + lag_id: "104" mc_act_stdby: "N/A" - - lag_id: "105" - adm: "up" opr: "up" - weighted: "No" threshold: "0" up_count: "1" + weighted: "No" + - adm: "up" + lag_id: "105" mc_act_stdby: "N/A" - - lag_id: "106" - adm: "up" opr: "up" - weighted: "No" threshold: "0" up_count: "1" + weighted: "No" + - adm: "up" + lag_id: "106" mc_act_stdby: "N/A" - - lag_id: "107" - adm: "up" opr: "up" - weighted: "No" threshold: "0" up_count: "1" + weighted: "No" + - adm: "up" + lag_id: "107" mc_act_stdby: "N/A" - - lag_id: "108" - adm: "up" opr: "up" - weighted: "No" threshold: "0" up_count: "1" + weighted: "No" + - adm: "up" + lag_id: "108" mc_act_stdby: "N/A" - - lag_id: "109" - adm: "up" opr: "up" - weighted: "No" threshold: "0" up_count: "1" + weighted: "No" + - adm: "up" + lag_id: "109" mc_act_stdby: "N/A" - - lag_id: "110" - adm: "up" opr: "up" - weighted: "No" threshold: "0" up_count: "1" + weighted: "No" + - adm: "up" + lag_id: "110" mc_act_stdby: "active" - - lag_id: "111" - adm: "up" opr: "up" - weighted: "No" threshold: "0" up_count: "1" + weighted: "No" + - adm: "up" + lag_id: "111" mc_act_stdby: "N/A" - - lag_id: "112" - adm: "up" opr: "up" - weighted: "No" threshold: "0" up_count: "1" + weighted: "No" + - adm: "up" + lag_id: "112" mc_act_stdby: "N/A" - - lag_id: "114" - adm: "up" opr: "up" - weighted: "No" threshold: "0" up_count: "1" + weighted: "No" + - adm: "up" + lag_id: "114" mc_act_stdby: "N/A" - - lag_id: "115" - adm: "up" opr: "up" - weighted: "No" threshold: "0" up_count: "1" + weighted: "No" + - adm: "up" + lag_id: "115" mc_act_stdby: "N/A" - - lag_id: "120" - adm: "up" opr: "up" + threshold: "0" + up_count: "1" weighted: "No" + - adm: "up" + lag_id: "120" + mc_act_stdby: "N/A" + opr: "up" threshold: "0" up_count: "1" + weighted: "No" + - adm: "down" + lag_id: "124" mc_act_stdby: "N/A" - - lag_id: "124" - adm: "down" opr: "down" - weighted: "No" threshold: "0" up_count: "0" + weighted: "No" + - adm: "up" + lag_id: "140" mc_act_stdby: "N/A" - - lag_id: "140" - adm: "up" opr: "up" - weighted: "No" threshold: "0" up_count: "1" + weighted: "No" + - adm: "down" + lag_id: "150" mc_act_stdby: "N/A" - - lag_id: "150" - adm: "down" opr: "down" - weighted: "No" threshold: "0" up_count: "0" - mc_act_stdby: "N/A" - - lag_id: "153" - adm: "up" - opr: "up" weighted: "No" + - adm: "up" + lag_id: "153" + mc_act_stdby: "active" + opr: "up" threshold: "0" up_count: "1" - mc_act_stdby: "active" - - lag_id: "180" - adm: "down" - opr: "down" weighted: "No" + - adm: "down" + lag_id: "180" + mc_act_stdby: "N/A" + opr: "down" threshold: "0" up_count: "0" - mc_act_stdby: "N/A" + weighted: "No" From 42775081270e81edecb4f7c542e1e4976c48303d Mon Sep 17 00:00:00 2001 From: Michael Bear <38406045+mjbear@users.noreply.github.com> Date: Thu, 12 Feb 2026 21:07:13 -0500 Subject: [PATCH 2/5] Add error directive and patterns to Start state --- ntc_templates/templates/alcatel_sros_show_lag.textfsm | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/ntc_templates/templates/alcatel_sros_show_lag.textfsm b/ntc_templates/templates/alcatel_sros_show_lag.textfsm index 5d2226814b..0a2b5c47c8 100644 --- a/ntc_templates/templates/alcatel_sros_show_lag.textfsm +++ b/ntc_templates/templates/alcatel_sros_show_lag.textfsm @@ -7,7 +7,12 @@ Value UP_COUNT (\d+) Value MC_ACT_STDBY (N/A|active|standby) Start + ^==+ + ^Lag\s+Data\s*$$ + ^Lag-id\s+Adm\s+Opr\s+Weighted\s+Threshold\s+Up-Count\s+MC\s+Act/Stdby\s*$$ + ^\s+name\s*$$ ^----------- -> Lag + ^. -> Error Lag ^${LAG_ID}\s+${ADM}\s+${OPR}\s+${WEIGHTED}\s+${THRESHOLD}\s+${UP_COUNT}\s+${MC_ACT_STDBY}(\s|$$) -> Record From 947b48e5492433cb4387cef9dc20c994518e22c2 Mon Sep 17 00:00:00 2001 From: Michael Bear <38406045+mjbear@users.noreply.github.com> Date: Thu, 12 Feb 2026 21:09:07 -0500 Subject: [PATCH 3/5] Add basic matching for lag names --- .../templates/alcatel_sros_show_lag.textfsm | 1 + tests/alcatel_sros/show_lag/show_lag_name.raw | 22 ++++++++++ tests/alcatel_sros/show_lag/show_lag_name.yml | 44 +++++++++++++++++++ 3 files changed, 67 insertions(+) create mode 100644 tests/alcatel_sros/show_lag/show_lag_name.raw create mode 100644 tests/alcatel_sros/show_lag/show_lag_name.yml diff --git a/ntc_templates/templates/alcatel_sros_show_lag.textfsm b/ntc_templates/templates/alcatel_sros_show_lag.textfsm index 0a2b5c47c8..ce3bb0b169 100644 --- a/ntc_templates/templates/alcatel_sros_show_lag.textfsm +++ b/ntc_templates/templates/alcatel_sros_show_lag.textfsm @@ -16,6 +16,7 @@ Start Lag ^${LAG_ID}\s+${ADM}\s+${OPR}\s+${WEIGHTED}\s+${THRESHOLD}\s+${UP_COUNT}\s+${MC_ACT_STDBY}(\s|$$) -> Record + ^\s+lag-\S+\s*$$ ^\s*$$ ^----------- ^=========== diff --git a/tests/alcatel_sros/show_lag/show_lag_name.raw b/tests/alcatel_sros/show_lag/show_lag_name.raw new file mode 100644 index 0000000000..f206022fdc --- /dev/null +++ b/tests/alcatel_sros/show_lag/show_lag_name.raw @@ -0,0 +1,22 @@ + +=============================================================================== +Lag Data +=============================================================================== +Lag-id Adm Opr Weighted Threshold Up-Count MC Act/Stdby + name +------------------------------------------------------------------------------- +1 up up No 0 1 N/A + lag-1 +2 up up No 0 1 N/A + lag-2 +19 up up No 0 2 N/A + lag-19 +20 down down No 0 0 N/A + lag-20 +50 down down No 0 0 N/A + lag-myname +101 up up No 0 1 N/A + lag-101 +------------------------------------------------------------------------------- +Total Lag-ids: 6 Single Chassis: 6 MC Act: 0 MC Stdby: 0 +=============================================================================== diff --git a/tests/alcatel_sros/show_lag/show_lag_name.yml b/tests/alcatel_sros/show_lag/show_lag_name.yml new file mode 100644 index 0000000000..be560552ba --- /dev/null +++ b/tests/alcatel_sros/show_lag/show_lag_name.yml @@ -0,0 +1,44 @@ +--- +parsed_sample: + - adm: "up" + lag_id: "1" + mc_act_stdby: "N/A" + opr: "up" + threshold: "0" + up_count: "1" + weighted: "No" + - adm: "up" + lag_id: "2" + mc_act_stdby: "N/A" + opr: "up" + threshold: "0" + up_count: "1" + weighted: "No" + - adm: "up" + lag_id: "19" + mc_act_stdby: "N/A" + opr: "up" + threshold: "0" + up_count: "2" + weighted: "No" + - adm: "down" + lag_id: "20" + mc_act_stdby: "N/A" + opr: "down" + threshold: "0" + up_count: "0" + weighted: "No" + - adm: "down" + lag_id: "50" + mc_act_stdby: "N/A" + opr: "down" + threshold: "0" + up_count: "0" + weighted: "No" + - adm: "up" + lag_id: "101" + mc_act_stdby: "N/A" + opr: "up" + threshold: "0" + up_count: "1" + weighted: "No" From 8c99e9707f795dcf0a106bbb50f607e7721a8deb Mon Sep 17 00:00:00 2001 From: Michael Bear <38406045+mjbear@users.noreply.github.com> Date: Thu, 12 Feb 2026 21:28:31 -0500 Subject: [PATCH 4/5] Add support for capturing sros lag name --- .../templates/alcatel_sros_show_lag.textfsm | 6 ++-- tests/alcatel_sros/show_lag/show_lag.yml | 31 +++++++++++++++++++ tests/alcatel_sros/show_lag/show_lag_name.yml | 6 ++++ 3 files changed, 41 insertions(+), 2 deletions(-) diff --git a/ntc_templates/templates/alcatel_sros_show_lag.textfsm b/ntc_templates/templates/alcatel_sros_show_lag.textfsm index ce3bb0b169..23dfb50cdc 100644 --- a/ntc_templates/templates/alcatel_sros_show_lag.textfsm +++ b/ntc_templates/templates/alcatel_sros_show_lag.textfsm @@ -5,6 +5,7 @@ Value WEIGHTED (Yes|No) Value THRESHOLD (\d+) Value UP_COUNT (\d+) Value MC_ACT_STDBY (N/A|active|standby) +Value LAG_NAME (lag-\S+) Start ^==+ @@ -15,8 +16,9 @@ Start ^. -> Error Lag - ^${LAG_ID}\s+${ADM}\s+${OPR}\s+${WEIGHTED}\s+${THRESHOLD}\s+${UP_COUNT}\s+${MC_ACT_STDBY}(\s|$$) -> Record - ^\s+lag-\S+\s*$$ + ^\d+\s+((up|down)\s+){2} -> Continue.Record + ^${LAG_ID}\s+${ADM}\s+${OPR}\s+${WEIGHTED}\s+${THRESHOLD}\s+${UP_COUNT}\s+${MC_ACT_STDBY}(\s|$$) + ^\s+${LAG_NAME}\s*$$ ^\s*$$ ^----------- ^=========== diff --git a/tests/alcatel_sros/show_lag/show_lag.yml b/tests/alcatel_sros/show_lag/show_lag.yml index a0a6ef43da..07fec9a0fa 100644 --- a/tests/alcatel_sros/show_lag/show_lag.yml +++ b/tests/alcatel_sros/show_lag/show_lag.yml @@ -2,6 +2,7 @@ parsed_sample: - adm: "up" lag_id: "1" + lag_name: "" mc_act_stdby: "N/A" opr: "up" threshold: "0" @@ -9,6 +10,7 @@ parsed_sample: weighted: "No" - adm: "up" lag_id: "2" + lag_name: "" mc_act_stdby: "N/A" opr: "up" threshold: "0" @@ -16,6 +18,7 @@ parsed_sample: weighted: "No" - adm: "up" lag_id: "3" + lag_name: "" mc_act_stdby: "N/A" opr: "up" threshold: "0" @@ -23,6 +26,7 @@ parsed_sample: weighted: "No" - adm: "down" lag_id: "4" + lag_name: "" mc_act_stdby: "N/A" opr: "down" threshold: "0" @@ -30,6 +34,7 @@ parsed_sample: weighted: "No" - adm: "down" lag_id: "5" + lag_name: "" mc_act_stdby: "N/A" opr: "down" threshold: "0" @@ -37,6 +42,7 @@ parsed_sample: weighted: "No" - adm: "down" lag_id: "10" + lag_name: "" mc_act_stdby: "N/A" opr: "down" threshold: "0" @@ -44,6 +50,7 @@ parsed_sample: weighted: "No" - adm: "up" lag_id: "20" + lag_name: "" mc_act_stdby: "standby" opr: "down" threshold: "0" @@ -51,6 +58,7 @@ parsed_sample: weighted: "No" - adm: "down" lag_id: "70" + lag_name: "" mc_act_stdby: "N/A" opr: "down" threshold: "0" @@ -58,6 +66,7 @@ parsed_sample: weighted: "No" - adm: "up" lag_id: "80" + lag_name: "" mc_act_stdby: "N/A" opr: "down" threshold: "0" @@ -65,6 +74,7 @@ parsed_sample: weighted: "No" - adm: "down" lag_id: "90" + lag_name: "" mc_act_stdby: "N/A" opr: "down" threshold: "0" @@ -72,6 +82,7 @@ parsed_sample: weighted: "No" - adm: "up" lag_id: "100" + lag_name: "" mc_act_stdby: "N/A" opr: "up" threshold: "0" @@ -79,6 +90,7 @@ parsed_sample: weighted: "No" - adm: "up" lag_id: "101" + lag_name: "" mc_act_stdby: "N/A" opr: "up" threshold: "0" @@ -86,6 +98,7 @@ parsed_sample: weighted: "No" - adm: "up" lag_id: "102" + lag_name: "" mc_act_stdby: "N/A" opr: "up" threshold: "0" @@ -93,6 +106,7 @@ parsed_sample: weighted: "No" - adm: "up" lag_id: "103" + lag_name: "" mc_act_stdby: "active" opr: "up" threshold: "0" @@ -100,6 +114,7 @@ parsed_sample: weighted: "No" - adm: "up" lag_id: "104" + lag_name: "" mc_act_stdby: "N/A" opr: "up" threshold: "0" @@ -107,6 +122,7 @@ parsed_sample: weighted: "No" - adm: "up" lag_id: "105" + lag_name: "" mc_act_stdby: "N/A" opr: "up" threshold: "0" @@ -114,6 +130,7 @@ parsed_sample: weighted: "No" - adm: "up" lag_id: "106" + lag_name: "" mc_act_stdby: "N/A" opr: "up" threshold: "0" @@ -121,6 +138,7 @@ parsed_sample: weighted: "No" - adm: "up" lag_id: "107" + lag_name: "" mc_act_stdby: "N/A" opr: "up" threshold: "0" @@ -128,6 +146,7 @@ parsed_sample: weighted: "No" - adm: "up" lag_id: "108" + lag_name: "" mc_act_stdby: "N/A" opr: "up" threshold: "0" @@ -135,6 +154,7 @@ parsed_sample: weighted: "No" - adm: "up" lag_id: "109" + lag_name: "" mc_act_stdby: "N/A" opr: "up" threshold: "0" @@ -142,6 +162,7 @@ parsed_sample: weighted: "No" - adm: "up" lag_id: "110" + lag_name: "" mc_act_stdby: "active" opr: "up" threshold: "0" @@ -149,6 +170,7 @@ parsed_sample: weighted: "No" - adm: "up" lag_id: "111" + lag_name: "" mc_act_stdby: "N/A" opr: "up" threshold: "0" @@ -156,6 +178,7 @@ parsed_sample: weighted: "No" - adm: "up" lag_id: "112" + lag_name: "" mc_act_stdby: "N/A" opr: "up" threshold: "0" @@ -163,6 +186,7 @@ parsed_sample: weighted: "No" - adm: "up" lag_id: "114" + lag_name: "" mc_act_stdby: "N/A" opr: "up" threshold: "0" @@ -170,6 +194,7 @@ parsed_sample: weighted: "No" - adm: "up" lag_id: "115" + lag_name: "" mc_act_stdby: "N/A" opr: "up" threshold: "0" @@ -177,6 +202,7 @@ parsed_sample: weighted: "No" - adm: "up" lag_id: "120" + lag_name: "" mc_act_stdby: "N/A" opr: "up" threshold: "0" @@ -184,6 +210,7 @@ parsed_sample: weighted: "No" - adm: "down" lag_id: "124" + lag_name: "" mc_act_stdby: "N/A" opr: "down" threshold: "0" @@ -191,6 +218,7 @@ parsed_sample: weighted: "No" - adm: "up" lag_id: "140" + lag_name: "" mc_act_stdby: "N/A" opr: "up" threshold: "0" @@ -198,6 +226,7 @@ parsed_sample: weighted: "No" - adm: "down" lag_id: "150" + lag_name: "" mc_act_stdby: "N/A" opr: "down" threshold: "0" @@ -205,6 +234,7 @@ parsed_sample: weighted: "No" - adm: "up" lag_id: "153" + lag_name: "" mc_act_stdby: "active" opr: "up" threshold: "0" @@ -212,6 +242,7 @@ parsed_sample: weighted: "No" - adm: "down" lag_id: "180" + lag_name: "" mc_act_stdby: "N/A" opr: "down" threshold: "0" diff --git a/tests/alcatel_sros/show_lag/show_lag_name.yml b/tests/alcatel_sros/show_lag/show_lag_name.yml index be560552ba..b9f8ec326b 100644 --- a/tests/alcatel_sros/show_lag/show_lag_name.yml +++ b/tests/alcatel_sros/show_lag/show_lag_name.yml @@ -2,6 +2,7 @@ parsed_sample: - adm: "up" lag_id: "1" + lag_name: "lag-1" mc_act_stdby: "N/A" opr: "up" threshold: "0" @@ -9,6 +10,7 @@ parsed_sample: weighted: "No" - adm: "up" lag_id: "2" + lag_name: "lag-2" mc_act_stdby: "N/A" opr: "up" threshold: "0" @@ -16,6 +18,7 @@ parsed_sample: weighted: "No" - adm: "up" lag_id: "19" + lag_name: "lag-19" mc_act_stdby: "N/A" opr: "up" threshold: "0" @@ -23,6 +26,7 @@ parsed_sample: weighted: "No" - adm: "down" lag_id: "20" + lag_name: "lag-20" mc_act_stdby: "N/A" opr: "down" threshold: "0" @@ -30,6 +34,7 @@ parsed_sample: weighted: "No" - adm: "down" lag_id: "50" + lag_name: "lag-myname" mc_act_stdby: "N/A" opr: "down" threshold: "0" @@ -37,6 +42,7 @@ parsed_sample: weighted: "No" - adm: "up" lag_id: "101" + lag_name: "lag-101" mc_act_stdby: "N/A" opr: "up" threshold: "0" From 26327d0e47355e94f533a660c50794a948b3be52 Mon Sep 17 00:00:00 2001 From: Michael Bear <38406045+mjbear@users.noreply.github.com> Date: Thu, 12 Feb 2026 21:33:19 -0500 Subject: [PATCH 5/5] Adjusted separator and condensed states - The output is simple enough to utilize just a Start state resulting in reduced duplication - Simplify a repeating pattern for the separators - and = - Simplify the regex for whitespace at the end of a data line --- ntc_templates/templates/alcatel_sros_show_lag.textfsm | 11 +++-------- 1 file changed, 3 insertions(+), 8 deletions(-) diff --git a/ntc_templates/templates/alcatel_sros_show_lag.textfsm b/ntc_templates/templates/alcatel_sros_show_lag.textfsm index 23dfb50cdc..bb6074a15c 100644 --- a/ntc_templates/templates/alcatel_sros_show_lag.textfsm +++ b/ntc_templates/templates/alcatel_sros_show_lag.textfsm @@ -8,19 +8,14 @@ Value MC_ACT_STDBY (N/A|active|standby) Value LAG_NAME (lag-\S+) Start - ^==+ ^Lag\s+Data\s*$$ ^Lag-id\s+Adm\s+Opr\s+Weighted\s+Threshold\s+Up-Count\s+MC\s+Act/Stdby\s*$$ ^\s+name\s*$$ - ^----------- -> Lag - ^. -> Error - -Lag ^\d+\s+((up|down)\s+){2} -> Continue.Record - ^${LAG_ID}\s+${ADM}\s+${OPR}\s+${WEIGHTED}\s+${THRESHOLD}\s+${UP_COUNT}\s+${MC_ACT_STDBY}(\s|$$) + ^${LAG_ID}\s+${ADM}\s+${OPR}\s+${WEIGHTED}\s+${THRESHOLD}\s+${UP_COUNT}\s+${MC_ACT_STDBY}\s*$$ ^\s+${LAG_NAME}\s*$$ ^\s*$$ - ^----------- - ^=========== + ^===+ + ^---+ ^Total ^. -> Error