diff --git a/Mimasa7_V3/3.0/board.xml b/Mimasa7_V3/3.0/board.xml
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+ Mimas a7 Artix7 Board File Image
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+ 1.0
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+3.0
+Mimasa7_V3
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+ DDR3 board interface.
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+ Reset Button
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+ Secondary interface to communicate with ethernet phy.
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+ Primary interface to communicate with ethernet phy in RGMII mode.
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+ Onboard Reset Button
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+ DDR3 memory
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+ 3.3V Single-Ended 100MHz oscillator used as system clock on the board
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+ CPU Reset, Active High
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+ 128Mb flash provides non-volatile storage for use by the FPGA.
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+ USB-to-UART Bridge, which allows a connection to a host computer with a USB port
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+ PHY Ethernet on the board
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\ No newline at end of file
diff --git a/Mimasa7_V3/3.0/mig.prj b/Mimasa7_V3/3.0/mig.prj
new file mode 100644
index 0000000..e91a01e
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+++ b/Mimasa7_V3/3.0/mig.prj
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+
+
+ design_1_mig_7series_0_0
+ 1
+ 1
+ OFF
+ 1024
+ ON
+ Enabled
+ xc7a50t-fgg484/-1
+ 4.1
+ No Buffer
+ Use System Clock
+ ACTIVE HIGH
+ FALSE
+ 1
+ 50 Ohms
+ 0
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+ DDR3_SDRAM/Components/MT41J128M16XX-125
+ 2500
+ 1.8V
+ 4:1
+ 200
+ 0
+ 800
+ 1.000
+ 1
+ 1
+ 1
+ 1
+ 16
+ 1
+ 1
+ Disabled
+ Normal
+ 4
+ FALSE
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+ 14
+ 10
+ 3
+ 1.5V
+ 268435456
+ BANK_ROW_COLUMN
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+ 8 - Fixed
+ Sequential
+ 6
+ Normal
+ No
+ Slow Exit
+ Enable
+ RZQ/7
+ Disable
+ Enable
+ RZQ/4
+ 0
+ Disabled
+ Enabled
+ Output Buffer Enabled
+ Full Array
+ 5
+ Enabled
+ Normal
+ Dynamic ODT off
+ AXI
+
+ RD_PRI_REG
+ 28
+ 128
+ 4
+ 0
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+
+
diff --git a/Mimasa7_V3/3.0/part0_pins.xml b/Mimasa7_V3/3.0/part0_pins.xml
new file mode 100644
index 0000000..bdf0f71
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+++ b/Mimasa7_V3/3.0/part0_pins.xml
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diff --git a/Mimasa7_V3/3.0/preset.xml b/Mimasa7_V3/3.0/preset.xml
new file mode 100644
index 0000000..7e137e1
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+++ b/Mimasa7_V3/3.0/preset.xml
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