An error occurs when logical synthesis is performed using the Design Compiler

[RENEK-bool]

When I type the following command
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define_design_lib WORK -path ./work
analyze -format verilog {./rtl/mor1kx/rtl/verilog/mor1kx-defines.v
./rtl/mor1kx/rtl/verilog/mor1kx_dmmu.v
./rtl/mor1kx/rtl/verilog/mor1kx_execute_ctrl_cappuccino.v
./rtl/mor1kx/rtl/verilog/mor1kx_pic.v
./rtl/mor1kx/rtl/verilog/mor1kx_rf_cappuccino.v
./rtl/mor1kx/rtl/verilog/mor1kx_icache.v
./rtl/mor1kx/rtl/verilog/mor1kx_cpu_prontoespresso.v
./rtl/mor1kx/rtl/verilog/mor1kx_branch_prediction.v
./rtl/mor1kx/rtl/verilog/mor1kx_ctrl_prontoespresso.v
./rtl/mor1kx/rtl/verilog/mor1kx_cache_lru.v
./rtl/mor1kx/rtl/verilog/mor1kx_cpu.v
./rtl/mor1kx/rtl/verilog/mor1kx_execute_alu.v
./rtl/mor1kx/rtl/verilog/mor1kx_decode_execute_cappuccino.v
./rtl/mor1kx/rtl/verilog/mor1kx_ticktimer.v
./rtl/mor1kx/rtl/verilog/mor1kx_rf_espresso.v
./rtl/mor1kx/rtl/verilog/mor1kx_fetch_espresso.v
./rtl/mor1kx/rtl/verilog/mor1kx_decode.v
./rtl/mor1kx/rtl/verilog/mor1kx-sprs.v
./rtl/mor1kx/rtl/verilog/pfpu32/pfpu32_top.v
./rtl/mor1kx/rtl/verilog/pfpu32/pfpu32_f2i.v
./rtl/mor1kx/rtl/verilog/pfpu32/pfpu32_addsub.v
./rtl/mor1kx/rtl/verilog/pfpu32/pfpu32_cmp.v
./rtl/mor1kx/rtl/verilog/pfpu32/pfpu32_i2f.v
./rtl/mor1kx/rtl/verilog/pfpu32/pfpu32_muldiv.v
./rtl/mor1kx/rtl/verilog/pfpu32/pfpu32_rnd.v
./rtl/mor1kx/rtl/verilog/mor1kx_lsu_cappuccino.v
./rtl/mor1kx/rtl/verilog/mor1kx_dcache.v
./rtl/mor1kx/rtl/verilog/mor1kx_true_dpram_sclk.v
./rtl/mor1kx/rtl/verilog/mor1kx_wb_mux_espresso.v
./rtl/mor1kx/rtl/verilog/mor1kx_ctrl_espresso.v
./rtl/mor1kx/rtl/verilog/mor1kx_fetch_cappuccino.v
./rtl/mor1kx/rtl/verilog/mor1kx_cfgrs.v
./rtl/mor1kx/rtl/verilog/mor1kx_ctrl_cappuccino.v
./rtl/mor1kx/rtl/verilog/mor1kx_fetch_tcm_prontoespresso.v
./rtl/mor1kx/rtl/verilog/mor1kx_wb_mux_cappuccino.v
./rtl/mor1kx/rtl/verilog/mor1kx_fetch_prontoespresso.v
./rtl/mor1kx/rtl/verilog/mor1kx_bus_if_wb32.v
./rtl/mor1kx/rtl/verilog/mor1kx_immu.v
./rtl/mor1kx/rtl/verilog/mor1kx_store_buffer.v
./rtl/mor1kx/rtl/verilog/mor1kx_lsu_espresso.v
./rtl/mor1kx/rtl/verilog/mor1kx.v
./rtl/mor1kx/rtl/verilog/mor1kx_branch_predictor_simple.v
./rtl/mor1kx/rtl/verilog/mor1kx_branch_predictor_saturation_counter.v
./rtl/mor1kx/rtl/verilog/mor1kx_cpu_espresso.v
./rtl/mor1kx/rtl/verilog/mor1kx_simple_dpram_sclk.v
./rtl/mor1kx/rtl/verilog/mor1kx_cpu_cappuccino.v
}
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The Design Compiler displays the following error message
Error: ./rtl/mor1kx/rtl/verilog/mor1kx_cpu_prontoespresso.v:721: bad hierarchical name (mor1kx_rf_espresso). (VER-264)