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thommythomasophsauter
thommythomaso
authored and
phsauter
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Xilinx: Add simple FPGA flow for Genesys2
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‎Bender.yml‎

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- rtl/user_domain.sv
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# Level 3
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- rtl/croc_soc.sv
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# Level 4
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- target: not(fpga)
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files:
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# Level 0
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- rtl/croc_chip.sv
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# netlist for simulation
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files:
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- rtl/tb_croc_soc.sv
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- target: genesys2
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files:
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- xilinx/hw/croc_xilinx.sv
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- xilinx/hw/fan_ctrl.sv
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vendor_package:
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#################################
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# commonly used building blocks #

‎xilinx/.gitignore‎

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build
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out
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scripts/add_sources.genesys2.tcl
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‎xilinx/hw/croc_xilinx.sv‎

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// Copyright 2024 ETH Zurich and University of Bologna.
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// Solderpad Hardware License, Version 0.51, see LICENSE for details.
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// SPDX-License-Identifier: SHL-0.51
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//
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// Nicole Narr <narrn@student.ethz.ch>
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// Christopher Reinwardt <creinwar@student.ethz.ch>
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// Cyril Koenig <cykoenig@iis.ee.ethz.ch>
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// Yann Picod <ypicod@ethz.ch>
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// Paul Scheffler <paulsc@iis.ee.ethz.ch>
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// Philippe Sauter <phsauter@iis.ee.ethz.ch>
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`ifdef TARGET_GENESYS2
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`define USE_RESETN
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`define USE_JTAG_TRSTN
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`define USE_STATUS
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`define USE_SWITCHES
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`define USE_LEDS
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`define USE_FAN
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`define USE_VIO
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`endif
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`define ila(__name, __signal) \
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(* dont_touch = "yes" *) (* mark_debug = "true" *) logic [$bits(__signal)-1:0] __name; \
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assign __name = __signal;
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module croc_xilinx import croc_pkg::*; #(
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localparam int unsigned GpioCount = 4
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) (
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input logic sys_clk_p,
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input logic sys_clk_n,
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`ifdef USE_RESET
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input logic sys_reset,
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`endif
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`ifdef USE_RESETN
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input logic sys_resetn,
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`endif
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`ifdef USE_SWITCHES
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input logic fetch_en_i, // switch 7
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input logic [GpioCount-1:0] gpio_i, // switch 0-3
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`endif
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`ifdef USE_LEDS
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output logic [GpioCount-1:0] gpio_o,
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`endif
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`ifdef USE_STATUS
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output logic status_o,
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`endif
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input logic jtag_tck_i,
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input logic jtag_tms_i,
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input logic jtag_tdi_i,
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output logic jtag_tdo_o,
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`ifdef USE_JTAG_TRSTN
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input logic jtag_trst_ni,
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`endif
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`ifdef USE_JTAG_VDDGND
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output logic jtag_vdd_o,
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output logic jtag_gnd_o,
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`endif
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`ifdef USE_FAN
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input logic [2:0] fan_sw, // switch 4-6
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output logic fan_pwm,
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`endif
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output logic uart_tx_o,
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input logic uart_rx_i
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);
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////////////////////////
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// Clock Generation //
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////////////////////////
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wire sys_clk;
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wire soc_clk;
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IBUFDS #(
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.IBUF_LOW_PWR ("FALSE")
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) i_bufds_sys_clk (
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.I ( sys_clk_p ),
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.IB ( sys_clk_n ),
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.O ( sys_clk )
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);
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clkwiz i_clkwiz (
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.clk_in1 ( sys_clk ),
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.reset ( '0 ),
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.locked ( ),
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.clk_20 ( soc_clk )
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);
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/////////////////////
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// System Inputs //
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/////////////////////
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// Select SoC reset
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`ifdef USE_RESET
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logic sys_resetn;
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assign sys_resetn = ~sys_reset;
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`elsif USE_RESETN
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logic sys_reset;
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assign sys_reset = ~sys_resetn;
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`endif
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// Tie off inputs of no switches
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`ifndef USE_SWITCHES
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logic fetch_en_i;
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logic [GpioCount-2:0] gpio_i;
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assign test_mode_i = '0;
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assign fetch_en_i = '0;
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assign gpio_i = '0;
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`endif
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`ifndef USE_STATUS
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logic status_o;
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`endif
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`ifndef USE_LEDS
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logic [GpioCount-1:0] gpio_o;
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`endif
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////////////
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// VIOs //
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////////////
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logic vio_reset, vio_fetch_en, vio_gpio;
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`ifdef USE_VIO
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vio i_vio (
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.clk ( soc_clk ),
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.probe_out0 ( vio_reset ),
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.probe_out1 ( vio_fetch_en ),
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.probe_out2 ( vio_gpio )
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);
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`else
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assign vio_reset = '0;
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assign vio_fetch_en = '0;
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assign vio_gpio = '0;
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`endif
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//////////////
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// SOC IO //
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//////////////
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logic soc_fetch_en;
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logic soc_rst_n;
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assign soc_fetch_en = fetch_en_i | vio_fetch_en;
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assign soc_rst = ~sys_resetn | vio_reset;
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logic [GpioCount-1:0] soc_gpio_i;
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logic [GpioCount-1:0] soc_gpio_o;
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logic [GpioCount-1:0] soc_gpio_out_en_o;
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for(genvar idx=0; idx<GpioCount; idx++) begin
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assign gpio_o[idx] = soc_gpio_out_en_o[idx] ? soc_gpio_o[idx] : '0;
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if(idx == 0) begin
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assign soc_gpio_i[idx] = ~soc_gpio_out_en_o[idx] ? vio_gpio | gpio_i[0] : '0;
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end else begin
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assign soc_gpio_i[idx] = ~soc_gpio_out_en_o[idx] ? gpio_i[idx] : '0;
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end
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end
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//////////////////
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// Reset Sync //
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//////////////////
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wire rst_n;
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rstgen i_rstgen (
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.clk_i ( soc_clk ),
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.rst_ni ( ~soc_rst ),
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.test_mode_i ( '0 ),
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.rst_no ( rst_n ),
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.init_no ( )
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);
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////////////
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// JTAG //
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////////////
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`ifdef USE_JTAG_VDDGND
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assign jtag_vdd_o = 1'b1;
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assign jtag_gnd_o = 1'b0;
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`endif
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`ifndef USE_JTAG_TRSTN
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logic jtag_trst_ni;
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assign jtag_trst_ni = 1'b1;
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`endif
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/////////////////////////
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// "RTC" Clock Divider //
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/////////////////////////
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logic rtc_clk_d, rtc_clk_q;
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logic [15:0] counter_d, counter_q;
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// Divide soc_clk (20 MHz) by 610 => ~32.768kHz RTC Clock
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// TODO: does genesys 2 have a 32.768kHz reference clock?
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always_comb begin
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counter_d = counter_q + 1;
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rtc_clk_d = rtc_clk_q;
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if(counter_q == 610) begin
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counter_d = '0;
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rtc_clk_d = ~rtc_clk_q;
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end
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end
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always_ff @(posedge soc_clk, negedge rst_n) begin
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if(~rst_n) begin
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counter_q <= '0;
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rtc_clk_q <= 0;
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end else begin
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counter_q <= counter_d;
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rtc_clk_q <= rtc_clk_d;
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end
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end
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/////////////////
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// Fan Control //
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/////////////////
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`ifdef USE_FAN
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fan_ctrl i_fan_ctrl (
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.clk_i ( soc_clk ),
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.rst_ni ( rst_n ),
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.pwm_setting_i ( {'0, fan_sw} ),
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.fan_pwm_o ( fan_pwm )
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);
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`endif
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//////////////////
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// Cheshire SoC //
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//////////////////
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logic soc_testmode_i;
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assign soc_testmode_i = '0;
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croc_soc #(
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.GpioCount( GpioCount )
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)
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i_croc_soc (
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.clk_i ( soc_clk ),
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.rst_ni ( rst_n ),
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.ref_clk_i ( rtc_clk_q ),
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.testmode_i ( soc_testmode_i ),
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.fetch_en_i ( soc_fetch_en ),
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.status_o ( status_o ),
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.jtag_tck_i ( jtag_tck_i ),
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.jtag_tdi_i ( jtag_tdi_i ),
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.jtag_tdo_o ( jtag_tdo_o ),
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.jtag_tms_i ( jtag_tms_i ),
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.jtag_trst_ni ( jtag_trst_ni ),
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.uart_rx_i ( uart_rx_i ),
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.uart_tx_o ( uart_tx_o ),
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.gpio_i ( soc_gpio_i ),
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.gpio_o ( soc_gpio_o ),
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.gpio_out_en_o ( soc_gpio_out_en_o )
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);
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endmodule

‎xilinx/hw/fan_ctrl.sv‎

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// Copyright 2018 ETH Zurich and University of Bologna.
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// Solderpad Hardware License, Version 0.51, see LICENSE for details.
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// SPDX-License-Identifier: SHL-0.51
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//
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// Author: Florian Zaruba, zarubaf@iis.ee.ethz.ch
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// Description: PWM Fan Control for Genesys II board
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module fan_ctrl (
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input logic clk_i,
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input logic rst_ni,
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input logic [3:0] pwm_setting_i,
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output logic fan_pwm_o
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);
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logic [3:0] ms_clock_d, ms_clock_q;
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logic [11:0] cycle_counter_d, cycle_counter_q;
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// clock divider
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always_comb begin
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cycle_counter_d = cycle_counter_q + 1;
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ms_clock_d = ms_clock_q;
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// divide clock by 49
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// At 50 MHz input clock this results in a 62.5 kHz
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// PWM Signal
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if (cycle_counter_q == 49) begin
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cycle_counter_d = 0;
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ms_clock_d = ms_clock_q + 1;
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end
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if (ms_clock_q == 15) begin
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ms_clock_d = 0;
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end
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end
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// duty cycle
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always_comb begin
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if (ms_clock_q < pwm_setting_i) begin
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fan_pwm_o = 1'b1;
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end else begin
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fan_pwm_o = 1'b0;
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end
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end
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always_ff @(posedge clk_i or negedge rst_ni) begin
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if (~rst_ni) begin
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ms_clock_q <= '0;
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cycle_counter_q <= '0;
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end else begin
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ms_clock_q <= ms_clock_d;
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cycle_counter_q <= cycle_counter_d;
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end
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end
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endmodule

‎xilinx/implement.sh‎

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bender script vivado -t fpga -t rtl -t genesys2 > scripts/add_sources.genesys2.tcl
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mkdir -p build/genesys2.clkwiz
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cd build/genesys2.clkwiz && \
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vitis-2022.1 vivado -mode batch -log ../genesys2.clkwiz.log -jou ../genesys2.clkwiz.jou \
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-source ../../scripts/impl_ip.tcl \
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-tclargs genesys2 clkwiz \
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&& cd ../..
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mkdir -p build/genesys2.vio
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cd build/genesys2.vio &&
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vitis-2022.1 vivado -mode batch -log ../genesys2.vio.log -jou ../genesys2.vio.jou \
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-source ../../scripts/impl_ip.tcl \
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-tclargs genesys2 vio\
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&& cd ../..
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mkdir -p build/genesys2.croc
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cd build/genesys2.croc && \
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vitis-2022.1 vivado -mode batch -log ../croc.genesys2.log -jou ../croc.genesys2.jou \
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-source ../../scripts/impl_sys.tcl \
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-tclargs genesys2 croc \
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../genesys2.clkwiz/out.xci \
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../genesys2.vio/out.xci

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