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Jie Zhangquic-rajeshk
Jie Zhang
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quic-rajeshk
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FROMLIST: drm/msm/a6xx: Add support for Adreno 612
Add support for Adreno 612 GPU found in SM6150/QCS615 chipsets. A612 falls under ADRENO_6XX_GEN1 family and is a cut down version of A615 GPU. A612 has a new IP called Reduced Graphics Management Unit or RGMU which is a small state machine which helps to toggle GX GDSC (connected to CX rail) to implement IFPC feature. It doesn't support any other features of a full fledged GMU like clock control, resource voting to rpmh etc. So we need linux clock driver support like other gmu-wrapper implementations to control gpu core clock and gpu GX gdsc. This patch skips RGMU core initialization and act more like a gmu-wrapper case. Signed-off-by: Jie Zhang <quic_jiezh@quicinc.com> Signed-off-by: Akhil P Oommen <akhilpo@oss.qualcomm.com> Link: https://lore.kernel.org/all/20251107-qcs615-spin-2-v2-1-a2d7c4fbf6e6@oss.qualcomm.com/
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-14
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6 files changed

+90
-14
lines changed

‎drivers/gpu/drm/msm/adreno/a6xx_catalog.c‎

Lines changed: 16 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -705,6 +705,22 @@ static const struct adreno_info a6xx_gpus[] = {
705705
{ 157, 3 },
706706
{ 127, 4 },
707707
),
708+
}, {
709+
.chip_ids = ADRENO_CHIP_IDS(0x06010200),
710+
.family = ADRENO_6XX_GEN1,
711+
.fw = {
712+
[ADRENO_FW_SQE] = "a630_sqe.fw",
713+
[ADRENO_FW_GMU] = "a612_rgmu.bin",
714+
},
715+
.gmem = (SZ_128K + SZ_4K),
716+
.inactive_period = DRM_MSM_INACTIVE_PERIOD,
717+
.init = a6xx_gpu_init,
718+
.a6xx = &(const struct a6xx_info) {
719+
.hwcg = a612_hwcg,
720+
.protect = &a630_protect,
721+
.gmu_cgc_mode = 0x00000022,
722+
.prim_fifo_threshold = 0x00080000,
723+
},
708724
}, {
709725
.chip_ids = ADRENO_CHIP_IDS(0x06010500),
710726
.family = ADRENO_6XX_GEN1,

‎drivers/gpu/drm/msm/adreno/a6xx_gmu.c‎

Lines changed: 22 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -350,12 +350,18 @@ static const struct a6xx_gmu_oob_bits a6xx_gmu_oob_bits[] = {
350350
/* Trigger a OOB (out of band) request to the GMU */
351351
int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
352352
{
353+
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
354+
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
353355
int ret;
354356
u32 val;
355357
int request, ack;
356358

357359
WARN_ON_ONCE(!mutex_is_locked(&gmu->lock));
358360

361+
/* Skip OOB calls since RGMU is not enabled */
362+
if (adreno_has_rgmu(adreno_gpu))
363+
return 0;
364+
359365
if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits))
360366
return -EINVAL;
361367

@@ -395,10 +401,16 @@ int a6xx_gmu_set_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
395401
/* Clear a pending OOB state in the GMU */
396402
void a6xx_gmu_clear_oob(struct a6xx_gmu *gmu, enum a6xx_gmu_oob_state state)
397403
{
404+
struct a6xx_gpu *a6xx_gpu = container_of(gmu, struct a6xx_gpu, gmu);
405+
struct adreno_gpu *adreno_gpu = &a6xx_gpu->base;
398406
int bit;
399407

400408
WARN_ON_ONCE(!mutex_is_locked(&gmu->lock));
401409

410+
/* Skip OOB calls since RGMU is not enabled */
411+
if (adreno_has_rgmu(adreno_gpu))
412+
return;
413+
402414
if (state >= ARRAY_SIZE(a6xx_gmu_oob_bits))
403415
return;
404416

@@ -1900,7 +1912,8 @@ void a6xx_gmu_remove(struct a6xx_gpu *a6xx_gpu)
19001912
gmu->mmio = NULL;
19011913
gmu->rscc = NULL;
19021914

1903-
if (!adreno_has_gmu_wrapper(adreno_gpu)) {
1915+
if (!adreno_has_gmu_wrapper(adreno_gpu) &&
1916+
!adreno_has_rgmu(adreno_gpu)) {
19041917
a6xx_gmu_memory_free(gmu);
19051918

19061919
free_irq(gmu->gmu_irq, gmu);
@@ -1942,6 +1955,13 @@ int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
19421955
/* Mark legacy for manual SPTPRAC control */
19431956
gmu->legacy = true;
19441957

1958+
/* RGMU requires clocks */
1959+
ret = devm_clk_bulk_get_all(gmu->dev, &gmu->clocks);
1960+
if (ret < 0)
1961+
goto err_clk;
1962+
1963+
gmu->nr_clocks = ret;
1964+
19451965
/* Map the GMU registers */
19461966
gmu->mmio = a6xx_gmu_get_mmio(pdev, "gmu");
19471967
if (IS_ERR(gmu->mmio)) {
@@ -1981,6 +2001,7 @@ int a6xx_gmu_wrapper_init(struct a6xx_gpu *a6xx_gpu, struct device_node *node)
19812001
err_mmio:
19822002
iounmap(gmu->mmio);
19832003

2004+
err_clk:
19842005
/* Drop reference taken in of_find_device_by_node */
19852006
put_device(gmu->dev);
19862007

‎drivers/gpu/drm/msm/adreno/a6xx_gpu.c‎

Lines changed: 36 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -612,15 +612,26 @@ static void a6xx_set_hwcg(struct msm_gpu *gpu, bool state)
612612

613613
if (adreno_is_a630(adreno_gpu))
614614
clock_cntl_on = 0x8aa8aa02;
615-
else if (adreno_is_a610(adreno_gpu))
615+
else if (adreno_is_a610(adreno_gpu) || adreno_is_a612(adreno_gpu))
616616
clock_cntl_on = 0xaaa8aa82;
617617
else if (adreno_is_a702(adreno_gpu))
618618
clock_cntl_on = 0xaaaaaa82;
619619
else
620620
clock_cntl_on = 0x8aa8aa82;
621621

622-
cgc_delay = adreno_is_a615_family(adreno_gpu) ? 0x111 : 0x10111;
623-
cgc_hyst = adreno_is_a615_family(adreno_gpu) ? 0x555 : 0x5555;
622+
if (adreno_is_a612(adreno_gpu))
623+
cgc_delay = 0x11;
624+
else if (adreno_is_a615_family(adreno_gpu))
625+
cgc_delay = 0x111;
626+
else
627+
cgc_delay = 0x10111;
628+
629+
if (adreno_is_a612(adreno_gpu))
630+
cgc_hyst = 0x55;
631+
else if (adreno_is_a615_family(adreno_gpu))
632+
cgc_hyst = 0x555;
633+
else
634+
cgc_hyst = 0x5555;
624635

625636
gmu_write(&a6xx_gpu->gmu, REG_A6XX_GPU_GMU_AO_GMU_CGC_MODE_CNTL,
626637
state ? adreno_gpu->info->a6xx->gmu_cgc_mode : 0);
@@ -714,6 +725,9 @@ static int a6xx_calc_ubwc_config(struct adreno_gpu *gpu)
714725
cfg->ubwc_swizzle = 0x7;
715726
}
716727

728+
if (adreno_is_a612(gpu))
729+
cfg->highest_bank_bit = 14;
730+
717731
if (adreno_is_a618(gpu))
718732
cfg->highest_bank_bit = 14;
719733

@@ -1288,7 +1302,7 @@ static int hw_init(struct msm_gpu *gpu)
12881302
gpu_write(gpu, REG_A6XX_CP_LPAC_PROG_FIFO_SIZE, 0x00000020);
12891303

12901304
/* Setting the mem pool size */
1291-
if (adreno_is_a610(adreno_gpu)) {
1305+
if (adreno_is_a610(adreno_gpu) || adreno_is_a612(adreno_gpu)) {
12921306
gpu_write(gpu, REG_A6XX_CP_MEM_POOL_SIZE, 48);
12931307
gpu_write(gpu, REG_A6XX_CP_MEM_POOL_DBG_ADDR, 47);
12941308
} else if (adreno_is_a702(adreno_gpu)) {
@@ -1321,7 +1335,8 @@ static int hw_init(struct msm_gpu *gpu)
13211335
a6xx_set_ubwc_config(gpu);
13221336

13231337
/* Enable fault detection */
1324-
if (adreno_is_a730(adreno_gpu) ||
1338+
if (adreno_is_a612(adreno_gpu) ||
1339+
adreno_is_a730(adreno_gpu) ||
13251340
adreno_is_a740_family(adreno_gpu))
13261341
gpu_write(gpu, REG_A6XX_RBBM_INTERFACE_HANG_INT_CNTL, (1 << 30) | 0xcfffff);
13271342
else if (adreno_is_a690(adreno_gpu))
@@ -1576,7 +1591,7 @@ static void a6xx_recover(struct msm_gpu *gpu)
15761591
*/
15771592
gpu->active_submits = 0;
15781593

1579-
if (adreno_has_gmu_wrapper(adreno_gpu)) {
1594+
if (adreno_has_gmu_wrapper(adreno_gpu) || adreno_has_rgmu(adreno_gpu)) {
15801595
/* Drain the outstanding traffic on memory buses */
15811596
a6xx_bus_clear_pending_transactions(adreno_gpu, true);
15821597

@@ -2229,6 +2244,12 @@ static int a6xx_pm_resume(struct msm_gpu *gpu)
22292244
if (ret)
22302245
goto err_bulk_clk;
22312246

2247+
ret = clk_bulk_prepare_enable(gmu->nr_clocks, gmu->clocks);
2248+
if (ret) {
2249+
clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks);
2250+
goto err_bulk_clk;
2251+
}
2252+
22322253
if (adreno_is_a619_holi(adreno_gpu))
22332254
a6xx_sptprac_enable(gmu);
22342255

@@ -2242,8 +2263,10 @@ static int a6xx_pm_resume(struct msm_gpu *gpu)
22422263
err_set_opp:
22432264
mutex_unlock(&a6xx_gpu->gmu.lock);
22442265

2245-
if (!ret)
2266+
if (!ret) {
22462267
msm_devfreq_resume(gpu);
2268+
a6xx_llc_activate(a6xx_gpu);
2269+
}
22472270

22482271
return ret;
22492272
}
@@ -2284,6 +2307,8 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu)
22842307

22852308
trace_msm_gpu_suspend(0);
22862309

2310+
a6xx_llc_deactivate(a6xx_gpu);
2311+
22872312
msm_devfreq_suspend(gpu);
22882313

22892314
mutex_lock(&a6xx_gpu->gmu.lock);
@@ -2295,6 +2320,7 @@ static int a6xx_pm_suspend(struct msm_gpu *gpu)
22952320
a6xx_sptprac_disable(gmu);
22962321

22972322
clk_bulk_disable_unprepare(gpu->nr_clocks, gpu->grp_clks);
2323+
clk_bulk_disable_unprepare(gmu->nr_clocks, gmu->clocks);
22982324

22992325
pm_runtime_put_sync(gmu->gxpd);
23002326
dev_pm_opp_set_opp(&gpu->pdev->dev, NULL);
@@ -2673,7 +2699,8 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
26732699
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 4);
26742700
else if (is_a7xx)
26752701
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_a7xx, 1);
2676-
else if (adreno_has_gmu_wrapper(adreno_gpu))
2702+
else if (adreno_has_gmu_wrapper(adreno_gpu) ||
2703+
of_device_is_compatible(node, "qcom,adreno-rgmu"))
26772704
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs_gmuwrapper, 1);
26782705
else
26792706
ret = adreno_gpu_init(dev, pdev, adreno_gpu, &funcs, 1);
@@ -2689,7 +2716,7 @@ struct msm_gpu *a6xx_gpu_init(struct drm_device *dev)
26892716
if (adreno_is_a618(adreno_gpu) || adreno_is_7c3(adreno_gpu))
26902717
priv->gpu_clamp_to_idle = true;
26912718

2692-
if (adreno_has_gmu_wrapper(adreno_gpu))
2719+
if (adreno_has_gmu_wrapper(adreno_gpu) || adreno_has_rgmu(adreno_gpu))
26932720
ret = a6xx_gmu_wrapper_init(a6xx_gpu, node);
26942721
else
26952722
ret = a6xx_gmu_init(a6xx_gpu, node);

‎drivers/gpu/drm/msm/adreno/a6xx_gpu_state.c‎

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1596,7 +1596,8 @@ struct msm_gpu_state *a6xx_gpu_state_get(struct msm_gpu *gpu)
15961596
/* Get the generic state from the adreno core */
15971597
adreno_gpu_state_get(gpu, &a6xx_state->base);
15981598

1599-
if (!adreno_has_gmu_wrapper(adreno_gpu)) {
1599+
if (!adreno_has_gmu_wrapper(adreno_gpu) &&
1600+
!adreno_has_rgmu(adreno_gpu)) {
16001601
a6xx_get_gmu_registers(gpu, a6xx_state);
16011602

16021603
a6xx_state->gmu_log = a6xx_snapshot_gmu_bo(a6xx_state, &a6xx_gpu->gmu.log);

‎drivers/gpu/drm/msm/adreno/adreno_gpu.c‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1189,6 +1189,7 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev,
11891189

11901190
/* Only handle the core clock when GMU is not in use (or is absent). */
11911191
if (adreno_has_gmu_wrapper(adreno_gpu) ||
1192+
adreno_has_rgmu(adreno_gpu) ||
11921193
adreno_gpu->info->family < ADRENO_6XX_GEN1) {
11931194
/*
11941195
* This can only be done before devm_pm_opp_of_add_table(), or

‎drivers/gpu/drm/msm/adreno/adreno_gpu.h‎

Lines changed: 13 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -392,6 +392,16 @@ static inline int adreno_is_a610(const struct adreno_gpu *gpu)
392392
return adreno_is_revn(gpu, 610);
393393
}
394394

395+
static inline int adreno_is_a612(const struct adreno_gpu *gpu)
396+
{
397+
return gpu->info->chip_ids[0] == 0x06010200;
398+
}
399+
400+
static inline bool adreno_has_rgmu(const struct adreno_gpu *gpu)
401+
{
402+
return adreno_is_a612(gpu);
403+
}
404+
395405
static inline int adreno_is_a618(const struct adreno_gpu *gpu)
396406
{
397407
return adreno_is_revn(gpu, 618);
@@ -466,9 +476,9 @@ static inline int adreno_is_a610_family(const struct adreno_gpu *gpu)
466476
{
467477
if (WARN_ON_ONCE(!gpu->info))
468478
return false;
469-
470-
/* TODO: A612 */
471-
return adreno_is_a610(gpu) || adreno_is_a702(gpu);
479+
return adreno_is_a610(gpu) ||
480+
adreno_is_a612(gpu) ||
481+
adreno_is_a702(gpu);
472482
}
473483

474484
/* TODO: 615/616 */

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