From 0188ea99d001dbb73fd38a1930992cfdb4b9de01 Mon Sep 17 00:00:00 2001 From: Robert Bragg Date: Thu, 6 Nov 2014 20:54:28 +0000 Subject: [PATCH 01/21] drm/i915: Add i915 perf infrastructure This adds a DRM_IOCTL_I915_PERF_OPEN ioctl comparable to perf_event_open that opens a file descriptor for an event source. Based on our initial experience aiming to use the core perf infrastructure, this interface is inspired by perf, but focused on exposing metrics about work running on Gen graphics instead a CPU. One notable difference is that it doesn't support mmaping a circular buffer of samples into userspace. The currently planned use cases require an internal buffering that forces at least one copy of data which can be neatly hidden in a read() based interface. No specific event types are supported yet so perf_event_open can currently only get as far as returning EINVAL for an unknown event type. Signed-off-by: Robert Bragg --- drivers/gpu/drm/i915/Makefile | 3 + drivers/gpu/drm/i915/i915_dma.c | 7 + drivers/gpu/drm/i915/i915_drv.h | 74 ++++++ drivers/gpu/drm/i915/i915_perf.c | 430 +++++++++++++++++++++++++++++++ include/uapi/drm/i915_drm.h | 69 +++++ 5 files changed, 583 insertions(+) create mode 100644 drivers/gpu/drm/i915/i915_perf.c diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 44d290ae199911..5485495fb133ad 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -93,6 +93,9 @@ i915-y += dvo_ch7017.o \ # virtual gpu code i915-y += i915_vgpu.o +# perf code +i915-y += i915_perf.o + # legacy horrors i915-y += i915_dma.o diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index b4741d121a744f..4d8676d53892be 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -893,6 +893,11 @@ int i915_driver_load(struct drm_device *dev, unsigned long flags) mutex_init(&dev_priv->csr_lock); mutex_init(&dev_priv->av_mutex); + /* Must at least be initialized before trying to pin any context + * which i915_perf hooks into. + */ + i915_perf_init(dev); + intel_pm_setup(dev); intel_display_crc_init(dev); @@ -1139,6 +1144,7 @@ int i915_driver_unload(struct drm_device *dev) return ret; } + i915_perf_fini(dev); intel_power_domains_fini(dev_priv); intel_gpu_ips_teardown(); @@ -1329,6 +1335,7 @@ const struct drm_ioctl_desc i915_ioctls[] = { DRM_IOCTL_DEF_DRV(I915_GEM_USERPTR, i915_gem_userptr_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_GETPARAM, i915_gem_context_getparam_ioctl, DRM_RENDER_ALLOW), DRM_IOCTL_DEF_DRV(I915_GEM_CONTEXT_SETPARAM, i915_gem_context_setparam_ioctl, DRM_RENDER_ALLOW), + DRM_IOCTL_DEF_DRV(I915_PERF_OPEN, i915_perf_open_ioctl, DRM_RENDER_ALLOW), }; int i915_max_ioctl = ARRAY_SIZE(i915_ioctls); diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index f4af19a0d56963..83da3694a75b15 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1698,6 +1698,67 @@ struct i915_execbuffer_params { struct drm_i915_gem_request *request; }; +struct i915_perf_read_state { + int count; + ssize_t read; + char __user *buf; +}; + +struct i915_perf_stream { + struct drm_i915_private *dev_priv; + + struct list_head link; + + u32 sample_flags; + + struct intel_context *ctx; + bool enabled; + + /* Enables the collection of HW samples, either in response to + * I915_PERF_IOCTL_ENABLE or implicitly called when stream is + * opened without I915_PERF_FLAG_DISABLED */ + void (*enable)(struct i915_perf_stream *stream); + + /* Disables the collection of HW samples, either in response to + * I915_PERF_IOCTL_DISABLE or implicitly called before + * destroying the stream. */ + void (*disable)(struct i915_perf_stream *stream); + + /* Return: true if any i915 perf records are ready to read() + * for this stream */ + bool (*can_read)(struct i915_perf_stream *stream); + + /* Call poll_wait, passing a wait queue that will be woken + * once there is something ready to read() for the stream */ + void (*poll_wait)(struct i915_perf_stream *stream, + struct file *file, + poll_table *wait); + + /* For handling a blocking read, wait until there is something + * to ready to read() for the stream. E.g. wait on the same + * wait queue that would be passed to poll_wait() until + * ->can_read() returns true (if its safe to call ->can_read() + * without the i915 perf lock held). */ + int (*wait_unlocked)(struct i915_perf_stream *stream); + + /* Copy as many buffered i915 perf samples and records for + * this stream to userspace as will fit in the given buffer. + * + * Only write complete records. + * + * read_state->count is the length of read_state->buf + * + * Update read_state->read with the number of bytes written. + */ + void (*read)(struct i915_perf_stream *stream, + struct i915_perf_read_state *read_state); + + /* Cleanup any stream specific resources. + * + * The stream will always be disabled before this is called */ + void (*destroy)(struct i915_perf_stream *stream); +}; + struct drm_i915_private { struct drm_device *dev; struct kmem_cache *objects; @@ -1941,6 +2002,12 @@ struct drm_i915_private { struct i915_runtime_pm pm; + struct { + bool initialized; + struct mutex lock; + struct list_head streams; + } perf; + /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ struct { int (*execbuf_submit)(struct i915_execbuffer_params *params, @@ -3175,6 +3242,9 @@ int i915_gem_context_getparam_ioctl(struct drm_device *dev, void *data, int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, struct drm_file *file_priv); +int i915_perf_open_ioctl(struct drm_device *dev, void *data, + struct drm_file *file); + /* i915_gem_evict.c */ int __must_check i915_gem_evict_something(struct drm_device *dev, struct i915_address_space *vm, @@ -3288,6 +3358,10 @@ int i915_parse_cmds(struct intel_engine_cs *ring, u32 batch_len, bool is_master); +/* i915_perf.c */ +extern void i915_perf_init(struct drm_device *dev); +extern void i915_perf_fini(struct drm_device *dev); + /* i915_suspend.c */ extern int i915_save_state(struct drm_device *dev); extern int i915_restore_state(struct drm_device *dev); diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c new file mode 100644 index 00000000000000..8fcd946b5bee08 --- /dev/null +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -0,0 +1,430 @@ +/* + * Copyright © 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + */ + +#include +#include + +#include "i915_drv.h" + +struct perf_open_properties +{ + u32 sample_flags; + + u64 single_context:1; + u64 ctx_handle; +}; + +static ssize_t i915_perf_read_locked(struct i915_perf_stream *stream, + struct file *file, + char __user *buf, + size_t count, + loff_t *ppos) +{ + struct drm_i915_private *dev_priv = stream->dev_priv; + struct i915_perf_read_state state = { count, 0, buf }; + int ret; + + if (file->f_flags & O_NONBLOCK) { + if (!stream->can_read(stream)) + return -EAGAIN; + } else { + mutex_unlock(&dev_priv->perf.lock); + ret = stream->wait_unlocked(stream); + mutex_lock(&dev_priv->perf.lock); + + if (ret) + return ret; + } + + stream->read(stream, &state); + if (state.read == 0) + return -ENOSPC; + + return state.read; +} + +static ssize_t i915_perf_read(struct file *file, + char __user *buf, + size_t count, + loff_t *ppos) +{ + struct i915_perf_stream *stream = file->private_data; + struct drm_i915_private *dev_priv = stream->dev_priv; + ssize_t ret; + + mutex_lock(&dev_priv->perf.lock); + ret = i915_perf_read_locked(stream, file, buf, count, ppos); + mutex_unlock(&dev_priv->perf.lock); + + return ret; +} + +static unsigned int i915_perf_poll_locked(struct i915_perf_stream *stream, + struct file *file, + poll_table *wait) +{ + unsigned int streams = 0; + + stream->poll_wait(stream, file, wait); + + if (stream->can_read(stream)) + streams |= POLLIN; + + return streams; +} + +static unsigned int i915_perf_poll(struct file *file, poll_table *wait) +{ + struct i915_perf_stream *stream = file->private_data; + struct drm_i915_private *dev_priv = stream->dev_priv; + int ret; + + mutex_lock(&dev_priv->perf.lock); + ret = i915_perf_poll_locked(stream, file, wait); + mutex_unlock(&dev_priv->perf.lock); + + return ret; +} + +static void i915_perf_enable_locked(struct i915_perf_stream *stream) +{ + if (stream->enabled) + return; + + /* Allow stream->enable() to refer to this */ + stream->enabled = true; + + if (stream->enable) + stream->enable(stream); +} + +static void i915_perf_disable_locked(struct i915_perf_stream *stream) +{ + if (!stream->enabled) + return; + + /* Allow stream->disable() to refer to this */ + stream->enabled = false; + + if (stream->disable) + stream->disable(stream); +} + +static long i915_perf_ioctl_locked(struct i915_perf_stream *stream, + unsigned int cmd, + unsigned long arg) +{ + switch (cmd) { + case I915_PERF_IOCTL_ENABLE: + i915_perf_enable_locked(stream); + return 0; + case I915_PERF_IOCTL_DISABLE: + i915_perf_disable_locked(stream); + return 0; + } + + return -EINVAL; +} + +static long i915_perf_ioctl(struct file *file, + unsigned int cmd, + unsigned long arg) +{ + struct i915_perf_stream *stream = file->private_data; + struct drm_i915_private *dev_priv = stream->dev_priv; + long ret; + + mutex_lock(&dev_priv->perf.lock); + ret = i915_perf_ioctl_locked(stream, cmd, arg); + mutex_unlock(&dev_priv->perf.lock); + + return ret; +} + +static void i915_perf_destroy_locked(struct i915_perf_stream *stream) +{ + struct drm_i915_private *dev_priv = stream->dev_priv; + + if (stream->enabled) + i915_perf_disable_locked(stream); + + if (stream->destroy) + stream->destroy(stream); + + list_del(&stream->link); + + if (stream->ctx) { + mutex_lock(&dev_priv->dev->struct_mutex); + i915_gem_context_unreference(stream->ctx); + mutex_unlock(&dev_priv->dev->struct_mutex); + } + + kfree(stream); +} + +static int i915_perf_release(struct inode *inode, struct file *file) +{ + struct i915_perf_stream *stream = file->private_data; + struct drm_i915_private *dev_priv = stream->dev_priv; + + mutex_lock(&dev_priv->perf.lock); + i915_perf_destroy_locked(stream); + mutex_unlock(&dev_priv->perf.lock); + + return 0; +} + + +static const struct file_operations fops = { + .owner = THIS_MODULE, + .llseek = no_llseek, + .release = i915_perf_release, + .poll = i915_perf_poll, + .read = i915_perf_read, + .unlocked_ioctl = i915_perf_ioctl, +}; + +static struct intel_context * +lookup_context(struct drm_i915_private *dev_priv, + struct file *user_filp, + u32 ctx_user_handle) +{ + struct intel_context *ctx; + + mutex_lock(&dev_priv->dev->struct_mutex); + list_for_each_entry(ctx, &dev_priv->context_list, link) { + struct drm_file *drm_file; + + if (!ctx->file_priv) + continue; + + drm_file = ctx->file_priv->file; + + if (user_filp->private_data == drm_file && + ctx->user_handle == ctx_user_handle) { + i915_gem_context_reference(ctx); + mutex_unlock(&dev_priv->dev->struct_mutex); + + return ctx; + } + } + mutex_unlock(&dev_priv->dev->struct_mutex); + + return NULL; +} + +int i915_perf_open_ioctl_locked(struct drm_device *dev, + struct drm_i915_perf_open_param *param, + struct perf_open_properties *props, + struct drm_file *file) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct intel_context *specific_ctx = NULL; + struct i915_perf_stream *stream = NULL; + unsigned long f_flags = 0; + int stream_fd; + int ret = 0; + + if (props->single_context) { + u32 ctx_handle = props->ctx_handle; + + specific_ctx = lookup_context(dev_priv, file->filp, ctx_handle); + if (!specific_ctx) { + DRM_ERROR("Failed to look up context with ID %u for opening perf stream\n", + ctx_handle); + ret = -EINVAL; + goto err; + } + } + + if (!specific_ctx && !capable(CAP_SYS_ADMIN)) { + DRM_ERROR("Insufficient privileges to open system-wide i915 perf stream\n"); + ret = -EACCES; + goto err_ctx; + } + + stream = kzalloc(sizeof(*stream), GFP_KERNEL); + if (!stream) { + ret = -ENOMEM; + goto err_ctx; + } + + stream->sample_flags = props->sample_flags; + stream->dev_priv = dev_priv; + stream->ctx = specific_ctx; + + /* + * TODO: support sampling something + * + * For now this is as far as we can go. + */ + DRM_ERROR("Unsupported i915 perf stream configuration\n"); + ret = -EINVAL; + goto err_alloc; + + list_add(&stream->link, &dev_priv->perf.streams); + + if (param->flags & I915_PERF_FLAG_FD_CLOEXEC) + f_flags |= O_CLOEXEC; + if (param->flags & I915_PERF_FLAG_FD_NONBLOCK) + f_flags |= O_NONBLOCK; + + stream_fd = anon_inode_getfd("[i915_perf]", &fops, stream, f_flags); + if (stream_fd < 0) { + ret = stream_fd; + goto err_open; + } + + if (!(param->flags & I915_PERF_FLAG_DISABLED)) + i915_perf_enable_locked(stream); + + return stream_fd; + +err_open: + list_del(&stream->link); + if (stream->destroy) + stream->destroy(stream); +err_alloc: + kfree(stream); +err_ctx: + if (specific_ctx) { + mutex_lock(&dev_priv->dev->struct_mutex); + i915_gem_context_unreference(specific_ctx); + mutex_unlock(&dev_priv->dev->struct_mutex); + } +err: + return ret; +} + +/* Note we copy the properties from userspace outside of the i915 perf + * mutex to avoid an awkward lockdep with mmap_sem. + * + * Note this function only validates properties in isolation it doesn't + * validate that the combination of properties makes sense or that all + * properties necessary for a particular kind of stream have be set. + */ +static int read_properties_unlocked(struct drm_i915_private *dev_priv, + u64 __user *uprops, + u32 n_props, + struct perf_open_properties *props) +{ + u64 __user *uprop = uprops; + int i; + + memset(props, 0, sizeof(struct perf_open_properties)); + + if (!n_props) { + DRM_ERROR("No i915 perf properties given"); + return -EINVAL; + } + + if (n_props > DRM_I915_PERF_PROP_MAX) { + DRM_ERROR("More i915 perf properties specified than exist"); + return -EINVAL; + } + + for (i = 0; i < n_props; i++) { + u64 id, value; + int ret; + + ret = get_user(id, (u64 __user *)uprop); + if (ret) + return ret; + + if (id == 0 || id >= DRM_I915_PERF_PROP_MAX) { + DRM_ERROR("Unknown i915 perf property ID"); + return -EINVAL; + } + + ret = get_user(value, (u64 __user *)uprop + 1); + if (ret) + return ret; + + switch ((enum drm_i915_perf_property_id)id) { + case DRM_I915_PERF_CTX_HANDLE_PROP: + props->single_context = 1; + props->ctx_handle = value; + break; + + case DRM_I915_PERF_PROP_MAX: + BUG(); + } + + uprop += 2; + } + + return 0; +} + +int i915_perf_open_ioctl(struct drm_device *dev, void *data, + struct drm_file *file) +{ + struct drm_i915_private *dev_priv = dev->dev_private; + struct drm_i915_perf_open_param *param = data; + struct perf_open_properties props; + u32 known_open_flags = 0; + int ret; + + known_open_flags = I915_PERF_FLAG_FD_CLOEXEC | + I915_PERF_FLAG_FD_NONBLOCK | + I915_PERF_FLAG_DISABLED; + if (param->flags & ~known_open_flags) { + DRM_ERROR("Unknown drm_i915_perf_open_param flag\n"); + return -EINVAL; + } + + ret = read_properties_unlocked(dev_priv, + to_user_ptr(param->properties), + param->n_properties, + &props); + if (ret) + return ret; + + mutex_lock(&dev_priv->perf.lock); + ret = i915_perf_open_ioctl_locked(dev, param, &props, file); + mutex_unlock(&dev_priv->perf.lock); + + return ret; +} + +void i915_perf_init(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = to_i915(dev); + + INIT_LIST_HEAD(&dev_priv->perf.streams); + mutex_init(&dev_priv->perf.lock); + + dev_priv->perf.initialized = true; +} + +void i915_perf_fini(struct drm_device *dev) +{ + struct drm_i915_private *dev_priv = to_i915(dev); + + if (!dev_priv->perf.initialized) + return; + + /* Currently nothing to clean up */ + + dev_priv->perf.initialized = false; +} diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 484a9fb2047951..ff4507eafd5fd4 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -230,6 +230,7 @@ typedef struct _drm_i915_sarea { #define DRM_I915_GEM_USERPTR 0x33 #define DRM_I915_GEM_CONTEXT_GETPARAM 0x34 #define DRM_I915_GEM_CONTEXT_SETPARAM 0x35 +#define DRM_I915_PERF_OPEN 0x36 #define DRM_IOCTL_I915_INIT DRM_IOW( DRM_COMMAND_BASE + DRM_I915_INIT, drm_i915_init_t) #define DRM_IOCTL_I915_FLUSH DRM_IO ( DRM_COMMAND_BASE + DRM_I915_FLUSH) @@ -283,6 +284,7 @@ typedef struct _drm_i915_sarea { #define DRM_IOCTL_I915_GEM_USERPTR DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_USERPTR, struct drm_i915_gem_userptr) #define DRM_IOCTL_I915_GEM_CONTEXT_GETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_GETPARAM, struct drm_i915_gem_context_param) #define DRM_IOCTL_I915_GEM_CONTEXT_SETPARAM DRM_IOWR (DRM_COMMAND_BASE + DRM_I915_GEM_CONTEXT_SETPARAM, struct drm_i915_gem_context_param) +#define DRM_IOCTL_I915_PERF_OPEN DRM_IOWR(DRM_COMMAND_BASE + DRM_I915_PERF_OPEN, struct drm_i915_perf_open_param) /* Allow drivers to submit batchbuffers directly to hardware, relying * on the security mechanisms provided by hardware. @@ -1130,4 +1132,71 @@ struct drm_i915_gem_context_param { __u64 value; }; +#define I915_PERF_FLAG_FD_CLOEXEC (1<<0) +#define I915_PERF_FLAG_FD_NONBLOCK (1<<1) +#define I915_PERF_FLAG_DISABLED (1<<2) + +enum drm_i915_perf_property_id { + /** + * Open the stream for a specific context handle (as used with + * execbuffer2). A stream opened for a specific context this way + * won't typically require root privileges. + */ + DRM_I915_PERF_CTX_HANDLE_PROP = 1, + + DRM_I915_PERF_PROP_MAX /* non-ABI */ +}; + +struct drm_i915_perf_open_param { + /** CLOEXEC, NONBLOCK... */ + __u32 flags; + + /** + * Pointer to array of u64 (id, value) pairs configuring the stream + * to open. + */ + __u64 __user properties; + + /** The number of u64 (id, value) pairs */ + __u32 n_properties; +}; + +#define I915_PERF_IOCTL_ENABLE _IO('i', 0x0) +#define I915_PERF_IOCTL_DISABLE _IO('i', 0x1) + +/** + * Common to all i915 perf records + */ +struct drm_i915_perf_record_header { + __u32 type; + __u16 pad; + __u16 size; +}; + +enum drm_i915_perf_record_type { + + /** + * Samples are the work horse record type whose contents are extensible + * and defined when opening an i915 perf stream based on the given + * properties. + * + * Boolean properties following the naming convention + * DRM_I915_PERF_SAMPLE_xyz_PROP request the inclusion of 'xyz' data in + * every sample. + * + * The order of these sample properties given by userspace has no + * affect on the ordering of data within a sample. The order will be + * documented here. + * + * struct { + * struct drm_i915_perf_record_header header; + * + * TODO: itemize extensible sample data here + * }; + */ + DRM_I915_PERF_RECORD_SAMPLE = 1, + + DRM_I915_PERF_RECORD_MAX /* non-ABI */ +}; + #endif /* _UAPI_I915_DRM_H_ */ From bd4af6137b5d933300468f8a9627fc9199b313ed Mon Sep 17 00:00:00 2001 From: Robert Bragg Date: Tue, 10 Feb 2015 17:00:27 +0000 Subject: [PATCH 02/21] drm/i915: rename OACONTROL GEN7_OACONTROL OACONTROL changes quite a bit for gen8, with some bits split out into a per-context OACTXCONTROL register Signed-off-by: Robert Bragg --- drivers/gpu/drm/i915/i915_cmd_parser.c | 4 ++-- drivers/gpu/drm/i915/i915_reg.h | 2 +- 2 files changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_cmd_parser.c b/drivers/gpu/drm/i915/i915_cmd_parser.c index db58c8d664c2d4..8583793682defe 100644 --- a/drivers/gpu/drm/i915/i915_cmd_parser.c +++ b/drivers/gpu/drm/i915/i915_cmd_parser.c @@ -439,7 +439,7 @@ static const struct drm_i915_reg_descriptor gen7_render_regs[] = { REG64(CL_PRIMITIVES_COUNT), REG64(PS_INVOCATION_COUNT), REG64(PS_DEPTH_COUNT), - REG32(OACONTROL), /* Only allowed for LRI and SRM. See below. */ + REG32(GEN7_OACONTROL), /* Only allowed for LRI and SRM. See below. */ REG64(MI_PREDICATE_SRC0), REG64(MI_PREDICATE_SRC1), REG32(GEN7_3DPRIM_END_OFFSET), @@ -1023,7 +1023,7 @@ static bool check_cmd(const struct intel_engine_cs *ring, * to the register. Hence, limit OACONTROL writes to * only MI_LOAD_REGISTER_IMM commands. */ - if (reg_addr == OACONTROL) { + if (reg_addr == GEN7_OACONTROL) { if (desc->cmd.value == MI_LOAD_REGISTER_MEM) { DRM_DEBUG_DRIVER("CMD: Rejected LRM to OACONTROL\n"); return false; diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index bc7b8faba84d83..e64c866ab2abb6 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -540,7 +540,7 @@ #define GEN7_GPGPU_DISPATCHDIMY 0x2504 #define GEN7_GPGPU_DISPATCHDIMZ 0x2508 -#define OACONTROL 0x2360 +#define GEN7_OACONTROL 0x2360 #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 From 18f2a6d82769a9c4def77209fdd7950f0d071007 Mon Sep 17 00:00:00 2001 From: Robert Bragg Date: Mon, 21 Sep 2015 14:33:35 +0100 Subject: [PATCH 03/21] drm/i915: Add 'render basic' Haswell OA unit config Adds a static OA unit, MUX + B Counter configuration for basic render metrics on Haswell. This is autogenerated from an internal XML description of metric sets. Signed-off-by: Robert Bragg --- drivers/gpu/drm/i915/Makefile | 3 +- drivers/gpu/drm/i915/i915_drv.h | 14 +++ drivers/gpu/drm/i915/i915_oa_hsw.c | 132 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_oa_hsw.h | 34 ++++++++ 4 files changed, 182 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/i915/i915_oa_hsw.c create mode 100644 drivers/gpu/drm/i915/i915_oa_hsw.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 5485495fb133ad..5b1c688ecaef7d 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -94,7 +94,8 @@ i915-y += dvo_ch7017.o \ i915-y += i915_vgpu.o # perf code -i915-y += i915_perf.o +i915-y += i915_perf.o \ + i915_oa_hsw.o # legacy horrors i915-y += i915_dma.o diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 83da3694a75b15..9376824ccc26e9 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1698,6 +1698,11 @@ struct i915_execbuffer_params { struct drm_i915_gem_request *request; }; +struct i915_oa_reg { + u32 addr; + u32 value; +}; + struct i915_perf_read_state { int count; ssize_t read; @@ -2006,6 +2011,15 @@ struct drm_i915_private { bool initialized; struct mutex lock; struct list_head streams; + + struct { + u32 metrics_set; + + const struct i915_oa_reg *mux_regs; + int mux_regs_len; + const struct i915_oa_reg *b_counter_regs; + int b_counter_regs_len; + } oa; } perf; /* Abstract the submission mechanism (legacy ringbuffer or execlists) away */ diff --git a/drivers/gpu/drm/i915/i915_oa_hsw.c b/drivers/gpu/drm/i915/i915_oa_hsw.c new file mode 100644 index 00000000000000..c05745e1d567c5 --- /dev/null +++ b/drivers/gpu/drm/i915/i915_oa_hsw.c @@ -0,0 +1,132 @@ +/* + * Autogenerated file, DO NOT EDIT manually! + * + * Copyright (c) 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +#include "i915_drv.h" + +enum metric_set_id { + METRIC_SET_ID_RENDER_BASIC = 1, +}; + +int i915_oa_n_builtin_metric_sets_hsw = 1; + +static const struct i915_oa_reg b_counter_config_render_basic[] = { + { 0x2724, 0x00800000 }, + { 0x2720, 0x00000000 }, + { 0x2714, 0x00800000 }, + { 0x2710, 0x00000000 }, +}; + +static const struct i915_oa_reg mux_config_render_basic[] = { + { 0x253A4, 0x01600000 }, + { 0x25440, 0x00100000 }, + { 0x25128, 0x00000000 }, + { 0x2691C, 0x00000800 }, + { 0x26AA0, 0x01500000 }, + { 0x26B9C, 0x00006000 }, + { 0x2791C, 0x00000800 }, + { 0x27AA0, 0x01500000 }, + { 0x27B9C, 0x00006000 }, + { 0x2641C, 0x00000400 }, + { 0x25380, 0x00000010 }, + { 0x2538C, 0x00000000 }, + { 0x25384, 0x0800AAAA }, + { 0x25400, 0x00000004 }, + { 0x2540C, 0x06029000 }, + { 0x25410, 0x00000002 }, + { 0x25404, 0x5C30FFFF }, + { 0x25100, 0x00000016 }, + { 0x25110, 0x00000400 }, + { 0x25104, 0x00000000 }, + { 0x26804, 0x00001211 }, + { 0x26884, 0x00000100 }, + { 0x26900, 0x00000002 }, + { 0x26908, 0x00700000 }, + { 0x26904, 0x00000000 }, + { 0x26984, 0x00001022 }, + { 0x26A04, 0x00000011 }, + { 0x26A80, 0x00000006 }, + { 0x26A88, 0x00000C02 }, + { 0x26A84, 0x00000000 }, + { 0x26B04, 0x00001000 }, + { 0x26B80, 0x00000002 }, + { 0x26B8C, 0x00000007 }, + { 0x26B84, 0x00000000 }, + { 0x27804, 0x00004844 }, + { 0x27884, 0x00000400 }, + { 0x27900, 0x00000002 }, + { 0x27908, 0x0E000000 }, + { 0x27904, 0x00000000 }, + { 0x27984, 0x00004088 }, + { 0x27A04, 0x00000044 }, + { 0x27A80, 0x00000006 }, + { 0x27A88, 0x00018040 }, + { 0x27A84, 0x00000000 }, + { 0x27B04, 0x00004000 }, + { 0x27B80, 0x00000002 }, + { 0x27B8C, 0x000000E0 }, + { 0x27B84, 0x00000000 }, + { 0x26104, 0x00002222 }, + { 0x26184, 0x0C006666 }, + { 0x26284, 0x04000000 }, + { 0x26304, 0x04000000 }, + { 0x26400, 0x00000002 }, + { 0x26410, 0x000000A0 }, + { 0x26404, 0x00000000 }, + { 0x25420, 0x04108020 }, + { 0x25424, 0x1284A420 }, + { 0x2541C, 0x00000000 }, + { 0x25428, 0x00042049 }, +}; + +static int select_render_basic_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_render_basic; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_render_basic); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_render_basic; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_render_basic); + + return 0; +} + +int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = NULL; + dev_priv->perf.oa.mux_regs_len = 0; + dev_priv->perf.oa.b_counter_regs = NULL; + dev_priv->perf.oa.b_counter_regs_len = 0; + + switch (dev_priv->perf.oa.metrics_set) { + case METRIC_SET_ID_RENDER_BASIC: + return select_render_basic_config(dev_priv); + default: + return -ENODEV; + } +} diff --git a/drivers/gpu/drm/i915/i915_oa_hsw.h b/drivers/gpu/drm/i915/i915_oa_hsw.h new file mode 100644 index 00000000000000..b618a1f0aa94d7 --- /dev/null +++ b/drivers/gpu/drm/i915/i915_oa_hsw.h @@ -0,0 +1,34 @@ +/* + * Autogenerated file, DO NOT EDIT manually! + * + * Copyright (c) 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +#ifndef __I915_OA_HSW_H__ +#define __I915_OA_HSW_H__ + +extern int i915_oa_n_builtin_metric_sets_hsw; + +extern int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv); + +#endif From 70c21e16d1fcbea65e4d9dccc7879f190fdd8bb4 Mon Sep 17 00:00:00 2001 From: Robert Bragg Date: Wed, 16 Sep 2015 19:26:36 +0100 Subject: [PATCH 04/21] drm/i915: Add i915 perf event for Haswell OA unit Gen graphics hardware can be set up to periodically write snapshots of performance counters into a circular buffer via its Observation Architecture and this patch exposes that capability to userspace via the i915 perf interface. Cc: Chris Wilson Signed-off-by: Robert Bragg Signed-off-by: Zhenyu Wang --- drivers/gpu/drm/i915/i915_drv.h | 49 ++ drivers/gpu/drm/i915/i915_gem_context.c | 23 +- drivers/gpu/drm/i915/i915_perf.c | 706 +++++++++++++++++++++++- drivers/gpu/drm/i915/i915_reg.h | 338 ++++++++++++ include/uapi/drm/i915_drm.h | 56 +- 5 files changed, 1152 insertions(+), 20 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 9376824ccc26e9..d028d2e090c4e4 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1698,6 +1698,11 @@ struct i915_execbuffer_params { struct drm_i915_gem_request *request; }; +struct i915_oa_format { + u32 format; + int size; +}; + struct i915_oa_reg { u32 addr; u32 value; @@ -1715,6 +1720,7 @@ struct i915_perf_stream { struct list_head link; u32 sample_flags; + int sample_size; struct intel_context *ctx; bool enabled; @@ -1764,6 +1770,20 @@ struct i915_perf_stream { void (*destroy)(struct i915_perf_stream *stream); }; +struct i915_oa_ops { + void (*init_oa_buffer)(struct drm_i915_private *dev_priv); + int (*enable_metric_set)(struct drm_i915_private *dev_priv); + void (*disable_metric_set)(struct drm_i915_private *dev_priv); + void (*oa_enable)(struct drm_i915_private *dev_priv); + void (*oa_disable)(struct drm_i915_private *dev_priv); + void (*update_oacontrol)(struct drm_i915_private *dev_priv); + void (*update_hw_ctx_id_locked)(struct drm_i915_private *dev_priv, + u32 ctx_id); + void (*read)(struct i915_perf_stream *stream, + struct i915_perf_read_state *read_state); + bool (*oa_buffer_is_empty)(struct drm_i915_private *dev_priv); +}; + struct drm_i915_private { struct drm_device *dev; struct kmem_cache *objects; @@ -2009,16 +2029,43 @@ struct drm_i915_private { struct { bool initialized; + struct mutex lock; struct list_head streams; + spinlock_t hook_lock; + struct { + struct i915_perf_stream *exclusive_stream; + + u32 specific_ctx_id; + + struct hrtimer poll_check_timer; + wait_queue_head_t poll_wq; + + bool periodic; + u32 period_exponent; + u32 metrics_set; const struct i915_oa_reg *mux_regs; int mux_regs_len; const struct i915_oa_reg *b_counter_regs; int b_counter_regs_len; + + struct { + struct drm_i915_gem_object *obj; + u32 gtt_offset; + u8 *addr; + u32 head; + u32 tail; + int format; + int format_size; + } oa_buffer; + + struct i915_oa_ops ops; + const struct i915_oa_format *oa_formats; + int n_builtin_sets; } oa; } perf; @@ -3258,6 +3305,8 @@ int i915_gem_context_setparam_ioctl(struct drm_device *dev, void *data, int i915_perf_open_ioctl(struct drm_device *dev, void *data, struct drm_file *file); +void i915_oa_context_pin_notify(struct drm_i915_private *dev_priv, + struct intel_context *context); /* i915_gem_evict.c */ int __must_check i915_gem_evict_something(struct drm_device *dev, diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 02ceb7a4b4815e..b8d2d41c68f09d 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -133,6 +133,23 @@ static int get_context_size(struct drm_device *dev) return ret; } +static int i915_gem_context_pin_state(struct drm_device *dev, + struct intel_context *ctx) +{ + int ret; + + BUG_ON(!mutex_is_locked(&dev->struct_mutex)); + + ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state, + get_context_alignment(dev), 0); + if (ret) + return ret; + + i915_oa_context_pin_notify(dev->dev_private, ctx); + + return 0; +} + static void i915_gem_context_clean(struct intel_context *ctx) { struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; @@ -280,8 +297,7 @@ i915_gem_create_context(struct drm_device *dev, * be available. To avoid this we always pin the default * context. */ - ret = i915_gem_obj_ggtt_pin(ctx->legacy_hw_ctx.rcs_state, - get_context_alignment(dev), 0); + ret = i915_gem_context_pin_state(dev, ctx); if (ret) { DRM_DEBUG_DRIVER("Couldn't pin %d\n", ret); goto err_destroy; @@ -663,8 +679,7 @@ static int do_switch(struct drm_i915_gem_request *req) /* Trying to pin first makes error handling easier. */ if (ring == &dev_priv->ring[RCS]) { - ret = i915_gem_obj_ggtt_pin(to->legacy_hw_ctx.rcs_state, - get_context_alignment(ring->dev), 0); + ret = i915_gem_context_pin_state(ring->dev, to); if (ret) return ret; } diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 8fcd946b5bee08..d62de1af5c572b 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -25,6 +25,32 @@ #include #include "i915_drv.h" +#include "intel_ringbuffer.h" +#include "intel_lrc.h" +#include "i915_oa_hsw.h" + +/* Must be a power of two */ +#define OA_BUFFER_SIZE SZ_16M +#define OA_TAKEN(tail, head) ((tail - head) & (OA_BUFFER_SIZE - 1)) + +/* frequency for forwarding samples from OA to perf buffer */ +#define POLL_FREQUENCY 200 +#define POLL_PERIOD max_t(u64, 10000, NSEC_PER_SEC / POLL_FREQUENCY) + +#define OA_EXPONENT_MAX 0x3f + +static struct i915_oa_format hsw_oa_formats[I915_OA_FORMAT_MAX] = { + [I915_OA_FORMAT_A13] = { 0, 64 }, + [I915_OA_FORMAT_A29] = { 1, 128 }, + [I915_OA_FORMAT_A13_B8_C8] = { 2, 128 }, + /* A29_B8_C8 Disallowed as 192 bytes doesn't factor into buffer size */ + [I915_OA_FORMAT_B4_C8] = { 4, 64 }, + [I915_OA_FORMAT_A45_B8_C8] = { 5, 256 }, + [I915_OA_FORMAT_B4_C8_A16] = { 6, 128 }, + [I915_OA_FORMAT_C4_B8] = { 7, 64 }, +}; + +#define SAMPLE_OA_REPORT (1<<0) struct perf_open_properties { @@ -32,8 +58,577 @@ struct perf_open_properties u64 single_context:1; u64 ctx_handle; + + /* OA sampling state */ + int metrics_set; + int oa_format; + bool oa_periodic; + u32 oa_period_exponent; }; +static bool gen7_oa_buffer_is_empty(struct drm_i915_private *dev_priv) +{ + u32 oastatus2 = I915_READ(GEN7_OASTATUS2); + u32 oastatus1 = I915_READ(GEN7_OASTATUS1); + u32 head = oastatus2 & GEN7_OASTATUS2_HEAD_MASK; + u32 tail = oastatus1 & GEN7_OASTATUS1_TAIL_MASK; + + return OA_TAKEN(tail, head) == 0; +} + +static bool append_oa_status(struct i915_perf_stream *stream, + struct i915_perf_read_state *read_state, + enum drm_i915_perf_record_type type) +{ + struct drm_i915_perf_record_header header = { type, 0, sizeof(header) }; + + if ((read_state->count - read_state->read) < header.size) + return false; + + copy_to_user(read_state->buf, &header, sizeof(header)); + + read_state->buf += sizeof(header); + read_state->read += header.size; + + return true; +} + +static bool append_oa_sample(struct i915_perf_stream *stream, + struct i915_perf_read_state *read_state, + const u8 *report) +{ + struct drm_i915_private *dev_priv = stream->dev_priv; + int report_size = dev_priv->perf.oa.oa_buffer.format_size; + struct drm_i915_perf_record_header header; + u32 sample_flags = stream->sample_flags; + + header.type = DRM_I915_PERF_RECORD_SAMPLE; + header.pad = 0; + header.size = stream->sample_size; + + if ((read_state->count - read_state->read) < header.size) + return false; + + copy_to_user(read_state->buf, &header, sizeof(header)); + read_state->buf += sizeof(header); + + if (sample_flags & SAMPLE_OA_REPORT) { + copy_to_user(read_state->buf, report, report_size); + read_state->buf += report_size; + } + + read_state->read += header.size; + + return true; +} + +static u32 gen7_append_oa_reports(struct i915_perf_stream *stream, + struct i915_perf_read_state *read_state, + u32 head, + u32 tail) +{ + struct drm_i915_private *dev_priv = stream->dev_priv; + int report_size = dev_priv->perf.oa.oa_buffer.format_size; + u8 *oa_buf_base = dev_priv->perf.oa.oa_buffer.addr; + u32 mask = (OA_BUFFER_SIZE - 1); + u8 *report; + u32 taken; + + head -= dev_priv->perf.oa.oa_buffer.gtt_offset; + tail -= dev_priv->perf.oa.oa_buffer.gtt_offset; + + /* Note: the gpu doesn't wrap the tail according to the OA buffer size + * so when we need to make sure our head/tail values are in-bounds we + * use the above mask. + */ + + while ((taken = OA_TAKEN(tail, head))) { + /* The tail increases in 64 byte increments, not in + * format_size steps. */ + if (taken < report_size) + break; + + report = oa_buf_base + (head & mask); + + if (dev_priv->perf.oa.exclusive_stream->enabled) { + if (!append_oa_sample(stream, read_state, report)) + break; + } + + /* If append_oa_sample() returns false we shouldn't progress + * head so we update it afterwards... */ + head += report_size; + } + + return dev_priv->perf.oa.oa_buffer.gtt_offset + head; +} + +static void gen7_oa_read(struct i915_perf_stream *stream, + struct i915_perf_read_state *read_state) +{ + struct drm_i915_private *dev_priv = stream->dev_priv; + u32 oastatus2; + u32 oastatus1; + u32 head; + u32 tail; + + WARN_ON(!dev_priv->perf.oa.oa_buffer.addr); + + oastatus2 = I915_READ(GEN7_OASTATUS2); + oastatus1 = I915_READ(GEN7_OASTATUS1); + + head = oastatus2 & GEN7_OASTATUS2_HEAD_MASK; + tail = oastatus1 & GEN7_OASTATUS1_TAIL_MASK; + + if (unlikely(oastatus1 & (GEN7_OASTATUS1_OABUFFER_OVERFLOW | + GEN7_OASTATUS1_REPORT_LOST))) { + + if (oastatus1 & GEN7_OASTATUS1_OABUFFER_OVERFLOW) { + if (append_oa_status(stream, read_state, + DRM_I915_PERF_RECORD_OA_BUFFER_OVERFLOW)) + oastatus1 &= ~GEN7_OASTATUS1_OABUFFER_OVERFLOW; + } + + if (oastatus1 & GEN7_OASTATUS1_REPORT_LOST) { + if (append_oa_status(stream, read_state, + DRM_I915_PERF_RECORD_OA_REPORT_LOST)) + oastatus1 &= ~GEN7_OASTATUS1_REPORT_LOST; + } + + I915_WRITE(GEN7_OASTATUS1, oastatus1); + } + + head = gen7_append_oa_reports(stream, read_state, head, tail); + + I915_WRITE(GEN7_OASTATUS2, (head & GEN7_OASTATUS2_HEAD_MASK) | + OA_MEM_SELECT_GGTT); +} + +static bool i915_oa_can_read(struct i915_perf_stream *stream) +{ + struct drm_i915_private *dev_priv = stream->dev_priv; + + return !dev_priv->perf.oa.ops.oa_buffer_is_empty(dev_priv); +} + +static int i915_oa_wait_unlocked(struct i915_perf_stream *stream) +{ + struct drm_i915_private *dev_priv = stream->dev_priv; + + /* Note: the oa_buffer_is_empty() condition is ok to run unlocked as it + * just performs mmio reads of the OA buffer head + tail pointers and + * it's assumed we're handling some operation that implies the stream + * can't be destroyed until completion (such as a read()) that ensures + * the device + OA buffer can't disappear + */ + return wait_event_interruptible(dev_priv->perf.oa.poll_wq, + !dev_priv->perf.oa.ops.oa_buffer_is_empty(dev_priv)); +} + +static void i915_oa_poll_wait(struct i915_perf_stream *stream, + struct file *file, + poll_table *wait) +{ + struct drm_i915_private *dev_priv = stream->dev_priv; + + poll_wait(file, &dev_priv->perf.oa.poll_wq, wait); +} + +static void i915_oa_read(struct i915_perf_stream *stream, + struct i915_perf_read_state *read_state) +{ + struct drm_i915_private *dev_priv = stream->dev_priv; + + dev_priv->perf.oa.ops.read(stream, read_state); +} + +static void +free_oa_buffer(struct drm_i915_private *i915) +{ + mutex_lock(&i915->dev->struct_mutex); + + vunmap(i915->perf.oa.oa_buffer.addr); + i915_gem_object_ggtt_unpin(i915->perf.oa.oa_buffer.obj); + drm_gem_object_unreference(&i915->perf.oa.oa_buffer.obj->base); + + i915->perf.oa.oa_buffer.obj = NULL; + i915->perf.oa.oa_buffer.gtt_offset = 0; + i915->perf.oa.oa_buffer.addr = NULL; + + mutex_unlock(&i915->dev->struct_mutex); +} + +static void i915_oa_stream_destroy(struct i915_perf_stream *stream) +{ + struct drm_i915_private *dev_priv = stream->dev_priv; + + BUG_ON(stream != dev_priv->perf.oa.exclusive_stream); + + dev_priv->perf.oa.ops.disable_metric_set(dev_priv); + + free_oa_buffer(dev_priv); + + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); + intel_runtime_pm_put(dev_priv); + + dev_priv->perf.oa.exclusive_stream = NULL; +} + +static void *vmap_oa_buffer(struct drm_i915_gem_object *obj) +{ + int i; + void *addr = NULL; + struct sg_page_iter sg_iter; + struct page **pages; + + pages = drm_malloc_ab(obj->base.size >> PAGE_SHIFT, sizeof(*pages)); + if (pages == NULL) { + DRM_DEBUG_DRIVER("Failed to get space for pages\n"); + goto finish; + } + + i = 0; + for_each_sg_page(obj->pages->sgl, &sg_iter, obj->pages->nents, 0) { + pages[i] = sg_page_iter_page(&sg_iter); + i++; + } + + addr = vmap(pages, i, 0, PAGE_KERNEL); + if (addr == NULL) { + DRM_DEBUG_DRIVER("Failed to vmap pages\n"); + goto finish; + } + +finish: + if (pages) + drm_free_large(pages); + return addr; +} + +static void gen7_init_oa_buffer(struct drm_i915_private *dev_priv) +{ + /* Pre-DevBDW: OABUFFER must be set with counters off, + * before OASTATUS1, but after OASTATUS2 */ + I915_WRITE(GEN7_OASTATUS2, dev_priv->perf.oa.oa_buffer.gtt_offset | + OA_MEM_SELECT_GGTT); /* head */ + I915_WRITE(GEN7_OABUFFER, dev_priv->perf.oa.oa_buffer.gtt_offset); + I915_WRITE(GEN7_OASTATUS1, dev_priv->perf.oa.oa_buffer.gtt_offset | + OABUFFER_SIZE_16M); /* tail */ +} + +static int alloc_oa_buffer(struct drm_i915_private *dev_priv) +{ + struct drm_i915_gem_object *bo; + int ret; + + BUG_ON(dev_priv->perf.oa.oa_buffer.obj); + + ret = i915_mutex_lock_interruptible(dev_priv->dev); + if (ret) + return ret; + + bo = i915_gem_alloc_object(dev_priv->dev, OA_BUFFER_SIZE); + if (bo == NULL) { + DRM_ERROR("Failed to allocate OA buffer\n"); + ret = -ENOMEM; + goto unlock; + } + dev_priv->perf.oa.oa_buffer.obj = bo; + + ret = i915_gem_object_set_cache_level(bo, I915_CACHE_LLC); + if (ret) + goto err_unref; + + /* PreHSW required 512K alignment, HSW requires 16M */ + ret = i915_gem_obj_ggtt_pin(bo, SZ_16M, 0); + if (ret) + goto err_unref; + + dev_priv->perf.oa.oa_buffer.gtt_offset = i915_gem_obj_ggtt_offset(bo); + dev_priv->perf.oa.oa_buffer.addr = vmap_oa_buffer(bo); + + dev_priv->perf.oa.ops.init_oa_buffer(dev_priv); + + DRM_DEBUG_DRIVER("OA Buffer initialized, gtt offset = 0x%x, vaddr = %p", + dev_priv->perf.oa.oa_buffer.gtt_offset, + dev_priv->perf.oa.oa_buffer.addr); + + goto unlock; + +err_unref: + drm_gem_object_unreference(&bo->base); + +unlock: + mutex_unlock(&dev_priv->dev->struct_mutex); + return ret; +} + +static void config_oa_regs(struct drm_i915_private *dev_priv, + const struct i915_oa_reg *regs, + int n_regs) +{ + int i; + + for (i = 0; i < n_regs; i++) { + const struct i915_oa_reg *reg = regs + i; + + I915_WRITE(reg->addr, reg->value); + } +} + +static int hsw_enable_metric_set(struct drm_i915_private *dev_priv) +{ + int ret = i915_oa_select_metric_set_hsw(dev_priv); + + if (ret) + return ret; + + I915_WRITE(GDT_CHICKEN_BITS, GT_NOA_ENABLE); + + /* PRM: + * + * OA unit is using “crclk” for its functionality. When trunk + * level clock gating takes place, OA clock would be gated, + * unable to count the events from non-render clock domain. + * Render clock gating must be disabled when OA is enabled to + * count the events from non-render domain. Unit level clock + * gating for RCS should also be disabled. + */ + I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) & + ~GEN7_DOP_CLOCK_GATE_ENABLE)); + I915_WRITE(GEN6_UCGCTL1, (I915_READ(GEN6_UCGCTL1) | + GEN6_CSUNIT_CLOCK_GATE_DISABLE)); + + config_oa_regs(dev_priv, dev_priv->perf.oa.mux_regs, + dev_priv->perf.oa.mux_regs_len); + config_oa_regs(dev_priv, dev_priv->perf.oa.b_counter_regs, + dev_priv->perf.oa.b_counter_regs_len); + + return 0; +} + +static void hsw_disable_metric_set(struct drm_i915_private *dev_priv) +{ + I915_WRITE(GEN6_UCGCTL1, (I915_READ(GEN6_UCGCTL1) & + ~GEN6_CSUNIT_CLOCK_GATE_DISABLE)); + I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) | + GEN7_DOP_CLOCK_GATE_ENABLE)); + + I915_WRITE(GDT_CHICKEN_BITS, (I915_READ(GDT_CHICKEN_BITS) & + ~GT_NOA_ENABLE)); +} + +static void gen7_update_oacontrol_locked(struct drm_i915_private *dev_priv) +{ + assert_spin_locked(&dev_priv->perf.hook_lock); + + if (dev_priv->perf.oa.exclusive_stream->enabled) { + unsigned long ctx_id = 0; + bool pinning_ok = false; + + if (dev_priv->perf.oa.exclusive_stream->ctx && + dev_priv->perf.oa.specific_ctx_id) { + ctx_id = dev_priv->perf.oa.specific_ctx_id; + pinning_ok = true; + } + + if (dev_priv->perf.oa.exclusive_stream->ctx == NULL || + pinning_ok) { + bool periodic = dev_priv->perf.oa.periodic; + u32 period_exponent = dev_priv->perf.oa.period_exponent; + u32 report_format = dev_priv->perf.oa.oa_buffer.format; + + I915_WRITE(GEN7_OACONTROL, + (ctx_id & GEN7_OACONTROL_CTX_MASK) | + (period_exponent << + GEN7_OACONTROL_TIMER_PERIOD_SHIFT) | + (periodic ? + GEN7_OACONTROL_TIMER_ENABLE : 0) | + (report_format << + GEN7_OACONTROL_FORMAT_SHIFT) | + (ctx_id ? + GEN7_OACONTROL_PER_CTX_ENABLE : 0) | + GEN7_OACONTROL_ENABLE); + return; + } + } + + I915_WRITE(GEN7_OACONTROL, 0); +} + +static void gen7_oa_enable(struct drm_i915_private *dev_priv) +{ + unsigned long flags; + u32 oastatus1, tail; + + spin_lock_irqsave(&dev_priv->perf.hook_lock, flags); + gen7_update_oacontrol_locked(dev_priv); + spin_unlock_irqrestore(&dev_priv->perf.hook_lock, flags); + + /* Reset the head ptr so we don't forward reports from before now. */ + oastatus1 = I915_READ(GEN7_OASTATUS1); + tail = oastatus1 & GEN7_OASTATUS1_TAIL_MASK; + I915_WRITE(GEN7_OASTATUS2, (tail & GEN7_OASTATUS2_HEAD_MASK) | + OA_MEM_SELECT_GGTT); +} + +static void i915_oa_stream_enable(struct i915_perf_stream *stream) +{ + struct drm_i915_private *dev_priv = stream->dev_priv; + + dev_priv->perf.oa.ops.oa_enable(dev_priv); + + if (dev_priv->perf.oa.periodic) + hrtimer_start(&dev_priv->perf.oa.poll_check_timer, + ns_to_ktime(POLL_PERIOD), + HRTIMER_MODE_REL_PINNED); +} + +static void gen7_oa_disable(struct drm_i915_private *dev_priv) +{ + I915_WRITE(GEN7_OACONTROL, 0); +} + +static void i915_oa_stream_disable(struct i915_perf_stream *stream) +{ + struct drm_i915_private *dev_priv = stream->dev_priv; + + dev_priv->perf.oa.ops.oa_disable(dev_priv); + + if (dev_priv->perf.oa.periodic) + hrtimer_cancel(&dev_priv->perf.oa.poll_check_timer); +} + +static int i915_oa_stream_init(struct i915_perf_stream *stream, + struct drm_i915_perf_open_param *param, + struct perf_open_properties *props) +{ + struct drm_i915_private *dev_priv = stream->dev_priv; + int format_size; + int ret; + + if (!(props->sample_flags & SAMPLE_OA_REPORT)) { + DRM_ERROR("Only OA report sampling supported\n"); + return -EINVAL; + } + + if (!dev_priv->perf.oa.ops.init_oa_buffer) { + DRM_ERROR("OA unit not supported\n"); + return -ENODEV; + } + + /* To avoid the complexity of having to accurately filter + * counter reports and marshal to the appropriate client + * we currently only allow exclusive access */ + if (dev_priv->perf.oa.exclusive_stream) { + DRM_ERROR("OA unit already in use\n"); + return -EBUSY; + } + + if (!props->metrics_set) { + DRM_ERROR("OA metric set not specified\n"); + return -EINVAL; + } + + if (!props->oa_format) { + DRM_ERROR("OA report format not specified\n"); + return -EINVAL; + } + + stream->sample_size = sizeof(struct drm_i915_perf_record_header); + + format_size = dev_priv->perf.oa.oa_formats[props->oa_format].size; + + stream->sample_flags |= SAMPLE_OA_REPORT; + stream->sample_size += format_size; + + dev_priv->perf.oa.oa_buffer.format_size = format_size; + BUG_ON(dev_priv->perf.oa.oa_buffer.format_size == 0); + + dev_priv->perf.oa.oa_buffer.format = + dev_priv->perf.oa.oa_formats[props->oa_format].format; + + dev_priv->perf.oa.metrics_set = props->metrics_set; + + dev_priv->perf.oa.periodic = props->oa_periodic; + if (dev_priv->perf.oa.periodic) + dev_priv->perf.oa.period_exponent = props->oa_period_exponent; + + ret = alloc_oa_buffer(dev_priv); + if (ret) + return ret; + + dev_priv->perf.oa.exclusive_stream = stream; + + /* PRM - observability performance counters: + * + * OACONTROL, performance counter enable, note: + * + * "When this bit is set, in order to have coherent counts, + * RC6 power state and trunk clock gating must be disabled. + * This can be achieved by programming MMIO registers as + * 0xA094=0 and 0xA090[31]=1" + * + * In our case we are expected that taking pm + FORCEWAKE + * references will effectively disable RC6. + */ + intel_runtime_pm_get(dev_priv); + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); + + dev_priv->perf.oa.ops.enable_metric_set(dev_priv); + + stream->destroy = i915_oa_stream_destroy; + stream->enable = i915_oa_stream_enable; + stream->disable = i915_oa_stream_disable; + stream->can_read = i915_oa_can_read; + stream->wait_unlocked = i915_oa_wait_unlocked; + stream->poll_wait = i915_oa_poll_wait; + stream->read = i915_oa_read; + + return 0; +} + +static void gen7_update_hw_ctx_id_locked(struct drm_i915_private *dev_priv, + u32 ctx_id) +{ + assert_spin_locked(&dev_priv->perf.hook_lock); + + dev_priv->perf.oa.specific_ctx_id = ctx_id; + gen7_update_oacontrol_locked(dev_priv); +} + +static void i915_oa_context_pin_notify_locked(struct drm_i915_private *dev_priv, + struct intel_context *context) +{ + assert_spin_locked(&dev_priv->perf.hook_lock); + + if (i915.enable_execlists || + dev_priv->perf.oa.ops.update_hw_ctx_id_locked == NULL) + return; + + if (dev_priv->perf.oa.exclusive_stream && + dev_priv->perf.oa.exclusive_stream->ctx == context) { + struct drm_i915_gem_object *obj = + context->legacy_hw_ctx.rcs_state; + u32 ctx_id = i915_gem_obj_ggtt_offset(obj); + + dev_priv->perf.oa.ops.update_hw_ctx_id_locked(dev_priv, ctx_id); + } +} + +void i915_oa_context_pin_notify(struct drm_i915_private *dev_priv, + struct intel_context *context) +{ + unsigned long flags; + + if (!dev_priv->perf.initialized) + return; + + spin_lock_irqsave(&dev_priv->perf.hook_lock, flags); + i915_oa_context_pin_notify_locked(dev_priv, context); + spin_unlock_irqrestore(&dev_priv->perf.hook_lock, flags); +} + static ssize_t i915_perf_read_locked(struct i915_perf_stream *stream, struct file *file, char __user *buf, @@ -79,6 +674,20 @@ static ssize_t i915_perf_read(struct file *file, return ret; } +static enum hrtimer_restart poll_check_timer_cb(struct hrtimer *hrtimer) +{ + struct drm_i915_private *dev_priv = + container_of(hrtimer, typeof(*dev_priv), + perf.oa.poll_check_timer); + + if (!dev_priv->perf.oa.ops.oa_buffer_is_empty(dev_priv)) + wake_up(&dev_priv->perf.oa.poll_wq); + + hrtimer_forward_now(hrtimer, ns_to_ktime(POLL_PERIOD)); + + return HRTIMER_RESTART; +} + static unsigned int i915_perf_poll_locked(struct i915_perf_stream *stream, struct file *file, poll_table *wait) @@ -234,9 +843,9 @@ lookup_context(struct drm_i915_private *dev_priv, } int i915_perf_open_ioctl_locked(struct drm_device *dev, - struct drm_i915_perf_open_param *param, - struct perf_open_properties *props, - struct drm_file *file) + struct drm_i915_perf_open_param *param, + struct perf_open_properties *props, + struct drm_file *file) { struct drm_i915_private *dev_priv = dev->dev_private; struct intel_context *specific_ctx = NULL; @@ -269,18 +878,17 @@ int i915_perf_open_ioctl_locked(struct drm_device *dev, goto err_ctx; } - stream->sample_flags = props->sample_flags; stream->dev_priv = dev_priv; stream->ctx = specific_ctx; - /* - * TODO: support sampling something - * - * For now this is as far as we can go. - */ - DRM_ERROR("Unsupported i915 perf stream configuration\n"); - ret = -EINVAL; - goto err_alloc; + ret = i915_oa_stream_init(stream, param, props); + if (ret) + goto err_alloc; + + /* we avoid simply assigning stream->sample_flags = props->sample_flags + * to have _stream_init check the combination of sample flags more + * thoroughly, but still this is the expected result at this point. */ + BUG_ON(stream->sample_flags != props->sample_flags); list_add(&stream->link, &dev_priv->perf.streams); @@ -365,7 +973,52 @@ static int read_properties_unlocked(struct drm_i915_private *dev_priv, props->single_context = 1; props->ctx_handle = value; break; - + case DRM_I915_PERF_SAMPLE_OA_PROP: + props->sample_flags |= SAMPLE_OA_REPORT; + break; + case DRM_I915_PERF_OA_METRICS_SET_PROP: + if (value == 0 || value > dev_priv->perf.oa.n_builtin_sets) { + DRM_ERROR("Unknown OA metric set ID"); + return -EINVAL; + } + props->metrics_set = value; + break; + case DRM_I915_PERF_OA_FORMAT_PROP: + if (value == 0 || value >= I915_OA_FORMAT_MAX) { + DRM_ERROR("Invalid OA report format\n"); + return -EINVAL; + } + if (!dev_priv->perf.oa.oa_formats[value].size) { + DRM_ERROR("Invalid OA report format\n"); + return -EINVAL; + } + props->oa_format = value; + break; + case DRM_I915_PERF_OA_EXPONENT_PROP: + if (value > OA_EXPONENT_MAX) + return -EINVAL; + + /* NB: The exponent represents a period as follows: + * + * 80ns * 2^(period_exponent + 1) + * + * Theoretically we can program the OA unit to sample + * every 160ns but don't allow that by default unless + * root. + * + * Referring to perf's + * kernel.perf_event_max_sample_rate for a precedent + * (100000 by default); with an OA exponent of 6 we get + * a period of 10.240 microseconds -just under 100000Hz + */ + if (value < 6 && !capable(CAP_SYS_ADMIN)) { + DRM_ERROR("Sampling period too high without root privileges\n"); + return -EACCES; + } + + props->oa_periodic = true; + props->oa_period_exponent = value; + break; case DRM_I915_PERF_PROP_MAX: BUG(); } @@ -411,8 +1064,33 @@ void i915_perf_init(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); + if (!IS_HASWELL(dev)) + return; + + hrtimer_init(&dev_priv->perf.oa.poll_check_timer, + CLOCK_MONOTONIC, HRTIMER_MODE_REL); + dev_priv->perf.oa.poll_check_timer.function = poll_check_timer_cb; + init_waitqueue_head(&dev_priv->perf.oa.poll_wq); + INIT_LIST_HEAD(&dev_priv->perf.streams); mutex_init(&dev_priv->perf.lock); + spin_lock_init(&dev_priv->perf.hook_lock); + + dev_priv->perf.oa.ops.init_oa_buffer = gen7_init_oa_buffer; + dev_priv->perf.oa.ops.enable_metric_set = hsw_enable_metric_set; + dev_priv->perf.oa.ops.disable_metric_set = hsw_disable_metric_set; + dev_priv->perf.oa.ops.oa_enable = gen7_oa_enable; + dev_priv->perf.oa.ops.oa_disable = gen7_oa_disable; + dev_priv->perf.oa.ops.update_hw_ctx_id_locked = gen7_update_hw_ctx_id_locked; + dev_priv->perf.oa.ops.read = gen7_oa_read; + dev_priv->perf.oa.ops.oa_buffer_is_empty = gen7_oa_buffer_is_empty; + + dev_priv->perf.oa.oa_formats = hsw_oa_formats; + + dev_priv->perf.oa.n_builtin_sets = + i915_oa_n_builtin_metric_sets_hsw; + + dev_priv->perf.oa.oa_formats = hsw_oa_formats; dev_priv->perf.initialized = true; } @@ -424,7 +1102,7 @@ void i915_perf_fini(struct drm_device *dev) if (!dev_priv->perf.initialized) return; - /* Currently nothing to clean up */ + dev_priv->perf.oa.ops.init_oa_buffer = NULL; dev_priv->perf.initialized = false; } diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index e64c866ab2abb6..3d9841ccda530e 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -541,6 +541,343 @@ #define GEN7_GPGPU_DISPATCHDIMZ 0x2508 #define GEN7_OACONTROL 0x2360 +#define GEN7_OACONTROL_CTX_MASK 0xFFFFF000 +#define GEN7_OACONTROL_TIMER_PERIOD_MASK 0x3F +#define GEN7_OACONTROL_TIMER_PERIOD_SHIFT 6 +#define GEN7_OACONTROL_TIMER_ENABLE (1<<5) +#define GEN7_OACONTROL_FORMAT_A13 (0<<2) +#define GEN7_OACONTROL_FORMAT_A29 (1<<2) +#define GEN7_OACONTROL_FORMAT_A13_B8_C8 (2<<2) +#define GEN7_OACONTROL_FORMAT_A29_B8_C8 (3<<2) +#define GEN7_OACONTROL_FORMAT_B4_C8 (4<<2) +#define GEN7_OACONTROL_FORMAT_A45_B8_C8 (5<<2) +#define GEN7_OACONTROL_FORMAT_B4_C8_A16 (6<<2) +#define GEN7_OACONTROL_FORMAT_C4_B8 (7<<2) +#define GEN7_OACONTROL_FORMAT_SHIFT 2 +#define GEN7_OACONTROL_PER_CTX_ENABLE (1<<1) +#define GEN7_OACONTROL_ENABLE (1<<0) + +#define GEN8_OACTXID 0x2364 + +#define GEN8_OACONTROL 0x2B00 +#define GEN8_OA_REPORT_FORMAT_A12 (0<<2) +#define GEN8_OA_REPORT_FORMAT_A12_B8_C8 (2<<2) +#define GEN8_OA_REPORT_FORMAT_A36_B8_C8 (5<<2) +#define GEN8_OA_REPORT_FORMAT_C4_B8 (7<<2) +#define GEN8_OA_REPORT_FORMAT_SHIFT 2 +#define GEN8_OA_SPECIFIC_CONTEXT_ENABLE (1<<1) +#define GEN8_OA_COUNTER_ENABLE (1<<0) + +#define GEN8_OACTXCONTROL 0x2360 +#define GEN8_OA_TIMER_PERIOD_MASK 0x3F +#define GEN8_OA_TIMER_PERIOD_SHIFT 2 +#define GEN8_OA_TIMER_ENABLE (1<<1) +#define GEN8_OA_COUNTER_RESUME (1<<0) + +#define GEN7_OABUFFER 0x23B0 /* R/W */ +#define GEN7_OABUFFER_OVERRUN_DISABLE (1<<3) +#define GEN7_OABUFFER_EDGE_TRIGGER (1<<2) +#define GEN7_OABUFFER_STOP_RESUME_ENABLE (1<<1) +#define GEN7_OABUFFER_RESUME (1<<0) + +#define GEN8_OABUFFER 0x2b14 + +#define GEN7_OASTATUS1 0x2364 +#define GEN7_OASTATUS1_TAIL_MASK 0xffffffc0 +#define GEN7_OASTATUS1_COUNTER_OVERFLOW (1<<2) +#define GEN7_OASTATUS1_OABUFFER_OVERFLOW (1<<1) +#define GEN7_OASTATUS1_REPORT_LOST (1<<0) + +#define GEN7_OASTATUS2 0x2368 +#define GEN7_OASTATUS2_HEAD_MASK 0xffffffc0 + +#define GEN8_OASTATUS 0x2b08 +#define GEN8_OASTATUS_OVERRUN_STATUS (1<<3) +#define GEN8_OASTATUS_COUNTER_OVERFLOW (1<<2) +#define GEN8_OASTATUS_OABUFFER_OVERFLOW (1<<1) +#define GEN8_OASTATUS_REPORT_LOST (1<<0) + +#define GEN8_OAHEADPTR 0x2B0C +#define GEN8_OATAILPTR 0x2B10 + +#define OABUFFER_SIZE_128K (0<<3) +#define OABUFFER_SIZE_256K (1<<3) +#define OABUFFER_SIZE_512K (2<<3) +#define OABUFFER_SIZE_1M (3<<3) +#define OABUFFER_SIZE_2M (4<<3) +#define OABUFFER_SIZE_4M (5<<3) +#define OABUFFER_SIZE_8M (6<<3) +#define OABUFFER_SIZE_16M (7<<3) + +#define OA_MEM_SELECT_GGTT (1<<0) + +#define EU_PERF_CNTL0 0xe458 + +#define GDT_CHICKEN_BITS 0x9840 +#define GT_NOA_ENABLE 0x00000080 + +/* + * OA Boolean state + */ + +#define OAREPORTTRIG1 0x2740 +#define OAREPORTTRIG1_THRESHOLD_MASK 0xffff +#define OAREPORTTRIG1_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */ + +#define OAREPORTTRIG2 0x2744 +#define OAREPORTTRIG2_INVERT_A_0 (1<<0) +#define OAREPORTTRIG2_INVERT_A_1 (1<<1) +#define OAREPORTTRIG2_INVERT_A_2 (1<<2) +#define OAREPORTTRIG2_INVERT_A_3 (1<<3) +#define OAREPORTTRIG2_INVERT_A_4 (1<<4) +#define OAREPORTTRIG2_INVERT_A_5 (1<<5) +#define OAREPORTTRIG2_INVERT_A_6 (1<<6) +#define OAREPORTTRIG2_INVERT_A_7 (1<<7) +#define OAREPORTTRIG2_INVERT_A_8 (1<<8) +#define OAREPORTTRIG2_INVERT_A_9 (1<<9) +#define OAREPORTTRIG2_INVERT_A_10 (1<<10) +#define OAREPORTTRIG2_INVERT_A_11 (1<<11) +#define OAREPORTTRIG2_INVERT_A_12 (1<<12) +#define OAREPORTTRIG2_INVERT_A_13 (1<<13) +#define OAREPORTTRIG2_INVERT_A_14 (1<<14) +#define OAREPORTTRIG2_INVERT_A_15 (1<<15) +#define OAREPORTTRIG2_INVERT_B_0 (1<<16) +#define OAREPORTTRIG2_INVERT_B_1 (1<<17) +#define OAREPORTTRIG2_INVERT_B_2 (1<<18) +#define OAREPORTTRIG2_INVERT_B_3 (1<<19) +#define OAREPORTTRIG2_INVERT_C_0 (1<<20) +#define OAREPORTTRIG2_INVERT_C_1 (1<<21) +#define OAREPORTTRIG2_INVERT_D_0 (1<<22) +#define OAREPORTTRIG2_THRESHOLD_ENABLE (1<<23) +#define OAREPORTTRIG2_REPORT_TRIGGER_ENABLE (1<<31) + +#define OAREPORTTRIG3 0x2748 +#define OAREPORTTRIG3_NOA_SELECT_MASK 0xf +#define OAREPORTTRIG3_NOA_SELECT_8_SHIFT 0 +#define OAREPORTTRIG3_NOA_SELECT_9_SHIFT 4 +#define OAREPORTTRIG3_NOA_SELECT_10_SHIFT 8 +#define OAREPORTTRIG3_NOA_SELECT_11_SHIFT 12 +#define OAREPORTTRIG3_NOA_SELECT_12_SHIFT 16 +#define OAREPORTTRIG3_NOA_SELECT_13_SHIFT 20 +#define OAREPORTTRIG3_NOA_SELECT_14_SHIFT 24 +#define OAREPORTTRIG3_NOA_SELECT_15_SHIFT 28 + +#define OAREPORTTRIG4 0x274c +#define OAREPORTTRIG4_NOA_SELECT_MASK 0xf +#define OAREPORTTRIG4_NOA_SELECT_0_SHIFT 0 +#define OAREPORTTRIG4_NOA_SELECT_1_SHIFT 4 +#define OAREPORTTRIG4_NOA_SELECT_2_SHIFT 8 +#define OAREPORTTRIG4_NOA_SELECT_3_SHIFT 12 +#define OAREPORTTRIG4_NOA_SELECT_4_SHIFT 16 +#define OAREPORTTRIG4_NOA_SELECT_5_SHIFT 20 +#define OAREPORTTRIG4_NOA_SELECT_6_SHIFT 24 +#define OAREPORTTRIG4_NOA_SELECT_7_SHIFT 28 + +#define OAREPORTTRIG5 0x2750 +#define OAREPORTTRIG5_THRESHOLD_MASK 0xffff +#define OAREPORTTRIG5_EDGE_LEVEL_TRIGER_SELECT_MASK 0xffff0000 /* 0=level */ + +#define OAREPORTTRIG6 0x2754 +#define OAREPORTTRIG6_INVERT_A_0 (1<<0) +#define OAREPORTTRIG6_INVERT_A_1 (1<<1) +#define OAREPORTTRIG6_INVERT_A_2 (1<<2) +#define OAREPORTTRIG6_INVERT_A_3 (1<<3) +#define OAREPORTTRIG6_INVERT_A_4 (1<<4) +#define OAREPORTTRIG6_INVERT_A_5 (1<<5) +#define OAREPORTTRIG6_INVERT_A_6 (1<<6) +#define OAREPORTTRIG6_INVERT_A_7 (1<<7) +#define OAREPORTTRIG6_INVERT_A_8 (1<<8) +#define OAREPORTTRIG6_INVERT_A_9 (1<<9) +#define OAREPORTTRIG6_INVERT_A_10 (1<<10) +#define OAREPORTTRIG6_INVERT_A_11 (1<<11) +#define OAREPORTTRIG6_INVERT_A_12 (1<<12) +#define OAREPORTTRIG6_INVERT_A_13 (1<<13) +#define OAREPORTTRIG6_INVERT_A_14 (1<<14) +#define OAREPORTTRIG6_INVERT_A_15 (1<<15) +#define OAREPORTTRIG6_INVERT_B_0 (1<<16) +#define OAREPORTTRIG6_INVERT_B_1 (1<<17) +#define OAREPORTTRIG6_INVERT_B_2 (1<<18) +#define OAREPORTTRIG6_INVERT_B_3 (1<<19) +#define OAREPORTTRIG6_INVERT_C_0 (1<<20) +#define OAREPORTTRIG6_INVERT_C_1 (1<<21) +#define OAREPORTTRIG6_INVERT_D_0 (1<<22) +#define OAREPORTTRIG6_THRESHOLD_ENABLE (1<<23) +#define OAREPORTTRIG6_REPORT_TRIGGER_ENABLE (1<<31) + +#define OAREPORTTRIG7 0x2758 +#define OAREPORTTRIG7_NOA_SELECT_MASK 0xf +#define OAREPORTTRIG7_NOA_SELECT_8_SHIFT 0 +#define OAREPORTTRIG7_NOA_SELECT_9_SHIFT 4 +#define OAREPORTTRIG7_NOA_SELECT_10_SHIFT 8 +#define OAREPORTTRIG7_NOA_SELECT_11_SHIFT 12 +#define OAREPORTTRIG7_NOA_SELECT_12_SHIFT 16 +#define OAREPORTTRIG7_NOA_SELECT_13_SHIFT 20 +#define OAREPORTTRIG7_NOA_SELECT_14_SHIFT 24 +#define OAREPORTTRIG7_NOA_SELECT_15_SHIFT 28 + +#define OAREPORTTRIG8 0x275c +#define OAREPORTTRIG8_NOA_SELECT_MASK 0xf +#define OAREPORTTRIG8_NOA_SELECT_0_SHIFT 0 +#define OAREPORTTRIG8_NOA_SELECT_1_SHIFT 4 +#define OAREPORTTRIG8_NOA_SELECT_2_SHIFT 8 +#define OAREPORTTRIG8_NOA_SELECT_3_SHIFT 12 +#define OAREPORTTRIG8_NOA_SELECT_4_SHIFT 16 +#define OAREPORTTRIG8_NOA_SELECT_5_SHIFT 20 +#define OAREPORTTRIG8_NOA_SELECT_6_SHIFT 24 +#define OAREPORTTRIG8_NOA_SELECT_7_SHIFT 28 + +#define OASTARTTRIG1 0x2710 +#define OASTARTTRIG1_THRESHOLD_COUNT_MASK_MBZ 0xffff0000 +#define OASTARTTRIG1_THRESHOLD_MASK 0xffff + +#define OASTARTTRIG2 0x2714 +#define OASTARTTRIG2_INVERT_A_0 (1<<0) +#define OASTARTTRIG2_INVERT_A_1 (1<<1) +#define OASTARTTRIG2_INVERT_A_2 (1<<2) +#define OASTARTTRIG2_INVERT_A_3 (1<<3) +#define OASTARTTRIG2_INVERT_A_4 (1<<4) +#define OASTARTTRIG2_INVERT_A_5 (1<<5) +#define OASTARTTRIG2_INVERT_A_6 (1<<6) +#define OASTARTTRIG2_INVERT_A_7 (1<<7) +#define OASTARTTRIG2_INVERT_A_8 (1<<8) +#define OASTARTTRIG2_INVERT_A_9 (1<<9) +#define OASTARTTRIG2_INVERT_A_10 (1<<10) +#define OASTARTTRIG2_INVERT_A_11 (1<<11) +#define OASTARTTRIG2_INVERT_A_12 (1<<12) +#define OASTARTTRIG2_INVERT_A_13 (1<<13) +#define OASTARTTRIG2_INVERT_A_14 (1<<14) +#define OASTARTTRIG2_INVERT_A_15 (1<<15) +#define OASTARTTRIG2_INVERT_B_0 (1<<16) +#define OASTARTTRIG2_INVERT_B_1 (1<<17) +#define OASTARTTRIG2_INVERT_B_2 (1<<18) +#define OASTARTTRIG2_INVERT_B_3 (1<<19) +#define OASTARTTRIG2_INVERT_C_0 (1<<20) +#define OASTARTTRIG2_INVERT_C_1 (1<<21) +#define OASTARTTRIG2_INVERT_D_0 (1<<22) +#define OASTARTTRIG2_THRESHOLD_ENABLE (1<<23) +#define OASTARTTRIG2_START_TRIG_FLAG_MBZ (1<<24) +#define OASTARTTRIG2_EVENT_SELECT_0 (1<<28) +#define OASTARTTRIG2_EVENT_SELECT_1 (1<<29) +#define OASTARTTRIG2_EVENT_SELECT_2 (1<<30) +#define OASTARTTRIG2_EVENT_SELECT_3 (1<<31) + +#define OASTARTTRIG3 0x2718 +#define OASTARTTRIG3_NOA_SELECT_MASK 0xf +#define OASTARTTRIG3_NOA_SELECT_8_SHIFT 0 +#define OASTARTTRIG3_NOA_SELECT_9_SHIFT 4 +#define OASTARTTRIG3_NOA_SELECT_10_SHIFT 8 +#define OASTARTTRIG3_NOA_SELECT_11_SHIFT 12 +#define OASTARTTRIG3_NOA_SELECT_12_SHIFT 16 +#define OASTARTTRIG3_NOA_SELECT_13_SHIFT 20 +#define OASTARTTRIG3_NOA_SELECT_14_SHIFT 24 +#define OASTARTTRIG3_NOA_SELECT_15_SHIFT 28 + +#define OASTARTTRIG4 0x271c +#define OASTARTTRIG4_NOA_SELECT_MASK 0xf +#define OASTARTTRIG4_NOA_SELECT_0_SHIFT 0 +#define OASTARTTRIG4_NOA_SELECT_1_SHIFT 4 +#define OASTARTTRIG4_NOA_SELECT_2_SHIFT 8 +#define OASTARTTRIG4_NOA_SELECT_3_SHIFT 12 +#define OASTARTTRIG4_NOA_SELECT_4_SHIFT 16 +#define OASTARTTRIG4_NOA_SELECT_5_SHIFT 20 +#define OASTARTTRIG4_NOA_SELECT_6_SHIFT 24 +#define OASTARTTRIG4_NOA_SELECT_7_SHIFT 28 + +#define OASTARTTRIG5 0x2720 +#define OASTARTTRIG5_THRESHOLD_COUNT_MASK_MBZ 0xffff0000 +#define OASTARTTRIG5_THRESHOLD_MASK 0xffff + +#define OASTARTTRIG6 0x2724 +#define OASTARTTRIG6_INVERT_A_0 (1<<0) +#define OASTARTTRIG6_INVERT_A_1 (1<<1) +#define OASTARTTRIG6_INVERT_A_2 (1<<2) +#define OASTARTTRIG6_INVERT_A_3 (1<<3) +#define OASTARTTRIG6_INVERT_A_4 (1<<4) +#define OASTARTTRIG6_INVERT_A_5 (1<<5) +#define OASTARTTRIG6_INVERT_A_6 (1<<6) +#define OASTARTTRIG6_INVERT_A_7 (1<<7) +#define OASTARTTRIG6_INVERT_A_8 (1<<8) +#define OASTARTTRIG6_INVERT_A_9 (1<<9) +#define OASTARTTRIG6_INVERT_A_10 (1<<10) +#define OASTARTTRIG6_INVERT_A_11 (1<<11) +#define OASTARTTRIG6_INVERT_A_12 (1<<12) +#define OASTARTTRIG6_INVERT_A_13 (1<<13) +#define OASTARTTRIG6_INVERT_A_14 (1<<14) +#define OASTARTTRIG6_INVERT_A_15 (1<<15) +#define OASTARTTRIG6_INVERT_B_0 (1<<16) +#define OASTARTTRIG6_INVERT_B_1 (1<<17) +#define OASTARTTRIG6_INVERT_B_2 (1<<18) +#define OASTARTTRIG6_INVERT_B_3 (1<<19) +#define OASTARTTRIG6_INVERT_C_0 (1<<20) +#define OASTARTTRIG6_INVERT_C_1 (1<<21) +#define OASTARTTRIG6_INVERT_D_0 (1<<22) +#define OASTARTTRIG6_THRESHOLD_ENABLE (1<<23) +#define OASTARTTRIG6_START_TRIG_FLAG_MBZ (1<<24) +#define OASTARTTRIG6_EVENT_SELECT_4 (1<<28) +#define OASTARTTRIG6_EVENT_SELECT_5 (1<<29) +#define OASTARTTRIG6_EVENT_SELECT_6 (1<<30) +#define OASTARTTRIG6_EVENT_SELECT_7 (1<<31) + +#define OASTARTTRIG7 0x2728 +#define OASTARTTRIG7_NOA_SELECT_MASK 0xf +#define OASTARTTRIG7_NOA_SELECT_8_SHIFT 0 +#define OASTARTTRIG7_NOA_SELECT_9_SHIFT 4 +#define OASTARTTRIG7_NOA_SELECT_10_SHIFT 8 +#define OASTARTTRIG7_NOA_SELECT_11_SHIFT 12 +#define OASTARTTRIG7_NOA_SELECT_12_SHIFT 16 +#define OASTARTTRIG7_NOA_SELECT_13_SHIFT 20 +#define OASTARTTRIG7_NOA_SELECT_14_SHIFT 24 +#define OASTARTTRIG7_NOA_SELECT_15_SHIFT 28 + +#define OASTARTTRIG8 0x272c +#define OASTARTTRIG8_NOA_SELECT_MASK 0xf +#define OASTARTTRIG8_NOA_SELECT_0_SHIFT 0 +#define OASTARTTRIG8_NOA_SELECT_1_SHIFT 4 +#define OASTARTTRIG8_NOA_SELECT_2_SHIFT 8 +#define OASTARTTRIG8_NOA_SELECT_3_SHIFT 12 +#define OASTARTTRIG8_NOA_SELECT_4_SHIFT 16 +#define OASTARTTRIG8_NOA_SELECT_5_SHIFT 20 +#define OASTARTTRIG8_NOA_SELECT_6_SHIFT 24 +#define OASTARTTRIG8_NOA_SELECT_7_SHIFT 28 + +/* CECX_0 */ +#define OACEC_COMPARE_LESS_OR_EQUAL 6 +#define OACEC_COMPARE_NOT_EQUAL 5 +#define OACEC_COMPARE_LESS_THAN 4 +#define OACEC_COMPARE_GREATER_OR_EQUAL 3 +#define OACEC_COMPARE_EQUAL 2 +#define OACEC_COMPARE_GREATER_THAN 1 +#define OACEC_COMPARE_ANY_EQUAL 0 + +#define OACEC_COMPARE_VALUE_MASK 0xffff +#define OACEC_COMPARE_VALUE_SHIFT 3 + +#define OACEC_SELECT_NOA (0<<19) +#define OACEC_SELECT_PREV (1<<19) +#define OACEC_SELECT_BOOLEAN (2<<19) + +/* CECX_1 */ +#define OACEC_MASK_MASK 0xffff +#define OACEC_CONSIDERATIONS_MASK 0xffff +#define OACEC_CONSIDERATIONS_SHIFT 16 + +#define OACEC0_0 0x2770 +#define OACEC0_1 0x2774 +#define OACEC1_0 0x2778 +#define OACEC1_1 0x277c +#define OACEC2_0 0x2780 +#define OACEC2_1 0x2784 +#define OACEC3_0 0x2788 +#define OACEC3_1 0x278c +#define OACEC4_0 0x2790 +#define OACEC4_1 0x2794 +#define OACEC5_0 0x2798 +#define OACEC5_1 0x279c +#define OACEC6_0 0x27a0 +#define OACEC6_1 0x27a4 +#define OACEC7_0 0x27a8 +#define OACEC7_1 0x27ac + #define _GEN7_PIPEA_DE_LOAD_SL 0x70068 #define _GEN7_PIPEB_DE_LOAD_SL 0x71068 @@ -6750,6 +7087,7 @@ enum skl_disp_power_wells { # define GEN6_RCCUNIT_CLOCK_GATE_DISABLE (1 << 11) #define GEN6_UCGCTL3 0x9408 +# define GEN6_OACSUNIT_CLOCK_GATE_DISABLE (1 << 20) #define GEN7_UCGCTL4 0x940c #define GEN7_L3BANK2X_CLOCK_GATE_DISABLE (1<<25) diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index ff4507eafd5fd4..e747702eb1631a 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -1132,6 +1132,18 @@ struct drm_i915_gem_context_param { __u64 value; }; +enum drm_i915_oa_format { + I915_OA_FORMAT_A13 = 1, + I915_OA_FORMAT_A29, + I915_OA_FORMAT_A13_B8_C8, + I915_OA_FORMAT_B4_C8, + I915_OA_FORMAT_A45_B8_C8, + I915_OA_FORMAT_B4_C8_A16, + I915_OA_FORMAT_C4_B8, + + I915_OA_FORMAT_MAX /* non-ABI */ +}; + #define I915_PERF_FLAG_FD_CLOEXEC (1<<0) #define I915_PERF_FLAG_FD_NONBLOCK (1<<1) #define I915_PERF_FLAG_DISABLED (1<<2) @@ -1144,6 +1156,32 @@ enum drm_i915_perf_property_id { */ DRM_I915_PERF_CTX_HANDLE_PROP = 1, + /** + * A value of 1 requests the inclusion of raw OA unit reports as + * part of stream samples. + */ + DRM_I915_PERF_SAMPLE_OA_PROP, + + /** + * The value specifies which set of OA unit metrics should be + * be configured, defining the contents of any OA unit reports. + */ + DRM_I915_PERF_OA_METRICS_SET_PROP, + + /** + * The value specifies the size and layout of OA unit reports. + */ + DRM_I915_PERF_OA_FORMAT_PROP, + + /** + * Specifying this property implicitly requests periodic OA unit + * sampling and (at least on Haswell) the sampling frequency is derived + * from this exponent as follows: + * + * 80ns * 2^(period_exponent + 1) + */ + DRM_I915_PERF_OA_EXPONENT_PROP, + DRM_I915_PERF_PROP_MAX /* non-ABI */ }; @@ -1185,17 +1223,31 @@ enum drm_i915_perf_record_type { * every sample. * * The order of these sample properties given by userspace has no - * affect on the ordering of data within a sample. The order will be + * affect on the ordering of data within a sample. The order is * documented here. * * struct { * struct drm_i915_perf_record_header header; * - * TODO: itemize extensible sample data here + * { u32 oa_report[]; } && DRM_I915_PERF_SAMPLE_OA_PROP * }; */ DRM_I915_PERF_RECORD_SAMPLE = 1, + /* + * Indicates that one or more OA reports was not written + * by the hardware. + */ + DRM_I915_PERF_RECORD_OA_REPORT_LOST = 2, + + /* + * Indicates that the internal circular buffer that Gen + * graphics writes OA reports into has filled, which may + * either mean that old reports could be overwritten or + * subsequent reports lost until the buffer is cleared. + */ + DRM_I915_PERF_RECORD_OA_BUFFER_OVERFLOW = 3, + DRM_I915_PERF_RECORD_MAX /* non-ABI */ }; From 5af0aef0f13b45e19ee6d67d235fe66629bbe731 Mon Sep 17 00:00:00 2001 From: Robert Bragg Date: Fri, 30 Oct 2015 17:12:12 +0000 Subject: [PATCH 05/21] drm/i915: advertise available metrics via sysfs Each metric set is given a sysfs entry like: /sys/class/drm/card0/metrics//id This allows userspace to enumerate the specific sets that are available for the current system. The 'id' file contains an unsigned integer that can be used to open the associated metric set via DRM_IOCTL_I915_PERF_OPEN. The is a globally unique ID for a specific OA unit configuration that can be reliably used as a key to lookup corresponding counter meta data and normalization equations. Signed-off-by: Robert Bragg --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_oa_hsw.c | 45 ++++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_oa_hsw.h | 4 +++ drivers/gpu/drm/i915/i915_perf.c | 18 +++++++++++- 4 files changed, 68 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d028d2e090c4e4..90efbb5674646f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2030,6 +2030,8 @@ struct drm_i915_private { struct { bool initialized; + struct kobject *metrics_kobj; + struct mutex lock; struct list_head streams; diff --git a/drivers/gpu/drm/i915/i915_oa_hsw.c b/drivers/gpu/drm/i915/i915_oa_hsw.c index c05745e1d567c5..9be5f388727f9e 100644 --- a/drivers/gpu/drm/i915/i915_oa_hsw.c +++ b/drivers/gpu/drm/i915/i915_oa_hsw.c @@ -24,6 +24,8 @@ * */ +#include + #include "i915_drv.h" enum metric_set_id { @@ -130,3 +132,46 @@ int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv) return -ENODEV; } } + +static ssize_t +show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); +} + +static struct device_attribute dev_attr_render_basic_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_render_basic_id, + .store = NULL, +}; + +static struct attribute *attrs_render_basic[] = { + &dev_attr_render_basic_id.attr, + NULL, +}; + +static struct attribute_group group_render_basic = { + .name = "403d8832-1a27-4aa6-a64e-f5389ce7b212", + .attrs = attrs_render_basic, +}; + +int +i915_perf_init_sysfs_hsw(struct drm_i915_private *dev_priv) +{ + int ret; + + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); + if (ret) + goto error_render_basic; + + return 0; + +error_render_basic: + return ret; +} + +void +i915_perf_deinit_sysfs_hsw(struct drm_i915_private *dev_priv) +{ + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); +} diff --git a/drivers/gpu/drm/i915/i915_oa_hsw.h b/drivers/gpu/drm/i915/i915_oa_hsw.h index b618a1f0aa94d7..e4ba89d058fa00 100644 --- a/drivers/gpu/drm/i915/i915_oa_hsw.h +++ b/drivers/gpu/drm/i915/i915_oa_hsw.h @@ -31,4 +31,8 @@ extern int i915_oa_n_builtin_metric_sets_hsw; extern int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv); +extern int i915_perf_init_sysfs_hsw(struct drm_i915_private *dev_priv); + +extern void i915_perf_deinit_sysfs_hsw(struct drm_i915_private *dev_priv); + #endif diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index d62de1af5c572b..cfa1a549ef67fc 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -1067,6 +1067,11 @@ void i915_perf_init(struct drm_device *dev) if (!IS_HASWELL(dev)) return; + dev_priv->perf.metrics_kobj = + kobject_create_and_add("metrics", &dev->primary->kdev->kobj); + if (!dev_priv->perf.metrics_kobj) + return; + hrtimer_init(&dev_priv->perf.oa.poll_check_timer, CLOCK_MONOTONIC, HRTIMER_MODE_REL); dev_priv->perf.oa.poll_check_timer.function = poll_check_timer_cb; @@ -1090,9 +1095,15 @@ void i915_perf_init(struct drm_device *dev) dev_priv->perf.oa.n_builtin_sets = i915_oa_n_builtin_metric_sets_hsw; - dev_priv->perf.oa.oa_formats = hsw_oa_formats; + if (i915_perf_init_sysfs_hsw(dev_priv)) { + kobject_put(dev_priv->perf.metrics_kobj); + dev_priv->perf.metrics_kobj = NULL; + return; + } dev_priv->perf.initialized = true; + + return; } void i915_perf_fini(struct drm_device *dev) @@ -1102,6 +1113,11 @@ void i915_perf_fini(struct drm_device *dev) if (!dev_priv->perf.initialized) return; + i915_perf_deinit_sysfs_hsw(dev_priv); + + kobject_put(dev_priv->perf.metrics_kobj); + dev_priv->perf.metrics_kobj = NULL; + dev_priv->perf.oa.ops.init_oa_buffer = NULL; dev_priv->perf.initialized = false; From 171307affcd27ca45730e6a20972adbeefb020c9 Mon Sep 17 00:00:00 2001 From: Robert Bragg Date: Wed, 4 Mar 2015 15:59:25 +0000 Subject: [PATCH 06/21] drm/i915: Add dev.i915.perf_event_paranoid sysctl option Consistent with the kernel.perf_event_paranoid sysctl option that can allow non-root users to access system wide cpu metrics, this can optionally allow non-root users to access system wide OA counter metrics from Gen graphics hardware. Signed-off-by: Robert Bragg --- drivers/gpu/drm/i915/i915_drv.h | 1 + drivers/gpu/drm/i915/i915_perf.c | 46 +++++++++++++++++++++++++++++++- 2 files changed, 46 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 90efbb5674646f..01a37afebecf4e 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2031,6 +2031,7 @@ struct drm_i915_private { bool initialized; struct kobject *metrics_kobj; + struct ctl_table_header *sysctl_header; struct mutex lock; struct list_head streams; diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index cfa1a549ef67fc..61a86f04855286 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -37,6 +37,8 @@ #define POLL_FREQUENCY 200 #define POLL_PERIOD max_t(u64, 10000, NSEC_PER_SEC / POLL_FREQUENCY) +static u32 i915_perf_stream_paranoid = true; + #define OA_EXPONENT_MAX 0x3f static struct i915_oa_format hsw_oa_formats[I915_OA_FORMAT_MAX] = { @@ -866,7 +868,13 @@ int i915_perf_open_ioctl_locked(struct drm_device *dev, } } - if (!specific_ctx && !capable(CAP_SYS_ADMIN)) { + /* Similar to perf's kernel.perf_paranoid_cpu sysctl option + * we check a dev.i915.perf_stream_paranoid sysctl option + * to determine if it's ok to access system wide OA counters + * without CAP_SYS_ADMIN privileges. + */ + if (!specific_ctx && + i915_perf_stream_paranoid && !capable(CAP_SYS_ADMIN)) { DRM_ERROR("Insufficient privileges to open system-wide i915 perf stream\n"); ret = -EACCES; goto err_ctx; @@ -1060,6 +1068,38 @@ int i915_perf_open_ioctl(struct drm_device *dev, void *data, return ret; } + +static struct ctl_table oa_table[] = { + { + .procname = "perf_stream_paranoid", + .data = &i915_perf_stream_paranoid, + .maxlen = sizeof(i915_perf_stream_paranoid), + .mode = 0644, + .proc_handler = proc_dointvec, + }, + {} +}; + +static struct ctl_table i915_root[] = { + { + .procname = "i915", + .maxlen = 0, + .mode = 0555, + .child = oa_table, + }, + {} +}; + +static struct ctl_table dev_root[] = { + { + .procname = "dev", + .maxlen = 0, + .mode = 0555, + .child = i915_root, + }, + {} +}; + void i915_perf_init(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); @@ -1101,6 +1141,8 @@ void i915_perf_init(struct drm_device *dev) return; } + dev_priv->perf.sysctl_header = register_sysctl_table(dev_root); + dev_priv->perf.initialized = true; return; @@ -1113,6 +1155,8 @@ void i915_perf_fini(struct drm_device *dev) if (!dev_priv->perf.initialized) return; + unregister_sysctl_table(dev_priv->perf.sysctl_header); + i915_perf_deinit_sysfs_hsw(dev_priv); kobject_put(dev_priv->perf.metrics_kobj); From 77127907b72acb54c85f0088abf7c332f86cef96 Mon Sep 17 00:00:00 2001 From: Robert Bragg Date: Wed, 15 Jul 2015 18:47:15 +0100 Subject: [PATCH 07/21] drm/i915: add oa_event_min_timer_exponent sysctl The minimal sampling period is now configurable via a dev.i915.oa_min_timer_exponent sysctl parameter. Following the precedent set by perf, the default is the minimum that won't (on its own) exceed the default kernel.perf_event_max_sample_rate default of 100000 samples/s. Signed-off-by: Robert Bragg --- drivers/gpu/drm/i915/i915_perf.c | 40 +++++++++++++++++++++++--------- 1 file changed, 29 insertions(+), 11 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 61a86f04855286..5aa49127487349 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -41,6 +41,23 @@ static u32 i915_perf_stream_paranoid = true; #define OA_EXPONENT_MAX 0x3f +/* for sysctl proc_dointvec_minmax of i915_oa_min_timer_exponent */ +static int zero; +static int oa_exponent_max = OA_EXPONENT_MAX; + +/* Theoretically we can program the OA unit to sample every 160ns but don't + * allow that by default unless root... + * + * The period is derived from the exponent as: + * + * period = 80ns * 2^(exponent + 1) + * + * Referring to perf's kernel.perf_event_max_sample_rate for a precedent + * (100000 by default); with an OA exponent of 6 we get a period of 10.240 + * microseconds - just under 100000Hz + */ +static u32 i915_oa_min_timer_exponent = 6; + static struct i915_oa_format hsw_oa_formats[I915_OA_FORMAT_MAX] = { [I915_OA_FORMAT_A13] = { 0, 64 }, [I915_OA_FORMAT_A29] = { 1, 128 }, @@ -1006,20 +1023,12 @@ static int read_properties_unlocked(struct drm_i915_private *dev_priv, if (value > OA_EXPONENT_MAX) return -EINVAL; - /* NB: The exponent represents a period as follows: - * - * 80ns * 2^(period_exponent + 1) - * - * Theoretically we can program the OA unit to sample + /* Theoretically we can program the OA unit to sample * every 160ns but don't allow that by default unless * root. - * - * Referring to perf's - * kernel.perf_event_max_sample_rate for a precedent - * (100000 by default); with an OA exponent of 6 we get - * a period of 10.240 microseconds -just under 100000Hz */ - if (value < 6 && !capable(CAP_SYS_ADMIN)) { + if (value < i915_oa_min_timer_exponent && + !capable(CAP_SYS_ADMIN)) { DRM_ERROR("Sampling period too high without root privileges\n"); return -EACCES; } @@ -1077,6 +1086,15 @@ static struct ctl_table oa_table[] = { .mode = 0644, .proc_handler = proc_dointvec, }, + { + .procname = "oa_min_timer_exponent", + .data = &i915_oa_min_timer_exponent, + .maxlen = sizeof(i915_oa_min_timer_exponent), + .mode = 0644, + .proc_handler = proc_dointvec_minmax, + .extra1 = &zero, + .extra2 = &oa_exponent_max, + }, {} }; From 984db7441ba1baa073387398bf7a24c76f73fb39 Mon Sep 17 00:00:00 2001 From: Robert Bragg Date: Tue, 22 Sep 2015 14:46:05 +0100 Subject: [PATCH 08/21] drm/i915: Add more Haswell OA metric sets This adds 'compute', 'compute extended', 'memory reads', 'memory writes' and 'sampler balance' metric sets for Haswell. Signed-off-by: Robert Bragg --- drivers/gpu/drm/i915/i915_oa_hsw.c | 483 ++++++++++++++++++++++++++++- 1 file changed, 482 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/i915_oa_hsw.c b/drivers/gpu/drm/i915/i915_oa_hsw.c index 9be5f388727f9e..6f94619663f207 100644 --- a/drivers/gpu/drm/i915/i915_oa_hsw.c +++ b/drivers/gpu/drm/i915/i915_oa_hsw.c @@ -30,9 +30,14 @@ enum metric_set_id { METRIC_SET_ID_RENDER_BASIC = 1, + METRIC_SET_ID_COMPUTE_BASIC, + METRIC_SET_ID_COMPUTE_EXTENDED, + METRIC_SET_ID_MEMORY_READS, + METRIC_SET_ID_MEMORY_WRITES, + METRIC_SET_ID_SAMPLER_BALANCE, }; -int i915_oa_n_builtin_metric_sets_hsw = 1; +int i915_oa_n_builtin_metric_sets_hsw = 6; static const struct i915_oa_reg b_counter_config_render_basic[] = { { 0x2724, 0x00800000 }, @@ -118,6 +123,332 @@ static int select_render_basic_config(struct drm_i915_private *dev_priv) return 0; } +static const struct i915_oa_reg b_counter_config_compute_basic[] = { + { 0x2710, 0x00000000 }, + { 0x2714, 0x00800000 }, + { 0x2718, 0xAAAAAAAA }, + { 0x271C, 0xAAAAAAAA }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x00800000 }, + { 0x2728, 0xAAAAAAAA }, + { 0x272C, 0xAAAAAAAA }, + { 0x2740, 0x00000000 }, + { 0x2744, 0x00000000 }, + { 0x2748, 0x00000000 }, + { 0x274C, 0x00000000 }, + { 0x2750, 0x00000000 }, + { 0x2754, 0x00000000 }, + { 0x2758, 0x00000000 }, + { 0x275C, 0x00000000 }, +}; + +static const struct i915_oa_reg mux_config_compute_basic[] = { + { 0x253A4, 0x00000000 }, + { 0x2681C, 0x01F00800 }, + { 0x26820, 0x00001000 }, + { 0x2781C, 0x01F00800 }, + { 0x26520, 0x00000007 }, + { 0x265A0, 0x00000007 }, + { 0x25380, 0x00000010 }, + { 0x2538C, 0x00300000 }, + { 0x25384, 0xAA8AAAAA }, + { 0x25404, 0xFFFFFFFF }, + { 0x26800, 0x00004202 }, + { 0x26808, 0x00605817 }, + { 0x2680C, 0x10001005 }, + { 0x26804, 0x00000000 }, + { 0x27800, 0x00000102 }, + { 0x27808, 0x0C0701E0 }, + { 0x2780C, 0x000200A0 }, + { 0x27804, 0x00000000 }, + { 0x26484, 0x44000000 }, + { 0x26704, 0x44000000 }, + { 0x26500, 0x00000006 }, + { 0x26510, 0x00000001 }, + { 0x26504, 0x88000000 }, + { 0x26580, 0x00000006 }, + { 0x26590, 0x00000020 }, + { 0x26584, 0x00000000 }, + { 0x26104, 0x55822222 }, + { 0x26184, 0xAA866666 }, + { 0x25420, 0x08320C83 }, + { 0x25424, 0x06820C83 }, + { 0x2541C, 0x00000000 }, + { 0x25428, 0x00000C03 }, +}; + +static int select_compute_basic_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_compute_basic; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_compute_basic); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_compute_basic; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_compute_basic); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_compute_extended[] = { + { 0x2724, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2710, 0x00000000 }, + { 0x2770, 0x0007fe2a }, + { 0x2774, 0x0000ff00 }, + { 0x2778, 0x0007fe6a }, + { 0x277c, 0x0000ff00 }, + { 0x2780, 0x0007fe92 }, + { 0x2784, 0x0000ff00 }, + { 0x2788, 0x0007fea2 }, + { 0x278c, 0x0000ff00 }, + { 0x2790, 0x0007fe32 }, + { 0x2794, 0x0000ff00 }, + { 0x2798, 0x0007fe9a }, + { 0x279c, 0x0000ff00 }, + { 0x27a0, 0x0007ff23 }, + { 0x27a4, 0x0000ff00 }, + { 0x27a8, 0x0007fff3 }, + { 0x27ac, 0x0000fffe }, +}; + +static const struct i915_oa_reg mux_config_compute_extended[] = { + { 0x2681C, 0x3EB00800 }, + { 0x26820, 0x00900000 }, + { 0x25384, 0x02AAAAAA }, + { 0x25404, 0x03FFFFFF }, + { 0x26800, 0x00142284 }, + { 0x26808, 0x0E629062 }, + { 0x2680C, 0x3F6F55CB }, + { 0x26810, 0x00000014 }, + { 0x26804, 0x00000000 }, + { 0x26104, 0x02AAAAAA }, + { 0x26184, 0x02AAAAAA }, + { 0x25420, 0x00000000 }, + { 0x25424, 0x00000000 }, + { 0x2541C, 0x00000000 }, + { 0x25428, 0x00000000 }, +}; + +static int select_compute_extended_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_compute_extended; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_compute_extended); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_compute_extended; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_compute_extended); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_memory_reads[] = { + { 0x2724, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2710, 0x00000000 }, + { 0x274c, 0x76543298 }, + { 0x2748, 0x98989898 }, + { 0x2744, 0x000000e4 }, + { 0x2740, 0x00000000 }, + { 0x275c, 0x98a98a98 }, + { 0x2758, 0x88888888 }, + { 0x2754, 0x000c5500 }, + { 0x2750, 0x00000000 }, + { 0x2770, 0x0007f81a }, + { 0x2774, 0x0000fc00 }, + { 0x2778, 0x0007f82a }, + { 0x277c, 0x0000fc00 }, + { 0x2780, 0x0007f872 }, + { 0x2784, 0x0000fc00 }, + { 0x2788, 0x0007f8ba }, + { 0x278c, 0x0000fc00 }, + { 0x2790, 0x0007f87a }, + { 0x2794, 0x0000fc00 }, + { 0x2798, 0x0007f8ea }, + { 0x279c, 0x0000fc00 }, + { 0x27a0, 0x0007f8e2 }, + { 0x27a4, 0x0000fc00 }, + { 0x27a8, 0x0007f8f2 }, + { 0x27ac, 0x0000fc00 }, +}; + +static const struct i915_oa_reg mux_config_memory_reads[] = { + { 0x253A4, 0x34300000 }, + { 0x25440, 0x2D800000 }, + { 0x25444, 0x00000008 }, + { 0x25128, 0x0E600000 }, + { 0x25380, 0x00000450 }, + { 0x25390, 0x00052C43 }, + { 0x25384, 0x00000000 }, + { 0x25400, 0x00006144 }, + { 0x25408, 0x0A418820 }, + { 0x2540C, 0x000820E6 }, + { 0x25404, 0xFF500000 }, + { 0x25100, 0x000005D6 }, + { 0x2510C, 0x0EF00000 }, + { 0x25104, 0x00000000 }, + { 0x25420, 0x02108421 }, + { 0x25424, 0x00008421 }, + { 0x2541C, 0x00000000 }, + { 0x25428, 0x00000000 }, +}; + +static int select_memory_reads_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_memory_reads; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_memory_reads); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_memory_reads; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_memory_reads); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_memory_writes[] = { + { 0x2724, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2710, 0x00000000 }, + { 0x274c, 0x76543298 }, + { 0x2748, 0x98989898 }, + { 0x2744, 0x000000e4 }, + { 0x2740, 0x00000000 }, + { 0x275c, 0xbabababa }, + { 0x2758, 0x88888888 }, + { 0x2754, 0x000c5500 }, + { 0x2750, 0x00000000 }, + { 0x2770, 0x0007f81a }, + { 0x2774, 0x0000fc00 }, + { 0x2778, 0x0007f82a }, + { 0x277c, 0x0000fc00 }, + { 0x2780, 0x0007f822 }, + { 0x2784, 0x0000fc00 }, + { 0x2788, 0x0007f8ba }, + { 0x278c, 0x0000fc00 }, + { 0x2790, 0x0007f87a }, + { 0x2794, 0x0000fc00 }, + { 0x2798, 0x0007f8ea }, + { 0x279c, 0x0000fc00 }, + { 0x27a0, 0x0007f8e2 }, + { 0x27a4, 0x0000fc00 }, + { 0x27a8, 0x0007f8f2 }, + { 0x27ac, 0x0000fc00 }, +}; + +static const struct i915_oa_reg mux_config_memory_writes[] = { + { 0x253A4, 0x34300000 }, + { 0x25440, 0x01500000 }, + { 0x25444, 0x00000120 }, + { 0x25128, 0x0C200000 }, + { 0x25380, 0x00000450 }, + { 0x25390, 0x00052C43 }, + { 0x25384, 0x00000000 }, + { 0x25400, 0x00007184 }, + { 0x25408, 0x0A418820 }, + { 0x2540C, 0x000820E6 }, + { 0x25404, 0xFF500000 }, + { 0x25100, 0x000005D6 }, + { 0x2510C, 0x1E700000 }, + { 0x25104, 0x00000000 }, + { 0x25420, 0x02108421 }, + { 0x25424, 0x00008421 }, + { 0x2541C, 0x00000000 }, + { 0x25428, 0x00000000 }, +}; + +static int select_memory_writes_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_memory_writes; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_memory_writes); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_memory_writes; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_memory_writes); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_sampler_balance[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0x00800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x00800000 }, +}; + +static const struct i915_oa_reg mux_config_sampler_balance[] = { + { 0x2eb9c, 0x01906400 }, + { 0x2fb9c, 0x01906400 }, + { 0x253a4, 0x00000000 }, + { 0x26b9c, 0x01906400 }, + { 0x27b9c, 0x01906400 }, + { 0x27104, 0x00a00000 }, + { 0x27184, 0x00a50000 }, + { 0x2e804, 0x00500000 }, + { 0x2e984, 0x00500000 }, + { 0x2eb04, 0x00500000 }, + { 0x2eb80, 0x00000084 }, + { 0x2eb8c, 0x14200000 }, + { 0x2eb84, 0x00000000 }, + { 0x2f804, 0x00050000 }, + { 0x2f984, 0x00050000 }, + { 0x2fb04, 0x00050000 }, + { 0x2fb80, 0x00000084 }, + { 0x2fb8c, 0x00050800 }, + { 0x2fb84, 0x00000000 }, + { 0x25380, 0x00000010 }, + { 0x2538c, 0x000000c0 }, + { 0x25384, 0xaa550000 }, + { 0x25404, 0xffffc000 }, + { 0x26804, 0x50000000 }, + { 0x26984, 0x50000000 }, + { 0x26b04, 0x50000000 }, + { 0x26b80, 0x00000084 }, + { 0x26b90, 0x00050800 }, + { 0x26b84, 0x00000000 }, + { 0x27804, 0x05000000 }, + { 0x27984, 0x05000000 }, + { 0x27b04, 0x05000000 }, + { 0x27b80, 0x00000084 }, + { 0x27b90, 0x00000142 }, + { 0x27b84, 0x00000000 }, + { 0x26104, 0xa0000000 }, + { 0x26184, 0xa5000000 }, + { 0x25424, 0x00008620 }, + { 0x2541c, 0x00000000 }, + { 0x25428, 0x0004a54a }, +}; + +static int select_sampler_balance_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_sampler_balance; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_sampler_balance); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_sampler_balance; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_sampler_balance); + + return 0; +} + int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv) { dev_priv->perf.oa.mux_regs = NULL; @@ -128,6 +459,16 @@ int i915_oa_select_metric_set_hsw(struct drm_i915_private *dev_priv) switch (dev_priv->perf.oa.metrics_set) { case METRIC_SET_ID_RENDER_BASIC: return select_render_basic_config(dev_priv); + case METRIC_SET_ID_COMPUTE_BASIC: + return select_compute_basic_config(dev_priv); + case METRIC_SET_ID_COMPUTE_EXTENDED: + return select_compute_extended_config(dev_priv); + case METRIC_SET_ID_MEMORY_READS: + return select_memory_reads_config(dev_priv); + case METRIC_SET_ID_MEMORY_WRITES: + return select_memory_writes_config(dev_priv); + case METRIC_SET_ID_SAMPLER_BALANCE: + return select_sampler_balance_config(dev_priv); default: return -ENODEV; } @@ -155,6 +496,116 @@ static struct attribute_group group_render_basic = { .attrs = attrs_render_basic, }; +static ssize_t +show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); +} + +static struct device_attribute dev_attr_compute_basic_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_compute_basic_id, + .store = NULL, +}; + +static struct attribute *attrs_compute_basic[] = { + &dev_attr_compute_basic_id.attr, + NULL, +}; + +static struct attribute_group group_compute_basic = { + .name = "39ad14bc-2380-45c4-91eb-fbcb3aa7ae7b", + .attrs = attrs_compute_basic, +}; + +static ssize_t +show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); +} + +static struct device_attribute dev_attr_compute_extended_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_compute_extended_id, + .store = NULL, +}; + +static struct attribute *attrs_compute_extended[] = { + &dev_attr_compute_extended_id.attr, + NULL, +}; + +static struct attribute_group group_compute_extended = { + .name = "3865be28-6982-49fe-9494-e4d1b4795413", + .attrs = attrs_compute_extended, +}; + +static ssize_t +show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); +} + +static struct device_attribute dev_attr_memory_reads_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_memory_reads_id, + .store = NULL, +}; + +static struct attribute *attrs_memory_reads[] = { + &dev_attr_memory_reads_id.attr, + NULL, +}; + +static struct attribute_group group_memory_reads = { + .name = "bb5ed49b-2497-4095-94f6-26ba294db88a", + .attrs = attrs_memory_reads, +}; + +static ssize_t +show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); +} + +static struct device_attribute dev_attr_memory_writes_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_memory_writes_id, + .store = NULL, +}; + +static struct attribute *attrs_memory_writes[] = { + &dev_attr_memory_writes_id.attr, + NULL, +}; + +static struct attribute_group group_memory_writes = { + .name = "3358d639-9b5f-45ab-976d-9b08cbfc6240", + .attrs = attrs_memory_writes, +}; + +static ssize_t +show_sampler_balance_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_BALANCE); +} + +static struct device_attribute dev_attr_sampler_balance_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_sampler_balance_id, + .store = NULL, +}; + +static struct attribute *attrs_sampler_balance[] = { + &dev_attr_sampler_balance_id.attr, + NULL, +}; + +static struct attribute_group group_sampler_balance = { + .name = "bc274488-b4b6-40c7-90da-b77d7ad16189", + .attrs = attrs_sampler_balance, +}; + int i915_perf_init_sysfs_hsw(struct drm_i915_private *dev_priv) { @@ -163,9 +614,34 @@ i915_perf_init_sysfs_hsw(struct drm_i915_private *dev_priv) ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); if (ret) goto error_render_basic; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); + if (ret) + goto error_compute_basic; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); + if (ret) + goto error_compute_extended; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); + if (ret) + goto error_memory_reads; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); + if (ret) + goto error_memory_writes; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_balance); + if (ret) + goto error_sampler_balance; return 0; +error_sampler_balance: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); +error_memory_writes: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); +error_memory_reads: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); +error_compute_extended: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); +error_compute_basic: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); error_render_basic: return ret; } @@ -174,4 +650,9 @@ void i915_perf_deinit_sysfs_hsw(struct drm_i915_private *dev_priv) { sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_balance); } From d111e12aa81806bd197f71368d8f6ccc86dd3212 Mon Sep 17 00:00:00 2001 From: Robert Bragg Date: Wed, 10 Jun 2015 21:46:59 +0100 Subject: [PATCH 09/21] drm/i915: start tracking device_info slice_mask The mask of slices enabled sometimes affects what Observability counters are exposed for a particular metric set configuration and so userspace needs the mask to be able to correctly normalize the raw data. Signed-off-by: Robert Bragg --- drivers/gpu/drm/i915/i915_dma.c | 3 +++ drivers/gpu/drm/i915/i915_drv.h | 1 + 2 files changed, 4 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 4d8676d53892be..9cc6abfc95c9ad 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -554,6 +554,7 @@ static void cherryview_sseu_info_init(struct drm_device *dev) info = (struct intel_device_info *)&dev_priv->info; fuse = I915_READ(CHV_FUSE_GT); + info->slice_mask = 1; info->slice_total = 1; if (!(fuse & CHV_FGT_DISABLE_SS0)) { @@ -604,6 +605,7 @@ static void gen9_sseu_info_init(struct drm_device *dev) ss_disable = (fuse2 & GEN9_F2_SS_DIS_MASK) >> GEN9_F2_SS_DIS_SHIFT; + info->slice_mask = s_enable; info->slice_total = hweight32(s_enable); /* * The subslice disable field is global, i.e. it applies @@ -690,6 +692,7 @@ static void broadwell_sseu_info_init(struct drm_device *dev) info = (struct intel_device_info *)&dev_priv->info; + info->slice_mask = s_enable; info->slice_total = hweight32(s_enable); /* diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 01a37afebecf4e..4f9b75e8807756 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -806,6 +806,7 @@ struct intel_device_info { u8 subslice_per_slice; u8 eu_total; u8 eu_per_subslice; + u32 slice_mask; /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ u8 subslice_7eu[3]; u8 has_slice_pg:1; From 65c8b1fc5e791344d477d33e1a9520c03702b892 Mon Sep 17 00:00:00 2001 From: Robert Bragg Date: Tue, 16 Jun 2015 15:08:14 +0100 Subject: [PATCH 10/21] drm/i915: expose _SLICE_MASK GETPARM Enables userspace to determine the number of slices enabled and also know what specific slices are enabled. This information is required, for example, to be able to analyse some OA counter reports where the counter configuration depends on the HW slice configuration. Signed-off-by: Robert Bragg --- drivers/gpu/drm/i915/i915_dma.c | 5 +++++ include/uapi/drm/i915_drm.h | 1 + 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 9cc6abfc95c9ad..749c8305c1ec23 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -170,6 +170,11 @@ static int i915_getparam(struct drm_device *dev, void *data, case I915_PARAM_HAS_RESOURCE_STREAMER: value = HAS_RESOURCE_STREAMER(dev); break; + case I915_PARAM_SLICE_MASK: + value = INTEL_INFO(dev_priv)->slice_mask; + if (!value) + return -ENODEV; + break; default: DRM_DEBUG("Unknown parameter %d\n", param->param); return -EINVAL; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index e747702eb1631a..5ae528c4a3eb19 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -358,6 +358,7 @@ typedef struct drm_i915_irq_wait { #define I915_PARAM_EU_TOTAL 34 #define I915_PARAM_HAS_GPU_RESET 35 #define I915_PARAM_HAS_RESOURCE_STREAMER 36 +#define I915_PARAM_SLICE_MASK 45 /* XXX: rebase before landing */ typedef struct drm_i915_getparam { __s32 param; From c9e71d5da57b91cc4884ce2d48c6ad90add0eeb8 Mon Sep 17 00:00:00 2001 From: Robert Bragg Date: Thu, 11 Jun 2015 14:01:50 +0100 Subject: [PATCH 11/21] drm/i915: start tracking device_info subslice_mask Not assuming the subslice mask is uniform across all slices this mask covers all slices with N bits per slice, where N is the maximum number of slices for a particular Gen. Notably this matches the definition of the $SubsliceMask variable that is currently found in out OA metrics XML files. Notably this updates the ss_max constant (max number of sub slices) from 4 to 3 because although the FUSE2 register provides a 4 bit mask, gen 9 configurations really only go up to a maximum of 3 slices, with bit 3 in the FUSE2 subslice disabled mask always set. Cc: Zhenyu Wang Signed-off-by: Robert Bragg --- drivers/gpu/drm/i915/i915_dma.c | 29 ++++++++++++++++++++++++----- drivers/gpu/drm/i915/i915_drv.h | 1 + 2 files changed, 25 insertions(+), 5 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 749c8305c1ec23..06976b0085d737 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -561,8 +561,10 @@ static void cherryview_sseu_info_init(struct drm_device *dev) info->slice_mask = 1; info->slice_total = 1; + info->subslice_mask = 0; if (!(fuse & CHV_FGT_DISABLE_SS0)) { + info->subslice_mask |= 0x1; info->subslice_per_slice++; eu_dis = fuse & (CHV_FGT_EU_DIS_SS0_R0_MASK | CHV_FGT_EU_DIS_SS0_R1_MASK); @@ -570,6 +572,7 @@ static void cherryview_sseu_info_init(struct drm_device *dev) } if (!(fuse & CHV_FGT_DISABLE_SS1)) { + info->subslice_mask |= 0x2; info->subslice_per_slice++; eu_dis = fuse & (CHV_FGT_EU_DIS_SS1_R0_MASK | CHV_FGT_EU_DIS_SS1_R1_MASK); @@ -598,9 +601,9 @@ static void gen9_sseu_info_init(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; struct intel_device_info *info; - int s_max = 3, ss_max = 4, eu_max = 8; + int s_max = 3, ss_max = 3, eu_max = 8; int s, ss; - u32 fuse2, s_enable, ss_disable, eu_disable; + u32 fuse2, s_enable, ss_disable, eu_disable, ss_mask; u8 eu_mask = 0xff; info = (struct intel_device_info *)&dev_priv->info; @@ -612,10 +615,18 @@ static void gen9_sseu_info_init(struct drm_device *dev) info->slice_mask = s_enable; info->slice_total = hweight32(s_enable); + /* * The subslice disable field is global, i.e. it applies - * to each of the enabled slices. - */ + * to each of the enabled slices. We generalise this into + * a mask covering all slices... + */ + ss_mask = ss_disable ^ ((1 << ss_max) - 1); + for (s = 0; s < s_max; s++) { + if (s_enable & (0x1 << s)) + info->subslice_mask |= ss_mask << (ss_max * s); + } + info->subslice_per_slice = ss_max - hweight32(ss_disable); info->subslice_total = info->slice_total * info->subslice_per_slice; @@ -682,6 +693,7 @@ static void broadwell_sseu_info_init(struct drm_device *dev) const int s_max = 3, ss_max = 3, eu_max = 8; int s, ss; u32 fuse2, eu_disable[s_max], s_enable, ss_disable; + u32 ss_mask; fuse2 = I915_READ(GEN8_FUSE2); s_enable = (fuse2 & GEN8_F2_S_ENA_MASK) >> GEN8_F2_S_ENA_SHIFT; @@ -702,8 +714,15 @@ static void broadwell_sseu_info_init(struct drm_device *dev) /* * The subslice disable field is global, i.e. it applies - * to each of the enabled slices. + * to each of the enabled slices. We generalize this into + * a mask covering all slices... */ + ss_mask = ss_disable ^ ((1 << ss_max) - 1); + for (s = 0; s < s_max; s++) { + if (s_enable & (0x1 << s)) + info->subslice_mask |= ss_mask << (ss_max * s); + } + info->subslice_per_slice = ss_max - hweight32(ss_disable); info->subslice_total = info->slice_total * info->subslice_per_slice; diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 4f9b75e8807756..cb9a1915040444 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -807,6 +807,7 @@ struct intel_device_info { u8 eu_total; u8 eu_per_subslice; u32 slice_mask; + u32 subslice_mask; /* For each slice, which subslice(s) has(have) 7 EUs (bitfield)? */ u8 subslice_7eu[3]; u8 has_slice_pg:1; From 85be763880ea3238a794887361dde9bea9470f4c Mon Sep 17 00:00:00 2001 From: Robert Bragg Date: Tue, 16 Jun 2015 15:09:28 +0100 Subject: [PATCH 12/21] drm/i915: expose _SUBSLICE_MASK GETPARM Assuming a uniform mask across all slices, this enables userspace to determine the specific sub slices enabled. This information is required, for example, to be able to analyse some OA counter reports where the counter configuration depends on the HW sub slice configuration. Signed-off-by: Robert Bragg --- drivers/gpu/drm/i915/i915_dma.c | 5 +++++ include/uapi/drm/i915_drm.h | 1 + 2 files changed, 6 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_dma.c b/drivers/gpu/drm/i915/i915_dma.c index 06976b0085d737..d1365ee4d8f7df 100644 --- a/drivers/gpu/drm/i915/i915_dma.c +++ b/drivers/gpu/drm/i915/i915_dma.c @@ -175,6 +175,11 @@ static int i915_getparam(struct drm_device *dev, void *data, if (!value) return -ENODEV; break; + case I915_PARAM_SUBSLICE_MASK: + value = INTEL_INFO(dev_priv)->subslice_mask; + if (!value) + return -ENODEV; + break; default: DRM_DEBUG("Unknown parameter %d\n", param->param); return -EINVAL; diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 5ae528c4a3eb19..68f2bb64094154 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -359,6 +359,7 @@ typedef struct drm_i915_irq_wait { #define I915_PARAM_HAS_GPU_RESET 35 #define I915_PARAM_HAS_RESOURCE_STREAMER 36 #define I915_PARAM_SLICE_MASK 45 /* XXX: rebase before landing */ +#define I915_PARAM_SUBSLICE_MASK 46 typedef struct drm_i915_getparam { __s32 param; From a31ac4169f026d5df81f5434f331fc05ebcb38ac Mon Sep 17 00:00:00 2001 From: Sourab Gupta Date: Thu, 30 Jul 2015 09:55:18 +0530 Subject: [PATCH 13/21] drm/i915: Introduce global id for contexts The current context user handles are specific to drm file instance. There are some usecases, which may require a global id for the contexts. For e.g. a system level GPU profiler tool may lean upon the global context ids to associate the performance snapshots with individual contexts. This global id may also be used further in order to provide a unique context id to hw. In this patch, the global ids are allocated from a separate cyclic idr and can be further utilized for any usecase described above. v2: According to Chris' suggestion, implemented a separate idr for holding global ids for contexts, as opposed to overloading the file specific ctx->user_handle for this purpose. This global id can also further be used wherever hw has to be programmed with ctx unique id, though this patch just introduces the hw global id as such. Signed-off-by: Sourab Gupta --- drivers/gpu/drm/i915/i915_drv.h | 3 +++ drivers/gpu/drm/i915/i915_gem_context.c | 21 +++++++++++++++++++++ 2 files changed, 24 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index cb9a1915040444..1d2ae56a4b6ceb 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -873,6 +873,7 @@ struct i915_ctx_hang_stats { struct intel_context { struct kref ref; int user_handle; + int global_id; uint8_t remap_slice; struct drm_i915_private *i915; int flags; @@ -1865,6 +1866,8 @@ struct drm_i915_private { bool preserve_bios_swizzle; + struct idr global_ctx_idr; + /* overlay */ struct intel_overlay *overlay; diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index b8d2d41c68f09d..3697962d1d9ef2 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -256,6 +256,18 @@ __create_hw_context(struct drm_device *dev, ctx->file_priv = file_priv; ctx->user_handle = ret; + + /* TODO: If required, this global id can be used for programming the hw + * fields too. In that case, we'll have take care of hw restrictions + * while allocating idr. e.g. for some hw, we may not have full 32 bits + * available. + */ + ret = idr_alloc_cyclic(&dev_priv->global_ctx_idr, + ctx, 0, 0, GFP_KERNEL); + if (ret < 0) + goto err_out; + + ctx->global_id = ret; /* NB: Mark all slices as needing a remap so that when the context first * loads it will restore whatever remap state already exists. If there * is no remap info, it will be a NOP. */ @@ -280,6 +292,7 @@ i915_gem_create_context(struct drm_device *dev, struct drm_i915_file_private *file_priv) { const bool is_global_default_ctx = file_priv == NULL; + struct drm_i915_private *dev_priv = dev->dev_private; struct intel_context *ctx; int ret = 0; @@ -326,6 +339,7 @@ i915_gem_create_context(struct drm_device *dev, i915_gem_object_ggtt_unpin(ctx->legacy_hw_ctx.rcs_state); err_destroy: idr_remove(&file_priv->context_idr, ctx->user_handle); + idr_remove(&dev_priv->global_ctx_idr, ctx->global_id); i915_gem_context_unreference(ctx); return ERR_PTR(ret); } @@ -389,6 +403,7 @@ int i915_gem_context_init(struct drm_device *dev) dev_priv->hw_context_size = 0; } } + idr_init(&dev_priv->global_ctx_idr); ctx = i915_gem_create_context(dev, NULL); if (IS_ERR(ctx)) { @@ -416,6 +431,8 @@ void i915_gem_context_fini(struct drm_device *dev) struct intel_context *dctx = dev_priv->ring[RCS].default_context; int i; + idr_destroy(&dev_priv->global_ctx_idr); + if (dctx->legacy_hw_ctx.rcs_state) { /* The only known way to stop the gpu from accessing the hw context is * to reset it. Do this as the very last operation to avoid confusing @@ -478,6 +495,8 @@ static int context_idr_cleanup(int id, void *p, void *data) { struct intel_context *ctx = p; + idr_remove(&ctx->i915->global_ctx_idr, ctx->global_id); + i915_gem_context_unreference(ctx); return 0; } @@ -888,6 +907,7 @@ int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, { struct drm_i915_gem_context_destroy *args = data; struct drm_i915_file_private *file_priv = file->driver_priv; + struct drm_i915_private *dev_priv = dev->dev_private; struct intel_context *ctx; int ret; @@ -905,6 +925,7 @@ int i915_gem_context_destroy_ioctl(struct drm_device *dev, void *data, } idr_remove(&ctx->file_priv->context_idr, ctx->user_handle); + idr_remove(&dev_priv->global_ctx_idr, ctx->global_id); i915_gem_context_unreference(ctx); mutex_unlock(&dev->struct_mutex); From 6367133c5bd07bc9a8be43458cf832af299e5683 Mon Sep 17 00:00:00 2001 From: Robert Bragg Date: Mon, 7 Sep 2015 16:32:14 +0100 Subject: [PATCH 14/21] drm/i915: Constrain intel_context::global_id to 20 bits This will allow the ID to be given to the HW as the unique context identifier that's written, for example, to the context status buffer on preemption and included in reports written by the OA unit. Cc: Sourab Gupta Signed-off-by: Robert Bragg --- drivers/gpu/drm/i915/i915_gem_context.c | 11 +++++------ 1 file changed, 5 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 3697962d1d9ef2..9688a825f4c56f 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -90,6 +90,10 @@ #include "i915_drv.h" #include "i915_trace.h" +/* With execlist scheduling we can program our own HW context ID but we we + * are limited to 20bits */ +#define I915_MAX_HW_CTX_ID ((1<<20)-1) + /* This is a HW constraint. The value below is the largest known requirement * I've seen in a spec to date, and that was a workaround for a non-shipping * part. It should be safe to decrease this, but it's more future proof as is. @@ -257,13 +261,8 @@ __create_hw_context(struct drm_device *dev, ctx->file_priv = file_priv; ctx->user_handle = ret; - /* TODO: If required, this global id can be used for programming the hw - * fields too. In that case, we'll have take care of hw restrictions - * while allocating idr. e.g. for some hw, we may not have full 32 bits - * available. - */ ret = idr_alloc_cyclic(&dev_priv->global_ctx_idr, - ctx, 0, 0, GFP_KERNEL); + ctx, 0, I915_MAX_HW_CTX_ID, GFP_KERNEL); if (ret < 0) goto err_out; From 969f5c3a2ce6253a4146058916acaee9d88531ce Mon Sep 17 00:00:00 2001 From: Robert Bragg Date: Mon, 7 Sep 2015 17:55:36 +0100 Subject: [PATCH 15/21] drm/i915: return ctx->global_id from intel_execlists_ctx_id() The newly added intel_context::global_id is suitable (a globally unique 20 bit ID) for giving to the hardware as a unique context identifier. Compared to using the pinned address of a logical ring context these IDs are constant for the lifetime of a context whereas a context could be repinned at different addresses during its lifetime. Having a stable ID is useful when we need to buffer information associated with a context based on this ID so the association can't be lost. For example the OA unit writes out counter reports to a circular buffer tagged with this ID and we want to be able to accurately filter reports for a specific context, ideally without the added complexity of tracking context re-pinning while the OA buffer may contain reports with older IDs. Cc: Sourab Gupta Signed-off-by: Robert Bragg --- drivers/gpu/drm/i915/i915_debugfs.c | 7 ++++--- drivers/gpu/drm/i915/intel_lrc.c | 22 ++++++++++------------ drivers/gpu/drm/i915/intel_lrc.h | 2 +- 3 files changed, 15 insertions(+), 16 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_debugfs.c b/drivers/gpu/drm/i915/i915_debugfs.c index 8aab974b0564c4..ff4a6fedab634b 100644 --- a/drivers/gpu/drm/i915/i915_debugfs.c +++ b/drivers/gpu/drm/i915/i915_debugfs.c @@ -1970,6 +1970,7 @@ static int i915_context_status(struct seq_file *m, void *unused) static void i915_dump_lrc_obj(struct seq_file *m, struct intel_engine_cs *ring, + struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj) { struct page *page; @@ -1984,7 +1985,7 @@ static void i915_dump_lrc_obj(struct seq_file *m, } seq_printf(m, "CONTEXT: %s %u\n", ring->name, - intel_execlists_ctx_id(ctx_obj)); + intel_execlists_ctx_id(ctx)); if (!i915_gem_obj_ggtt_bound(ctx_obj)) seq_puts(m, "\tNot bound in GGTT\n"); @@ -2033,7 +2034,7 @@ static int i915_dump_lrc(struct seq_file *m, void *unused) list_for_each_entry(ctx, &dev_priv->context_list, link) { for_each_ring(ring, dev_priv, i) { if (ring->default_context != ctx) - i915_dump_lrc_obj(m, ring, + i915_dump_lrc_obj(m, ring, ctx, ctx->engine[i].state); } } @@ -2112,7 +2113,7 @@ static int i915_execlists(struct seq_file *m, void *data) ctx_obj = head_req->ctx->engine[ring_id].state; seq_printf(m, "\tHead request id: %u\n", - intel_execlists_ctx_id(ctx_obj)); + intel_execlists_ctx_id(head_req->ctx)); seq_printf(m, "\tHead request tail: %u\n", head_req->tail); } diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 88e12bdf79e233..548ee53f1cb939 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -260,7 +260,7 @@ int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists /** * intel_execlists_ctx_id() - get the Execlists Context ID - * @ctx_obj: Logical Ring Context backing object. + * @ctx: LR context * * Do not confuse with ctx->id! Unfortunately we have a name overload * here: the old context ID we pass to userspace as a handler so that @@ -269,15 +269,15 @@ int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists * interrupts. * * Return: 20-bits globally unique context ID. + * + * Further the ID given to HW can now be relied on to be constant for + * the lifetime of the context, unlike previously when we used an + * associated logical ring context address (which could be repinned at + * a different address). */ -u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj) +u32 intel_execlists_ctx_id(struct intel_context *ctx) { - u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj) + - LRC_PPHWSP_PN * PAGE_SIZE; - - /* LRCA is required to be 4K aligned so the more significant 20 bits - * are globally unique */ - return lrca >> 12; + return ctx->global_id; } static bool disable_lite_restore_wa(struct intel_engine_cs *ring) @@ -305,7 +305,7 @@ uint64_t intel_lr_context_descriptor(struct intel_context *ctx, desc |= GEN8_CTX_L3LLC_COHERENT; desc |= GEN8_CTX_PRIVILEGE; desc |= lrca; - desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT; + desc |= (u64)intel_execlists_ctx_id(ctx) << GEN8_CTX_ID_SHIFT; /* TODO: WaDisableLiteRestore when we start using semaphore * signalling between Command Streamers */ @@ -473,9 +473,7 @@ static bool execlists_check_remove_request(struct intel_engine_cs *ring, execlist_link); if (head_req != NULL) { - struct drm_i915_gem_object *ctx_obj = - head_req->ctx->engine[ring->id].state; - if (intel_execlists_ctx_id(ctx_obj) == request_id) { + if (intel_execlists_ctx_id(head_req->ctx) == request_id) { WARN(head_req->elsp_submitted == 0, "Never submitted head request\n"); diff --git a/drivers/gpu/drm/i915/intel_lrc.h b/drivers/gpu/drm/i915/intel_lrc.h index 4e60d54ba66de8..1b08cd2260cd27 100644 --- a/drivers/gpu/drm/i915/intel_lrc.h +++ b/drivers/gpu/drm/i915/intel_lrc.h @@ -93,7 +93,7 @@ struct i915_execbuffer_params; int intel_execlists_submission(struct i915_execbuffer_params *params, struct drm_i915_gem_execbuffer2 *args, struct list_head *vmas); -u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj); +u32 intel_execlists_ctx_id(struct intel_context *ctx); void intel_lrc_irq_handler(struct intel_engine_cs *ring); void intel_execlists_retire_requests(struct intel_engine_cs *ring); From 6a74db5e7dc04435a8784315a1bce56c56beccc8 Mon Sep 17 00:00:00 2001 From: Robert Bragg Date: Wed, 16 Sep 2015 19:18:23 +0100 Subject: [PATCH 16/21] drm/i915: Add uncore mmio api for per-context registers Since the exponent for periodic OA counter sampling is maintained in a per-context register while we want to treat it as if it were global state we need to be able to safely issue an mmio write to a per-context register and affect any currently running context. We have to take some extra care in this case and this adds a utility api to encapsulate what's required. Signed-off-by: Robert Bragg --- drivers/gpu/drm/i915/i915_drv.h | 4 ++ drivers/gpu/drm/i915/i915_reg.h | 3 ++ drivers/gpu/drm/i915/intel_uncore.c | 70 +++++++++++++++++++++++++++++ 3 files changed, 77 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 1d2ae56a4b6ceb..ad19b60bd5cb30 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -688,6 +688,7 @@ enum forcewake_domains { }; struct intel_uncore_funcs { + int (*wait_for_rcs_busy)(struct drm_i915_private *dev_priv); void (*force_wake_get)(struct drm_i915_private *dev_priv, enum forcewake_domains domains); void (*force_wake_put)(struct drm_i915_private *dev_priv, @@ -713,6 +714,7 @@ struct intel_uncore { struct intel_uncore_funcs funcs; + atomic_t hold_rcs_busy_count; unsigned fifo_count; enum forcewake_domains fw_domains; @@ -2877,6 +2879,8 @@ static inline bool intel_vgpu_active(struct drm_device *dev) { return to_i915(dev)->vgpu.active; } +int intel_uncore_begin_ctx_mmio(struct drm_i915_private *dev_priv); +void intel_uncore_end_ctx_mmio(struct drm_i915_private *dev_priv); void i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe, diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index 3d9841ccda530e..a333038a77506a 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -2217,6 +2217,9 @@ enum skl_disp_power_wells { #define GEN8_RC_SEMA_IDLE_MSG_DISABLE (1 << 12) #define GEN8_FF_DOP_CLOCK_GATE_DISABLE (1<<10) +#define GEN6_RCS_PWR_FSM 0x22ac +#define GEN9_RCS_FE_FSM2 0x22a4 + /* Fuse readout registers for GT */ #define CHV_FUSE_GT (VLV_DISPLAY_BASE + 0x2168) #define CHV_FGT_DISABLE_SS0 (1 << 10) diff --git a/drivers/gpu/drm/i915/intel_uncore.c b/drivers/gpu/drm/i915/intel_uncore.c index 43cba129a0c000..986ea55d4318ae 100644 --- a/drivers/gpu/drm/i915/intel_uncore.c +++ b/drivers/gpu/drm/i915/intel_uncore.c @@ -1190,6 +1190,16 @@ static void intel_uncore_fw_domains_init(struct drm_device *dev) WARN_ON(dev_priv->uncore.fw_domains == 0); } +static int gen8_wait_for_rcs_busy(struct drm_i915_private *dev_priv) +{ + return wait_for((I915_READ(GEN6_RCS_PWR_FSM) & 0x3f) == 0x30, 50); +} + +static int gen9_wait_for_rcs_busy(struct drm_i915_private *dev_priv) +{ + return wait_for((I915_READ(GEN9_RCS_FE_FSM2) & 0x3f) == 0x30, 50); +} + void intel_uncore_init(struct drm_device *dev) { struct drm_i915_private *dev_priv = dev->dev_private; @@ -1205,6 +1215,7 @@ void intel_uncore_init(struct drm_device *dev) case 9: ASSIGN_WRITE_MMIO_VFUNCS(gen9); ASSIGN_READ_MMIO_VFUNCS(gen9); + dev_priv->uncore.funcs.wait_for_rcs_busy = gen9_wait_for_rcs_busy; break; case 8: if (IS_CHERRYVIEW(dev)) { @@ -1215,6 +1226,7 @@ void intel_uncore_init(struct drm_device *dev) ASSIGN_WRITE_MMIO_VFUNCS(gen8); ASSIGN_READ_MMIO_VFUNCS(gen6); } + dev_priv->uncore.funcs.wait_for_rcs_busy = gen8_wait_for_rcs_busy; break; case 7: case 6: @@ -1564,3 +1576,61 @@ void intel_uncore_check_errors(struct drm_device *dev) __raw_i915_write32(dev_priv, FPGA_DBG, FPGA_DBG_RM_NOCLAIM); } } + +static int hold_rcs_busy(struct drm_i915_private *dev_priv) +{ + int ret = 0; + + if (atomic_inc_and_test(&dev_priv->uncore.hold_rcs_busy_count)) { + I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, + _MASKED_BIT_ENABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); + + ret = dev_priv->uncore.funcs.wait_for_rcs_busy(dev_priv); + } + + return ret; +} + +static void release_rcs_busy(struct drm_i915_private *dev_priv) +{ + if (!atomic_dec_and_test(&dev_priv->uncore.hold_rcs_busy_count)) { + I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, + _MASKED_BIT_DISABLE(GEN6_PSMI_SLEEP_MSG_DISABLE)); + } +} + +/* + * From Broadwell PRM, 3D-Media-GPGPU -> Register State Context + * + * MMIO reads or writes to any of the registers listed in the + * “Register State Context image” subsections through HOST/IA + * MMIO interface for debug purposes must follow the steps below: + * + * - SW should set the Force Wakeup bit to prevent GT from entering C6. + * - Write 0x2050[31:0] = 0x00010001 (disable sequence). + * - Disable IDLE messaging in CS (Write 0x2050[31:0] = 0x00010001). + * - Poll/Wait for register bits of 0x22AC[6:0] turn to 0x30 value. + * - Read/Write to desired MMIO registers. + * - Enable IDLE messaging in CS (Write 0x2050[31:0] = 0x00010000). + * - Force Wakeup bit should be reset to enable C6 entry. + */ +int intel_uncore_begin_ctx_mmio(struct drm_i915_private *dev_priv) +{ + int ret = 0; + + BUG_ON(dev_priv->info.gen < 8); + + intel_uncore_forcewake_get(dev_priv, FORCEWAKE_RENDER); + + ret = hold_rcs_busy(dev_priv); + if (ret) + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_RENDER); + + return ret; +} + +void intel_uncore_end_ctx_mmio(struct drm_i915_private *dev_priv) +{ + release_rcs_busy(dev_priv); + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_RENDER); +} From ac938f3575e7378b3f8bf063ab0c8c7fa3e62abd Mon Sep 17 00:00:00 2001 From: Robert Bragg Date: Mon, 21 Sep 2015 14:31:18 +0100 Subject: [PATCH 17/21] drm/i915: Add 'render basic' Gen8+ OA unit configs Adds a static OA unit, MUX, B Counter + Flex EU configurations for basic render metrics on Broadwell, Cherryview and Skylake. These are autogenerated from an internal XML description of metric sets. Signed-off-by: Robert Bragg --- drivers/gpu/drm/i915/Makefile | 5 +- drivers/gpu/drm/i915/i915_drv.h | 2 + drivers/gpu/drm/i915/i915_oa_bdw.c | 355 +++++++++++++++++++++++++++++ drivers/gpu/drm/i915/i915_oa_bdw.h | 38 +++ drivers/gpu/drm/i915/i915_oa_chv.c | 196 ++++++++++++++++ drivers/gpu/drm/i915/i915_oa_chv.h | 38 +++ drivers/gpu/drm/i915/i915_oa_skl.c | 289 +++++++++++++++++++++++ drivers/gpu/drm/i915/i915_oa_skl.h | 38 +++ 8 files changed, 960 insertions(+), 1 deletion(-) create mode 100644 drivers/gpu/drm/i915/i915_oa_bdw.c create mode 100644 drivers/gpu/drm/i915/i915_oa_bdw.h create mode 100644 drivers/gpu/drm/i915/i915_oa_chv.c create mode 100644 drivers/gpu/drm/i915/i915_oa_chv.h create mode 100644 drivers/gpu/drm/i915/i915_oa_skl.c create mode 100644 drivers/gpu/drm/i915/i915_oa_skl.h diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile index 5b1c688ecaef7d..c5bfca0b0806c3 100644 --- a/drivers/gpu/drm/i915/Makefile +++ b/drivers/gpu/drm/i915/Makefile @@ -95,7 +95,10 @@ i915-y += i915_vgpu.o # perf code i915-y += i915_perf.o \ - i915_oa_hsw.o + i915_oa_hsw.o \ + i915_oa_bdw.o \ + i915_oa_chv.o \ + i915_oa_skl.o # legacy horrors i915-y += i915_dma.o diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index ad19b60bd5cb30..d6e89e957bc5df 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2062,6 +2062,8 @@ struct drm_i915_private { int mux_regs_len; const struct i915_oa_reg *b_counter_regs; int b_counter_regs_len; + const struct i915_oa_reg *flex_regs; + int flex_regs_len; struct { struct drm_i915_gem_object *obj; diff --git a/drivers/gpu/drm/i915/i915_oa_bdw.c b/drivers/gpu/drm/i915/i915_oa_bdw.c new file mode 100644 index 00000000000000..a352799f50efda --- /dev/null +++ b/drivers/gpu/drm/i915/i915_oa_bdw.c @@ -0,0 +1,355 @@ +/* + * Autogenerated file, DO NOT EDIT manually! + * + * Copyright (c) 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +#include + +#include "i915_drv.h" + +enum metric_set_id { + METRIC_SET_ID_RENDER_BASIC = 1, +}; + +int i915_oa_n_builtin_metric_sets_bdw = 1; + +static const struct i915_oa_reg b_counter_config_render_basic[] = { + { 0x2710, 0x00000000 }, + { 0x2714, 0x00800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x00800000 }, +}; + +static const struct i915_oa_reg flex_eu_config_render_basic[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_render_basic_1_0_slices_0x01[] = { + { 0x9888, 0x143F000F }, + { 0x9888, 0x14110014 }, + { 0x9888, 0x14310014 }, + { 0x9888, 0x14BF000F }, + { 0x9888, 0x13837BE0 }, + { 0x9888, 0x3B800060 }, + { 0x9888, 0x3D800005 }, + { 0x9888, 0x005C4000 }, + { 0x9888, 0x065C8000 }, + { 0x9888, 0x085CC000 }, + { 0x9888, 0x003D8000 }, + { 0x9888, 0x183D0800 }, + { 0x9888, 0x0A3F0023 }, + { 0x9888, 0x103F0000 }, + { 0x9888, 0x00584000 }, + { 0x9888, 0x08584000 }, + { 0x9888, 0x0A5A4000 }, + { 0x9888, 0x005B4000 }, + { 0x9888, 0x0E5B8000 }, + { 0x9888, 0x185B2400 }, + { 0x9888, 0x0A1D4000 }, + { 0x9888, 0x0C1F0800 }, + { 0x9888, 0x0E1FAA00 }, + { 0x9888, 0x00384000 }, + { 0x9888, 0x0E384000 }, + { 0x9888, 0x16384000 }, + { 0x9888, 0x18380001 }, + { 0x9888, 0x00392000 }, + { 0x9888, 0x06398000 }, + { 0x9888, 0x0839A000 }, + { 0x9888, 0x0A391000 }, + { 0x9888, 0x00104000 }, + { 0x9888, 0x08104000 }, + { 0x9888, 0x00110030 }, + { 0x9888, 0x08110031 }, + { 0x9888, 0x10110000 }, + { 0x9888, 0x00134000 }, + { 0x9888, 0x16130020 }, + { 0x9888, 0x06308000 }, + { 0x9888, 0x08308000 }, + { 0x9888, 0x06311800 }, + { 0x9888, 0x08311880 }, + { 0x9888, 0x10310000 }, + { 0x9888, 0x0E334000 }, + { 0x9888, 0x16330080 }, + { 0x9888, 0x0ABF1180 }, + { 0x9888, 0x10BF0000 }, + { 0x9888, 0x0ADA8000 }, + { 0x9888, 0x0A9D8000 }, + { 0x9888, 0x109F0002 }, + { 0x9888, 0x0AB94000 }, + { 0x9888, 0x0D888000 }, + { 0x9888, 0x018A8000 }, + { 0x9888, 0x0F8A8000 }, + { 0x9888, 0x198A8000 }, + { 0x9888, 0x1B8A00A0 }, + { 0x9888, 0x238B0020 }, + { 0x9888, 0x258B2550 }, + { 0x9888, 0x198C1000 }, + { 0x9888, 0x0B8D8000 }, + { 0x9888, 0x1F85AA80 }, + { 0x9888, 0x2185AAA0 }, + { 0x9888, 0x2385002A }, + { 0x9888, 0x0D831021 }, + { 0x9888, 0x0F83572F }, + { 0x9888, 0x01835680 }, + { 0x9888, 0x038315AC }, + { 0x9888, 0x0583002A }, + { 0x9888, 0x11830000 }, + { 0x9888, 0x19835400 }, + { 0x9888, 0x1B830001 }, + { 0x9888, 0x07830000 }, + { 0x9888, 0x09830000 }, + { 0x9888, 0x0184C000 }, + { 0x9888, 0x07848000 }, + { 0x9888, 0x0984C000 }, + { 0x9888, 0x0B84C000 }, + { 0x9888, 0x0D84C000 }, + { 0x9888, 0x0F84C000 }, + { 0x9888, 0x0384C000 }, + { 0x9888, 0x05844000 }, + { 0x9888, 0x1B80C137 }, + { 0x9888, 0x1D80C147 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x1180C000 }, + { 0x9888, 0x17808000 }, + { 0x9888, 0x1980C000 }, + { 0x9888, 0x1F80C000 }, + { 0x9888, 0x1380C000 }, + { 0x9888, 0x15804000 }, + { 0x0D24, 0x00000000 }, + { 0x9888, 0x4D801110 }, + { 0x9888, 0x4F800331 }, + { 0x9888, 0x43800802 }, + { 0x9888, 0x51800000 }, + { 0x9888, 0x45801465 }, + { 0x9888, 0x53801111 }, + { 0x9888, 0x478014A5 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x3F8014A5 }, + { 0x9888, 0x41800005 }, +}; + +static const struct i915_oa_reg mux_config_render_basic_1_1_slices_0x02[] = { + { 0x9888, 0x143F000F }, + { 0x9888, 0x14BF000F }, + { 0x9888, 0x14910014 }, + { 0x9888, 0x14B10014 }, + { 0x9888, 0x13837BE0 }, + { 0x9888, 0x3B800060 }, + { 0x9888, 0x3D800005 }, + { 0x9888, 0x0A3F0023 }, + { 0x9888, 0x103F0000 }, + { 0x9888, 0x0A5A4000 }, + { 0x9888, 0x0A1D4000 }, + { 0x9888, 0x0E1F8000 }, + { 0x9888, 0x0A391000 }, + { 0x9888, 0x00DC4000 }, + { 0x9888, 0x06DC8000 }, + { 0x9888, 0x08DCC000 }, + { 0x9888, 0x00BD8000 }, + { 0x9888, 0x18BD0800 }, + { 0x9888, 0x0ABF1180 }, + { 0x9888, 0x10BF0000 }, + { 0x9888, 0x00D84000 }, + { 0x9888, 0x08D84000 }, + { 0x9888, 0x0ADA8000 }, + { 0x9888, 0x00DB4000 }, + { 0x9888, 0x0EDB8000 }, + { 0x9888, 0x18DB2400 }, + { 0x9888, 0x0A9D8000 }, + { 0x9888, 0x0C9F0800 }, + { 0x9888, 0x0E9F2A00 }, + { 0x9888, 0x109F0002 }, + { 0x9888, 0x00B84000 }, + { 0x9888, 0x0EB84000 }, + { 0x9888, 0x16B84000 }, + { 0x9888, 0x18B80001 }, + { 0x9888, 0x00B92000 }, + { 0x9888, 0x06B98000 }, + { 0x9888, 0x08B9A000 }, + { 0x9888, 0x0AB94000 }, + { 0x9888, 0x00904000 }, + { 0x9888, 0x08904000 }, + { 0x9888, 0x00910030 }, + { 0x9888, 0x08910031 }, + { 0x9888, 0x10910000 }, + { 0x9888, 0x00934000 }, + { 0x9888, 0x16930020 }, + { 0x9888, 0x06B08000 }, + { 0x9888, 0x08B08000 }, + { 0x9888, 0x06B11800 }, + { 0x9888, 0x08B11880 }, + { 0x9888, 0x10B10000 }, + { 0x9888, 0x0EB34000 }, + { 0x9888, 0x16B30080 }, + { 0x9888, 0x01888000 }, + { 0x9888, 0x0D88B800 }, + { 0x9888, 0x1B8A0080 }, + { 0x9888, 0x238B0040 }, + { 0x9888, 0x258B26A0 }, + { 0x9888, 0x018C4000 }, + { 0x9888, 0x0F8C4000 }, + { 0x9888, 0x178C2000 }, + { 0x9888, 0x198C1100 }, + { 0x9888, 0x018D2000 }, + { 0x9888, 0x078D8000 }, + { 0x9888, 0x098DA000 }, + { 0x9888, 0x0B8D8000 }, + { 0x9888, 0x1F85AA80 }, + { 0x9888, 0x2185AAA0 }, + { 0x9888, 0x2385002A }, + { 0x9888, 0x0D831021 }, + { 0x9888, 0x0F83572F }, + { 0x9888, 0x01835680 }, + { 0x9888, 0x038315AC }, + { 0x9888, 0x0583002A }, + { 0x9888, 0x11830000 }, + { 0x9888, 0x19835400 }, + { 0x9888, 0x1B830001 }, + { 0x9888, 0x07830000 }, + { 0x9888, 0x09830000 }, + { 0x9888, 0x0184C000 }, + { 0x9888, 0x07848000 }, + { 0x9888, 0x0984C000 }, + { 0x9888, 0x0B84C000 }, + { 0x9888, 0x0D84C000 }, + { 0x9888, 0x0F84C000 }, + { 0x9888, 0x0384C000 }, + { 0x9888, 0x05844000 }, + { 0x9888, 0x1B80C137 }, + { 0x9888, 0x1D80C147 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x1180C000 }, + { 0x9888, 0x17808000 }, + { 0x9888, 0x1980C000 }, + { 0x9888, 0x1F80C000 }, + { 0x9888, 0x1380C000 }, + { 0x9888, 0x15804000 }, + { 0x0D24, 0x00000000 }, + { 0x9888, 0x4D805550 }, + { 0x9888, 0x4F800335 }, + { 0x9888, 0x43800802 }, + { 0x9888, 0x51800400 }, + { 0x9888, 0x458004A1 }, + { 0x9888, 0x53805555 }, + { 0x9888, 0x47800421 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x3F800421 }, + { 0x9888, 0x41800841 }, +}; + +static int select_render_basic_config(struct drm_i915_private *dev_priv) +{ + if (INTEL_INFO(dev_priv)->slice_mask & 0x01) { + dev_priv->perf.oa.mux_regs = + mux_config_render_basic_1_0_slices_0x01; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_render_basic_1_0_slices_0x01); + } else if (INTEL_INFO(dev_priv)->slice_mask & 0x02) { + dev_priv->perf.oa.mux_regs = + mux_config_render_basic_1_1_slices_0x02; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_render_basic_1_1_slices_0x02); + } else { + DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set"); + return -EINVAL; + } + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_render_basic; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_render_basic); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_render_basic; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_render_basic); + + return 0; +} + +int i915_oa_select_metric_set_bdw(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = NULL; + dev_priv->perf.oa.mux_regs_len = 0; + dev_priv->perf.oa.b_counter_regs = NULL; + dev_priv->perf.oa.b_counter_regs_len = 0; + dev_priv->perf.oa.flex_regs = NULL; + dev_priv->perf.oa.flex_regs_len = 0; + + switch (dev_priv->perf.oa.metrics_set) { + case METRIC_SET_ID_RENDER_BASIC: + return select_render_basic_config(dev_priv); + default: + return -ENODEV; + } +} + +static ssize_t +show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); +} + +static struct device_attribute dev_attr_render_basic_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_render_basic_id, + .store = NULL, +}; + +static struct attribute *attrs_render_basic[] = { + &dev_attr_render_basic_id.attr, + NULL, +}; + +static struct attribute_group group_render_basic = { + .name = "b541bd57-0e0f-4154-b4c0-5858010a2bf7", + .attrs = attrs_render_basic, +}; + +int +i915_perf_init_sysfs_bdw(struct drm_i915_private *dev_priv) +{ + int ret; + + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); + if (ret) + goto error_render_basic; + + return 0; + +error_render_basic: + return ret; +} + +void +i915_perf_deinit_sysfs_bdw(struct drm_i915_private *dev_priv) +{ + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); +} diff --git a/drivers/gpu/drm/i915/i915_oa_bdw.h b/drivers/gpu/drm/i915/i915_oa_bdw.h new file mode 100644 index 00000000000000..ad28e4c2e53936 --- /dev/null +++ b/drivers/gpu/drm/i915/i915_oa_bdw.h @@ -0,0 +1,38 @@ +/* + * Autogenerated file, DO NOT EDIT manually! + * + * Copyright (c) 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +#ifndef __I915_OA_BDW_H__ +#define __I915_OA_BDW_H__ + +extern int i915_oa_n_builtin_metric_sets_bdw; + +extern int i915_oa_select_metric_set_bdw(struct drm_i915_private *dev_priv); + +extern int i915_perf_init_sysfs_bdw(struct drm_i915_private *dev_priv); + +extern void i915_perf_deinit_sysfs_bdw(struct drm_i915_private *dev_priv); + +#endif diff --git a/drivers/gpu/drm/i915/i915_oa_chv.c b/drivers/gpu/drm/i915/i915_oa_chv.c new file mode 100644 index 00000000000000..703b61c681275d --- /dev/null +++ b/drivers/gpu/drm/i915/i915_oa_chv.c @@ -0,0 +1,196 @@ +/* + * Autogenerated file, DO NOT EDIT manually! + * + * Copyright (c) 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +#include + +#include "i915_drv.h" + +enum metric_set_id { + METRIC_SET_ID_RENDER_BASIC = 1, +}; + +int i915_oa_n_builtin_metric_sets_chv = 1; + +static const struct i915_oa_reg b_counter_config_render_basic[] = { + { 0x2710, 0x00000000 }, + { 0x2714, 0x00800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x00800000 }, +}; + +static const struct i915_oa_reg flex_eu_config_render_basic[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_render_basic[] = { + { 0x9888, 0x59800000 }, + { 0x9888, 0x59800001 }, + { 0x9888, 0x2C110014 }, + { 0x9888, 0x2E110000 }, + { 0x9888, 0x2C310014 }, + { 0x9888, 0x2E310000 }, + { 0x9888, 0x2B8303DF }, + { 0x9888, 0x358002C0 }, + { 0x9888, 0x00580888 }, + { 0x9888, 0x00190555 }, + { 0x9888, 0x00380444 }, + { 0x9888, 0x003A0666 }, + { 0x9888, 0x00100111 }, + { 0x9888, 0x06110030 }, + { 0x9888, 0x0A110031 }, + { 0x9888, 0x0E110046 }, + { 0x9888, 0x04110000 }, + { 0x9888, 0x00110000 }, + { 0x9888, 0x00130111 }, + { 0x9888, 0x00300444 }, + { 0x9888, 0x08310030 }, + { 0x9888, 0x0C310031 }, + { 0x9888, 0x10310046 }, + { 0x9888, 0x04310000 }, + { 0x9888, 0x00310000 }, + { 0x9888, 0x00330444 }, + { 0x9888, 0x018B0FFF }, + { 0x9888, 0x01855000 }, + { 0x9888, 0x03850555 }, + { 0x9888, 0x13830021 }, + { 0x9888, 0x15830020 }, + { 0x9888, 0x1783002F }, + { 0x9888, 0x1983002E }, + { 0x9888, 0x1B83002D }, + { 0x9888, 0x1D83002C }, + { 0x9888, 0x1F83002B }, + { 0x9888, 0x2183002A }, + { 0x9888, 0x05830000 }, + { 0x9888, 0x01840555 }, + { 0x9888, 0x23800071 }, + { 0x9888, 0x25800072 }, + { 0x9888, 0x05800000 }, + { 0x9888, 0x01805000 }, + { 0x9888, 0x03800555 }, + { 0x9888, 0x01865000 }, + { 0x9888, 0x03860555 }, + { 0x9888, 0x01875000 }, + { 0x9888, 0x03870555 }, + { 0x9888, 0x418000AA }, + { 0x9888, 0x4380000A }, + { 0x9888, 0x45800000 }, + { 0x9888, 0x47800000 }, + { 0x9888, 0x498000C8 }, + { 0x9888, 0x4B8000C8 }, + { 0x9888, 0x4D8000C8 }, + { 0x9888, 0x4F80014A }, + { 0x9888, 0x5180014A }, + { 0x9888, 0x5380014A }, + { 0x9888, 0x5580014A }, + { 0x9888, 0x578001CE }, + { 0x9888, 0x59800000 }, +}; + +static int select_render_basic_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_render_basic; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_render_basic); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_render_basic; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_render_basic); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_render_basic; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_render_basic); + + return 0; +} + +int i915_oa_select_metric_set_chv(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = NULL; + dev_priv->perf.oa.mux_regs_len = 0; + dev_priv->perf.oa.b_counter_regs = NULL; + dev_priv->perf.oa.b_counter_regs_len = 0; + dev_priv->perf.oa.flex_regs = NULL; + dev_priv->perf.oa.flex_regs_len = 0; + + switch (dev_priv->perf.oa.metrics_set) { + case METRIC_SET_ID_RENDER_BASIC: + return select_render_basic_config(dev_priv); + default: + return -ENODEV; + } +} + +static ssize_t +show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); +} + +static struct device_attribute dev_attr_render_basic_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_render_basic_id, + .store = NULL, +}; + +static struct attribute *attrs_render_basic[] = { + &dev_attr_render_basic_id.attr, + NULL, +}; + +static struct attribute_group group_render_basic = { + .name = "9d8a3af5-c02c-4a4a-b947-f1672469e0fb", + .attrs = attrs_render_basic, +}; + +int +i915_perf_init_sysfs_chv(struct drm_i915_private *dev_priv) +{ + int ret; + + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); + if (ret) + goto error_render_basic; + + return 0; + +error_render_basic: + return ret; +} + +void +i915_perf_deinit_sysfs_chv(struct drm_i915_private *dev_priv) +{ + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); +} diff --git a/drivers/gpu/drm/i915/i915_oa_chv.h b/drivers/gpu/drm/i915/i915_oa_chv.h new file mode 100644 index 00000000000000..be3a5e0c3c2fd6 --- /dev/null +++ b/drivers/gpu/drm/i915/i915_oa_chv.h @@ -0,0 +1,38 @@ +/* + * Autogenerated file, DO NOT EDIT manually! + * + * Copyright (c) 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +#ifndef __I915_OA_CHV_H__ +#define __I915_OA_CHV_H__ + +extern int i915_oa_n_builtin_metric_sets_chv; + +extern int i915_oa_select_metric_set_chv(struct drm_i915_private *dev_priv); + +extern int i915_perf_init_sysfs_chv(struct drm_i915_private *dev_priv); + +extern void i915_perf_deinit_sysfs_chv(struct drm_i915_private *dev_priv); + +#endif diff --git a/drivers/gpu/drm/i915/i915_oa_skl.c b/drivers/gpu/drm/i915/i915_oa_skl.c new file mode 100644 index 00000000000000..e0e7d6a5b664dc --- /dev/null +++ b/drivers/gpu/drm/i915/i915_oa_skl.c @@ -0,0 +1,289 @@ +/* + * Autogenerated file, DO NOT EDIT manually! + * + * Copyright (c) 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +#include + +#include "i915_drv.h" + +enum metric_set_id { + METRIC_SET_ID_RENDER_BASIC = 1, +}; + +int i915_oa_n_builtin_metric_sets_skl = 1; + +static const struct i915_oa_reg b_counter_config_render_basic[] = { + { 0x2710, 0x00000000 }, + { 0x2714, 0x00800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x00800000 }, +}; + +static const struct i915_oa_reg flex_eu_config_render_basic[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_render_basic_1_1_sku_lt_0x02[] = { + { 0x9888, 0x166C01E0 }, + { 0x9888, 0x12170280 }, + { 0x9888, 0x12370280 }, + { 0x9888, 0x159303DF }, + { 0x9888, 0x3F901403 }, + { 0x9888, 0x1A4E0080 }, + { 0x9888, 0x0A6C0053 }, + { 0x9888, 0x106C0000 }, + { 0x9888, 0x1C6C0000 }, + { 0x9888, 0x0A1B4000 }, + { 0x9888, 0x1C1C0001 }, + { 0x9888, 0x002F1000 }, + { 0x9888, 0x042F1000 }, + { 0x9888, 0x004C4000 }, + { 0x9888, 0x0A4C8400 }, + { 0x9888, 0x000D2000 }, + { 0x9888, 0x060D8000 }, + { 0x9888, 0x080DA000 }, + { 0x9888, 0x0A0D2000 }, + { 0x9888, 0x0C0F0400 }, + { 0x9888, 0x0E0F6600 }, + { 0x9888, 0x002C8000 }, + { 0x9888, 0x162C2200 }, + { 0x9888, 0x062D8000 }, + { 0x9888, 0x082D8000 }, + { 0x9888, 0x00133000 }, + { 0x9888, 0x08133000 }, + { 0x9888, 0x00170020 }, + { 0x9888, 0x08170021 }, + { 0x9888, 0x10170000 }, + { 0x9888, 0x0633C000 }, + { 0x9888, 0x0833C000 }, + { 0x9888, 0x06370800 }, + { 0x9888, 0x08370840 }, + { 0x9888, 0x10370000 }, + { 0x9888, 0x0D933031 }, + { 0x9888, 0x0F933E3F }, + { 0x9888, 0x01933D00 }, + { 0x9888, 0x03933B3C }, + { 0x9888, 0x0593003A }, + { 0x9888, 0x1D930000 }, + { 0x9888, 0x1B930000 }, + { 0x9888, 0x13930000 }, + { 0x9888, 0x17930000 }, + { 0x9888, 0x1F952A80 }, + { 0x9888, 0x1D9500AA }, + { 0x9888, 0x1D900157 }, + { 0x9888, 0x1F900167 }, + { 0x9888, 0x35900000 }, + { 0x9888, 0x2B908000 }, + { 0x9888, 0x2D908000 }, + { 0x9888, 0x2F908000 }, + { 0x9888, 0x31908000 }, + { 0x9888, 0x15908000 }, + { 0x9888, 0x17908000 }, + { 0x9888, 0x19908000 }, + { 0x9888, 0x1B908000 }, + { 0x0D28, 0x00000000 }, + { 0x9888, 0x1190001F }, + { 0x9888, 0x51901100 }, + { 0x9888, 0x41900020 }, + { 0x9888, 0x55900000 }, + { 0x9888, 0x45900C42 }, + { 0x9888, 0x47900061 }, + { 0x9888, 0x57901110 }, + { 0x9888, 0x49900000 }, + { 0x9888, 0x37900000 }, + { 0x9888, 0x33900000 }, + { 0x9888, 0x4B900000 }, + { 0x9888, 0x59900001 }, + { 0x9888, 0x43900000 }, + { 0x9888, 0x53901111 }, +}; + +static const struct i915_oa_reg mux_config_render_basic_1_1_sku_gte_0x02[] = { + { 0x00009888, 0x166C01E0 }, + { 0x00009888, 0x12170280 }, + { 0x00009888, 0x12370280 }, + { 0x00009888, 0x159303DF }, + { 0x00009888, 0x3F901403 }, + { 0x00009888, 0x1A4E0080 }, + { 0x00009888, 0x0A6C0053 }, + { 0x00009888, 0x106C0000 }, + { 0x00009888, 0x1C6C0000 }, + { 0x00009888, 0x0A1B4000 }, + { 0x00009888, 0x1C1C0001 }, + { 0x00009888, 0x002F1000 }, + { 0x00009888, 0x042F1000 }, + { 0x00009888, 0x004C4000 }, + { 0x00009888, 0x0A4C8400 }, + { 0x00009888, 0x000D2000 }, + { 0x00009888, 0x060D8000 }, + { 0x00009888, 0x080DA000 }, + { 0x00009888, 0x0A0D2000 }, + { 0x00009888, 0x0C0F0400 }, + { 0x00009888, 0x0E0F6600 }, + { 0x00009888, 0x002C8000 }, + { 0x00009888, 0x162C2200 }, + { 0x00009888, 0x062D8000 }, + { 0x00009888, 0x082D8000 }, + { 0x00009888, 0x00133000 }, + { 0x00009888, 0x08133000 }, + { 0x00009888, 0x00170020 }, + { 0x00009888, 0x08170021 }, + { 0x00009888, 0x10170000 }, + { 0x00009888, 0x0633C000 }, + { 0x00009888, 0x0833C000 }, + { 0x00009888, 0x06370800 }, + { 0x00009888, 0x08370840 }, + { 0x00009888, 0x10370000 }, + { 0x00009888, 0x0D933031 }, + { 0x00009888, 0x0F933E3F }, + { 0x00009888, 0x01933D00 }, + { 0x00009888, 0x03933B3C }, + { 0x00009888, 0x0593003A }, + { 0x00009888, 0x11930000 }, + { 0x00009888, 0x1D930000 }, + { 0x00009888, 0x19930000 }, + { 0x00009888, 0x1B930000 }, + { 0x00009888, 0x1D900157 }, + { 0x00009888, 0x1F900167 }, + { 0x00009888, 0x35900000 }, + { 0x00009888, 0x2B908000 }, + { 0x00009888, 0x2D908000 }, + { 0x00009888, 0x2F908000 }, + { 0x00009888, 0x31908000 }, + { 0x00009888, 0x15908000 }, + { 0x00009888, 0x17908000 }, + { 0x00009888, 0x19908000 }, + { 0x00009888, 0x1B908000 }, + { 0x00009888, 0x1190001F }, + { 0x00009888, 0x51901100 }, + { 0x00009888, 0x41900420 }, + { 0x00009888, 0x55900000 }, + { 0x00009888, 0x45900C42 }, + { 0x00009888, 0x47900061 }, + { 0x00009888, 0x57901110 }, + { 0x00009888, 0x49900420 }, + { 0x00009888, 0x37900000 }, + { 0x00009888, 0x33900000 }, + { 0x00009888, 0x4B900021 }, + { 0x00009888, 0x59900001 }, + { 0x00009888, 0x43900421 }, + { 0x00009888, 0x53901111 }, +}; + +static int select_render_basic_config(struct drm_i915_private *dev_priv) +{ + if (dev_priv->dev->pdev->revision < 0x02) { + dev_priv->perf.oa.mux_regs = + mux_config_render_basic_1_1_sku_lt_0x02; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_render_basic_1_1_sku_lt_0x02); + } else if (dev_priv->dev->pdev->revision >= 0x02) { + dev_priv->perf.oa.mux_regs = + mux_config_render_basic_1_1_sku_gte_0x02; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_render_basic_1_1_sku_gte_0x02); + } else { + DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_BASIC\" metric set"); + return -EINVAL; + } + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_render_basic; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_render_basic); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_render_basic; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_render_basic); + + return 0; +} + +int i915_oa_select_metric_set_skl(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = NULL; + dev_priv->perf.oa.mux_regs_len = 0; + dev_priv->perf.oa.b_counter_regs = NULL; + dev_priv->perf.oa.b_counter_regs_len = 0; + dev_priv->perf.oa.flex_regs = NULL; + dev_priv->perf.oa.flex_regs_len = 0; + + switch (dev_priv->perf.oa.metrics_set) { + case METRIC_SET_ID_RENDER_BASIC: + return select_render_basic_config(dev_priv); + default: + return -ENODEV; + } +} + +static ssize_t +show_render_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_BASIC); +} + +static struct device_attribute dev_attr_render_basic_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_render_basic_id, + .store = NULL, +}; + +static struct attribute *attrs_render_basic[] = { + &dev_attr_render_basic_id.attr, + NULL, +}; + +static struct attribute_group group_render_basic = { + .name = "fdfc01cc-e28e-423a-aae0-b5ed5d4d7a9f", + .attrs = attrs_render_basic, +}; + +int +i915_perf_init_sysfs_skl(struct drm_i915_private *dev_priv) +{ + int ret; + + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); + if (ret) + goto error_render_basic; + + return 0; + +error_render_basic: + return ret; +} + +void +i915_perf_deinit_sysfs_skl(struct drm_i915_private *dev_priv) +{ + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); +} diff --git a/drivers/gpu/drm/i915/i915_oa_skl.h b/drivers/gpu/drm/i915/i915_oa_skl.h new file mode 100644 index 00000000000000..997a2c553256a1 --- /dev/null +++ b/drivers/gpu/drm/i915/i915_oa_skl.h @@ -0,0 +1,38 @@ +/* + * Autogenerated file, DO NOT EDIT manually! + * + * Copyright (c) 2015 Intel Corporation + * + * Permission is hereby granted, free of charge, to any person obtaining a + * copy of this software and associated documentation files (the "Software"), + * to deal in the Software without restriction, including without limitation + * the rights to use, copy, modify, merge, publish, distribute, sublicense, + * and/or sell copies of the Software, and to permit persons to whom the + * Software is furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice (including the next + * paragraph) shall be included in all copies or substantial portions of the + * Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING + * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS + * IN THE SOFTWARE. + * + */ + +#ifndef __I915_OA_SKL_H__ +#define __I915_OA_SKL_H__ + +extern int i915_oa_n_builtin_metric_sets_skl; + +extern int i915_oa_select_metric_set_skl(struct drm_i915_private *dev_priv); + +extern int i915_perf_init_sysfs_skl(struct drm_i915_private *dev_priv); + +extern void i915_perf_deinit_sysfs_skl(struct drm_i915_private *dev_priv); + +#endif From e9aaf89be785afd6bbdb58dea52b3ff1b14c20d2 Mon Sep 17 00:00:00 2001 From: Robert Bragg Date: Tue, 22 Sep 2015 17:59:00 +0100 Subject: [PATCH 18/21] drm/i915: Add OA unit support for Gen 8+ Enables access to OA unit metrics for BDW, CHV and SKL which all share the same OA unit design. Signed-off-by: Robert Bragg --- drivers/gpu/drm/i915/i915_drv.h | 7 + drivers/gpu/drm/i915/i915_gem_context.c | 2 + drivers/gpu/drm/i915/i915_perf.c | 543 +++++++++++++++++++++++- drivers/gpu/drm/i915/intel_lrc.c | 4 + drivers/gpu/drm/i915/intel_ringbuffer.h | 2 + include/uapi/drm/i915_drm.h | 19 +- 6 files changed, 553 insertions(+), 24 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index d6e89e957bc5df..c409c8f1db38ee 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -1784,6 +1784,7 @@ struct i915_oa_ops { void (*update_oacontrol)(struct drm_i915_private *dev_priv); void (*update_hw_ctx_id_locked)(struct drm_i915_private *dev_priv, u32 ctx_id); + void (*legacy_ctx_switch_unlocked)(struct drm_i915_gem_request *req); void (*read)(struct i915_perf_stream *stream, struct i915_perf_read_state *read_state); bool (*oa_buffer_is_empty)(struct drm_i915_private *dev_priv); @@ -2071,10 +2072,14 @@ struct drm_i915_private { u8 *addr; u32 head; u32 tail; + u32 last_ctx_id; int format; int format_size; } oa_buffer; + u32 ctx_oactxctrl_off; + u32 ctx_flexeu0_off; + struct i915_oa_ops ops; const struct i915_oa_format *oa_formats; int n_builtin_sets; @@ -3321,6 +3326,8 @@ int i915_perf_open_ioctl(struct drm_device *dev, void *data, struct drm_file *file); void i915_oa_context_pin_notify(struct drm_i915_private *dev_priv, struct intel_context *context); +void i915_oa_legacy_ctx_switch_notify(struct drm_i915_gem_request *req); +void i915_oa_update_reg_state(struct intel_engine_cs *ring, uint32_t *reg_state); /* i915_gem_evict.c */ int __must_check i915_gem_evict_something(struct drm_device *dev, diff --git a/drivers/gpu/drm/i915/i915_gem_context.c b/drivers/gpu/drm/i915/i915_gem_context.c index 9688a825f4c56f..3a90e798e431b0 100644 --- a/drivers/gpu/drm/i915/i915_gem_context.c +++ b/drivers/gpu/drm/i915/i915_gem_context.c @@ -828,6 +828,8 @@ static int do_switch(struct drm_i915_gem_request *req) } } + i915_oa_legacy_ctx_switch_notify(req); + return 0; unpin_out: diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index 5aa49127487349..c5447b4382907d 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -28,6 +28,9 @@ #include "intel_ringbuffer.h" #include "intel_lrc.h" #include "i915_oa_hsw.h" +#include "i915_oa_bdw.h" +#include "i915_oa_chv.h" +#include "i915_oa_skl.h" /* Must be a power of two */ #define OA_BUFFER_SIZE SZ_16M @@ -69,6 +72,13 @@ static struct i915_oa_format hsw_oa_formats[I915_OA_FORMAT_MAX] = { [I915_OA_FORMAT_C4_B8] = { 7, 64 }, }; +static struct i915_oa_format gen8_plus_oa_formats[I915_OA_FORMAT_MAX] = { + [I915_OA_FORMAT_A12] = { 0, 64 }, + [I915_OA_FORMAT_A12_B8_C8] = { 2, 128 }, + [I915_OA_FORMAT_A32u40_A4u32_B8_C8] = { 5, 256 }, + [I915_OA_FORMAT_C4_B8] = { 7, 64 }, +}; + #define SAMPLE_OA_REPORT (1<<0) struct perf_open_properties @@ -85,6 +95,14 @@ struct perf_open_properties u32 oa_period_exponent; }; +static bool gen8_oa_buffer_is_empty(struct drm_i915_private *dev_priv) +{ + u32 head = I915_READ(GEN8_OAHEADPTR); + u32 tail = I915_READ(GEN8_OATAILPTR); + + return OA_TAKEN(tail, head) == 0; +} + static bool gen7_oa_buffer_is_empty(struct drm_i915_private *dev_priv) { u32 oastatus2 = I915_READ(GEN7_OASTATUS2); @@ -141,6 +159,116 @@ static bool append_oa_sample(struct i915_perf_stream *stream, return true; } +static u32 gen8_append_oa_reports(struct i915_perf_stream *stream, + struct i915_perf_read_state *read_state, + u32 head, + u32 tail) +{ + struct drm_i915_private *dev_priv = stream->dev_priv; + int report_size = dev_priv->perf.oa.oa_buffer.format_size; + u8 *oa_buf_base = dev_priv->perf.oa.oa_buffer.addr; + u32 mask = (OA_BUFFER_SIZE - 1); + u8 *report; + u32 taken; + + head -= dev_priv->perf.oa.oa_buffer.gtt_offset; + tail -= dev_priv->perf.oa.oa_buffer.gtt_offset; + + /* Note: the gpu doesn't wrap the tail according to the OA buffer size + * so when we need to make sure our head/tail values are in-bounds we + * use the above mask. + */ + + while ((taken = OA_TAKEN(tail, head))) { + u32 ctx_id; + + /* The tail increases in 64 byte increments, not in + * format_size steps. */ + if (taken < report_size) + break; + + /* All the report sizes factor neatly into the buffer + * size so we never expect to see a report split + * between the beginning and end of the buffer... */ + BUG_ON((OA_BUFFER_SIZE - (head & mask)) < report_size); + + report = oa_buf_base + (head & mask); + + ctx_id = *(u32 *)(report + 12); + if (i915.enable_execlists) { + /* XXX: Just keep the lower 20 bits for now since I'm + * not entirely sure if the HW touches any of the higher + * bits */ + ctx_id &= 0xfffff; + } + + if (dev_priv->perf.oa.exclusive_stream->enabled) { + + /* NB: For Gen 8 we handle per-context report filtering + * ourselves instead of programming the OA unit with a + * specific context id. + * + * NB: To allow userspace to calculate all counter + * deltas for a specific context we have to send the + * first report belonging to any subsequently + * switched-too context. + */ + if (!dev_priv->perf.oa.exclusive_stream->ctx || + (dev_priv->perf.oa.specific_ctx_id == ctx_id || + (dev_priv->perf.oa.specific_ctx_id != + dev_priv->perf.oa.oa_buffer.last_ctx_id))) { + + if (!append_oa_sample(stream, read_state, report)) + break; + } + } + + /* If append_oa_sample() returns false we shouldn't progress + * head so we update it afterwards... */ + dev_priv->perf.oa.oa_buffer.last_ctx_id = ctx_id; + head += report_size; + } + + return dev_priv->perf.oa.oa_buffer.gtt_offset + head; +} + +static void gen8_oa_read(struct i915_perf_stream *stream, + struct i915_perf_read_state *read_state) +{ + struct drm_i915_private *dev_priv = stream->dev_priv; + u32 oastatus; + u32 head; + u32 tail; + + WARN_ON(!dev_priv->perf.oa.oa_buffer.addr); + + head = I915_READ(GEN8_OAHEADPTR); + tail = I915_READ(GEN8_OATAILPTR); + oastatus = I915_READ(GEN8_OASTATUS); + + if (unlikely(oastatus & (GEN8_OASTATUS_OABUFFER_OVERFLOW | + GEN8_OASTATUS_REPORT_LOST))) { + + if (oastatus & GEN8_OASTATUS_OABUFFER_OVERFLOW) { + if (append_oa_status(stream, read_state, + DRM_I915_PERF_RECORD_OA_BUFFER_OVERFLOW)) + oastatus &= ~GEN8_OASTATUS_OABUFFER_OVERFLOW; + } + + if (oastatus & GEN8_OASTATUS_REPORT_LOST) { + if (append_oa_status(stream, read_state, + DRM_I915_PERF_RECORD_OA_REPORT_LOST)) + oastatus &= ~GEN8_OASTATUS_REPORT_LOST; + } + + I915_WRITE(GEN8_OASTATUS, oastatus); + } + + head = gen8_append_oa_reports(stream, read_state, head, tail); + + I915_WRITE(GEN8_OAHEADPTR, head); +} + static u32 gen7_append_oa_reports(struct i915_perf_stream *stream, struct i915_perf_read_state *read_state, u32 head, @@ -335,6 +463,23 @@ static void gen7_init_oa_buffer(struct drm_i915_private *dev_priv) OABUFFER_SIZE_16M); /* tail */ } +static void gen8_init_oa_buffer(struct drm_i915_private *dev_priv) +{ + I915_WRITE(GEN8_OAHEADPTR, + dev_priv->perf.oa.oa_buffer.gtt_offset); + /* PRM says: + * + * "This MMIO must be set before the OATAILPTR + * register and after the OAHEADPTR register. This is + * to enable proper functionality of the overflow + * bit." + */ + I915_WRITE(GEN8_OABUFFER, dev_priv->perf.oa.oa_buffer.gtt_offset | + OABUFFER_SIZE_16M | OA_MEM_SELECT_GGTT); + I915_WRITE(GEN8_OATAILPTR, + dev_priv->perf.oa.oa_buffer.gtt_offset); +} + static int alloc_oa_buffer(struct drm_i915_private *dev_priv) { struct drm_i915_gem_object *bo; @@ -437,6 +582,154 @@ static void hsw_disable_metric_set(struct drm_i915_private *dev_priv) ~GT_NOA_ENABLE)); } +/* Manages updating the per-context aspects of the OA stream + * configuration across all contexts. + * + * The awkward consideration here is that OACTXCONTROL controls the + * exponent for periodic sampling which is primarily used for system + * wide profiling where we'd like a consistent sampling period even in + * the face of context switches. + * + * Our approach of updating the register state context (as opposed to + * say using a workaround batch buffer) ensures that the hardware + * won't automatically reload an out-of-date timer exponent even + * transiently before a WA BB could be parsed. + */ +static int configure_all_contexts(struct drm_i915_private *dev_priv) +{ + struct drm_device *dev = dev_priv->dev; + struct intel_context *ctx; + struct intel_engine_cs *ring; + int ring_id; + int ret; + + ret = mutex_lock_interruptible(&dev->struct_mutex); + if (ret) + return ret; + + list_for_each_entry(ctx, &dev_priv->context_list, link) { + + for_each_ring(ring, dev_priv, ring_id) { + /* The actual update of the register state context + * will happen the next time this logical ring + * is submitted. (See i915_oa_update_reg_state() + * which hooks into execlists_update_context()) + */ + atomic_set(&ring->oa_state_dirty, true); + } + } + + mutex_unlock(&dev->struct_mutex); + + /* Now update the current context. + * + * Note: Using MMIO to update per-context registers requires + * some extra care... + */ + ret = intel_uncore_begin_ctx_mmio(dev_priv); + if (ret) { + DRM_ERROR("Failed to bring RCS out of idle to update current ctx OA state"); + return ret; + } + + I915_WRITE(GEN8_OACTXCONTROL, ((dev_priv->perf.oa.period_exponent << + GEN8_OA_TIMER_PERIOD_SHIFT) | + (dev_priv->perf.oa.periodic ? + GEN8_OA_TIMER_ENABLE : 0) | + GEN8_OA_COUNTER_RESUME)); + + config_oa_regs(dev_priv, dev_priv->perf.oa.flex_regs, + dev_priv->perf.oa.flex_regs_len); + + intel_uncore_end_ctx_mmio(dev_priv); + + return 0; +} + +static int bdw_enable_metric_set(struct drm_i915_private *dev_priv) +{ + int ret = i915_oa_select_metric_set_bdw(dev_priv); + + if (ret) + return ret; + + I915_WRITE(GDT_CHICKEN_BITS, 0xA0); + config_oa_regs(dev_priv, dev_priv->perf.oa.mux_regs, + dev_priv->perf.oa.mux_regs_len); + I915_WRITE(GDT_CHICKEN_BITS, 0x80); + config_oa_regs(dev_priv, dev_priv->perf.oa.b_counter_regs, + dev_priv->perf.oa.b_counter_regs_len); + + configure_all_contexts(dev_priv); + + return 0; +} + +static void bdw_disable_metric_set(struct drm_i915_private *dev_priv) +{ + I915_WRITE(GEN6_UCGCTL1, (I915_READ(GEN6_UCGCTL1) & + ~GEN6_CSUNIT_CLOCK_GATE_DISABLE)); + I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) | + GEN7_DOP_CLOCK_GATE_ENABLE)); +#warning "BDW: Do we need to write to CHICKEN2 to disable DOP clock gating when idle? (vpg does this)" +} + +static int chv_enable_metric_set(struct drm_i915_private *dev_priv) +{ + int ret = i915_oa_select_metric_set_chv(dev_priv); + + if (ret) + return ret; + + I915_WRITE(GDT_CHICKEN_BITS, 0xA0); + config_oa_regs(dev_priv, dev_priv->perf.oa.mux_regs, + dev_priv->perf.oa.mux_regs_len); + I915_WRITE(GDT_CHICKEN_BITS, 0x80); + config_oa_regs(dev_priv, dev_priv->perf.oa.b_counter_regs, + dev_priv->perf.oa.b_counter_regs_len); + + configure_all_contexts(dev_priv); + + return 0; +} + +static void chv_disable_metric_set(struct drm_i915_private *dev_priv) +{ + I915_WRITE(GEN6_UCGCTL1, (I915_READ(GEN6_UCGCTL1) & + ~GEN6_CSUNIT_CLOCK_GATE_DISABLE)); + I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) | + GEN7_DOP_CLOCK_GATE_ENABLE)); +#warning "CHV: Do we need to write to CHICKEN2 to disable DOP clock gating when idle? (vpg does this)" +} + +static int skl_enable_metric_set(struct drm_i915_private *dev_priv) +{ + int ret = i915_oa_select_metric_set_skl(dev_priv); + + if (ret) + return ret; + + I915_WRITE(GDT_CHICKEN_BITS, 0xA0); + config_oa_regs(dev_priv, dev_priv->perf.oa.mux_regs, + dev_priv->perf.oa.mux_regs_len); + I915_WRITE(GDT_CHICKEN_BITS, 0x80); + config_oa_regs(dev_priv, dev_priv->perf.oa.b_counter_regs, + dev_priv->perf.oa.b_counter_regs_len); + + configure_all_contexts(dev_priv); + + return 0; +} + +static void skl_disable_metric_set(struct drm_i915_private *dev_priv) +{ + I915_WRITE(GEN6_UCGCTL1, (I915_READ(GEN6_UCGCTL1) & + ~GEN6_CSUNIT_CLOCK_GATE_DISABLE)); + I915_WRITE(GEN7_MISCCPCTL, (I915_READ(GEN7_MISCCPCTL) | + GEN7_DOP_CLOCK_GATE_ENABLE)); +#warning "SKL: Do we need to write to CHICKEN2 to disable DOP clock gating when idle? (vpg does this)" +} + static void gen7_update_oacontrol_locked(struct drm_i915_private *dev_priv) { assert_spin_locked(&dev_priv->perf.hook_lock); @@ -491,6 +784,23 @@ static void gen7_oa_enable(struct drm_i915_private *dev_priv) OA_MEM_SELECT_GGTT); } +static void gen8_oa_enable(struct drm_i915_private *dev_priv) +{ + u32 report_format = dev_priv->perf.oa.oa_buffer.format; + u32 tail; + + /* Note: we don't rely on the hardware to perform single context + * filtering and instead filter on the cpu based on the context-id + * field of reports */ + I915_WRITE(GEN8_OACONTROL, (report_format << + GEN8_OA_REPORT_FORMAT_SHIFT) | + GEN8_OA_COUNTER_ENABLE); + + /* Reset the head ptr so we don't forward reports from before now. */ + tail = I915_READ(GEN8_OATAILPTR); + I915_WRITE(GEN8_OAHEADPTR, tail); +} + static void i915_oa_stream_enable(struct i915_perf_stream *stream) { struct drm_i915_private *dev_priv = stream->dev_priv; @@ -508,6 +818,11 @@ static void gen7_oa_disable(struct drm_i915_private *dev_priv) I915_WRITE(GEN7_OACONTROL, 0); } +static void gen8_oa_disable(struct drm_i915_private *dev_priv) +{ + I915_WRITE(GEN8_OACONTROL, 0); +} + static void i915_oa_stream_disable(struct i915_perf_stream *stream) { struct drm_i915_private *dev_priv = stream->dev_priv; @@ -573,6 +888,10 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, if (dev_priv->perf.oa.periodic) dev_priv->perf.oa.period_exponent = props->oa_period_exponent; + if (i915.enable_execlists && stream->ctx) + dev_priv->perf.oa.specific_ctx_id = + intel_execlists_ctx_id(stream->ctx); + ret = alloc_oa_buffer(dev_priv); if (ret) return ret; @@ -648,6 +967,131 @@ void i915_oa_context_pin_notify(struct drm_i915_private *dev_priv, spin_unlock_irqrestore(&dev_priv->perf.hook_lock, flags); } +static void gen8_legacy_ctx_switch_unlocked(struct drm_i915_gem_request *req) +{ + struct drm_i915_private *dev_priv = req->i915; + struct intel_engine_cs *ring = req->ring; + const struct i915_oa_reg *flex_regs = dev_priv->perf.oa.flex_regs; + int n_flex_regs = dev_priv->perf.oa.flex_regs_len; + int ret; + int i; + + if (!atomic_read(&ring->oa_state_dirty)) + return; + + ret = intel_ring_begin(req, n_flex_regs * 2 + 4); + if (ret) + return; + + intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(n_flex_regs + 1)); + + intel_ring_emit(ring, GEN8_OACTXCONTROL); + intel_ring_emit(ring, + (dev_priv->perf.oa.period_exponent << + GEN8_OA_TIMER_PERIOD_SHIFT) | + (dev_priv->perf.oa.periodic ? + GEN8_OA_TIMER_ENABLE : 0) | + GEN8_OA_COUNTER_RESUME); + + for (i = 0; i < n_flex_regs; i++) { + intel_ring_emit(ring, flex_regs[i].addr); + intel_ring_emit(ring, flex_regs[i].value); + } + intel_ring_emit(ring, MI_NOOP); + intel_ring_advance(ring); + + atomic_set(&ring->oa_state_dirty, false); +} + +void i915_oa_legacy_ctx_switch_notify(struct drm_i915_gem_request *req) +{ + struct drm_i915_private *dev_priv = req->i915; + + if (!dev_priv->perf.initialized) + return; + + if (dev_priv->perf.oa.ops.legacy_ctx_switch_unlocked == NULL) + return; + + if (dev_priv->perf.oa.exclusive_stream && + dev_priv->perf.oa.exclusive_stream->enabled) { + + /* XXX: We don't take a lock here and this may run + * async with respect to stream methods. Notably we + * don't want to block context switches by long i915 + * perf read() operations. + * + * It's expect to always be safe to read the + * dev_priv->perf state needed here, and expected to + * be benign to redundantly update the state if the OA + * unit has been disabled since oa_state_dirty was + * last set. + */ + dev_priv->perf.oa.ops.legacy_ctx_switch_unlocked(req); + } +} + +static void gen8_update_reg_state_unlocked(struct intel_engine_cs *ring, + uint32_t *reg_state) +{ + struct drm_i915_private *dev_priv = ring->dev->dev_private; + const struct i915_oa_reg *flex_regs = dev_priv->perf.oa.flex_regs; + int n_flex_regs = dev_priv->perf.oa.flex_regs_len; + int ctx_oactxctrl = dev_priv->perf.oa.ctx_oactxctrl_off; + int ctx_flexeu0 = dev_priv->perf.oa.ctx_flexeu0_off; + int i; + + if (!atomic_read(&ring->oa_state_dirty)) + return; + + reg_state[ctx_oactxctrl] = GEN8_OACTXCONTROL; + reg_state[ctx_oactxctrl+1] = (dev_priv->perf.oa.period_exponent << + GEN8_OA_TIMER_PERIOD_SHIFT) | + (dev_priv->perf.oa.periodic ? + GEN8_OA_TIMER_ENABLE : 0) | + GEN8_OA_COUNTER_RESUME; + + for (i = 0; i < n_flex_regs; i++) { + uint32_t offset = flex_regs[i].addr; + + /* Map from mmio address to register state context + * offset... */ + + offset -= EU_PERF_CNTL0; + + offset >>= 5; /* Flex EU mmio registers are separated by 256 + * bytes, here they are separated by 8 bytes */ + + /* EU_PERF_CNTL0 offset in register state context... */ + offset += ctx_flexeu0; + + reg_state[offset] = flex_regs[i].addr; + reg_state[offset+1] = flex_regs[i].value; + } + + atomic_set(&ring->oa_state_dirty, false); +} + +void i915_oa_update_reg_state(struct intel_engine_cs *ring, uint32_t *reg_state) +{ + struct drm_i915_private *dev_priv = ring->dev->dev_private; + + if (!dev_priv->perf.initialized) + return; + + /* XXX: We don't take a lock here and this may run async with + * respect to stream methods. Notably we don't want to block + * context switches by long i915 perf read() operations. + * + * It's expect to always be safe to read the dev_priv->perf + * state needed here, and expected to be benign to redundantly + * update the state if the OA unit has been disabled since + * oa_state_dirty was last set. + */ + + gen8_update_reg_state_unlocked(ring, reg_state); +} + static ssize_t i915_perf_read_locked(struct i915_perf_stream *stream, struct file *file, char __user *buf, @@ -1122,7 +1566,9 @@ void i915_perf_init(struct drm_device *dev) { struct drm_i915_private *dev_priv = to_i915(dev); - if (!IS_HASWELL(dev)) + if (!(IS_HASWELL(dev) || + IS_BROADWELL(dev) || IS_CHERRYVIEW(dev) || + IS_SKYLAKE(dev))) return; dev_priv->perf.metrics_kobj = @@ -1139,30 +1585,86 @@ void i915_perf_init(struct drm_device *dev) mutex_init(&dev_priv->perf.lock); spin_lock_init(&dev_priv->perf.hook_lock); - dev_priv->perf.oa.ops.init_oa_buffer = gen7_init_oa_buffer; - dev_priv->perf.oa.ops.enable_metric_set = hsw_enable_metric_set; - dev_priv->perf.oa.ops.disable_metric_set = hsw_disable_metric_set; - dev_priv->perf.oa.ops.oa_enable = gen7_oa_enable; - dev_priv->perf.oa.ops.oa_disable = gen7_oa_disable; - dev_priv->perf.oa.ops.update_hw_ctx_id_locked = gen7_update_hw_ctx_id_locked; - dev_priv->perf.oa.ops.read = gen7_oa_read; - dev_priv->perf.oa.ops.oa_buffer_is_empty = gen7_oa_buffer_is_empty; + if (IS_HASWELL(dev)) { + dev_priv->perf.oa.ops.init_oa_buffer = gen7_init_oa_buffer; + dev_priv->perf.oa.ops.enable_metric_set = hsw_enable_metric_set; + dev_priv->perf.oa.ops.disable_metric_set = hsw_disable_metric_set; + dev_priv->perf.oa.ops.oa_enable = gen7_oa_enable; + dev_priv->perf.oa.ops.oa_disable = gen7_oa_disable; + dev_priv->perf.oa.ops.update_hw_ctx_id_locked = gen7_update_hw_ctx_id_locked; + dev_priv->perf.oa.ops.read = gen7_oa_read; + dev_priv->perf.oa.ops.oa_buffer_is_empty = gen7_oa_buffer_is_empty; - dev_priv->perf.oa.oa_formats = hsw_oa_formats; + dev_priv->perf.oa.oa_formats = hsw_oa_formats; - dev_priv->perf.oa.n_builtin_sets = - i915_oa_n_builtin_metric_sets_hsw; + dev_priv->perf.oa.n_builtin_sets = + i915_oa_n_builtin_metric_sets_hsw; - if (i915_perf_init_sysfs_hsw(dev_priv)) { - kobject_put(dev_priv->perf.metrics_kobj); - dev_priv->perf.metrics_kobj = NULL; - return; + if (i915_perf_init_sysfs_hsw(dev_priv)) + goto sysfs_error; + } else { + dev_priv->perf.oa.ops.init_oa_buffer = gen8_init_oa_buffer; + dev_priv->perf.oa.ops.oa_enable = gen8_oa_enable; + dev_priv->perf.oa.ops.oa_disable = gen8_oa_disable; + dev_priv->perf.oa.ops.read = gen8_oa_read; + dev_priv->perf.oa.ops.oa_buffer_is_empty = gen8_oa_buffer_is_empty; + + dev_priv->perf.oa.oa_formats = gen8_plus_oa_formats; + + if (!i915.enable_execlists) { + dev_priv->perf.oa.ops.legacy_ctx_switch_unlocked = + gen8_legacy_ctx_switch_unlocked; + } + + if (IS_BROADWELL(dev)) { + dev_priv->perf.oa.ops.enable_metric_set = + bdw_enable_metric_set; + dev_priv->perf.oa.ops.disable_metric_set = + bdw_disable_metric_set; + dev_priv->perf.oa.ctx_oactxctrl_off = 0x120; + dev_priv->perf.oa.ctx_flexeu0_off = 0x2ce; + dev_priv->perf.oa.n_builtin_sets = + i915_oa_n_builtin_metric_sets_bdw; + + if (i915_perf_init_sysfs_bdw(dev_priv)) + goto sysfs_error; + } else if (IS_CHERRYVIEW(dev)) { + dev_priv->perf.oa.ops.enable_metric_set = + chv_enable_metric_set; + dev_priv->perf.oa.ops.disable_metric_set = + chv_disable_metric_set; + dev_priv->perf.oa.ctx_oactxctrl_off = 0x120; + dev_priv->perf.oa.ctx_flexeu0_off = 0x2ce; + dev_priv->perf.oa.n_builtin_sets = + i915_oa_n_builtin_metric_sets_chv; + + if (i915_perf_init_sysfs_chv(dev_priv)) + goto sysfs_error; + } else if (IS_SKYLAKE(dev)) { + dev_priv->perf.oa.ops.enable_metric_set = + skl_enable_metric_set; + dev_priv->perf.oa.ops.disable_metric_set = + skl_disable_metric_set; + dev_priv->perf.oa.ctx_oactxctrl_off = 0x128; + dev_priv->perf.oa.ctx_flexeu0_off = 0x3de; + dev_priv->perf.oa.n_builtin_sets = + i915_oa_n_builtin_metric_sets_skl; + + if (i915_perf_init_sysfs_skl(dev_priv)) + goto sysfs_error; + } } dev_priv->perf.sysctl_header = register_sysctl_table(dev_root); dev_priv->perf.initialized = true; + return; + +sysfs_error: + kobject_put(dev_priv->perf.metrics_kobj); + dev_priv->perf.metrics_kobj = NULL; + return; } @@ -1175,7 +1677,14 @@ void i915_perf_fini(struct drm_device *dev) unregister_sysctl_table(dev_priv->perf.sysctl_header); - i915_perf_deinit_sysfs_hsw(dev_priv); + if (IS_HASWELL(dev)) + i915_perf_deinit_sysfs_hsw(dev_priv); + else if (IS_BROADWELL(dev)) + i915_perf_deinit_sysfs_bdw(dev_priv); + else if (IS_CHERRYVIEW(dev)) + i915_perf_deinit_sysfs_chv(dev_priv); + else if (IS_SKYLAKE(dev)) + i915_perf_deinit_sysfs_skl(dev_priv); kobject_put(dev_priv->perf.metrics_kobj); dev_priv->perf.metrics_kobj = NULL; diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 548ee53f1cb939..4789555aa80501 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -385,6 +385,8 @@ static int execlists_update_context(struct drm_i915_gem_request *rq) ASSIGN_CTX_PDP(ppgtt, reg_state, 0); } + i915_oa_update_reg_state(ring, reg_state); + kunmap_atomic(reg_state); return 0; @@ -2354,6 +2356,8 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev); } + i915_oa_update_reg_state(ring, reg_state); + kunmap_atomic(reg_state); ctx_obj->dirty = 1; diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 49fa41dc0eb66a..302882c2b77426 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -346,6 +346,8 @@ struct intel_engine_cs { * to encode the command length in the header). */ u32 (*get_cmd_length_mask)(u32 cmd_header); + + atomic_t oa_state_dirty; }; bool intel_ring_initialized(struct intel_engine_cs *ring); diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 68f2bb64094154..4a6789548d7e42 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -1135,13 +1135,18 @@ struct drm_i915_gem_context_param { }; enum drm_i915_oa_format { - I915_OA_FORMAT_A13 = 1, - I915_OA_FORMAT_A29, - I915_OA_FORMAT_A13_B8_C8, - I915_OA_FORMAT_B4_C8, - I915_OA_FORMAT_A45_B8_C8, - I915_OA_FORMAT_B4_C8_A16, - I915_OA_FORMAT_C4_B8, + I915_OA_FORMAT_A13 = 1, /* HSW only */ + I915_OA_FORMAT_A29, /* HSW only */ + I915_OA_FORMAT_A13_B8_C8, /* HSW only */ + I915_OA_FORMAT_B4_C8, /* HSW only */ + I915_OA_FORMAT_A45_B8_C8, /* HSW only */ + I915_OA_FORMAT_B4_C8_A16, /* HSW only */ + I915_OA_FORMAT_C4_B8, /* HSW+ */ + + /* Gen8+ */ + I915_OA_FORMAT_A12, + I915_OA_FORMAT_A12_B8_C8, + I915_OA_FORMAT_A32u40_A4u32_B8_C8, I915_OA_FORMAT_MAX /* non-ABI */ }; From 753f3707b2b8e8904b0f5fa2518b52e7350bc292 Mon Sep 17 00:00:00 2001 From: Robert Bragg Date: Wed, 7 Oct 2015 14:27:00 +0100 Subject: [PATCH 19/21] drm/i915: Add more OA configs for BDW, CHV + SKL Signed-off-by: Robert Bragg --- drivers/gpu/drm/i915/i915_oa_bdw.c | 3849 +++++++++++++++++++++++++++- drivers/gpu/drm/i915/i915_oa_chv.c | 2219 +++++++++++++++- drivers/gpu/drm/i915/i915_oa_skl.c | 2556 +++++++++++++++++- 3 files changed, 8621 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_oa_bdw.c b/drivers/gpu/drm/i915/i915_oa_bdw.c index a352799f50efda..604a76f85cf919 100644 --- a/drivers/gpu/drm/i915/i915_oa_bdw.c +++ b/drivers/gpu/drm/i915/i915_oa_bdw.c @@ -30,9 +30,27 @@ enum metric_set_id { METRIC_SET_ID_RENDER_BASIC = 1, + METRIC_SET_ID_COMPUTE_BASIC, + METRIC_SET_ID_RENDER_PIPE_PROFILE, + METRIC_SET_ID_MEMORY_READS, + METRIC_SET_ID_MEMORY_WRITES, + METRIC_SET_ID_COMPUTE_EXTENDED, + METRIC_SET_ID_COMPUTE_L3_CACHE, + METRIC_SET_ID_DATA_PORT_READS_COALESCING, + METRIC_SET_ID_DATA_PORT_WRITES_COALESCING, + METRIC_SET_ID_HDC_AND_SF, + METRIC_SET_ID_L3_1, + METRIC_SET_ID_L3_2, + METRIC_SET_ID_L3_3, + METRIC_SET_ID_L3_4, + METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, + METRIC_SET_ID_SAMPLER_1, + METRIC_SET_ID_SAMPLER_2, + METRIC_SET_ID_TDL_1, + METRIC_SET_ID_TDL_2, }; -int i915_oa_n_builtin_metric_sets_bdw = 1; +int i915_oa_n_builtin_metric_sets_bdw = 19; static const struct i915_oa_reg b_counter_config_render_basic[] = { { 0x2710, 0x00000000 }, @@ -294,6 +312,3295 @@ static int select_render_basic_config(struct drm_i915_private *dev_priv) return 0; } +static const struct i915_oa_reg b_counter_config_compute_basic[] = { + { 0x2710, 0x00000000 }, + { 0x2714, 0x00800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x00800000 }, +}; + +static const struct i915_oa_reg flex_eu_config_compute_basic[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00000003 }, + { 0xE658, 0x00002001 }, + { 0xE758, 0x00778008 }, + { 0xE45c, 0x00088078 }, + { 0xE55c, 0x00808708 }, + { 0xE65c, 0x00a08908 }, +}; + +static const struct i915_oa_reg mux_config_compute_basic_1_0_slices_0x01[] = { + { 0x9888, 0x105C00E0 }, + { 0x9888, 0x105800E0 }, + { 0x9888, 0x103800E0 }, + { 0x9888, 0x3580001A }, + { 0x9888, 0x3B800060 }, + { 0x9888, 0x3D800005 }, + { 0x9888, 0x065C2100 }, + { 0x9888, 0x0A5C0041 }, + { 0x9888, 0x0C5C6600 }, + { 0x9888, 0x005C6580 }, + { 0x9888, 0x085C8000 }, + { 0x9888, 0x0E5C8000 }, + { 0x9888, 0x00580042 }, + { 0x9888, 0x08582080 }, + { 0x9888, 0x0C58004C }, + { 0x9888, 0x0E582580 }, + { 0x9888, 0x005B4000 }, + { 0x9888, 0x185B1000 }, + { 0x9888, 0x1A5B0104 }, + { 0x9888, 0x0C1FA800 }, + { 0x9888, 0x0E1FAA00 }, + { 0x9888, 0x101F02AA }, + { 0x9888, 0x08380042 }, + { 0x9888, 0x0A382080 }, + { 0x9888, 0x0E38404C }, + { 0x9888, 0x0238404B }, + { 0x9888, 0x00384000 }, + { 0x9888, 0x16380000 }, + { 0x9888, 0x18381145 }, + { 0x9888, 0x04380000 }, + { 0x9888, 0x0039A000 }, + { 0x9888, 0x06398000 }, + { 0x9888, 0x0839A000 }, + { 0x9888, 0x0A39A000 }, + { 0x9888, 0x0C39A000 }, + { 0x9888, 0x0E39A000 }, + { 0x9888, 0x02392000 }, + { 0x9888, 0x018A8000 }, + { 0x9888, 0x0F8A8000 }, + { 0x9888, 0x198A8000 }, + { 0x9888, 0x1B8AAAA0 }, + { 0x9888, 0x1D8A0002 }, + { 0x9888, 0x038A8000 }, + { 0x9888, 0x058A8000 }, + { 0x9888, 0x238B02A0 }, + { 0x9888, 0x258B5550 }, + { 0x9888, 0x278B0015 }, + { 0x9888, 0x1F850A80 }, + { 0x9888, 0x2185AAA0 }, + { 0x9888, 0x2385002A }, + { 0x9888, 0x01834000 }, + { 0x9888, 0x0F834000 }, + { 0x9888, 0x19835400 }, + { 0x9888, 0x1B830155 }, + { 0x9888, 0x03834000 }, + { 0x9888, 0x05834000 }, + { 0x9888, 0x0184C000 }, + { 0x9888, 0x07848000 }, + { 0x9888, 0x0984C000 }, + { 0x9888, 0x0B84C000 }, + { 0x9888, 0x0D84C000 }, + { 0x9888, 0x0F84C000 }, + { 0x9888, 0x03844000 }, + { 0x9888, 0x17808137 }, + { 0x9888, 0x1980C147 }, + { 0x9888, 0x1B80C0E5 }, + { 0x9888, 0x1D80C0E3 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x1180C000 }, + { 0x9888, 0x1F80C000 }, + { 0x9888, 0x13804000 }, + { 0x9888, 0x15800000 }, + { 0x0D24, 0x00000000 }, + { 0x9888, 0x4D801000 }, + { 0x9888, 0x4F800111 }, + { 0x9888, 0x43800062 }, + { 0x9888, 0x51800000 }, + { 0x9888, 0x45800062 }, + { 0x9888, 0x53800000 }, + { 0x9888, 0x47800062 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x3F801062 }, + { 0x9888, 0x41801084 }, +}; + +static const struct i915_oa_reg mux_config_compute_basic_1_2_slices_0x02[] = { + { 0x9888, 0x10DC00E0 }, + { 0x9888, 0x10D800E0 }, + { 0x9888, 0x10B800E0 }, + { 0x9888, 0x3580001A }, + { 0x9888, 0x3B800060 }, + { 0x9888, 0x3D800005 }, + { 0x9888, 0x06DC2100 }, + { 0x9888, 0x0ADC0041 }, + { 0x9888, 0x0CDC6600 }, + { 0x9888, 0x00DC6580 }, + { 0x9888, 0x08DC8000 }, + { 0x9888, 0x0EDC8000 }, + { 0x9888, 0x00D80042 }, + { 0x9888, 0x08D82080 }, + { 0x9888, 0x0CD8004C }, + { 0x9888, 0x0ED82580 }, + { 0x9888, 0x00DB4000 }, + { 0x9888, 0x18DB1000 }, + { 0x9888, 0x1ADB0104 }, + { 0x9888, 0x0C9FA800 }, + { 0x9888, 0x0E9FAA00 }, + { 0x9888, 0x109F02AA }, + { 0x9888, 0x08B80042 }, + { 0x9888, 0x0AB82080 }, + { 0x9888, 0x0EB8404C }, + { 0x9888, 0x02B8404B }, + { 0x9888, 0x00B84000 }, + { 0x9888, 0x16B80000 }, + { 0x9888, 0x18B81145 }, + { 0x9888, 0x04B80000 }, + { 0x9888, 0x00B9A000 }, + { 0x9888, 0x06B98000 }, + { 0x9888, 0x08B9A000 }, + { 0x9888, 0x0AB9A000 }, + { 0x9888, 0x0CB9A000 }, + { 0x9888, 0x0EB9A000 }, + { 0x9888, 0x02B92000 }, + { 0x9888, 0x01888000 }, + { 0x9888, 0x0D88F800 }, + { 0x9888, 0x0F88000F }, + { 0x9888, 0x03888000 }, + { 0x9888, 0x05888000 }, + { 0x9888, 0x238B0540 }, + { 0x9888, 0x258BAAA0 }, + { 0x9888, 0x278B002A }, + { 0x9888, 0x018C4000 }, + { 0x9888, 0x0F8C4000 }, + { 0x9888, 0x178C2000 }, + { 0x9888, 0x198C5500 }, + { 0x9888, 0x1B8C0015 }, + { 0x9888, 0x038C4000 }, + { 0x9888, 0x058C4000 }, + { 0x9888, 0x018DA000 }, + { 0x9888, 0x078D8000 }, + { 0x9888, 0x098DA000 }, + { 0x9888, 0x0B8DA000 }, + { 0x9888, 0x0D8DA000 }, + { 0x9888, 0x0F8DA000 }, + { 0x9888, 0x038D2000 }, + { 0x9888, 0x1F850A80 }, + { 0x9888, 0x2185AAA0 }, + { 0x9888, 0x2385002A }, + { 0x9888, 0x01834000 }, + { 0x9888, 0x0F834000 }, + { 0x9888, 0x19835400 }, + { 0x9888, 0x1B830155 }, + { 0x9888, 0x03834000 }, + { 0x9888, 0x05834000 }, + { 0x9888, 0x0184C000 }, + { 0x9888, 0x07848000 }, + { 0x9888, 0x0984C000 }, + { 0x9888, 0x0B84C000 }, + { 0x9888, 0x0D84C000 }, + { 0x9888, 0x0F84C000 }, + { 0x9888, 0x03844000 }, + { 0x9888, 0x17808137 }, + { 0x9888, 0x1980C147 }, + { 0x9888, 0x1B80C0E5 }, + { 0x9888, 0x1D80C0E3 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x1180C000 }, + { 0x9888, 0x1F80C000 }, + { 0x9888, 0x13804000 }, + { 0x9888, 0x15800000 }, + { 0x0D24, 0x00000000 }, + { 0x9888, 0x4D805000 }, + { 0x9888, 0x4F800555 }, + { 0x9888, 0x43800062 }, + { 0x9888, 0x51800000 }, + { 0x9888, 0x45800062 }, + { 0x9888, 0x53800000 }, + { 0x9888, 0x47800062 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x3F800062 }, + { 0x9888, 0x41800000 }, +}; + +static int select_compute_basic_config(struct drm_i915_private *dev_priv) +{ + if (INTEL_INFO(dev_priv)->slice_mask & 0x01) { + dev_priv->perf.oa.mux_regs = + mux_config_compute_basic_1_0_slices_0x01; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_compute_basic_1_0_slices_0x01); + } else if (INTEL_INFO(dev_priv)->slice_mask & 0x02) { + dev_priv->perf.oa.mux_regs = + mux_config_compute_basic_1_2_slices_0x02; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_compute_basic_1_2_slices_0x02); + } else { + DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set"); + return -EINVAL; + } + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_compute_basic; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_compute_basic); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_compute_basic; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_compute_basic); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { + { 0x2724, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2710, 0x00000000 }, + { 0x2770, 0x0007ffea }, + { 0x2774, 0x00007ffc }, + { 0x2778, 0x0007affa }, + { 0x277c, 0x0000f5fd }, + { 0x2780, 0x00079ffa }, + { 0x2784, 0x0000f3fb }, + { 0x2788, 0x0007bf7a }, + { 0x278c, 0x0000f7e7 }, + { 0x2790, 0x0007fefa }, + { 0x2794, 0x0000f7cf }, + { 0x2798, 0x00077ffa }, + { 0x279c, 0x0000efdf }, + { 0x27a0, 0x0006fffa }, + { 0x27a4, 0x0000cfbf }, + { 0x27a8, 0x0003fffa }, + { 0x27ac, 0x00005f7f }, +}; + +static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00015014 }, + { 0xE658, 0x00025024 }, + { 0xE758, 0x00035034 }, + { 0xE45c, 0x00045044 }, + { 0xE55c, 0x00055054 }, + { 0xE65c, 0x00065064 }, +}; + +static const struct i915_oa_reg mux_config_render_pipe_profile[] = { + { 0x9888, 0x0A1E0000 }, + { 0x9888, 0x0C1F000F }, + { 0x9888, 0x10176800 }, + { 0x9888, 0x1191001F }, + { 0x9888, 0x0B880320 }, + { 0x9888, 0x01890C40 }, + { 0x9888, 0x118A1C00 }, + { 0x9888, 0x118D7C00 }, + { 0x9888, 0x118E0020 }, + { 0x9888, 0x118F4C00 }, + { 0x9888, 0x11900000 }, + { 0x9888, 0x13900001 }, + { 0x9888, 0x065C4000 }, + { 0x9888, 0x0C3D8000 }, + { 0x9888, 0x06584000 }, + { 0x9888, 0x0C5B4000 }, + { 0x9888, 0x081E0040 }, + { 0x9888, 0x0E1E0000 }, + { 0x9888, 0x021F5400 }, + { 0x9888, 0x001F0000 }, + { 0x9888, 0x101F0010 }, + { 0x9888, 0x0E1F0080 }, + { 0x9888, 0x0C384000 }, + { 0x9888, 0x06392000 }, + { 0x9888, 0x0C13C000 }, + { 0x9888, 0x06164000 }, + { 0x9888, 0x06170012 }, + { 0x9888, 0x00170000 }, + { 0x9888, 0x01910005 }, + { 0x9888, 0x07880002 }, + { 0x9888, 0x01880C00 }, + { 0x9888, 0x0F880000 }, + { 0x9888, 0x0D880000 }, + { 0x9888, 0x05880000 }, + { 0x9888, 0x09890032 }, + { 0x9888, 0x078A0800 }, + { 0x9888, 0x0F8A0A00 }, + { 0x9888, 0x198A4000 }, + { 0x9888, 0x1B8A2000 }, + { 0x9888, 0x1D8A0000 }, + { 0x9888, 0x038A4000 }, + { 0x9888, 0x0B8A8000 }, + { 0x9888, 0x0D8A8000 }, + { 0x9888, 0x238B54C0 }, + { 0x9888, 0x258BAA55 }, + { 0x9888, 0x278B0019 }, + { 0x9888, 0x198C0100 }, + { 0x9888, 0x058C4000 }, + { 0x9888, 0x0F8D0015 }, + { 0x9888, 0x018D1000 }, + { 0x9888, 0x098D8000 }, + { 0x9888, 0x0B8DF000 }, + { 0x9888, 0x0D8D3000 }, + { 0x9888, 0x038DE000 }, + { 0x9888, 0x058D3000 }, + { 0x9888, 0x0D8E0004 }, + { 0x9888, 0x058E000C }, + { 0x9888, 0x098E0000 }, + { 0x9888, 0x078E0000 }, + { 0x9888, 0x038E0000 }, + { 0x9888, 0x0B8F0020 }, + { 0x9888, 0x198F0C00 }, + { 0x9888, 0x078F8000 }, + { 0x9888, 0x098F4000 }, + { 0x9888, 0x0B900980 }, + { 0x9888, 0x03900D80 }, + { 0x9888, 0x01900000 }, + { 0x9888, 0x1F85AA80 }, + { 0x9888, 0x2185AAAA }, + { 0x9888, 0x2385002A }, + { 0x9888, 0x01834000 }, + { 0x9888, 0x0F834000 }, + { 0x9888, 0x19835400 }, + { 0x9888, 0x1B830155 }, + { 0x9888, 0x03834000 }, + { 0x9888, 0x05834000 }, + { 0x9888, 0x07834000 }, + { 0x9888, 0x09834000 }, + { 0x9888, 0x0B834000 }, + { 0x9888, 0x0D834000 }, + { 0x9888, 0x0184C000 }, + { 0x9888, 0x0784C000 }, + { 0x9888, 0x0984C000 }, + { 0x9888, 0x0B84C000 }, + { 0x9888, 0x0D84C000 }, + { 0x9888, 0x0F84C000 }, + { 0x9888, 0x0384C000 }, + { 0x9888, 0x0584C000 }, + { 0x9888, 0x1180C000 }, + { 0x9888, 0x1780C000 }, + { 0x9888, 0x1980C000 }, + { 0x9888, 0x1B80C000 }, + { 0x9888, 0x1D80C000 }, + { 0x9888, 0x1F80C000 }, + { 0x9888, 0x1380C000 }, + { 0x9888, 0x1580C000 }, + { 0x0D24, 0x00000000 }, + { 0x9888, 0x4D801111 }, + { 0x9888, 0x3D800800 }, + { 0x9888, 0x4F801011 }, + { 0x9888, 0x43800443 }, + { 0x9888, 0x51801111 }, + { 0x9888, 0x45800422 }, + { 0x9888, 0x53801111 }, + { 0x9888, 0x47800C60 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x3F800422 }, + { 0x9888, 0x41800021 }, +}; + +static int select_render_pipe_profile_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_render_pipe_profile; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_render_pipe_profile); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_render_pipe_profile; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_render_pipe_profile); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_render_pipe_profile; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_render_pipe_profile); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_memory_reads[] = { + { 0x2724, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2710, 0x00000000 }, + { 0x274c, 0x86543210 }, + { 0x2748, 0x86543210 }, + { 0x2744, 0x00006667 }, + { 0x2740, 0x00000000 }, + { 0x275c, 0x86543210 }, + { 0x2758, 0x86543210 }, + { 0x2754, 0x00006465 }, + { 0x2750, 0x00000000 }, + { 0x2770, 0x0007f81a }, + { 0x2774, 0x0000fe00 }, + { 0x2778, 0x0007f82a }, + { 0x277c, 0x0000fe00 }, + { 0x2780, 0x0007f872 }, + { 0x2784, 0x0000fe00 }, + { 0x2788, 0x0007f8ba }, + { 0x278c, 0x0000fe00 }, + { 0x2790, 0x0007f87a }, + { 0x2794, 0x0000fe00 }, + { 0x2798, 0x0007f8ea }, + { 0x279c, 0x0000fe00 }, + { 0x27a0, 0x0007f8e2 }, + { 0x27a4, 0x0000fe00 }, + { 0x27a8, 0x0007f8f2 }, + { 0x27ac, 0x0000fe00 }, +}; + +static const struct i915_oa_reg flex_eu_config_memory_reads[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00015014 }, + { 0xE658, 0x00025024 }, + { 0xE758, 0x00035034 }, + { 0xE45c, 0x00045044 }, + { 0xE55c, 0x00055054 }, + { 0xE65c, 0x00065064 }, +}; + +static const struct i915_oa_reg mux_config_memory_reads[] = { + { 0x9888, 0x198B0343 }, + { 0x9888, 0x13845800 }, + { 0x9888, 0x15840018 }, + { 0x9888, 0x3580001A }, + { 0x9888, 0x038B6300 }, + { 0x9888, 0x058B6B62 }, + { 0x9888, 0x078B006A }, + { 0x9888, 0x118B0000 }, + { 0x9888, 0x238B0000 }, + { 0x9888, 0x258B0000 }, + { 0x9888, 0x1F85A080 }, + { 0x9888, 0x2185AAAA }, + { 0x9888, 0x2385000A }, + { 0x9888, 0x07834000 }, + { 0x9888, 0x09834000 }, + { 0x9888, 0x0B834000 }, + { 0x9888, 0x0D834000 }, + { 0x9888, 0x01840018 }, + { 0x9888, 0x07844C80 }, + { 0x9888, 0x09840D9A }, + { 0x9888, 0x0B840E9C }, + { 0x9888, 0x0D840F9E }, + { 0x9888, 0x0F840010 }, + { 0x9888, 0x11840000 }, + { 0x9888, 0x03848000 }, + { 0x9888, 0x0584C000 }, + { 0x9888, 0x2F8000E5 }, + { 0x9888, 0x138080E3 }, + { 0x9888, 0x1580C0E1 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x11804000 }, + { 0x9888, 0x1780C000 }, + { 0x9888, 0x1980C000 }, + { 0x9888, 0x1B80C000 }, + { 0x9888, 0x1D80C000 }, + { 0x9888, 0x1F804000 }, + { 0x0D24, 0x00000000 }, + { 0x9888, 0x4D800000 }, + { 0x9888, 0x3D800800 }, + { 0x9888, 0x4F800000 }, + { 0x9888, 0x43800842 }, + { 0x9888, 0x51800000 }, + { 0x9888, 0x45800842 }, + { 0x9888, 0x53800000 }, + { 0x9888, 0x47801042 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x3F800084 }, + { 0x9888, 0x41800000 }, +}; + +static int select_memory_reads_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_memory_reads; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_memory_reads); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_memory_reads; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_memory_reads); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_memory_reads; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_memory_reads); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_memory_writes[] = { + { 0x2724, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2710, 0x00000000 }, + { 0x274c, 0x86543210 }, + { 0x2748, 0x86543210 }, + { 0x2744, 0x00006667 }, + { 0x2740, 0x00000000 }, + { 0x275c, 0x86543210 }, + { 0x2758, 0x86543210 }, + { 0x2754, 0x00006465 }, + { 0x2750, 0x00000000 }, + { 0x2770, 0x0007f81a }, + { 0x2774, 0x0000fe00 }, + { 0x2778, 0x0007f82a }, + { 0x277c, 0x0000fe00 }, + { 0x2780, 0x0007f822 }, + { 0x2784, 0x0000fe00 }, + { 0x2788, 0x0007f8ba }, + { 0x278c, 0x0000fe00 }, + { 0x2790, 0x0007f87a }, + { 0x2794, 0x0000fe00 }, + { 0x2798, 0x0007f8ea }, + { 0x279c, 0x0000fe00 }, + { 0x27a0, 0x0007f8e2 }, + { 0x27a4, 0x0000fe00 }, + { 0x27a8, 0x0007f8f2 }, + { 0x27ac, 0x0000fe00 }, +}; + +static const struct i915_oa_reg flex_eu_config_memory_writes[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00015014 }, + { 0xE658, 0x00025024 }, + { 0xE758, 0x00035034 }, + { 0xE45c, 0x00045044 }, + { 0xE55c, 0x00055054 }, + { 0xE65c, 0x00065064 }, +}; + +static const struct i915_oa_reg mux_config_memory_writes[] = { + { 0x9888, 0x198B0343 }, + { 0x9888, 0x13845400 }, + { 0x9888, 0x3580001A }, + { 0x9888, 0x3D800805 }, + { 0x9888, 0x038B6300 }, + { 0x9888, 0x058B6B62 }, + { 0x9888, 0x078B006A }, + { 0x9888, 0x118B0000 }, + { 0x9888, 0x238B0000 }, + { 0x9888, 0x258B0000 }, + { 0x9888, 0x1F85A080 }, + { 0x9888, 0x2185AAAA }, + { 0x9888, 0x23850002 }, + { 0x9888, 0x07834000 }, + { 0x9888, 0x09834000 }, + { 0x9888, 0x0B834000 }, + { 0x9888, 0x0D834000 }, + { 0x9888, 0x01840010 }, + { 0x9888, 0x07844880 }, + { 0x9888, 0x09840992 }, + { 0x9888, 0x0B840A94 }, + { 0x9888, 0x0D840B96 }, + { 0x9888, 0x11840000 }, + { 0x9888, 0x03848000 }, + { 0x9888, 0x0584C000 }, + { 0x9888, 0x2D800147 }, + { 0x9888, 0x2F8000E5 }, + { 0x9888, 0x138080E3 }, + { 0x9888, 0x1580C0E1 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x11804000 }, + { 0x9888, 0x1780C000 }, + { 0x9888, 0x1980C000 }, + { 0x9888, 0x1B80C000 }, + { 0x9888, 0x1D80C000 }, + { 0x9888, 0x1F800000 }, + { 0x0D24, 0x00000000 }, + { 0x9888, 0x4D800000 }, + { 0x9888, 0x4F800000 }, + { 0x9888, 0x43800842 }, + { 0x9888, 0x51800000 }, + { 0x9888, 0x45800842 }, + { 0x9888, 0x53800000 }, + { 0x9888, 0x47801082 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x3F800084 }, + { 0x9888, 0x41800000 }, +}; + +static int select_memory_writes_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_memory_writes; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_memory_writes); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_memory_writes; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_memory_writes); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_memory_writes; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_memory_writes); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_compute_extended[] = { + { 0x2724, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2710, 0x00000000 }, + { 0x2770, 0x0007fc2a }, + { 0x2774, 0x0000bf00 }, + { 0x2778, 0x0007fc6a }, + { 0x277c, 0x0000bf00 }, + { 0x2780, 0x0007fc92 }, + { 0x2784, 0x0000bf00 }, + { 0x2788, 0x0007fca2 }, + { 0x278c, 0x0000bf00 }, + { 0x2790, 0x0007fc32 }, + { 0x2794, 0x0000bf00 }, + { 0x2798, 0x0007fc9a }, + { 0x279c, 0x0000bf00 }, + { 0x27a0, 0x0007fe6a }, + { 0x27a4, 0x0000bf00 }, + { 0x27a8, 0x0007fe7a }, + { 0x27ac, 0x0000bf00 }, +}; + +static const struct i915_oa_reg flex_eu_config_compute_extended[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00000003 }, + { 0xE658, 0x00002001 }, + { 0xE758, 0x00778008 }, + { 0xE45c, 0x00088078 }, + { 0xE55c, 0x00808708 }, + { 0xE65c, 0x00a08908 }, +}; + +static const struct i915_oa_reg mux_config_compute_extended_1_0_subslices_0x01[] = { + { 0x9888, 0x143D0160 }, + { 0x9888, 0x163D2800 }, + { 0x9888, 0x183D0120 }, + { 0x9888, 0x105800E0 }, + { 0x9888, 0x005CC000 }, + { 0x9888, 0x065C8000 }, + { 0x9888, 0x085CC000 }, + { 0x9888, 0x0A5CC000 }, + { 0x9888, 0x0C5CC000 }, + { 0x9888, 0x0E5CC000 }, + { 0x9888, 0x025CC000 }, + { 0x9888, 0x045CC000 }, + { 0x9888, 0x003D0011 }, + { 0x9888, 0x063D0900 }, + { 0x9888, 0x083D0A13 }, + { 0x9888, 0x0A3D0B15 }, + { 0x9888, 0x0C3D2317 }, + { 0x9888, 0x043D21B7 }, + { 0x9888, 0x103D0000 }, + { 0x9888, 0x0E3D0000 }, + { 0x9888, 0x1A3D0000 }, + { 0x9888, 0x0E5825C1 }, + { 0x9888, 0x00586100 }, + { 0x9888, 0x0258204C }, + { 0x9888, 0x06588000 }, + { 0x9888, 0x0858C000 }, + { 0x9888, 0x0A58C000 }, + { 0x9888, 0x0C58C000 }, + { 0x9888, 0x0458C000 }, + { 0x9888, 0x005B4000 }, + { 0x9888, 0x0E5B4000 }, + { 0x9888, 0x185B5400 }, + { 0x9888, 0x1A5B0155 }, + { 0x9888, 0x025B4000 }, + { 0x9888, 0x045B4000 }, + { 0x9888, 0x065B4000 }, + { 0x9888, 0x085B4000 }, + { 0x9888, 0x0A5B4000 }, + { 0x9888, 0x0C1FA800 }, + { 0x9888, 0x0E1FAA2A }, + { 0x9888, 0x101F02AA }, + { 0x9888, 0x00384000 }, + { 0x9888, 0x0E384000 }, + { 0x9888, 0x16384000 }, + { 0x9888, 0x18381555 }, + { 0x9888, 0x02384000 }, + { 0x9888, 0x04384000 }, + { 0x9888, 0x06384000 }, + { 0x9888, 0x08384000 }, + { 0x9888, 0x0A384000 }, + { 0x9888, 0x0039A000 }, + { 0x9888, 0x06398000 }, + { 0x9888, 0x0839A000 }, + { 0x9888, 0x0A39A000 }, + { 0x9888, 0x0C39A000 }, + { 0x9888, 0x0E39A000 }, + { 0x9888, 0x0239A000 }, + { 0x9888, 0x0439A000 }, + { 0x9888, 0x018A8000 }, + { 0x9888, 0x0F8A8000 }, + { 0x9888, 0x198A8000 }, + { 0x9888, 0x1B8AAAA0 }, + { 0x9888, 0x1D8A0002 }, + { 0x9888, 0x038A8000 }, + { 0x9888, 0x058A8000 }, + { 0x9888, 0x078A8000 }, + { 0x9888, 0x098A8000 }, + { 0x9888, 0x0B8A8000 }, + { 0x9888, 0x238B2AA0 }, + { 0x9888, 0x258B5551 }, + { 0x9888, 0x278B0015 }, +}; + +static const struct i915_oa_reg mux_config_compute_extended_1_1_subslices_0x08[] = { + { 0x9888, 0x14BD0160 }, + { 0x9888, 0x16BD2800 }, + { 0x9888, 0x18BD0120 }, + { 0x9888, 0x10D800E0 }, + { 0x9888, 0x00DCC000 }, + { 0x9888, 0x06DC8000 }, + { 0x9888, 0x08DCC000 }, + { 0x9888, 0x0ADCC000 }, + { 0x9888, 0x0CDCC000 }, + { 0x9888, 0x0EDCC000 }, + { 0x9888, 0x02DCC000 }, + { 0x9888, 0x04DCC000 }, + { 0x9888, 0x00BD0011 }, + { 0x9888, 0x06BD0900 }, + { 0x9888, 0x08BD0A13 }, + { 0x9888, 0x0ABD0B15 }, + { 0x9888, 0x0CBD2317 }, + { 0x9888, 0x04BD21B7 }, + { 0x9888, 0x10BD0000 }, + { 0x9888, 0x0EBD0000 }, + { 0x9888, 0x1ABD0000 }, + { 0x9888, 0x0ED825C1 }, + { 0x9888, 0x00D86100 }, + { 0x9888, 0x02D8204C }, + { 0x9888, 0x06D88000 }, + { 0x9888, 0x08D8C000 }, + { 0x9888, 0x0AD8C000 }, + { 0x9888, 0x0CD8C000 }, + { 0x9888, 0x04D8C000 }, + { 0x9888, 0x00DB4000 }, + { 0x9888, 0x0EDB4000 }, + { 0x9888, 0x18DB5400 }, + { 0x9888, 0x1ADB0155 }, + { 0x9888, 0x02DB4000 }, + { 0x9888, 0x04DB4000 }, + { 0x9888, 0x06DB4000 }, + { 0x9888, 0x08DB4000 }, + { 0x9888, 0x0ADB4000 }, + { 0x9888, 0x0C9FA800 }, + { 0x9888, 0x0E9FAA2A }, + { 0x9888, 0x109F02AA }, + { 0x9888, 0x00B84000 }, + { 0x9888, 0x0EB84000 }, + { 0x9888, 0x16B84000 }, + { 0x9888, 0x18B81555 }, + { 0x9888, 0x02B84000 }, + { 0x9888, 0x04B84000 }, + { 0x9888, 0x06B84000 }, + { 0x9888, 0x08B84000 }, + { 0x9888, 0x0AB84000 }, + { 0x9888, 0x00B9A000 }, + { 0x9888, 0x06B98000 }, + { 0x9888, 0x08B9A000 }, + { 0x9888, 0x0AB9A000 }, + { 0x9888, 0x0CB9A000 }, + { 0x9888, 0x0EB9A000 }, + { 0x9888, 0x02B9A000 }, + { 0x9888, 0x04B9A000 }, + { 0x9888, 0x01888000 }, + { 0x9888, 0x0D88F800 }, + { 0x9888, 0x0F88000F }, + { 0x9888, 0x03888000 }, + { 0x9888, 0x05888000 }, + { 0x9888, 0x07888000 }, + { 0x9888, 0x09888000 }, + { 0x9888, 0x0B888000 }, + { 0x9888, 0x238B5540 }, + { 0x9888, 0x258BAAA2 }, + { 0x9888, 0x278B002A }, + { 0x9888, 0x018C4000 }, + { 0x9888, 0x0F8C4000 }, + { 0x9888, 0x178C2000 }, + { 0x9888, 0x198C5500 }, + { 0x9888, 0x1B8C0015 }, + { 0x9888, 0x038C4000 }, + { 0x9888, 0x058C4000 }, + { 0x9888, 0x078C4000 }, + { 0x9888, 0x098C4000 }, + { 0x9888, 0x0B8C4000 }, + { 0x9888, 0x018DA000 }, + { 0x9888, 0x078D8000 }, + { 0x9888, 0x098DA000 }, + { 0x9888, 0x0B8DA000 }, + { 0x9888, 0x0D8DA000 }, + { 0x9888, 0x0F8DA000 }, + { 0x9888, 0x038DA000 }, + { 0x9888, 0x058DA000 }, +}; + +static const struct i915_oa_reg mux_config_compute_extended_1_2_subslices_0x02[] = { + { 0x9888, 0x105C00E0 }, + { 0x9888, 0x145B0160 }, + { 0x9888, 0x165B2800 }, + { 0x9888, 0x185B0120 }, + { 0x9888, 0x0E5C25C1 }, + { 0x9888, 0x005C6100 }, + { 0x9888, 0x025C204C }, + { 0x9888, 0x065C8000 }, + { 0x9888, 0x085CC000 }, + { 0x9888, 0x0A5CC000 }, + { 0x9888, 0x0C5CC000 }, + { 0x9888, 0x045CC000 }, + { 0x9888, 0x005B0011 }, + { 0x9888, 0x065B0900 }, + { 0x9888, 0x085B0A13 }, + { 0x9888, 0x0A5B0B15 }, + { 0x9888, 0x0C5B2317 }, + { 0x9888, 0x045B21B7 }, + { 0x9888, 0x105B0000 }, + { 0x9888, 0x0E5B0000 }, + { 0x9888, 0x1A5B0000 }, + { 0x9888, 0x0C1FA800 }, + { 0x9888, 0x0E1FAA2A }, + { 0x9888, 0x101F02AA }, + { 0x9888, 0x00384000 }, + { 0x9888, 0x0E384000 }, + { 0x9888, 0x16384000 }, + { 0x9888, 0x18381555 }, + { 0x9888, 0x02384000 }, + { 0x9888, 0x04384000 }, + { 0x9888, 0x06384000 }, + { 0x9888, 0x08384000 }, + { 0x9888, 0x0A384000 }, + { 0x9888, 0x0039A000 }, + { 0x9888, 0x06398000 }, + { 0x9888, 0x0839A000 }, + { 0x9888, 0x0A39A000 }, + { 0x9888, 0x0C39A000 }, + { 0x9888, 0x0E39A000 }, + { 0x9888, 0x0239A000 }, + { 0x9888, 0x0439A000 }, + { 0x9888, 0x018A8000 }, + { 0x9888, 0x0F8A8000 }, + { 0x9888, 0x198A8000 }, + { 0x9888, 0x1B8AAAA0 }, + { 0x9888, 0x1D8A0002 }, + { 0x9888, 0x038A8000 }, + { 0x9888, 0x058A8000 }, + { 0x9888, 0x078A8000 }, + { 0x9888, 0x098A8000 }, + { 0x9888, 0x0B8A8000 }, + { 0x9888, 0x238B2AA0 }, + { 0x9888, 0x258B5551 }, + { 0x9888, 0x278B0015 }, +}; + +static const struct i915_oa_reg mux_config_compute_extended_1_3_subslices_0x10[] = { + { 0x9888, 0x10DC00E0 }, + { 0x9888, 0x14DB0160 }, + { 0x9888, 0x16DB2800 }, + { 0x9888, 0x18DB0120 }, + { 0x9888, 0x0EDC25C1 }, + { 0x9888, 0x00DC6100 }, + { 0x9888, 0x02DC204C }, + { 0x9888, 0x06DC8000 }, + { 0x9888, 0x08DCC000 }, + { 0x9888, 0x0ADCC000 }, + { 0x9888, 0x0CDCC000 }, + { 0x9888, 0x04DCC000 }, + { 0x9888, 0x00DB0011 }, + { 0x9888, 0x06DB0900 }, + { 0x9888, 0x08DB0A13 }, + { 0x9888, 0x0ADB0B15 }, + { 0x9888, 0x0CDB2317 }, + { 0x9888, 0x04DB21B7 }, + { 0x9888, 0x10DB0000 }, + { 0x9888, 0x0EDB0000 }, + { 0x9888, 0x1ADB0000 }, + { 0x9888, 0x0C9FA800 }, + { 0x9888, 0x0E9FAA2A }, + { 0x9888, 0x109F02AA }, + { 0x9888, 0x00B84000 }, + { 0x9888, 0x0EB84000 }, + { 0x9888, 0x16B84000 }, + { 0x9888, 0x18B81555 }, + { 0x9888, 0x02B84000 }, + { 0x9888, 0x04B84000 }, + { 0x9888, 0x06B84000 }, + { 0x9888, 0x08B84000 }, + { 0x9888, 0x0AB84000 }, + { 0x9888, 0x00B9A000 }, + { 0x9888, 0x06B98000 }, + { 0x9888, 0x08B9A000 }, + { 0x9888, 0x0AB9A000 }, + { 0x9888, 0x0CB9A000 }, + { 0x9888, 0x0EB9A000 }, + { 0x9888, 0x02B9A000 }, + { 0x9888, 0x04B9A000 }, + { 0x9888, 0x01888000 }, + { 0x9888, 0x0D88F800 }, + { 0x9888, 0x0F88000F }, + { 0x9888, 0x03888000 }, + { 0x9888, 0x05888000 }, + { 0x9888, 0x07888000 }, + { 0x9888, 0x09888000 }, + { 0x9888, 0x0B888000 }, + { 0x9888, 0x238B5540 }, + { 0x9888, 0x258BAAA2 }, + { 0x9888, 0x278B002A }, + { 0x9888, 0x018C4000 }, + { 0x9888, 0x0F8C4000 }, + { 0x9888, 0x178C2000 }, + { 0x9888, 0x198C5500 }, + { 0x9888, 0x1B8C0015 }, + { 0x9888, 0x038C4000 }, + { 0x9888, 0x058C4000 }, + { 0x9888, 0x078C4000 }, + { 0x9888, 0x098C4000 }, + { 0x9888, 0x0B8C4000 }, + { 0x9888, 0x018DA000 }, + { 0x9888, 0x078D8000 }, + { 0x9888, 0x098DA000 }, + { 0x9888, 0x0B8DA000 }, + { 0x9888, 0x0D8DA000 }, + { 0x9888, 0x0F8DA000 }, + { 0x9888, 0x038DA000 }, + { 0x9888, 0x058DA000 }, +}; + +static const struct i915_oa_reg mux_config_compute_extended_1_4_subslices_0x04[] = { + { 0x9888, 0x103800E0 }, + { 0x9888, 0x143A0160 }, + { 0x9888, 0x163A2800 }, + { 0x9888, 0x183A0120 }, + { 0x9888, 0x0C1FA800 }, + { 0x9888, 0x0E1FAA2A }, + { 0x9888, 0x101F02AA }, + { 0x9888, 0x0E38A5C1 }, + { 0x9888, 0x0038A100 }, + { 0x9888, 0x0238204C }, + { 0x9888, 0x16388000 }, + { 0x9888, 0x183802AA }, + { 0x9888, 0x04380000 }, + { 0x9888, 0x06380000 }, + { 0x9888, 0x08388000 }, + { 0x9888, 0x0A388000 }, + { 0x9888, 0x0039A000 }, + { 0x9888, 0x06398000 }, + { 0x9888, 0x0839A000 }, + { 0x9888, 0x0A39A000 }, + { 0x9888, 0x0C39A000 }, + { 0x9888, 0x0E39A000 }, + { 0x9888, 0x0239A000 }, + { 0x9888, 0x0439A000 }, + { 0x9888, 0x003A0011 }, + { 0x9888, 0x063A0900 }, + { 0x9888, 0x083A0A13 }, + { 0x9888, 0x0A3A0B15 }, + { 0x9888, 0x0C3A2317 }, + { 0x9888, 0x043A21B7 }, + { 0x9888, 0x103A0000 }, + { 0x9888, 0x0E3A0000 }, + { 0x9888, 0x1A3A0000 }, + { 0x9888, 0x018A8000 }, + { 0x9888, 0x0F8A8000 }, + { 0x9888, 0x198A8000 }, + { 0x9888, 0x1B8AAAA0 }, + { 0x9888, 0x1D8A0002 }, + { 0x9888, 0x038A8000 }, + { 0x9888, 0x058A8000 }, + { 0x9888, 0x078A8000 }, + { 0x9888, 0x098A8000 }, + { 0x9888, 0x0B8A8000 }, + { 0x9888, 0x238B2AA0 }, + { 0x9888, 0x258B5551 }, + { 0x9888, 0x278B0015 }, +}; + +static const struct i915_oa_reg mux_config_compute_extended_1_5_subslices_0x20[] = { + { 0x9888, 0x10B800E0 }, + { 0x9888, 0x14BA0160 }, + { 0x9888, 0x16BA2800 }, + { 0x9888, 0x18BA0120 }, + { 0x9888, 0x0C9FA800 }, + { 0x9888, 0x0E9FAA2A }, + { 0x9888, 0x109F02AA }, + { 0x9888, 0x0EB8A5C1 }, + { 0x9888, 0x00B8A100 }, + { 0x9888, 0x02B8204C }, + { 0x9888, 0x16B88000 }, + { 0x9888, 0x18B802AA }, + { 0x9888, 0x04B80000 }, + { 0x9888, 0x06B80000 }, + { 0x9888, 0x08B88000 }, + { 0x9888, 0x0AB88000 }, + { 0x9888, 0x00B9A000 }, + { 0x9888, 0x06B98000 }, + { 0x9888, 0x08B9A000 }, + { 0x9888, 0x0AB9A000 }, + { 0x9888, 0x0CB9A000 }, + { 0x9888, 0x0EB9A000 }, + { 0x9888, 0x02B9A000 }, + { 0x9888, 0x04B9A000 }, + { 0x9888, 0x00BA0011 }, + { 0x9888, 0x06BA0900 }, + { 0x9888, 0x08BA0A13 }, + { 0x9888, 0x0ABA0B15 }, + { 0x9888, 0x0CBA2317 }, + { 0x9888, 0x04BA21B7 }, + { 0x9888, 0x10BA0000 }, + { 0x9888, 0x0EBA0000 }, + { 0x9888, 0x1ABA0000 }, + { 0x9888, 0x01888000 }, + { 0x9888, 0x0D88F800 }, + { 0x9888, 0x0F88000F }, + { 0x9888, 0x03888000 }, + { 0x9888, 0x05888000 }, + { 0x9888, 0x07888000 }, + { 0x9888, 0x09888000 }, + { 0x9888, 0x0B888000 }, + { 0x9888, 0x238B5540 }, + { 0x9888, 0x258BAAA2 }, + { 0x9888, 0x278B002A }, + { 0x9888, 0x018C4000 }, + { 0x9888, 0x0F8C4000 }, + { 0x9888, 0x178C2000 }, + { 0x9888, 0x198C5500 }, + { 0x9888, 0x1B8C0015 }, + { 0x9888, 0x038C4000 }, + { 0x9888, 0x058C4000 }, + { 0x9888, 0x078C4000 }, + { 0x9888, 0x098C4000 }, + { 0x9888, 0x0B8C4000 }, + { 0x9888, 0x018DA000 }, + { 0x9888, 0x078D8000 }, + { 0x9888, 0x098DA000 }, + { 0x9888, 0x0B8DA000 }, + { 0x9888, 0x0D8DA000 }, + { 0x9888, 0x0F8DA000 }, + { 0x9888, 0x038DA000 }, + { 0x9888, 0x058DA000 }, +}; + +static const struct i915_oa_reg mux_config_compute_extended[] = { + { 0x9888, 0x1F85AA80 }, + { 0x9888, 0x2185AAA2 }, + { 0x9888, 0x2385002A }, + { 0x9888, 0x01834000 }, + { 0x9888, 0x0F834000 }, + { 0x9888, 0x19835400 }, + { 0x9888, 0x1B830155 }, + { 0x9888, 0x03834000 }, + { 0x9888, 0x05834000 }, + { 0x9888, 0x07834000 }, + { 0x9888, 0x09834000 }, + { 0x9888, 0x0B834000 }, + { 0x9888, 0x0184C000 }, + { 0x9888, 0x07848000 }, + { 0x9888, 0x0984C000 }, + { 0x9888, 0x0B84C000 }, + { 0x9888, 0x0D84C000 }, + { 0x9888, 0x0F84C000 }, + { 0x9888, 0x0384C000 }, + { 0x9888, 0x0584C000 }, + { 0x9888, 0x1180C000 }, + { 0x9888, 0x17808000 }, + { 0x9888, 0x1980C000 }, + { 0x9888, 0x1B80C000 }, + { 0x9888, 0x1D80C000 }, + { 0x9888, 0x1F80C000 }, + { 0x9888, 0x1380C000 }, + { 0x9888, 0x1580C000 }, + { 0x0D24, 0x00000000 }, + { 0x9888, 0x4D800000 }, + { 0x9888, 0x3D800000 }, + { 0x9888, 0x4F800000 }, + { 0x9888, 0x43800000 }, + { 0x9888, 0x51800000 }, + { 0x9888, 0x45800000 }, + { 0x9888, 0x53800000 }, + { 0x9888, 0x47800420 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x3F800421 }, + { 0x9888, 0x41800000 }, +}; + +static int select_compute_extended_config(struct drm_i915_private *dev_priv) +{ + if (INTEL_INFO(dev_priv)->subslice_mask & 0x01) { + dev_priv->perf.oa.mux_regs = + mux_config_compute_extended_1_0_subslices_0x01; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_compute_extended_1_0_subslices_0x01); + } else if (INTEL_INFO(dev_priv)->subslice_mask & 0x08) { + dev_priv->perf.oa.mux_regs = + mux_config_compute_extended_1_1_subslices_0x08; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_compute_extended_1_1_subslices_0x08); + } else if (INTEL_INFO(dev_priv)->subslice_mask & 0x02) { + dev_priv->perf.oa.mux_regs = + mux_config_compute_extended_1_2_subslices_0x02; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_compute_extended_1_2_subslices_0x02); + } else if (INTEL_INFO(dev_priv)->subslice_mask & 0x10) { + dev_priv->perf.oa.mux_regs = + mux_config_compute_extended_1_3_subslices_0x10; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_compute_extended_1_3_subslices_0x10); + } else if (INTEL_INFO(dev_priv)->subslice_mask & 0x04) { + dev_priv->perf.oa.mux_regs = + mux_config_compute_extended_1_4_subslices_0x04; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_compute_extended_1_4_subslices_0x04); + } else if (INTEL_INFO(dev_priv)->subslice_mask & 0x20) { + dev_priv->perf.oa.mux_regs = + mux_config_compute_extended_1_5_subslices_0x20; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_compute_extended_1_5_subslices_0x20); + dev_priv->perf.oa.mux_regs = + mux_config_compute_extended; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_compute_extended); + } else { + DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set"); + return -EINVAL; + } + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_compute_extended; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_compute_extended); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_compute_extended; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_compute_extended); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = { + { 0x2710, 0x00000000 }, + { 0x2714, 0x30800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x30800000 }, + { 0x2770, 0x0007fffa }, + { 0x2774, 0x0000fefe }, + { 0x2778, 0x0007fffa }, + { 0x277c, 0x0000fefd }, + { 0x2790, 0x0007fffa }, + { 0x2794, 0x0000fbef }, + { 0x2798, 0x0007fffa }, + { 0x279c, 0x0000fbdf }, +}; + +static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00000003 }, + { 0xE658, 0x00002001 }, + { 0xE758, 0x00101100 }, + { 0xE45c, 0x00201200 }, + { 0xE55c, 0x00301300 }, + { 0xE65c, 0x00401400 }, +}; + +static const struct i915_oa_reg mux_config_compute_l3_cache[] = { + { 0x9888, 0x143F00B3 }, + { 0x9888, 0x14BF00B3 }, + { 0x9888, 0x138303C0 }, + { 0x9888, 0x3B800060 }, + { 0x9888, 0x3D800805 }, + { 0x9888, 0x003F0029 }, + { 0x9888, 0x063F1400 }, + { 0x9888, 0x083F1225 }, + { 0x9888, 0x0E3F1327 }, + { 0x9888, 0x103F0000 }, + { 0x9888, 0x005A4000 }, + { 0x9888, 0x065A8000 }, + { 0x9888, 0x085AC000 }, + { 0x9888, 0x0E5AC000 }, + { 0x9888, 0x001D4000 }, + { 0x9888, 0x061D8000 }, + { 0x9888, 0x081DC000 }, + { 0x9888, 0x0E1DC000 }, + { 0x9888, 0x0C1F0800 }, + { 0x9888, 0x0E1F2A00 }, + { 0x9888, 0x101F0280 }, + { 0x9888, 0x00391000 }, + { 0x9888, 0x06394000 }, + { 0x9888, 0x08395000 }, + { 0x9888, 0x0E395000 }, + { 0x9888, 0x0ABF1429 }, + { 0x9888, 0x0CBF1225 }, + { 0x9888, 0x00BF1380 }, + { 0x9888, 0x02BF0026 }, + { 0x9888, 0x10BF0000 }, + { 0x9888, 0x0ADAC000 }, + { 0x9888, 0x0CDAC000 }, + { 0x9888, 0x00DA8000 }, + { 0x9888, 0x02DA4000 }, + { 0x9888, 0x0A9DC000 }, + { 0x9888, 0x0C9DC000 }, + { 0x9888, 0x009D8000 }, + { 0x9888, 0x029D4000 }, + { 0x9888, 0x0E9F8000 }, + { 0x9888, 0x109F002A }, + { 0x9888, 0x0C9FA000 }, + { 0x9888, 0x0AB95000 }, + { 0x9888, 0x0CB95000 }, + { 0x9888, 0x00B94000 }, + { 0x9888, 0x02B91000 }, + { 0x9888, 0x0D88C000 }, + { 0x9888, 0x0F880003 }, + { 0x9888, 0x03888000 }, + { 0x9888, 0x05888000 }, + { 0x9888, 0x018A8000 }, + { 0x9888, 0x0F8A8000 }, + { 0x9888, 0x198A8000 }, + { 0x9888, 0x1B8A8020 }, + { 0x9888, 0x1D8A0002 }, + { 0x9888, 0x238B0520 }, + { 0x9888, 0x258BA950 }, + { 0x9888, 0x278B0016 }, + { 0x9888, 0x198C5400 }, + { 0x9888, 0x1B8C0001 }, + { 0x9888, 0x038C4000 }, + { 0x9888, 0x058C4000 }, + { 0x9888, 0x0B8DA000 }, + { 0x9888, 0x0D8DA000 }, + { 0x9888, 0x018D8000 }, + { 0x9888, 0x038D2000 }, + { 0x9888, 0x1F85AA80 }, + { 0x9888, 0x2185AAA0 }, + { 0x9888, 0x2385002A }, + { 0x9888, 0x03835180 }, + { 0x9888, 0x05834022 }, + { 0x9888, 0x11830000 }, + { 0x9888, 0x01834000 }, + { 0x9888, 0x0F834000 }, + { 0x9888, 0x19835400 }, + { 0x9888, 0x1B830155 }, + { 0x9888, 0x07830000 }, + { 0x9888, 0x09830000 }, + { 0x9888, 0x0184C000 }, + { 0x9888, 0x07848000 }, + { 0x9888, 0x0984C000 }, + { 0x9888, 0x0B84C000 }, + { 0x9888, 0x0D84C000 }, + { 0x9888, 0x0F84C000 }, + { 0x9888, 0x0384C000 }, + { 0x9888, 0x05844000 }, + { 0x9888, 0x1B80C137 }, + { 0x9888, 0x1D80C147 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x1180C000 }, + { 0x9888, 0x17808000 }, + { 0x9888, 0x1980C000 }, + { 0x9888, 0x1F80C000 }, + { 0x9888, 0x1380C000 }, + { 0x9888, 0x15804000 }, + { 0x0D24, 0x00000000 }, + { 0x9888, 0x4D801000 }, + { 0x9888, 0x4F800111 }, + { 0x9888, 0x43800842 }, + { 0x9888, 0x51800000 }, + { 0x9888, 0x45800000 }, + { 0x9888, 0x53800000 }, + { 0x9888, 0x47800840 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x3F800800 }, + { 0x9888, 0x418014A2 }, +}; + +static int select_compute_l3_cache_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_compute_l3_cache; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_compute_l3_cache); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_compute_l3_cache; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_compute_l3_cache); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_compute_l3_cache; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_compute_l3_cache); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_data_port_reads_coalescing[] = { + { 0x2724, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2710, 0x00000000 }, + { 0x274c, 0xba98ba98 }, + { 0x2748, 0xba98ba98 }, + { 0x2744, 0x00003377 }, + { 0x2740, 0x00000000 }, + { 0x2770, 0x0007fff2 }, + { 0x2774, 0x00007ff0 }, + { 0x2778, 0x0007ffe2 }, + { 0x277c, 0x00007ff0 }, + { 0x2780, 0x0007ffc2 }, + { 0x2784, 0x00007ff0 }, + { 0x2788, 0x0007ff82 }, + { 0x278c, 0x00007ff0 }, + { 0x2790, 0x0007fffa }, + { 0x2794, 0x0000bfef }, + { 0x2798, 0x0007fffa }, + { 0x279c, 0x0000bfdf }, + { 0x27a0, 0x0007fffa }, + { 0x27a4, 0x0000bfbf }, + { 0x27a8, 0x0007fffa }, + { 0x27ac, 0x0000bf7f }, +}; + +static const struct i915_oa_reg flex_eu_config_data_port_reads_coalescing[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00000003 }, + { 0xE658, 0x00002001 }, + { 0xE758, 0x00778008 }, + { 0xE45c, 0x00088078 }, + { 0xE55c, 0x00808708 }, + { 0xE65c, 0x00a08908 }, +}; + +static const struct i915_oa_reg mux_config_data_port_reads_coalescing_1_0_subslices_0x01[] = { + { 0x9888, 0x103D0005 }, + { 0x9888, 0x163D240B }, + { 0x9888, 0x1058022F }, + { 0x9888, 0x185B5520 }, + { 0x9888, 0x198B0003 }, + { 0x9888, 0x005CC000 }, + { 0x9888, 0x065CC000 }, + { 0x9888, 0x085CC000 }, + { 0x9888, 0x0A5CC000 }, + { 0x9888, 0x0C5CC000 }, + { 0x9888, 0x0E5CC000 }, + { 0x9888, 0x025C4000 }, + { 0x9888, 0x045C8000 }, + { 0x9888, 0x003D0000 }, + { 0x9888, 0x063D00B0 }, + { 0x9888, 0x083D0182 }, + { 0x9888, 0x0A3D10A0 }, + { 0x9888, 0x0C3D11A2 }, + { 0x9888, 0x0E3D0000 }, + { 0x9888, 0x183D0000 }, + { 0x9888, 0x1A3D0000 }, + { 0x9888, 0x0E582242 }, + { 0x9888, 0x00586700 }, + { 0x9888, 0x0258004F }, + { 0x9888, 0x0658C000 }, + { 0x9888, 0x0858C000 }, + { 0x9888, 0x0A58C000 }, + { 0x9888, 0x0C58C000 }, + { 0x9888, 0x045B6300 }, + { 0x9888, 0x105B0000 }, + { 0x9888, 0x005B4000 }, + { 0x9888, 0x0E5B4000 }, + { 0x9888, 0x1A5B0155 }, + { 0x9888, 0x025B4000 }, + { 0x9888, 0x0A5B0000 }, + { 0x9888, 0x0C5B4000 }, + { 0x9888, 0x0C1FA800 }, + { 0x9888, 0x0E1FAAA0 }, + { 0x9888, 0x101F02AA }, + { 0x9888, 0x00384000 }, + { 0x9888, 0x0E384000 }, + { 0x9888, 0x16384000 }, + { 0x9888, 0x18381555 }, + { 0x9888, 0x02384000 }, + { 0x9888, 0x04384000 }, + { 0x9888, 0x0A384000 }, + { 0x9888, 0x0C384000 }, + { 0x9888, 0x0039A000 }, + { 0x9888, 0x0639A000 }, + { 0x9888, 0x0839A000 }, + { 0x9888, 0x0A39A000 }, + { 0x9888, 0x0C39A000 }, + { 0x9888, 0x0E39A000 }, + { 0x9888, 0x02392000 }, + { 0x9888, 0x04398000 }, + { 0x9888, 0x018A8000 }, + { 0x9888, 0x0F8A8000 }, + { 0x9888, 0x198A8000 }, + { 0x9888, 0x1B8AAAA0 }, + { 0x9888, 0x1D8A0002 }, + { 0x9888, 0x038A8000 }, + { 0x9888, 0x058A8000 }, + { 0x9888, 0x0B8A8000 }, + { 0x9888, 0x0D8A8000 }, + { 0x9888, 0x038B6300 }, + { 0x9888, 0x058B0062 }, + { 0x9888, 0x118B0000 }, + { 0x9888, 0x238B02A0 }, + { 0x9888, 0x258B5555 }, + { 0x9888, 0x278B0015 }, + { 0x9888, 0x1F85AA80 }, + { 0x9888, 0x2185AAAA }, + { 0x9888, 0x2385002A }, + { 0x9888, 0x01834000 }, + { 0x9888, 0x0F834000 }, + { 0x9888, 0x19835400 }, + { 0x9888, 0x1B830155 }, + { 0x9888, 0x03834000 }, + { 0x9888, 0x05834000 }, + { 0x9888, 0x07834000 }, + { 0x9888, 0x09834000 }, + { 0x9888, 0x0B834000 }, + { 0x9888, 0x0D834000 }, + { 0x9888, 0x0184C000 }, + { 0x9888, 0x0784C000 }, + { 0x9888, 0x0984C000 }, + { 0x9888, 0x0B84C000 }, + { 0x9888, 0x0D84C000 }, + { 0x9888, 0x0F84C000 }, + { 0x9888, 0x0384C000 }, + { 0x9888, 0x0584C000 }, + { 0x9888, 0x1180C000 }, + { 0x9888, 0x1780C000 }, + { 0x9888, 0x1980C000 }, + { 0x9888, 0x1B80C000 }, + { 0x9888, 0x1D80C000 }, + { 0x9888, 0x1F80C000 }, + { 0x9888, 0x1380C000 }, + { 0x9888, 0x1580C000 }, + { 0x0D24, 0x00000000 }, + { 0x9888, 0x4D801000 }, + { 0x9888, 0x3D800000 }, + { 0x9888, 0x4F800001 }, + { 0x9888, 0x43800000 }, + { 0x9888, 0x51800000 }, + { 0x9888, 0x45800000 }, + { 0x9888, 0x53800000 }, + { 0x9888, 0x47800420 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x3F800421 }, + { 0x9888, 0x41800041 }, +}; + +static int select_data_port_reads_coalescing_config(struct drm_i915_private *dev_priv) +{ + if (INTEL_INFO(dev_priv)->subslice_mask & 0x01) { + dev_priv->perf.oa.mux_regs = + mux_config_data_port_reads_coalescing_1_0_subslices_0x01; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_data_port_reads_coalescing_1_0_subslices_0x01); + } else { + DRM_DEBUG_DRIVER("No suitable MUX config for \"DATA_PORT_READS_COALESCING\" metric set"); + return -EINVAL; + } + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_data_port_reads_coalescing; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_data_port_reads_coalescing); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_data_port_reads_coalescing; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_data_port_reads_coalescing); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_data_port_writes_coalescing[] = { + { 0x2724, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2710, 0x00000000 }, + { 0x274c, 0xba98ba98 }, + { 0x2748, 0xba98ba98 }, + { 0x2744, 0x00003377 }, + { 0x2740, 0x00000000 }, + { 0x2770, 0x0007ff72 }, + { 0x2774, 0x0000bfd0 }, + { 0x2778, 0x0007ff62 }, + { 0x277c, 0x0000bfd0 }, + { 0x2780, 0x0007ff42 }, + { 0x2784, 0x0000bfd0 }, + { 0x2788, 0x0007ff02 }, + { 0x278c, 0x0000bfd0 }, + { 0x2790, 0x0005fff2 }, + { 0x2794, 0x0000bfd0 }, + { 0x2798, 0x0005ffe2 }, + { 0x279c, 0x0000bfd0 }, + { 0x27a0, 0x0005ffc2 }, + { 0x27a4, 0x0000bfd0 }, + { 0x27a8, 0x0005ff82 }, + { 0x27ac, 0x0000bfd0 }, +}; + +static const struct i915_oa_reg flex_eu_config_data_port_writes_coalescing[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00000003 }, + { 0xE658, 0x00002001 }, + { 0xE758, 0x00778008 }, + { 0xE45c, 0x00088078 }, + { 0xE55c, 0x00808708 }, + { 0xE65c, 0x00a08908 }, +}; + +static const struct i915_oa_reg mux_config_data_port_writes_coalescing_1_0_subslices_0x01[] = { + { 0x9888, 0x103D0005 }, + { 0x9888, 0x143D0120 }, + { 0x9888, 0x163D2400 }, + { 0x9888, 0x1058022F }, + { 0x9888, 0x105B0000 }, + { 0x9888, 0x198B0003 }, + { 0x9888, 0x005CC000 }, + { 0x9888, 0x065CC000 }, + { 0x9888, 0x085CC000 }, + { 0x9888, 0x0A5CC000 }, + { 0x9888, 0x0E5CC000 }, + { 0x9888, 0x025C4000 }, + { 0x9888, 0x045C8000 }, + { 0x9888, 0x003D0000 }, + { 0x9888, 0x063D0094 }, + { 0x9888, 0x083D0182 }, + { 0x9888, 0x0A3D1814 }, + { 0x9888, 0x0E3D0000 }, + { 0x9888, 0x183D0000 }, + { 0x9888, 0x1A3D0000 }, + { 0x9888, 0x0C3D0000 }, + { 0x9888, 0x0E582242 }, + { 0x9888, 0x00586700 }, + { 0x9888, 0x0258004F }, + { 0x9888, 0x0658C000 }, + { 0x9888, 0x0858C000 }, + { 0x9888, 0x0A58C000 }, + { 0x9888, 0x045B6A80 }, + { 0x9888, 0x005B4000 }, + { 0x9888, 0x0E5B4000 }, + { 0x9888, 0x185B5400 }, + { 0x9888, 0x1A5B0141 }, + { 0x9888, 0x025B4000 }, + { 0x9888, 0x0A5B0000 }, + { 0x9888, 0x0C5B4000 }, + { 0x9888, 0x0C1FA800 }, + { 0x9888, 0x0E1FAAA0 }, + { 0x9888, 0x101F0282 }, + { 0x9888, 0x00384000 }, + { 0x9888, 0x0E384000 }, + { 0x9888, 0x16384000 }, + { 0x9888, 0x18381415 }, + { 0x9888, 0x02384000 }, + { 0x9888, 0x04384000 }, + { 0x9888, 0x0A384000 }, + { 0x9888, 0x0C384000 }, + { 0x9888, 0x0039A000 }, + { 0x9888, 0x0639A000 }, + { 0x9888, 0x0839A000 }, + { 0x9888, 0x0A39A000 }, + { 0x9888, 0x0E39A000 }, + { 0x9888, 0x02392000 }, + { 0x9888, 0x04398000 }, + { 0x9888, 0x018A8000 }, + { 0x9888, 0x0F8A8000 }, + { 0x9888, 0x198A8000 }, + { 0x9888, 0x1B8A82A0 }, + { 0x9888, 0x1D8A0002 }, + { 0x9888, 0x038A8000 }, + { 0x9888, 0x058A8000 }, + { 0x9888, 0x0B8A8000 }, + { 0x9888, 0x0D8A8000 }, + { 0x9888, 0x038B6300 }, + { 0x9888, 0x058B0062 }, + { 0x9888, 0x118B0000 }, + { 0x9888, 0x238B02A0 }, + { 0x9888, 0x258B1555 }, + { 0x9888, 0x278B0014 }, + { 0x9888, 0x1F85AA80 }, + { 0x9888, 0x21852AAA }, + { 0x9888, 0x23850028 }, + { 0x9888, 0x01834000 }, + { 0x9888, 0x0F834000 }, + { 0x9888, 0x19835400 }, + { 0x9888, 0x1B830141 }, + { 0x9888, 0x03834000 }, + { 0x9888, 0x05834000 }, + { 0x9888, 0x07834000 }, + { 0x9888, 0x09834000 }, + { 0x9888, 0x0B834000 }, + { 0x9888, 0x0D834000 }, + { 0x9888, 0x0184C000 }, + { 0x9888, 0x0784C000 }, + { 0x9888, 0x0984C000 }, + { 0x9888, 0x0B84C000 }, + { 0x9888, 0x0F84C000 }, + { 0x9888, 0x0384C000 }, + { 0x9888, 0x0584C000 }, + { 0x9888, 0x1180C000 }, + { 0x9888, 0x1780C000 }, + { 0x9888, 0x1980C000 }, + { 0x9888, 0x1B80C000 }, + { 0x9888, 0x1F80C000 }, + { 0x9888, 0x1380C000 }, + { 0x9888, 0x1580C000 }, + { 0x0D24, 0x00000000 }, + { 0x9888, 0x4D801000 }, + { 0x9888, 0x3D800000 }, + { 0x9888, 0x4F800001 }, + { 0x9888, 0x43800000 }, + { 0x9888, 0x51800000 }, + { 0x9888, 0x45800000 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x53800000 }, + { 0x9888, 0x47800420 }, + { 0x9888, 0x3F800421 }, + { 0x9888, 0x41800041 }, +}; + +static int select_data_port_writes_coalescing_config(struct drm_i915_private *dev_priv) +{ + if (INTEL_INFO(dev_priv)->subslice_mask & 0x01) { + dev_priv->perf.oa.mux_regs = + mux_config_data_port_writes_coalescing_1_0_subslices_0x01; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_data_port_writes_coalescing_1_0_subslices_0x01); + } else { + DRM_DEBUG_DRIVER("No suitable MUX config for \"DATA_PORT_WRITES_COALESCING\" metric set"); + return -EINVAL; + } + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_data_port_writes_coalescing; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_data_port_writes_coalescing); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_data_port_writes_coalescing; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_data_port_writes_coalescing); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0x10800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x00800000 }, + { 0x2770, 0x00000002 }, + { 0x2774, 0x0000fff7 }, +}; + +static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_hdc_and_sf[] = { + { 0x9888, 0x105c0232 }, + { 0x9888, 0x10580232 }, + { 0x9888, 0x10380232 }, + { 0x9888, 0x10dc0232 }, + { 0x9888, 0x10d80232 }, + { 0x9888, 0x10b80232 }, + { 0x9888, 0x118e4400 }, + { 0x9888, 0x025c6080 }, + { 0x9888, 0x045c004b }, + { 0x9888, 0x005c8000 }, + { 0x9888, 0x00582080 }, + { 0x9888, 0x0258004b }, + { 0x9888, 0x025b4000 }, + { 0x9888, 0x045b4000 }, + { 0x9888, 0x0c1fa000 }, + { 0x9888, 0x0e1f00aa }, + { 0x9888, 0x04386080 }, + { 0x9888, 0x0638404b }, + { 0x9888, 0x02384000 }, + { 0x9888, 0x08384000 }, + { 0x9888, 0x0a380000 }, + { 0x9888, 0x0c380000 }, + { 0x9888, 0x00398000 }, + { 0x9888, 0x0239a000 }, + { 0x9888, 0x0439a000 }, + { 0x9888, 0x06392000 }, + { 0x9888, 0x0cdc25c1 }, + { 0x9888, 0x0adcc000 }, + { 0x9888, 0x0ad825c1 }, + { 0x9888, 0x18db4000 }, + { 0x9888, 0x1adb0001 }, + { 0x9888, 0x0e9f8000 }, + { 0x9888, 0x109f02aa }, + { 0x9888, 0x0eb825c1 }, + { 0x9888, 0x18b80154 }, + { 0x9888, 0x0ab9a000 }, + { 0x9888, 0x0cb9a000 }, + { 0x9888, 0x0eb9a000 }, + { 0x9888, 0x0d88c000 }, + { 0x9888, 0x0f88000f }, + { 0x9888, 0x038a8000 }, + { 0x9888, 0x058a8000 }, + { 0x9888, 0x078a8000 }, + { 0x9888, 0x098a8000 }, + { 0x9888, 0x0b8a8000 }, + { 0x9888, 0x0d8a8000 }, + { 0x9888, 0x258baa05 }, + { 0x9888, 0x278b002a }, + { 0x9888, 0x238b2a80 }, + { 0x9888, 0x198c5400 }, + { 0x9888, 0x1b8c0015 }, + { 0x9888, 0x098dc000 }, + { 0x9888, 0x0b8da000 }, + { 0x9888, 0x0d8da000 }, + { 0x9888, 0x0f8da000 }, + { 0x9888, 0x098e05c0 }, + { 0x9888, 0x058e0000 }, + { 0x9888, 0x198f0020 }, + { 0x9888, 0x2185aa0a }, + { 0x9888, 0x2385002a }, + { 0x9888, 0x1f85aa00 }, + { 0x9888, 0x19835000 }, + { 0x9888, 0x1b830155 }, + { 0x9888, 0x03834000 }, + { 0x9888, 0x05834000 }, + { 0x9888, 0x07834000 }, + { 0x9888, 0x09834000 }, + { 0x9888, 0x0b834000 }, + { 0x9888, 0x0d834000 }, + { 0x9888, 0x09848000 }, + { 0x9888, 0x0b84c000 }, + { 0x9888, 0x0d84c000 }, + { 0x9888, 0x0f84c000 }, + { 0x9888, 0x01848000 }, + { 0x9888, 0x0384c000 }, + { 0x9888, 0x0584c000 }, + { 0x9888, 0x07844000 }, + { 0x9888, 0x19808000 }, + { 0x9888, 0x1b80c000 }, + { 0x9888, 0x1d80c000 }, + { 0x9888, 0x1f80c000 }, + { 0x9888, 0x11808000 }, + { 0x9888, 0x1380c000 }, + { 0x9888, 0x1580c000 }, + { 0x9888, 0x17804000 }, + { 0x9888, 0x51800040 }, + { 0x9888, 0x43800400 }, + { 0x9888, 0x45800800 }, + { 0x9888, 0x53800000 }, + { 0x9888, 0x47800c62 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x4d800000 }, + { 0x9888, 0x3f801042 }, + { 0x9888, 0x4f800000 }, + { 0x9888, 0x418014a4 }, +}; + +static int select_hdc_and_sf_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_hdc_and_sf; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_hdc_and_sf); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_hdc_and_sf; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_hdc_and_sf); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_hdc_and_sf; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_hdc_and_sf); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_l3_1[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0xf0800000 }, + { 0x2770, 0x00100070 }, + { 0x2774, 0x0000fff1 }, + { 0x2778, 0x00014002 }, + { 0x277c, 0x0000c3ff }, + { 0x2780, 0x00010002 }, + { 0x2784, 0x0000c7ff }, + { 0x2788, 0x00004002 }, + { 0x278c, 0x0000d3ff }, + { 0x2790, 0x00100700 }, + { 0x2794, 0x0000ff1f }, + { 0x2798, 0x00001402 }, + { 0x279c, 0x0000fc3f }, + { 0x27a0, 0x00001002 }, + { 0x27a4, 0x0000fc7f }, + { 0x27a8, 0x00000402 }, + { 0x27ac, 0x0000fd3f }, +}; + +static const struct i915_oa_reg flex_eu_config_l3_1[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_l3_1[] = { + { 0x9888, 0x10bf03da }, + { 0x9888, 0x14bf0001 }, + { 0x9888, 0x12980340 }, + { 0x9888, 0x12990340 }, + { 0x9888, 0x0cbf1187 }, + { 0x9888, 0x0ebf1205 }, + { 0x9888, 0x00bf0500 }, + { 0x9888, 0x02bf042b }, + { 0x9888, 0x04bf002c }, + { 0x9888, 0x0cdac000 }, + { 0x9888, 0x0edac000 }, + { 0x9888, 0x00da8000 }, + { 0x9888, 0x02dac000 }, + { 0x9888, 0x04da4000 }, + { 0x9888, 0x04983400 }, + { 0x9888, 0x10980000 }, + { 0x9888, 0x06990034 }, + { 0x9888, 0x10990000 }, + { 0x9888, 0x0c9dc000 }, + { 0x9888, 0x0e9dc000 }, + { 0x9888, 0x009d8000 }, + { 0x9888, 0x029dc000 }, + { 0x9888, 0x049d4000 }, + { 0x9888, 0x109f02a8 }, + { 0x9888, 0x0c9fa000 }, + { 0x9888, 0x0e9f00ba }, + { 0x9888, 0x0cb88000 }, + { 0x9888, 0x0cb95000 }, + { 0x9888, 0x0eb95000 }, + { 0x9888, 0x00b94000 }, + { 0x9888, 0x02b95000 }, + { 0x9888, 0x04b91000 }, + { 0x9888, 0x06b92000 }, + { 0x9888, 0x0cba4000 }, + { 0x9888, 0x0f88000f }, + { 0x9888, 0x03888000 }, + { 0x9888, 0x05888000 }, + { 0x9888, 0x07888000 }, + { 0x9888, 0x09888000 }, + { 0x9888, 0x0b888000 }, + { 0x9888, 0x0d880400 }, + { 0x9888, 0x258b800a }, + { 0x9888, 0x278b002a }, + { 0x9888, 0x238b5500 }, + { 0x9888, 0x198c4000 }, + { 0x9888, 0x1b8c0015 }, + { 0x9888, 0x038c4000 }, + { 0x9888, 0x058c4000 }, + { 0x9888, 0x078c4000 }, + { 0x9888, 0x098c4000 }, + { 0x9888, 0x0b8c4000 }, + { 0x9888, 0x0d8c4000 }, + { 0x9888, 0x0d8da000 }, + { 0x9888, 0x0f8da000 }, + { 0x9888, 0x018d8000 }, + { 0x9888, 0x038da000 }, + { 0x9888, 0x058da000 }, + { 0x9888, 0x078d2000 }, + { 0x9888, 0x2185800a }, + { 0x9888, 0x2385002a }, + { 0x9888, 0x1f85aa00 }, + { 0x9888, 0x1b830154 }, + { 0x9888, 0x03834000 }, + { 0x9888, 0x05834000 }, + { 0x9888, 0x07834000 }, + { 0x9888, 0x09834000 }, + { 0x9888, 0x0b834000 }, + { 0x9888, 0x0d834000 }, + { 0x9888, 0x0d84c000 }, + { 0x9888, 0x0f84c000 }, + { 0x9888, 0x01848000 }, + { 0x9888, 0x0384c000 }, + { 0x9888, 0x0584c000 }, + { 0x9888, 0x07844000 }, + { 0x9888, 0x1d80c000 }, + { 0x9888, 0x1f80c000 }, + { 0x9888, 0x11808000 }, + { 0x9888, 0x1380c000 }, + { 0x9888, 0x1580c000 }, + { 0x9888, 0x17804000 }, + { 0x9888, 0x53800000 }, + { 0x9888, 0x45800000 }, + { 0x9888, 0x47800000 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x4d800000 }, + { 0x9888, 0x3f800000 }, + { 0x9888, 0x4f800000 }, + { 0x9888, 0x41800060 }, +}; + +static int select_l3_1_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_l3_1; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_l3_1); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_l3_1; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_l3_1); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_l3_1; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_l3_1); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_l3_2[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0xf0800000 }, + { 0x2770, 0x00100070 }, + { 0x2774, 0x0000fff1 }, + { 0x2778, 0x00014002 }, + { 0x277c, 0x0000c3ff }, + { 0x2780, 0x00010002 }, + { 0x2784, 0x0000c7ff }, + { 0x2788, 0x00004002 }, + { 0x278c, 0x0000d3ff }, + { 0x2790, 0x00100700 }, + { 0x2794, 0x0000ff1f }, + { 0x2798, 0x00001402 }, + { 0x279c, 0x0000fc3f }, + { 0x27a0, 0x00001002 }, + { 0x27a4, 0x0000fc7f }, + { 0x27a8, 0x00000402 }, + { 0x27ac, 0x0000fd3f }, +}; + +static const struct i915_oa_reg flex_eu_config_l3_2[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_l3_2[] = { + { 0x9888, 0x103f03da }, + { 0x9888, 0x143f0001 }, + { 0x9888, 0x12180340 }, + { 0x9888, 0x12190340 }, + { 0x9888, 0x0c3f1187 }, + { 0x9888, 0x0e3f1205 }, + { 0x9888, 0x003f0500 }, + { 0x9888, 0x023f042b }, + { 0x9888, 0x043f002c }, + { 0x9888, 0x0c5ac000 }, + { 0x9888, 0x0e5ac000 }, + { 0x9888, 0x005a8000 }, + { 0x9888, 0x025ac000 }, + { 0x9888, 0x045a4000 }, + { 0x9888, 0x04183400 }, + { 0x9888, 0x10180000 }, + { 0x9888, 0x06190034 }, + { 0x9888, 0x10190000 }, + { 0x9888, 0x0c1dc000 }, + { 0x9888, 0x0e1dc000 }, + { 0x9888, 0x001d8000 }, + { 0x9888, 0x021dc000 }, + { 0x9888, 0x041d4000 }, + { 0x9888, 0x101f02a8 }, + { 0x9888, 0x0c1fa000 }, + { 0x9888, 0x0e1f00ba }, + { 0x9888, 0x0c388000 }, + { 0x9888, 0x0c395000 }, + { 0x9888, 0x0e395000 }, + { 0x9888, 0x00394000 }, + { 0x9888, 0x02395000 }, + { 0x9888, 0x04391000 }, + { 0x9888, 0x06392000 }, + { 0x9888, 0x0c3a4000 }, + { 0x9888, 0x1b8aa800 }, + { 0x9888, 0x1d8a0002 }, + { 0x9888, 0x038a8000 }, + { 0x9888, 0x058a8000 }, + { 0x9888, 0x078a8000 }, + { 0x9888, 0x098a8000 }, + { 0x9888, 0x0b8a8000 }, + { 0x9888, 0x0d8a8000 }, + { 0x9888, 0x258b4005 }, + { 0x9888, 0x278b0015 }, + { 0x9888, 0x238b2a80 }, + { 0x9888, 0x2185800a }, + { 0x9888, 0x2385002a }, + { 0x9888, 0x1f85aa00 }, + { 0x9888, 0x1b830154 }, + { 0x9888, 0x03834000 }, + { 0x9888, 0x05834000 }, + { 0x9888, 0x07834000 }, + { 0x9888, 0x09834000 }, + { 0x9888, 0x0b834000 }, + { 0x9888, 0x0d834000 }, + { 0x9888, 0x0d84c000 }, + { 0x9888, 0x0f84c000 }, + { 0x9888, 0x01848000 }, + { 0x9888, 0x0384c000 }, + { 0x9888, 0x0584c000 }, + { 0x9888, 0x07844000 }, + { 0x9888, 0x1d80c000 }, + { 0x9888, 0x1f80c000 }, + { 0x9888, 0x11808000 }, + { 0x9888, 0x1380c000 }, + { 0x9888, 0x1580c000 }, + { 0x9888, 0x17804000 }, + { 0x9888, 0x53800000 }, + { 0x9888, 0x45800000 }, + { 0x9888, 0x47800000 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x4d800000 }, + { 0x9888, 0x3f800000 }, + { 0x9888, 0x4f800000 }, + { 0x9888, 0x41800060 }, +}; + +static int select_l3_2_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_l3_2; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_l3_2); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_l3_2; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_l3_2); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_l3_2; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_l3_2); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_l3_3[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0xf0800000 }, + { 0x2770, 0x00100070 }, + { 0x2774, 0x0000fff1 }, + { 0x2778, 0x00014002 }, + { 0x277c, 0x0000c3ff }, + { 0x2780, 0x00010002 }, + { 0x2784, 0x0000c7ff }, + { 0x2788, 0x00004002 }, + { 0x278c, 0x0000d3ff }, + { 0x2790, 0x00100700 }, + { 0x2794, 0x0000ff1f }, + { 0x2798, 0x00001402 }, + { 0x279c, 0x0000fc3f }, + { 0x27a0, 0x00001002 }, + { 0x27a4, 0x0000fc7f }, + { 0x27a8, 0x00000402 }, + { 0x27ac, 0x0000fd3f }, +}; + +static const struct i915_oa_reg flex_eu_config_l3_3[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_l3_3[] = { + { 0x9888, 0x121b0340 }, + { 0x9888, 0x103f0274 }, + { 0x9888, 0x123f0000 }, + { 0x9888, 0x129b0340 }, + { 0x9888, 0x10bf0274 }, + { 0x9888, 0x12bf0000 }, + { 0x9888, 0x041b3400 }, + { 0x9888, 0x101b0000 }, + { 0x9888, 0x045c8000 }, + { 0x9888, 0x0a3d4000 }, + { 0x9888, 0x003f0080 }, + { 0x9888, 0x023f0793 }, + { 0x9888, 0x043f0014 }, + { 0x9888, 0x04588000 }, + { 0x9888, 0x005a8000 }, + { 0x9888, 0x025ac000 }, + { 0x9888, 0x045a4000 }, + { 0x9888, 0x0a5b4000 }, + { 0x9888, 0x001d8000 }, + { 0x9888, 0x021dc000 }, + { 0x9888, 0x041d4000 }, + { 0x9888, 0x0c1fa000 }, + { 0x9888, 0x0e1f002a }, + { 0x9888, 0x0a384000 }, + { 0x9888, 0x00394000 }, + { 0x9888, 0x02395000 }, + { 0x9888, 0x04399000 }, + { 0x9888, 0x069b0034 }, + { 0x9888, 0x109b0000 }, + { 0x9888, 0x06dc4000 }, + { 0x9888, 0x0cbd4000 }, + { 0x9888, 0x0cbf0981 }, + { 0x9888, 0x0ebf0a0f }, + { 0x9888, 0x06d84000 }, + { 0x9888, 0x0cdac000 }, + { 0x9888, 0x0edac000 }, + { 0x9888, 0x0cdb4000 }, + { 0x9888, 0x0c9dc000 }, + { 0x9888, 0x0e9dc000 }, + { 0x9888, 0x109f02a8 }, + { 0x9888, 0x0e9f0080 }, + { 0x9888, 0x0cb84000 }, + { 0x9888, 0x0cb95000 }, + { 0x9888, 0x0eb95000 }, + { 0x9888, 0x06b92000 }, + { 0x9888, 0x0f88000f }, + { 0x9888, 0x0d880400 }, + { 0x9888, 0x038a8000 }, + { 0x9888, 0x058a8000 }, + { 0x9888, 0x078a8000 }, + { 0x9888, 0x098a8000 }, + { 0x9888, 0x0b8a8000 }, + { 0x9888, 0x258b8009 }, + { 0x9888, 0x278b002a }, + { 0x9888, 0x238b2a80 }, + { 0x9888, 0x198c4000 }, + { 0x9888, 0x1b8c0015 }, + { 0x9888, 0x0d8c4000 }, + { 0x9888, 0x0d8da000 }, + { 0x9888, 0x0f8da000 }, + { 0x9888, 0x078d2000 }, + { 0x9888, 0x2185800a }, + { 0x9888, 0x2385002a }, + { 0x9888, 0x1f85aa00 }, + { 0x9888, 0x1b830154 }, + { 0x9888, 0x03834000 }, + { 0x9888, 0x05834000 }, + { 0x9888, 0x07834000 }, + { 0x9888, 0x09834000 }, + { 0x9888, 0x0b834000 }, + { 0x9888, 0x0d834000 }, + { 0x9888, 0x0d84c000 }, + { 0x9888, 0x0f84c000 }, + { 0x9888, 0x01848000 }, + { 0x9888, 0x0384c000 }, + { 0x9888, 0x0584c000 }, + { 0x9888, 0x07844000 }, + { 0x9888, 0x1d80c000 }, + { 0x9888, 0x1f80c000 }, + { 0x9888, 0x11808000 }, + { 0x9888, 0x1380c000 }, + { 0x9888, 0x1580c000 }, + { 0x9888, 0x17804000 }, + { 0x9888, 0x53800000 }, + { 0x9888, 0x45800c00 }, + { 0x9888, 0x47800c63 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x4d800000 }, + { 0x9888, 0x3f8014a5 }, + { 0x9888, 0x4f800000 }, + { 0x9888, 0x41800045 }, +}; + +static int select_l3_3_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_l3_3; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_l3_3); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_l3_3; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_l3_3); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_l3_3; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_l3_3); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_l3_4[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0xf0800000 }, + { 0x2770, 0x00100070 }, + { 0x2774, 0x0000fff1 }, + { 0x2778, 0x00014002 }, + { 0x277c, 0x0000c3ff }, + { 0x2780, 0x00010002 }, + { 0x2784, 0x0000c7ff }, + { 0x2788, 0x00004002 }, + { 0x278c, 0x0000d3ff }, + { 0x2790, 0x00100700 }, + { 0x2794, 0x0000ff1f }, + { 0x2798, 0x00001402 }, + { 0x279c, 0x0000fc3f }, + { 0x27a0, 0x00001002 }, + { 0x27a4, 0x0000fc7f }, + { 0x27a8, 0x00000402 }, + { 0x27ac, 0x0000fd3f }, +}; + +static const struct i915_oa_reg flex_eu_config_l3_4[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_l3_4[] = { + { 0x9888, 0x121a0340 }, + { 0x9888, 0x103f0017 }, + { 0x9888, 0x123f0020 }, + { 0x9888, 0x129a0340 }, + { 0x9888, 0x10bf0017 }, + { 0x9888, 0x12bf0020 }, + { 0x9888, 0x041a3400 }, + { 0x9888, 0x101a0000 }, + { 0x9888, 0x043b8000 }, + { 0x9888, 0x0a3e0010 }, + { 0x9888, 0x003f0200 }, + { 0x9888, 0x023f0113 }, + { 0x9888, 0x043f0014 }, + { 0x9888, 0x02592000 }, + { 0x9888, 0x005a8000 }, + { 0x9888, 0x025ac000 }, + { 0x9888, 0x045a4000 }, + { 0x9888, 0x0a1c8000 }, + { 0x9888, 0x001d8000 }, + { 0x9888, 0x021dc000 }, + { 0x9888, 0x041d4000 }, + { 0x9888, 0x0a1e8000 }, + { 0x9888, 0x0c1fa000 }, + { 0x9888, 0x0e1f001a }, + { 0x9888, 0x00394000 }, + { 0x9888, 0x02395000 }, + { 0x9888, 0x04391000 }, + { 0x9888, 0x069a0034 }, + { 0x9888, 0x109a0000 }, + { 0x9888, 0x06bb4000 }, + { 0x9888, 0x0abe0040 }, + { 0x9888, 0x0cbf0984 }, + { 0x9888, 0x0ebf0a02 }, + { 0x9888, 0x02d94000 }, + { 0x9888, 0x0cdac000 }, + { 0x9888, 0x0edac000 }, + { 0x9888, 0x0c9c0400 }, + { 0x9888, 0x0c9dc000 }, + { 0x9888, 0x0e9dc000 }, + { 0x9888, 0x0c9e0400 }, + { 0x9888, 0x109f02a8 }, + { 0x9888, 0x0e9f0040 }, + { 0x9888, 0x0cb95000 }, + { 0x9888, 0x0eb95000 }, + { 0x9888, 0x0f88000f }, + { 0x9888, 0x0d880400 }, + { 0x9888, 0x038a8000 }, + { 0x9888, 0x058a8000 }, + { 0x9888, 0x078a8000 }, + { 0x9888, 0x098a8000 }, + { 0x9888, 0x0b8a8000 }, + { 0x9888, 0x258b8009 }, + { 0x9888, 0x278b002a }, + { 0x9888, 0x238b2a80 }, + { 0x9888, 0x198c4000 }, + { 0x9888, 0x1b8c0015 }, + { 0x9888, 0x0d8c4000 }, + { 0x9888, 0x0d8da000 }, + { 0x9888, 0x0f8da000 }, + { 0x9888, 0x078d2000 }, + { 0x9888, 0x2185800a }, + { 0x9888, 0x2385002a }, + { 0x9888, 0x1f85aa00 }, + { 0x9888, 0x1b830154 }, + { 0x9888, 0x03834000 }, + { 0x9888, 0x05834000 }, + { 0x9888, 0x07834000 }, + { 0x9888, 0x09834000 }, + { 0x9888, 0x0b834000 }, + { 0x9888, 0x0d834000 }, + { 0x9888, 0x0d84c000 }, + { 0x9888, 0x0f84c000 }, + { 0x9888, 0x01848000 }, + { 0x9888, 0x0384c000 }, + { 0x9888, 0x0584c000 }, + { 0x9888, 0x07844000 }, + { 0x9888, 0x1d80c000 }, + { 0x9888, 0x1f80c000 }, + { 0x9888, 0x11808000 }, + { 0x9888, 0x1380c000 }, + { 0x9888, 0x1580c000 }, + { 0x9888, 0x17804000 }, + { 0x9888, 0x53800000 }, + { 0x9888, 0x45800800 }, + { 0x9888, 0x47800842 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x4d800000 }, + { 0x9888, 0x3f801084 }, + { 0x9888, 0x4f800000 }, + { 0x9888, 0x41800044 }, +}; + +static int select_l3_4_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_l3_4; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_l3_4); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_l3_4; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_l3_4); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_l3_4; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_l3_4); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x30800000 }, + { 0x2770, 0x00006000 }, + { 0x2774, 0x0000f3ff }, + { 0x2778, 0x00001800 }, + { 0x277c, 0x0000fcff }, + { 0x2780, 0x00000600 }, + { 0x2784, 0x0000ff3f }, + { 0x2788, 0x00000180 }, + { 0x278c, 0x0000ffcf }, + { 0x2790, 0x00000060 }, + { 0x2794, 0x0000fff3 }, + { 0x2798, 0x00000018 }, + { 0x279c, 0x0000fffc }, +}; + +static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { + { 0x9888, 0x143b000e }, + { 0x9888, 0x043c55c0 }, + { 0x9888, 0x0a1e0280 }, + { 0x9888, 0x0c1e0408 }, + { 0x9888, 0x10390000 }, + { 0x9888, 0x12397a1f }, + { 0x9888, 0x14bb000e }, + { 0x9888, 0x04bc5000 }, + { 0x9888, 0x0a9e0296 }, + { 0x9888, 0x0c9e0008 }, + { 0x9888, 0x10b90000 }, + { 0x9888, 0x12b97a1f }, + { 0x9888, 0x063b0042 }, + { 0x9888, 0x103b0000 }, + { 0x9888, 0x083c0000 }, + { 0x9888, 0x0a3e0040 }, + { 0x9888, 0x043f8000 }, + { 0x9888, 0x02594000 }, + { 0x9888, 0x045a8000 }, + { 0x9888, 0x0c1c0400 }, + { 0x9888, 0x041d8000 }, + { 0x9888, 0x081e02c0 }, + { 0x9888, 0x0e1e0000 }, + { 0x9888, 0x0c1fa800 }, + { 0x9888, 0x0e1f0260 }, + { 0x9888, 0x101f0014 }, + { 0x9888, 0x003905e0 }, + { 0x9888, 0x06390bc0 }, + { 0x9888, 0x02390018 }, + { 0x9888, 0x04394000 }, + { 0x9888, 0x04bb0042 }, + { 0x9888, 0x10bb0000 }, + { 0x9888, 0x02bc05c0 }, + { 0x9888, 0x08bc0000 }, + { 0x9888, 0x0abe0004 }, + { 0x9888, 0x02bf8000 }, + { 0x9888, 0x02d91000 }, + { 0x9888, 0x02da8000 }, + { 0x9888, 0x089c8000 }, + { 0x9888, 0x029d8000 }, + { 0x9888, 0x089e8000 }, + { 0x9888, 0x0e9e0000 }, + { 0x9888, 0x0e9fa806 }, + { 0x9888, 0x109f0142 }, + { 0x9888, 0x08b90617 }, + { 0x9888, 0x0ab90be0 }, + { 0x9888, 0x02b94000 }, + { 0x9888, 0x0d88f000 }, + { 0x9888, 0x0f88000c }, + { 0x9888, 0x07888000 }, + { 0x9888, 0x09888000 }, + { 0x9888, 0x018a8000 }, + { 0x9888, 0x0f8a8000 }, + { 0x9888, 0x1b8a2800 }, + { 0x9888, 0x038a8000 }, + { 0x9888, 0x058a8000 }, + { 0x9888, 0x0b8a8000 }, + { 0x9888, 0x0d8a8000 }, + { 0x9888, 0x238b52a0 }, + { 0x9888, 0x258b6a95 }, + { 0x9888, 0x278b0029 }, + { 0x9888, 0x178c2000 }, + { 0x9888, 0x198c1500 }, + { 0x9888, 0x1b8c0014 }, + { 0x9888, 0x078c4000 }, + { 0x9888, 0x098c4000 }, + { 0x9888, 0x098da000 }, + { 0x9888, 0x0b8da000 }, + { 0x9888, 0x0f8da000 }, + { 0x9888, 0x038d8000 }, + { 0x9888, 0x058d2000 }, + { 0x9888, 0x1f85aa80 }, + { 0x9888, 0x2185aaaa }, + { 0x9888, 0x2385002a }, + { 0x9888, 0x01834000 }, + { 0x9888, 0x0f834000 }, + { 0x9888, 0x19835400 }, + { 0x9888, 0x1b830155 }, + { 0x9888, 0x03834000 }, + { 0x9888, 0x05834000 }, + { 0x9888, 0x07834000 }, + { 0x9888, 0x09834000 }, + { 0x9888, 0x0b834000 }, + { 0x9888, 0x0d834000 }, + { 0x9888, 0x0184c000 }, + { 0x9888, 0x0784c000 }, + { 0x9888, 0x0984c000 }, + { 0x9888, 0x0b84c000 }, + { 0x9888, 0x0d84c000 }, + { 0x9888, 0x0f84c000 }, + { 0x9888, 0x0384c000 }, + { 0x9888, 0x0584c000 }, + { 0x9888, 0x1180c000 }, + { 0x9888, 0x1780c000 }, + { 0x9888, 0x1980c000 }, + { 0x9888, 0x1b80c000 }, + { 0x9888, 0x1d80c000 }, + { 0x9888, 0x1f80c000 }, + { 0x9888, 0x1380c000 }, + { 0x9888, 0x1580c000 }, + { 0x9888, 0x4d800444 }, + { 0x9888, 0x3d800000 }, + { 0x9888, 0x4f804000 }, + { 0x9888, 0x43801080 }, + { 0x9888, 0x51800000 }, + { 0x9888, 0x45800084 }, + { 0x9888, 0x53800044 }, + { 0x9888, 0x47801080 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x3f800000 }, + { 0x9888, 0x41800840 }, +}; + +static int select_rasterizer_and_pixel_backend_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_rasterizer_and_pixel_backend; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_rasterizer_and_pixel_backend; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_rasterizer_and_pixel_backend; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_sampler_1[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0x70800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x00800000 }, + { 0x2770, 0x0000c000 }, + { 0x2774, 0x0000e7ff }, + { 0x2778, 0x00003000 }, + { 0x277c, 0x0000f9ff }, + { 0x2780, 0x00000c00 }, + { 0x2784, 0x0000fe7f }, +}; + +static const struct i915_oa_reg flex_eu_config_sampler_1[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_sampler_1[] = { + { 0x9888, 0x18921400 }, + { 0x9888, 0x149500ab }, + { 0x9888, 0x18b21400 }, + { 0x9888, 0x14b500ab }, + { 0x9888, 0x18d21400 }, + { 0x9888, 0x14d500ab }, + { 0x9888, 0x0cdc8000 }, + { 0x9888, 0x0edc4000 }, + { 0x9888, 0x02dcc000 }, + { 0x9888, 0x04dcc000 }, + { 0x9888, 0x1abd00a0 }, + { 0x9888, 0x0abd8000 }, + { 0x9888, 0x0cd88000 }, + { 0x9888, 0x0ed84000 }, + { 0x9888, 0x04d88000 }, + { 0x9888, 0x1adb0050 }, + { 0x9888, 0x04db8000 }, + { 0x9888, 0x06db8000 }, + { 0x9888, 0x08db8000 }, + { 0x9888, 0x0adb4000 }, + { 0x9888, 0x109f02a0 }, + { 0x9888, 0x0c9fa000 }, + { 0x9888, 0x0e9f00aa }, + { 0x9888, 0x18b82500 }, + { 0x9888, 0x02b88000 }, + { 0x9888, 0x04b84000 }, + { 0x9888, 0x06b84000 }, + { 0x9888, 0x08b84000 }, + { 0x9888, 0x0ab84000 }, + { 0x9888, 0x0cb88000 }, + { 0x9888, 0x0cb98000 }, + { 0x9888, 0x0eb9a000 }, + { 0x9888, 0x00b98000 }, + { 0x9888, 0x02b9a000 }, + { 0x9888, 0x04b9a000 }, + { 0x9888, 0x06b92000 }, + { 0x9888, 0x1aba0200 }, + { 0x9888, 0x02ba8000 }, + { 0x9888, 0x0cba8000 }, + { 0x9888, 0x04908000 }, + { 0x9888, 0x04918000 }, + { 0x9888, 0x04927300 }, + { 0x9888, 0x10920000 }, + { 0x9888, 0x1893000a }, + { 0x9888, 0x0a934000 }, + { 0x9888, 0x0a946000 }, + { 0x9888, 0x0c959000 }, + { 0x9888, 0x0e950098 }, + { 0x9888, 0x10950000 }, + { 0x9888, 0x04b04000 }, + { 0x9888, 0x04b14000 }, + { 0x9888, 0x04b20073 }, + { 0x9888, 0x10b20000 }, + { 0x9888, 0x04b38000 }, + { 0x9888, 0x06b38000 }, + { 0x9888, 0x08b34000 }, + { 0x9888, 0x04b4c000 }, + { 0x9888, 0x02b59890 }, + { 0x9888, 0x10b50000 }, + { 0x9888, 0x06d04000 }, + { 0x9888, 0x06d14000 }, + { 0x9888, 0x06d20073 }, + { 0x9888, 0x10d20000 }, + { 0x9888, 0x18d30020 }, + { 0x9888, 0x02d38000 }, + { 0x9888, 0x0cd34000 }, + { 0x9888, 0x0ad48000 }, + { 0x9888, 0x04d42000 }, + { 0x9888, 0x0ed59000 }, + { 0x9888, 0x00d59800 }, + { 0x9888, 0x10d50000 }, + { 0x9888, 0x0f88000e }, + { 0x9888, 0x03888000 }, + { 0x9888, 0x05888000 }, + { 0x9888, 0x07888000 }, + { 0x9888, 0x09888000 }, + { 0x9888, 0x0b888000 }, + { 0x9888, 0x0d880400 }, + { 0x9888, 0x278b002a }, + { 0x9888, 0x238b5500 }, + { 0x9888, 0x258b000a }, + { 0x9888, 0x1b8c0015 }, + { 0x9888, 0x038c4000 }, + { 0x9888, 0x058c4000 }, + { 0x9888, 0x078c4000 }, + { 0x9888, 0x098c4000 }, + { 0x9888, 0x0b8c4000 }, + { 0x9888, 0x0d8c4000 }, + { 0x9888, 0x0d8d8000 }, + { 0x9888, 0x0f8da000 }, + { 0x9888, 0x018d8000 }, + { 0x9888, 0x038da000 }, + { 0x9888, 0x058da000 }, + { 0x9888, 0x078d2000 }, + { 0x9888, 0x2385002a }, + { 0x9888, 0x1f85aa00 }, + { 0x9888, 0x2185000a }, + { 0x9888, 0x1b830150 }, + { 0x9888, 0x03834000 }, + { 0x9888, 0x05834000 }, + { 0x9888, 0x07834000 }, + { 0x9888, 0x09834000 }, + { 0x9888, 0x0b834000 }, + { 0x9888, 0x0d834000 }, + { 0x9888, 0x0d848000 }, + { 0x9888, 0x0f84c000 }, + { 0x9888, 0x01848000 }, + { 0x9888, 0x0384c000 }, + { 0x9888, 0x0584c000 }, + { 0x9888, 0x07844000 }, + { 0x9888, 0x1d808000 }, + { 0x9888, 0x1f80c000 }, + { 0x9888, 0x11808000 }, + { 0x9888, 0x1380c000 }, + { 0x9888, 0x1580c000 }, + { 0x9888, 0x17804000 }, + { 0x9888, 0x53800000 }, + { 0x9888, 0x47801021 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x4d800000 }, + { 0x9888, 0x3f800c64 }, + { 0x9888, 0x4f800000 }, + { 0x9888, 0x41800c02 }, +}; + +static int select_sampler_1_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_sampler_1; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_sampler_1); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_sampler_1; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_sampler_1); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_sampler_1; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_sampler_1); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_sampler_2[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0x70800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x00800000 }, + { 0x2770, 0x0000c000 }, + { 0x2774, 0x0000e7ff }, + { 0x2778, 0x00003000 }, + { 0x277c, 0x0000f9ff }, + { 0x2780, 0x00000c00 }, + { 0x2784, 0x0000fe7f }, +}; + +static const struct i915_oa_reg flex_eu_config_sampler_2[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_sampler_2[] = { + { 0x9888, 0x18121400 }, + { 0x9888, 0x141500ab }, + { 0x9888, 0x18321400 }, + { 0x9888, 0x143500ab }, + { 0x9888, 0x18521400 }, + { 0x9888, 0x145500ab }, + { 0x9888, 0x0c5c8000 }, + { 0x9888, 0x0e5c4000 }, + { 0x9888, 0x025cc000 }, + { 0x9888, 0x045cc000 }, + { 0x9888, 0x1a3d00a0 }, + { 0x9888, 0x0a3d8000 }, + { 0x9888, 0x0c588000 }, + { 0x9888, 0x0e584000 }, + { 0x9888, 0x04588000 }, + { 0x9888, 0x1a5b0050 }, + { 0x9888, 0x045b8000 }, + { 0x9888, 0x065b8000 }, + { 0x9888, 0x085b8000 }, + { 0x9888, 0x0a5b4000 }, + { 0x9888, 0x101f02a0 }, + { 0x9888, 0x0c1fa000 }, + { 0x9888, 0x0e1f00aa }, + { 0x9888, 0x18382500 }, + { 0x9888, 0x02388000 }, + { 0x9888, 0x04384000 }, + { 0x9888, 0x06384000 }, + { 0x9888, 0x08384000 }, + { 0x9888, 0x0a384000 }, + { 0x9888, 0x0c388000 }, + { 0x9888, 0x0c398000 }, + { 0x9888, 0x0e39a000 }, + { 0x9888, 0x00398000 }, + { 0x9888, 0x0239a000 }, + { 0x9888, 0x0439a000 }, + { 0x9888, 0x06392000 }, + { 0x9888, 0x1a3a0200 }, + { 0x9888, 0x023a8000 }, + { 0x9888, 0x0c3a8000 }, + { 0x9888, 0x04108000 }, + { 0x9888, 0x04118000 }, + { 0x9888, 0x04127300 }, + { 0x9888, 0x10120000 }, + { 0x9888, 0x1813000a }, + { 0x9888, 0x0a134000 }, + { 0x9888, 0x0a146000 }, + { 0x9888, 0x0c159000 }, + { 0x9888, 0x0e150098 }, + { 0x9888, 0x10150000 }, + { 0x9888, 0x04304000 }, + { 0x9888, 0x04314000 }, + { 0x9888, 0x04320073 }, + { 0x9888, 0x10320000 }, + { 0x9888, 0x04338000 }, + { 0x9888, 0x06338000 }, + { 0x9888, 0x08334000 }, + { 0x9888, 0x0434c000 }, + { 0x9888, 0x02359890 }, + { 0x9888, 0x10350000 }, + { 0x9888, 0x06504000 }, + { 0x9888, 0x06514000 }, + { 0x9888, 0x06520073 }, + { 0x9888, 0x10520000 }, + { 0x9888, 0x18530020 }, + { 0x9888, 0x02538000 }, + { 0x9888, 0x0c534000 }, + { 0x9888, 0x0a548000 }, + { 0x9888, 0x04542000 }, + { 0x9888, 0x0e559000 }, + { 0x9888, 0x00559800 }, + { 0x9888, 0x10550000 }, + { 0x9888, 0x1b8aa000 }, + { 0x9888, 0x1d8a0002 }, + { 0x9888, 0x038a8000 }, + { 0x9888, 0x058a8000 }, + { 0x9888, 0x078a8000 }, + { 0x9888, 0x098a8000 }, + { 0x9888, 0x0b8a8000 }, + { 0x9888, 0x0d8a8000 }, + { 0x9888, 0x278b0015 }, + { 0x9888, 0x238b2a80 }, + { 0x9888, 0x258b0005 }, + { 0x9888, 0x2385002a }, + { 0x9888, 0x1f85aa00 }, + { 0x9888, 0x2185000a }, + { 0x9888, 0x1b830150 }, + { 0x9888, 0x03834000 }, + { 0x9888, 0x05834000 }, + { 0x9888, 0x07834000 }, + { 0x9888, 0x09834000 }, + { 0x9888, 0x0b834000 }, + { 0x9888, 0x0d834000 }, + { 0x9888, 0x0d848000 }, + { 0x9888, 0x0f84c000 }, + { 0x9888, 0x01848000 }, + { 0x9888, 0x0384c000 }, + { 0x9888, 0x0584c000 }, + { 0x9888, 0x07844000 }, + { 0x9888, 0x1d808000 }, + { 0x9888, 0x1f80c000 }, + { 0x9888, 0x11808000 }, + { 0x9888, 0x1380c000 }, + { 0x9888, 0x1580c000 }, + { 0x9888, 0x17804000 }, + { 0x9888, 0x53800000 }, + { 0x9888, 0x47801021 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x4d800000 }, + { 0x9888, 0x3f800c64 }, + { 0x9888, 0x4f800000 }, + { 0x9888, 0x41800c02 }, +}; + +static int select_sampler_2_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_sampler_2; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_sampler_2); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_sampler_2; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_sampler_2); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_sampler_2; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_sampler_2); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_tdl_1[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x30800000 }, + { 0x2770, 0x00000002 }, + { 0x2774, 0x0000fdff }, + { 0x2778, 0x00000000 }, + { 0x277c, 0x0000fe7f }, + { 0x2780, 0x00000002 }, + { 0x2784, 0x0000ffbf }, + { 0x2788, 0x00000000 }, + { 0x278c, 0x0000ffcf }, + { 0x2790, 0x00000002 }, + { 0x2794, 0x0000fff7 }, + { 0x2798, 0x00000000 }, + { 0x279c, 0x0000fff9 }, +}; + +static const struct i915_oa_reg flex_eu_config_tdl_1[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_tdl_1[] = { + { 0x9888, 0x16154d60 }, + { 0x9888, 0x16352e60 }, + { 0x9888, 0x16554d60 }, + { 0x9888, 0x16950000 }, + { 0x9888, 0x16b50000 }, + { 0x9888, 0x16d50000 }, + { 0x9888, 0x005c8000 }, + { 0x9888, 0x045cc000 }, + { 0x9888, 0x065c4000 }, + { 0x9888, 0x083d8000 }, + { 0x9888, 0x0a3d8000 }, + { 0x9888, 0x0458c000 }, + { 0x9888, 0x025b8000 }, + { 0x9888, 0x085b4000 }, + { 0x9888, 0x0a5b4000 }, + { 0x9888, 0x0c5b8000 }, + { 0x9888, 0x0c1fa000 }, + { 0x9888, 0x0e1f00aa }, + { 0x9888, 0x02384000 }, + { 0x9888, 0x04388000 }, + { 0x9888, 0x06388000 }, + { 0x9888, 0x08384000 }, + { 0x9888, 0x0a384000 }, + { 0x9888, 0x0c384000 }, + { 0x9888, 0x00398000 }, + { 0x9888, 0x0239a000 }, + { 0x9888, 0x0439a000 }, + { 0x9888, 0x06392000 }, + { 0x9888, 0x043a8000 }, + { 0x9888, 0x063a8000 }, + { 0x9888, 0x08138000 }, + { 0x9888, 0x0a138000 }, + { 0x9888, 0x06143000 }, + { 0x9888, 0x0415cfc7 }, + { 0x9888, 0x10150000 }, + { 0x9888, 0x02338000 }, + { 0x9888, 0x0c338000 }, + { 0x9888, 0x04342000 }, + { 0x9888, 0x06344000 }, + { 0x9888, 0x0035c700 }, + { 0x9888, 0x063500cf }, + { 0x9888, 0x10350000 }, + { 0x9888, 0x04538000 }, + { 0x9888, 0x06538000 }, + { 0x9888, 0x0454c000 }, + { 0x9888, 0x0255cfc7 }, + { 0x9888, 0x10550000 }, + { 0x9888, 0x06dc8000 }, + { 0x9888, 0x08dc4000 }, + { 0x9888, 0x0cdcc000 }, + { 0x9888, 0x0edcc000 }, + { 0x9888, 0x1abd00a8 }, + { 0x9888, 0x0cd8c000 }, + { 0x9888, 0x0ed84000 }, + { 0x9888, 0x0edb8000 }, + { 0x9888, 0x18db0800 }, + { 0x9888, 0x1adb0254 }, + { 0x9888, 0x0e9faa00 }, + { 0x9888, 0x109f02aa }, + { 0x9888, 0x0eb84000 }, + { 0x9888, 0x16b84000 }, + { 0x9888, 0x18b8156a }, + { 0x9888, 0x06b98000 }, + { 0x9888, 0x08b9a000 }, + { 0x9888, 0x0ab9a000 }, + { 0x9888, 0x0cb9a000 }, + { 0x9888, 0x0eb9a000 }, + { 0x9888, 0x18baa000 }, + { 0x9888, 0x1aba0002 }, + { 0x9888, 0x16934000 }, + { 0x9888, 0x1893000a }, + { 0x9888, 0x0a947000 }, + { 0x9888, 0x0c95c5c1 }, + { 0x9888, 0x0e9500c3 }, + { 0x9888, 0x10950000 }, + { 0x9888, 0x0eb38000 }, + { 0x9888, 0x16b30040 }, + { 0x9888, 0x18b30020 }, + { 0x9888, 0x06b48000 }, + { 0x9888, 0x08b41000 }, + { 0x9888, 0x0ab48000 }, + { 0x9888, 0x06b5c500 }, + { 0x9888, 0x08b500c3 }, + { 0x9888, 0x0eb5c100 }, + { 0x9888, 0x10b50000 }, + { 0x9888, 0x16d31500 }, + { 0x9888, 0x08d4e000 }, + { 0x9888, 0x08d5c100 }, + { 0x9888, 0x0ad5c3c5 }, + { 0x9888, 0x10d50000 }, + { 0x9888, 0x0d88f800 }, + { 0x9888, 0x0f88000f }, + { 0x9888, 0x038a8000 }, + { 0x9888, 0x058a8000 }, + { 0x9888, 0x078a8000 }, + { 0x9888, 0x098a8000 }, + { 0x9888, 0x0b8a8000 }, + { 0x9888, 0x0d8a8000 }, + { 0x9888, 0x258baaa5 }, + { 0x9888, 0x278b002a }, + { 0x9888, 0x238b2a80 }, + { 0x9888, 0x0f8c4000 }, + { 0x9888, 0x178c2000 }, + { 0x9888, 0x198c5500 }, + { 0x9888, 0x1b8c0015 }, + { 0x9888, 0x078d8000 }, + { 0x9888, 0x098da000 }, + { 0x9888, 0x0b8da000 }, + { 0x9888, 0x0d8da000 }, + { 0x9888, 0x0f8da000 }, + { 0x9888, 0x2185aaaa }, + { 0x9888, 0x2385002a }, + { 0x9888, 0x1f85aa00 }, + { 0x9888, 0x0f834000 }, + { 0x9888, 0x19835400 }, + { 0x9888, 0x1b830155 }, + { 0x9888, 0x03834000 }, + { 0x9888, 0x05834000 }, + { 0x9888, 0x07834000 }, + { 0x9888, 0x09834000 }, + { 0x9888, 0x0b834000 }, + { 0x9888, 0x0d834000 }, + { 0x9888, 0x0784c000 }, + { 0x9888, 0x0984c000 }, + { 0x9888, 0x0b84c000 }, + { 0x9888, 0x0d84c000 }, + { 0x9888, 0x0f84c000 }, + { 0x9888, 0x01848000 }, + { 0x9888, 0x0384c000 }, + { 0x9888, 0x0584c000 }, + { 0x9888, 0x1780c000 }, + { 0x9888, 0x1980c000 }, + { 0x9888, 0x1b80c000 }, + { 0x9888, 0x1d80c000 }, + { 0x9888, 0x1f80c000 }, + { 0x9888, 0x11808000 }, + { 0x9888, 0x1380c000 }, + { 0x9888, 0x1580c000 }, + { 0x9888, 0x4f800000 }, + { 0x9888, 0x43800c42 }, + { 0x9888, 0x51800000 }, + { 0x9888, 0x45800063 }, + { 0x9888, 0x53800000 }, + { 0x9888, 0x47800800 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x4d800000 }, + { 0x9888, 0x3f8014a4 }, + { 0x9888, 0x41801042 }, +}; + +static int select_tdl_1_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_tdl_1; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_tdl_1); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_tdl_1; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_tdl_1); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_tdl_1; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_tdl_1); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_tdl_2[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x30800000 }, + { 0x2770, 0x00000002 }, + { 0x2774, 0x0000fdff }, + { 0x2778, 0x00000000 }, + { 0x277c, 0x0000fe7f }, + { 0x2780, 0x00000000 }, + { 0x2784, 0x0000ff9f }, + { 0x2788, 0x00000000 }, + { 0x278c, 0x0000ffe7 }, + { 0x2790, 0x00000002 }, + { 0x2794, 0x0000fffb }, + { 0x2798, 0x00000002 }, + { 0x279c, 0x0000fffd }, +}; + +static const struct i915_oa_reg flex_eu_config_tdl_2[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_tdl_2[] = { + { 0x9888, 0x16150000 }, + { 0x9888, 0x16350000 }, + { 0x9888, 0x16550000 }, + { 0x9888, 0x16952e60 }, + { 0x9888, 0x16b54d60 }, + { 0x9888, 0x16d52e60 }, + { 0x9888, 0x065c8000 }, + { 0x9888, 0x085cc000 }, + { 0x9888, 0x0a5cc000 }, + { 0x9888, 0x0c5c4000 }, + { 0x9888, 0x0e3d8000 }, + { 0x9888, 0x183da000 }, + { 0x9888, 0x06588000 }, + { 0x9888, 0x08588000 }, + { 0x9888, 0x0a584000 }, + { 0x9888, 0x0e5b4000 }, + { 0x9888, 0x185b5800 }, + { 0x9888, 0x1a5b000a }, + { 0x9888, 0x0e1faa00 }, + { 0x9888, 0x101f02aa }, + { 0x9888, 0x0e384000 }, + { 0x9888, 0x16384000 }, + { 0x9888, 0x18382a55 }, + { 0x9888, 0x06398000 }, + { 0x9888, 0x0839a000 }, + { 0x9888, 0x0a39a000 }, + { 0x9888, 0x0c39a000 }, + { 0x9888, 0x0e39a000 }, + { 0x9888, 0x1a3a02a0 }, + { 0x9888, 0x0e138000 }, + { 0x9888, 0x16130500 }, + { 0x9888, 0x06148000 }, + { 0x9888, 0x08146000 }, + { 0x9888, 0x0615c100 }, + { 0x9888, 0x0815c500 }, + { 0x9888, 0x0a1500c3 }, + { 0x9888, 0x10150000 }, + { 0x9888, 0x16335040 }, + { 0x9888, 0x08349000 }, + { 0x9888, 0x0a341000 }, + { 0x9888, 0x083500c1 }, + { 0x9888, 0x0a35c500 }, + { 0x9888, 0x0c3500c3 }, + { 0x9888, 0x10350000 }, + { 0x9888, 0x1853002a }, + { 0x9888, 0x0a54e000 }, + { 0x9888, 0x0c55c500 }, + { 0x9888, 0x0e55c1c3 }, + { 0x9888, 0x10550000 }, + { 0x9888, 0x00dc8000 }, + { 0x9888, 0x02dcc000 }, + { 0x9888, 0x04dc4000 }, + { 0x9888, 0x04bd8000 }, + { 0x9888, 0x06bd8000 }, + { 0x9888, 0x02d8c000 }, + { 0x9888, 0x02db8000 }, + { 0x9888, 0x04db4000 }, + { 0x9888, 0x06db4000 }, + { 0x9888, 0x08db8000 }, + { 0x9888, 0x0c9fa000 }, + { 0x9888, 0x0e9f00aa }, + { 0x9888, 0x02b84000 }, + { 0x9888, 0x04b84000 }, + { 0x9888, 0x06b84000 }, + { 0x9888, 0x08b84000 }, + { 0x9888, 0x0ab88000 }, + { 0x9888, 0x0cb88000 }, + { 0x9888, 0x00b98000 }, + { 0x9888, 0x02b9a000 }, + { 0x9888, 0x04b9a000 }, + { 0x9888, 0x06b92000 }, + { 0x9888, 0x0aba8000 }, + { 0x9888, 0x0cba8000 }, + { 0x9888, 0x04938000 }, + { 0x9888, 0x06938000 }, + { 0x9888, 0x0494c000 }, + { 0x9888, 0x0295cfc7 }, + { 0x9888, 0x10950000 }, + { 0x9888, 0x02b38000 }, + { 0x9888, 0x08b38000 }, + { 0x9888, 0x04b42000 }, + { 0x9888, 0x06b41000 }, + { 0x9888, 0x00b5c700 }, + { 0x9888, 0x04b500cf }, + { 0x9888, 0x10b50000 }, + { 0x9888, 0x0ad38000 }, + { 0x9888, 0x0cd38000 }, + { 0x9888, 0x06d46000 }, + { 0x9888, 0x04d5c700 }, + { 0x9888, 0x06d500cf }, + { 0x9888, 0x10d50000 }, + { 0x9888, 0x03888000 }, + { 0x9888, 0x05888000 }, + { 0x9888, 0x07888000 }, + { 0x9888, 0x09888000 }, + { 0x9888, 0x0b888000 }, + { 0x9888, 0x0d880400 }, + { 0x9888, 0x0f8a8000 }, + { 0x9888, 0x198a8000 }, + { 0x9888, 0x1b8aaaa0 }, + { 0x9888, 0x1d8a0002 }, + { 0x9888, 0x258b555a }, + { 0x9888, 0x278b0015 }, + { 0x9888, 0x238b5500 }, + { 0x9888, 0x038c4000 }, + { 0x9888, 0x058c4000 }, + { 0x9888, 0x078c4000 }, + { 0x9888, 0x098c4000 }, + { 0x9888, 0x0b8c4000 }, + { 0x9888, 0x0d8c4000 }, + { 0x9888, 0x018d8000 }, + { 0x9888, 0x038da000 }, + { 0x9888, 0x058da000 }, + { 0x9888, 0x078d2000 }, + { 0x9888, 0x2185aaaa }, + { 0x9888, 0x2385002a }, + { 0x9888, 0x1f85aa00 }, + { 0x9888, 0x0f834000 }, + { 0x9888, 0x19835400 }, + { 0x9888, 0x1b830155 }, + { 0x9888, 0x03834000 }, + { 0x9888, 0x05834000 }, + { 0x9888, 0x07834000 }, + { 0x9888, 0x09834000 }, + { 0x9888, 0x0b834000 }, + { 0x9888, 0x0d834000 }, + { 0x9888, 0x0784c000 }, + { 0x9888, 0x0984c000 }, + { 0x9888, 0x0b84c000 }, + { 0x9888, 0x0d84c000 }, + { 0x9888, 0x0f84c000 }, + { 0x9888, 0x01848000 }, + { 0x9888, 0x0384c000 }, + { 0x9888, 0x0584c000 }, + { 0x9888, 0x1780c000 }, + { 0x9888, 0x1980c000 }, + { 0x9888, 0x1b80c000 }, + { 0x9888, 0x1d80c000 }, + { 0x9888, 0x1f80c000 }, + { 0x9888, 0x11808000 }, + { 0x9888, 0x1380c000 }, + { 0x9888, 0x1580c000 }, + { 0x9888, 0x4f800000 }, + { 0x9888, 0x43800882 }, + { 0x9888, 0x51800000 }, + { 0x9888, 0x45801082 }, + { 0x9888, 0x53800000 }, + { 0x9888, 0x478014a5 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x4d800000 }, + { 0x9888, 0x3f800002 }, + { 0x9888, 0x41800c62 }, +}; + +static int select_tdl_2_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_tdl_2; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_tdl_2); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_tdl_2; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_tdl_2); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_tdl_2; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_tdl_2); + + return 0; +} + int i915_oa_select_metric_set_bdw(struct drm_i915_private *dev_priv) { dev_priv->perf.oa.mux_regs = NULL; @@ -306,6 +3613,42 @@ int i915_oa_select_metric_set_bdw(struct drm_i915_private *dev_priv) switch (dev_priv->perf.oa.metrics_set) { case METRIC_SET_ID_RENDER_BASIC: return select_render_basic_config(dev_priv); + case METRIC_SET_ID_COMPUTE_BASIC: + return select_compute_basic_config(dev_priv); + case METRIC_SET_ID_RENDER_PIPE_PROFILE: + return select_render_pipe_profile_config(dev_priv); + case METRIC_SET_ID_MEMORY_READS: + return select_memory_reads_config(dev_priv); + case METRIC_SET_ID_MEMORY_WRITES: + return select_memory_writes_config(dev_priv); + case METRIC_SET_ID_COMPUTE_EXTENDED: + return select_compute_extended_config(dev_priv); + case METRIC_SET_ID_COMPUTE_L3_CACHE: + return select_compute_l3_cache_config(dev_priv); + case METRIC_SET_ID_DATA_PORT_READS_COALESCING: + return select_data_port_reads_coalescing_config(dev_priv); + case METRIC_SET_ID_DATA_PORT_WRITES_COALESCING: + return select_data_port_writes_coalescing_config(dev_priv); + case METRIC_SET_ID_HDC_AND_SF: + return select_hdc_and_sf_config(dev_priv); + case METRIC_SET_ID_L3_1: + return select_l3_1_config(dev_priv); + case METRIC_SET_ID_L3_2: + return select_l3_2_config(dev_priv); + case METRIC_SET_ID_L3_3: + return select_l3_3_config(dev_priv); + case METRIC_SET_ID_L3_4: + return select_l3_4_config(dev_priv); + case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: + return select_rasterizer_and_pixel_backend_config(dev_priv); + case METRIC_SET_ID_SAMPLER_1: + return select_sampler_1_config(dev_priv); + case METRIC_SET_ID_SAMPLER_2: + return select_sampler_2_config(dev_priv); + case METRIC_SET_ID_TDL_1: + return select_tdl_1_config(dev_priv); + case METRIC_SET_ID_TDL_2: + return select_tdl_2_config(dev_priv); default: return -ENODEV; } @@ -333,6 +3676,402 @@ static struct attribute_group group_render_basic = { .attrs = attrs_render_basic, }; +static ssize_t +show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); +} + +static struct device_attribute dev_attr_compute_basic_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_compute_basic_id, + .store = NULL, +}; + +static struct attribute *attrs_compute_basic[] = { + &dev_attr_compute_basic_id.attr, + NULL, +}; + +static struct attribute_group group_compute_basic = { + .name = "35fbc9b2-a891-40a6-a38d-022bb7057552", + .attrs = attrs_compute_basic, +}; + +static ssize_t +show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); +} + +static struct device_attribute dev_attr_render_pipe_profile_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_render_pipe_profile_id, + .store = NULL, +}; + +static struct attribute *attrs_render_pipe_profile[] = { + &dev_attr_render_pipe_profile_id.attr, + NULL, +}; + +static struct attribute_group group_render_pipe_profile = { + .name = "233d0544-fff7-4281-8291-e02f222aff72", + .attrs = attrs_render_pipe_profile, +}; + +static ssize_t +show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); +} + +static struct device_attribute dev_attr_memory_reads_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_memory_reads_id, + .store = NULL, +}; + +static struct attribute *attrs_memory_reads[] = { + &dev_attr_memory_reads_id.attr, + NULL, +}; + +static struct attribute_group group_memory_reads = { + .name = "2b255d48-2117-4fef-a8f7-f151e1d25a2c", + .attrs = attrs_memory_reads, +}; + +static ssize_t +show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); +} + +static struct device_attribute dev_attr_memory_writes_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_memory_writes_id, + .store = NULL, +}; + +static struct attribute *attrs_memory_writes[] = { + &dev_attr_memory_writes_id.attr, + NULL, +}; + +static struct attribute_group group_memory_writes = { + .name = "f7fd3220-b466-4a4d-9f98-b0caf3f2394c", + .attrs = attrs_memory_writes, +}; + +static ssize_t +show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); +} + +static struct device_attribute dev_attr_compute_extended_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_compute_extended_id, + .store = NULL, +}; + +static struct attribute *attrs_compute_extended[] = { + &dev_attr_compute_extended_id.attr, + NULL, +}; + +static struct attribute_group group_compute_extended = { + .name = "e99ccaca-821c-4df9-97a7-96bdb7204e43", + .attrs = attrs_compute_extended, +}; + +static ssize_t +show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE); +} + +static struct device_attribute dev_attr_compute_l3_cache_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_compute_l3_cache_id, + .store = NULL, +}; + +static struct attribute *attrs_compute_l3_cache[] = { + &dev_attr_compute_l3_cache_id.attr, + NULL, +}; + +static struct attribute_group group_compute_l3_cache = { + .name = "27a364dc-8225-4ecb-b607-d6f1925598d9", + .attrs = attrs_compute_l3_cache, +}; + +static ssize_t +show_data_port_reads_coalescing_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_DATA_PORT_READS_COALESCING); +} + +static struct device_attribute dev_attr_data_port_reads_coalescing_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_data_port_reads_coalescing_id, + .store = NULL, +}; + +static struct attribute *attrs_data_port_reads_coalescing[] = { + &dev_attr_data_port_reads_coalescing_id.attr, + NULL, +}; + +static struct attribute_group group_data_port_reads_coalescing = { + .name = "857fc630-2f09-4804-85f1-084adfadd5ab", + .attrs = attrs_data_port_reads_coalescing, +}; + +static ssize_t +show_data_port_writes_coalescing_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_DATA_PORT_WRITES_COALESCING); +} + +static struct device_attribute dev_attr_data_port_writes_coalescing_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_data_port_writes_coalescing_id, + .store = NULL, +}; + +static struct attribute *attrs_data_port_writes_coalescing[] = { + &dev_attr_data_port_writes_coalescing_id.attr, + NULL, +}; + +static struct attribute_group group_data_port_writes_coalescing = { + .name = "343ebc99-4a55-414c-8c17-d8e259cf5e20", + .attrs = attrs_data_port_writes_coalescing, +}; + +static ssize_t +show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); +} + +static struct device_attribute dev_attr_hdc_and_sf_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_hdc_and_sf_id, + .store = NULL, +}; + +static struct attribute *attrs_hdc_and_sf[] = { + &dev_attr_hdc_and_sf_id.attr, + NULL, +}; + +static struct attribute_group group_hdc_and_sf = { + .name = "2cf0c064-68df-4fac-9b3f-57f51ca8a069", + .attrs = attrs_hdc_and_sf, +}; + +static ssize_t +show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); +} + +static struct device_attribute dev_attr_l3_1_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_l3_1_id, + .store = NULL, +}; + +static struct attribute *attrs_l3_1[] = { + &dev_attr_l3_1_id.attr, + NULL, +}; + +static struct attribute_group group_l3_1 = { + .name = "78a87ff9-543a-49ce-95ea-26d86071ea93", + .attrs = attrs_l3_1, +}; + +static ssize_t +show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2); +} + +static struct device_attribute dev_attr_l3_2_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_l3_2_id, + .store = NULL, +}; + +static struct attribute *attrs_l3_2[] = { + &dev_attr_l3_2_id.attr, + NULL, +}; + +static struct attribute_group group_l3_2 = { + .name = "9f2cece5-7bfe-4320-ad66-8c7cc526bec5", + .attrs = attrs_l3_2, +}; + +static ssize_t +show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3); +} + +static struct device_attribute dev_attr_l3_3_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_l3_3_id, + .store = NULL, +}; + +static struct attribute *attrs_l3_3[] = { + &dev_attr_l3_3_id.attr, + NULL, +}; + +static struct attribute_group group_l3_3 = { + .name = "d890ef38-d309-47e4-b8b5-aa779bb19ab0", + .attrs = attrs_l3_3, +}; + +static ssize_t +show_l3_4_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_L3_4); +} + +static struct device_attribute dev_attr_l3_4_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_l3_4_id, + .store = NULL, +}; + +static struct attribute *attrs_l3_4[] = { + &dev_attr_l3_4_id.attr, + NULL, +}; + +static struct attribute_group group_l3_4 = { + .name = "5fdff4a6-9dc8-45e1-bfda-ef54869fbdd4", + .attrs = attrs_l3_4, +}; + +static ssize_t +show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); +} + +static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_rasterizer_and_pixel_backend_id, + .store = NULL, +}; + +static struct attribute *attrs_rasterizer_and_pixel_backend[] = { + &dev_attr_rasterizer_and_pixel_backend_id.attr, + NULL, +}; + +static struct attribute_group group_rasterizer_and_pixel_backend = { + .name = "2c0e45e1-7e2c-4a14-ae00-0b7ec868b8aa", + .attrs = attrs_rasterizer_and_pixel_backend, +}; + +static ssize_t +show_sampler_1_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_1); +} + +static struct device_attribute dev_attr_sampler_1_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_sampler_1_id, + .store = NULL, +}; + +static struct attribute *attrs_sampler_1[] = { + &dev_attr_sampler_1_id.attr, + NULL, +}; + +static struct attribute_group group_sampler_1 = { + .name = "71148d78-baf5-474f-878a-e23158d0265d", + .attrs = attrs_sampler_1, +}; + +static ssize_t +show_sampler_2_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_2); +} + +static struct device_attribute dev_attr_sampler_2_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_sampler_2_id, + .store = NULL, +}; + +static struct attribute *attrs_sampler_2[] = { + &dev_attr_sampler_2_id.attr, + NULL, +}; + +static struct attribute_group group_sampler_2 = { + .name = "b996a2b7-c59c-492d-877a-8cd54fd6df84", + .attrs = attrs_sampler_2, +}; + +static ssize_t +show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); +} + +static struct device_attribute dev_attr_tdl_1_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_tdl_1_id, + .store = NULL, +}; + +static struct attribute *attrs_tdl_1[] = { + &dev_attr_tdl_1_id.attr, + NULL, +}; + +static struct attribute_group group_tdl_1 = { + .name = "eb2fecba-b431-42e7-8261-fe9429a6e67a", + .attrs = attrs_tdl_1, +}; + +static ssize_t +show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); +} + +static struct device_attribute dev_attr_tdl_2_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_tdl_2_id, + .store = NULL, +}; + +static struct attribute *attrs_tdl_2[] = { + &dev_attr_tdl_2_id.attr, + NULL, +}; + +static struct attribute_group group_tdl_2 = { + .name = "60749470-a648-4a4b-9f10-dbfe1e36e44d", + .attrs = attrs_tdl_2, +}; + int i915_perf_init_sysfs_bdw(struct drm_i915_private *dev_priv) { @@ -341,9 +4080,99 @@ i915_perf_init_sysfs_bdw(struct drm_i915_private *dev_priv) ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); if (ret) goto error_render_basic; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); + if (ret) + goto error_compute_basic; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); + if (ret) + goto error_render_pipe_profile; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); + if (ret) + goto error_memory_reads; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); + if (ret) + goto error_memory_writes; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); + if (ret) + goto error_compute_extended; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); + if (ret) + goto error_compute_l3_cache; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_data_port_reads_coalescing); + if (ret) + goto error_data_port_reads_coalescing; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_data_port_writes_coalescing); + if (ret) + goto error_data_port_writes_coalescing; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); + if (ret) + goto error_hdc_and_sf; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); + if (ret) + goto error_l3_1; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2); + if (ret) + goto error_l3_2; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3); + if (ret) + goto error_l3_3; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_4); + if (ret) + goto error_l3_4; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); + if (ret) + goto error_rasterizer_and_pixel_backend; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_1); + if (ret) + goto error_sampler_1; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_2); + if (ret) + goto error_sampler_2; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); + if (ret) + goto error_tdl_1; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); + if (ret) + goto error_tdl_2; return 0; +error_tdl_2: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); +error_tdl_1: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2); +error_sampler_2: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1); +error_sampler_1: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); +error_rasterizer_and_pixel_backend: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4); +error_l3_4: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); +error_l3_3: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); +error_l3_2: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); +error_l3_1: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); +error_hdc_and_sf: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_writes_coalescing); +error_data_port_writes_coalescing: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_reads_coalescing); +error_data_port_reads_coalescing: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); +error_compute_l3_cache: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); +error_compute_extended: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); +error_memory_writes: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); +error_memory_reads: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); +error_render_pipe_profile: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); +error_compute_basic: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); error_render_basic: return ret; } @@ -352,4 +4181,22 @@ void i915_perf_deinit_sysfs_bdw(struct drm_i915_private *dev_priv) { sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_reads_coalescing); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_data_port_writes_coalescing); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); } diff --git a/drivers/gpu/drm/i915/i915_oa_chv.c b/drivers/gpu/drm/i915/i915_oa_chv.c index 703b61c681275d..c8828599b65522 100644 --- a/drivers/gpu/drm/i915/i915_oa_chv.c +++ b/drivers/gpu/drm/i915/i915_oa_chv.c @@ -30,9 +30,21 @@ enum metric_set_id { METRIC_SET_ID_RENDER_BASIC = 1, + METRIC_SET_ID_COMPUTE_BASIC, + METRIC_SET_ID_RENDER_PIPE_PROFILE, + METRIC_SET_ID_HDC_AND_SF, + METRIC_SET_ID_L3_1, + METRIC_SET_ID_L3_2, + METRIC_SET_ID_L3_3, + METRIC_SET_ID_L3_4, + METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, + METRIC_SET_ID_SAMPLER_1, + METRIC_SET_ID_SAMPLER_2, + METRIC_SET_ID_TDL_1, + METRIC_SET_ID_TDL_2, }; -int i915_oa_n_builtin_metric_sets_chv = 1; +int i915_oa_n_builtin_metric_sets_chv = 13; static const struct i915_oa_reg b_counter_config_render_basic[] = { { 0x2710, 0x00000000 }, @@ -135,6 +147,1851 @@ static int select_render_basic_config(struct drm_i915_private *dev_priv) return 0; } +static const struct i915_oa_reg b_counter_config_compute_basic[] = { + { 0x2710, 0x00000000 }, + { 0x2714, 0x00800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x00800000 }, +}; + +static const struct i915_oa_reg flex_eu_config_compute_basic[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00000003 }, + { 0xE658, 0x00002001 }, + { 0xE758, 0x00778008 }, + { 0xE45c, 0x00088078 }, + { 0xE55c, 0x00808708 }, + { 0xE65c, 0x00a08908 }, +}; + +static const struct i915_oa_reg mux_config_compute_basic[] = { + { 0x9888, 0x59800000 }, + { 0x9888, 0x59800001 }, + { 0x9888, 0x2E5800E0 }, + { 0x9888, 0x2E3800E0 }, + { 0x9888, 0x3580024F }, + { 0x9888, 0x3D800140 }, + { 0x9888, 0x08580042 }, + { 0x9888, 0x0C580040 }, + { 0x9888, 0x1058004C }, + { 0x9888, 0x1458004B }, + { 0x9888, 0x04580000 }, + { 0x9888, 0x00580000 }, + { 0x9888, 0x00195555 }, + { 0x9888, 0x06380042 }, + { 0x9888, 0x0A380040 }, + { 0x9888, 0x0E38004C }, + { 0x9888, 0x1238004B }, + { 0x9888, 0x04380000 }, + { 0x9888, 0x00384444 }, + { 0x9888, 0x003A5555 }, + { 0x9888, 0x018BFFFF }, + { 0x9888, 0x01845555 }, + { 0x9888, 0x17800074 }, + { 0x9888, 0x1980007D }, + { 0x9888, 0x1B80007C }, + { 0x9888, 0x1D8000B6 }, + { 0x9888, 0x1F8000B7 }, + { 0x9888, 0x05800000 }, + { 0x9888, 0x03800000 }, + { 0x9888, 0x418000AA }, + { 0x9888, 0x438000AA }, + { 0x9888, 0x45800000 }, + { 0x9888, 0x47800000 }, + { 0x9888, 0x4980012A }, + { 0x9888, 0x4B80012A }, + { 0x9888, 0x4D80012A }, + { 0x9888, 0x4F80012A }, + { 0x9888, 0x518001CE }, + { 0x9888, 0x538001CE }, + { 0x9888, 0x5580000E }, + { 0x9888, 0x59800000 }, +}; + +static int select_compute_basic_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_compute_basic; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_compute_basic); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_compute_basic; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_compute_basic); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_compute_basic; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_compute_basic); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { + { 0x2724, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2710, 0x00000000 }, + { 0x2770, 0x0007ffea }, + { 0x2774, 0x00007ffc }, + { 0x2778, 0x0007affa }, + { 0x277c, 0x0000f5fd }, + { 0x2780, 0x00079ffa }, + { 0x2784, 0x0000f3fb }, + { 0x2788, 0x0007bf7a }, + { 0x278c, 0x0000f7e7 }, + { 0x2790, 0x0007fefa }, + { 0x2794, 0x0000f7cf }, + { 0x2798, 0x00077ffa }, + { 0x279c, 0x0000efdf }, + { 0x27a0, 0x0006fffa }, + { 0x27a4, 0x0000cfbf }, + { 0x27a8, 0x0003fffa }, + { 0x27ac, 0x00005f7f }, +}; + +static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00015014 }, + { 0xE658, 0x00025024 }, + { 0xE758, 0x00035034 }, + { 0xE45c, 0x00045044 }, + { 0xE55c, 0x00055054 }, + { 0xE65c, 0x00065064 }, +}; + +static const struct i915_oa_reg mux_config_render_pipe_profile[] = { + { 0x9888, 0x59800000 }, + { 0x9888, 0x59800001 }, + { 0x9888, 0x261E0000 }, + { 0x9888, 0x281F000F }, + { 0x9888, 0x2817001A }, + { 0x9888, 0x2791001F }, + { 0x9888, 0x27880019 }, + { 0x9888, 0x2D890000 }, + { 0x9888, 0x278A0007 }, + { 0x9888, 0x298D001F }, + { 0x9888, 0x278E0020 }, + { 0x9888, 0x2B8F0012 }, + { 0x9888, 0x29900000 }, + { 0x9888, 0x00184000 }, + { 0x9888, 0x02181000 }, + { 0x9888, 0x02194000 }, + { 0x9888, 0x141E0002 }, + { 0x9888, 0x041E0000 }, + { 0x9888, 0x001E0000 }, + { 0x9888, 0x221F0015 }, + { 0x9888, 0x041F0000 }, + { 0x9888, 0x001F4000 }, + { 0x9888, 0x021F0000 }, + { 0x9888, 0x023A8000 }, + { 0x9888, 0x0213C000 }, + { 0x9888, 0x02164000 }, + { 0x9888, 0x24170012 }, + { 0x9888, 0x04170000 }, + { 0x9888, 0x07910005 }, + { 0x9888, 0x05910000 }, + { 0x9888, 0x01911500 }, + { 0x9888, 0x03910501 }, + { 0x9888, 0x0D880002 }, + { 0x9888, 0x1D880003 }, + { 0x9888, 0x05880000 }, + { 0x9888, 0x0B890032 }, + { 0x9888, 0x1B890031 }, + { 0x9888, 0x05890000 }, + { 0x9888, 0x01890040 }, + { 0x9888, 0x03890040 }, + { 0x9888, 0x098A0000 }, + { 0x9888, 0x198A0004 }, + { 0x9888, 0x058A0000 }, + { 0x9888, 0x018A8050 }, + { 0x9888, 0x038A2050 }, + { 0x9888, 0x018B95A9 }, + { 0x9888, 0x038BE5A9 }, + { 0x9888, 0x018C1500 }, + { 0x9888, 0x038C0501 }, + { 0x9888, 0x178D0015 }, + { 0x9888, 0x058D0000 }, + { 0x9888, 0x138E0004 }, + { 0x9888, 0x218E000C }, + { 0x9888, 0x058E0000 }, + { 0x9888, 0x018E0500 }, + { 0x9888, 0x038E0101 }, + { 0x9888, 0x0F8F0027 }, + { 0x9888, 0x058F0000 }, + { 0x9888, 0x018F0000 }, + { 0x9888, 0x038F0001 }, + { 0x9888, 0x11900013 }, + { 0x9888, 0x1F900017 }, + { 0x9888, 0x05900000 }, + { 0x9888, 0x01900100 }, + { 0x9888, 0x03900001 }, + { 0x9888, 0x01845555 }, + { 0x9888, 0x03845555 }, + { 0x9888, 0x418000AA }, + { 0x9888, 0x438000AA }, + { 0x9888, 0x458000AA }, + { 0x9888, 0x478000AA }, + { 0x9888, 0x4980018C }, + { 0x9888, 0x4B80014B }, + { 0x9888, 0x4D800128 }, + { 0x9888, 0x4F80012A }, + { 0x9888, 0x51800187 }, + { 0x9888, 0x5380014B }, + { 0x9888, 0x55800149 }, + { 0x9888, 0x5780010A }, + { 0x9888, 0x59800000 }, +}; + +static int select_render_pipe_profile_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_render_pipe_profile; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_render_pipe_profile); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_render_pipe_profile; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_render_pipe_profile); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_render_pipe_profile; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_render_pipe_profile); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0x10800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x00800000 }, + { 0x2770, 0x00000002 }, + { 0x2774, 0x0000fff7 }, +}; + +static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_hdc_and_sf[] = { + { 0x9888, 0x105c0232 }, + { 0x9888, 0x10580232 }, + { 0x9888, 0x10380232 }, + { 0x9888, 0x10dc0232 }, + { 0x9888, 0x10d80232 }, + { 0x9888, 0x10b80232 }, + { 0x9888, 0x118e4400 }, + { 0x9888, 0x025c6080 }, + { 0x9888, 0x045c004b }, + { 0x9888, 0x005c8000 }, + { 0x9888, 0x00582080 }, + { 0x9888, 0x0258004b }, + { 0x9888, 0x025b4000 }, + { 0x9888, 0x045b4000 }, + { 0x9888, 0x0c1fa000 }, + { 0x9888, 0x0e1f00aa }, + { 0x9888, 0x04386080 }, + { 0x9888, 0x0638404b }, + { 0x9888, 0x02384000 }, + { 0x9888, 0x08384000 }, + { 0x9888, 0x0a380000 }, + { 0x9888, 0x0c380000 }, + { 0x9888, 0x00398000 }, + { 0x9888, 0x0239a000 }, + { 0x9888, 0x0439a000 }, + { 0x9888, 0x06392000 }, + { 0x9888, 0x0cdc25c1 }, + { 0x9888, 0x0adcc000 }, + { 0x9888, 0x0ad825c1 }, + { 0x9888, 0x18db4000 }, + { 0x9888, 0x1adb0001 }, + { 0x9888, 0x0e9f8000 }, + { 0x9888, 0x109f02aa }, + { 0x9888, 0x0eb825c1 }, + { 0x9888, 0x18b80154 }, + { 0x9888, 0x0ab9a000 }, + { 0x9888, 0x0cb9a000 }, + { 0x9888, 0x0eb9a000 }, + { 0x9888, 0x0d88c000 }, + { 0x9888, 0x0f88000f }, + { 0x9888, 0x038a8000 }, + { 0x9888, 0x058a8000 }, + { 0x9888, 0x078a8000 }, + { 0x9888, 0x098a8000 }, + { 0x9888, 0x0b8a8000 }, + { 0x9888, 0x0d8a8000 }, + { 0x9888, 0x258baa05 }, + { 0x9888, 0x278b002a }, + { 0x9888, 0x238b2a80 }, + { 0x9888, 0x198c5400 }, + { 0x9888, 0x1b8c0015 }, + { 0x9888, 0x098dc000 }, + { 0x9888, 0x0b8da000 }, + { 0x9888, 0x0d8da000 }, + { 0x9888, 0x0f8da000 }, + { 0x9888, 0x098e05c0 }, + { 0x9888, 0x058e0000 }, + { 0x9888, 0x198f0020 }, + { 0x9888, 0x2185aa0a }, + { 0x9888, 0x2385002a }, + { 0x9888, 0x1f85aa00 }, + { 0x9888, 0x19835000 }, + { 0x9888, 0x1b830155 }, + { 0x9888, 0x03834000 }, + { 0x9888, 0x05834000 }, + { 0x9888, 0x07834000 }, + { 0x9888, 0x09834000 }, + { 0x9888, 0x0b834000 }, + { 0x9888, 0x0d834000 }, + { 0x9888, 0x09848000 }, + { 0x9888, 0x0b84c000 }, + { 0x9888, 0x0d84c000 }, + { 0x9888, 0x0f84c000 }, + { 0x9888, 0x01848000 }, + { 0x9888, 0x0384c000 }, + { 0x9888, 0x0584c000 }, + { 0x9888, 0x07844000 }, + { 0x9888, 0x19808000 }, + { 0x9888, 0x1b80c000 }, + { 0x9888, 0x1d80c000 }, + { 0x9888, 0x1f80c000 }, + { 0x9888, 0x11808000 }, + { 0x9888, 0x1380c000 }, + { 0x9888, 0x1580c000 }, + { 0x9888, 0x17804000 }, + { 0x9888, 0x51800040 }, + { 0x9888, 0x43800400 }, + { 0x9888, 0x45800800 }, + { 0x9888, 0x53800000 }, + { 0x9888, 0x47800c62 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x4d800000 }, + { 0x9888, 0x3f801042 }, + { 0x9888, 0x4f800000 }, + { 0x9888, 0x418014a4 }, +}; + +static int select_hdc_and_sf_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_hdc_and_sf; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_hdc_and_sf); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_hdc_and_sf; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_hdc_and_sf); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_hdc_and_sf; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_hdc_and_sf); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_l3_1[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0xf0800000 }, + { 0x2770, 0x00100070 }, + { 0x2774, 0x0000fff1 }, + { 0x2778, 0x00014002 }, + { 0x277c, 0x0000c3ff }, + { 0x2780, 0x00010002 }, + { 0x2784, 0x0000c7ff }, + { 0x2788, 0x00004002 }, + { 0x278c, 0x0000d3ff }, + { 0x2790, 0x00100700 }, + { 0x2794, 0x0000ff1f }, + { 0x2798, 0x00001402 }, + { 0x279c, 0x0000fc3f }, + { 0x27a0, 0x00001002 }, + { 0x27a4, 0x0000fc7f }, + { 0x27a8, 0x00000402 }, + { 0x27ac, 0x0000fd3f }, +}; + +static const struct i915_oa_reg flex_eu_config_l3_1[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_l3_1[] = { + { 0x9888, 0x10bf03da }, + { 0x9888, 0x14bf0001 }, + { 0x9888, 0x12980340 }, + { 0x9888, 0x12990340 }, + { 0x9888, 0x0cbf1187 }, + { 0x9888, 0x0ebf1205 }, + { 0x9888, 0x00bf0500 }, + { 0x9888, 0x02bf042b }, + { 0x9888, 0x04bf002c }, + { 0x9888, 0x0cdac000 }, + { 0x9888, 0x0edac000 }, + { 0x9888, 0x00da8000 }, + { 0x9888, 0x02dac000 }, + { 0x9888, 0x04da4000 }, + { 0x9888, 0x04983400 }, + { 0x9888, 0x10980000 }, + { 0x9888, 0x06990034 }, + { 0x9888, 0x10990000 }, + { 0x9888, 0x0c9dc000 }, + { 0x9888, 0x0e9dc000 }, + { 0x9888, 0x009d8000 }, + { 0x9888, 0x029dc000 }, + { 0x9888, 0x049d4000 }, + { 0x9888, 0x109f02a8 }, + { 0x9888, 0x0c9fa000 }, + { 0x9888, 0x0e9f00ba }, + { 0x9888, 0x0cb88000 }, + { 0x9888, 0x0cb95000 }, + { 0x9888, 0x0eb95000 }, + { 0x9888, 0x00b94000 }, + { 0x9888, 0x02b95000 }, + { 0x9888, 0x04b91000 }, + { 0x9888, 0x06b92000 }, + { 0x9888, 0x0cba4000 }, + { 0x9888, 0x0f88000f }, + { 0x9888, 0x03888000 }, + { 0x9888, 0x05888000 }, + { 0x9888, 0x07888000 }, + { 0x9888, 0x09888000 }, + { 0x9888, 0x0b888000 }, + { 0x9888, 0x0d880400 }, + { 0x9888, 0x258b800a }, + { 0x9888, 0x278b002a }, + { 0x9888, 0x238b5500 }, + { 0x9888, 0x198c4000 }, + { 0x9888, 0x1b8c0015 }, + { 0x9888, 0x038c4000 }, + { 0x9888, 0x058c4000 }, + { 0x9888, 0x078c4000 }, + { 0x9888, 0x098c4000 }, + { 0x9888, 0x0b8c4000 }, + { 0x9888, 0x0d8c4000 }, + { 0x9888, 0x0d8da000 }, + { 0x9888, 0x0f8da000 }, + { 0x9888, 0x018d8000 }, + { 0x9888, 0x038da000 }, + { 0x9888, 0x058da000 }, + { 0x9888, 0x078d2000 }, + { 0x9888, 0x2185800a }, + { 0x9888, 0x2385002a }, + { 0x9888, 0x1f85aa00 }, + { 0x9888, 0x1b830154 }, + { 0x9888, 0x03834000 }, + { 0x9888, 0x05834000 }, + { 0x9888, 0x07834000 }, + { 0x9888, 0x09834000 }, + { 0x9888, 0x0b834000 }, + { 0x9888, 0x0d834000 }, + { 0x9888, 0x0d84c000 }, + { 0x9888, 0x0f84c000 }, + { 0x9888, 0x01848000 }, + { 0x9888, 0x0384c000 }, + { 0x9888, 0x0584c000 }, + { 0x9888, 0x07844000 }, + { 0x9888, 0x1d80c000 }, + { 0x9888, 0x1f80c000 }, + { 0x9888, 0x11808000 }, + { 0x9888, 0x1380c000 }, + { 0x9888, 0x1580c000 }, + { 0x9888, 0x17804000 }, + { 0x9888, 0x53800000 }, + { 0x9888, 0x45800000 }, + { 0x9888, 0x47800000 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x4d800000 }, + { 0x9888, 0x3f800000 }, + { 0x9888, 0x4f800000 }, + { 0x9888, 0x41800060 }, +}; + +static int select_l3_1_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_l3_1; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_l3_1); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_l3_1; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_l3_1); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_l3_1; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_l3_1); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_l3_2[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0xf0800000 }, + { 0x2770, 0x00100070 }, + { 0x2774, 0x0000fff1 }, + { 0x2778, 0x00014002 }, + { 0x277c, 0x0000c3ff }, + { 0x2780, 0x00010002 }, + { 0x2784, 0x0000c7ff }, + { 0x2788, 0x00004002 }, + { 0x278c, 0x0000d3ff }, + { 0x2790, 0x00100700 }, + { 0x2794, 0x0000ff1f }, + { 0x2798, 0x00001402 }, + { 0x279c, 0x0000fc3f }, + { 0x27a0, 0x00001002 }, + { 0x27a4, 0x0000fc7f }, + { 0x27a8, 0x00000402 }, + { 0x27ac, 0x0000fd3f }, +}; + +static const struct i915_oa_reg flex_eu_config_l3_2[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_l3_2[] = { + { 0x9888, 0x103f03da }, + { 0x9888, 0x143f0001 }, + { 0x9888, 0x12180340 }, + { 0x9888, 0x12190340 }, + { 0x9888, 0x0c3f1187 }, + { 0x9888, 0x0e3f1205 }, + { 0x9888, 0x003f0500 }, + { 0x9888, 0x023f042b }, + { 0x9888, 0x043f002c }, + { 0x9888, 0x0c5ac000 }, + { 0x9888, 0x0e5ac000 }, + { 0x9888, 0x005a8000 }, + { 0x9888, 0x025ac000 }, + { 0x9888, 0x045a4000 }, + { 0x9888, 0x04183400 }, + { 0x9888, 0x10180000 }, + { 0x9888, 0x06190034 }, + { 0x9888, 0x10190000 }, + { 0x9888, 0x0c1dc000 }, + { 0x9888, 0x0e1dc000 }, + { 0x9888, 0x001d8000 }, + { 0x9888, 0x021dc000 }, + { 0x9888, 0x041d4000 }, + { 0x9888, 0x101f02a8 }, + { 0x9888, 0x0c1fa000 }, + { 0x9888, 0x0e1f00ba }, + { 0x9888, 0x0c388000 }, + { 0x9888, 0x0c395000 }, + { 0x9888, 0x0e395000 }, + { 0x9888, 0x00394000 }, + { 0x9888, 0x02395000 }, + { 0x9888, 0x04391000 }, + { 0x9888, 0x06392000 }, + { 0x9888, 0x0c3a4000 }, + { 0x9888, 0x1b8aa800 }, + { 0x9888, 0x1d8a0002 }, + { 0x9888, 0x038a8000 }, + { 0x9888, 0x058a8000 }, + { 0x9888, 0x078a8000 }, + { 0x9888, 0x098a8000 }, + { 0x9888, 0x0b8a8000 }, + { 0x9888, 0x0d8a8000 }, + { 0x9888, 0x258b4005 }, + { 0x9888, 0x278b0015 }, + { 0x9888, 0x238b2a80 }, + { 0x9888, 0x2185800a }, + { 0x9888, 0x2385002a }, + { 0x9888, 0x1f85aa00 }, + { 0x9888, 0x1b830154 }, + { 0x9888, 0x03834000 }, + { 0x9888, 0x05834000 }, + { 0x9888, 0x07834000 }, + { 0x9888, 0x09834000 }, + { 0x9888, 0x0b834000 }, + { 0x9888, 0x0d834000 }, + { 0x9888, 0x0d84c000 }, + { 0x9888, 0x0f84c000 }, + { 0x9888, 0x01848000 }, + { 0x9888, 0x0384c000 }, + { 0x9888, 0x0584c000 }, + { 0x9888, 0x07844000 }, + { 0x9888, 0x1d80c000 }, + { 0x9888, 0x1f80c000 }, + { 0x9888, 0x11808000 }, + { 0x9888, 0x1380c000 }, + { 0x9888, 0x1580c000 }, + { 0x9888, 0x17804000 }, + { 0x9888, 0x53800000 }, + { 0x9888, 0x45800000 }, + { 0x9888, 0x47800000 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x4d800000 }, + { 0x9888, 0x3f800000 }, + { 0x9888, 0x4f800000 }, + { 0x9888, 0x41800060 }, +}; + +static int select_l3_2_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_l3_2; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_l3_2); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_l3_2; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_l3_2); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_l3_2; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_l3_2); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_l3_3[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0xf0800000 }, + { 0x2770, 0x00100070 }, + { 0x2774, 0x0000fff1 }, + { 0x2778, 0x00014002 }, + { 0x277c, 0x0000c3ff }, + { 0x2780, 0x00010002 }, + { 0x2784, 0x0000c7ff }, + { 0x2788, 0x00004002 }, + { 0x278c, 0x0000d3ff }, + { 0x2790, 0x00100700 }, + { 0x2794, 0x0000ff1f }, + { 0x2798, 0x00001402 }, + { 0x279c, 0x0000fc3f }, + { 0x27a0, 0x00001002 }, + { 0x27a4, 0x0000fc7f }, + { 0x27a8, 0x00000402 }, + { 0x27ac, 0x0000fd3f }, +}; + +static const struct i915_oa_reg flex_eu_config_l3_3[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_l3_3[] = { + { 0x9888, 0x121b0340 }, + { 0x9888, 0x103f0274 }, + { 0x9888, 0x123f0000 }, + { 0x9888, 0x129b0340 }, + { 0x9888, 0x10bf0274 }, + { 0x9888, 0x12bf0000 }, + { 0x9888, 0x041b3400 }, + { 0x9888, 0x101b0000 }, + { 0x9888, 0x045c8000 }, + { 0x9888, 0x0a3d4000 }, + { 0x9888, 0x003f0080 }, + { 0x9888, 0x023f0793 }, + { 0x9888, 0x043f0014 }, + { 0x9888, 0x04588000 }, + { 0x9888, 0x005a8000 }, + { 0x9888, 0x025ac000 }, + { 0x9888, 0x045a4000 }, + { 0x9888, 0x0a5b4000 }, + { 0x9888, 0x001d8000 }, + { 0x9888, 0x021dc000 }, + { 0x9888, 0x041d4000 }, + { 0x9888, 0x0c1fa000 }, + { 0x9888, 0x0e1f002a }, + { 0x9888, 0x0a384000 }, + { 0x9888, 0x00394000 }, + { 0x9888, 0x02395000 }, + { 0x9888, 0x04399000 }, + { 0x9888, 0x069b0034 }, + { 0x9888, 0x109b0000 }, + { 0x9888, 0x06dc4000 }, + { 0x9888, 0x0cbd4000 }, + { 0x9888, 0x0cbf0981 }, + { 0x9888, 0x0ebf0a0f }, + { 0x9888, 0x06d84000 }, + { 0x9888, 0x0cdac000 }, + { 0x9888, 0x0edac000 }, + { 0x9888, 0x0cdb4000 }, + { 0x9888, 0x0c9dc000 }, + { 0x9888, 0x0e9dc000 }, + { 0x9888, 0x109f02a8 }, + { 0x9888, 0x0e9f0080 }, + { 0x9888, 0x0cb84000 }, + { 0x9888, 0x0cb95000 }, + { 0x9888, 0x0eb95000 }, + { 0x9888, 0x06b92000 }, + { 0x9888, 0x0f88000f }, + { 0x9888, 0x0d880400 }, + { 0x9888, 0x038a8000 }, + { 0x9888, 0x058a8000 }, + { 0x9888, 0x078a8000 }, + { 0x9888, 0x098a8000 }, + { 0x9888, 0x0b8a8000 }, + { 0x9888, 0x258b8009 }, + { 0x9888, 0x278b002a }, + { 0x9888, 0x238b2a80 }, + { 0x9888, 0x198c4000 }, + { 0x9888, 0x1b8c0015 }, + { 0x9888, 0x0d8c4000 }, + { 0x9888, 0x0d8da000 }, + { 0x9888, 0x0f8da000 }, + { 0x9888, 0x078d2000 }, + { 0x9888, 0x2185800a }, + { 0x9888, 0x2385002a }, + { 0x9888, 0x1f85aa00 }, + { 0x9888, 0x1b830154 }, + { 0x9888, 0x03834000 }, + { 0x9888, 0x05834000 }, + { 0x9888, 0x07834000 }, + { 0x9888, 0x09834000 }, + { 0x9888, 0x0b834000 }, + { 0x9888, 0x0d834000 }, + { 0x9888, 0x0d84c000 }, + { 0x9888, 0x0f84c000 }, + { 0x9888, 0x01848000 }, + { 0x9888, 0x0384c000 }, + { 0x9888, 0x0584c000 }, + { 0x9888, 0x07844000 }, + { 0x9888, 0x1d80c000 }, + { 0x9888, 0x1f80c000 }, + { 0x9888, 0x11808000 }, + { 0x9888, 0x1380c000 }, + { 0x9888, 0x1580c000 }, + { 0x9888, 0x17804000 }, + { 0x9888, 0x53800000 }, + { 0x9888, 0x45800c00 }, + { 0x9888, 0x47800c63 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x4d800000 }, + { 0x9888, 0x3f8014a5 }, + { 0x9888, 0x4f800000 }, + { 0x9888, 0x41800045 }, +}; + +static int select_l3_3_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_l3_3; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_l3_3); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_l3_3; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_l3_3); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_l3_3; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_l3_3); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_l3_4[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0xf0800000 }, + { 0x2770, 0x00100070 }, + { 0x2774, 0x0000fff1 }, + { 0x2778, 0x00014002 }, + { 0x277c, 0x0000c3ff }, + { 0x2780, 0x00010002 }, + { 0x2784, 0x0000c7ff }, + { 0x2788, 0x00004002 }, + { 0x278c, 0x0000d3ff }, + { 0x2790, 0x00100700 }, + { 0x2794, 0x0000ff1f }, + { 0x2798, 0x00001402 }, + { 0x279c, 0x0000fc3f }, + { 0x27a0, 0x00001002 }, + { 0x27a4, 0x0000fc7f }, + { 0x27a8, 0x00000402 }, + { 0x27ac, 0x0000fd3f }, +}; + +static const struct i915_oa_reg flex_eu_config_l3_4[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_l3_4[] = { + { 0x9888, 0x121a0340 }, + { 0x9888, 0x103f0017 }, + { 0x9888, 0x123f0020 }, + { 0x9888, 0x129a0340 }, + { 0x9888, 0x10bf0017 }, + { 0x9888, 0x12bf0020 }, + { 0x9888, 0x041a3400 }, + { 0x9888, 0x101a0000 }, + { 0x9888, 0x043b8000 }, + { 0x9888, 0x0a3e0010 }, + { 0x9888, 0x003f0200 }, + { 0x9888, 0x023f0113 }, + { 0x9888, 0x043f0014 }, + { 0x9888, 0x02592000 }, + { 0x9888, 0x005a8000 }, + { 0x9888, 0x025ac000 }, + { 0x9888, 0x045a4000 }, + { 0x9888, 0x0a1c8000 }, + { 0x9888, 0x001d8000 }, + { 0x9888, 0x021dc000 }, + { 0x9888, 0x041d4000 }, + { 0x9888, 0x0a1e8000 }, + { 0x9888, 0x0c1fa000 }, + { 0x9888, 0x0e1f001a }, + { 0x9888, 0x00394000 }, + { 0x9888, 0x02395000 }, + { 0x9888, 0x04391000 }, + { 0x9888, 0x069a0034 }, + { 0x9888, 0x109a0000 }, + { 0x9888, 0x06bb4000 }, + { 0x9888, 0x0abe0040 }, + { 0x9888, 0x0cbf0984 }, + { 0x9888, 0x0ebf0a02 }, + { 0x9888, 0x02d94000 }, + { 0x9888, 0x0cdac000 }, + { 0x9888, 0x0edac000 }, + { 0x9888, 0x0c9c0400 }, + { 0x9888, 0x0c9dc000 }, + { 0x9888, 0x0e9dc000 }, + { 0x9888, 0x0c9e0400 }, + { 0x9888, 0x109f02a8 }, + { 0x9888, 0x0e9f0040 }, + { 0x9888, 0x0cb95000 }, + { 0x9888, 0x0eb95000 }, + { 0x9888, 0x0f88000f }, + { 0x9888, 0x0d880400 }, + { 0x9888, 0x038a8000 }, + { 0x9888, 0x058a8000 }, + { 0x9888, 0x078a8000 }, + { 0x9888, 0x098a8000 }, + { 0x9888, 0x0b8a8000 }, + { 0x9888, 0x258b8009 }, + { 0x9888, 0x278b002a }, + { 0x9888, 0x238b2a80 }, + { 0x9888, 0x198c4000 }, + { 0x9888, 0x1b8c0015 }, + { 0x9888, 0x0d8c4000 }, + { 0x9888, 0x0d8da000 }, + { 0x9888, 0x0f8da000 }, + { 0x9888, 0x078d2000 }, + { 0x9888, 0x2185800a }, + { 0x9888, 0x2385002a }, + { 0x9888, 0x1f85aa00 }, + { 0x9888, 0x1b830154 }, + { 0x9888, 0x03834000 }, + { 0x9888, 0x05834000 }, + { 0x9888, 0x07834000 }, + { 0x9888, 0x09834000 }, + { 0x9888, 0x0b834000 }, + { 0x9888, 0x0d834000 }, + { 0x9888, 0x0d84c000 }, + { 0x9888, 0x0f84c000 }, + { 0x9888, 0x01848000 }, + { 0x9888, 0x0384c000 }, + { 0x9888, 0x0584c000 }, + { 0x9888, 0x07844000 }, + { 0x9888, 0x1d80c000 }, + { 0x9888, 0x1f80c000 }, + { 0x9888, 0x11808000 }, + { 0x9888, 0x1380c000 }, + { 0x9888, 0x1580c000 }, + { 0x9888, 0x17804000 }, + { 0x9888, 0x53800000 }, + { 0x9888, 0x45800800 }, + { 0x9888, 0x47800842 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x4d800000 }, + { 0x9888, 0x3f801084 }, + { 0x9888, 0x4f800000 }, + { 0x9888, 0x41800044 }, +}; + +static int select_l3_4_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_l3_4; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_l3_4); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_l3_4; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_l3_4); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_l3_4; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_l3_4); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x30800000 }, + { 0x2770, 0x00006000 }, + { 0x2774, 0x0000f3ff }, + { 0x2778, 0x00001800 }, + { 0x277c, 0x0000fcff }, + { 0x2780, 0x00000600 }, + { 0x2784, 0x0000ff3f }, + { 0x2788, 0x00000180 }, + { 0x278c, 0x0000ffcf }, + { 0x2790, 0x00000060 }, + { 0x2794, 0x0000fff3 }, + { 0x2798, 0x00000018 }, + { 0x279c, 0x0000fffc }, +}; + +static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { + { 0x9888, 0x143b000e }, + { 0x9888, 0x043c55c0 }, + { 0x9888, 0x0a1e0280 }, + { 0x9888, 0x0c1e0408 }, + { 0x9888, 0x10390000 }, + { 0x9888, 0x12397a1f }, + { 0x9888, 0x14bb000e }, + { 0x9888, 0x04bc5000 }, + { 0x9888, 0x0a9e0296 }, + { 0x9888, 0x0c9e0008 }, + { 0x9888, 0x10b90000 }, + { 0x9888, 0x12b97a1f }, + { 0x9888, 0x063b0042 }, + { 0x9888, 0x103b0000 }, + { 0x9888, 0x083c0000 }, + { 0x9888, 0x0a3e0040 }, + { 0x9888, 0x043f8000 }, + { 0x9888, 0x02594000 }, + { 0x9888, 0x045a8000 }, + { 0x9888, 0x0c1c0400 }, + { 0x9888, 0x041d8000 }, + { 0x9888, 0x081e02c0 }, + { 0x9888, 0x0e1e0000 }, + { 0x9888, 0x0c1fa800 }, + { 0x9888, 0x0e1f0260 }, + { 0x9888, 0x101f0014 }, + { 0x9888, 0x003905e0 }, + { 0x9888, 0x06390bc0 }, + { 0x9888, 0x02390018 }, + { 0x9888, 0x04394000 }, + { 0x9888, 0x04bb0042 }, + { 0x9888, 0x10bb0000 }, + { 0x9888, 0x02bc05c0 }, + { 0x9888, 0x08bc0000 }, + { 0x9888, 0x0abe0004 }, + { 0x9888, 0x02bf8000 }, + { 0x9888, 0x02d91000 }, + { 0x9888, 0x02da8000 }, + { 0x9888, 0x089c8000 }, + { 0x9888, 0x029d8000 }, + { 0x9888, 0x089e8000 }, + { 0x9888, 0x0e9e0000 }, + { 0x9888, 0x0e9fa806 }, + { 0x9888, 0x109f0142 }, + { 0x9888, 0x08b90617 }, + { 0x9888, 0x0ab90be0 }, + { 0x9888, 0x02b94000 }, + { 0x9888, 0x0d88f000 }, + { 0x9888, 0x0f88000c }, + { 0x9888, 0x07888000 }, + { 0x9888, 0x09888000 }, + { 0x9888, 0x018a8000 }, + { 0x9888, 0x0f8a8000 }, + { 0x9888, 0x1b8a2800 }, + { 0x9888, 0x038a8000 }, + { 0x9888, 0x058a8000 }, + { 0x9888, 0x0b8a8000 }, + { 0x9888, 0x0d8a8000 }, + { 0x9888, 0x238b52a0 }, + { 0x9888, 0x258b6a95 }, + { 0x9888, 0x278b0029 }, + { 0x9888, 0x178c2000 }, + { 0x9888, 0x198c1500 }, + { 0x9888, 0x1b8c0014 }, + { 0x9888, 0x078c4000 }, + { 0x9888, 0x098c4000 }, + { 0x9888, 0x098da000 }, + { 0x9888, 0x0b8da000 }, + { 0x9888, 0x0f8da000 }, + { 0x9888, 0x038d8000 }, + { 0x9888, 0x058d2000 }, + { 0x9888, 0x1f85aa80 }, + { 0x9888, 0x2185aaaa }, + { 0x9888, 0x2385002a }, + { 0x9888, 0x01834000 }, + { 0x9888, 0x0f834000 }, + { 0x9888, 0x19835400 }, + { 0x9888, 0x1b830155 }, + { 0x9888, 0x03834000 }, + { 0x9888, 0x05834000 }, + { 0x9888, 0x07834000 }, + { 0x9888, 0x09834000 }, + { 0x9888, 0x0b834000 }, + { 0x9888, 0x0d834000 }, + { 0x9888, 0x0184c000 }, + { 0x9888, 0x0784c000 }, + { 0x9888, 0x0984c000 }, + { 0x9888, 0x0b84c000 }, + { 0x9888, 0x0d84c000 }, + { 0x9888, 0x0f84c000 }, + { 0x9888, 0x0384c000 }, + { 0x9888, 0x0584c000 }, + { 0x9888, 0x1180c000 }, + { 0x9888, 0x1780c000 }, + { 0x9888, 0x1980c000 }, + { 0x9888, 0x1b80c000 }, + { 0x9888, 0x1d80c000 }, + { 0x9888, 0x1f80c000 }, + { 0x9888, 0x1380c000 }, + { 0x9888, 0x1580c000 }, + { 0x9888, 0x4d800444 }, + { 0x9888, 0x3d800000 }, + { 0x9888, 0x4f804000 }, + { 0x9888, 0x43801080 }, + { 0x9888, 0x51800000 }, + { 0x9888, 0x45800084 }, + { 0x9888, 0x53800044 }, + { 0x9888, 0x47801080 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x3f800000 }, + { 0x9888, 0x41800840 }, +}; + +static int select_rasterizer_and_pixel_backend_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_rasterizer_and_pixel_backend; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_rasterizer_and_pixel_backend; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_rasterizer_and_pixel_backend; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_sampler_1[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0x70800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x00800000 }, + { 0x2770, 0x0000c000 }, + { 0x2774, 0x0000e7ff }, + { 0x2778, 0x00003000 }, + { 0x277c, 0x0000f9ff }, + { 0x2780, 0x00000c00 }, + { 0x2784, 0x0000fe7f }, +}; + +static const struct i915_oa_reg flex_eu_config_sampler_1[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_sampler_1[] = { + { 0x9888, 0x18921400 }, + { 0x9888, 0x149500ab }, + { 0x9888, 0x18b21400 }, + { 0x9888, 0x14b500ab }, + { 0x9888, 0x18d21400 }, + { 0x9888, 0x14d500ab }, + { 0x9888, 0x0cdc8000 }, + { 0x9888, 0x0edc4000 }, + { 0x9888, 0x02dcc000 }, + { 0x9888, 0x04dcc000 }, + { 0x9888, 0x1abd00a0 }, + { 0x9888, 0x0abd8000 }, + { 0x9888, 0x0cd88000 }, + { 0x9888, 0x0ed84000 }, + { 0x9888, 0x04d88000 }, + { 0x9888, 0x1adb0050 }, + { 0x9888, 0x04db8000 }, + { 0x9888, 0x06db8000 }, + { 0x9888, 0x08db8000 }, + { 0x9888, 0x0adb4000 }, + { 0x9888, 0x109f02a0 }, + { 0x9888, 0x0c9fa000 }, + { 0x9888, 0x0e9f00aa }, + { 0x9888, 0x18b82500 }, + { 0x9888, 0x02b88000 }, + { 0x9888, 0x04b84000 }, + { 0x9888, 0x06b84000 }, + { 0x9888, 0x08b84000 }, + { 0x9888, 0x0ab84000 }, + { 0x9888, 0x0cb88000 }, + { 0x9888, 0x0cb98000 }, + { 0x9888, 0x0eb9a000 }, + { 0x9888, 0x00b98000 }, + { 0x9888, 0x02b9a000 }, + { 0x9888, 0x04b9a000 }, + { 0x9888, 0x06b92000 }, + { 0x9888, 0x1aba0200 }, + { 0x9888, 0x02ba8000 }, + { 0x9888, 0x0cba8000 }, + { 0x9888, 0x04908000 }, + { 0x9888, 0x04918000 }, + { 0x9888, 0x04927300 }, + { 0x9888, 0x10920000 }, + { 0x9888, 0x1893000a }, + { 0x9888, 0x0a934000 }, + { 0x9888, 0x0a946000 }, + { 0x9888, 0x0c959000 }, + { 0x9888, 0x0e950098 }, + { 0x9888, 0x10950000 }, + { 0x9888, 0x04b04000 }, + { 0x9888, 0x04b14000 }, + { 0x9888, 0x04b20073 }, + { 0x9888, 0x10b20000 }, + { 0x9888, 0x04b38000 }, + { 0x9888, 0x06b38000 }, + { 0x9888, 0x08b34000 }, + { 0x9888, 0x04b4c000 }, + { 0x9888, 0x02b59890 }, + { 0x9888, 0x10b50000 }, + { 0x9888, 0x06d04000 }, + { 0x9888, 0x06d14000 }, + { 0x9888, 0x06d20073 }, + { 0x9888, 0x10d20000 }, + { 0x9888, 0x18d30020 }, + { 0x9888, 0x02d38000 }, + { 0x9888, 0x0cd34000 }, + { 0x9888, 0x0ad48000 }, + { 0x9888, 0x04d42000 }, + { 0x9888, 0x0ed59000 }, + { 0x9888, 0x00d59800 }, + { 0x9888, 0x10d50000 }, + { 0x9888, 0x0f88000e }, + { 0x9888, 0x03888000 }, + { 0x9888, 0x05888000 }, + { 0x9888, 0x07888000 }, + { 0x9888, 0x09888000 }, + { 0x9888, 0x0b888000 }, + { 0x9888, 0x0d880400 }, + { 0x9888, 0x278b002a }, + { 0x9888, 0x238b5500 }, + { 0x9888, 0x258b000a }, + { 0x9888, 0x1b8c0015 }, + { 0x9888, 0x038c4000 }, + { 0x9888, 0x058c4000 }, + { 0x9888, 0x078c4000 }, + { 0x9888, 0x098c4000 }, + { 0x9888, 0x0b8c4000 }, + { 0x9888, 0x0d8c4000 }, + { 0x9888, 0x0d8d8000 }, + { 0x9888, 0x0f8da000 }, + { 0x9888, 0x018d8000 }, + { 0x9888, 0x038da000 }, + { 0x9888, 0x058da000 }, + { 0x9888, 0x078d2000 }, + { 0x9888, 0x2385002a }, + { 0x9888, 0x1f85aa00 }, + { 0x9888, 0x2185000a }, + { 0x9888, 0x1b830150 }, + { 0x9888, 0x03834000 }, + { 0x9888, 0x05834000 }, + { 0x9888, 0x07834000 }, + { 0x9888, 0x09834000 }, + { 0x9888, 0x0b834000 }, + { 0x9888, 0x0d834000 }, + { 0x9888, 0x0d848000 }, + { 0x9888, 0x0f84c000 }, + { 0x9888, 0x01848000 }, + { 0x9888, 0x0384c000 }, + { 0x9888, 0x0584c000 }, + { 0x9888, 0x07844000 }, + { 0x9888, 0x1d808000 }, + { 0x9888, 0x1f80c000 }, + { 0x9888, 0x11808000 }, + { 0x9888, 0x1380c000 }, + { 0x9888, 0x1580c000 }, + { 0x9888, 0x17804000 }, + { 0x9888, 0x53800000 }, + { 0x9888, 0x47801021 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x4d800000 }, + { 0x9888, 0x3f800c64 }, + { 0x9888, 0x4f800000 }, + { 0x9888, 0x41800c02 }, +}; + +static int select_sampler_1_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_sampler_1; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_sampler_1); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_sampler_1; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_sampler_1); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_sampler_1; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_sampler_1); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_sampler_2[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0x70800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x00800000 }, + { 0x2770, 0x0000c000 }, + { 0x2774, 0x0000e7ff }, + { 0x2778, 0x00003000 }, + { 0x277c, 0x0000f9ff }, + { 0x2780, 0x00000c00 }, + { 0x2784, 0x0000fe7f }, +}; + +static const struct i915_oa_reg flex_eu_config_sampler_2[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_sampler_2[] = { + { 0x9888, 0x18121400 }, + { 0x9888, 0x141500ab }, + { 0x9888, 0x18321400 }, + { 0x9888, 0x143500ab }, + { 0x9888, 0x18521400 }, + { 0x9888, 0x145500ab }, + { 0x9888, 0x0c5c8000 }, + { 0x9888, 0x0e5c4000 }, + { 0x9888, 0x025cc000 }, + { 0x9888, 0x045cc000 }, + { 0x9888, 0x1a3d00a0 }, + { 0x9888, 0x0a3d8000 }, + { 0x9888, 0x0c588000 }, + { 0x9888, 0x0e584000 }, + { 0x9888, 0x04588000 }, + { 0x9888, 0x1a5b0050 }, + { 0x9888, 0x045b8000 }, + { 0x9888, 0x065b8000 }, + { 0x9888, 0x085b8000 }, + { 0x9888, 0x0a5b4000 }, + { 0x9888, 0x101f02a0 }, + { 0x9888, 0x0c1fa000 }, + { 0x9888, 0x0e1f00aa }, + { 0x9888, 0x18382500 }, + { 0x9888, 0x02388000 }, + { 0x9888, 0x04384000 }, + { 0x9888, 0x06384000 }, + { 0x9888, 0x08384000 }, + { 0x9888, 0x0a384000 }, + { 0x9888, 0x0c388000 }, + { 0x9888, 0x0c398000 }, + { 0x9888, 0x0e39a000 }, + { 0x9888, 0x00398000 }, + { 0x9888, 0x0239a000 }, + { 0x9888, 0x0439a000 }, + { 0x9888, 0x06392000 }, + { 0x9888, 0x1a3a0200 }, + { 0x9888, 0x023a8000 }, + { 0x9888, 0x0c3a8000 }, + { 0x9888, 0x04108000 }, + { 0x9888, 0x04118000 }, + { 0x9888, 0x04127300 }, + { 0x9888, 0x10120000 }, + { 0x9888, 0x1813000a }, + { 0x9888, 0x0a134000 }, + { 0x9888, 0x0a146000 }, + { 0x9888, 0x0c159000 }, + { 0x9888, 0x0e150098 }, + { 0x9888, 0x10150000 }, + { 0x9888, 0x04304000 }, + { 0x9888, 0x04314000 }, + { 0x9888, 0x04320073 }, + { 0x9888, 0x10320000 }, + { 0x9888, 0x04338000 }, + { 0x9888, 0x06338000 }, + { 0x9888, 0x08334000 }, + { 0x9888, 0x0434c000 }, + { 0x9888, 0x02359890 }, + { 0x9888, 0x10350000 }, + { 0x9888, 0x06504000 }, + { 0x9888, 0x06514000 }, + { 0x9888, 0x06520073 }, + { 0x9888, 0x10520000 }, + { 0x9888, 0x18530020 }, + { 0x9888, 0x02538000 }, + { 0x9888, 0x0c534000 }, + { 0x9888, 0x0a548000 }, + { 0x9888, 0x04542000 }, + { 0x9888, 0x0e559000 }, + { 0x9888, 0x00559800 }, + { 0x9888, 0x10550000 }, + { 0x9888, 0x1b8aa000 }, + { 0x9888, 0x1d8a0002 }, + { 0x9888, 0x038a8000 }, + { 0x9888, 0x058a8000 }, + { 0x9888, 0x078a8000 }, + { 0x9888, 0x098a8000 }, + { 0x9888, 0x0b8a8000 }, + { 0x9888, 0x0d8a8000 }, + { 0x9888, 0x278b0015 }, + { 0x9888, 0x238b2a80 }, + { 0x9888, 0x258b0005 }, + { 0x9888, 0x2385002a }, + { 0x9888, 0x1f85aa00 }, + { 0x9888, 0x2185000a }, + { 0x9888, 0x1b830150 }, + { 0x9888, 0x03834000 }, + { 0x9888, 0x05834000 }, + { 0x9888, 0x07834000 }, + { 0x9888, 0x09834000 }, + { 0x9888, 0x0b834000 }, + { 0x9888, 0x0d834000 }, + { 0x9888, 0x0d848000 }, + { 0x9888, 0x0f84c000 }, + { 0x9888, 0x01848000 }, + { 0x9888, 0x0384c000 }, + { 0x9888, 0x0584c000 }, + { 0x9888, 0x07844000 }, + { 0x9888, 0x1d808000 }, + { 0x9888, 0x1f80c000 }, + { 0x9888, 0x11808000 }, + { 0x9888, 0x1380c000 }, + { 0x9888, 0x1580c000 }, + { 0x9888, 0x17804000 }, + { 0x9888, 0x53800000 }, + { 0x9888, 0x47801021 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x4d800000 }, + { 0x9888, 0x3f800c64 }, + { 0x9888, 0x4f800000 }, + { 0x9888, 0x41800c02 }, +}; + +static int select_sampler_2_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_sampler_2; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_sampler_2); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_sampler_2; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_sampler_2); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_sampler_2; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_sampler_2); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_tdl_1[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x30800000 }, + { 0x2770, 0x00000002 }, + { 0x2774, 0x0000fdff }, + { 0x2778, 0x00000000 }, + { 0x277c, 0x0000fe7f }, + { 0x2780, 0x00000002 }, + { 0x2784, 0x0000ffbf }, + { 0x2788, 0x00000000 }, + { 0x278c, 0x0000ffcf }, + { 0x2790, 0x00000002 }, + { 0x2794, 0x0000fff7 }, + { 0x2798, 0x00000000 }, + { 0x279c, 0x0000fff9 }, +}; + +static const struct i915_oa_reg flex_eu_config_tdl_1[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_tdl_1[] = { + { 0x9888, 0x16154d60 }, + { 0x9888, 0x16352e60 }, + { 0x9888, 0x16554d60 }, + { 0x9888, 0x16950000 }, + { 0x9888, 0x16b50000 }, + { 0x9888, 0x16d50000 }, + { 0x9888, 0x005c8000 }, + { 0x9888, 0x045cc000 }, + { 0x9888, 0x065c4000 }, + { 0x9888, 0x083d8000 }, + { 0x9888, 0x0a3d8000 }, + { 0x9888, 0x0458c000 }, + { 0x9888, 0x025b8000 }, + { 0x9888, 0x085b4000 }, + { 0x9888, 0x0a5b4000 }, + { 0x9888, 0x0c5b8000 }, + { 0x9888, 0x0c1fa000 }, + { 0x9888, 0x0e1f00aa }, + { 0x9888, 0x02384000 }, + { 0x9888, 0x04388000 }, + { 0x9888, 0x06388000 }, + { 0x9888, 0x08384000 }, + { 0x9888, 0x0a384000 }, + { 0x9888, 0x0c384000 }, + { 0x9888, 0x00398000 }, + { 0x9888, 0x0239a000 }, + { 0x9888, 0x0439a000 }, + { 0x9888, 0x06392000 }, + { 0x9888, 0x043a8000 }, + { 0x9888, 0x063a8000 }, + { 0x9888, 0x08138000 }, + { 0x9888, 0x0a138000 }, + { 0x9888, 0x06143000 }, + { 0x9888, 0x0415cfc7 }, + { 0x9888, 0x10150000 }, + { 0x9888, 0x02338000 }, + { 0x9888, 0x0c338000 }, + { 0x9888, 0x04342000 }, + { 0x9888, 0x06344000 }, + { 0x9888, 0x0035c700 }, + { 0x9888, 0x063500cf }, + { 0x9888, 0x10350000 }, + { 0x9888, 0x04538000 }, + { 0x9888, 0x06538000 }, + { 0x9888, 0x0454c000 }, + { 0x9888, 0x0255cfc7 }, + { 0x9888, 0x10550000 }, + { 0x9888, 0x06dc8000 }, + { 0x9888, 0x08dc4000 }, + { 0x9888, 0x0cdcc000 }, + { 0x9888, 0x0edcc000 }, + { 0x9888, 0x1abd00a8 }, + { 0x9888, 0x0cd8c000 }, + { 0x9888, 0x0ed84000 }, + { 0x9888, 0x0edb8000 }, + { 0x9888, 0x18db0800 }, + { 0x9888, 0x1adb0254 }, + { 0x9888, 0x0e9faa00 }, + { 0x9888, 0x109f02aa }, + { 0x9888, 0x0eb84000 }, + { 0x9888, 0x16b84000 }, + { 0x9888, 0x18b8156a }, + { 0x9888, 0x06b98000 }, + { 0x9888, 0x08b9a000 }, + { 0x9888, 0x0ab9a000 }, + { 0x9888, 0x0cb9a000 }, + { 0x9888, 0x0eb9a000 }, + { 0x9888, 0x18baa000 }, + { 0x9888, 0x1aba0002 }, + { 0x9888, 0x16934000 }, + { 0x9888, 0x1893000a }, + { 0x9888, 0x0a947000 }, + { 0x9888, 0x0c95c5c1 }, + { 0x9888, 0x0e9500c3 }, + { 0x9888, 0x10950000 }, + { 0x9888, 0x0eb38000 }, + { 0x9888, 0x16b30040 }, + { 0x9888, 0x18b30020 }, + { 0x9888, 0x06b48000 }, + { 0x9888, 0x08b41000 }, + { 0x9888, 0x0ab48000 }, + { 0x9888, 0x06b5c500 }, + { 0x9888, 0x08b500c3 }, + { 0x9888, 0x0eb5c100 }, + { 0x9888, 0x10b50000 }, + { 0x9888, 0x16d31500 }, + { 0x9888, 0x08d4e000 }, + { 0x9888, 0x08d5c100 }, + { 0x9888, 0x0ad5c3c5 }, + { 0x9888, 0x10d50000 }, + { 0x9888, 0x0d88f800 }, + { 0x9888, 0x0f88000f }, + { 0x9888, 0x038a8000 }, + { 0x9888, 0x058a8000 }, + { 0x9888, 0x078a8000 }, + { 0x9888, 0x098a8000 }, + { 0x9888, 0x0b8a8000 }, + { 0x9888, 0x0d8a8000 }, + { 0x9888, 0x258baaa5 }, + { 0x9888, 0x278b002a }, + { 0x9888, 0x238b2a80 }, + { 0x9888, 0x0f8c4000 }, + { 0x9888, 0x178c2000 }, + { 0x9888, 0x198c5500 }, + { 0x9888, 0x1b8c0015 }, + { 0x9888, 0x078d8000 }, + { 0x9888, 0x098da000 }, + { 0x9888, 0x0b8da000 }, + { 0x9888, 0x0d8da000 }, + { 0x9888, 0x0f8da000 }, + { 0x9888, 0x2185aaaa }, + { 0x9888, 0x2385002a }, + { 0x9888, 0x1f85aa00 }, + { 0x9888, 0x0f834000 }, + { 0x9888, 0x19835400 }, + { 0x9888, 0x1b830155 }, + { 0x9888, 0x03834000 }, + { 0x9888, 0x05834000 }, + { 0x9888, 0x07834000 }, + { 0x9888, 0x09834000 }, + { 0x9888, 0x0b834000 }, + { 0x9888, 0x0d834000 }, + { 0x9888, 0x0784c000 }, + { 0x9888, 0x0984c000 }, + { 0x9888, 0x0b84c000 }, + { 0x9888, 0x0d84c000 }, + { 0x9888, 0x0f84c000 }, + { 0x9888, 0x01848000 }, + { 0x9888, 0x0384c000 }, + { 0x9888, 0x0584c000 }, + { 0x9888, 0x1780c000 }, + { 0x9888, 0x1980c000 }, + { 0x9888, 0x1b80c000 }, + { 0x9888, 0x1d80c000 }, + { 0x9888, 0x1f80c000 }, + { 0x9888, 0x11808000 }, + { 0x9888, 0x1380c000 }, + { 0x9888, 0x1580c000 }, + { 0x9888, 0x4f800000 }, + { 0x9888, 0x43800c42 }, + { 0x9888, 0x51800000 }, + { 0x9888, 0x45800063 }, + { 0x9888, 0x53800000 }, + { 0x9888, 0x47800800 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x4d800000 }, + { 0x9888, 0x3f8014a4 }, + { 0x9888, 0x41801042 }, +}; + +static int select_tdl_1_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_tdl_1; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_tdl_1); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_tdl_1; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_tdl_1); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_tdl_1; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_tdl_1); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_tdl_2[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x30800000 }, + { 0x2770, 0x00000002 }, + { 0x2774, 0x0000fdff }, + { 0x2778, 0x00000000 }, + { 0x277c, 0x0000fe7f }, + { 0x2780, 0x00000000 }, + { 0x2784, 0x0000ff9f }, + { 0x2788, 0x00000000 }, + { 0x278c, 0x0000ffe7 }, + { 0x2790, 0x00000002 }, + { 0x2794, 0x0000fffb }, + { 0x2798, 0x00000002 }, + { 0x279c, 0x0000fffd }, +}; + +static const struct i915_oa_reg flex_eu_config_tdl_2[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_tdl_2[] = { + { 0x9888, 0x16150000 }, + { 0x9888, 0x16350000 }, + { 0x9888, 0x16550000 }, + { 0x9888, 0x16952e60 }, + { 0x9888, 0x16b54d60 }, + { 0x9888, 0x16d52e60 }, + { 0x9888, 0x065c8000 }, + { 0x9888, 0x085cc000 }, + { 0x9888, 0x0a5cc000 }, + { 0x9888, 0x0c5c4000 }, + { 0x9888, 0x0e3d8000 }, + { 0x9888, 0x183da000 }, + { 0x9888, 0x06588000 }, + { 0x9888, 0x08588000 }, + { 0x9888, 0x0a584000 }, + { 0x9888, 0x0e5b4000 }, + { 0x9888, 0x185b5800 }, + { 0x9888, 0x1a5b000a }, + { 0x9888, 0x0e1faa00 }, + { 0x9888, 0x101f02aa }, + { 0x9888, 0x0e384000 }, + { 0x9888, 0x16384000 }, + { 0x9888, 0x18382a55 }, + { 0x9888, 0x06398000 }, + { 0x9888, 0x0839a000 }, + { 0x9888, 0x0a39a000 }, + { 0x9888, 0x0c39a000 }, + { 0x9888, 0x0e39a000 }, + { 0x9888, 0x1a3a02a0 }, + { 0x9888, 0x0e138000 }, + { 0x9888, 0x16130500 }, + { 0x9888, 0x06148000 }, + { 0x9888, 0x08146000 }, + { 0x9888, 0x0615c100 }, + { 0x9888, 0x0815c500 }, + { 0x9888, 0x0a1500c3 }, + { 0x9888, 0x10150000 }, + { 0x9888, 0x16335040 }, + { 0x9888, 0x08349000 }, + { 0x9888, 0x0a341000 }, + { 0x9888, 0x083500c1 }, + { 0x9888, 0x0a35c500 }, + { 0x9888, 0x0c3500c3 }, + { 0x9888, 0x10350000 }, + { 0x9888, 0x1853002a }, + { 0x9888, 0x0a54e000 }, + { 0x9888, 0x0c55c500 }, + { 0x9888, 0x0e55c1c3 }, + { 0x9888, 0x10550000 }, + { 0x9888, 0x00dc8000 }, + { 0x9888, 0x02dcc000 }, + { 0x9888, 0x04dc4000 }, + { 0x9888, 0x04bd8000 }, + { 0x9888, 0x06bd8000 }, + { 0x9888, 0x02d8c000 }, + { 0x9888, 0x02db8000 }, + { 0x9888, 0x04db4000 }, + { 0x9888, 0x06db4000 }, + { 0x9888, 0x08db8000 }, + { 0x9888, 0x0c9fa000 }, + { 0x9888, 0x0e9f00aa }, + { 0x9888, 0x02b84000 }, + { 0x9888, 0x04b84000 }, + { 0x9888, 0x06b84000 }, + { 0x9888, 0x08b84000 }, + { 0x9888, 0x0ab88000 }, + { 0x9888, 0x0cb88000 }, + { 0x9888, 0x00b98000 }, + { 0x9888, 0x02b9a000 }, + { 0x9888, 0x04b9a000 }, + { 0x9888, 0x06b92000 }, + { 0x9888, 0x0aba8000 }, + { 0x9888, 0x0cba8000 }, + { 0x9888, 0x04938000 }, + { 0x9888, 0x06938000 }, + { 0x9888, 0x0494c000 }, + { 0x9888, 0x0295cfc7 }, + { 0x9888, 0x10950000 }, + { 0x9888, 0x02b38000 }, + { 0x9888, 0x08b38000 }, + { 0x9888, 0x04b42000 }, + { 0x9888, 0x06b41000 }, + { 0x9888, 0x00b5c700 }, + { 0x9888, 0x04b500cf }, + { 0x9888, 0x10b50000 }, + { 0x9888, 0x0ad38000 }, + { 0x9888, 0x0cd38000 }, + { 0x9888, 0x06d46000 }, + { 0x9888, 0x04d5c700 }, + { 0x9888, 0x06d500cf }, + { 0x9888, 0x10d50000 }, + { 0x9888, 0x03888000 }, + { 0x9888, 0x05888000 }, + { 0x9888, 0x07888000 }, + { 0x9888, 0x09888000 }, + { 0x9888, 0x0b888000 }, + { 0x9888, 0x0d880400 }, + { 0x9888, 0x0f8a8000 }, + { 0x9888, 0x198a8000 }, + { 0x9888, 0x1b8aaaa0 }, + { 0x9888, 0x1d8a0002 }, + { 0x9888, 0x258b555a }, + { 0x9888, 0x278b0015 }, + { 0x9888, 0x238b5500 }, + { 0x9888, 0x038c4000 }, + { 0x9888, 0x058c4000 }, + { 0x9888, 0x078c4000 }, + { 0x9888, 0x098c4000 }, + { 0x9888, 0x0b8c4000 }, + { 0x9888, 0x0d8c4000 }, + { 0x9888, 0x018d8000 }, + { 0x9888, 0x038da000 }, + { 0x9888, 0x058da000 }, + { 0x9888, 0x078d2000 }, + { 0x9888, 0x2185aaaa }, + { 0x9888, 0x2385002a }, + { 0x9888, 0x1f85aa00 }, + { 0x9888, 0x0f834000 }, + { 0x9888, 0x19835400 }, + { 0x9888, 0x1b830155 }, + { 0x9888, 0x03834000 }, + { 0x9888, 0x05834000 }, + { 0x9888, 0x07834000 }, + { 0x9888, 0x09834000 }, + { 0x9888, 0x0b834000 }, + { 0x9888, 0x0d834000 }, + { 0x9888, 0x0784c000 }, + { 0x9888, 0x0984c000 }, + { 0x9888, 0x0b84c000 }, + { 0x9888, 0x0d84c000 }, + { 0x9888, 0x0f84c000 }, + { 0x9888, 0x01848000 }, + { 0x9888, 0x0384c000 }, + { 0x9888, 0x0584c000 }, + { 0x9888, 0x1780c000 }, + { 0x9888, 0x1980c000 }, + { 0x9888, 0x1b80c000 }, + { 0x9888, 0x1d80c000 }, + { 0x9888, 0x1f80c000 }, + { 0x9888, 0x11808000 }, + { 0x9888, 0x1380c000 }, + { 0x9888, 0x1580c000 }, + { 0x9888, 0x4f800000 }, + { 0x9888, 0x43800882 }, + { 0x9888, 0x51800000 }, + { 0x9888, 0x45801082 }, + { 0x9888, 0x53800000 }, + { 0x9888, 0x478014a5 }, + { 0x9888, 0x21800000 }, + { 0x9888, 0x31800000 }, + { 0x9888, 0x4d800000 }, + { 0x9888, 0x3f800002 }, + { 0x9888, 0x41800c62 }, +}; + +static int select_tdl_2_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_tdl_2; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_tdl_2); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_tdl_2; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_tdl_2); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_tdl_2; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_tdl_2); + + return 0; +} + int i915_oa_select_metric_set_chv(struct drm_i915_private *dev_priv) { dev_priv->perf.oa.mux_regs = NULL; @@ -147,6 +2004,30 @@ int i915_oa_select_metric_set_chv(struct drm_i915_private *dev_priv) switch (dev_priv->perf.oa.metrics_set) { case METRIC_SET_ID_RENDER_BASIC: return select_render_basic_config(dev_priv); + case METRIC_SET_ID_COMPUTE_BASIC: + return select_compute_basic_config(dev_priv); + case METRIC_SET_ID_RENDER_PIPE_PROFILE: + return select_render_pipe_profile_config(dev_priv); + case METRIC_SET_ID_HDC_AND_SF: + return select_hdc_and_sf_config(dev_priv); + case METRIC_SET_ID_L3_1: + return select_l3_1_config(dev_priv); + case METRIC_SET_ID_L3_2: + return select_l3_2_config(dev_priv); + case METRIC_SET_ID_L3_3: + return select_l3_3_config(dev_priv); + case METRIC_SET_ID_L3_4: + return select_l3_4_config(dev_priv); + case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: + return select_rasterizer_and_pixel_backend_config(dev_priv); + case METRIC_SET_ID_SAMPLER_1: + return select_sampler_1_config(dev_priv); + case METRIC_SET_ID_SAMPLER_2: + return select_sampler_2_config(dev_priv); + case METRIC_SET_ID_TDL_1: + return select_tdl_1_config(dev_priv); + case METRIC_SET_ID_TDL_2: + return select_tdl_2_config(dev_priv); default: return -ENODEV; } @@ -174,6 +2055,270 @@ static struct attribute_group group_render_basic = { .attrs = attrs_render_basic, }; +static ssize_t +show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); +} + +static struct device_attribute dev_attr_compute_basic_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_compute_basic_id, + .store = NULL, +}; + +static struct attribute *attrs_compute_basic[] = { + &dev_attr_compute_basic_id.attr, + NULL, +}; + +static struct attribute_group group_compute_basic = { + .name = "f522a89c-ecd1-4522-8331-3383c54af5f5", + .attrs = attrs_compute_basic, +}; + +static ssize_t +show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); +} + +static struct device_attribute dev_attr_render_pipe_profile_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_render_pipe_profile_id, + .store = NULL, +}; + +static struct attribute *attrs_render_pipe_profile[] = { + &dev_attr_render_pipe_profile_id.attr, + NULL, +}; + +static struct attribute_group group_render_pipe_profile = { + .name = "a9ccc03d-a943-4e6b-9cd6-13e063075927", + .attrs = attrs_render_pipe_profile, +}; + +static ssize_t +show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); +} + +static struct device_attribute dev_attr_hdc_and_sf_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_hdc_and_sf_id, + .store = NULL, +}; + +static struct attribute *attrs_hdc_and_sf[] = { + &dev_attr_hdc_and_sf_id.attr, + NULL, +}; + +static struct attribute_group group_hdc_and_sf = { + .name = "2cf0c064-68df-4fac-9b3f-57f51ca8a069", + .attrs = attrs_hdc_and_sf, +}; + +static ssize_t +show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); +} + +static struct device_attribute dev_attr_l3_1_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_l3_1_id, + .store = NULL, +}; + +static struct attribute *attrs_l3_1[] = { + &dev_attr_l3_1_id.attr, + NULL, +}; + +static struct attribute_group group_l3_1 = { + .name = "78a87ff9-543a-49ce-95ea-26d86071ea93", + .attrs = attrs_l3_1, +}; + +static ssize_t +show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2); +} + +static struct device_attribute dev_attr_l3_2_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_l3_2_id, + .store = NULL, +}; + +static struct attribute *attrs_l3_2[] = { + &dev_attr_l3_2_id.attr, + NULL, +}; + +static struct attribute_group group_l3_2 = { + .name = "9f2cece5-7bfe-4320-ad66-8c7cc526bec5", + .attrs = attrs_l3_2, +}; + +static ssize_t +show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3); +} + +static struct device_attribute dev_attr_l3_3_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_l3_3_id, + .store = NULL, +}; + +static struct attribute *attrs_l3_3[] = { + &dev_attr_l3_3_id.attr, + NULL, +}; + +static struct attribute_group group_l3_3 = { + .name = "d890ef38-d309-47e4-b8b5-aa779bb19ab0", + .attrs = attrs_l3_3, +}; + +static ssize_t +show_l3_4_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_L3_4); +} + +static struct device_attribute dev_attr_l3_4_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_l3_4_id, + .store = NULL, +}; + +static struct attribute *attrs_l3_4[] = { + &dev_attr_l3_4_id.attr, + NULL, +}; + +static struct attribute_group group_l3_4 = { + .name = "5fdff4a6-9dc8-45e1-bfda-ef54869fbdd4", + .attrs = attrs_l3_4, +}; + +static ssize_t +show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); +} + +static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_rasterizer_and_pixel_backend_id, + .store = NULL, +}; + +static struct attribute *attrs_rasterizer_and_pixel_backend[] = { + &dev_attr_rasterizer_and_pixel_backend_id.attr, + NULL, +}; + +static struct attribute_group group_rasterizer_and_pixel_backend = { + .name = "2c0e45e1-7e2c-4a14-ae00-0b7ec868b8aa", + .attrs = attrs_rasterizer_and_pixel_backend, +}; + +static ssize_t +show_sampler_1_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_1); +} + +static struct device_attribute dev_attr_sampler_1_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_sampler_1_id, + .store = NULL, +}; + +static struct attribute *attrs_sampler_1[] = { + &dev_attr_sampler_1_id.attr, + NULL, +}; + +static struct attribute_group group_sampler_1 = { + .name = "71148d78-baf5-474f-878a-e23158d0265d", + .attrs = attrs_sampler_1, +}; + +static ssize_t +show_sampler_2_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER_2); +} + +static struct device_attribute dev_attr_sampler_2_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_sampler_2_id, + .store = NULL, +}; + +static struct attribute *attrs_sampler_2[] = { + &dev_attr_sampler_2_id.attr, + NULL, +}; + +static struct attribute_group group_sampler_2 = { + .name = "b996a2b7-c59c-492d-877a-8cd54fd6df84", + .attrs = attrs_sampler_2, +}; + +static ssize_t +show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); +} + +static struct device_attribute dev_attr_tdl_1_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_tdl_1_id, + .store = NULL, +}; + +static struct attribute *attrs_tdl_1[] = { + &dev_attr_tdl_1_id.attr, + NULL, +}; + +static struct attribute_group group_tdl_1 = { + .name = "eb2fecba-b431-42e7-8261-fe9429a6e67a", + .attrs = attrs_tdl_1, +}; + +static ssize_t +show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); +} + +static struct device_attribute dev_attr_tdl_2_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_tdl_2_id, + .store = NULL, +}; + +static struct attribute *attrs_tdl_2[] = { + &dev_attr_tdl_2_id.attr, + NULL, +}; + +static struct attribute_group group_tdl_2 = { + .name = "60749470-a648-4a4b-9f10-dbfe1e36e44d", + .attrs = attrs_tdl_2, +}; + int i915_perf_init_sysfs_chv(struct drm_i915_private *dev_priv) { @@ -182,9 +2327,69 @@ i915_perf_init_sysfs_chv(struct drm_i915_private *dev_priv) ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); if (ret) goto error_render_basic; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); + if (ret) + goto error_compute_basic; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); + if (ret) + goto error_render_pipe_profile; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); + if (ret) + goto error_hdc_and_sf; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); + if (ret) + goto error_l3_1; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2); + if (ret) + goto error_l3_2; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3); + if (ret) + goto error_l3_3; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_4); + if (ret) + goto error_l3_4; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); + if (ret) + goto error_rasterizer_and_pixel_backend; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_1); + if (ret) + goto error_sampler_1; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler_2); + if (ret) + goto error_sampler_2; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); + if (ret) + goto error_tdl_1; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); + if (ret) + goto error_tdl_2; return 0; +error_tdl_2: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); +error_tdl_1: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2); +error_sampler_2: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1); +error_sampler_1: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); +error_rasterizer_and_pixel_backend: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4); +error_l3_4: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); +error_l3_3: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); +error_l3_2: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); +error_l3_1: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); +error_hdc_and_sf: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); +error_render_pipe_profile: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); +error_compute_basic: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); error_render_basic: return ret; } @@ -193,4 +2398,16 @@ void i915_perf_deinit_sysfs_chv(struct drm_i915_private *dev_priv) { sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_4); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_1); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler_2); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); } diff --git a/drivers/gpu/drm/i915/i915_oa_skl.c b/drivers/gpu/drm/i915/i915_oa_skl.c index e0e7d6a5b664dc..e608f7030d56e1 100644 --- a/drivers/gpu/drm/i915/i915_oa_skl.c +++ b/drivers/gpu/drm/i915/i915_oa_skl.c @@ -30,9 +30,23 @@ enum metric_set_id { METRIC_SET_ID_RENDER_BASIC = 1, + METRIC_SET_ID_COMPUTE_BASIC, + METRIC_SET_ID_RENDER_PIPE_PROFILE, + METRIC_SET_ID_MEMORY_READS, + METRIC_SET_ID_MEMORY_WRITES, + METRIC_SET_ID_COMPUTE_EXTENDED, + METRIC_SET_ID_COMPUTE_L3_CACHE, + METRIC_SET_ID_HDC_AND_SF, + METRIC_SET_ID_L3_1, + METRIC_SET_ID_L3_2, + METRIC_SET_ID_L3_3, + METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND, + METRIC_SET_ID_SAMPLER, + METRIC_SET_ID_TDL_1, + METRIC_SET_ID_TDL_2, }; -int i915_oa_n_builtin_metric_sets_skl = 1; +int i915_oa_n_builtin_metric_sets_skl = 15; static const struct i915_oa_reg b_counter_config_render_basic[] = { { 0x2710, 0x00000000 }, @@ -228,6 +242,2126 @@ static int select_render_basic_config(struct drm_i915_private *dev_priv) return 0; } +static const struct i915_oa_reg b_counter_config_compute_basic[] = { + { 0x2710, 0x00000000 }, + { 0x2714, 0x00800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x00800000 }, +}; + +static const struct i915_oa_reg flex_eu_config_compute_basic[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00000003 }, + { 0xE658, 0x00002001 }, + { 0xE758, 0x00778008 }, + { 0xE45c, 0x00088078 }, + { 0xE55c, 0x00808708 }, + { 0xE65c, 0x00a08908 }, +}; + +static const struct i915_oa_reg mux_config_compute_basic_1_0_slices_0x01_and_sku_lt_0x02[] = { + { 0x9888, 0x104F00E0 }, + { 0x9888, 0x124F1C00 }, + { 0x9888, 0x106C00E0 }, + { 0x9888, 0x37906800 }, + { 0x9888, 0x3F901403 }, + { 0x9888, 0x184E8000 }, + { 0x9888, 0x1A4E8200 }, + { 0x9888, 0x044E8000 }, + { 0x9888, 0x004F0DB2 }, + { 0x9888, 0x064F0900 }, + { 0x9888, 0x084F1880 }, + { 0x9888, 0x0A4F0011 }, + { 0x9888, 0x0C4F0E3C }, + { 0x9888, 0x0E4F1D80 }, + { 0x9888, 0x086C0002 }, + { 0x9888, 0x0A6C0100 }, + { 0x9888, 0x0E6C000C }, + { 0x9888, 0x026C000B }, + { 0x9888, 0x1C6C0000 }, + { 0x9888, 0x1A6C0000 }, + { 0x9888, 0x081B4000 }, + { 0x9888, 0x0A1B8000 }, + { 0x9888, 0x0E1B4000 }, + { 0x9888, 0x021B4000 }, + { 0x9888, 0x1A1C4000 }, + { 0x9888, 0x1C1C0012 }, + { 0x9888, 0x141C8000 }, + { 0x9888, 0x005BC000 }, + { 0x9888, 0x065B8000 }, + { 0x9888, 0x085B8000 }, + { 0x9888, 0x0A5B4000 }, + { 0x9888, 0x0C5BC000 }, + { 0x9888, 0x0E5B8000 }, + { 0x9888, 0x105C8000 }, + { 0x9888, 0x1A5CA000 }, + { 0x9888, 0x1C5C002D }, + { 0x9888, 0x125C8000 }, + { 0x9888, 0x0A4C0800 }, + { 0x9888, 0x0C4C0082 }, + { 0x9888, 0x084C8000 }, + { 0x9888, 0x000DA000 }, + { 0x9888, 0x060D8000 }, + { 0x9888, 0x080DA000 }, + { 0x9888, 0x0A0DA000 }, + { 0x9888, 0x0C0DA000 }, + { 0x9888, 0x0E0DA000 }, + { 0x9888, 0x020D2000 }, + { 0x9888, 0x0C0F5400 }, + { 0x9888, 0x0E0F5500 }, + { 0x9888, 0x100F0155 }, + { 0x9888, 0x002CC000 }, + { 0x9888, 0x0E2CC000 }, + { 0x9888, 0x162CBE00 }, + { 0x9888, 0x182C00EF }, + { 0x9888, 0x022CC000 }, + { 0x9888, 0x042C8000 }, + { 0x9888, 0x19900157 }, + { 0x9888, 0x1B900167 }, + { 0x9888, 0x1D900105 }, + { 0x9888, 0x1F900103 }, + { 0x9888, 0x35900000 }, + { 0x0D28, 0x00000000 }, + { 0x9888, 0x11900FFF }, + { 0x9888, 0x51900000 }, + { 0x9888, 0x41900840 }, + { 0x9888, 0x55900000 }, + { 0x9888, 0x45900842 }, + { 0x9888, 0x47900840 }, + { 0x9888, 0x57900000 }, + { 0x9888, 0x49900840 }, + { 0x9888, 0x33900000 }, + { 0x9888, 0x4B900040 }, + { 0x9888, 0x59900000 }, + { 0x9888, 0x43900840 }, + { 0x9888, 0x53901111 }, +}; + +static const struct i915_oa_reg mux_config_compute_basic_1_0_slices_0x01_and_sku_gte_0x02[] = { + { 0x00009888, 0x104F00E0 }, + { 0x00009888, 0x124F1C00 }, + { 0x00009888, 0x106C00E0 }, + { 0x00009888, 0x37906800 }, + { 0x00009888, 0x3F901403 }, + { 0x00009888, 0x004E8000 }, + { 0x00009888, 0x1A4E0820 }, + { 0x00009888, 0x1C4E0002 }, + { 0x00009888, 0x064F0900 }, + { 0x00009888, 0x084F0032 }, + { 0x00009888, 0x0A4F1810 }, + { 0x00009888, 0x0C4F0E00 }, + { 0x00009888, 0x0E4F003C }, + { 0x00009888, 0x004F0D80 }, + { 0x00009888, 0x024F003B }, + { 0x00009888, 0x006C0002 }, + { 0x00009888, 0x086C0000 }, + { 0x00009888, 0x0C6C000C }, + { 0x00009888, 0x0E6C0B00 }, + { 0x00009888, 0x186C0000 }, + { 0x00009888, 0x1C6C0000 }, + { 0x00009888, 0x1E6C0000 }, + { 0x00009888, 0x001B4000 }, + { 0x00009888, 0x081B8000 }, + { 0x00009888, 0x0C1B4000 }, + { 0x00009888, 0x0E1B8000 }, + { 0x00009888, 0x101C8000 }, + { 0x00009888, 0x1A1C8000 }, + { 0x00009888, 0x1C1C0024 }, + { 0x00009888, 0x065B8000 }, + { 0x00009888, 0x085B4000 }, + { 0x00009888, 0x0A5BC000 }, + { 0x00009888, 0x0C5B8000 }, + { 0x00009888, 0x0E5B4000 }, + { 0x00009888, 0x005B8000 }, + { 0x00009888, 0x025B4000 }, + { 0x00009888, 0x1A5C6000 }, + { 0x00009888, 0x1C5C001B }, + { 0x00009888, 0x125C8000 }, + { 0x00009888, 0x145C8000 }, + { 0x00009888, 0x004C8000 }, + { 0x00009888, 0x0A4C2000 }, + { 0x00009888, 0x0C4C0208 }, + { 0x00009888, 0x000DA000 }, + { 0x00009888, 0x060D8000 }, + { 0x00009888, 0x080DA000 }, + { 0x00009888, 0x0A0DA000 }, + { 0x00009888, 0x0C0DA000 }, + { 0x00009888, 0x0E0DA000 }, + { 0x00009888, 0x020D2000 }, + { 0x00009888, 0x0C0F5400 }, + { 0x00009888, 0x0E0F5500 }, + { 0x00009888, 0x100F0155 }, + { 0x00009888, 0x002C8000 }, + { 0x00009888, 0x0E2CC000 }, + { 0x00009888, 0x162CFB00 }, + { 0x00009888, 0x182C00BE }, + { 0x00009888, 0x022CC000 }, + { 0x00009888, 0x042CC000 }, + { 0x00009888, 0x19900157 }, + { 0x00009888, 0x1B900167 }, + { 0x00009888, 0x1D900105 }, + { 0x00009888, 0x1F900103 }, + { 0x00009888, 0x35900000 }, + { 0x00009888, 0x11900FFF }, + { 0x00009888, 0x51900000 }, + { 0x00009888, 0x41900800 }, + { 0x00009888, 0x55900000 }, + { 0x00009888, 0x45900842 }, + { 0x00009888, 0x47900802 }, + { 0x00009888, 0x57900000 }, + { 0x00009888, 0x49900802 }, + { 0x00009888, 0x33900000 }, + { 0x00009888, 0x4B900002 }, + { 0x00009888, 0x59900000 }, + { 0x00009888, 0x43900842 }, + { 0x00009888, 0x53901111 }, +}; + +static const struct i915_oa_reg mux_config_compute_basic_1_2_slices_0x02_and_sku_lt_0x02[] = { +}; + +static int select_compute_basic_config(struct drm_i915_private *dev_priv) +{ + if ((INTEL_INFO(dev_priv)->slice_mask & 0x01) && + (dev_priv->dev->pdev->revision < 0x02)) { + dev_priv->perf.oa.mux_regs = + mux_config_compute_basic_1_0_slices_0x01_and_sku_lt_0x02; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_compute_basic_1_0_slices_0x01_and_sku_lt_0x02); + } else if ((INTEL_INFO(dev_priv)->slice_mask & 0x01) && + (dev_priv->dev->pdev->revision >= 0x02)) { + dev_priv->perf.oa.mux_regs = + mux_config_compute_basic_1_0_slices_0x01_and_sku_gte_0x02; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_compute_basic_1_0_slices_0x01_and_sku_gte_0x02); + } else if ((INTEL_INFO(dev_priv)->slice_mask & 0x02) && + (dev_priv->dev->pdev->revision < 0x02)) { + dev_priv->perf.oa.mux_regs = + mux_config_compute_basic_1_2_slices_0x02_and_sku_lt_0x02; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_compute_basic_1_2_slices_0x02_and_sku_lt_0x02); + } else { + DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_BASIC\" metric set"); + return -EINVAL; + } + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_compute_basic; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_compute_basic); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_compute_basic; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_compute_basic); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_render_pipe_profile[] = { + { 0x2724, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2710, 0x00000000 }, + { 0x2770, 0x0007ffea }, + { 0x2774, 0x00007ffc }, + { 0x2778, 0x0007affa }, + { 0x277c, 0x0000f5fd }, + { 0x2780, 0x00079ffa }, + { 0x2784, 0x0000f3fb }, + { 0x2788, 0x0007bf7a }, + { 0x278c, 0x0000f7e7 }, + { 0x2790, 0x0007fefa }, + { 0x2794, 0x0000f7cf }, + { 0x2798, 0x00077ffa }, + { 0x279c, 0x0000efdf }, + { 0x27a0, 0x0006fffa }, + { 0x27a4, 0x0000cfbf }, + { 0x27a8, 0x0003fffa }, + { 0x27ac, 0x00005f7f }, +}; + +static const struct i915_oa_reg flex_eu_config_render_pipe_profile[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00015014 }, + { 0xE658, 0x00025024 }, + { 0xE758, 0x00035034 }, + { 0xE45c, 0x00045044 }, + { 0xE55c, 0x00055054 }, + { 0xE65c, 0x00065064 }, +}; + +static const struct i915_oa_reg mux_config_render_pipe_profile_1_0_sku_lt_0x02[] = { + { 0x9888, 0x0C0E001F }, + { 0x9888, 0x0A0F0000 }, + { 0x9888, 0x10116800 }, + { 0x9888, 0x178A03E0 }, + { 0x9888, 0x11824C00 }, + { 0x9888, 0x11830020 }, + { 0x9888, 0x13840020 }, + { 0x9888, 0x11850019 }, + { 0x9888, 0x11860007 }, + { 0x9888, 0x01870C40 }, + { 0x9888, 0x17880000 }, + { 0x9888, 0x022F4000 }, + { 0x9888, 0x0A4C0040 }, + { 0x9888, 0x0C0D8000 }, + { 0x9888, 0x040D4000 }, + { 0x9888, 0x060D2000 }, + { 0x9888, 0x020E5400 }, + { 0x9888, 0x000E0000 }, + { 0x9888, 0x080F0040 }, + { 0x9888, 0x000F0000 }, + { 0x9888, 0x100F0000 }, + { 0x9888, 0x0E0F0040 }, + { 0x9888, 0x0C2C8000 }, + { 0x9888, 0x06104000 }, + { 0x9888, 0x06110012 }, + { 0x9888, 0x06131000 }, + { 0x9888, 0x01898000 }, + { 0x9888, 0x0D890100 }, + { 0x9888, 0x03898000 }, + { 0x9888, 0x09808000 }, + { 0x9888, 0x0B808000 }, + { 0x9888, 0x0380C000 }, + { 0x9888, 0x0F8A0075 }, + { 0x9888, 0x1D8A0000 }, + { 0x9888, 0x118A8000 }, + { 0x9888, 0x1B8A4000 }, + { 0x9888, 0x138A8000 }, + { 0x9888, 0x1D81A000 }, + { 0x9888, 0x15818000 }, + { 0x9888, 0x17818000 }, + { 0x9888, 0x0B820030 }, + { 0x9888, 0x07828000 }, + { 0x9888, 0x0D824000 }, + { 0x9888, 0x0F828000 }, + { 0x9888, 0x05824000 }, + { 0x9888, 0x0D830003 }, + { 0x9888, 0x0583000C }, + { 0x9888, 0x09830000 }, + { 0x9888, 0x03838000 }, + { 0x9888, 0x07838000 }, + { 0x9888, 0x0B840980 }, + { 0x9888, 0x03844D80 }, + { 0x9888, 0x11840000 }, + { 0x9888, 0x09848000 }, + { 0x9888, 0x09850080 }, + { 0x9888, 0x03850003 }, + { 0x9888, 0x01850000 }, + { 0x9888, 0x07860000 }, + { 0x9888, 0x0F860400 }, + { 0x9888, 0x09870032 }, + { 0x9888, 0x01888052 }, + { 0x9888, 0x11880000 }, + { 0x9888, 0x09884000 }, + { 0x9888, 0x15968000 }, + { 0x9888, 0x17968000 }, + { 0x9888, 0x0F96C000 }, + { 0x9888, 0x1F950011 }, + { 0x9888, 0x1D950014 }, + { 0x9888, 0x0592C000 }, + { 0x9888, 0x0B928000 }, + { 0x9888, 0x0D924000 }, + { 0x9888, 0x0F924000 }, + { 0x9888, 0x11928000 }, + { 0x9888, 0x1392C000 }, + { 0x9888, 0x09924000 }, + { 0x9888, 0x01985000 }, + { 0x9888, 0x07988000 }, + { 0x9888, 0x09981000 }, + { 0x9888, 0x0B982000 }, + { 0x9888, 0x0D982000 }, + { 0x9888, 0x0F989000 }, + { 0x9888, 0x05982000 }, + { 0x9888, 0x13904000 }, + { 0x9888, 0x21904000 }, + { 0x9888, 0x23904000 }, + { 0x9888, 0x25908000 }, + { 0x9888, 0x27904000 }, + { 0x9888, 0x29908000 }, + { 0x9888, 0x2B904000 }, + { 0x9888, 0x2F904000 }, + { 0x9888, 0x31904000 }, + { 0x9888, 0x15904000 }, + { 0x9888, 0x17908000 }, + { 0x9888, 0x19908000 }, + { 0x9888, 0x1B904000 }, + { 0x9888, 0x0B978000 }, + { 0x9888, 0x0F974000 }, + { 0x9888, 0x11974000 }, + { 0x9888, 0x13978000 }, + { 0x9888, 0x09974000 }, + { 0x0D28, 0x00000000 }, + { 0x9888, 0x1190C080 }, + { 0x9888, 0x51900000 }, + { 0x9888, 0x419010A0 }, + { 0x9888, 0x55904000 }, + { 0x9888, 0x45901000 }, + { 0x9888, 0x47900084 }, + { 0x9888, 0x57904400 }, + { 0x9888, 0x499000A5 }, + { 0x9888, 0x37900000 }, + { 0x9888, 0x33900000 }, + { 0x9888, 0x4B900081 }, + { 0x9888, 0x59900000 }, + { 0x9888, 0x439014A4 }, + { 0x9888, 0x53900400 }, +}; + +static const struct i915_oa_reg mux_config_render_pipe_profile_1_0_sku_gte_0x02[] = { + { 0x00009888, 0x0C0E001F }, + { 0x00009888, 0x0A0F0000 }, + { 0x00009888, 0x10116800 }, + { 0x00009888, 0x178A03E0 }, + { 0x00009888, 0x11824C00 }, + { 0x00009888, 0x11830020 }, + { 0x00009888, 0x13840020 }, + { 0x00009888, 0x11850019 }, + { 0x00009888, 0x11860007 }, + { 0x00009888, 0x01870C40 }, + { 0x00009888, 0x17880000 }, + { 0x00009888, 0x022F4000 }, + { 0x00009888, 0x0A4C0040 }, + { 0x00009888, 0x0C0D8000 }, + { 0x00009888, 0x040D4000 }, + { 0x00009888, 0x060D2000 }, + { 0x00009888, 0x020E5400 }, + { 0x00009888, 0x000E0000 }, + { 0x00009888, 0x080F0040 }, + { 0x00009888, 0x000F0000 }, + { 0x00009888, 0x100F0000 }, + { 0x00009888, 0x0E0F0040 }, + { 0x00009888, 0x0C2C8000 }, + { 0x00009888, 0x06104000 }, + { 0x00009888, 0x06110012 }, + { 0x00009888, 0x06131000 }, + { 0x00009888, 0x01898000 }, + { 0x00009888, 0x0D890100 }, + { 0x00009888, 0x03898000 }, + { 0x00009888, 0x09808000 }, + { 0x00009888, 0x0B808000 }, + { 0x00009888, 0x0380C000 }, + { 0x00009888, 0x0F8A0075 }, + { 0x00009888, 0x1D8A0000 }, + { 0x00009888, 0x118A8000 }, + { 0x00009888, 0x1B8A4000 }, + { 0x00009888, 0x138A8000 }, + { 0x00009888, 0x1D81A000 }, + { 0x00009888, 0x15818000 }, + { 0x00009888, 0x17818000 }, + { 0x00009888, 0x0B820030 }, + { 0x00009888, 0x07828000 }, + { 0x00009888, 0x0D824000 }, + { 0x00009888, 0x0F828000 }, + { 0x00009888, 0x05824000 }, + { 0x00009888, 0x0D830003 }, + { 0x00009888, 0x0583000C }, + { 0x00009888, 0x09830000 }, + { 0x00009888, 0x03838000 }, + { 0x00009888, 0x07838000 }, + { 0x00009888, 0x0B840980 }, + { 0x00009888, 0x03844D80 }, + { 0x00009888, 0x11840000 }, + { 0x00009888, 0x09848000 }, + { 0x00009888, 0x09850080 }, + { 0x00009888, 0x03850003 }, + { 0x00009888, 0x01850000 }, + { 0x00009888, 0x07860000 }, + { 0x00009888, 0x0F860400 }, + { 0x00009888, 0x09870032 }, + { 0x00009888, 0x01888052 }, + { 0x00009888, 0x11880000 }, + { 0x00009888, 0x09884000 }, + { 0x00009888, 0x1B931001 }, + { 0x00009888, 0x1D930001 }, + { 0x00009888, 0x19934000 }, + { 0x00009888, 0x1B958000 }, + { 0x00009888, 0x1D950094 }, + { 0x00009888, 0x19958000 }, + { 0x00009888, 0x05E5A000 }, + { 0x00009888, 0x01E5C000 }, + { 0x00009888, 0x0592C000 }, + { 0x00009888, 0x0B928000 }, + { 0x00009888, 0x0D924000 }, + { 0x00009888, 0x0F924000 }, + { 0x00009888, 0x11928000 }, + { 0x00009888, 0x1392C000 }, + { 0x00009888, 0x09924000 }, + { 0x00009888, 0x01985000 }, + { 0x00009888, 0x07988000 }, + { 0x00009888, 0x09981000 }, + { 0x00009888, 0x0B982000 }, + { 0x00009888, 0x0D982000 }, + { 0x00009888, 0x0F989000 }, + { 0x00009888, 0x05982000 }, + { 0x00009888, 0x13904000 }, + { 0x00009888, 0x21904000 }, + { 0x00009888, 0x23904000 }, + { 0x00009888, 0x25908000 }, + { 0x00009888, 0x27904000 }, + { 0x00009888, 0x29908000 }, + { 0x00009888, 0x2B904000 }, + { 0x00009888, 0x2F904000 }, + { 0x00009888, 0x31904000 }, + { 0x00009888, 0x15904000 }, + { 0x00009888, 0x17908000 }, + { 0x00009888, 0x19908000 }, + { 0x00009888, 0x1B904000 }, + { 0x00009888, 0x1190C080 }, + { 0x00009888, 0x51900000 }, + { 0x00009888, 0x419010A0 }, + { 0x00009888, 0x55904000 }, + { 0x00009888, 0x45901000 }, + { 0x00009888, 0x47900084 }, + { 0x00009888, 0x57904400 }, + { 0x00009888, 0x499000A5 }, + { 0x00009888, 0x37900000 }, + { 0x00009888, 0x33900000 }, + { 0x00009888, 0x4B900081 }, + { 0x00009888, 0x59900000 }, + { 0x00009888, 0x439014A4 }, + { 0x00009888, 0x53900400 }, +}; + +static int select_render_pipe_profile_config(struct drm_i915_private *dev_priv) +{ + if (dev_priv->dev->pdev->revision < 0x02) { + dev_priv->perf.oa.mux_regs = + mux_config_render_pipe_profile_1_0_sku_lt_0x02; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_render_pipe_profile_1_0_sku_lt_0x02); + } else if (dev_priv->dev->pdev->revision >= 0x02) { + dev_priv->perf.oa.mux_regs = + mux_config_render_pipe_profile_1_0_sku_gte_0x02; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_render_pipe_profile_1_0_sku_gte_0x02); + } else { + DRM_DEBUG_DRIVER("No suitable MUX config for \"RENDER_PIPE_PROFILE\" metric set"); + return -EINVAL; + } + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_render_pipe_profile; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_render_pipe_profile); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_render_pipe_profile; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_render_pipe_profile); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_memory_reads[] = { + { 0x272c, 0xffffffff }, + { 0x2728, 0xffffffff }, + { 0x2724, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x271c, 0xffffffff }, + { 0x2718, 0xffffffff }, + { 0x2714, 0xf0800000 }, + { 0x2710, 0x00000000 }, + { 0x274c, 0x86543210 }, + { 0x2748, 0x86543210 }, + { 0x2744, 0x00006667 }, + { 0x2740, 0x00000000 }, + { 0x275c, 0x86543210 }, + { 0x2758, 0x86543210 }, + { 0x2754, 0x00006465 }, + { 0x2750, 0x00000000 }, + { 0x2770, 0x0007f81a }, + { 0x2774, 0x0000fe00 }, + { 0x2778, 0x0007f82a }, + { 0x277c, 0x0000fe00 }, + { 0x2780, 0x0007f872 }, + { 0x2784, 0x0000fe00 }, + { 0x2788, 0x0007f8ba }, + { 0x278c, 0x0000fe00 }, + { 0x2790, 0x0007f87a }, + { 0x2794, 0x0000fe00 }, + { 0x2798, 0x0007f8ea }, + { 0x279c, 0x0000fe00 }, + { 0x27a0, 0x0007f8e2 }, + { 0x27a4, 0x0000fe00 }, + { 0x27a8, 0x0007f8f2 }, + { 0x27ac, 0x0000fe00 }, +}; + +static const struct i915_oa_reg flex_eu_config_memory_reads[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00015014 }, + { 0xE658, 0x00025024 }, + { 0xE758, 0x00035034 }, + { 0xE45c, 0x00045044 }, + { 0xE55c, 0x00055054 }, + { 0xE65c, 0x00065064 }, +}; + +static const struct i915_oa_reg mux_config_memory_reads_1_0_slices_0x01_and_sku_lt_0x02[] = { + { 0x9888, 0x11810C00 }, + { 0x9888, 0x1381001A }, + { 0x9888, 0x13946000 }, + { 0x9888, 0x37906800 }, + { 0x9888, 0x3F900003 }, + { 0x9888, 0x03811300 }, + { 0x9888, 0x05811B12 }, + { 0x9888, 0x0781001A }, + { 0x9888, 0x1F810000 }, + { 0x9888, 0x17810000 }, + { 0x9888, 0x19810000 }, + { 0x9888, 0x1B810000 }, + { 0x9888, 0x1D810000 }, + { 0x9888, 0x0F968000 }, + { 0x9888, 0x1196C000 }, + { 0x9888, 0x13964000 }, + { 0x9888, 0x11938000 }, + { 0x9888, 0x1B93FE00 }, + { 0x9888, 0x01940010 }, + { 0x9888, 0x07941100 }, + { 0x9888, 0x09941312 }, + { 0x9888, 0x0B941514 }, + { 0x9888, 0x0D941716 }, + { 0x9888, 0x11940000 }, + { 0x9888, 0x19940000 }, + { 0x9888, 0x1B940000 }, + { 0x9888, 0x1D940000 }, + { 0x9888, 0x1B954000 }, + { 0x9888, 0x1D95A550 }, + { 0x9888, 0x1F9502AA }, + { 0x9888, 0x2F900157 }, + { 0x9888, 0x31900105 }, + { 0x9888, 0x15900103 }, + { 0x9888, 0x17900101 }, + { 0x9888, 0x35900000 }, + { 0x9888, 0x13908000 }, + { 0x9888, 0x21908000 }, + { 0x9888, 0x23908000 }, + { 0x9888, 0x25908000 }, + { 0x9888, 0x27908000 }, + { 0x9888, 0x29908000 }, + { 0x9888, 0x2B908000 }, + { 0x9888, 0x2D908000 }, + { 0x9888, 0x19908000 }, + { 0x9888, 0x1B908000 }, + { 0x9888, 0x1D908000 }, + { 0x9888, 0x1F908000 }, + { 0x0D28, 0x00000000 }, + { 0x9888, 0x11900000 }, + { 0x9888, 0x51900000 }, + { 0x9888, 0x41900C00 }, + { 0x9888, 0x55900000 }, + { 0x9888, 0x45900000 }, + { 0x9888, 0x47900000 }, + { 0x9888, 0x57900000 }, + { 0x9888, 0x49900000 }, + { 0x9888, 0x33900000 }, + { 0x9888, 0x4B900063 }, + { 0x9888, 0x59900000 }, + { 0x9888, 0x43900003 }, + { 0x9888, 0x53900000 }, +}; + +static const struct i915_oa_reg mux_config_memory_reads_1_0_slices_0x01_and_sku_gte_0x02[] = { + { 0x00009888, 0x11810C00 }, + { 0x00009888, 0x1381001A }, + { 0x00009888, 0x13946000 }, + { 0x00009888, 0x15940016 }, + { 0x00009888, 0x37906800 }, + { 0x00009888, 0x03811300 }, + { 0x00009888, 0x05811B12 }, + { 0x00009888, 0x0781001A }, + { 0x00009888, 0x1F810000 }, + { 0x00009888, 0x17810000 }, + { 0x00009888, 0x19810000 }, + { 0x00009888, 0x1B810000 }, + { 0x00009888, 0x1D810000 }, + { 0x00009888, 0x19930800 }, + { 0x00009888, 0x1B93AA55 }, + { 0x00009888, 0x1D9300AA }, + { 0x00009888, 0x01940010 }, + { 0x00009888, 0x07941100 }, + { 0x00009888, 0x09941312 }, + { 0x00009888, 0x0B941514 }, + { 0x00009888, 0x0D941716 }, + { 0x00009888, 0x0F940018 }, + { 0x00009888, 0x1B940000 }, + { 0x00009888, 0x11940000 }, + { 0x00009888, 0x01E58000 }, + { 0x00009888, 0x03E57000 }, + { 0x00009888, 0x31900105 }, + { 0x00009888, 0x15900103 }, + { 0x00009888, 0x17900101 }, + { 0x00009888, 0x35900000 }, + { 0x00009888, 0x13908000 }, + { 0x00009888, 0x21908000 }, + { 0x00009888, 0x23908000 }, + { 0x00009888, 0x25908000 }, + { 0x00009888, 0x27908000 }, + { 0x00009888, 0x29908000 }, + { 0x00009888, 0x2B908000 }, + { 0x00009888, 0x2D908000 }, + { 0x00009888, 0x2F908000 }, + { 0x00009888, 0x19908000 }, + { 0x00009888, 0x1B908000 }, + { 0x00009888, 0x1D908000 }, + { 0x00009888, 0x1F908000 }, + { 0x00009888, 0x11900000 }, + { 0x00009888, 0x51900000 }, + { 0x00009888, 0x41900C20 }, + { 0x00009888, 0x55900000 }, + { 0x00009888, 0x45900400 }, + { 0x00009888, 0x47900421 }, + { 0x00009888, 0x57900000 }, + { 0x00009888, 0x49900421 }, + { 0x00009888, 0x33900000 }, + { 0x00009888, 0x4B900061 }, + { 0x00009888, 0x59900000 }, + { 0x00009888, 0x43900003 }, + { 0x00009888, 0x53900000 }, +}; + +static int select_memory_reads_config(struct drm_i915_private *dev_priv) +{ + if ((INTEL_INFO(dev_priv)->slice_mask & 0x01) && + (dev_priv->dev->pdev->revision < 0x02)) { + dev_priv->perf.oa.mux_regs = + mux_config_memory_reads_1_0_slices_0x01_and_sku_lt_0x02; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_memory_reads_1_0_slices_0x01_and_sku_lt_0x02); + } else if ((INTEL_INFO(dev_priv)->slice_mask & 0x01) && + (dev_priv->dev->pdev->revision >= 0x02)) { + dev_priv->perf.oa.mux_regs = + mux_config_memory_reads_1_0_slices_0x01_and_sku_gte_0x02; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_memory_reads_1_0_slices_0x01_and_sku_gte_0x02); + } else { + DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_READS\" metric set"); + return -EINVAL; + } + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_memory_reads; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_memory_reads); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_memory_reads; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_memory_reads); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_memory_writes[] = { + { 0x272c, 0xffffffff }, + { 0x2728, 0xffffffff }, + { 0x2724, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x271c, 0xffffffff }, + { 0x2718, 0xffffffff }, + { 0x2714, 0xf0800000 }, + { 0x2710, 0x00000000 }, + { 0x274c, 0x86543210 }, + { 0x2748, 0x86543210 }, + { 0x2744, 0x00006667 }, + { 0x2740, 0x00000000 }, + { 0x275c, 0x86543210 }, + { 0x2758, 0x86543210 }, + { 0x2754, 0x00006465 }, + { 0x2750, 0x00000000 }, + { 0x2770, 0x0007f81a }, + { 0x2774, 0x0000fe00 }, + { 0x2778, 0x0007f82a }, + { 0x277c, 0x0000fe00 }, + { 0x2780, 0x0007f822 }, + { 0x2784, 0x0000fe00 }, + { 0x2788, 0x0007f8ba }, + { 0x278c, 0x0000fe00 }, + { 0x2790, 0x0007f87a }, + { 0x2794, 0x0000fe00 }, + { 0x2798, 0x0007f8ea }, + { 0x279c, 0x0000fe00 }, + { 0x27a0, 0x0007f8e2 }, + { 0x27a4, 0x0000fe00 }, + { 0x27a8, 0x0007f8f2 }, + { 0x27ac, 0x0000fe00 }, +}; + +static const struct i915_oa_reg flex_eu_config_memory_writes[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00015014 }, + { 0xE658, 0x00025024 }, + { 0xE758, 0x00035034 }, + { 0xE45c, 0x00045044 }, + { 0xE55c, 0x00055054 }, + { 0xE65c, 0x00065064 }, +}; + +static const struct i915_oa_reg mux_config_memory_writes_1_0_slices_0x01_and_sku_lt_0x02[] = { + { 0x9888, 0x11810C00 }, + { 0x9888, 0x1381001A }, + { 0x9888, 0x13945400 }, + { 0x9888, 0x37906800 }, + { 0x9888, 0x3F901400 }, + { 0x9888, 0x03811300 }, + { 0x9888, 0x05811B12 }, + { 0x9888, 0x0781001A }, + { 0x9888, 0x1F810000 }, + { 0x9888, 0x17810000 }, + { 0x9888, 0x19810000 }, + { 0x9888, 0x1B810000 }, + { 0x9888, 0x1D810000 }, + { 0x9888, 0x0F968000 }, + { 0x9888, 0x1196C000 }, + { 0x9888, 0x13964000 }, + { 0x9888, 0x11938000 }, + { 0x9888, 0x1B93FE00 }, + { 0x9888, 0x01940010 }, + { 0x9888, 0x07941100 }, + { 0x9888, 0x09941312 }, + { 0x9888, 0x0B941514 }, + { 0x9888, 0x0D941716 }, + { 0x9888, 0x11940000 }, + { 0x9888, 0x19940000 }, + { 0x9888, 0x1B940000 }, + { 0x9888, 0x1D940000 }, + { 0x9888, 0x1B954000 }, + { 0x9888, 0x1D95A550 }, + { 0x9888, 0x1F9502AA }, + { 0x9888, 0x2F900167 }, + { 0x9888, 0x31900105 }, + { 0x9888, 0x15900103 }, + { 0x9888, 0x17900101 }, + { 0x9888, 0x35900000 }, + { 0x9888, 0x13908000 }, + { 0x9888, 0x21908000 }, + { 0x9888, 0x23908000 }, + { 0x9888, 0x25908000 }, + { 0x9888, 0x27908000 }, + { 0x9888, 0x29908000 }, + { 0x9888, 0x2B908000 }, + { 0x9888, 0x2D908000 }, + { 0x9888, 0x19908000 }, + { 0x9888, 0x1B908000 }, + { 0x9888, 0x1D908000 }, + { 0x9888, 0x1F908000 }, + { 0x0D28, 0x00000000 }, + { 0x9888, 0x11900000 }, + { 0x9888, 0x51900000 }, + { 0x9888, 0x41900C00 }, + { 0x9888, 0x55900000 }, + { 0x9888, 0x45900000 }, + { 0x9888, 0x47900000 }, + { 0x9888, 0x57900000 }, + { 0x9888, 0x49900000 }, + { 0x9888, 0x33900000 }, + { 0x9888, 0x4B900063 }, + { 0x9888, 0x59900000 }, + { 0x9888, 0x43900003 }, + { 0x9888, 0x53900000 }, +}; + +static const struct i915_oa_reg mux_config_memory_writes_1_0_slices_0x01_and_sku_gte_0x02[] = { + { 0x00009888, 0x11810C00 }, + { 0x00009888, 0x1381001A }, + { 0x00009888, 0x13945400 }, + { 0x00009888, 0x37906800 }, + { 0x00009888, 0x3F901400 }, + { 0x00009888, 0x03811300 }, + { 0x00009888, 0x05811B12 }, + { 0x00009888, 0x0781001A }, + { 0x00009888, 0x1F810000 }, + { 0x00009888, 0x17810000 }, + { 0x00009888, 0x19810000 }, + { 0x00009888, 0x1B810000 }, + { 0x00009888, 0x1D810000 }, + { 0x00009888, 0x19930800 }, + { 0x00009888, 0x1B93AA55 }, + { 0x00009888, 0x1D93002A }, + { 0x00009888, 0x01940010 }, + { 0x00009888, 0x07941100 }, + { 0x00009888, 0x09941312 }, + { 0x00009888, 0x0B941514 }, + { 0x00009888, 0x0D941716 }, + { 0x00009888, 0x1B940000 }, + { 0x00009888, 0x11940000 }, + { 0x00009888, 0x01E58000 }, + { 0x00009888, 0x03E57000 }, + { 0x00009888, 0x2F900167 }, + { 0x00009888, 0x31900105 }, + { 0x00009888, 0x15900103 }, + { 0x00009888, 0x17900101 }, + { 0x00009888, 0x35900000 }, + { 0x00009888, 0x13908000 }, + { 0x00009888, 0x21908000 }, + { 0x00009888, 0x23908000 }, + { 0x00009888, 0x25908000 }, + { 0x00009888, 0x27908000 }, + { 0x00009888, 0x29908000 }, + { 0x00009888, 0x2B908000 }, + { 0x00009888, 0x2D908000 }, + { 0x00009888, 0x19908000 }, + { 0x00009888, 0x1B908000 }, + { 0x00009888, 0x1D908000 }, + { 0x00009888, 0x1F908000 }, + { 0x00009888, 0x11900000 }, + { 0x00009888, 0x51900000 }, + { 0x00009888, 0x41900C20 }, + { 0x00009888, 0x55900000 }, + { 0x00009888, 0x45900400 }, + { 0x00009888, 0x47900421 }, + { 0x00009888, 0x57900000 }, + { 0x00009888, 0x49900421 }, + { 0x00009888, 0x33900000 }, + { 0x00009888, 0x4B900063 }, + { 0x00009888, 0x59900000 }, + { 0x00009888, 0x43900003 }, + { 0x00009888, 0x53900000 }, +}; + +static int select_memory_writes_config(struct drm_i915_private *dev_priv) +{ + if ((INTEL_INFO(dev_priv)->slice_mask & 0x01) && + (dev_priv->dev->pdev->revision < 0x02)) { + dev_priv->perf.oa.mux_regs = + mux_config_memory_writes_1_0_slices_0x01_and_sku_lt_0x02; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_memory_writes_1_0_slices_0x01_and_sku_lt_0x02); + } else if ((INTEL_INFO(dev_priv)->slice_mask & 0x01) && + (dev_priv->dev->pdev->revision >= 0x02)) { + dev_priv->perf.oa.mux_regs = + mux_config_memory_writes_1_0_slices_0x01_and_sku_gte_0x02; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_memory_writes_1_0_slices_0x01_and_sku_gte_0x02); + } else { + DRM_DEBUG_DRIVER("No suitable MUX config for \"MEMORY_WRITES\" metric set"); + return -EINVAL; + } + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_memory_writes; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_memory_writes); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_memory_writes; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_memory_writes); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_compute_extended[] = { + { 0x2724, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2710, 0x00000000 }, + { 0x2770, 0x0007fc2a }, + { 0x2774, 0x0000bf00 }, + { 0x2778, 0x0007fc6a }, + { 0x277c, 0x0000bf00 }, + { 0x2780, 0x0007fc92 }, + { 0x2784, 0x0000bf00 }, + { 0x2788, 0x0007fca2 }, + { 0x278c, 0x0000bf00 }, + { 0x2790, 0x0007fc32 }, + { 0x2794, 0x0000bf00 }, + { 0x2798, 0x0007fc9a }, + { 0x279c, 0x0000bf00 }, + { 0x27a0, 0x0007fe6a }, + { 0x27a4, 0x0000bf00 }, + { 0x27a8, 0x0007fe7a }, + { 0x27ac, 0x0000bf00 }, +}; + +static const struct i915_oa_reg flex_eu_config_compute_extended[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00000003 }, + { 0xE658, 0x00002001 }, + { 0xE758, 0x00778008 }, + { 0xE45c, 0x00088078 }, + { 0xE55c, 0x00808708 }, + { 0xE65c, 0x00a08908 }, +}; + +static const struct i915_oa_reg mux_config_compute_extended_1_0_subslices_0x01_and_sku_lt_0x02[] = { + { 0x9888, 0x106C00E0 }, + { 0x9888, 0x141C8160 }, + { 0x9888, 0x161C8015 }, + { 0x9888, 0x181C0120 }, + { 0x9888, 0x004E8000 }, + { 0x9888, 0x0E4E8000 }, + { 0x9888, 0x184E8000 }, + { 0x9888, 0x1A4EAAA0 }, + { 0x9888, 0x1C4E0002 }, + { 0x9888, 0x024E8000 }, + { 0x9888, 0x044E8000 }, + { 0x9888, 0x064E8000 }, + { 0x9888, 0x084E8000 }, + { 0x9888, 0x0A4E8000 }, + { 0x9888, 0x0E6C0B01 }, + { 0x9888, 0x006C0200 }, + { 0x9888, 0x026C000C }, + { 0x9888, 0x1C6C0000 }, + { 0x9888, 0x1E6C0000 }, + { 0x9888, 0x1A6C0000 }, + { 0x9888, 0x0E1BC000 }, + { 0x9888, 0x001B8000 }, + { 0x9888, 0x021BC000 }, + { 0x9888, 0x001C0041 }, + { 0x9888, 0x061C4200 }, + { 0x9888, 0x081C4443 }, + { 0x9888, 0x0A1C4645 }, + { 0x9888, 0x0C1C7647 }, + { 0x9888, 0x041C7357 }, + { 0x9888, 0x1C1C0030 }, + { 0x9888, 0x101C0000 }, + { 0x9888, 0x1A1C0000 }, + { 0x9888, 0x121C8000 }, + { 0x9888, 0x004C8000 }, + { 0x9888, 0x0A4CAA2A }, + { 0x9888, 0x0C4C02AA }, + { 0x9888, 0x084CA000 }, + { 0x9888, 0x000DA000 }, + { 0x9888, 0x060D8000 }, + { 0x9888, 0x080DA000 }, + { 0x9888, 0x0A0DA000 }, + { 0x9888, 0x0C0DA000 }, + { 0x9888, 0x0E0DA000 }, + { 0x9888, 0x020DA000 }, + { 0x9888, 0x040DA000 }, + { 0x9888, 0x0C0F5400 }, + { 0x9888, 0x0E0F5515 }, + { 0x9888, 0x100F0155 }, + { 0x9888, 0x002C8000 }, + { 0x9888, 0x0E2C8000 }, + { 0x9888, 0x162CAA00 }, + { 0x9888, 0x182C00AA }, + { 0x9888, 0x022C8000 }, + { 0x9888, 0x042C8000 }, + { 0x9888, 0x062C8000 }, + { 0x9888, 0x082C8000 }, + { 0x9888, 0x0A2C8000 }, + { 0x0D28, 0x00000000 }, + { 0x9888, 0x11907FFF }, + { 0x9888, 0x51900000 }, + { 0x9888, 0x41900040 }, + { 0x9888, 0x55900000 }, + { 0x9888, 0x45900802 }, + { 0x9888, 0x47900842 }, + { 0x9888, 0x57900000 }, + { 0x9888, 0x49900842 }, + { 0x9888, 0x37900000 }, + { 0x9888, 0x33900000 }, + { 0x9888, 0x4B900000 }, + { 0x9888, 0x59900000 }, + { 0x9888, 0x43900800 }, + { 0x9888, 0x53900000 }, +}; + +static const struct i915_oa_reg mux_config_compute_extended_1_1_subslices_0x08_and_sku_lt_0x02[] = { +}; + +static const struct i915_oa_reg mux_config_compute_extended_1_2_subslices_0x02_and_sku_lt_0x02[] = { + { 0x9888, 0x104F00E0 }, + { 0x9888, 0x143C0160 }, + { 0x9888, 0x163C0015 }, + { 0x9888, 0x183C0120 }, + { 0x9888, 0x0E4F0D91 }, + { 0x9888, 0x004F0900 }, + { 0x9888, 0x024F081C }, + { 0x9888, 0x003C0041 }, + { 0x9888, 0x063C4200 }, + { 0x9888, 0x083C4443 }, + { 0x9888, 0x0A3C4645 }, + { 0x9888, 0x0C3C7647 }, + { 0x9888, 0x043C7357 }, + { 0x9888, 0x1C3C0000 }, + { 0x9888, 0x103C0000 }, + { 0x9888, 0x1A3C0000 }, + { 0x9888, 0x0E5BC000 }, + { 0x9888, 0x005B8000 }, + { 0x9888, 0x025BC000 }, + { 0x9888, 0x1C5C0030 }, + { 0x9888, 0x125C8000 }, + { 0x9888, 0x145C8000 }, + { 0x9888, 0x165C8000 }, + { 0x9888, 0x004CC000 }, + { 0x9888, 0x0A4CFF3C }, + { 0x9888, 0x0C4C003F }, + { 0x9888, 0x000DA000 }, + { 0x9888, 0x060D8000 }, + { 0x9888, 0x080DA000 }, + { 0x9888, 0x0A0DA000 }, + { 0x9888, 0x0C0DA000 }, + { 0x9888, 0x0E0DA000 }, + { 0x9888, 0x020DA000 }, + { 0x9888, 0x040DA000 }, + { 0x9888, 0x0C0F5400 }, + { 0x9888, 0x0E0F5515 }, + { 0x9888, 0x100F0155 }, + { 0x9888, 0x002C8000 }, + { 0x9888, 0x0E2C8000 }, + { 0x9888, 0x162CAA00 }, + { 0x9888, 0x182C00FA }, + { 0x9888, 0x022CC000 }, + { 0x9888, 0x042CC000 }, + { 0x9888, 0x062CC000 }, + { 0x9888, 0x082C8000 }, + { 0x9888, 0x0A2C8000 }, + { 0x0D28, 0x00000000 }, + { 0x9888, 0x11907FFF }, + { 0x9888, 0x51900000 }, + { 0x9888, 0x41900020 }, + { 0x9888, 0x55900000 }, + { 0x9888, 0x45900401 }, + { 0x9888, 0x47900421 }, + { 0x9888, 0x57900000 }, + { 0x9888, 0x49900421 }, + { 0x9888, 0x37900000 }, + { 0x9888, 0x33900000 }, + { 0x9888, 0x4B900000 }, + { 0x9888, 0x59900000 }, + { 0x9888, 0x43900400 }, + { 0x9888, 0x53900000 }, +}; + +static const struct i915_oa_reg mux_config_compute_extended_1_3_subslices_0x10_and_sku_lt_0x02[] = { +}; + +static const struct i915_oa_reg mux_config_compute_extended_1_4_subslices_0x04_and_sku_lt_0x02[] = { + { 0x9888, 0x124F1C00 }, + { 0x9888, 0x145C8160 }, + { 0x9888, 0x165C8015 }, + { 0x9888, 0x185C0120 }, + { 0x9888, 0x0E4F1DB1 }, + { 0x9888, 0x004F1900 }, + { 0x9888, 0x024F183C }, + { 0x9888, 0x104F0000 }, + { 0x9888, 0x0E5BC000 }, + { 0x9888, 0x005B8000 }, + { 0x9888, 0x025BC000 }, + { 0x9888, 0x005C0041 }, + { 0x9888, 0x065C4200 }, + { 0x9888, 0x085C4443 }, + { 0x9888, 0x0A5C4645 }, + { 0x9888, 0x0C5C7647 }, + { 0x9888, 0x045C7357 }, + { 0x9888, 0x1C5C0030 }, + { 0x9888, 0x105C0000 }, + { 0x9888, 0x1A5C0000 }, + { 0x9888, 0x125C8000 }, + { 0x9888, 0x000DA000 }, + { 0x9888, 0x060D8000 }, + { 0x9888, 0x080DA000 }, + { 0x9888, 0x0A0DA000 }, + { 0x9888, 0x0C0DA000 }, + { 0x9888, 0x0E0DA000 }, + { 0x9888, 0x020DA000 }, + { 0x9888, 0x040DA000 }, + { 0x9888, 0x0C0F5400 }, + { 0x9888, 0x0E0F5515 }, + { 0x9888, 0x100F0155 }, + { 0x9888, 0x002CC000 }, + { 0x9888, 0x0E2CC000 }, + { 0x9888, 0x162CFF00 }, + { 0x9888, 0x182C00FF }, + { 0x9888, 0x022CC000 }, + { 0x9888, 0x042CC000 }, + { 0x9888, 0x062CC000 }, + { 0x9888, 0x082CC000 }, + { 0x9888, 0x0A2CC000 }, + { 0x0D28, 0x00000000 }, + { 0x9888, 0x11907FFF }, + { 0x9888, 0x51900000 }, + { 0x9888, 0x41900040 }, + { 0x9888, 0x55900000 }, + { 0x9888, 0x45900802 }, + { 0x9888, 0x47900842 }, + { 0x9888, 0x57900000 }, + { 0x9888, 0x49900842 }, + { 0x9888, 0x37900000 }, + { 0x9888, 0x33900000 }, + { 0x9888, 0x4B900000 }, + { 0x9888, 0x59900000 }, + { 0x9888, 0x43900800 }, + { 0x9888, 0x53900000 }, +}; + +static const struct i915_oa_reg mux_config_compute_extended_1_5_subslices_0x20_and_sku_lt_0x02[] = { +}; + +static int select_compute_extended_config(struct drm_i915_private *dev_priv) +{ + if ((INTEL_INFO(dev_priv)->subslice_mask & 0x01) && + (dev_priv->dev->pdev->revision < 0x02)) { + dev_priv->perf.oa.mux_regs = + mux_config_compute_extended_1_0_subslices_0x01_and_sku_lt_0x02; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_compute_extended_1_0_subslices_0x01_and_sku_lt_0x02); + } else if ((INTEL_INFO(dev_priv)->subslice_mask & 0x08) && + (dev_priv->dev->pdev->revision < 0x02)) { + dev_priv->perf.oa.mux_regs = + mux_config_compute_extended_1_1_subslices_0x08_and_sku_lt_0x02; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_compute_extended_1_1_subslices_0x08_and_sku_lt_0x02); + } else if ((INTEL_INFO(dev_priv)->subslice_mask & 0x02) && + (dev_priv->dev->pdev->revision < 0x02)) { + dev_priv->perf.oa.mux_regs = + mux_config_compute_extended_1_2_subslices_0x02_and_sku_lt_0x02; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_compute_extended_1_2_subslices_0x02_and_sku_lt_0x02); + } else if ((INTEL_INFO(dev_priv)->subslice_mask & 0x10) && + (dev_priv->dev->pdev->revision < 0x02)) { + dev_priv->perf.oa.mux_regs = + mux_config_compute_extended_1_3_subslices_0x10_and_sku_lt_0x02; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_compute_extended_1_3_subslices_0x10_and_sku_lt_0x02); + } else if ((INTEL_INFO(dev_priv)->subslice_mask & 0x04) && + (dev_priv->dev->pdev->revision < 0x02)) { + dev_priv->perf.oa.mux_regs = + mux_config_compute_extended_1_4_subslices_0x04_and_sku_lt_0x02; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_compute_extended_1_4_subslices_0x04_and_sku_lt_0x02); + } else if ((INTEL_INFO(dev_priv)->subslice_mask & 0x20) && + (dev_priv->dev->pdev->revision < 0x02)) { + dev_priv->perf.oa.mux_regs = + mux_config_compute_extended_1_5_subslices_0x20_and_sku_lt_0x02; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_compute_extended_1_5_subslices_0x20_and_sku_lt_0x02); + } else { + DRM_DEBUG_DRIVER("No suitable MUX config for \"COMPUTE_EXTENDED\" metric set"); + return -EINVAL; + } + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_compute_extended; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_compute_extended); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_compute_extended; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_compute_extended); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_compute_l3_cache[] = { + { 0x2710, 0x00000000 }, + { 0x2714, 0x30800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x30800000 }, + { 0x2770, 0x0007fffa }, + { 0x2774, 0x0000fefe }, + { 0x2778, 0x0007fffa }, + { 0x277c, 0x0000fefd }, + { 0x2790, 0x0007fffa }, + { 0x2794, 0x0000fbef }, + { 0x2798, 0x0007fffa }, + { 0x279c, 0x0000fbdf }, +}; + +static const struct i915_oa_reg flex_eu_config_compute_l3_cache[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00000003 }, + { 0xE658, 0x00002001 }, + { 0xE758, 0x00101100 }, + { 0xE45c, 0x00201200 }, + { 0xE55c, 0x00301300 }, + { 0xE65c, 0x00401400 }, +}; + +static const struct i915_oa_reg mux_config_compute_l3_cache[] = { + { 0x00009888, 0x166C0760 }, + { 0x00009888, 0x1593001E }, + { 0x00009888, 0x3F901403 }, + { 0x00009888, 0x004E8000 }, + { 0x00009888, 0x0E4E8000 }, + { 0x00009888, 0x184E8000 }, + { 0x00009888, 0x1A4E8020 }, + { 0x00009888, 0x1C4E0002 }, + { 0x00009888, 0x006C0051 }, + { 0x00009888, 0x066C5000 }, + { 0x00009888, 0x086C5C5D }, + { 0x00009888, 0x0E6C5E5F }, + { 0x00009888, 0x106C0000 }, + { 0x00009888, 0x186C0000 }, + { 0x00009888, 0x1C6C0000 }, + { 0x00009888, 0x1E6C0000 }, + { 0x00009888, 0x001B4000 }, + { 0x00009888, 0x061B8000 }, + { 0x00009888, 0x081BC000 }, + { 0x00009888, 0x0E1BC000 }, + { 0x00009888, 0x101C8000 }, + { 0x00009888, 0x1A1CE000 }, + { 0x00009888, 0x1C1C0030 }, + { 0x00009888, 0x004C8000 }, + { 0x00009888, 0x0A4C2A00 }, + { 0x00009888, 0x0C4C0280 }, + { 0x00009888, 0x000D2000 }, + { 0x00009888, 0x060D8000 }, + { 0x00009888, 0x080DA000 }, + { 0x00009888, 0x0E0DA000 }, + { 0x00009888, 0x0C0F0400 }, + { 0x00009888, 0x0E0F1500 }, + { 0x00009888, 0x100F0140 }, + { 0x00009888, 0x002C8000 }, + { 0x00009888, 0x0E2C8000 }, + { 0x00009888, 0x162C0A00 }, + { 0x00009888, 0x182C00A0 }, + { 0x00009888, 0x03933300 }, + { 0x00009888, 0x05930032 }, + { 0x00009888, 0x11930000 }, + { 0x00009888, 0x1B930000 }, + { 0x00009888, 0x1D900157 }, + { 0x00009888, 0x1F900167 }, + { 0x00009888, 0x35900000 }, + { 0x00009888, 0x19908000 }, + { 0x00009888, 0x1B908000 }, + { 0x00009888, 0x1190030F }, + { 0x00009888, 0x51900000 }, + { 0x00009888, 0x41900000 }, + { 0x00009888, 0x55900000 }, + { 0x00009888, 0x45900042 }, + { 0x00009888, 0x47900000 }, + { 0x00009888, 0x37900000 }, + { 0x00009888, 0x33900000 }, + { 0x00009888, 0x57900000 }, + { 0x00009888, 0x4B900000 }, + { 0x00009888, 0x59900000 }, + { 0x00009888, 0x53901111 }, + { 0x00009888, 0x43900420 }, +}; + +static int select_compute_l3_cache_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_compute_l3_cache; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_compute_l3_cache); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_compute_l3_cache; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_compute_l3_cache); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_compute_l3_cache; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_compute_l3_cache); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_hdc_and_sf[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0x10800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x00800000 }, + { 0x2770, 0x00000002 }, + { 0x2774, 0x0000fdff }, +}; + +static const struct i915_oa_reg flex_eu_config_hdc_and_sf[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_hdc_and_sf[] = { + { 0x9888, 0x104f0232 }, + { 0x9888, 0x124f4640 }, + { 0x9888, 0x106c0232 }, + { 0x9888, 0x11834400 }, + { 0x9888, 0x0a4e8000 }, + { 0x9888, 0x0c4e8000 }, + { 0x9888, 0x004f1880 }, + { 0x9888, 0x024f08bb }, + { 0x9888, 0x044f001b }, + { 0x9888, 0x046c0100 }, + { 0x9888, 0x066c000b }, + { 0x9888, 0x1a6c0000 }, + { 0x9888, 0x041b8000 }, + { 0x9888, 0x061b4000 }, + { 0x9888, 0x1a1c1800 }, + { 0x9888, 0x005b8000 }, + { 0x9888, 0x025bc000 }, + { 0x9888, 0x045b4000 }, + { 0x9888, 0x125c8000 }, + { 0x9888, 0x145c8000 }, + { 0x9888, 0x165c8000 }, + { 0x9888, 0x185c8000 }, + { 0x9888, 0x0a4c00a0 }, + { 0x9888, 0x000d8000 }, + { 0x9888, 0x020da000 }, + { 0x9888, 0x040da000 }, + { 0x9888, 0x060d2000 }, + { 0x9888, 0x0c0f5000 }, + { 0x9888, 0x0e0f0055 }, + { 0x9888, 0x022cc000 }, + { 0x9888, 0x042cc000 }, + { 0x9888, 0x062cc000 }, + { 0x9888, 0x082cc000 }, + { 0x9888, 0x0a2c8000 }, + { 0x9888, 0x0c2c8000 }, + { 0x9888, 0x0f828000 }, + { 0x9888, 0x0f8305c0 }, + { 0x9888, 0x09830000 }, + { 0x9888, 0x07830000 }, + { 0x9888, 0x1d950080 }, + { 0x9888, 0x13928000 }, + { 0x9888, 0x0f988000 }, + { 0x9888, 0x31904000 }, + { 0x9888, 0x1190fc00 }, + { 0x9888, 0x37900000 }, + { 0x9888, 0x59900000 }, + { 0x9888, 0x4b9000a0 }, + { 0x9888, 0x51900000 }, + { 0x9888, 0x41900800 }, + { 0x9888, 0x43900842 }, + { 0x9888, 0x53900000 }, + { 0x9888, 0x45900000 }, + { 0x9888, 0x33900000 }, +}; + +static int select_hdc_and_sf_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_hdc_and_sf; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_hdc_and_sf); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_hdc_and_sf; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_hdc_and_sf); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_hdc_and_sf; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_hdc_and_sf); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_l3_1[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0xf0800000 }, + { 0x2770, 0x00100070 }, + { 0x2774, 0x0000fff1 }, + { 0x2778, 0x00014002 }, + { 0x277c, 0x0000c3ff }, + { 0x2780, 0x00010002 }, + { 0x2784, 0x0000c7ff }, + { 0x2788, 0x00004002 }, + { 0x278c, 0x0000d3ff }, + { 0x2790, 0x00100700 }, + { 0x2794, 0x0000ff1f }, + { 0x2798, 0x00001402 }, + { 0x279c, 0x0000fc3f }, + { 0x27a0, 0x00001002 }, + { 0x27a4, 0x0000fc7f }, + { 0x27a8, 0x00000402 }, + { 0x27ac, 0x0000fd3f }, +}; + +static const struct i915_oa_reg flex_eu_config_l3_1[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_l3_1[] = { + { 0x9888, 0x126c7b40 }, + { 0x9888, 0x166c0020 }, + { 0x9888, 0x0a603444 }, + { 0x9888, 0x0a613400 }, + { 0x9888, 0x1a4ea800 }, + { 0x9888, 0x1c4e0002 }, + { 0x9888, 0x024e8000 }, + { 0x9888, 0x044e8000 }, + { 0x9888, 0x064e8000 }, + { 0x9888, 0x084e8000 }, + { 0x9888, 0x0a4e8000 }, + { 0x9888, 0x064f4000 }, + { 0x9888, 0x0c6c5327 }, + { 0x9888, 0x0e6c5425 }, + { 0x9888, 0x006c2a00 }, + { 0x9888, 0x026c285b }, + { 0x9888, 0x046c005c }, + { 0x9888, 0x106c0000 }, + { 0x9888, 0x1c6c0000 }, + { 0x9888, 0x1e6c0000 }, + { 0x9888, 0x1a6c0800 }, + { 0x9888, 0x0c1bc000 }, + { 0x9888, 0x0e1bc000 }, + { 0x9888, 0x001b8000 }, + { 0x9888, 0x021bc000 }, + { 0x9888, 0x041bc000 }, + { 0x9888, 0x1c1c003c }, + { 0x9888, 0x121c8000 }, + { 0x9888, 0x141c8000 }, + { 0x9888, 0x161c8000 }, + { 0x9888, 0x181c8000 }, + { 0x9888, 0x1a1c0800 }, + { 0x9888, 0x065b4000 }, + { 0x9888, 0x1a5c1000 }, + { 0x9888, 0x10600000 }, + { 0x9888, 0x04600000 }, + { 0x9888, 0x0c610044 }, + { 0x9888, 0x10610000 }, + { 0x9888, 0x06610000 }, + { 0x9888, 0x0c4c02a8 }, + { 0x9888, 0x084ca000 }, + { 0x9888, 0x0a4c002a }, + { 0x9888, 0x0c0da000 }, + { 0x9888, 0x0e0da000 }, + { 0x9888, 0x000d8000 }, + { 0x9888, 0x020da000 }, + { 0x9888, 0x040da000 }, + { 0x9888, 0x060d2000 }, + { 0x9888, 0x100f0154 }, + { 0x9888, 0x0c0f5000 }, + { 0x9888, 0x0e0f0055 }, + { 0x9888, 0x182c00aa }, + { 0x9888, 0x022c8000 }, + { 0x9888, 0x042c8000 }, + { 0x9888, 0x062c8000 }, + { 0x9888, 0x082c8000 }, + { 0x9888, 0x0a2c8000 }, + { 0x9888, 0x0c2cc000 }, + { 0x9888, 0x1190ffc0 }, + { 0x9888, 0x57900000 }, + { 0x9888, 0x49900420 }, + { 0x9888, 0x37900000 }, + { 0x9888, 0x33900000 }, + { 0x9888, 0x4b900021 }, + { 0x9888, 0x59900000 }, + { 0x9888, 0x51900000 }, + { 0x9888, 0x41900400 }, + { 0x9888, 0x43900421 }, + { 0x9888, 0x53900000 }, + { 0x9888, 0x45900040 }, +}; + +static int select_l3_1_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_l3_1; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_l3_1); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_l3_1; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_l3_1); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_l3_1; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_l3_1); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_l3_2[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x00800000 }, + { 0x2770, 0x00100070 }, + { 0x2774, 0x0000fff1 }, + { 0x2778, 0x00028002 }, + { 0x277c, 0x000087ff }, + { 0x2780, 0x00020002 }, + { 0x2784, 0x00008fff }, + { 0x2788, 0x00008002 }, + { 0x278c, 0x0000a7ff }, +}; + +static const struct i915_oa_reg flex_eu_config_l3_2[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_l3_2[] = { + { 0x9888, 0x126c02e0 }, + { 0x9888, 0x146c0001 }, + { 0x9888, 0x0a623400 }, + { 0x9888, 0x044e8000 }, + { 0x9888, 0x064e8000 }, + { 0x9888, 0x084e8000 }, + { 0x9888, 0x0a4e8000 }, + { 0x9888, 0x064f4000 }, + { 0x9888, 0x026c3324 }, + { 0x9888, 0x046c3422 }, + { 0x9888, 0x106c0000 }, + { 0x9888, 0x1a6c0000 }, + { 0x9888, 0x021bc000 }, + { 0x9888, 0x041bc000 }, + { 0x9888, 0x141c8000 }, + { 0x9888, 0x161c8000 }, + { 0x9888, 0x181c8000 }, + { 0x9888, 0x1a1c0800 }, + { 0x9888, 0x065b4000 }, + { 0x9888, 0x1a5c1000 }, + { 0x9888, 0x06614000 }, + { 0x9888, 0x0c620044 }, + { 0x9888, 0x10620000 }, + { 0x9888, 0x06620000 }, + { 0x9888, 0x084c8000 }, + { 0x9888, 0x0a4c002a }, + { 0x9888, 0x020da000 }, + { 0x9888, 0x040da000 }, + { 0x9888, 0x060d2000 }, + { 0x9888, 0x0c0f4000 }, + { 0x9888, 0x0e0f0055 }, + { 0x9888, 0x042c8000 }, + { 0x9888, 0x062c8000 }, + { 0x9888, 0x082c8000 }, + { 0x9888, 0x0a2c8000 }, + { 0x9888, 0x0c2cc000 }, + { 0x9888, 0x1190f800 }, + { 0x9888, 0x37900000 }, + { 0x9888, 0x51900000 }, + { 0x9888, 0x43900000 }, + { 0x9888, 0x53900000 }, + { 0x9888, 0x45900000 }, + { 0x9888, 0x33900000 }, +}; + +static int select_l3_2_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_l3_2; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_l3_2); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_l3_2; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_l3_2); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_l3_2; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_l3_2); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_l3_3[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x00800000 }, + { 0x2770, 0x00100070 }, + { 0x2774, 0x0000fff1 }, + { 0x2778, 0x00028002 }, + { 0x277c, 0x000087ff }, + { 0x2780, 0x00020002 }, + { 0x2784, 0x00008fff }, + { 0x2788, 0x00008002 }, + { 0x278c, 0x0000a7ff }, +}; + +static const struct i915_oa_reg flex_eu_config_l3_3[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_l3_3[] = { + { 0x9888, 0x126c4e80 }, + { 0x9888, 0x146c0000 }, + { 0x9888, 0x0a633400 }, + { 0x9888, 0x044e8000 }, + { 0x9888, 0x064e8000 }, + { 0x9888, 0x084e8000 }, + { 0x9888, 0x0a4e8000 }, + { 0x9888, 0x0c4e8000 }, + { 0x9888, 0x026c3321 }, + { 0x9888, 0x046c342f }, + { 0x9888, 0x106c0000 }, + { 0x9888, 0x1a6c2000 }, + { 0x9888, 0x021bc000 }, + { 0x9888, 0x041bc000 }, + { 0x9888, 0x061b4000 }, + { 0x9888, 0x141c8000 }, + { 0x9888, 0x161c8000 }, + { 0x9888, 0x181c8000 }, + { 0x9888, 0x1a1c1800 }, + { 0x9888, 0x06604000 }, + { 0x9888, 0x0c630044 }, + { 0x9888, 0x10630000 }, + { 0x9888, 0x06630000 }, + { 0x9888, 0x084c8000 }, + { 0x9888, 0x0a4c00aa }, + { 0x9888, 0x020da000 }, + { 0x9888, 0x040da000 }, + { 0x9888, 0x060d2000 }, + { 0x9888, 0x0c0f4000 }, + { 0x9888, 0x0e0f0055 }, + { 0x9888, 0x042c8000 }, + { 0x9888, 0x062c8000 }, + { 0x9888, 0x082c8000 }, + { 0x9888, 0x0a2c8000 }, + { 0x9888, 0x0c2c8000 }, + { 0x9888, 0x1190f800 }, + { 0x9888, 0x37900000 }, + { 0x9888, 0x51900000 }, + { 0x9888, 0x43900842 }, + { 0x9888, 0x53900000 }, + { 0x9888, 0x45900002 }, + { 0x9888, 0x33900000 }, +}; + +static int select_l3_3_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_l3_3; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_l3_3); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_l3_3; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_l3_3); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_l3_3; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_l3_3); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_rasterizer_and_pixel_backend[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0x30800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x00800000 }, + { 0x2770, 0x00000002 }, + { 0x2774, 0x0000efff }, + { 0x2778, 0x00006000 }, + { 0x277c, 0x0000f3ff }, +}; + +static const struct i915_oa_reg flex_eu_config_rasterizer_and_pixel_backend[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_rasterizer_and_pixel_backend[] = { + { 0x9888, 0x102f3800 }, + { 0x9888, 0x144d0500 }, + { 0x9888, 0x120d03c0 }, + { 0x9888, 0x140d03cf }, + { 0x9888, 0x0c0f0004 }, + { 0x9888, 0x0c4e4000 }, + { 0x9888, 0x042f0480 }, + { 0x9888, 0x082f0000 }, + { 0x9888, 0x022f0000 }, + { 0x9888, 0x0a4c0090 }, + { 0x9888, 0x064d0027 }, + { 0x9888, 0x004d0000 }, + { 0x9888, 0x000d0d40 }, + { 0x9888, 0x020d803f }, + { 0x9888, 0x040d8023 }, + { 0x9888, 0x100d0000 }, + { 0x9888, 0x060d2000 }, + { 0x9888, 0x020f0010 }, + { 0x9888, 0x000f0000 }, + { 0x9888, 0x0e0f0050 }, + { 0x9888, 0x0a2c8000 }, + { 0x9888, 0x0c2c8000 }, + { 0x9888, 0x1190fc00 }, + { 0x9888, 0x37900000 }, + { 0x9888, 0x51900000 }, + { 0x9888, 0x41901400 }, + { 0x9888, 0x43901485 }, + { 0x9888, 0x53900000 }, + { 0x9888, 0x45900001 }, + { 0x9888, 0x33900000 }, +}; + +static int select_rasterizer_and_pixel_backend_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_rasterizer_and_pixel_backend; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_rasterizer_and_pixel_backend); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_rasterizer_and_pixel_backend; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_rasterizer_and_pixel_backend); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_rasterizer_and_pixel_backend; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_rasterizer_and_pixel_backend); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_sampler[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0x70800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x00800000 }, + { 0x2770, 0x0000c000 }, + { 0x2774, 0x0000e7ff }, + { 0x2778, 0x00003000 }, + { 0x277c, 0x0000f9ff }, + { 0x2780, 0x00000c00 }, + { 0x2784, 0x0000fe7f }, +}; + +static const struct i915_oa_reg flex_eu_config_sampler[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_sampler[] = { + { 0x9888, 0x14152c00 }, + { 0x9888, 0x16150005 }, + { 0x9888, 0x121600a0 }, + { 0x9888, 0x14352c00 }, + { 0x9888, 0x16350005 }, + { 0x9888, 0x123600a0 }, + { 0x9888, 0x14552c00 }, + { 0x9888, 0x16550005 }, + { 0x9888, 0x125600a0 }, + { 0x9888, 0x062f6000 }, + { 0x9888, 0x022f2000 }, + { 0x9888, 0x0c4c0050 }, + { 0x9888, 0x0a4c0010 }, + { 0x9888, 0x0c0d8000 }, + { 0x9888, 0x0e0da000 }, + { 0x9888, 0x000d8000 }, + { 0x9888, 0x020da000 }, + { 0x9888, 0x040da000 }, + { 0x9888, 0x060d2000 }, + { 0x9888, 0x100f0350 }, + { 0x9888, 0x0c0fb000 }, + { 0x9888, 0x0e0f00da }, + { 0x9888, 0x182c0028 }, + { 0x9888, 0x0a2c8000 }, + { 0x9888, 0x022dc000 }, + { 0x9888, 0x042d4000 }, + { 0x9888, 0x0c138000 }, + { 0x9888, 0x0e132000 }, + { 0x9888, 0x0413c000 }, + { 0x9888, 0x1c140018 }, + { 0x9888, 0x0c157000 }, + { 0x9888, 0x0e150078 }, + { 0x9888, 0x10150000 }, + { 0x9888, 0x04162180 }, + { 0x9888, 0x02160000 }, + { 0x9888, 0x04174000 }, + { 0x9888, 0x0233a000 }, + { 0x9888, 0x04333000 }, + { 0x9888, 0x14348000 }, + { 0x9888, 0x16348000 }, + { 0x9888, 0x02357870 }, + { 0x9888, 0x10350000 }, + { 0x9888, 0x04360043 }, + { 0x9888, 0x02360000 }, + { 0x9888, 0x04371000 }, + { 0x9888, 0x0e538000 }, + { 0x9888, 0x00538000 }, + { 0x9888, 0x06533000 }, + { 0x9888, 0x1c540020 }, + { 0x9888, 0x12548000 }, + { 0x9888, 0x0e557000 }, + { 0x9888, 0x00557800 }, + { 0x9888, 0x10550000 }, + { 0x9888, 0x06560043 }, + { 0x9888, 0x02560000 }, + { 0x9888, 0x06571000 }, + { 0x9888, 0x1190ff80 }, + { 0x9888, 0x57900000 }, + { 0x9888, 0x49900000 }, + { 0x9888, 0x37900000 }, + { 0x9888, 0x33900000 }, + { 0x9888, 0x4b900060 }, + { 0x9888, 0x59900000 }, + { 0x9888, 0x51900000 }, + { 0x9888, 0x41900c00 }, + { 0x9888, 0x43900842 }, + { 0x9888, 0x53900000 }, + { 0x9888, 0x45900060 }, +}; + +static int select_sampler_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_sampler; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_sampler); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_sampler; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_sampler); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_sampler; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_sampler); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_tdl_1[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0xf0800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x30800000 }, + { 0x2770, 0x00000002 }, + { 0x2774, 0x00007fff }, + { 0x2778, 0x00000000 }, + { 0x277c, 0x00009fff }, + { 0x2780, 0x00000002 }, + { 0x2784, 0x0000efff }, + { 0x2788, 0x00000000 }, + { 0x278c, 0x0000f3ff }, + { 0x2790, 0x00000002 }, + { 0x2794, 0x0000fdff }, + { 0x2798, 0x00000000 }, + { 0x279c, 0x0000fe7f }, +}; + +static const struct i915_oa_reg flex_eu_config_tdl_1[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_tdl_1[] = { + { 0x9888, 0x12120000 }, + { 0x9888, 0x12320000 }, + { 0x9888, 0x12520000 }, + { 0x9888, 0x002f8000 }, + { 0x9888, 0x022f3000 }, + { 0x9888, 0x0a4c0015 }, + { 0x9888, 0x0c0d8000 }, + { 0x9888, 0x0e0da000 }, + { 0x9888, 0x000d8000 }, + { 0x9888, 0x020da000 }, + { 0x9888, 0x040da000 }, + { 0x9888, 0x060d2000 }, + { 0x9888, 0x100f03a0 }, + { 0x9888, 0x0c0ff000 }, + { 0x9888, 0x0e0f0095 }, + { 0x9888, 0x062c8000 }, + { 0x9888, 0x082c8000 }, + { 0x9888, 0x0a2c8000 }, + { 0x9888, 0x0c2d8000 }, + { 0x9888, 0x0e2d4000 }, + { 0x9888, 0x062d4000 }, + { 0x9888, 0x02108000 }, + { 0x9888, 0x0410c000 }, + { 0x9888, 0x02118000 }, + { 0x9888, 0x0411c000 }, + { 0x9888, 0x02121880 }, + { 0x9888, 0x041219b5 }, + { 0x9888, 0x00120000 }, + { 0x9888, 0x02134000 }, + { 0x9888, 0x04135000 }, + { 0x9888, 0x0c308000 }, + { 0x9888, 0x0e304000 }, + { 0x9888, 0x06304000 }, + { 0x9888, 0x0c318000 }, + { 0x9888, 0x0e314000 }, + { 0x9888, 0x06314000 }, + { 0x9888, 0x0c321a80 }, + { 0x9888, 0x0e320033 }, + { 0x9888, 0x06320031 }, + { 0x9888, 0x00320000 }, + { 0x9888, 0x0c334000 }, + { 0x9888, 0x0e331000 }, + { 0x9888, 0x06331000 }, + { 0x9888, 0x0e508000 }, + { 0x9888, 0x00508000 }, + { 0x9888, 0x02504000 }, + { 0x9888, 0x0e518000 }, + { 0x9888, 0x00518000 }, + { 0x9888, 0x02514000 }, + { 0x9888, 0x0e521880 }, + { 0x9888, 0x00521a80 }, + { 0x9888, 0x02520033 }, + { 0x9888, 0x0e534000 }, + { 0x9888, 0x00534000 }, + { 0x9888, 0x02531000 }, + { 0x9888, 0x1190ff80 }, + { 0x9888, 0x57900000 }, + { 0x9888, 0x49900800 }, + { 0x9888, 0x37900000 }, + { 0x9888, 0x33900000 }, + { 0x9888, 0x4b900062 }, + { 0x9888, 0x59900000 }, + { 0x9888, 0x51900000 }, + { 0x9888, 0x41900c00 }, + { 0x9888, 0x43900003 }, + { 0x9888, 0x53900000 }, + { 0x9888, 0x45900040 }, +}; + +static int select_tdl_1_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_tdl_1; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_tdl_1); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_tdl_1; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_tdl_1); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_tdl_1; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_tdl_1); + + return 0; +} + +static const struct i915_oa_reg b_counter_config_tdl_2[] = { + { 0x2740, 0x00000000 }, + { 0x2744, 0x00800000 }, + { 0x2710, 0x00000000 }, + { 0x2714, 0x00800000 }, + { 0x2720, 0x00000000 }, + { 0x2724, 0x00800000 }, +}; + +static const struct i915_oa_reg flex_eu_config_tdl_2[] = { + { 0xE458, 0x00005004 }, + { 0xE558, 0x00010003 }, + { 0xE658, 0x00012011 }, + { 0xE758, 0x00015014 }, + { 0xE45c, 0x00051050 }, + { 0xE55c, 0x00053052 }, + { 0xE65c, 0x00055054 }, +}; + +static const struct i915_oa_reg mux_config_tdl_2[] = { + { 0x9888, 0x12124d60 }, + { 0x9888, 0x12322e60 }, + { 0x9888, 0x12524d60 }, + { 0x9888, 0x022f3000 }, + { 0x9888, 0x0a4c0014 }, + { 0x9888, 0x000d8000 }, + { 0x9888, 0x020da000 }, + { 0x9888, 0x040da000 }, + { 0x9888, 0x060d2000 }, + { 0x9888, 0x0c0fe000 }, + { 0x9888, 0x0e0f0097 }, + { 0x9888, 0x082c8000 }, + { 0x9888, 0x0a2c8000 }, + { 0x9888, 0x002d8000 }, + { 0x9888, 0x062d4000 }, + { 0x9888, 0x0410c000 }, + { 0x9888, 0x0411c000 }, + { 0x9888, 0x04121fb7 }, + { 0x9888, 0x00120000 }, + { 0x9888, 0x04135000 }, + { 0x9888, 0x00308000 }, + { 0x9888, 0x06304000 }, + { 0x9888, 0x00318000 }, + { 0x9888, 0x06314000 }, + { 0x9888, 0x00321b80 }, + { 0x9888, 0x0632003f }, + { 0x9888, 0x00334000 }, + { 0x9888, 0x06331000 }, + { 0x9888, 0x0250c000 }, + { 0x9888, 0x0251c000 }, + { 0x9888, 0x02521fb7 }, + { 0x9888, 0x00520000 }, + { 0x9888, 0x02535000 }, + { 0x9888, 0x1190fc00 }, + { 0x9888, 0x37900000 }, + { 0x9888, 0x51900000 }, + { 0x9888, 0x41900800 }, + { 0x9888, 0x43900063 }, + { 0x9888, 0x53900000 }, + { 0x9888, 0x45900040 }, + { 0x9888, 0x33900000 }, +}; + +static int select_tdl_2_config(struct drm_i915_private *dev_priv) +{ + dev_priv->perf.oa.mux_regs = + mux_config_tdl_2; + dev_priv->perf.oa.mux_regs_len = + ARRAY_SIZE(mux_config_tdl_2); + + dev_priv->perf.oa.b_counter_regs = + b_counter_config_tdl_2; + dev_priv->perf.oa.b_counter_regs_len = + ARRAY_SIZE(b_counter_config_tdl_2); + + dev_priv->perf.oa.flex_regs = + flex_eu_config_tdl_2; + dev_priv->perf.oa.flex_regs_len = + ARRAY_SIZE(flex_eu_config_tdl_2); + + return 0; +} + int i915_oa_select_metric_set_skl(struct drm_i915_private *dev_priv) { dev_priv->perf.oa.mux_regs = NULL; @@ -240,6 +2374,34 @@ int i915_oa_select_metric_set_skl(struct drm_i915_private *dev_priv) switch (dev_priv->perf.oa.metrics_set) { case METRIC_SET_ID_RENDER_BASIC: return select_render_basic_config(dev_priv); + case METRIC_SET_ID_COMPUTE_BASIC: + return select_compute_basic_config(dev_priv); + case METRIC_SET_ID_RENDER_PIPE_PROFILE: + return select_render_pipe_profile_config(dev_priv); + case METRIC_SET_ID_MEMORY_READS: + return select_memory_reads_config(dev_priv); + case METRIC_SET_ID_MEMORY_WRITES: + return select_memory_writes_config(dev_priv); + case METRIC_SET_ID_COMPUTE_EXTENDED: + return select_compute_extended_config(dev_priv); + case METRIC_SET_ID_COMPUTE_L3_CACHE: + return select_compute_l3_cache_config(dev_priv); + case METRIC_SET_ID_HDC_AND_SF: + return select_hdc_and_sf_config(dev_priv); + case METRIC_SET_ID_L3_1: + return select_l3_1_config(dev_priv); + case METRIC_SET_ID_L3_2: + return select_l3_2_config(dev_priv); + case METRIC_SET_ID_L3_3: + return select_l3_3_config(dev_priv); + case METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND: + return select_rasterizer_and_pixel_backend_config(dev_priv); + case METRIC_SET_ID_SAMPLER: + return select_sampler_config(dev_priv); + case METRIC_SET_ID_TDL_1: + return select_tdl_1_config(dev_priv); + case METRIC_SET_ID_TDL_2: + return select_tdl_2_config(dev_priv); default: return -ENODEV; } @@ -267,6 +2429,314 @@ static struct attribute_group group_render_basic = { .attrs = attrs_render_basic, }; +static ssize_t +show_compute_basic_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_BASIC); +} + +static struct device_attribute dev_attr_compute_basic_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_compute_basic_id, + .store = NULL, +}; + +static struct attribute *attrs_compute_basic[] = { + &dev_attr_compute_basic_id.attr, + NULL, +}; + +static struct attribute_group group_compute_basic = { + .name = "c9c7ace5-614a-4f8e-90c7-30064c36cad2", + .attrs = attrs_compute_basic, +}; + +static ssize_t +show_render_pipe_profile_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_RENDER_PIPE_PROFILE); +} + +static struct device_attribute dev_attr_render_pipe_profile_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_render_pipe_profile_id, + .store = NULL, +}; + +static struct attribute *attrs_render_pipe_profile[] = { + &dev_attr_render_pipe_profile_id.attr, + NULL, +}; + +static struct attribute_group group_render_pipe_profile = { + .name = "99797dc2-b48f-4d83-b973-613cff01202b", + .attrs = attrs_render_pipe_profile, +}; + +static ssize_t +show_memory_reads_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_READS); +} + +static struct device_attribute dev_attr_memory_reads_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_memory_reads_id, + .store = NULL, +}; + +static struct attribute *attrs_memory_reads[] = { + &dev_attr_memory_reads_id.attr, + NULL, +}; + +static struct attribute_group group_memory_reads = { + .name = "afa148ea-77fb-48ee-b8f8-e5e971ecf589", + .attrs = attrs_memory_reads, +}; + +static ssize_t +show_memory_writes_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_MEMORY_WRITES); +} + +static struct device_attribute dev_attr_memory_writes_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_memory_writes_id, + .store = NULL, +}; + +static struct attribute *attrs_memory_writes[] = { + &dev_attr_memory_writes_id.attr, + NULL, +}; + +static struct attribute_group group_memory_writes = { + .name = "bfce7061-e6f1-4a78-bed8-c9cc69af70f9", + .attrs = attrs_memory_writes, +}; + +static ssize_t +show_compute_extended_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_EXTENDED); +} + +static struct device_attribute dev_attr_compute_extended_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_compute_extended_id, + .store = NULL, +}; + +static struct attribute *attrs_compute_extended[] = { + &dev_attr_compute_extended_id.attr, + NULL, +}; + +static struct attribute_group group_compute_extended = { + .name = "c35ddcab-b1f2-452f-969a-a8209d531a00", + .attrs = attrs_compute_extended, +}; + +static ssize_t +show_compute_l3_cache_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_COMPUTE_L3_CACHE); +} + +static struct device_attribute dev_attr_compute_l3_cache_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_compute_l3_cache_id, + .store = NULL, +}; + +static struct attribute *attrs_compute_l3_cache[] = { + &dev_attr_compute_l3_cache_id.attr, + NULL, +}; + +static struct attribute_group group_compute_l3_cache = { + .name = "2b0d0c83-706a-4cb6-b55e-d6bcf51fa6d3", + .attrs = attrs_compute_l3_cache, +}; + +static ssize_t +show_hdc_and_sf_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_HDC_AND_SF); +} + +static struct device_attribute dev_attr_hdc_and_sf_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_hdc_and_sf_id, + .store = NULL, +}; + +static struct attribute *attrs_hdc_and_sf[] = { + &dev_attr_hdc_and_sf_id.attr, + NULL, +}; + +static struct attribute_group group_hdc_and_sf = { + .name = "d084f6a9-f706-4b74-b98c-65daa5340517", + .attrs = attrs_hdc_and_sf, +}; + +static ssize_t +show_l3_1_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_L3_1); +} + +static struct device_attribute dev_attr_l3_1_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_l3_1_id, + .store = NULL, +}; + +static struct attribute *attrs_l3_1[] = { + &dev_attr_l3_1_id.attr, + NULL, +}; + +static struct attribute_group group_l3_1 = { + .name = "c7ed493c-54ff-4152-baf4-07e31e7a24cb", + .attrs = attrs_l3_1, +}; + +static ssize_t +show_l3_2_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_L3_2); +} + +static struct device_attribute dev_attr_l3_2_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_l3_2_id, + .store = NULL, +}; + +static struct attribute *attrs_l3_2[] = { + &dev_attr_l3_2_id.attr, + NULL, +}; + +static struct attribute_group group_l3_2 = { + .name = "43ad9300-198a-4734-8f3a-2a2151b9dab6", + .attrs = attrs_l3_2, +}; + +static ssize_t +show_l3_3_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_L3_3); +} + +static struct device_attribute dev_attr_l3_3_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_l3_3_id, + .store = NULL, +}; + +static struct attribute *attrs_l3_3[] = { + &dev_attr_l3_3_id.attr, + NULL, +}; + +static struct attribute_group group_l3_3 = { + .name = "ccfce3f2-6c63-4630-a043-f2a0243fed8f", + .attrs = attrs_l3_3, +}; + +static ssize_t +show_rasterizer_and_pixel_backend_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_RASTERIZER_AND_PIXEL_BACKEND); +} + +static struct device_attribute dev_attr_rasterizer_and_pixel_backend_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_rasterizer_and_pixel_backend_id, + .store = NULL, +}; + +static struct attribute *attrs_rasterizer_and_pixel_backend[] = { + &dev_attr_rasterizer_and_pixel_backend_id.attr, + NULL, +}; + +static struct attribute_group group_rasterizer_and_pixel_backend = { + .name = "2e564b28-98fa-42a0-8bbc-7915de3cc03c", + .attrs = attrs_rasterizer_and_pixel_backend, +}; + +static ssize_t +show_sampler_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_SAMPLER); +} + +static struct device_attribute dev_attr_sampler_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_sampler_id, + .store = NULL, +}; + +static struct attribute *attrs_sampler[] = { + &dev_attr_sampler_id.attr, + NULL, +}; + +static struct attribute_group group_sampler = { + .name = "a305533f-7e36-4fb6-8749-c6280bce3457", + .attrs = attrs_sampler, +}; + +static ssize_t +show_tdl_1_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_1); +} + +static struct device_attribute dev_attr_tdl_1_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_tdl_1_id, + .store = NULL, +}; + +static struct attribute *attrs_tdl_1[] = { + &dev_attr_tdl_1_id.attr, + NULL, +}; + +static struct attribute_group group_tdl_1 = { + .name = "34ecd59f-6b52-4004-916f-afe9530a0442", + .attrs = attrs_tdl_1, +}; + +static ssize_t +show_tdl_2_id(struct device *kdev, struct device_attribute *attr, char *buf) +{ + return sprintf(buf, "%d\n", METRIC_SET_ID_TDL_2); +} + +static struct device_attribute dev_attr_tdl_2_id = { + .attr = { .name = "id", .mode = S_IRUGO }, + .show = show_tdl_2_id, + .store = NULL, +}; + +static struct attribute *attrs_tdl_2[] = { + &dev_attr_tdl_2_id.attr, + NULL, +}; + +static struct attribute_group group_tdl_2 = { + .name = "ee1990d9-6e93-4c7c-aa9e-b40e1ec4d41b", + .attrs = attrs_tdl_2, +}; + int i915_perf_init_sysfs_skl(struct drm_i915_private *dev_priv) { @@ -275,9 +2745,79 @@ i915_perf_init_sysfs_skl(struct drm_i915_private *dev_priv) ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_basic); if (ret) goto error_render_basic; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_basic); + if (ret) + goto error_compute_basic; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); + if (ret) + goto error_render_pipe_profile; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_reads); + if (ret) + goto error_memory_reads; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_memory_writes); + if (ret) + goto error_memory_writes; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_extended); + if (ret) + goto error_compute_extended; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); + if (ret) + goto error_compute_l3_cache; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); + if (ret) + goto error_hdc_and_sf; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_1); + if (ret) + goto error_l3_1; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_2); + if (ret) + goto error_l3_2; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_l3_3); + if (ret) + goto error_l3_3; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); + if (ret) + goto error_rasterizer_and_pixel_backend; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_sampler); + if (ret) + goto error_sampler; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_1); + if (ret) + goto error_tdl_1; + ret = sysfs_create_group(dev_priv->perf.metrics_kobj, &group_tdl_2); + if (ret) + goto error_tdl_2; return 0; +error_tdl_2: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); +error_tdl_1: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); +error_sampler: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); +error_rasterizer_and_pixel_backend: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); +error_l3_3: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); +error_l3_2: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); +error_l3_1: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); +error_hdc_and_sf: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); +error_compute_l3_cache: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); +error_compute_extended: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); +error_memory_writes: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); +error_memory_reads: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); +error_render_pipe_profile: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); +error_compute_basic: + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); error_render_basic: return ret; } @@ -286,4 +2826,18 @@ void i915_perf_deinit_sysfs_skl(struct drm_i915_private *dev_priv) { sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_basic); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_basic); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_render_pipe_profile); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_reads); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_memory_writes); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_extended); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_compute_l3_cache); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_hdc_and_sf); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_1); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_2); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_l3_3); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_rasterizer_and_pixel_backend); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_sampler); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_1); + sysfs_remove_group(dev_priv->perf.metrics_kobj, &group_tdl_2); } From 42050b283dd124c13358de0b63f1b98be71bdb73 Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Fri, 19 Feb 2016 14:20:30 +0000 Subject: [PATCH 20/21] drm/i915: Add DRM_I915_PERF_OA_ENABLE property --- drivers/gpu/drm/i915/i915_drv.h | 2 ++ drivers/gpu/drm/i915/i915_perf.c | 6 ++++++ include/uapi/drm/i915_drm.h | 6 ++++++ 3 files changed, 14 insertions(+) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index c409c8f1db38ee..3f62e4269d7fc4 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2083,6 +2083,8 @@ struct drm_i915_private { struct i915_oa_ops ops; const struct i915_oa_format *oa_formats; int n_builtin_sets; + + bool enable_rc6; } oa; } perf; diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index c5447b4382907d..d74704cb088b19 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -93,6 +93,7 @@ struct perf_open_properties int oa_format; bool oa_periodic; u32 oa_period_exponent; + bool enable_rc6; }; static bool gen8_oa_buffer_is_empty(struct drm_i915_private *dev_priv) @@ -898,6 +899,8 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, dev_priv->perf.oa.exclusive_stream = stream; + dev_priv->perf.oa.enable_rc6 = props->enable_rc6; + /* PRM - observability performance counters: * * OACONTROL, performance counter enable, note: @@ -1480,6 +1483,9 @@ static int read_properties_unlocked(struct drm_i915_private *dev_priv, props->oa_periodic = true; props->oa_period_exponent = value; break; + case DRM_I915_PERF_OA_ENABLE_RC6: + props->enable_rc6 = true; + break; case DRM_I915_PERF_PROP_MAX: BUG(); } diff --git a/include/uapi/drm/i915_drm.h b/include/uapi/drm/i915_drm.h index 4a6789548d7e42..4e049384a0883c 100644 --- a/include/uapi/drm/i915_drm.h +++ b/include/uapi/drm/i915_drm.h @@ -1189,6 +1189,12 @@ enum drm_i915_perf_property_id { */ DRM_I915_PERF_OA_EXPONENT_PROP, + /** + * A value of 1 requests that RC6 not be disabled, by default this will + * disabled + */ + DRM_I915_PERF_OA_ENABLE_RC6, + DRM_I915_PERF_PROP_MAX /* non-ABI */ }; From 5e6f54beca8bfd5f7fc5887c6b877c3ebebe5aaf Mon Sep 17 00:00:00 2001 From: Matthew Auld Date: Fri, 19 Feb 2016 14:22:17 +0000 Subject: [PATCH 21/21] drm/i915: OA RC6 WA BB --- drivers/gpu/drm/i915/i915_drv.h | 4 + drivers/gpu/drm/i915/i915_perf.c | 153 +++++++++++++++++++++++- drivers/gpu/drm/i915/intel_lrc.c | 59 ++++++++- drivers/gpu/drm/i915/intel_ringbuffer.h | 3 +- 4 files changed, 210 insertions(+), 9 deletions(-) diff --git a/drivers/gpu/drm/i915/i915_drv.h b/drivers/gpu/drm/i915/i915_drv.h index 3f62e4269d7fc4..340b6bc570e63f 100644 --- a/drivers/gpu/drm/i915/i915_drv.h +++ b/drivers/gpu/drm/i915/i915_drv.h @@ -2085,6 +2085,9 @@ struct drm_i915_private { int n_builtin_sets; bool enable_rc6; + struct drm_i915_gem_object *ctx_wa_obj_buf[2]; + int ctx_wa_idx; + bool dirty_wa_obj; } oa; } perf; @@ -3330,6 +3333,7 @@ void i915_oa_context_pin_notify(struct drm_i915_private *dev_priv, struct intel_context *context); void i915_oa_legacy_ctx_switch_notify(struct drm_i915_gem_request *req); void i915_oa_update_reg_state(struct intel_engine_cs *ring, uint32_t *reg_state); +struct drm_i915_gem_object *i915_oa_ctx_wa_obj(struct drm_i915_private *dev_priv); /* i915_gem_evict.c */ int __must_check i915_gem_evict_something(struct drm_device *dev, diff --git a/drivers/gpu/drm/i915/i915_perf.c b/drivers/gpu/drm/i915/i915_perf.c index d74704cb088b19..1c1db7562a9ad8 100644 --- a/drivers/gpu/drm/i915/i915_perf.c +++ b/drivers/gpu/drm/i915/i915_perf.c @@ -416,8 +416,10 @@ static void i915_oa_stream_destroy(struct i915_perf_stream *stream) free_oa_buffer(dev_priv); - intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); - intel_runtime_pm_put(dev_priv); + if (!dev_priv->perf.oa.enable_rc6) { + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); + intel_runtime_pm_put(dev_priv); + } dev_priv->perf.oa.exclusive_stream = NULL; } @@ -834,6 +836,119 @@ static void i915_oa_stream_disable(struct i915_perf_stream *stream) hrtimer_cancel(&dev_priv->perf.oa.poll_check_timer); } +struct drm_i915_gem_object * +i915_oa_ctx_wa_obj(struct drm_i915_private *dev_priv) +{ + struct drm_i915_gem_object *ctx_wa_obj = + dev_priv->perf.oa.ctx_wa_obj_buf[dev_priv->perf.oa.ctx_wa_idx]; + + if (dev_priv->perf.oa.dirty_wa_obj) { + dev_priv->perf.oa.dirty_wa_obj = false; + dev_priv->perf.oa.ctx_wa_idx = !dev_priv->perf.oa.ctx_wa_idx; + } + + return ctx_wa_obj; +} + +static int init_ctx_wa_obj_buf(struct drm_i915_private *dev_priv) +{ + struct intel_engine_cs *ring = &dev_priv->ring[RCS]; + struct page *page = i915_gem_object_get_page(ring->wa_ctx.obj, 0); + uint32_t *data = kmap_atomic(page); + int ret; + + dev_priv->perf.oa.ctx_wa_obj_buf[0] = + i915_gem_object_create_from_data(dev_priv->dev, data, + PAGE_SIZE); + kunmap_atomic(data); + + if (!dev_priv->perf.oa.ctx_wa_obj_buf[0]) { + DRM_DEBUG_DRIVER("failed to allocate rc6 wa bb\n"); + return -ENOMEM; + } + + ret = i915_gem_obj_ggtt_pin(dev_priv->perf.oa.ctx_wa_obj_buf[0], + PAGE_SIZE, 0); + if (ret) { + DRM_DEBUG_DRIVER("failed to pin rc6 wa bb\n"); + + mutex_lock(&dev_priv->dev->struct_mutex); + drm_gem_object_unreference(&dev_priv->perf.oa.ctx_wa_obj_buf[0]->base); + mutex_unlock(&dev_priv->dev->struct_mutex); + + dev_priv->perf.oa.ctx_wa_obj_buf[0] = NULL; + + return ret; + } + + dev_priv->perf.oa.ctx_wa_obj_buf[1] = ring->wa_ctx.obj; + + return 0; +} + +static int init_rc6_wa_bb(struct drm_i915_private *dev_priv) +{ + struct page *page; + uint32_t *batch; + int ret, index, i, num_regs; + struct intel_engine_cs *ring = &dev_priv->ring[RCS]; + struct drm_i915_gem_object *ctx_wa_obj; + + if (!dev_priv->perf.oa.ctx_wa_obj_buf[0]) { + ret = init_ctx_wa_obj_buf(dev_priv); + if (ret) + return ret; + } + + dev_priv->perf.oa.dirty_wa_obj = true; + + ctx_wa_obj = dev_priv->perf.oa.ctx_wa_obj_buf[dev_priv->perf.oa.ctx_wa_idx]; + + page = i915_gem_object_get_page(ctx_wa_obj, 0); + batch = kmap_atomic(page); + + index = ring->wa_ctx.per_ctx_rc6.offset; + + batch[index++] = MI_NOOP; + batch[index++] = MI_LOAD_REGISTER_IMM(1); + batch[index++] = GDT_CHICKEN_BITS; + batch[index++] = 0xA0; + + for (i = 0; i < dev_priv->perf.oa.mux_regs_len; i++) { + /* x <= 16 must hold with MI_LOAD_REGISTER_IMM(x) */ + if (i % 16 == 0) { + num_regs = min(16, dev_priv->perf.oa.mux_regs_len - i); + batch[index++] = MI_NOOP; + batch[index++] = MI_LOAD_REGISTER_IMM(num_regs); + } + + batch[index++] = dev_priv->perf.oa.mux_regs[i].addr; + batch[index++] = dev_priv->perf.oa.mux_regs[i].value; + } + + batch[index++] = MI_NOOP; + batch[index++] = MI_LOAD_REGISTER_IMM(1); + batch[index++] = GDT_CHICKEN_BITS; + batch[index++] = 0x80; + + for (i = 0; i < dev_priv->perf.oa.b_counter_regs_len; i++) { + if (i % 16 == 0) { + num_regs = min(16, dev_priv->perf.oa.b_counter_regs_len - i); + batch[index++] = MI_NOOP; + batch[index++] = MI_LOAD_REGISTER_IMM(num_regs); + } + + batch[index++] = dev_priv->perf.oa.b_counter_regs[i].addr; + batch[index++] = dev_priv->perf.oa.b_counter_regs[i].value; + } + + batch[index++] = MI_BATCH_BUFFER_END; + + kunmap_atomic(batch); + + return 0; +} + static int i915_oa_stream_init(struct i915_perf_stream *stream, struct drm_i915_perf_open_param *param, struct perf_open_properties *props) @@ -912,12 +1027,38 @@ static int i915_oa_stream_init(struct i915_perf_stream *stream, * * In our case we are expected that taking pm + FORCEWAKE * references will effectively disable RC6. + * + * For BDW+, RC6 + OA is not plagued by this issue, so we instead + * try to leave RC6 enabled. One caveat though is that we now need + * to restore the NOA MUX configuration upon exiting RC6. */ - intel_runtime_pm_get(dev_priv); - intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); + + /* We must disable RC6 until we are able to correctly setup the RC6 WA + * BB, if requested, otherwise we could potentially loose some OA state + * which is not automatically restored as part of the OA power context */ + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); + intel_runtime_pm_put(dev_priv); dev_priv->perf.oa.ops.enable_metric_set(dev_priv); + if (props->enable_rc6) { + if (IS_BROADWELL(dev_priv->dev)) { + ret = init_rc6_wa_bb(dev_priv); + if (ret) + DRM_ERROR("Failed to enable RC6 with OA\n"); + } else { + DRM_ERROR("OA with RC6 enabled is not supported on this" + " platform\n"); + ret = -EINVAL; + } + + intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); + intel_runtime_pm_put(dev_priv); + + if (ret) + return ret; + } + stream->destroy = i915_oa_stream_destroy; stream->enable = i915_oa_stream_enable; stream->disable = i915_oa_stream_disable; @@ -1665,6 +1806,10 @@ void i915_perf_init(struct drm_device *dev) dev_priv->perf.initialized = true; + dev_priv->perf.oa.ctx_wa_obj_buf[0] = NULL; + dev_priv->perf.oa.ctx_wa_idx = 0; + dev_priv->perf.oa.dirty_wa_obj = false; + return; sysfs_error: diff --git a/drivers/gpu/drm/i915/intel_lrc.c b/drivers/gpu/drm/i915/intel_lrc.c index 4789555aa80501..bb8df80515a659 100644 --- a/drivers/gpu/drm/i915/intel_lrc.c +++ b/drivers/gpu/drm/i915/intel_lrc.c @@ -1286,8 +1286,6 @@ static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring, * * The number of DWORDS written are returned using this field. * - * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding - * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant. */ static int gen8_init_perctx_bb(struct intel_engine_cs *ring, struct i915_wa_ctx_bb *wa_ctx, @@ -1299,7 +1297,9 @@ static int gen8_init_perctx_bb(struct intel_engine_cs *ring, /* WaDisableCtxRestoreArbitration:bdw,chv */ wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); - wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); + /* Pad to end of cacheline */ + while (index % CACHELINE_DWORDS) + wa_ctx_emit(batch, index, MI_NOOP); return wa_ctx_end(wa_ctx, *offset = index, 1); } @@ -1354,6 +1354,33 @@ static int gen9_init_perctx_bb(struct intel_engine_cs *ring, (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); + /* Pad to end of cacheline */ + while (index % CACHELINE_DWORDS) + wa_ctx_emit(batch, index, MI_NOOP); + + return wa_ctx_end(wa_ctx, *offset = index, 1); +} + + +/* + * This batch is started immediately after per_ctx batch. Since we ensure + * that per_ctx ends on a cacheline this batch is aligned automatically. + * + * This batch is a placeholder which we can potentially later use to the + * restore the NOA MUX configuration, the size and contents of which we do not + * know until we are able to configure the OA unit. + * + * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add + * padding to align it with cacheline as padding after MI_BATCH_BUFFER_END is + * redundant + */ +static int init_oa_rc6_wa_bb(struct intel_engine_cs *ring, + struct i915_wa_ctx_bb *wa_ctx, + uint32_t *const batch, + uint32_t *offset) +{ + uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); + wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); return wa_ctx_end(wa_ctx, *offset = index, 1); @@ -1436,6 +1463,7 @@ static int intel_init_workaround_bb(struct intel_engine_cs *ring) &offset); if (ret) goto out; + } else if (INTEL_INFO(ring->dev)->gen == 9) { ret = gen9_init_indirectctx_bb(ring, &wa_ctx->indirect_ctx, @@ -1452,6 +1480,11 @@ static int intel_init_workaround_bb(struct intel_engine_cs *ring) goto out; } + ret = init_oa_rc6_wa_bb(ring, + &wa_ctx->per_ctx_rc6, + batch, + &offset); + out: kunmap_atomic(batch); if (ret) @@ -2305,7 +2338,25 @@ populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_o reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0; if (ring->wa_ctx.obj) { struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx; - uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj); + struct drm_i915_gem_object *wa_ctx_obj = wa_ctx->obj; + uint32_t ggtt_offset; + + /* To support RC6 while capturing metrics with the OA + * unit, we need to restore the NOA Mux configuration + * upon existing RC6, while using the CTX_WA_PTR would + * be a better solution here, there is reportadly HW bug + * on SKL+ where the batch is not always executed, so + * using the per-ctx batch seems to be next best solution + * + * Given that we need to able to update the per-ctx + * batch on the fly with the NOA Mux config, we + * double-buffer the batch, as the batch could + * potentially still be in use by a restore in progress + * */ + if (dev_priv->perf.oa.enable_rc6) + wa_ctx_obj = i915_oa_ctx_wa_obj(dev_priv); + + ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx_obj); reg_state[CTX_RCS_INDIRECT_CTX+1] = (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) | diff --git a/drivers/gpu/drm/i915/intel_ringbuffer.h b/drivers/gpu/drm/i915/intel_ringbuffer.h index 302882c2b77426..18affa9228777f 100644 --- a/drivers/gpu/drm/i915/intel_ringbuffer.h +++ b/drivers/gpu/drm/i915/intel_ringbuffer.h @@ -139,7 +139,8 @@ struct i915_ctx_workarounds { struct i915_wa_ctx_bb { u32 offset; u32 size; - } indirect_ctx, per_ctx; + } indirect_ctx, per_ctx, per_ctx_rc6; + struct drm_i915_gem_object *obj; };