Add store instruction

Author: scopeInfinity

planner/instruction.py

@@ -69,17 +69,12 @@ def from_binary(cls, bin: List[int]):
         return cls(val)
 
 class MBlockSelector_stage3(Enum):
-    '''
-    bits: [1  as is_no_write][.][.]
-    bits: [0][ 0 ][io_write else ram_write]
-    bits: [0][ 1 ][pc_next else pc_next_if_eq]
-
-    '''
-    NO_WRITE           = 4
-    VRW_SOURCE_RAM     = 0
-    VRW_SOURCE_IO      = 1
-    PC_NEXT            = 2
-    PC_NEXT_IF_ZERO    = 3
+    NO_WRITE           = 0
+    VRW_SOURCE_RAM     = 1
+    VRW_SOURCE_IO      = 2
+    VRW_VALUE_RAM      = 3
+    PC_NEXT            = 4
+    PC_NEXT_IF_ZERO    = 5
 
     @classmethod
     def wire(cls, sel) -> List:
@@ -312,6 +307,11 @@ def size(self):
                                          MBlockSelector_stage2.VR_VALUE_RAM,
                                          MBlockSelector_stage3.VRW_SOURCE_RAM,
                                          ALU.PASS_RW)),
+    ParserInstruction("STORE", unit.Operand.DADDRESS, unit.Operand.ADDRESS,
+                      EncodedInstruction(MBlockSelector_stage1.VR_SOURCE_RAM,
+                                         MBlockSelector_stage2.VRW_SOURCE_RAM,
+                                         MBlockSelector_stage3.VRW_VALUE_RAM,
+                                         ALU.PASS_R)),
     ParserInstruction("CMP", unit.Operand.ADDRESS, unit.Operand.ADDRESS,
                       EncodedInstruction(MBlockSelector_stage1.VR_SOURCE_RAM,
                                          MBlockSelector_stage2.VRW_SOURCE_RAM,

planner/instruction_test.py

@@ -19,6 +19,8 @@ def test_all_instructions_validation(self):
 
             ("load R3, [R1]", "LOAD [12], [[4]]"),
             ("load R4, [[50]]", "LOAD [16], [[50]]"),
+            ("store [R1], R3", "STORE [[4]], [12]"),
+            ("store [[50]], R4", "STORE [[50]], [16]"),
 
             ("add  R0, [10]", "ADD  [0], [10]"),
             ("addc R1, 10",   "ADDC [4], 10"),

planner/sim/bin_parser.py

@@ -102,13 +102,16 @@ def m_fetch_and_store_stage3(
         self,
         output_devices: List[devices.Device],
         vw_value: int,
+        vrw_value: int,
         vrw_source: int,
         sel: instruction.MBlockSelector_stage3):
         assert vrw_source >= 0 and vrw_source < 256
         if sel == instruction.MBlockSelector_stage3.NO_WRITE:
             return
         if sel == instruction.MBlockSelector_stage3.VRW_SOURCE_RAM:
             return self.write_ram(vrw_source, 4, vw_value)  # write using 8-bit address
+        if sel == instruction.MBlockSelector_stage3.VRW_VALUE_RAM:
+            return self.write_ram(vrw_value, 4, vw_value)  # write using 8-bit address
         if sel == instruction.MBlockSelector_stage3.VRW_SOURCE_IO:
             assert vw_value >= 0 and vw_value < (1<<32)
             output_devices[vrw_source].update(vw_value)
@@ -186,6 +189,7 @@ def step(self):
         self.m_fetch_and_store_stage3(
             self.output_devices,
             vw_value,
+            vrw_value,
             vrw_source,
             mblock_s3)
 

planner/sim/bin_parser_test.py

@@ -31,7 +31,10 @@
     add  R1, R4
     jmp loop_start
 loop_end:
-    out 0x06, R1
+    # answer is in R1
+    movc R2, 12 # memory address of R3
+    store [R2], R1
+    out 0x06, R3
 loop_exit:
     jmp loop_exit
 

programs/boot_sequence.not_ready_asm renamed to programs/boot_sequence.asm

@@ -1,3 +1,4 @@
+# TODO: This is not ready yet
 #  Program
 #       ROM[BootSequence]
 #
@@ -7,7 +8,7 @@
 #  * ROM[Program] address-line at 0
 #  Really small program to copy ROM[Program] to RAM[Program]
 
-PROGRAM_START equ 0x20
+PROGRAM_ORG equ 0x40
 
 section .text
   main:
@@ -17,18 +18,19 @@ section .text
     in   R0, 0   # io -> ram
     movc R8, 1
 
-    movc R2, PROGRAM_START    # const -> ram
+    movc R2, PROGRAM_ORG      # const -> ram
     movc R1, 1                # const -> ram
   _copy_more:
     out 0, R1                # ram -> io
     in  R3, 0                # io -> ram
     add R1, R8
     add R2, R8
-    store R2, R3             # ram -> ram
+    store [R2], R3             # ram -> ram
     # bytes left to copy
-    sub R0, 1
+    subc R0, 1
     cmp R0, R9
-    jneq _copy_more
+    jz _copy_completed
+    jmp _copy_more
 
   _copy_completed:
     jmp _copy_completed