continuation of multi-shard + ram bus

[hero78119]

To deal with > 1 shards and satisfy offline memory constrain
related to #1061, #1063, #699, #698, #697, #696, #700

change scope

• separate mem bus to read/write 2 different map
• add new public input
• integrate local init chip
• integrate local final chip
• shift opcode & mem record to shard ts
• integrate mem bus chip
• refactor mock prover mock proving

benchmarks

bench on single chunk
with fibonacci on CPU: 5900XT 32 cores, 64GB RAM

Benchmark	Median Time (s)	Median Change (%)
fibonacci_max_steps_1048576	2.8142	+1.54% (Change within noise threshold)
fibonacci_max_steps_2097152	4.9337	+1.05% (Change within noise threshold)
fibonacci_max_steps_4194304	9.1971	-3.21% (Change within noise threshold)

which shows no performance impact

[hero78119]

multi shards and continuation support

This PR add Shard: meta info BEFORE emulate, and ShardContext: meta info AFTER emulate. ShardContext was passed into opcode & table circuit, and each memory access (read/write) was categorized via ShardContext and differentiate it's within or outside chunk

[hero78119]

shards mem records tracking

refer ceno_emul/src/chunked_vec.rs
To tracking a memory write record being accessed in the future or not, a data structure ChunkedVec was being added in emulator to track future access toward this record. As in each cycle there used to be something write, so the cycle pattern is pretty dense, we choose implement dynamic extended vector so leverage index access with a slightly waste of space.

[kunxian-xia]

LGTM 🎉