From 537e8b8e99ccfdce70601299ea0ff0a4f36e9b0a Mon Sep 17 00:00:00 2001
From: sutichunxiao <15586784538@163.com>
Date: Tue, 30 Oct 2018 13:59:29 +0800
Subject: [PATCH 1/3] Modify the project configuration to make the project
compile
---
ports/stm32f10x/Backup of bacnet.ewp | 2175 +++++++++++++
ports/stm32f10x/CMSIS/core_cmFunc.h | 609 ++++
ports/stm32f10x/CMSIS/core_cmInstr.h | 585 ++++
ports/stm32f10x/Debug/Exe/c.out | Bin 0 -> 606752 bytes
ports/stm32f10x/Debug/Obj/abort.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/abort.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/apdu.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/apdu.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/automac.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/automac.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/bacaddr.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/bacaddr.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/bacapp.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/bacapp.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/bacdcode.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/bacdcode.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/bacerror.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/bacerror.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/bacint.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/bacint.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/bacnet.pbd | Bin 0 -> 23 bytes
ports/stm32f10x/Debug/Obj/bacnet.pbd.browse | Bin 0 -> 23 bytes
ports/stm32f10x/Debug/Obj/bacnet.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/bacnet.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/bacreal.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/bacreal.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/bacstr.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/bacstr.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/bo.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/bo.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/crc.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/crc.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/dcc.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/dcc.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/device.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/device.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/dlmstp.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/dlmstp.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/fifo.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/fifo.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/h_dcc.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/h_dcc.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/h_npdu.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/h_npdu.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/h_rd.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/h_rd.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/h_rp.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/h_rp.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/h_rpm.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/h_rpm.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/h_whohas.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/h_whohas.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/h_whois.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/h_whois.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/h_wp.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/h_wp.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/iam.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/iam.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/ihave.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/ihave.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/led.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/led.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/main.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/main.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/memcopy.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/memcopy.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/noserv.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/noserv.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/npdu.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/npdu.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/proplist.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/proplist.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/rd.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/rd.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/reject.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/reject.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/ringbuf.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/ringbuf.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/rp.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/rp.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/rpm.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/rpm.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/rs485.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/rs485.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/s_iam.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/s_iam.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/s_ihave.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/s_ihave.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/stm32f10x_adc.pbi | Bin 0 -> 38 bytes
.../Debug/Obj/stm32f10x_adc.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/stm32f10x_bkp.pbi | Bin 0 -> 38 bytes
.../Debug/Obj/stm32f10x_bkp.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/stm32f10x_can.pbi | Bin 0 -> 38 bytes
.../Debug/Obj/stm32f10x_can.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/stm32f10x_cec.pbi | Bin 0 -> 38 bytes
.../Debug/Obj/stm32f10x_cec.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/stm32f10x_crc.pbi | Bin 0 -> 38 bytes
.../Debug/Obj/stm32f10x_crc.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/stm32f10x_dac.pbi | Bin 0 -> 38 bytes
.../Debug/Obj/stm32f10x_dac.pbi.cout | 304 ++
.../stm32f10x/Debug/Obj/stm32f10x_dbgmcu.pbi | Bin 0 -> 38 bytes
.../Debug/Obj/stm32f10x_dbgmcu.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/stm32f10x_dma.pbi | Bin 0 -> 38 bytes
.../Debug/Obj/stm32f10x_dma.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/stm32f10x_exti.pbi | Bin 0 -> 38 bytes
.../Debug/Obj/stm32f10x_exti.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/stm32f10x_flash.pbi | Bin 0 -> 38 bytes
.../Debug/Obj/stm32f10x_flash.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/stm32f10x_fsmc.pbi | Bin 0 -> 38 bytes
.../Debug/Obj/stm32f10x_fsmc.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/stm32f10x_gpio.pbi | Bin 0 -> 38 bytes
.../Debug/Obj/stm32f10x_gpio.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/stm32f10x_i2c.pbi | Bin 0 -> 38 bytes
.../Debug/Obj/stm32f10x_i2c.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/stm32f10x_it.pbi | Bin 0 -> 38 bytes
.../stm32f10x/Debug/Obj/stm32f10x_it.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/stm32f10x_iwdg.pbi | Bin 0 -> 38 bytes
.../Debug/Obj/stm32f10x_iwdg.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/stm32f10x_misc.pbi | Bin 0 -> 38 bytes
.../Debug/Obj/stm32f10x_misc.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/stm32f10x_pwr.pbi | Bin 0 -> 38 bytes
.../Debug/Obj/stm32f10x_pwr.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/stm32f10x_rcc.pbi | Bin 0 -> 38 bytes
.../Debug/Obj/stm32f10x_rcc.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/stm32f10x_rtc.pbi | Bin 0 -> 38 bytes
.../Debug/Obj/stm32f10x_rtc.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/stm32f10x_sdio.pbi | Bin 0 -> 38 bytes
.../Debug/Obj/stm32f10x_sdio.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/stm32f10x_spi.pbi | Bin 0 -> 38 bytes
.../Debug/Obj/stm32f10x_spi.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/stm32f10x_tim.pbi | Bin 0 -> 38 bytes
.../Debug/Obj/stm32f10x_tim.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/stm32f10x_usart.pbi | Bin 0 -> 38 bytes
.../Debug/Obj/stm32f10x_usart.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/stm32f10x_wwdg.pbi | Bin 0 -> 38 bytes
.../Debug/Obj/stm32f10x_wwdg.pbi.cout | 304 ++
.../stm32f10x/Debug/Obj/system_stm32f10x.pbi | Bin 0 -> 38 bytes
.../Debug/Obj/system_stm32f10x.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/timer.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/timer.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/timer_sys.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/timer_sys.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/txbuf.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/txbuf.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/whohas.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/whohas.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/whois.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/whois.pbi.cout | 304 ++
ports/stm32f10x/Debug/Obj/wp.pbi | Bin 0 -> 38 bytes
ports/stm32f10x/Debug/Obj/wp.pbi.cout | 304 ++
ports/stm32f10x/bacnet.dep | 1736 +++++++++++
ports/stm32f10x/bacnet.ewd | 2697 +++++++++++++++++
ports/stm32f10x/bacnet.ewp | 208 +-
.../stm32f10x/settings/bacnet.Debug.cspy.bat | 24 +
ports/stm32f10x/settings/bacnet.dbgdt | 5 +
ports/stm32f10x/settings/bacnet.dni | 44 +
ports/stm32f10x/settings/bacnet.wsdt | 66 +
ports/stm32f10x/settings/bacnet.wspos | 2 +
158 files changed, 29910 insertions(+), 129 deletions(-)
create mode 100644 ports/stm32f10x/Backup of bacnet.ewp
create mode 100644 ports/stm32f10x/CMSIS/core_cmFunc.h
create mode 100644 ports/stm32f10x/CMSIS/core_cmInstr.h
create mode 100644 ports/stm32f10x/Debug/Exe/c.out
create mode 100644 ports/stm32f10x/Debug/Obj/abort.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/abort.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/apdu.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/apdu.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/automac.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/automac.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/bacaddr.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/bacaddr.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/bacapp.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/bacapp.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/bacdcode.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/bacdcode.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/bacerror.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/bacerror.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/bacint.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/bacint.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/bacnet.pbd
create mode 100644 ports/stm32f10x/Debug/Obj/bacnet.pbd.browse
create mode 100644 ports/stm32f10x/Debug/Obj/bacnet.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/bacnet.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/bacreal.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/bacreal.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/bacstr.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/bacstr.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/bo.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/bo.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/crc.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/crc.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/dcc.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/dcc.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/device.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/device.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/dlmstp.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/dlmstp.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/fifo.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/fifo.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/h_dcc.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/h_dcc.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/h_npdu.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/h_npdu.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/h_rd.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/h_rd.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/h_rp.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/h_rp.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/h_rpm.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/h_rpm.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/h_whohas.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/h_whohas.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/h_whois.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/h_whois.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/h_wp.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/h_wp.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/iam.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/iam.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/ihave.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/ihave.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/led.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/led.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/main.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/main.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/memcopy.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/memcopy.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/noserv.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/noserv.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/npdu.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/npdu.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/proplist.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/proplist.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/rd.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/rd.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/reject.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/reject.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/ringbuf.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/ringbuf.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/rp.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/rp.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/rpm.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/rpm.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/rs485.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/rs485.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/s_iam.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/s_iam.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/s_ihave.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/s_ihave.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_adc.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_adc.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_bkp.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_bkp.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_can.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_can.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_cec.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_cec.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_crc.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_crc.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_dac.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_dac.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_dbgmcu.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_dbgmcu.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_dma.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_dma.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_exti.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_exti.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_flash.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_flash.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_fsmc.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_fsmc.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_gpio.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_gpio.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_i2c.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_i2c.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_it.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_it.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_iwdg.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_iwdg.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_misc.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_misc.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_pwr.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_pwr.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_rcc.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_rcc.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_rtc.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_rtc.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_sdio.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_sdio.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_spi.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_spi.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_tim.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_tim.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_usart.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_usart.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_wwdg.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/stm32f10x_wwdg.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/system_stm32f10x.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/system_stm32f10x.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/timer.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/timer.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/timer_sys.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/timer_sys.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/txbuf.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/txbuf.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/whohas.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/whohas.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/whois.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/whois.pbi.cout
create mode 100644 ports/stm32f10x/Debug/Obj/wp.pbi
create mode 100644 ports/stm32f10x/Debug/Obj/wp.pbi.cout
create mode 100644 ports/stm32f10x/bacnet.dep
create mode 100644 ports/stm32f10x/bacnet.ewd
create mode 100644 ports/stm32f10x/settings/bacnet.Debug.cspy.bat
create mode 100644 ports/stm32f10x/settings/bacnet.dbgdt
create mode 100644 ports/stm32f10x/settings/bacnet.dni
create mode 100644 ports/stm32f10x/settings/bacnet.wsdt
create mode 100644 ports/stm32f10x/settings/bacnet.wspos
diff --git a/ports/stm32f10x/Backup of bacnet.ewp b/ports/stm32f10x/Backup of bacnet.ewp
new file mode 100644
index 0000000..d44a9a3
--- /dev/null
+++ b/ports/stm32f10x/Backup of bacnet.ewp
@@ -0,0 +1,2175 @@
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+ $PROJ_DIR$\..\..\src\abort.c
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+
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+ BACnet-Handlers
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+ $PROJ_DIR$\..\..\demo\handler\h_dcc.c
+
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+
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+
+
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+ STM32-Lib
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+
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+ $PROJ_DIR$\drivers\src\stm32f10x_rcc.c
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+ $PROJ_DIR$\drivers\src\stm32f10x_spi.c
+
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+ $PROJ_DIR$\drivers\src\stm32f10x_tim.c
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+ $PROJ_DIR$\drivers\src\stm32f10x_usart.c
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+ $PROJ_DIR$\drivers\src\stm32f10x_wwdg.c
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+ $PROJ_DIR$\bo.c
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+ $PROJ_DIR$\main.c
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+ $PROJ_DIR$\rs485.c
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+ $PROJ_DIR$\stm32f10x_it.c
+
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+ $PROJ_DIR$\system_stm32f10x.c
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+ $PROJ_DIR$\timer.c
+
+
+ $PROJ_DIR$\timer_sys.c
+
+
+
+
diff --git a/ports/stm32f10x/CMSIS/core_cmFunc.h b/ports/stm32f10x/CMSIS/core_cmFunc.h
new file mode 100644
index 0000000..88819f9
--- /dev/null
+++ b/ports/stm32f10x/CMSIS/core_cmFunc.h
@@ -0,0 +1,609 @@
+/**************************************************************************//**
+ * @file core_cmFunc.h
+ * @brief CMSIS Cortex-M Core Function Access Header File
+ * @version V2.10
+ * @date 26. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ########################### Core Function Access ########################### */
+/** \ingroup CMSIS_Core_FunctionInterface
+ \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+ @{
+ */
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq(); */
+/* intrinsic void __disable_irq(); */
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+static __INLINE uint32_t __get_CONTROL(void)
+{
+ register uint32_t __regControl __ASM("control");
+ return(__regControl);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+static __INLINE void __set_CONTROL(uint32_t control)
+{
+ register uint32_t __regControl __ASM("control");
+ __regControl = control;
+}
+
+
+/** \brief Get ISPR Register
+
+ This function returns the content of the ISPR Register.
+
+ \return ISPR Register value
+ */
+static __INLINE uint32_t __get_IPSR(void)
+{
+ register uint32_t __regIPSR __ASM("ipsr");
+ return(__regIPSR);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+static __INLINE uint32_t __get_APSR(void)
+{
+ register uint32_t __regAPSR __ASM("apsr");
+ return(__regAPSR);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+static __INLINE uint32_t __get_xPSR(void)
+{
+ register uint32_t __regXPSR __ASM("xpsr");
+ return(__regXPSR);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+static __INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ return(__regProcessStackPointer);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+static __INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ register uint32_t __regProcessStackPointer __ASM("psp");
+ __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+static __INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ return(__regMainStackPointer);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+static __INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ register uint32_t __regMainStackPointer __ASM("msp");
+ __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+static __INLINE uint32_t __get_PRIMASK(void)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ return(__regPriMask);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ register uint32_t __regPriMask __ASM("primask");
+ __regPriMask = (priMask);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq __enable_fiq
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq __disable_fiq
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+static __INLINE uint32_t __get_BASEPRI(void)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ return(__regBasePri);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+static __INLINE void __set_BASEPRI(uint32_t basePri)
+{
+ register uint32_t __regBasePri __ASM("basepri");
+ __regBasePri = (basePri & 0xff);
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+static __INLINE uint32_t __get_FAULTMASK(void)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ return(__regFaultMask);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ register uint32_t __regFaultMask __ASM("faultmask");
+ __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+static __INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ return(__regfpscr);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+static __INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ register uint32_t __regfpscr __ASM("fpscr");
+ __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief Enable IRQ Interrupts
+
+ This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
+{
+ __ASM volatile ("cpsie i");
+}
+
+
+/** \brief Disable IRQ Interrupts
+
+ This function disables IRQ interrupts by setting the I-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
+{
+ __ASM volatile ("cpsid i");
+}
+
+
+/** \brief Get Control Register
+
+ This function returns the content of the Control Register.
+
+ \return Control Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, control" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Control Register
+
+ This function writes the given value to the Control Register.
+
+ \param [in] control Control Register value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
+{
+ __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/** \brief Get ISPR Register
+
+ This function returns the content of the ISPR Register.
+
+ \return ISPR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get APSR Register
+
+ This function returns the content of the APSR Register.
+
+ \return APSR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get xPSR Register
+
+ This function returns the content of the xPSR Register.
+
+ \return xPSR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Get Process Stack Pointer
+
+ This function returns the current value of the Process Stack Pointer (PSP).
+
+ \return PSP Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, psp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Process Stack Pointer
+
+ This function assigns the given value to the Process Stack Pointer (PSP).
+
+ \param [in] topOfProcStack Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+ __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
+}
+
+
+/** \brief Get Main Stack Pointer
+
+ This function returns the current value of the Main Stack Pointer (MSP).
+
+ \return MSP Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
+{
+ register uint32_t result;
+
+ __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Main Stack Pointer
+
+ This function assigns the given value to the Main Stack Pointer (MSP).
+
+ \param [in] topOfMainStack Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+ __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
+}
+
+
+/** \brief Get Priority Mask
+
+ This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+ \return Priority Mask value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, primask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Priority Mask
+
+ This function assigns the given value to the Priority Mask Register.
+
+ \param [in] priMask Priority Mask
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+ __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Enable FIQ
+
+ This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
+{
+ __ASM volatile ("cpsie f");
+}
+
+
+/** \brief Disable FIQ
+
+ This function disables FIQ interrupts by setting the F-bit in the CPSR.
+ Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
+{
+ __ASM volatile ("cpsid f");
+}
+
+
+/** \brief Get Base Priority
+
+ This function returns the current value of the Base Priority register.
+
+ \return Base Priority register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Base Priority
+
+ This function assigns the given value to the Base Priority register.
+
+ \param [in] basePri Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
+{
+ __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+
+/** \brief Get Fault Mask
+
+ This function returns the current value of the Fault Mask register.
+
+ \return Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
+{
+ uint32_t result;
+
+ __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+ return(result);
+}
+
+
+/** \brief Set Fault Mask
+
+ This function assigns the given value to the Fault Mask register.
+
+ \param [in] faultMask Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+ __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if (__CORTEX_M == 0x04)
+
+/** \brief Get FPSCR
+
+ This function returns the current value of the Floating Point Status/Control register.
+
+ \return Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ uint32_t result;
+
+ __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+ return(result);
+#else
+ return(0);
+#endif
+}
+
+
+/** \brief Set FPSCR
+
+ This function assigns the given value to the Floating Point Status/Control register.
+
+ \param [in] fpscr Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/ports/stm32f10x/CMSIS/core_cmInstr.h b/ports/stm32f10x/CMSIS/core_cmInstr.h
new file mode 100644
index 0000000..78d2ef8
--- /dev/null
+++ b/ports/stm32f10x/CMSIS/core_cmInstr.h
@@ -0,0 +1,585 @@
+/**************************************************************************//**
+ * @file core_cmInstr.h
+ * @brief CMSIS Cortex-M Core Instruction Access Header File
+ * @version V2.10
+ * @date 19. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers. This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ########################## Core Instruction Access ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+ Access to dedicated instructions
+ @{
+*/
+
+#if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+ #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP __nop
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+#define __WFI __wfi
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+#define __WFE __wfe
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV __sev
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+#define __ISB() __isb(0xF)
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB() __dsb(0xF)
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+#define __DMB() __dmb(0xF)
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __REV __rev
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+static __INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+ rev16 r0, r0
+ bx lr
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+static __INLINE __ASM int32_t __REVSH(int32_t value)
+{
+ revsh r0, r0
+ bx lr
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+#define __RBIT __rbit
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXB(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXH(value, ptr) __strex(value, ptr)
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+#define __STREXW(value, ptr) __strex(value, ptr)
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX __clrex
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT __ssat
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT __usat
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+#define __CLZ __clz
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief No Operation
+
+ No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
+{
+ __ASM volatile ("nop");
+}
+
+
+/** \brief Wait For Interrupt
+
+ Wait For Interrupt is a hint instruction that suspends execution
+ until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
+{
+ __ASM volatile ("wfi");
+}
+
+
+/** \brief Wait For Event
+
+ Wait For Event is a hint instruction that permits the processor to enter
+ a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
+{
+ __ASM volatile ("wfe");
+}
+
+
+/** \brief Send Event
+
+ Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
+{
+ __ASM volatile ("sev");
+}
+
+
+/** \brief Instruction Synchronization Barrier
+
+ Instruction Synchronization Barrier flushes the pipeline in the processor,
+ so that all instructions following the ISB are fetched from cache or
+ memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
+{
+ __ASM volatile ("isb");
+}
+
+
+/** \brief Data Synchronization Barrier
+
+ This function acts as a special kind of Data Memory Barrier.
+ It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
+{
+ __ASM volatile ("dsb");
+}
+
+
+/** \brief Data Memory Barrier
+
+ This function ensures the apparent order of the explicit memory operations before
+ and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
+{
+ __ASM volatile ("dmb");
+}
+
+
+/** \brief Reverse byte order (32 bit)
+
+ This function reverses the byte order in integer value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order (16 bit)
+
+ This function reverses the byte order in two unsigned short values.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief Reverse byte order in signed short value
+
+ This function reverses the byte order in a signed short value with sign extension to integer.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+#if (__CORTEX_M >= 0x03)
+
+/** \brief Reverse bit order of value
+
+ This function reverses the bit order of the given value.
+
+ \param [in] value Value to reverse
+ \return Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
+{
+ uint32_t result;
+
+ __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (8 bit)
+
+ This function performs a exclusive LDR command for 8 bit value.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+ uint8_t result;
+
+ __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (16 bit)
+
+ This function performs a exclusive LDR command for 16 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+ uint16_t result;
+
+ __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief LDR Exclusive (32 bit)
+
+ This function performs a exclusive LDR command for 32 bit values.
+
+ \param [in] ptr Pointer to data
+ \return value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (8 bit)
+
+ This function performs a exclusive STR command for 8 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (16 bit)
+
+ This function performs a exclusive STR command for 16 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief STR Exclusive (32 bit)
+
+ This function performs a exclusive STR command for 32 bit values.
+
+ \param [in] value Value to store
+ \param [in] ptr Pointer to location
+ \return 0 Function succeeded
+ \return 1 Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+ uint32_t result;
+
+ __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+ return(result);
+}
+
+
+/** \brief Remove the exclusive lock
+
+ This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
+{
+ __ASM volatile ("clrex");
+}
+
+
+/** \brief Signed Saturate
+
+ This function saturates a signed value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (1..32)
+ \return Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Unsigned Saturate
+
+ This function saturates an unsigned value.
+
+ \param [in] value Value to be saturated
+ \param [in] sat Bit position to saturate to (0..31)
+ \return Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({ \
+ uint32_t __RES, __ARG1 = (ARG1); \
+ __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
+ __RES; \
+ })
+
+
+/** \brief Count leading zeros
+
+ This function counts the number of leading zeros of a data value.
+
+ \param [in] value Value to count the leading zeros
+ \return number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
+{
+ uint8_t result;
+
+ __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+ return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/ports/stm32f10x/Debug/Exe/c.out b/ports/stm32f10x/Debug/Exe/c.out
new file mode 100644
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