From 19a9ef57f561614d844552fa867ff13c3d0e6c0e Mon Sep 17 00:00:00 2001 From: steveri Date: Wed, 4 Jun 2025 09:56:31 -0700 Subject: [PATCH 01/12] Add debug option for golden_test.sh --- bin/golden_test.sh | 7 ++++++- 1 file changed, 6 insertions(+), 1 deletion(-) diff --git a/bin/golden_test.sh b/bin/golden_test.sh index 36fa821..c130439 100755 --- a/bin/golden_test.sh +++ b/bin/golden_test.sh @@ -447,7 +447,12 @@ for t in "${tests[@]}"; do | awk '{print $0 "'" --- $npoints $nunits $nports"'"; }' keep_abbrev=1 - if [ "$keep_abbrev" ]; then + if [ "$DBG" ]; then + echo "" + echo "Keeping $tmp for debugging purposes" + wc -l $tmp + echo "" + elif [ "$keep_abbrev" ]; then echo "" echo "Keeping first 300 lines ONLY of $tmp" wc -l $tmp From 2c5f1522ebb2860f131bbf51647b5db4f053f5a8 Mon Sep 17 00:00:00 2001 From: steveri Date: Wed, 4 Jun 2025 10:03:36 -0700 Subject: [PATCH 02/12] Better async 1port SRAM works for both vcs and verilator maybe --- rtl/SRAM.vp | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/rtl/SRAM.vp b/rtl/SRAM.vp index a77fa9c..0412487 100644 --- a/rtl/SRAM.vp +++ b/rtl/SRAM.vp @@ -73,7 +73,8 @@ module `mname` output logic [`$data_width-1`:0] rd_data_o; // Read data OUT. input logic [`$data_width-1`:0] wr_data_i; // Write data IN. - reg [`$data_width-1`:0] mem[0:`$nrows-1`]; // memory cells + reg [`$data_width-1`:0] mem[0:`$nrows-1`]; // Memory cells + reg [`$data_width-1`:0] wr_data_i_prev; // Hack to make true-1port work I guess //; # For debugging //; my $real="63:32"; # Real @@ -114,21 +115,20 @@ module `mname` ////////////////////////////////////////////////////////////////////////////// // WRITE TRUE_1PORT // FIXME use a proper async SRAM (see above)!!! fiddle w/signals outside, in wrapper :( - // - // always @(ez_i or wz_i) begin // doesn't work for verilator - // always @(ez_i or wz_i) begin // NOT AN EDGE!!!!!!!!! - // - always @(negedge wz_i) begin // trial/error debugging - saw behavior on (correct) vcs wave - if (~ez_i & ~wz_i) begin + + // Want to trigger writes on negedge wz_i + always @(negedge clk_i) wr_data_i_prev = wr_data_i; // omg + always @(wz_i) begin + if (!ez_i && !wz_i) begin // WRITE TRUE_1PORT - mem[addr_i] <= wr_data_i; + mem[addr_i] <= wr_data_i_prev; // WRITE DEBUG $display("%m %1d: ez_i=%1d and wz_i=%1d", $time, ez_i, wz_i); - $display("%m %1d: Wrote wr_data_i mem[%1d] <= %16x", $time, addr_i, wr_data_i); + $display("%m %1d: Wrote wr_data_i mem[%1d] <= %16x", $time, addr_i, wr_data_i_prev); $display("`$myname` t5 %5d: Wrote(f) wr_data_i mem[%1d] <= (bsr'%08X,bsr'%08X)", - $time, addr_i, `ri("wr_data_i")`); + $time, addr_i, `ri("wr_data_i_prev")`); $display(""); end end From acbf0d20bbe9886c82acba578b049e758a2aeebe Mon Sep 17 00:00:00 2001 From: steveri Date: Wed, 4 Jun 2025 10:08:04 -0700 Subject: [PATCH 03/12] Added note about stupid-endianness --- rtl/fftram.vp | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/rtl/fftram.vp b/rtl/fftram.vp index 79b83ba..977a41e 100644 --- a/rtl/fftram.vp +++ b/rtl/fftram.vp @@ -591,6 +591,10 @@ module `mname` //; foreach my $p ("1", "2") { ////////////////////////////////////////////////////////////////////////////// // SRAM data in`$p` OUT from sram (or bypass buffer) to butterfly unit + // OMG note stupid-endian: match[MSB] = match[0] FIXME FIXME FIXME? + // E.g. if there are four srams + // match==8 => match[0] == 1 => SRAM000 + // match==1 => match[3] == 1 => SRAM003 // //;# assign BFLY0_in1_data_o = <= BUG/FIXME/TODO inaccurate //;# ( BFLY0_op1_match[0] ) ? (bypass000 ? (buf000 : SRAM000_rd_data)) : From 17308597101bccfa9074a9dab3b6282cce8770c7 Mon Sep 17 00:00:00 2001 From: steveri Date: Wed, 4 Jun 2025 10:12:57 -0700 Subject: [PATCH 04/12] restore original tst/top_fft.vp i think --- tst/top_fft.vp | 11 +++++++++++ 1 file changed, 11 insertions(+) diff --git a/tst/top_fft.vp b/tst/top_fft.vp index 2bee55e..6be17e8 100644 --- a/tst/top_fft.vp +++ b/tst/top_fft.vp @@ -434,11 +434,22 @@ module `mname`( input logic clk, output wire done ); // //////////////////////////////////// + logic [31:0] clock_counter; initial begin start = 1'b0; // Should be comb logic based on rst_n etc? leave it for now rst_n = 1'b1; + clock_counter = 32'b0; end + //////////////////////////////////////////////////////////////////////// + // clock counter I guess + // + + always @ (posedge clk) begin + clock_counter <= clock_counter + 32'b1; + end + + // note cgra does this: // always @(posedge clk or posedge reset) begin // if (reset==1'b1) begin ... From 903c327ff40ee1847657de4bc048b3c6c38ca373 Mon Sep 17 00:00:00 2001 From: steveri Date: Wed, 4 Jun 2025 10:14:10 -0700 Subject: [PATCH 05/12] try with all sram variants, not just 2port... --- bin/golden_test.sh | 1 + 1 file changed, 1 insertion(+) diff --git a/bin/golden_test.sh b/bin/golden_test.sh index c130439..82ce540 100755 --- a/bin/golden_test.sh +++ b/bin/golden_test.sh @@ -245,6 +245,7 @@ else done done + DO_2PORT_ONLY= if [ "$DO_2PORT_ONLY" ]; then # Delete all tests except sram=2port # This hack exists b/c Verilator only works on 2port srams From 0ca50d2a259c74a43d7be777c23931f066dfcd71 Mon Sep 17 00:00:00 2001 From: steveri Date: Wed, 4 Jun 2025 10:19:11 -0700 Subject: [PATCH 06/12] Remove dpump from regressions, it still be bursted --- bin/golden_test.sh | 19 ++++++++++++++----- 1 file changed, 14 insertions(+), 5 deletions(-) diff --git a/bin/golden_test.sh b/bin/golden_test.sh index 82ce540..dd3c036 100755 --- a/bin/golden_test.sh +++ b/bin/golden_test.sh @@ -245,11 +245,20 @@ else done done - DO_2PORT_ONLY= - if [ "$DO_2PORT_ONLY" ]; then - # Delete all tests except sram=2port - # This hack exists b/c Verilator only works on 2port srams - t2=$(printf '%s\n' "${tests[@]}" | egrep '2port|hline') +# DO_2PORT_ONLY= +# if [ "$DO_2PORT_ONLY" ]; then +# # Delete all tests except sram=2port +# # This hack exists b/c Verilator only works on 2port srams +# t2=$(printf '%s\n' "${tests[@]}" | egrep '2port|hline') +# mapfile -t tests < <(echo "${t2[@]}") +# fi + + # Got 1port working, hoory! But dpump still busted. + SKIP_DPUMP=True + if [ "$SKIP_DPUMP" ]; then + # Delete all tests except sram=1port,2port, i.e. all dpump tests + # This hack exists b/c Verilator still does not work on dpump srams + t2=$(printf '%s\n' "${tests[@]}" | grep -v 'dpump') mapfile -t tests < <(echo "${t2[@]}") fi From e3ba7a903954e791a34c18ae91b6496836bd0418 Mon Sep 17 00:00:00 2001 From: steveri Date: Wed, 4 Jun 2025 10:31:25 -0700 Subject: [PATCH 07/12] trying to clean up a mess --- bin/golden_test.sh | 1 + test/test-regress.sh | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/bin/golden_test.sh b/bin/golden_test.sh index dd3c036..4afd78e 100755 --- a/bin/golden_test.sh +++ b/bin/golden_test.sh @@ -352,6 +352,7 @@ for t in "${tests[@]}"; do echo "$sfx not supported (16 SRAM's for 8 points!?)"; continue fi [ $sfx == "8_4_1port" ] && echo "*** NOTE $sfx is SUPPOSED to fail! (16 SRAM's for 8 points\!?) ***" + [ $sfx == "8_4_1port" ] && echo "TR FAIL: But that's okay, $sfx is SUPPOSED to fail! (16 SRAM's for 8 points\!?) ***" # Print out date, id info date; echo $sfx": npoints=$npoints, nunits=$nunits, sram=$sram; alg=$swizzalg; sim=$SIMULATOR" diff --git a/test/test-regress.sh b/test/test-regress.sh index ba3be49..eed54bf 100755 --- a/test/test-regress.sh +++ b/test/test-regress.sh @@ -97,7 +97,7 @@ test -d /tmp/fpu$$ && /bin/rm -rf /tmp/fpu$$ # Prepare to issue caveats in case of verilator version function verilator_caveats { printf "\n------------------------------------------------------------------------" - printf "\nNote that verilator tests only work for 2port sram." + printf "\nNote that verilator tests do not (yet) work for double-pump sram." printf "\nThis appears to be a verilator bug; all tests pass for vcs (trust me!)" printf "\n------------------------------------------------------------------------\n\n" } From d6aafd39957a86a672b8407c32c2a763a291b72a Mon Sep 17 00:00:00 2001 From: steveri Date: Wed, 4 Jun 2025 10:57:29 -0700 Subject: [PATCH 08/12] Cleaned up golden_test maybe --- bin/golden_test.sh | 24 +++++++++++------------- 1 file changed, 11 insertions(+), 13 deletions(-) diff --git a/bin/golden_test.sh b/bin/golden_test.sh index 4afd78e..c724529 100755 --- a/bin/golden_test.sh +++ b/bin/golden_test.sh @@ -145,6 +145,7 @@ MAKEFILE=$FFTGEN_DIR/Makefile tests=() ntests=1 +n_allowed_failures=0 # simulator can be either vcs or verilator SIMULATOR='verilator' @@ -349,10 +350,10 @@ for t in "${tests[@]}"; do # "8_4_1port" is not supported (at least for now) if [ $sfx == "8_4_1port" ]; then - echo "$sfx not supported (16 SRAM's for 8 points!?)"; continue + n_allowed_failures=1 + echo "TR FAIL: Combo not attempted --- 8 4 1port fail OKAY b/c makes no sense (16 SRAM's for 8 points\!?)" + continue fi - [ $sfx == "8_4_1port" ] && echo "*** NOTE $sfx is SUPPOSED to fail! (16 SRAM's for 8 points\!?) ***" - [ $sfx == "8_4_1port" ] && echo "TR FAIL: But that's okay, $sfx is SUPPOSED to fail! (16 SRAM's for 8 points\!?) ***" # Print out date, id info date; echo $sfx": npoints=$npoints, nunits=$nunits, sram=$sram; alg=$swizzalg; sim=$SIMULATOR" @@ -519,17 +520,14 @@ fi npass=`grep PASS $summfile | wc -l` echo "$npass/$ntests tests PASSED" -echo " (NOTE 47/48 pass is normal because '8 4 1' not supported.)" -echo +if [ "$n_allowed_failures" -eq 1 ]; then + printf " (NOTE: One failure is allowed because '8 4 1' not supported.)\n\n" +fi -if [ $ntests == 48 ]; then - if [ $npass != 47 ]; then - echo "ERROR golden_test.sh - should be 47/48 passes" - exit 13 - fi -elif [ $npass != $ntests ]; then - echo "ERROR golden_test.sh - test(s) failed" - exit 13 +npass_expected=$((ntests-n_allowed_failures)) + +if [ $npass -ne $npass_expected ]; then + printf "ERROR golden_test.sh - $npass_expected/$npass should PASS\n\n" fi echo Warnings: From f2f154b1303f80c8ba30de02c9996eba7f558148 Mon Sep 17 00:00:00 2001 From: steveri Date: Wed, 4 Jun 2025 11:26:34 -0700 Subject: [PATCH 09/12] cleanup --- bin/golden_test.sh | 11 ++++++++--- test/test-regress.sh | 9 +++------ 2 files changed, 11 insertions(+), 9 deletions(-) diff --git a/bin/golden_test.sh b/bin/golden_test.sh index c724529..2fcd095 100755 --- a/bin/golden_test.sh +++ b/bin/golden_test.sh @@ -255,7 +255,6 @@ else # fi # Got 1port working, hoory! But dpump still busted. - SKIP_DPUMP=True if [ "$SKIP_DPUMP" ]; then # Delete all tests except sram=1port,2port, i.e. all dpump tests # This hack exists b/c Verilator still does not work on dpump srams @@ -519,15 +518,18 @@ if [ ! -e $summfile ]; then fi npass=`grep PASS $summfile | wc -l` -echo "$npass/$ntests tests PASSED" +note="" if [ "$n_allowed_failures" -eq 1 ]; then - printf " (NOTE: One failure is allowed because '8 4 1' not supported.)\n\n" + note=" (NOTE: One failure is allowed b/c '8 4 1' not supported.)" fi +echo "$npass/$ntests tests PASSED$note" npass_expected=$((ntests-n_allowed_failures)) if [ $npass -ne $npass_expected ]; then printf "ERROR golden_test.sh - $npass_expected/$npass should PASS\n\n" + printf "FINAL RESULT = FAIL\n" + exit 13 fi echo Warnings: @@ -542,6 +544,9 @@ echo /bin/rm $summfile echo "NOTE did not keep result summary file '$summfile'" +printf "FINAL RESULT = PASS\n" + + # echo ============================================================================== # cat $summfile # echo ============================================================================== diff --git a/test/test-regress.sh b/test/test-regress.sh index eed54bf..f60224e 100755 --- a/test/test-regress.sh +++ b/test/test-regress.sh @@ -117,7 +117,7 @@ if [ "$is_verilator" ]; then exit 13 fi fi - verilator_caveats; export DO_2PORT_ONLY=1 + verilator_caveats; export SKIP_DPUMP=1 fi # Run the regressions! @@ -128,11 +128,8 @@ fi echo $fftgen/bin/golden_test.sh $* $fftgen/bin/golden_test.sh $* \ |& $nobuf tee test_results.log \ - | $nobuf egrep 'PASS|FAIL|ERR' + | $nobuf egrep 'PASS|FAIL|ERR| failure is allowed' [ "$is_verilator" ] && verilator_caveats - - egrep 'FAIL|ERR' test_results.log && result=FAIL || result=PASS - printf "\nFINAL RESULT = $result\n" - [ "$result" == PASS ] || exit 13 + egrep '^FINAL RESULT.*PASS' test_results.log || exit 13 ) From d30af6f625e222bfa9ac18a71b51c07aae155060 Mon Sep 17 00:00:00 2001 From: steveri Date: Wed, 4 Jun 2025 11:26:54 -0700 Subject: [PATCH 10/12] cleanup --- bin/golden_test.sh | 8 -------- 1 file changed, 8 deletions(-) diff --git a/bin/golden_test.sh b/bin/golden_test.sh index 2fcd095..d1922f8 100755 --- a/bin/golden_test.sh +++ b/bin/golden_test.sh @@ -246,14 +246,6 @@ else done done -# DO_2PORT_ONLY= -# if [ "$DO_2PORT_ONLY" ]; then -# # Delete all tests except sram=2port -# # This hack exists b/c Verilator only works on 2port srams -# t2=$(printf '%s\n' "${tests[@]}" | egrep '2port|hline') -# mapfile -t tests < <(echo "${t2[@]}") -# fi - # Got 1port working, hoory! But dpump still busted. if [ "$SKIP_DPUMP" ]; then # Delete all tests except sram=1port,2port, i.e. all dpump tests From 74508ca071859304f573a1c3c67d0d825889f2f2 Mon Sep 17 00:00:00 2001 From: steveri Date: Thu, 5 Jun 2025 06:05:45 -0700 Subject: [PATCH 11/12] cleanup --- tst/top_fft.vp | 11 ----------- 1 file changed, 11 deletions(-) diff --git a/tst/top_fft.vp b/tst/top_fft.vp index 6be17e8..2bee55e 100644 --- a/tst/top_fft.vp +++ b/tst/top_fft.vp @@ -434,22 +434,11 @@ module `mname`( input logic clk, output wire done ); // //////////////////////////////////// - logic [31:0] clock_counter; initial begin start = 1'b0; // Should be comb logic based on rst_n etc? leave it for now rst_n = 1'b1; - clock_counter = 32'b0; end - //////////////////////////////////////////////////////////////////////// - // clock counter I guess - // - - always @ (posedge clk) begin - clock_counter <= clock_counter + 32'b1; - end - - // note cgra does this: // always @(posedge clk or posedge reset) begin // if (reset==1'b1) begin ... From 20971a41644938d530590efef9156e62dc537a19 Mon Sep 17 00:00:00 2001 From: steveri Date: Thu, 5 Jun 2025 06:08:31 -0700 Subject: [PATCH 12/12] cleanup --- rtl/SRAM.vp | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/rtl/SRAM.vp b/rtl/SRAM.vp index 0412487..bfa4091 100644 --- a/rtl/SRAM.vp +++ b/rtl/SRAM.vp @@ -74,7 +74,7 @@ module `mname` input logic [`$data_width-1`:0] wr_data_i; // Write data IN. reg [`$data_width-1`:0] mem[0:`$nrows-1`]; // Memory cells - reg [`$data_width-1`:0] wr_data_i_prev; // Hack to make true-1port work I guess + reg [`$data_width-1`:0] wr_data_i_prev; // Hack to make true-1port work I guess //; # For debugging //; my $real="63:32"; # Real