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lines changed

6 files changed

+540
-510
lines changed

‎src/decode.c‎

Lines changed: 88 additions & 85 deletions
Original file line numberDiff line numberDiff line change
@@ -1982,7 +1982,8 @@ static inline bool op_cfsw(rv_insn_t *ir, const uint32_t insn)
19821982
#define op_cflwsp OP_UNIMP
19831983
#endif /* RV32_HAS(EXT_C) && RV32_HAS(EXT_F) */
19841984

1985-
static inline bool op_ivv(rv_insn_t *ir, const uint32_t insn) {
1985+
static inline bool op_ivv(rv_insn_t *ir, const uint32_t insn)
1986+
{
19861987
#define MASK 0xfc00707f
19871988
#define MATCH_VADD_VI 0x3057
19881989
#define MATCH_VAND_VI 0x24003057
@@ -2011,74 +2012,74 @@ static inline bool op_ivv(rv_insn_t *ir, const uint32_t insn) {
20112012
ir->rs2 = decode_rs2(insn);
20122013
ir->vm = decode_rvv_vm(insn);
20132014
switch (insn & MASK) {
2014-
case MATCH_VADD_VI:
2015+
case MATCH_VADD_VI:
20152016
ir->opcode = rv_insn_vadd_vi;
2016-
break;
2017-
case MATCH_VAND_VI:
2017+
break;
2018+
case MATCH_VAND_VI:
20182019
ir->opcode = rv_insn_vand_vi;
2019-
break;
2020-
case MATCH_VMADC_VI:
2020+
break;
2021+
case MATCH_VMADC_VI:
20212022
ir->opcode = rv_insn_vmadc_vi;
2022-
break;
2023-
case MATCH_VMSEQ_VI:
2023+
break;
2024+
case MATCH_VMSEQ_VI:
20242025
ir->opcode = rv_insn_vmseq_vi;
2025-
break;
2026-
case MATCH_VMSGT_VI:
2026+
break;
2027+
case MATCH_VMSGT_VI:
20272028
ir->opcode = rv_insn_vmsgt_vi;
2028-
break;
2029-
case MATCH_VMSGTU_VI:
2029+
break;
2030+
case MATCH_VMSGTU_VI:
20302031
ir->opcode = rv_insn_vmsgtu_vi;
2031-
break;
2032-
case MATCH_VMSLE_VI:
2032+
break;
2033+
case MATCH_VMSLE_VI:
20332034
ir->opcode = rv_insn_vmsle_vi;
2034-
break;
2035-
case MATCH_VMSLEU_VI:
2035+
break;
2036+
case MATCH_VMSLEU_VI:
20362037
ir->opcode = rv_insn_vmsleu_vi;
2037-
break;
2038-
case MATCH_VMSNE_VI:
2038+
break;
2039+
case MATCH_VMSNE_VI:
20392040
ir->opcode = rv_insn_vmsne_vi;
2040-
break;
2041-
case MATCH_VOR_VI:
2041+
break;
2042+
case MATCH_VOR_VI:
20422043
ir->opcode = rv_insn_vor_vi;
2043-
break;
2044-
case MATCH_VRGATHER_VI:
2044+
break;
2045+
case MATCH_VRGATHER_VI:
20452046
ir->opcode = rv_insn_vrgather_vi;
2046-
break;
2047-
case MATCH_VRSUB_VI:
2047+
break;
2048+
case MATCH_VRSUB_VI:
20482049
ir->opcode = rv_insn_vrsub_vi;
2049-
break;
2050-
case MATCH_VSADD_VI:
2050+
break;
2051+
case MATCH_VSADD_VI:
20512052
ir->opcode = rv_insn_vsadd_vi;
2052-
break;
2053-
case MATCH_VSADDU_VI:
2053+
break;
2054+
case MATCH_VSADDU_VI:
20542055
ir->opcode = rv_insn_vsaddu_vi;
2055-
break;
2056-
case MATCH_VSLIDEDOWN_VI:
2056+
break;
2057+
case MATCH_VSLIDEDOWN_VI:
20572058
ir->opcode = rv_insn_vslidedown_vi;
2058-
break;
2059-
case MATCH_VSLIDEUP_VI:
2059+
break;
2060+
case MATCH_VSLIDEUP_VI:
20602061
ir->opcode = rv_insn_vslideup_vi;
2061-
break;
2062-
case MATCH_VSLL_VI:
2062+
break;
2063+
case MATCH_VSLL_VI:
20632064
ir->opcode = rv_insn_vsll_vi;
2064-
break;
2065-
case MATCH_VSRA_VI:
2065+
break;
2066+
case MATCH_VSRA_VI:
20662067
ir->opcode = rv_insn_vsra_vi;
2067-
break;
2068-
case MATCH_VSRL_VI:
2068+
break;
2069+
case MATCH_VSRL_VI:
20692070
ir->opcode = rv_insn_vsrl_vi;
2070-
break;
2071-
case MATCH_VSSRA_VI:
2071+
break;
2072+
case MATCH_VSSRA_VI:
20722073
ir->opcode = rv_insn_vssra_vi;
2073-
break;
2074-
case MATCH_VSSRL_VI:
2074+
break;
2075+
case MATCH_VSSRL_VI:
20752076
ir->opcode = rv_insn_vssrl_vi;
2076-
break;
2077-
case MATCH_VXOR_VI:
2077+
break;
2078+
case MATCH_VXOR_VI:
20782079
ir->opcode = rv_insn_vxor_vi;
2079-
break;
2080-
default:
2081-
return false;
2080+
break;
2081+
default:
2082+
return false;
20822083
}
20832084
}
20842085

@@ -2090,43 +2091,45 @@ static inline bool op_fvf(rv_insn_t *ir, const uint32_t insn) {}
20902091
static inline bool op_mvx(rv_insn_t *ir, const uint32_t insn) {}
20912092

20922093
/* OP: RVV
2093-
* opcode is 0x57 for VALU and VCFG
2094+
* opcode is 0x57 for VALU and VCFG
20942095
*
20952096
* VALU format:
20962097
* 31 26 25 24 20 19 15 14 12 11 7 6 0
2097-
* funct6 | vm | vs2 | vs1 | 0 0 0 (funct3) | vd |1010111| OP-V (OPIVV)
2098-
* funct6 | vm | vs2 | vs1 | 0 0 1 (funct3) | vd/rd |1010111| OP-V (OPFVV)
2099-
* funct6 | vm | vs2 | vs1 | 0 1 0 (funct3) | vd/rd |1010111| OP-V (OPMVV)
2100-
* funct6 | vm | vs2 | imm[4:0] | 0 1 1 (funct3) | vd |1010111| OP-V (OPIVI)
2101-
* funct6 | vm | vs2 | rs1 | 1 0 0 (funct3) | vd |1010111| OP-V (OPIVX)
2102-
* funct6 | vm | vs2 | rs1 | 1 0 1 (funct3) | vd |1010111| OP-V (OPFVF)
2103-
* funct6 | vm | vs2 | rs1 | 1 1 0 (funct3) | vd/rd |1010111| OP-V (OPMVX)
2104-
* 6 1 5 5 3 5 7
2105-
*
2098+
* funct6 | vm | vs2 | vs1 | 0 0 0 (funct3) | vd |1010111|
2099+
* OP-V (OPIVV) funct6 | vm | vs2 | vs1 | 0 0 1 (funct3) | vd/rd
2100+
* |1010111| OP-V (OPFVV) funct6 | vm | vs2 | vs1 | 0 1 0 (funct3)
2101+
* | vd/rd |1010111| OP-V (OPMVV) funct6 | vm | vs2 | imm[4:0] | 0 1 1
2102+
* (funct3) | vd |1010111| OP-V (OPIVI) funct6 | vm | vs2 | rs1
2103+
* | 1 0 0 (funct3) | vd |1010111| OP-V (OPIVX) funct6 | vm | vs2 |
2104+
* rs1 | 1 0 1 (funct3) | vd |1010111| OP-V (OPFVF) funct6 | vm | vs2
2105+
* | rs1 | 1 1 0 (funct3) | vd/rd |1010111| OP-V (OPMVX) 6 1 5 5
2106+
* 3 5 7
2107+
*
21062108
* Where 'vm' is the bit indicates whether masking is enabled
2107-
* see https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#531-mask-encoding
2108-
*
2109+
* see
2110+
* https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#531-mask-encoding
2111+
*
21092112
* VMEM format:
2110-
*
2113+
*
21112114
* 31 29 28 27 26 25 24 20 19 15 14 12 11 7 6 0
2112-
* nf | mew| mop | vm | lumop | rs1 | width | vd |0000111| VL* unit-stride
2113-
* nf | mew| mop | vm | rs2 | rs1 | width | vd |0000111| VLS* strided
2114-
* nf | mew| mop | vm | vs2 | rs1 | width | vd |0000111| VLX* indexed
2115-
* 3 1 2 1 5 5 3 5 7
2116-
*
2115+
* nf | mew| mop | vm | lumop | rs1 | width | vd |0000111| VL*
2116+
* unit-stride nf | mew| mop | vm | rs2 | rs1 | width | vd
2117+
* |0000111| VLS* strided nf | mew| mop | vm | vs2 | rs1 | width | vd
2118+
* |0000111| VLX* indexed 3 1 2 1 5 5 3 5 7
2119+
*
21172120
* VCFG format:
2118-
*
2121+
*
21192122
* 31 30 25 24 20 19 15 14 12 11 7 6 0
21202123
* 0 | zimm[10:0] | rs1 | 1 1 1 | rd |1010111| vsetvli
21212124
* 1 | 1| zimm[ 9:0] | uimm[4:0]| 1 1 1 | rd |1010111| vsetivli
21222125
* 1 | 000000 | rs2 | rs1 | 1 1 1 | rd |1010111| vsetvl
21232126
* 1 6 5 5 3 5 7
2124-
*
2127+
*
21252128
* reference:
21262129
* https://github.com/riscv/riscv-isa-manual/blob/main/src/images/wavedrom/valu-format.edn
21272130
* https://github.com/riscv/riscv-isa-manual/blob/main/src/images/wavedrom/v-inst-table.edn
21282131
* https://observablehq.com/@drom/risc-v-v
2129-
*
2132+
*
21302133
* funct3
21312134
* | 0 | 0 | 0 | OPIVV | vector-vector | N/A
21322135
* | 0 | 0 | 1 | OPFVV | vector-vector | N/A
@@ -2140,22 +2143,22 @@ static inline bool op_v(rv_insn_t *ir, const uint32_t insn)
21402143
{
21412144
uint32_t funct3_mask = 0x7000;
21422145
switch ((insn & funct3_mask) >> 7) {
2143-
case 0:
2144-
return op_ivv(ir, insn);
2145-
case 1:
2146-
return op_fvv(ir, insn);
2147-
case 2:
2148-
return op_mvv(ir, insn);
2149-
case 3:
2150-
return op_ivi(ir, insn);
2151-
case 4:
2152-
return op_ivx(ir, insn);
2153-
case 5:
2154-
return op_fvf(ir, insn);
2155-
case 6:
2156-
return op_mvx(ir, insn);
2157-
default:
2158-
return false;
2146+
case 0:
2147+
return op_ivv(ir, insn);
2148+
case 1:
2149+
return op_fvv(ir, insn);
2150+
case 2:
2151+
return op_mvv(ir, insn);
2152+
case 3:
2153+
return op_ivi(ir, insn);
2154+
case 4:
2155+
return op_ivx(ir, insn);
2156+
case 5:
2157+
return op_fvf(ir, insn);
2158+
case 6:
2159+
return op_mvx(ir, insn);
2160+
default:
2161+
return false;
21592162
}
21602163

21612164
if ((insn & MASK_VSETVLI) == MATCH_VSETVLI) {
@@ -2167,7 +2170,7 @@ static inline bool op_v(rv_insn_t *ir, const uint32_t insn)
21672170
// vsetivli
21682171
ir->rd = (insn >> 7) & 0x1f;
21692172
ir->uimm = (insn >> 15) & 0x1f;
2170-
ir->zimm = (insn >> 20) & 0x3ff; // zimm[9:0]
2173+
ir->zimm = (insn >> 20) & 0x3ff; // zimm[9:0]
21712174

21722175
} else if ((insn & MASK_VSETVL) == MATCH_VSETVL) {
21732176
// vsetvl

‎src/decode.h‎

Lines changed: 24 additions & 24 deletions
Original file line numberDiff line numberDiff line change
@@ -195,30 +195,30 @@ enum op_field {
195195
_(fcvtswu, 0, 4, 0, ENC(rs1, rs2, rd)) \
196196
_(fmvwx, 0, 4, 0, ENC(rs1, rs2, rd)) \
197197
) \
198-
IIF(RV32_HAS(EXT_RVV))( \
199-
_(vadd_vi, 0, 4, 0, ENC(r1, r2, rd)) \
200-
_(vand_vi, 0, 4, 0, ENC(r1, r2, rd)) \
201-
_(vmadc_vi, 0, 4, 0, ENC(r1, r2, rd)) \
202-
_(vmseq_vi, 0, 4, 0, ENC(r1, r2, rd)) \
203-
_(vmsgt_vi, 0, 4, 0, ENC(r1, r2, rd)) \
204-
_(vmsgtu_vi, 0, 4, 0, ENC(r1, r2, rd)) \
205-
_(vmsle_vi, 0, 4, 0, ENC(r1, r2, rd)) \
206-
_(vmsleu_vi, 0, 4, 0, ENC(r1, r2, rd)) \
207-
_(vmsne_vi, 0, 4, 0, ENC(r1, r2, rd)) \
208-
_(vor_vi, 0, 4, 0, ENC(r1, r2, rd)) \
209-
_(vrgather_vi, 0, 4, 0, ENC(r1, r2, rd)) \
210-
_(vrsub_vi, 0, 4, 0, ENC(r1, r2, rd)) \
211-
_(vsadd_vi, 0, 4, 0, ENC(r1, r2, rd)) \
212-
_(vsaddu_vi, 0, 4, 0, ENC(r1, r2, rd)) \
213-
_(vslidedown_vi, 0, 4, 0, ENC(r1, r2, rd)) \
214-
_(vslideup_vi, 0, 4, 0, ENC(r1, r2, rd)) \
215-
_(vsll_vi, 0, 4, 0, ENC(r1, r2, rd)) \
216-
_(vsra_vi, 0, 4, 0, ENC(r1, r2, rd)) \
217-
_(vsrl_vi, 0, 4, 0, ENC(r1, r2, rd)) \
218-
_(vssra_vi, 0, 4, 0, ENC(r1, r2, rd)) \
219-
_(vssrl_vi, 0, 4, 0, ENC(r1, r2, rd)) \
220-
_(vxor_vi, 0, 4, 0, ENC(r1, r2, rd)) \
221-
) \
198+
IIF(RV32_HAS(EXT_RVV))( \
199+
_(vadd_vi, 0, 4, 0, ENC(r1, r2, rd)) \
200+
_(vand_vi, 0, 4, 0, ENC(r1, r2, rd)) \
201+
_(vmadc_vi, 0, 4, 0, ENC(r1, r2, rd)) \
202+
_(vmseq_vi, 0, 4, 0, ENC(r1, r2, rd)) \
203+
_(vmsgt_vi, 0, 4, 0, ENC(r1, r2, rd)) \
204+
_(vmsgtu_vi, 0, 4, 0, ENC(r1, r2, rd)) \
205+
_(vmsle_vi, 0, 4, 0, ENC(r1, r2, rd)) \
206+
_(vmsleu_vi, 0, 4, 0, ENC(r1, r2, rd)) \
207+
_(vmsne_vi, 0, 4, 0, ENC(r1, r2, rd)) \
208+
_(vor_vi, 0, 4, 0, ENC(r1, r2, rd)) \
209+
_(vrgather_vi, 0, 4, 0, ENC(r1, r2, rd)) \
210+
_(vrsub_vi, 0, 4, 0, ENC(r1, r2, rd)) \
211+
_(vsadd_vi, 0, 4, 0, ENC(r1, r2, rd)) \
212+
_(vsaddu_vi, 0, 4, 0, ENC(r1, r2, rd)) \
213+
_(vslidedown_vi, 0, 4, 0, ENC(r1, r2, rd)) \
214+
_(vslideup_vi, 0, 4, 0, ENC(r1, r2, rd)) \
215+
_(vsll_vi, 0, 4, 0, ENC(r1, r2, rd)) \
216+
_(vsra_vi, 0, 4, 0, ENC(r1, r2, rd)) \
217+
_(vsrl_vi, 0, 4, 0, ENC(r1, r2, rd)) \
218+
_(vssra_vi, 0, 4, 0, ENC(r1, r2, rd)) \
219+
_(vssrl_vi, 0, 4, 0, ENC(r1, r2, rd)) \
220+
_(vxor_vi, 0, 4, 0, ENC(r1, r2, rd)) \
221+
) \
222222
/* RV32C Standard Extension */ \
223223
IIF(RV32_HAS(EXT_C))( \
224224
_(caddi4spn, 0, 2, 1, ENC(rd)) \

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