Modularize single-width vector instruction

To emulate vector registers of length VLEN using an array of uint32_t,
we first handle different SEW values (8, 16, 32) using sew_*b_handler.
Inside the handler, the V*_LOOP macro expands to process different VL
values and operand types, along with its corresponding V*_LOOP_LEFT.

The goal is to maximize code reuse by defining individual operations
next to their respective vector instructions, which can be easily
applied using the OPT() macro.

V*_LOOP execution steps:
1. Copy the operand op1 (op2).
2. Align op1 to the right.
3. Perform the specified operation between op1 and op2.
4. Mask the result according to the corresponding SEW.
5. Shift the result left to align with the corresponding position.
6. Accumulate the result.

In vector register groups, registers should follow the pattern v2*n,
v2*n+1 when lmul = 2, etc. The current implementation allows using any
vector registers except those exceeding v31.

For vector masking, if the corresponding mask bit is 0, the value of the
destination vector register is preserved. The process is as follows:
1. Copy the destination register.
2. Clear the bits corresponding to VL.
3. Store the computed result in ans.
4. Update the destination register with ans.

If ir->vm == 0, vector masking is activated.

Author: vestata

src/rv32_constopt.c

@@ -1827,5 +1827,4 @@ CONSTOPT(vfwmsac_vv, {})
 CONSTOPT(vfwmsac_vf, {})
 CONSTOPT(vfwnmsac_vv, {})
 CONSTOPT(vfwnmsac_vf, {})
-
 #endif