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add underline to private members vars of ClockRib
1 parent 19e337b commit 221fafe

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2 files changed

+67
-67
lines changed

2 files changed

+67
-67
lines changed

vpr/src/route/rr_graph_generation/clock_network_builders.cpp

Lines changed: 56 additions & 56 deletions
Original file line numberDiff line numberDiff line change
@@ -96,12 +96,12 @@ ClockType ClockRib::get_network_type() const {
9696
*/
9797

9898
void ClockRib::set_metal_layer(float r_metal, float c_metal) {
99-
x_chan_wire.layer.r_metal = r_metal;
100-
x_chan_wire.layer.c_metal = c_metal;
99+
x_chan_wire_.layer.r_metal = r_metal;
100+
x_chan_wire_.layer.c_metal = c_metal;
101101
}
102102

103103
void ClockRib::set_metal_layer(MetalLayer metal_layer) {
104-
x_chan_wire.layer = metal_layer;
104+
x_chan_wire_.layer = metal_layer;
105105
}
106106

107107
void ClockRib::set_initial_wire_location(int start_x, int end_x, int y) {
@@ -112,9 +112,9 @@ void ClockRib::set_initial_wire_location(int start_x, int end_x, int y) {
112112
end_x, start_x);
113113
}
114114

115-
x_chan_wire.start = start_x;
116-
x_chan_wire.length = end_x - start_x;
117-
x_chan_wire.position = y;
115+
x_chan_wire_.start = start_x;
116+
x_chan_wire_.length = end_x - start_x;
117+
x_chan_wire_.position = y;
118118
}
119119

120120
void ClockRib::set_wire_repeat(int repeat_x, int repeat_y) {
@@ -124,29 +124,29 @@ void ClockRib::set_wire_repeat(int repeat_x, int repeat_y) {
124124
repeat_x, repeat_y);
125125
}
126126

127-
repeat.x = repeat_x;
128-
repeat.y = repeat_y;
127+
repeat_.x = repeat_x;
128+
repeat_.y = repeat_y;
129129
}
130130

131131
void ClockRib::set_drive_location(int offset_x) {
132-
drive.offset = offset_x;
132+
drive_.offset = offset_x;
133133
}
134134

135135
void ClockRib::set_drive_switch(int switch_idx) {
136-
drive.switch_idx = switch_idx;
136+
drive_.switch_idx = switch_idx;
137137
}
138138

139139
void ClockRib::set_drive_name(std::string name) {
140-
drive.name = name;
140+
drive_.name = name;
141141
}
142142

143143
void ClockRib::set_tap_locations(int offset_x, int increment_x) {
144-
tap.offset = offset_x;
145-
tap.increment = increment_x;
144+
tap_.offset = offset_x;
145+
tap_.increment = increment_x;
146146
}
147147

148148
void ClockRib::set_tap_name(std::string name) {
149-
tap.name = name;
149+
tap_.name = name;
150150
}
151151

152152
/*
@@ -160,52 +160,52 @@ void ClockRib::create_segments(std::vector<t_segment_inf>& segment_inf) {
160160

161161
// Drive point segment
162162
segment_inf.emplace_back();
163-
drive_seg_idx = segment_inf.size() - 1;
163+
drive_seg_idx_ = segment_inf.size() - 1;
164164

165-
index = drive_seg_idx;
165+
index = drive_seg_idx_;
166166
name = clock_name_ + "_drive";
167167
length = 1; // Since drive segment has one length, the left and right segments have length - 1
168168

169169
/*AA: ClockRibs are assumed to be horizontal currently. */
170170

171-
populate_segment_values(index, name, length, x_chan_wire.layer, segment_inf, e_parallel_axis::X_AXIS);
171+
populate_segment_values(index, name, length, x_chan_wire_.layer, segment_inf, e_parallel_axis::X_AXIS);
172172

173173
// Segment to the right of the drive point
174174
segment_inf.emplace_back();
175-
right_seg_idx = segment_inf.size() - 1;
175+
right_seg_idx_ = segment_inf.size() - 1;
176176

177-
index = right_seg_idx;
177+
index = right_seg_idx_;
178178
name = clock_name_ + "_right";
179-
length = (x_chan_wire.length - drive.offset) - 1;
179+
length = (x_chan_wire_.length - drive_.offset) - 1;
180180

181-
populate_segment_values(index, name, length, x_chan_wire.layer, segment_inf, e_parallel_axis::X_AXIS);
181+
populate_segment_values(index, name, length, x_chan_wire_.layer, segment_inf, e_parallel_axis::X_AXIS);
182182

183183
// Segment to the left of the drive point
184184
segment_inf.emplace_back();
185-
left_seg_idx = segment_inf.size() - 1;
185+
left_seg_idx_ = segment_inf.size() - 1;
186186

187-
index = left_seg_idx;
187+
index = left_seg_idx_;
188188
name = clock_name_ + "_left";
189-
length = drive.offset - 1;
189+
length = drive_.offset - 1;
190190

191-
populate_segment_values(index, name, length, x_chan_wire.layer, segment_inf, e_parallel_axis::X_AXIS);
191+
populate_segment_values(index, name, length, x_chan_wire_.layer, segment_inf, e_parallel_axis::X_AXIS);
192192
}
193193

194194
size_t ClockRib::estimate_additional_nodes(const DeviceGrid& grid) {
195195
// Avoid an infinite loop
196-
VTR_ASSERT(repeat.y > 0);
197-
VTR_ASSERT(repeat.x > 0);
196+
VTR_ASSERT(repeat_.y > 0);
197+
VTR_ASSERT(repeat_.x > 0);
198198

199199
size_t num_additional_nodes = 0;
200-
for (unsigned y = x_chan_wire.position; y < grid.height() - 1; y += repeat.y) {
201-
for (unsigned x_start = x_chan_wire.start; x_start < grid.width() - 1; x_start += repeat.x) {
202-
unsigned drive_x = x_start + drive.offset;
203-
unsigned x_end = x_start + x_chan_wire.length;
200+
for (unsigned y = x_chan_wire_.position; y < grid.height() - 1; y += repeat_.y) {
201+
for (unsigned x_start = x_chan_wire_.start; x_start < grid.width() - 1; x_start += repeat_.x) {
202+
unsigned drive_x = x_start + drive_.offset;
203+
unsigned x_end = x_start + x_chan_wire_.length;
204204

205205
// Adjust for boundry conditions
206206
int x_offset = 0;
207207
if ((x_start == 0) || // CHANX wires left boundry
208-
(x_start + repeat.x == x_end)) // Avoid overlap
208+
(x_start + repeat_.x == x_end)) // Avoid overlap
209209
{
210210
x_offset = 1;
211211
}
@@ -244,22 +244,22 @@ void ClockRib::create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGraphB
244244
int ptc_num = clock_graph.get_and_increment_chanx_ptc_num(); // used for drawing
245245

246246
// Avoid an infinite loop
247-
VTR_ASSERT(repeat.y > 0);
248-
VTR_ASSERT(repeat.x > 0);
247+
VTR_ASSERT(repeat_.y > 0);
248+
VTR_ASSERT(repeat_.x > 0);
249249

250250
// TODO: This function is not adapted to the multi-layer grid
251251
VTR_ASSERT(g_vpr_ctx.device().grid.get_num_layers() == 1);
252252
int layer_num = 0;
253253

254-
for (unsigned y = x_chan_wire.position; y < grid.height() - 1; y += repeat.y) {
255-
for (unsigned x_start = x_chan_wire.start; x_start < grid.width() - 1; x_start += repeat.x) {
256-
unsigned drive_x = x_start + drive.offset;
257-
unsigned x_end = x_start + x_chan_wire.length;
254+
for (unsigned y = x_chan_wire_.position; y < grid.height() - 1; y += repeat_.y) {
255+
for (unsigned x_start = x_chan_wire_.start; x_start < grid.width() - 1; x_start += repeat_.x) {
256+
unsigned drive_x = x_start + drive_.offset;
257+
unsigned x_end = x_start + x_chan_wire_.length;
258258

259259
// Adjust for boundry conditions
260260
int x_offset = 0;
261261
if ((x_start == 0) || // CHANX wires left boundry
262-
(x_start + repeat.x == x_end)) // Avoid overlap
262+
(x_start + repeat_.x == x_end)) // Avoid overlap
263263
{
264264
x_offset = 1;
265265
}
@@ -296,7 +296,7 @@ void ClockRib::create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGraphB
296296
Direction::BIDIR,
297297
rr_nodes,
298298
rr_graph_builder);
299-
clock_graph.add_switch_location(get_name(), drive.name, drive_x, y, drive_node_idx);
299+
clock_graph.add_switch_location(get_name(), drive_.name, drive_x, y, drive_node_idx);
300300

301301
// create rib wire to the right and left of the drive point
302302
auto left_node_idx = create_chanx_wire(layer_num,
@@ -323,8 +323,8 @@ void ClockRib::create_rr_nodes_and_internal_edges_for_one_instance(ClockRRGraphB
323323
clock_graph);
324324

325325
// connect drive point to each half rib using a directed switch
326-
clock_graph.add_edge(rr_edges_to_create, RRNodeId(drive_node_idx), RRNodeId(left_node_idx), drive.switch_idx, false);
327-
clock_graph.add_edge(rr_edges_to_create, RRNodeId(drive_node_idx), RRNodeId(right_node_idx), drive.switch_idx, false);
326+
clock_graph.add_edge(rr_edges_to_create, RRNodeId(drive_node_idx), RRNodeId(left_node_idx), drive_.switch_idx, false);
327+
clock_graph.add_edge(rr_edges_to_create, RRNodeId(drive_node_idx), RRNodeId(right_node_idx), drive_.switch_idx, false);
328328
}
329329
}
330330
}
@@ -346,20 +346,20 @@ int ClockRib::create_chanx_wire(int layer,
346346
rr_graph_builder.set_node_layer(chanx_node, layer, layer);
347347
rr_graph_builder.set_node_capacity(chanx_node, 1);
348348
rr_graph_builder.set_node_track_num(chanx_node, ptc_num);
349-
const NodeRCIndex rc_index = find_create_rr_rc_data(x_chan_wire.layer.r_metal, x_chan_wire.layer.c_metal, g_vpr_ctx.mutable_device().rr_rc_data);
349+
const NodeRCIndex rc_index = find_create_rr_rc_data(x_chan_wire_.layer.r_metal, x_chan_wire_.layer.c_metal, g_vpr_ctx.mutable_device().rr_rc_data);
350350
rr_graph_builder.set_node_rc_index(chanx_node, rc_index);
351351
rr_graph_builder.set_node_direction(chanx_node, direction);
352352

353353
short seg_index = 0;
354354
switch (direction) {
355355
case Direction::BIDIR:
356-
seg_index = drive_seg_idx;
356+
seg_index = drive_seg_idx_;
357357
break;
358358
case Direction::DEC:
359-
seg_index = left_seg_idx;
359+
seg_index = left_seg_idx_;
360360
break;
361361
case Direction::INC:
362-
seg_index = right_seg_idx;
362+
seg_index = right_seg_idx_;
363363
break;
364364
default:
365365
VTR_ASSERT_MSG(false, "Unidentified direction type for clock rib");
@@ -386,11 +386,11 @@ void ClockRib::record_tap_locations(unsigned x_start,
386386
int left_rr_node_idx,
387387
int right_rr_node_idx,
388388
ClockRRGraphBuilder& clock_graph) {
389-
for (unsigned x = x_start + tap.offset; x <= x_end; x += tap.increment) {
390-
if (x < (x_start + drive.offset - 1)) {
391-
clock_graph.add_switch_location(get_name(), tap.name, x, y, left_rr_node_idx);
389+
for (unsigned x = x_start + tap_.offset; x <= x_end; x += tap_.increment) {
390+
if (x < (x_start + drive_.offset - 1)) {
391+
clock_graph.add_switch_location(get_name(), tap_.name, x, y, left_rr_node_idx);
392392
} else {
393-
clock_graph.add_switch_location(get_name(), tap.name, x, y, right_rr_node_idx);
393+
clock_graph.add_switch_location(get_name(), tap_.name, x, y, right_rr_node_idx);
394394
}
395395
}
396396
}
@@ -401,14 +401,14 @@ void ClockRib::map_relative_seg_indices(const t_unified_to_parallel_seg_index& i
401401

402402
int seg_idx;
403403

404-
seg_idx = get_parallel_seg_index(drive_seg_idx, indices_map, e_parallel_axis::X_AXIS);
405-
drive_seg_idx = (seg_idx >= 0) ? seg_idx : drive_seg_idx;
404+
seg_idx = get_parallel_seg_index(drive_seg_idx_, indices_map, e_parallel_axis::X_AXIS);
405+
drive_seg_idx_ = (seg_idx >= 0) ? seg_idx : drive_seg_idx_;
406406

407-
seg_idx = get_parallel_seg_index(left_seg_idx, indices_map, e_parallel_axis::X_AXIS);
408-
left_seg_idx = (seg_idx >= 0) ? seg_idx : left_seg_idx;
407+
seg_idx = get_parallel_seg_index(left_seg_idx_, indices_map, e_parallel_axis::X_AXIS);
408+
left_seg_idx_ = (seg_idx >= 0) ? seg_idx : left_seg_idx_;
409409

410-
seg_idx = get_parallel_seg_index(right_seg_idx, indices_map, e_parallel_axis::X_AXIS);
411-
right_seg_idx = (seg_idx >= 0) ? seg_idx : right_seg_idx;
410+
seg_idx = get_parallel_seg_index(right_seg_idx_, indices_map, e_parallel_axis::X_AXIS);
411+
right_seg_idx_ = (seg_idx >= 0) ? seg_idx : right_seg_idx_;
412412
}
413413

414414
/*********************************************************************************

vpr/src/route/rr_graph_generation/clock_network_builders.h

Lines changed: 11 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -119,28 +119,28 @@ class ClockNetwork {
119119
class ClockRib : public ClockNetwork {
120120
private:
121121
// start and end x and position in the y
122-
Wire x_chan_wire;
123-
WireRepeat repeat;
122+
Wire x_chan_wire_;
123+
WireRepeat repeat_;
124124

125125
// offset in the x
126-
RibDrive drive;
126+
RibDrive drive_;
127127

128128
// offset and incr in the x
129-
RibTaps tap;
129+
RibTaps tap_;
130130

131131
// segment indices
132-
int right_seg_idx = UNDEFINED;
133-
int left_seg_idx = UNDEFINED;
134-
int drive_seg_idx = UNDEFINED;
132+
int right_seg_idx_ = UNDEFINED;
133+
int left_seg_idx_ = UNDEFINED;
134+
int drive_seg_idx_ = UNDEFINED;
135135

136136
public:
137137
/** Constructor**/
138138
ClockRib() {} // default
139139
ClockRib(Wire wire1, WireRepeat repeat1, RibDrive drive1, RibTaps tap1)
140-
: x_chan_wire(wire1)
141-
, repeat(repeat1)
142-
, drive(drive1)
143-
, tap(tap1) {}
140+
: x_chan_wire_(wire1)
141+
, repeat_(repeat1)
142+
, drive_(drive1)
143+
, tap_(tap1) {}
144144
/*
145145
* Getters
146146
*/

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