From 7b79b00bf8bf0e43bb41079f15f0985092167ef9 Mon Sep 17 00:00:00 2001
From: Andreas Olofsson <andreas@zeroasic.com>
Date: Sun, 25 Jan 2026 23:43:07 -0500
Subject: [PATCH 1/2] Extending lambdalib range

---
 pyproject.toml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/pyproject.toml b/pyproject.toml
index 5cf90d03..946dcfdb 100644
--- a/pyproject.toml
+++ b/pyproject.toml
@@ -19,7 +19,7 @@ requires-python = ">= 3.9"
 license = {file = "LICENSE"}
 dependencies = [
     "siliconcompiler >= 0.35.0",
-    "lambdalib >= 0.4.0, < 0.9.0"
+    "lambdalib >= 0.4.0, < 0.10.0"
 ]
 dynamic = ["version"]
 

From ac2f245793b4bfa05787368970eca3eaa2c6f736 Mon Sep 17 00:00:00 2001
From: Andreas Olofsson <andreas@zeroasic.com>
Date: Sun, 25 Jan 2026 23:43:26 -0500
Subject: [PATCH 2/2] Fixing memory addres bug - MAW does not belong here,
 should be set by downstream mem

---
 umi/sumi/umi_memif/rtl/umi_memif.v | 39 +++++++++++++++---------------
 1 file changed, 19 insertions(+), 20 deletions(-)

diff --git a/umi/sumi/umi_memif/rtl/umi_memif.v b/umi/sumi/umi_memif/rtl/umi_memif.v
index f26b5d0f..340889ff 100644
--- a/umi/sumi/umi_memif/rtl/umi_memif.v
+++ b/umi/sumi/umi_memif/rtl/umi_memif.v
@@ -17,30 +17,29 @@
 
 module umi_memif
   #(parameter DW = 256, // umi packet width
-    parameter AW = 64,  // umi address width
-    parameter MAW = 32  // ram address width
+    parameter AW = 64   // umi address width
     )
    (// ctrls
-    input            clk,
-    input            nreset,
+    input           clk,
+    input           nreset,
     // umi interface
-    input            umi_read,   // memory read
-    input            umi_write,  // memory write
-    input            umi_atomic, // read-modify-write
-    input [2:0]      umi_size,   // 1 --> DW/8 byte
-    input [7:0]      umi_len,    // total transfers = LEN + 1
-    input [7:0]      umi_atype,  // atomic type
-    input [AW-1:0]   umi_addr,   // size aligned address
-    input [DW-1:0]   umi_wrdata,
-    output [DW-1:0]  umi_rddata,
-    output           umi_ready,
+    input           umi_read,   // memory read
+    input           umi_write,  // memory write
+    input           umi_atomic, // read-modify-write
+    input [2:0]     umi_size,   // 1 --> DW/8 byte
+    input [7:0]     umi_len,    // total transfers = LEN + 1
+    input [7:0]     umi_atype,  // atomic type
+    input [AW-1:0]  umi_addr,   // size aligned address
+    input [DW-1:0]  umi_wrdata,
+    output [DW-1:0] umi_rddata,
+    output          umi_ready,
     // mem interface
-    output           mem_ce,
-    output           mem_we,
-    output [MAW-1:0] mem_addr,
-    output [DW-1:0]  mem_wrmask,
-    output [DW-1:0]  mem_wrdata,
-    input [DW-1:0]   mem_rddata
+    output          mem_ce,
+    output          mem_we,
+    output [AW-1:0] mem_addr,
+    output [DW-1:0] mem_wrmask,
+    output [DW-1:0] mem_wrdata,
+    input [DW-1:0]  mem_rddata
     );
 
    // local state