Alert_l: Modify APML ALERT_L to remove the dependency of RMI/TSI dts device node.

Documentation/devicetree/bindings/misc/amd,apml-alertl.yaml

@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/hwmon/amd,apml-alertl.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: >
+  Sideband Remote Management Interface (SB-RMI) and Temperature Sensor Interface
+  (SB-TSI) compliant AMD APML Alert_L GPIO.
+
+maintainers:
+  - Akshay Gupta <Akshay.Gupta@amd.com>
+
+description: |
+  Processors from AMD provide APML ALERT_L for BMC users to
+  monitor events.
+  APML Alert_L is asserted in multiple events,
+  - Machine Check Exception occurs within the system
+  - The processor alerts the SBI on system fatal error event
+  - Set by hardware as a result of a 0x71/0x72/0x73 command completion
+  - Set by firmware to indicate the completion of a mailbox operation
+  - High/Low Temperature Alert
+
+  APML Alert_L module define uevents to notify userspace of the
+  alert event.
+
+properties:
+  compatible:
+    const: apml-alertl
+
+  gpio:
+    maxItems: 1
+    description: |
+     GPIO specifier for APML Alert_L line. Specify GPIO controller, GPIO pin
+     and polarity.
+
+  socket-num:
+   $ref: /schemas/types.yaml#/definitions/uint32
+   minimum: 0
+   maximum: 255
+   description: |
+    Socket identifier for multi-socket AMD systems. This property identifies
+    which CPU socket this Alert_L GPIO is associated with.
+
+required:
+  - compatible
+  - gpio
+  - socket-num
+
+additionalProperties: false
+
+examples:
+  - |
+    /* Alert_L associated with Socket 0 */
+    alertl_sock0 {
+        compatible = "apml-alertl";
+        status = "okay";
+        gpios = <&ltpi0_gpio 20 GPIO_ACTIVE_LOW>;
+        socket-num =  /bits/ 8 <1>;
+    };
+...

arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-congo.dts

@@ -882,6 +882,16 @@
 	};
 };
 
+/ {
+	/* Alert_L associated with socket 0 */
+	alertl_sock0 {
+		compatible = "apml-alertl";
+		status = "okay";
+		socket-num =  /bits/ 8 <0>;
+		gpios = <&ltpi0_gpio 20 GPIO_ACTIVE_LOW>;
+	};
+};
+
 #ifdef I3C_HUB
 
 #define JESD300_SPD_I3C_MODE(bus, index, addr) \

arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-kenya.dts

@@ -572,6 +572,16 @@
 	};
 };
 
+/ {
+	/* Alert_L associated with socket 0 */
+	alertl_sock0 {
+		compatible = "apml-alertl";
+		status = "okay";
+		socket-num =  /bits/ 8 <0>;
+		gpios = <&ltpi0_gpio 20 GPIO_ACTIVE_LOW>;
+	};
+};
+
 #ifdef I3C_HUB
 
 #define JESD300_SPD_I3C_MODE(bus, index, addr) \

arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-morocco.dts

@@ -970,6 +970,24 @@
 	};
 };
 
+/ {
+	/* Alert_L associated with socket 0 */
+	alertl_sock0 {
+		compatible = "apml-alertl";
+		status = "okay";
+		socket-num =  /bits/ 8 <0>;
+		gpios = <&ltpi0_gpio 20 GPIO_ACTIVE_LOW>;
+	};
+
+	/* Alert_L associated with socket 1 */
+	alertl_sock1 {
+		compatible = "apml-alertl";
+		status = "okay";
+		socket-num =  /bits/ 8 <1>;
+		gpios = <&ltpi0_gpio 104 GPIO_ACTIVE_LOW>;
+	};
+};
+
 #ifdef I3C_HUB
 
 #define JESD300_SPD_I3C_MODE(bus, index, addr) \

arch/arm64/boot/dts/aspeed/aspeed-bmc-amd-nigeria.dts

@@ -741,6 +741,24 @@
 	};
 };
 
+/ {
+	/* Alert_L associated with socket 0 */
+	alertl_sock0 {
+		compatible = "apml-alertl";
+		status = "okay";
+		socket-num =  /bits/ 8 <0>;
+		gpios = <&ltpi0_gpio 20 GPIO_ACTIVE_LOW>;
+	};
+
+	/* Alert_L associated with socket 1 */
+	alertl_sock1 {
+		compatible = "apml-alertl";
+		status = "okay";
+		socket-num =  /bits/ 8 <1>;
+		gpios = <&ltpi0_gpio 104 GPIO_ACTIVE_LOW>;
+	};
+};
+
 #ifdef I3C_HUB
 
 #define JESD300_SPD_I3C_MODE(bus, index, addr) \

drivers/misc/amd-apml/Kconfig

@@ -3,9 +3,22 @@
 # AMD APML BMC interface drivers
 #
 
+config APML_COMMON
+    tristate "AMD APML common device registration framework"
+    default n
+    help
+      Enable support for the AMD APML (Advanced Platform Management Link)
+      common device registration framework. This module provides a centralized
+      registry where APML devices (SBRMI and SBTSI) can register themselves
+      for discovery by other APML subsystems.
+
+      This framework enables the Alert_L driver to safely discover and access
+      registered APML devices for alert processing across multiple sockets.
+
 config APML_SBRMI
     tristate "Emulated SB-RMI interface driver over i3c bus"
     depends on I3C && !SENSORS_SBRMI
+    depends on APML_COMMON
     select REGMAP_I3C if I3C
     help
       If you say yes here you get support for emulated RMI
@@ -17,10 +30,27 @@ config APML_SBRMI
 config APML_SBTSI
     tristate "Emulated SB-TSI interface driver over i3c bus"
     depends on I3C && !SENSORS_SBTSI
+    depends on APML_COMMON
     select REGMAP_I3C if I3C
     help
       If you say yes here you get support for emulated TSI
       interface on AMD SoCs with APML interface connected to a BMC device.
 
       This driver can also be built as a module. If so, the module will
       be called apml_sbtsi.
+
+config APML_ALERTL
+    tristate "Emulated apml alertl interface driver over i3c bus"
+    depends on (APML_SBRMI || APML_SBTSI) && APML_COMMON
+    default n
+    help
+      This driver provides support for AMD APML Alert_L interface,
+      enabling alert notification from AMD SoCs to a BMC (Baseboard
+      Management Controller) over I2C/I3C bus.
+
+      The driver monitors RAS and thermal events by handling alerts
+      from SBRMI and SBTSI devices, and reports these events to userspace
+      via uevents. Device configuration is managed via device tree bindings.
+
+      This driver can also be built as a module. If so, the module will
+      be called apml_alertl.ko.

drivers/misc/amd-apml/Makefile

@@ -4,5 +4,7 @@
 # AMD APML BMC interface drivers
 #
 
+obj-$(CONFIG_APML_COMMON)	+= apml_common.o
 obj-$(CONFIG_APML_SBRMI)	+= sbrmi.o sbrmi-common.o
 obj-$(CONFIG_APML_SBTSI)	+= apml_sbtsi.o
+obj-$(CONFIG_APML_ALERTL)	+= apml_alertl.o