Name		Name	Last commit message	Last commit date
Latest commit History 10 Commits
Single Port RAM.cache		Single Port RAM.cache
Single Port RAM.hw		Single Port RAM.hw
Single Port RAM.sim/sim_1/behav/xsim		Single Port RAM.sim/sim_1/behav/xsim
Single Port RAM.srcs		Single Port RAM.srcs
Single-Port-RAM.cache/sim		Single-Port-RAM.cache/sim
LICENSE		LICENSE
README.md		README.md
Single Port RAM.xpr		Single Port RAM.xpr

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Single-Port-RAM

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This project implements a single-port RAM using Verilog. The design simulates a memory module with a single read/write port, supporting basic memory operations like data storage and retrieval. It includes testbenches for functional verification and timing analysis to ensure reliable operation.