Engineer focused on design verification — I like understanding how hardware is supposed to behave, then building the environment that proves it actually does.
My work is mostly in SystemVerilog and UVM: testbenches with multiple agents, scoreboards, RAL models, functional coverage, and SVA assertions. I know my way around constrained-random stimulus, coverage-driven verification, and writing tests that actually find bugs — not just ones that pass. I've also done RTL design (FPGA, multi-clock SoCs), which helps when you need to think about what you're verifying, not just how.
On the tools side, I've worked with QuestaSim for simulation and have experience with CDC analysis. Comfortable reading specs, translating them into a verification plan, and closing coverage.
A handful of projects I built to get real reps in DV — full environments,
not just hello-world examples. The portfolio repo is the best starting point.
A DV role where I can hit the ground running. I'm comfortable with UVM methodology, I pick things up fast, and I'm genuinely interested in the work — not just looking for any job in the field.