Search results

Can ALLbank refresh be disabled in the simulation?

Status: Open.

#111 In CMU-SAFARI/ramulator2;

· zhengfugirl opened on Mar 26, 2026

The value of s_read_latency is too small in the simulation, and also the model does not calculate the write latency for write operations.

Status: Open.

#109 In CMU-SAFARI/ramulator2;

· zhengfugirl opened on Mar 26, 2026

Read latency statistics

Status: Open.

#100 In CMU-SAFARI/ramulator2;

· maheredia opened on Dec 1, 2025

Why tCK_ps in LPDDR5 is always recalculated and is different from the default value in timing_presets

Status: Open.

#83 In CMU-SAFARI/ramulator2;

· EricHnbc opened on Mar 21, 2025

DRAM Ramulator2 simulation time in gem5 keep 50.02%

Status: Open.

#72 In CMU-SAFARI/ramulator2;

· The-CliffWu opened on Dec 8, 2024

Multi-channel Ramulator + GEM5

Status: Open.

#69 In CMU-SAFARI/ramulator2;

· arkhadem opened on Oct 21, 2024

Calculate BW from the stats

Status: Open.

#51 In CMU-SAFARI/ramulator2;

· alinezhad2018 opened on Jun 24, 2024

SimpleO3 front end show significant Cache bandwidth bound when doing sequential memory access test.

Status: Open.

#49 In CMU-SAFARI/ramulator2;

· zzczzc20 opened on Jun 17, 2024

Invalid Condition in BH controller

Status: Open.

#45 In CMU-SAFARI/ramulator2;

· Arash1381-y opened on May 10, 2024

HBM Device Code seems to require a Rank level for use with SID."

Status: Open.

#38 In CMU-SAFARI/ramulator2;

· najun-auto opened on Mar 20, 2024

Inquiry about LPDDR5 Timing Parameters

Status: Open.

#34 In CMU-SAFARI/ramulator2;

· Chilly20011008 opened on Jan 21, 2024