CaltechOpticalObservatories · prkrtg · Mar 9, 2026 · Mar 9, 2026
diff --git a/src/kpf/kpf.cds b/src/kpf/kpf.cds
@@ -0,0 +1,42 @@
+/* -*- C -*- */
+/** ---------------------------------------------------------------------------
+ * @file   kpf.cds
+ * @brief  CDS/Deinterlace parameters for KPF instrument
+ */
+
+BIGBUF=_ARCHON_FRAMEBUFS
+FRAMEMODE=_ARCHON_FRAMEMODE
+LINECOUNT=_LINES_PER_TAP /* _CDS_LINES_PER_TAP */
+PIXELCOUNT=_PIXELS_PER_TAP /* _CDS_PIXELS_PER_TAP */
+RAWENABLE=_RAW_ENABLE
+RAWENDLINE=_RAW_ENDLINE
+RAWSAMPLES=_RAW_SAMPLES
+RAWSEL=_RAW_SELECT
+RAWSTARTLINE=_RAW_STARTLINE
+RAWSTARTPIXEL=_RAW_STARTPIXEL
+SAMPLEMODE=_ARCHON_SAMPLE_MODE
+SHP1=_FIRST_RESET_SAMPLE
+SHP2=_LAST_RESET_SAMPLE
+SHD1=_FIRST_VIDEO_SAMPLE
+SHD2=_LAST_VIDEO_SAMPLE
+TAPLINE0="AD1L,1,100"
+TAPLINE1="AD2R,1,100"
+TAPLINE2="AD3L,1,100"
+TAPLINE3="AD4R,1,100"
+TAPLINE4=""
+TAPLINE5=""
+TAPLINE6=""
+TAPLINE7=""
+TAPLINE8=""
+TAPLINE9=""
+TAPLINE10=""
+TAPLINE11=""
+TAPLINE12=""
+TAPLINE13=""
+TAPLINE14=""
+TAPLINE15=""
+TAPLINES=4
+TRIGOUTFORCE=0
+TRIGOUTINVERT=0
+TRIGOUTLEVEL=0
+TRIGOUTPOWER=1
diff --git a/src/kpf/kpf.conf b/src/kpf/kpf.conf
@@ -0,0 +1,22 @@
+/** ---------------------------------------------------------------------------
+ * @file     kpf.conf 
+ * @brief    WDL configuration file for KPF project
+ * @author   Stephen Kaye
+ * @date     2019-04-19 (created)
+ * @modified
+ *
+ * This file needs to identify the following four files:
+ *   WAVEFORM_FILE = <filename>
+ *   SYSTEM_FILE   = <filename>
+ *   SIGNAL_FILE   = <filename>
+ *   SEQUENCE_FILE = <filename>
+ *
+ */
+
+INCLUDE_FILE  = "kpf.def"        /* #defines and usage are self contained */
+CDS_FILE      = "kpf.cds"        /* uses #defines from .def file          */
+SIGNAL_FILE   = "kpf.signals"    /* #defines and usage are self contained */
+WAVEFORM_FILE = "kpf.waveform"   /* uses #defines from .def and .signals  */
+SEQUENCE_FILE = "kpf.seq"        /* uses #defines from .def and .waveform */
+MODULE_FILE   = "kpf.mod"        /* #defines and usage are self contained */
+MODE_FILE     = "kpf.modes"
diff --git a/src/kpf/kpf.def b/src/kpf/kpf.def
@@ -0,0 +1,94 @@
+/** -*- C -*- ---------------------------------------------------------------------------
+ * use "#define" to define user macros used within the Archon files,
+ * i.e. within the .script, .states, .cds, or .modules files
+ * Do not edit or remove the following line.
+ */
+
+/** ---------------------------------------------------------------------------
+ * Various configuration modes
+ */
+#define _SER_PATTERN_PIXELS_REAL 2       /* Num real pixels to clock */
+#define _SER_PATTERN_PIXELS_NOP  2       /* Num dummy pixels */
+
+#define _SHDEL                   470       /* miliseconds to delay before readout to allow shutter to close */ /* Add to 30 ms to turn the amps back on so we have a total delay time of 500 ms for shutter close */
+
+/** ---------------------------------------------------------------------------
+ * CDS-Deinterlace options
+ */
+#define _SKIP_LINES              0 /*0*/
+#define _SERIALPRESCAN           4
+#define _SERIALOVERSCAN          30 /* Use overscan for intial tests */
+#define _PARALLELOVERSCAN        50 /* Use overscan for initial tests */
+#defeval _IMAGEROWS              #eval 4080/2  /* Value from CCD data sheet (quadrant) */
+#defeval _IMAGECOLS              #eval 4080/2  /* Value from CCD data sheet (quadrant) */
+#defeval _IDLE_LINES             #eval _SKIP_LINES + _IMAGEROWS
+
+/* Are these lines for raw data? Keep, but comment out */
+/*#define _RAW_LINES                   2 */
+/*#defeval _CDS_LINES_PER_TAP          2 *//*#eval _IMAGEROWS + _PARALLELOVERSCAN - _SKIP_LINES*/
+/*#defeval _CDS_PIXELS_PER_TAP         2 *//*#eval _IMAGECOLS + _SERIALPRESCAN + _SERIALOVERSCAN*/ /*3272*/ /*3072*/
+
+#defeval _LINES_PER_TAP          #eval _IMAGEROWS + _PARALLELOVERSCAN - _SKIP_LINES
+#defeval _PIXELS_PER_TAP         #eval _IMAGECOLS + _SERIALPRESCAN + _SERIALOVERSCAN /*3272*/ /*3072*/
+
+/* This is for concurrent clocking, but need to divide by 3 since only 3 parallel phases */
+#defeval _PIXBYTHREE             #eval (_IMAGECOLS + _SERIALPRESCAN + _SERIALOVERSCAN)/3
+#defeval NumReads                #eval (_SERIALPRESCAN + _IMAGECOLS + _SERIALOVERSCAN)/3 - 1  /* Number of reads in concurrent clocking */
+
+
+/* The following define the pixel time and the width of some clocks */
+#define PixelT       84 /* Full pixel time */
+#define RGsettleT    17 /* Settling Time for the reset gate */
+#define SWsettleT    16 /* Settling Time for the summing well (charge dump) */
+
+#define _FIRST_RESET_SAMPLE      #eval RGsettleT    /* Start sampling after reset gate settling */
+#define _LAST_RESET_SAMPLE       #eval PixelT/2 - 1 /* End sampling at half of the pixel time   */
+#define _FIRST_VIDEO_SAMPLE      #eval PixelT/2 - 1 + SWsettleT /* Start sampling after summing well settling */
+#define _LAST_VIDEO_SAMPLE       #eval PixelT - 1               /* End sampling at the end of the pixel time  */
+
+#define _ARCHON_SAMPLE_MODE        1     /* 0=16bit, 1=32bit  */
+#define _ARCHON_FRAMEMODE          2     /* 0=top, 1=bottom, 2=split */
+#define _ARCHON_FRAMEBUFS          0     /* 0=3x512MB, 1=2x768MB, I.E. "BIGBUF" */
+
+/* This is information for raw sampling mode */
+#define _RAW_ENABLE                0 /* 0=no, 1=yes */
+#define _RAW_STARTLINE             0 /* first line of raw data, 0-65535 */
+#define _RAW_ENDLINE              10 /* last line of raw data, 0-65535 */
+#define _RAW_STARTPIXEL            0
+#define _RAW_SAMPLES           25600
+#define _RAW_SELECT               3  /* AD channel for raw data capture, 0-15 */
+
+/** ---------------------------------------------------------------------------
+ * Define clock voltage levels here (units are Volts)
+ */
+/* ____________________
+ * Clock voltage and the biases will be hard coded for the parallel low clock, 
+ * but calculated for the other clocks.  This is due to the data sheet advising
+ * bias and clock levels with respect to parallel clock level low               */
+
+/* Clocks */
+#define _SER_CLOCK_LOW      -5.0
+#define _SER1_CLOCK_LOW     -5.0
+#define _SER2_CLOCK_LOW     -5.0
+#define _SER3_CLOCK_LOW     -5.0
+#define _SER1_CLOCK_HIGH     5.0
+#define _SER2_CLOCK_HIGH     5.0
+#define _SER3_CLOCK_HIGH     5.0
+#define _SER_CLOCK_HIGH      5.0
+
+#define _SER_CLOCK_RCV       8.0 /* This is when charge goes from parallel to serial register */
+
+#define _PAR_CLOCK_IDLE_LOW   -9.0
+#define _PAR_CLOCK_IDLE_HIGH   3.0
+
+#define _PAR_CLOCK_EXP_LOW    -9.0 /* Default to parallel clock levels for now */
+#define _PAR_CLOCK_EXP_HIGH    3.0
+
+#define _PAR_CLOCK_LOW        -9.0
+#define _PAR_CLOCK_HIGH        3.0
+#define _PAR_CLOCK_HIGHEST     3.0
+
+#define _PAR_LASTGATE_HIGH     3.0
+
+#define _TG_CLOCK_LOW         -9.0
+#define _TG_CLOCK_HIGH         3.0
diff --git a/src/kpf/kpf.mod b/src/kpf/kpf.mod
@@ -0,0 +1,107 @@
+/** -*- C -*- **/
+
+#define	Iphi_slew_fast	100    /*100*/
+#define Iphi_slew_slow	 10 /*10*/
+#define Rphi_slew_fast	500 /* 500 was too fast */
+#define Rphi_slew_slow	 29.508 /*33*/
+
+#define TG_slew_fast	500
+#define TG_slew_slow	10
+
+#define BIAS_slew_fast 100
+#define BIAS_slew_slow 50
+
+#define DG_slew_fast 100
+#define DG_slew_slow 50
+
+#define OutputDrain     30.5
+
+#define OutputGate      2.5
+
+#define ResetDrain      18
+
+#define ResetGateHi      8
+#define SummingWellHi    5
+
+
+SLOT 3 lvds {
+  DIO 1 [0,0];
+  DIO 2 [0,0];
+  DIO 3 [0,0];
+  DIO 4 [0,0];
+  DIOPOWER = 0;
+}
+
+SLOT 4 driver {
+  DRV 1 [Rphi_slew_fast,Rphi_slew_slow,1];
+  DRV 2 [Rphi_slew_fast,Rphi_slew_slow,1];
+  DRV 3 [Rphi_slew_fast,Rphi_slew_slow,1];
+  DRV 4 [Rphi_slew_fast,Rphi_slew_slow,1];
+  DRV 5 [Rphi_slew_fast,Rphi_slew_slow,1];
+  DRV 6 [Rphi_slew_fast,Rphi_slew_slow,1];
+  DRV 7 [BIAS_slew_fast,BIAS_slew_slow,1];
+  DRV 8 [BIAS_slew_fast,BIAS_slew_slow,1];
+}
+
+SLOT 5 ad {
+  CLAMP 1 = 1.5;
+  CLAMP 2 = 1.5;
+  CLAMP 3 = 1.5;
+  CLAMP 4 = 1.5;
+  PREAMPGAIN = low;
+}
+
+SLOT 9 hvbias {
+  HVLC 1  [15,0]; /* Reset Drain a          */
+  HVLC 2  [15,0]; /* Reset Drain b          */
+  HVLC 3  [15,0]; /* Reset Drain c          */
+  HVLC 4  [15,0]; /* Reset Drain d          */
+  HVLC 5  [0,0];  /* Spare                  */
+  HVLC 6  [0,0];  /* Spare                  */
+  HVLC 7  [0,0];  /* Spare                  */
+  HVLC 8  [0,0];  /* Spare                  */
+  HVLC 9  [0,0];  /* Spare                  */
+  HVLC 10 [0,0];  /* Spare                  */
+  HVLC 11 [ResetGateHi,0];    /* Reset Gate High Rail   */
+  HVLC 12 [SummingWellHi,0];  /* Summing Well High Rail */
+  HVLC 13 [0,0];  /* Spare                  */
+  HVLC 14 [0,0];  /* Spare                  */
+  HVLC 15 [0,0];  /* Spare                  */
+  HVLC 16 [0,0];  /* Spare                  */
+  HVLC 17 [0,0];  /* Spare                  */
+  HVLC 18 [0,0];  /* Spare                  */
+  HVLC 19 [0,0];  /* Spare                  */
+  HVLC 20 [0,0];  /* Spare                  */
+  HVLC 21 [0,0];  /* Spare                  */
+  HVLC 22 [0,0];  /* Spare                  */
+  HVLC 23 [0,0];  /* Spare                  */
+  HVLC 24 [0,0];  /* Dump Drain All Quads   */
+  HVHC  1 [0,10,0,1];   /* Spare                         */
+  HVHC  2 [0,10,0,1];   /* Spare                         */
+  HVHC  3 [24,100,0,1]; /* Output Drain Top Left     (a) */
+  HVHC  4 [24,100,0,1]; /* Output Drain Top Right    (b) */
+  HVHC  5 [24,100,0,1]; /* Output Drain Bottom Right (c) */
+  HVHC  6 [24,100,0,1]; /* Output Drain Bottom Left  (d) */
+}
+
+SLOT 10 driver {
+  DRV 1 [Iphi_slew_fast,Iphi_slew_slow,1];
+  DRV 2 [Iphi_slew_fast,Iphi_slew_slow,1];
+  DRV 3 [Iphi_slew_fast,Iphi_slew_slow,1];
+  DRV 4 [Iphi_slew_fast,Iphi_slew_slow,1];
+  DRV 5 [Iphi_slew_fast,Iphi_slew_slow,1];
+  DRV 6 [Iphi_slew_fast,Iphi_slew_slow,1];
+  DRV 7 [TG_slew_fast,TG_slew_slow,1];
+  DRV 8 [TG_slew_fast,TG_slew_slow,1];
+}
+
+SLOT 11 driver {
+  DRV 1 [Rphi_slew_fast,Rphi_slew_slow,1];
+  DRV 2 [Rphi_slew_fast,Rphi_slew_slow,1];
+  DRV 3 [Rphi_slew_fast,Rphi_slew_slow,1];
+  DRV 4 [Rphi_slew_fast,Rphi_slew_slow,1];
+  DRV 5 [Rphi_slew_fast,Rphi_slew_slow,1];
+  DRV 6 [Rphi_slew_fast,Rphi_slew_slow,1];
+  DRV 7 [DG_slew_fast,DG_slew_slow,1];
+  DRV 8 [BIAS_slew_fast,BIAS_slew_slow,1];
+}
diff --git a/src/kpf/kpf.modes b/src/kpf/kpf.modes
@@ -0,0 +1,4 @@
+[MODE_DEFAULT]
+ARCH:NUM_CCDS=1
+ARCH:AMPS_PER_CCD_HORI=2
+ARCH:AMPS_PER_CCD_VERT=2