Digital Logic Design I — Verilog Exercises and Simulations

🇬🇷 Ελληνική έκδοση: README_GR.md

This repository contains a collection of Verilog implementations developed as part of a Digital Logic Design I course.
The exercises focus on fundamental concepts of hardware description languages (HDLs), combinational circuit design, hierarchical modeling, and timing analysis.

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📚 Contents

The repository includes solutions to seven laboratory exercises covering:

• Basic combinational circuits
• Logic gates and testbenches
• Multi-level combinational design
• Structural, dataflow, and behavioral modeling
• Hierarchical design using reusable modules
• Multiplexers and decoders
• Binary comparators with delay analysis
• BCD arithmetic circuits
• Ripple-carry and BCD adders
• Worst-case propagation delay estimation
• ModelSim simulations and waveform verification

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🧠 Learning Objectives

These implementations demonstrate:

• Writing synthesizable Verilog code
• Creating effective testbenches
• Comparing alternative hardware architectures
• Understanding propagation delay in digital circuits
• Using hierarchical design to manage complexity
• Verifying correctness through simulation

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🛠 Tools Used

• Verilog HDL
• ModelSim (simulation)
• XeLaTeX (technical report)
• Git for version control

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📂 Repository Structure

.
├── ex 1/
├── ex 2/
├── ex 3/
├── ex 4/
├── ex 5/
├── ex 6/
├── ex 7/
├── report/
└── README.md

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▶️ How to Run Simulations

1. Open ModelSim
2. Compile the desired Verilog files
3. Run the corresponding testbench
4. Inspect waveforms in the simulator

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🎓 Academic Context

This repository was created for educational purposes as part of an undergraduate course in Digital Logic Design.

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📜 License

This repository is intended for educational use only.