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1. vesp-alpha vesp-alpha Public archive

   RISC-V based student processor for embedded applications.

   SystemVerilog 3

2. riscv-tests riscv-tests Public

   Forked from riscv-software-src/riscv-tests

   C 1

3. jtag-example-basys3 jtag-example-basys3 Public

   Forked from freecores/jtag

   JTAG Test Access Port (TAP)

   Verilog 1

4. vesp-jtag vesp-jtag Public

   Forked from diegoherranz/steppenprobe

   Open Source Hardware JTAG/UART/GPIO interface board

   1

5. vesp-beta vesp-beta Public

   Single-cycle simplistic RISC-V RV32IMZicsr CPU accompanied by Wishbone SoC for educational purposes.

   C

6. wb-modules wb-modules Public

   Various Wishbone modules for VESP project.

   SystemVerilog