GitHub - KevinWahle/E5-FPGA: Procesador con pipeline de 5 etapas compatible con el set de instrucciones RV32-I en una arquitectura RISC-V

Name		Name	Last commit message	Last commit date
Latest commit History 22 Commits
.qsys_edit		.qsys_edit
db		db
greybox_tmp		greybox_tmp
incremental_db		incremental_db
output_files		output_files
simulation		simulation
HALCtrl.v.bak		HALCtrl.v.bak
HALTCtrl.v		HALTCtrl.v
HALTCtrl.v.bak		HALTCtrl.v.bak
HALT_ctrl.bsf		HALT_ctrl.bsf
HALTctrl.bsf		HALTctrl.bsf
JMP copy.v		JMP copy.v
JMP.bsf		JMP.bsf
JMP.v		JMP.v
JMP.v.bak		JMP.v.bak
LAM.bsf		LAM.bsf
LAM.v		LAM.v
LAM.v.bak		LAM.v.bak
Prog_mem.bsf		Prog_mem.bsf
Prog_mem.qip		Prog_mem.qip
Prog_mem.v		Prog_mem.v
Prog_mem_syn.v		Prog_mem_syn.v
TP2.bdf		TP2.bdf
TP2.qpf		TP2.qpf
TP2.qsf		TP2.qsf
TP2.qws		TP2.qws
Test1.vwf		Test1.vwf
alu.bsf		alu.bsf
alu.v		alu.v
alu.v.bak		alu.v.bak
decoder.bsf		decoder.bsf
decoder.v		decoder.v
decoder.v.bak		decoder.v.bak
ifu.bsf		ifu.bsf
ifu.v		ifu.v
ifu.v.bak		ifu.v.bak
latch32.bsf		latch32.bsf
latch32.v		latch32.v
latch32.v.bak		latch32.v.bak
latch5.bsf		latch5.bsf
latch5.v		latch5.v
latch5.v.bak		latch5.v.bak
latchAluIn.bsf		latchAluIn.bsf
latchAluIn.v		latchAluIn.v
latchAluIn.v.bak		latchAluIn.v.bak
latchDec.bsf		latchDec.bsf
latchDec.v		latchDec.v
latchDec.v.bak		latchDec.v.bak
prog_mem.mif		prog_mem.mif
ram.bsf		ram.bsf
ram.qip		ram.qip
ram.v		ram.v
ramTest.vwf		ramTest.vwf
reg_bank.bsf		reg_bank.bsf
reg_bank.v		reg_bank.v
reg_bank.v.bak		reg_bank.v.bak
testbench.txt		testbench.txt