🚀 My_CPU

📖 Introduction

This project implements a Custom CPU Architecture using Logisim Evolution. The design includes an Arithmetic Logic Unit (ALU), Registers, Control Unit, and Memory components to execute fundamental operations.

✨ Features

• ✅ ALU Operations → Supports addition, subtraction, AND, OR, and other basic arithmetic and logical operations. The ALU performs these operations based on the input instructions.
• ✅ Register File → Stores temporary data values that the CPU needs for immediate operations, helping improve processing efficiency and speed.
• ✅ Control Unit → Decodes the instruction and controls the execution of the CPU, coordinating how data flows between components such as ALU, memory, and registers.
• ✅ Clock-Driven Execution → Uses clock pulses to execute operations step-by-step, allowing for synchronization and controlling the flow of instructions in a sequential manner.
• ✅ RAM & ROM Integration → Integrates memory for data storage (RAM) and instruction storage (ROM), enabling the CPU to access data and execute instructions effectively.

📂 File Structure

/CPU_Design
│── 2107086_ALU.circ         # Arithmetic Logic Unit (ALU)
│── 2107086_CPU.circ         # CPU core logic
│── 2107086_alu2.circ        # Alternative ALU design
│── 2107086_Project_report.pdf # Documentation of the project
│── Instruction_1.txt        # Instruction file for CPU operations
│── ScreenShot/              # Folder containing simulation screenshots
│   └── Screenshot_1.png     # CPU simulation screenshot
│── .DS_Store                # System file (macOS specific)

🚀 How to Run the Project

🔹 Steps to Open in Logisim Evolution

1. Download and Install Logisim Evolution → Logisim Evolution
2. Open Logisim Evolution.
3. Click "File → Open" and select 2107086_CPU.circ.
4. Use "Simulate → Tick Once" to execute step-by-step.
5. Observe the registers, ALU, and memory changes during execution.

🔍 Debugging & Common Issues

🔹 Red Wire Errors (Floating Inputs)

• Ensure all inputs have defined values (use constants if needed).
• Check the Control Unit signals for proper instruction execution.

🔹 Clock Not Working

• Ensure the clock is connected to sequential components.
• Use "Tick Frequency → Slow" to debug step-by-step execution.

🔹 ALU Incorrect Outputs

• Check if the MUX selects the correct ALU operation.
• Verify that input values match expected results.

🛠 Future Improvements

• 🚀 Add pipeline stages for faster execution.
• 🚀 Implement interrupt handling for advanced functionality.
• 🚀 Improve instruction set support to handle more complex operations.

📜 License

This project is open-source. Feel free to use, modify, and contribute!

💡 Conclusion

This project demonstrates CPU architecture design in Logisim, focusing on the ALU, registers, memory, and control unit. It provides a foundation for learning computer organization and digital logic.