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[Fix] Combination Loop Error in ModelSim #21

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[Fix] Combination Loop Error in ModelSim #21

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fe339f4
creating branch to fix the combinational loop error in modelsim
petermurphyiv Mar 14, 2024
b900eeb
Cleaning up changes to fix DMA Loop Error in ModelSim
petermurphyiv Mar 14, 2024
5bbb06b
Cleaning up whitespaces
petermurphyiv Mar 14, 2024
aaace6d
Cleaning up whitespaces. Reverting unecessary change
petermurphyiv Mar 14, 2024
fa0f9d0
Cleaning up whitespaces. Reverting unecessary change
petermurphyiv Mar 14, 2024
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16 changes: 8 additions & 8 deletions tutorial/afu_types/01_pim_ifc/dma/hw/rtl/dma_write_engine.sv
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Original file line number Diff line number Diff line change
Expand Up @@ -100,13 +100,13 @@ module dma_write_engine #(
else next = IDLE;
end

state[ADDR_SETUP_BIT]:
if (!need_more_wlast) next = WAIT_FOR_WR_RSP;
else next = SEND_WR_REQ;

state[ADDR_SETUP_BIT]:
if (!need_more_wlast) next = WAIT_FOR_WR_RSP;
else next = SEND_WR_REQ;
state[SEND_WR_REQ_BIT]:
if (dest_mem.awvalid & dest_mem.awready) next = FIFO_EMPTY;
else next = SEND_WR_REQ;
if (dest_mem.awvalid & dest_mem.awready) next = FIFO_EMPTY;
else next = SEND_WR_REQ;

state[FIFO_EMPTY_NOT_READY_BIT]:
if (packet_complete & (!need_more_wlast)) next = WAIT_FOR_WR_RSP;
Expand Down Expand Up @@ -287,8 +287,8 @@ module dma_write_engine #(
state[NOT_READY_BIT]:begin end

state[RD_FIFO_WR_DEST_BIT]: begin
rd_fifo_if.rd_en = dest_mem.wready & rd_fifo_if.not_empty & (!next[ADDR_SETUP_BIT]);
dest_mem_wvalid = dest_mem.wready & rd_fifo_if.not_empty & (!next[ADDR_SETUP_BIT]);
rd_fifo_if.rd_en = dest_mem.wready & rd_fifo_if.not_empty & !(wlast_valid & need_more_wlast);
dest_mem_wvalid = dest_mem.wready & rd_fifo_if.not_empty & !(wlast_valid & need_more_wlast);
end

state[WAIT_FOR_WR_RSP_BIT]: begin
Expand Down