v1.0.1

AMBA/AXI/v4/AXI4.vhdl

@@ -85,8 +85,8 @@ package Axi4 is
 
 	type Axi4_ReadData_Interface is record
 		-- Handshake signals
-		Valid   : std_ulogic;
-		Ready   : std_ulogic;
+		Valid     : std_ulogic;
+		Ready     : std_ulogic;
 
 		-- Payload signals
 		ID        : ID_Type;

AMBA/AXI/v4/AXI4_Generic.vhdl

@@ -32,11 +32,12 @@ package Axi4_Generic is
 	generic (
 		constant ADDRESS_BITS : positive;
 		constant DATA_BITS    : positive;
-		constant STROBE_BITS  : positive := DATA_BITS / 8;
 		constant ID_BITS      : positive;
 		constant USER_BITS    : positive
 	);
 
+	constant STROBE_BITS  : positive := DATA_BITS / 8;
+
 	subtype Axi4_Address_SizedInterface is Axi4_Address_Interface(
 		ID(ID_BITS - 1 downto 0),
 		Address(ADDRESS_BITS - 1 downto 0),
@@ -86,7 +87,7 @@ package Axi4_Generic is
 			User(USER_BITS - 1 downto 0)
 		)
 	);
-	
+
 	subtype Axi4_SizedInterface_Vector is Axi4_Interface_Vector(open)(
 		WriteAddress(
 			ID(ID_BITS - 1 downto 0),

build.pro

@@ -0,0 +1,54 @@
+# ==================================================================================================================== #
+# Copyright 2016-2025 Open Source VHDL Group                                                                           #
+#                                                                                                                      #
+# Licensed under the Apache License, Version 2.0 (the "License");                                                      #
+# you may not use this file except in compliance with the License.                                                     #
+# You may obtain a copy of the License at                                                                              #
+#                                                                                                                      #
+#    http://www.apache.org/licenses/LICENSE-2.0                                                                        #
+#                                                                                                                      #
+# Unless required by applicable law or agreed to in writing, software                                                  #
+# distributed under the License is distributed on an "AS IS" BASIS,                                                    #
+# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.                                             #
+# See the License for the specific language governing permissions and                                                  #
+# limitations under the License.                                                                                       #
+# ==================================================================================================================== #
+# VHDLRevision: VHDL-2019
+# VHDLLibrary:  Interfaces
+
+library Interfaces
+
+# Common definitions
+analyze IO/Common.vhdl
+
+# Internal bus structures
+analyze AMBA/AXI/v4/AXI4Common.vhdl
+analyze AMBA/AXI/v4/AXI4.vhdl
+analyze AMBA/AXI/v4/AXI4_Generic.vhdl
+
+analyze AMBA/AXI/v4/AXI4Lite.vhdl
+analyze AMBA/AXI/v4/AXI4Lite_Generic.vhdl
+analyze AMBA/AXI/v4/AXI4Lite.presized.vhdl
+
+analyze AMBA/AXI/v4/AXI4Stream.vhdl
+analyze AMBA/AXI/v4/AXI4Stream_Generic.vhdl
+
+# Low-speed interfaces
+analyze IO/I2C.vhdl
+analyze IO/SPI.vhdl
+analyze IO/I2S.vhdl
+analyze IO/JTAG.vhdl
+analyze IO/UART.vhdl
+
+# Ethernet
+analyze IO/Ethernet.vhdl
+analyze IO/Cages.vhdl
+
+# Video interfaces
+analyze Video/VGA.vhdl
+analyze MIPI/C-PHY.vhdl
+analyze MIPI/D-PHY.vhdl
+analyze MIPI/M-PHY.vhdl
+
+# Miscellaneous interfaces
+analyze PoC/CSE.vhdl