This repository presents the code of the implementation of an embedded system module to allow the reconfiguration of an FPGA integrating the payload of a satellite. This design applies Warm Standby Spare redundancy and AES cryptography algorithm to increase its lifetime and protect the FPGA bitstream. The proposed module and system was prototyped with PIC18F family and Intel Cyclone IV FPGA.
Fig: Block diagram of the proposed prototype system with modules.
- Ground station: source code to simulate the gound station that send the bitstream.
- Communication subsystem: source code to emulate the communication subsytem with CAN protocol.
- Payload subsystem: source code of FPGA reconfiguration subsystem with cryptography, CAN protocol warm standby spare fault tolerant technique.
- Intel Quartus Prime
- Qt Creator
- Microchip MPLAB 8
- CCS Compiler
- Microchip PICDEM CAN-LIN 3
- Microchip MPLAB ICD 3
- Kit CoreEP4CE6
- Optional - Logic Converter TXS0108E
If you use this code in your research, we would appreciate a citation to the original paper and final course assignment:
@inproceedings{viel2017module,
title={A Module for Remote Reconfiguration of FPGAs in Satellites},
author={Viel, Felipe and Zeferino, Cesar Albenes},
booktitle={IBERCHIP workshop},
pages={50--53},
year={2017}
}
@MASTERSTHESIS {viel2016module,
author = "Felipe Viel",
title = "Desenvolvimento de módulo de reconfiguração remota de FPGA para ambiente espacial",
school = "University of Vale do Itajaí",
year = "2016",
type = "Bachelor's Thesis",
address = "Itajaí, SC, Brazil",
month = "dec",
crossref = "https://siaibib01.univali.br/pdf/Felipe%20Viel%202017.pdf"
}
Software base used and modified to PIC18F microcontroller is from SRunner EPCS software driver by Intel FPGA.
Copyright (c) 2023 Felipe Viel. Released under the MIT License. See LICENSE for details.