Add demo usage code to Verilog output

[WorldofKerry]

Is your feature request related to a problem? Please describe.
Actually using the generated Verilog module is quite verbose.

Describe the solution you'd like
In the generated Verilog code, add a comment that shows a usage example. E.g.

  wire [31:0] f0_output_0;
  wire f0_valid;
  wire f0_done;
  reg f0_start;
  reg f0_ready;
  fib f0(
    .n(32'd100),
    .__output_0(f0_output_0),

    .__start(f0_start),
    .__ready(f0_ready),

    .__valid(f0_valid),
    .__done(f0_done),

    .__clock(clk),
    .__reset(rst),
  );

Describe alternatives you've considered
No so far.

Additional context
Based on usage example from
https://github.com/WorldofKerry/quartus-hls/blob/40778512e25ffcedbc37ebcdea99e0f708d53777/verilog_src/lab3_top.v#L12-L41