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Use Circt for backend codegen

Status: Open.

#84 In WorldofKerry/ToHDL;

· WorldofKerry opened on Apr 17, 2025

Have a crate with pure python source code

Status: Open.

#83 In WorldofKerry/ToHDL;

· WorldofKerry opened on Apr 17, 2025

On error, save current IR and the error message

Status: Open.

#82 In WorldofKerry/ToHDL;

· WorldofKerry opened on Apr 17, 2025

Python's shift left is arithmetic, but Verilog's left shift is bitwise

Status: Open.

#68 In WorldofKerry/ToHDL;

· WorldofKerry opened on Apr 8, 2024

<code>if</code> without <code>else</code> is parsed incorrectly

Status: Open.

#66 In WorldofKerry/ToHDL;

· WorldofKerry opened on Apr 8, 2024

Enable unpack tuple syntax in function calls

Status: Open.

#65 In WorldofKerry/ToHDL;

· WorldofKerry opened on Apr 8, 2024

Add demo usage code to Verilog output

Status: Open.

#63 In WorldofKerry/ToHDL;

· WorldofKerry opened on Apr 8, 2024

Add bitwise negate support

Status: Open.

#62 In WorldofKerry/ToHDL;

· WorldofKerry opened on Apr 8, 2024

Design wrapper around int types to figure out min bit width

Status: Open.

#55 In WorldofKerry/ToHDL;

· WorldofKerry opened on Apr 1, 2024

Create a templated new pass trait creator

Status: Open.

#24 In WorldofKerry/ToHDL;

· WorldofKerry opened on Dec 4, 2023

Better optimizer with verilog codegen

Status: Open.

#23 In WorldofKerry/ToHDL;

· WorldofKerry opened on Dec 2, 2023

Improve pass manager design

Status: Open.

#19 In WorldofKerry/ToHDL;

· WorldofKerry opened on Nov 29, 2023