Python's shift left is arithmetic, but Verilog's left shift is bitwise

[WorldofKerry]

Describe the bug
Python's shift left is arithmetic, but Verilog's left shift is bitwise

To Reproduce
Try to do a left shift with a "negative" number, e.g.
c = a << b is translated to a shift left in Verilog. This is not what Python does.
A workaround is doing a bit mask with c = (a << b) & mask, (where mask it the largest expected value) on the Python side to get the same behaviour on the Verilog side.

Expected behavior
A arithmetic shift left should happen in Verilog.