I'm an aspiring hardware engineer passionate about bridging the gap between hardware and software. I love working at the intersection of digital logic, embedded systems, and modern programming.

🎓 Undergraduate Student | Electrical & Electronics Engineering (EEE) | BITS Pilani
📊 Current CGPA: 8.5 / 10

• 🛠 Skills:
  • Languages: Python, C, C++, JavaScript
  • Hardware Description: Verilog, SystemVerilog, TL Verilog
• 💡 Passion: Building efficient, robust systems by integrating hardware and software solutions.
• 🧑‍💻 Project Highlight:
  • 32-bit Pipelined RISC-V Processor
    Designed and implemented a 32-bit 6-staged pipelined RISC-V processor (IF → ID → RF → EX → MEM → WB) using TL-Verilog on the Makerchip simulator.
  • AHB-to-APB Bridge (Verilog) Implemented an AMBA AHB to APB bridge in Verilog for interfacing high-performance AHB peripherals with low-speed APB devices.

• Yosys – Worked with open-source synthesis tool for digital hardware designs (Verilog/SystemVerilog).
• NPR – Used for placement and routing in FPGA flows.
• Project IceStorm – Explored bitstream generation and FPGA programming for Lattice iCE40 devices.
• Flow Integration – Hands-on with the open-source FPGA toolchain to design, synthesize, and map hardware designs onto FPGAs.

Feel free to check out my repositories to see what I'm working on, and connect if you share similar interests in hardware engineering and embedded systems!

“Passionate about bridging hardware and software.”