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write_addr_reg unused debug #4

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write_addr_reg unused debug #4

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4 changes: 2 additions & 2 deletions rtl/cam_bram.v
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Original file line number Diff line number Diff line change
Expand Up @@ -216,7 +216,7 @@ always @* begin
end
STATE_DELETE_2: begin
// clear bit and write back
clear_bit = 1'b1 << write_addr;
clear_bit = 1'b1 << write_addr_reg;
wr_en = 1'b1;
if (write_delete_reg) begin
state_next = STATE_IDLE;
Expand All @@ -231,7 +231,7 @@ always @* begin
end
STATE_WRITE_2: begin
// set bit and write back
set_bit = 1'b1 << write_addr;
set_bit = 1'b1 << write_addr_reg;
wr_en = 1'b1;
state_next = STATE_IDLE;
end
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4 changes: 2 additions & 2 deletions rtl/cam_srl.v
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Original file line number Diff line number Diff line change
Expand Up @@ -177,7 +177,7 @@ always @* begin
end
STATE_WRITE: begin
// write entry
shift_en = 1'b1 << write_addr;
shift_en = 1'b1 << write_addr_reg;

for (i = 0; i < SLICE_COUNT; i = i + 1) begin
shift_data[i] = count_reg == write_data_padded_reg[SLICE_WIDTH * i +: SLICE_WIDTH];
Expand All @@ -192,7 +192,7 @@ always @* begin
end
STATE_DELETE: begin
// delete entry
shift_en = 1'b1 << write_addr;
shift_en = 1'b1 << write_addr_reg;
shift_data = {SLICE_COUNT{1'b0}};

if (count_reg == 0) begin
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