Mio fpga #91
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Mio fpga #91
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Make sure neither synthesis or simulation can go through with an empty block. Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Master AXI interface not connected. Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Vivado complains about: "ambiguous clock in event control" in the always block. Signed-off-by: Ola Jeppsson <ola@adapteva.com>
TODO: - Remap s_wr/s_rd addresses to 0x3e0XXXXX - Test Signed-off-by: Ola Jeppsson <ola@adapteva.com>
TODO: - Map MIO TX/RX pins to physical GPIO pins instead of just doing loopback in Verilog. Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Statically remap upper 12 bits of AXI slave address to REMAPID on outgoing access. Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
... otherwise Vivado will lock IPs in the same directory. Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Needed by MIO. Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Clear sticky bits status bits on reset, and allow clearing them by writing zeroes to the status register. Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Add MUX for mio/reg packet signals. Signed-off-by: Ola Jeppsson <ola@adapteva.com>
ctrlmode was undefined. Assuming config_reg[15] is reserved. Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Disable m_rd, m_rr signals for now. Only reading to register works. - Writing ARM -> AXI slave -> mio_in -> mio_tx -> mio_rx -> mio_out -> AXI master -> DRAM works (really basic testing). Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Read path from MIO still doesn't work (it times out) s_rd -> mio_in -> mio_tx -> mio_rx -> mio_out -> m_rd ... m_rr -> mio_in -> mio_tx -> mio_rx -> mio_out -> s_rr Signed-off-by: Ola Jeppsson <ola@adapteva.com>
Signed-off-by: Ola Jeppsson <ola@adapteva.com>
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still not stable,
lack of constraints might be the reason