WIP: ISLA-derived instruction specs

cranelift/codegen/build.rs

@@ -187,7 +187,8 @@ fn get_isle_compilations(
         make_isle_source_path_relative(&cur_dir, crate_dir.join("src").join("prelude_opt.isle"));
     let prelude_lower_isle =
         make_isle_source_path_relative(&cur_dir, crate_dir.join("src").join("prelude_lower.isle"));
-    let inst_specs = make_isle_source_path_relative(&cur_dir, crate_dir.join("src").join("inst_specs.isle"));
+    let inst_specs =
+        make_isle_source_path_relative(&cur_dir, crate_dir.join("src").join("inst_specs.isle"));
 
     // Directory for mid-end optimizations.
     let src_opts = make_isle_source_path_relative(&cur_dir, crate_dir.join("src").join("opts"));
@@ -253,6 +254,7 @@ fn get_isle_compilations(
                     prelude_lower_isle.clone(),
                     src_isa_aarch64.join("inst.isle"),
                     src_isa_aarch64.join("inst_neon.isle"),
+                    src_isa_aarch64.join("inst_specs.isle"),
                     inst_specs.clone(),
                     src_isa_aarch64.join("lower.isle"),
                     src_isa_aarch64.join("lower_dynamic_neon.isle"),

cranelift/codegen/src/isa/aarch64/inst.isle

@@ -2018,23 +2018,32 @@
 (spec (alu_rrr op t a b)
     (provide
       (= result (switch op
+              ((ALUOp.Add)
+                (if (<= t 32)
+                    (zero_ext 64 (bvadd (extract 31 0 a) (extract 31 0 b)))
+                    (bvadd a b)))
               ((ALUOp.Lsr)
                 (if (<= t 32)
-                    (conv_to 64 (bvlshr (extract 31 0 a) (bvand (bvsub (int2bv 32 32) #x00000001) (extract 31 0 b))))
+                    (zero_ext 64 (bvlshr (extract 31 0 a) (bvand (bvsub (int2bv 32 32) #x00000001) (extract 31 0 b))))
                     (bvlshr a (bvand (bvsub (int2bv 64 64) #x0000000000000001) b))))
               ((ALUOp.Asr)
                 (if (<= t 32)
-                    (conv_to 64 (bvashr (extract 31 0 a) (bvand (bvsub (int2bv 32 32) #x00000001) (extract 31 0 b))))
+                    (zero_ext 64 (bvashr (extract 31 0 a) (bvand (bvsub (int2bv 32 32) #x00000001) (extract 31 0 b))))
                     (bvashr a (bvand (bvsub (int2bv 64 64) #x0000000000000001) b))))
               ((ALUOp.Lsl)
                 (if (<= t 32)
-                    (conv_to 64 (bvshl (extract 31 0 a) (bvand (bvsub (int2bv 32 32) #x00000001) (extract 31 0 b))))
+                    (zero_ext 64 (bvshl (extract 31 0 a) (bvand (bvsub (int2bv 32 32) #x00000001) (extract 31 0 b))))
                     (bvshl a (bvand (bvsub (int2bv 64 64) #x0000000000000001) b)))))))
     (require
-      (or (= op (ALUOp.Lsr)) (= op (ALUOp.Asr)) (= op (ALUOp.Lsl)))
-      (or (= t 8) (= t 16) (= t 32) (= t 64))))
+      (or (= op (ALUOp.Add)) (= op (ALUOp.Lsr)) (= op (ALUOp.Asr)) (= op (ALUOp.Lsl)))
+      (or (= t 8) (= t 16) (= t 32) (= t 64)))
+      ;(or (= t 32) (= t 64)))
+      )
 (decl alu_rrr (ALUOp Type Reg Reg) Reg)
-(rule (alu_rrr op ty src1 src2)
+(instantiate alu_rrr
+    ((args (bv 8) Int (bv 64) (bv 64)) (ret (bv 64)) (canon (bv 64)))
+)
+(rule alu_rrr_emit (alu_rrr op ty src1 src2)
       (let ((dst WritableReg (temp_writable_reg $I64))
             (_ Unit (emit (MInst.AluRRR op (operand_size ty) dst src1 src2))))
         dst))
@@ -2633,10 +2642,14 @@
   (provide
     (= result
        (if (<= ty 32)
-           (conv_to 64 (bvadd (extract 31 0 a) (extract 31 0 b)))
-           (bvadd a b)))))
+           (zero_ext 64 (bvadd (extract 31 0 a) (extract 31 0 b)))
+           (bvadd a b))))
+  (require (or (= ty 8) (= ty 16) (= ty 32) (= ty 64))))
 (decl add (Type Reg Reg) Reg)
-(rule (add ty x y) (alu_rrr (ALUOp.Add) ty x y))
+(instantiate add
+    ((args Int (bv 64) (bv 64)) (ret (bv 64)) (canon (bv 64)))
+)
+(rule add_alu_rrr (add ty x y) (alu_rrr (ALUOp.Add) ty x y))
 
 (spec (add_imm ty a b)
   (provide

cranelift/codegen/src/isa/aarch64/inst/mod.rs

@@ -15,14 +15,14 @@ use smallvec::{smallvec, SmallVec};
 use std::fmt::Write;
 use std::string::{String, ToString};
 
-pub(crate) mod regs;
-pub(crate) use self::regs::*;
+pub mod regs;
+pub use self::regs::*;
 pub mod imms;
 pub use self::imms::*;
 pub mod args;
 pub use self::args::*;
 pub mod emit;
-pub(crate) use self::emit::*;
+pub use self::emit::*;
 use crate::isa::aarch64::abi::AArch64MachineDeps;
 
 pub(crate) mod unwind;
@@ -1191,7 +1191,11 @@ fn mem_finalize_for_show(mem: &AMode, state: &EmitState) -> (String, AMode) {
 }
 
 impl Inst {
-    fn print_with_state(&self, state: &mut EmitState, allocs: &mut AllocationConsumer) -> String {
+    pub fn print_with_state(
+        &self,
+        state: &mut EmitState,
+        allocs: &mut AllocationConsumer,
+    ) -> String {
         let mut empty_allocs = AllocationConsumer::default();
 
         fn op_name(alu_op: ALUOp) -> &'static str {