[Hardware][RISC-V] Add riscv64 support

[langc23]

The purpose of this PR is to support RISC-V architectures.

[langc23]

@benfred Hello, we hope the PR could merged into the mainline, but need your review and start workflow. Could you please take a time? Thanks.

[langc23]

@benfred @yihong0618 @peytondmurray @zanieb Hello, we hope the PR could merged into the mainline, but need your review and start workflow. Could you please take a time? Thanks.

[langc23]

@benfred @yihong0618 @peytondmurray @zanieb Hello, the purpose of this PR is to support RISC-V architectures. We hope the PR could merged into the mainline, but need your review and start workflow. Could you please take a time? Thanks.

[peytondmurray]

@langc23 Sorry, I'm not a maintainer, just an occasional contributor 🤷

[yihong0618]

@langc23 Sorry, me too...

[yihong0618]

@langc23 just checked its MIT License if you indeed need it, you can fork it and publish to pypi yourself

maybe named py-spy-fork and waiting for the maintainer not so busy time

[langc23]

@langc23 just checked its MIT License if you indeed need it, you can fork it and publish to pypi yourself

maybe named py-spy-fork and waiting for the maintainer not so busy time

Thank you for your suggestions. But I also hope it could merged into the mainline.