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@Darxoon
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@Darxoon Darxoon commented Dec 11, 2025

This is necessary to support some 3DS Thumb functions

@encounter
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encounter commented Dec 15, 2025

Thanks for the PR! The new relocation types need different behavior for extracting the right addend from the instruction data. It seems the 22-bit types (PC22, XPC22) pull 11 bits from the current and next instruction and combines them. Following this, PC11 would probably only extract the 11 bits from the current instruction, and PC8 would extract 8 bits.

@AetiasHax
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Just chiming in with extra information:

R_ARM_THM_PC8 is used for Encoding T1 of the LDR (literal) instruction. It represents the imm8 field which is multiplied by 4, so extracting the addend would look like (ins & 0xff) << 2.

R_ARM_THM_PC11 is used for Encoding T2 of the B instruction. The branch target imm11 is multiplied by 2 and sign-extended, so extracting the addend would be ((ins & 0x7ff) << 1) << 20 >> 20. Make sure to treat ins as a signed integer here so that << 20 >> 20 successfully sign extends the addend.

Both of these relocations exist in just one 16-bit Thumb instruction, as opposed to two Thumb instructions like with R_ARM_THM_PC22 and R_ARM_THM_XPC22.

Hope this helps!

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3 participants