Typo pass

materials/01-Introduction/03-python-background/17-inheriting-from-a-simobject.py

@@ -48,7 +48,7 @@ class L1ICache(L1Cache):
     """Simple L1 instruction cache with default values"""
 
     # Set the size
-    size = "32kB"
+    size = "32KiB"
 
     def __init__(self):
         super().__init__()

materials/02-Using-gem5/01-stdlib/01-02-fs-mode.py

@@ -14,14 +14,14 @@
 
 # Here we set up a MESI Two Level Cache Hierarchy.
 cache_hierarchy = MESITwoLevelCacheHierarchy(
-    l1d_size="16kB",
+    l1d_size="16KiB",
     l1d_assoc=8,
-    l1i_size="16kB",
+    l1i_size="16KiB",
     l1i_assoc=8,
-    l2_size="256kB",
+    l2_size="256KiB",
     l2_assoc=16,
     num_l2_banks=1,
 )
 
 # Set up the system memory.
-memory = SingleChannelDDR3_1600(size="3GB")
+memory = SingleChannelDDR3_1600(size="3GiB")

materials/02-Using-gem5/01-stdlib/02-processor.py

@@ -42,14 +42,14 @@ def __init__(self, width, rob_size, num_int_regs, num_fp_regs):
         pass
 
 
-main_memory = SingleChannelDDR4_2400(size="2GB")
+main_memory = SingleChannelDDR4_2400(size="2GiB")
 
 cache_hierarchy = MESITwoLevelCacheHierarchy(
-    l1d_size="16kB",
+    l1d_size="16KiB",
     l1d_assoc=8,
-    l1i_size="16kB",
+    l1i_size="16KiB",
     l1i_assoc=8,
-    l2_size="256kB",
+    l2_size="256KiB",
     l2_assoc=16,
     num_l2_banks=1,
 )

materials/02-Using-gem5/01-stdlib/completed/01-02-fs-mode.py

@@ -14,17 +14,17 @@
 
 # Here we setup a MESI Two Level Cache Hierarchy.
 cache_hierarchy = MESITwoLevelCacheHierarchy(
-    l1d_size="16kB",
+    l1d_size="16KiB",
     l1d_assoc=8,
-    l1i_size="16kB",
+    l1i_size="16KiB",
     l1i_assoc=8,
-    l2_size="256kB",
+    l2_size="256KiB",
     l2_assoc=16,
     num_l2_banks=1,
 )
 
 # Setup the system memory.
-memory = SingleChannelDDR3_1600(size="3GB")
+memory = SingleChannelDDR3_1600(size="3GiB")
 
 # Here we setup the processor. This is a special switchable processor in which
 # a starting core type and a switch core type must be specified. Once a

materials/02-Using-gem5/01-stdlib/completed/01-components.py

@@ -21,11 +21,11 @@
 
 # Here we setup a MESI Two Level Cache Hierarchy.
 cache_hierarchy = MESITwoLevelCacheHierarchy(
-    l1d_size="16kB",
+    l1d_size="16KiB",
     l1d_assoc=8,
-    l1i_size="16kB",
+    l1i_size="16KiB",
     l1i_assoc=8,
-    l2_size="256kB",
+    l2_size="256KiB",
     l2_assoc=16,
     num_l2_banks=1,
 )

materials/02-Using-gem5/01-stdlib/completed/02-processor.py

@@ -58,14 +58,14 @@ def __init__(self, width, rob_size, num_int_regs, num_fp_regs):
         super().__init__(cores)
 
 
-main_memory = SingleChannelDDR4_2400(size="2GB")
+main_memory = SingleChannelDDR4_2400(size="2GiB")
 
 cache_hierarchy = MESITwoLevelCacheHierarchy(
-    l1d_size="16kB",
+    l1d_size="16KiB",
     l1d_assoc=8,
-    l1i_size="16kB",
+    l1i_size="16KiB",
     l1i_assoc=8,
-    l2_size="256kB",
+    l2_size="256KiB",
     l2_assoc=16,
     num_l2_banks=1,
 )

materials/02-Using-gem5/02-gem5-resources/01-hello-example.py

@@ -23,7 +23,7 @@
 
 from gem5.simulate.simulator import Simulator
 
-memory = SingleChannelDDR4_2400(size="2GB")
+memory = SingleChannelDDR4_2400(size="2GiB")
 
 caches = PrivateL1SharedL2CacheHierarchy(
     l1d_size="32KiB",

materials/02-Using-gem5/02-gem5-resources/02-suite-workload-example.py

@@ -28,7 +28,7 @@
 
 from gem5.simulate.simulator import Simulator
 
-memory = SingleChannelDDR4_2400(size="2GB")
+memory = SingleChannelDDR4_2400(size="2GiB")
 
 caches = PrivateL1SharedL2CacheHierarchy(
     l1d_size="32KiB",

materials/02-Using-gem5/02-gem5-resources/03-run-local-resource-local-path.py

@@ -16,12 +16,12 @@
 cache_hierarchy = NoCache()
 
 # We use a single channel DDR3_1600 memory system
-memory = SingleChannelDDR3_1600(size="32MB")
+memory = SingleChannelDDR3_1600(size="32MiB")
 
 # We use a simple Timing processor with one core.
 processor = SimpleProcessor(cpu_type=CPUTypes.ATOMIC, isa=ISA.X86, num_cores=1)
 
-# The gem5 library simble board which can be used to run simple SE-mode
+# The gem5 library simple board which can be used to run simple SE-mode
 # simulations.
 board = SimpleBoard(
     clk_freq="3GHz",

materials/02-Using-gem5/02-gem5-resources/04-run-local-resource-json.py

@@ -16,12 +16,12 @@
 cache_hierarchy = NoCache()
 
 # We use a single channel DDR3_1600 memory system
-memory = SingleChannelDDR3_1600(size="32MB")
+memory = SingleChannelDDR3_1600(size="32MiB")
 
 # We use a simple Timing processor with one core.
 processor = SimpleProcessor(cpu_type=CPUTypes.ATOMIC, isa=ISA.X86, num_cores=1)
 
-# The gem5 library simble board which can be used to run simple SE-mode
+# The gem5 library simple board which can be used to run simple SE-mode
 # simulations.
 board = SimpleBoard(
     clk_freq="3GHz",

materials/02-Using-gem5/02-gem5-resources/complete/01-hello-example.py

@@ -22,7 +22,7 @@
 
 from gem5.simulate.simulator import Simulator
 
-memory = SingleChannelDDR4_2400(size="2GB")
+memory = SingleChannelDDR4_2400(size="2GiB")
 
 caches = PrivateL1SharedL2CacheHierarchy(
     l1d_size="32KiB",

materials/02-Using-gem5/02-gem5-resources/complete/02-suite-workload-example.py

@@ -28,7 +28,7 @@
 
 from gem5.simulate.simulator import Simulator
 
-memory = SingleChannelDDR4_2400(size="2GB")
+memory = SingleChannelDDR4_2400(size="2GiB")
 
 caches = PrivateL1SharedL2CacheHierarchy(
     l1d_size="32KiB",

materials/02-Using-gem5/02-gem5-resources/complete/03-run-local-resource-local-path.py

@@ -16,12 +16,12 @@
 cache_hierarchy = NoCache()
 
 # We use a single channel DDR3_1600 memory system
-memory = SingleChannelDDR3_1600(size="32MB")
+memory = SingleChannelDDR3_1600(size="32MiB")
 
 # We use a simple Timing processor with one core.
 processor = SimpleProcessor(cpu_type=CPUTypes.ATOMIC, isa=ISA.X86, num_cores=1)
 
-# The gem5 library simble board which can be used to run simple SE-mode
+# The gem5 library siple board which can be used to run simple SE-mode
 # simulations.
 board = SimpleBoard(
     clk_freq="3GHz",

materials/02-Using-gem5/02-gem5-resources/complete/04-run-local-resource-json.py

@@ -16,12 +16,12 @@
 cache_hierarchy = NoCache()
 
 # We use a single channel DDR3_1600 memory system
-memory = SingleChannelDDR3_1600(size="32MB")
+memory = SingleChannelDDR3_1600(size="32MiB")
 
 # We use a simple Timing processor with one core.
 processor = SimpleProcessor(cpu_type=CPUTypes.ATOMIC, isa=ISA.X86, num_cores=1)
 
-# The gem5 library simble board which can be used to run simple SE-mode
+# The gem5 library simple board which can be used to run simple SE-mode
 # simulations.
 board = SimpleBoard(
     clk_freq="3GHz",

materials/02-Using-gem5/03-running-in-gem5/00-SE-hello-world/00-SE-hello-world.py

@@ -52,11 +52,11 @@
 
 
 cache_hierarchy = PrivateL1CacheHierarchy(
-    l1d_size="64kB",
-    l1i_size="64kB",
+    l1d_size="64KiB",
+    l1i_size="64KiB",
 )
 
-memory = SingleChannelDDR4_2400("1GB")
+memory = SingleChannelDDR4_2400("1GiB")
 
 processor = SimpleProcessor(
     cpu_type = CPUTypes.TIMING,

materials/02-Using-gem5/03-running-in-gem5/03-run-x86-SE/03-run-x86-SE.py

@@ -52,11 +52,11 @@
 
 
 cache_hierarchy = PrivateL1CacheHierarchy(
-    l1d_size="64kB",
-    l1i_size="64kB",
+    l1d_size="64KiB",
+    l1i_size="64KiB",
 )
 
-memory = SingleChannelDDR4_2400("1GB")
+memory = SingleChannelDDR4_2400("1GiB")
 
 processor = SimpleProcessor(
     cpu_type = CPUTypes.TIMING,

materials/02-Using-gem5/03-running-in-gem5/03-run-x86-SE/complete/03-run-x86-SE.py

@@ -52,11 +52,11 @@
 
 
 cache_hierarchy = PrivateL1CacheHierarchy(
-    l1d_size="64kB",
-    l1i_size="64kB",
+    l1d_size="64KiB",
+    l1i_size="64KiB",
 )
 
-memory = SingleChannelDDR4_2400("1GB")
+memory = SingleChannelDDR4_2400("1GiB")
 
 processor = SimpleProcessor(
     cpu_type = CPUTypes.TIMING,

materials/02-Using-gem5/03-running-in-gem5/05-run-arm-SE/05-run-arm-SE.py

@@ -77,11 +77,11 @@
 
 
 cache_hierarchy = PrivateL1CacheHierarchy(
-    l1d_size="64kB",
-    l1i_size="64kB",
+    l1d_size="64KiB",
+    l1i_size="64KiB",
 )
 
-memory = SingleChannelDDR4_2400("1GB")
+memory = SingleChannelDDR4_2400("1GiB")
 
 processor = SimpleProcessor(
     cpu_type = CPUTypes.TIMING,

materials/02-Using-gem5/03-running-in-gem5/05-run-arm-SE/complete/05-run-arm-SE.py

@@ -77,11 +77,11 @@
 
 
 cache_hierarchy = PrivateL1CacheHierarchy(
-    l1d_size="64kB",
-    l1i_size="64kB",
+    l1d_size="64KiB",
+    l1i_size="64KiB",
 )
 
-memory = SingleChannelDDR4_2400("1GB")
+memory = SingleChannelDDR4_2400("1GiB")
 
 processor = SimpleProcessor(
     cpu_type = CPUTypes.TIMING,

materials/02-Using-gem5/03-running-in-gem5/06-traffic-gen/completed/step-1-linear-gen/simple-traffic-generators.py

@@ -43,7 +43,7 @@
 
 memory = SingleChannelDDR3_1600()
 
-generator = LinearGenerator(num_cores=1, rate="1GB/s")
+generator = LinearGenerator(num_cores=1, rate="1GiB/s")
 
 motherboard = TestBoard(
     clk_freq="3GHz",

materials/02-Using-gem5/03-running-in-gem5/06-traffic-gen/completed/step-2-hybrid-gen/components/hybrid_generator.py

@@ -46,7 +46,7 @@ def __init__(
         self,
         num_cores: int = 2,
         duration: str = "1ms",
-        rate: str = "1GB/s",
+        rate: str = "1GiB/s",
         block_size: int = 8,
         min_addr: int = 0,
         max_addr: int = 131072,

materials/02-Using-gem5/03-running-in-gem5/06-traffic-gen/components/hybrid_generator.py

@@ -46,7 +46,7 @@ def __init__(
         self,
         num_cores: int = 2,
         duration: str = "1ms",
-        rate: str = "1GB/s",
+        rate: str = "1GiB/s",
         block_size: int = 8,
         min_addr: int = 0,
         max_addr: int = 131072,

materials/02-Using-gem5/05-cache-hierarchies/completed/three_level.py

@@ -147,7 +147,7 @@ def _setup_io_cache(self, board: AbstractBoard) -> None:
             data_latency=50,
             response_latency=50,
             mshrs=20,
-            size="1kB",
+            size="1KiB",
             tgts_per_mshr=12,
             addr_ranges=board.mem_ranges,
         )

materials/02-Using-gem5/05-cache-hierarchies/test-cache.py

@@ -25,7 +25,7 @@
         l3_size="2MiB",
         l3_assoc=32,
     ),
-    memory=DualChannelDDR4_2400(size="2GB"),
+    memory=DualChannelDDR4_2400(size="2GiB"),
     clk_freq="3GHz",
 )
 

materials/02-Using-gem5/05-cache-hierarchies/three_level.py

@@ -96,7 +96,7 @@ def _setup_io_cache(self, board: AbstractBoard) -> None:
             data_latency=50,
             response_latency=50,
             mshrs=20,
-            size="1kB",
+            size="1KiB",
             tgts_per_mshr=12,
             addr_ranges=board.mem_ranges,
         )

materials/02-Using-gem5/06-memory/blank_memory.py

@@ -43,7 +43,7 @@ def createLinearTraffic(tgen):
 
 # Set up the system
 system.mem_mode = 'timing'
-system.mem_ranges = [AddrRange('512MB')] # Create an address range
+system.mem_ranges = [AddrRange('512MiB')] # Create an address range
 addr_range = system.mem_ranges[0]
 
 system.tgen = PyTrafficGen() # Create a traffic generator

materials/02-Using-gem5/06-memory/comm_monitor.py

@@ -40,13 +40,13 @@ def createLinearTraffic(tgen):
 
 # Set up the system
 system.mem_mode = 'timing'
-system.mem_ranges = [AddrRange('512MB')] # Create an address range
+system.mem_ranges = [AddrRange('512MiB')] # Create an address range
 addr_range = system.mem_ranges[0]
 
 system.tgen = PyTrafficGen() # Create a traffic generator
 
 system.l1cache = SimpleCache()
-system.l1cache.size = '32kB'
+system.l1cache.size = '32KiB'
 
 
 system.membus = SystemXBar(width = 64, max_routing_table_size = 16777216)
@@ -59,7 +59,7 @@ def createLinearTraffic(tgen):
 
 # memory interface parameters
 system.mem_ctrl.dram = DDR4_2400_16x4()
-system.mem_ctrl.dram.range = AddrRange('512MB')
+system.mem_ctrl.dram.range = AddrRange('512MiB')
 system.mem_ctrl.dram.read_buffer_size = 32
 system.mem_ctrl.dram.write_buffer_size = 64
 

materials/02-Using-gem5/06-memory/completed/blank_memory.py

@@ -41,7 +41,7 @@ def createLinearTraffic(tgen):
 
 # Set up the system
 system.mem_mode = 'timing'
-system.mem_ranges = [AddrRange('512MB')] # Create an address range
+system.mem_ranges = [AddrRange('512MiB')] # Create an address range
 addr_range = system.mem_ranges[0]
 
 system.tgen = PyTrafficGen() # Create a traffic generator
@@ -58,7 +58,7 @@ def createLinearTraffic(tgen):
 
 # memory interface parameters
 system.mem_ctrl.dram = DDR4_2400_16x4()
-system.mem_ctrl.dram.range = AddrRange('512MB')
+system.mem_ctrl.dram.range = AddrRange('512MiB')
 system.mem_ctrl.dram.read_buffer_size = 32
 system.mem_ctrl.dram.write_buffer_size = 64