MIPI CSI 2 Receiver

To-do List

• Primary format decoding
  • RGB888
  • RGB565
  • YUV422 8-bit
  • RAW8
  • RAW10
• Tests
  • D-PHY
  • CSI-2
  • Decoding
• Error-checking and correction
  • Header ECC
  • Footer Checksum
• N-lane
  • 1 lane
  • 2 lane
  • 3 lane
    • Roadblock: will receive more bytes than the 32-bit buffer
      • Consider long packet with 8 bytes
      • First 3 from header go from corresponding lanes
      • Header byte 4 comes from lane 1, Data byte 1, 2 come from lanes 2 & 3
      • Data byte 3, 4, 5 (!) come from lanes 1, 2, & 3
      • Thus, you are stuck with extra, on the same clock the user gets the buffer
  • 4 lane

Reference Documents

These documents are not hosted here! They are available on Library Genesis and at other locations.

• MIPI CSI-2 Specification
• MIPI D-PHY Specification

Special Thanks

• Gaurav Singh's posts on his IMX219 CSI-2 RX implementation