riscv64: Fix build option and potential SIGBUS error #169
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@pablodelara Hi Pablo, please consider including this PR in release v2.26, it fixes some bugs on riscv64. |
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When the compiler supports vector extensions, the -march option always enables vector by default. This causes illegal instruction errors on RISC-V CPU without vector support. It is sufficient to enable the vector extension in the assembler via `.option arch, +v`. Signed-off-by: Julian Zhu <julian.oerv@isrc.iscas.ac.cn>
…ion for riscv64 Signed-off-by: Julian Zhu <julian.oerv@isrc.iscas.ac.cn>
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LGTM |
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This is now merged, thanks! |
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This PR removes special-case
-marchoption to maintain compatibility with non-vector devices for riscv64. Additionally, it also fixes a potential unaligned memory access and SIGBUS error in the mh_sha256 vector implementation for riscv64.cc @sunyuechi