Fix unpacked dimensions when pulling up array ports

lib/src/references/slice_port_reference.dart

@@ -395,12 +395,21 @@ class SlicePortReference extends PortReference {
   /// logic signal.
   List<int>? get subsetDimensions => _elementWidthAndDimensions.dimensions;
 
+  /// The number of unpacked dimensions in the port subset, if applicable.
+  ///
+  /// Returns the count of unpacked dimensions after applying array indexing
+  /// and slicing operations. `null` if the result is a simple scalar logic
+  /// signal.
+  int? get subsetNumUnpackedDimensions =>
+      _elementWidthAndDimensions.numUnpackedDimensions;
+
   /// Cached calculation of element width and dimensions for the subset.
   ///
   /// This computes the effective width and dimensionality that results from
   /// applying the dimension access and slicing operations to the original port.
   late final _elementWidthAndDimensions = _getElementWidthAndDimensions();
-  ({int elementWidth, List<int>? dimensions}) _getElementWidthAndDimensions() {
+  ({int elementWidth, List<int>? dimensions, int? numUnpackedDimensions})
+      _getElementWidthAndDimensions() {
     var sig = port;
     int? leafIndex;
     if (dimensionAccess != null) {
@@ -418,28 +427,38 @@ class SlicePortReference extends PortReference {
 
     if (leafIndex != null) {
       assert(sig is! LogicArray, 'should not be an array');
-      return (elementWidth: 1, dimensions: null);
+      return (elementWidth: 1, dimensions: null, numUnpackedDimensions: null);
     } else if (hasSlicing) {
       final sliceWidth = sliceUpperIndex! - sliceLowerIndex! + 1;
       if (sig is LogicArray) {
         return (
           elementWidth: sig.elementWidth,
-          dimensions: List.of(sig.dimensions)..[0] = sliceWidth
+          dimensions: List.of(sig.dimensions)..[0] = sliceWidth,
+          numUnpackedDimensions: sig.numUnpackedDimensions
         );
       } else {
         // non-array, normal logic
-        return (elementWidth: sliceWidth, dimensions: null);
+        return (
+          elementWidth: sliceWidth,
+          dimensions: null,
+          numUnpackedDimensions: null
+        );
       }
     } else {
       if (sig is LogicArray) {
         // still an array, no slicing
         return (
           elementWidth: sig.elementWidth,
           dimensions: sig.dimensions,
+          numUnpackedDimensions: sig.numUnpackedDimensions
         );
       } else {
         // non-array, normal logic
-        return (elementWidth: sig.width, dimensions: null);
+        return (
+          elementWidth: sig.width,
+          dimensions: null,
+          numUnpackedDimensions: null
+        );
       }
     }
   }
@@ -453,7 +472,9 @@ class SlicePortReference extends PortReference {
       newModule.createPort(newPortName, direction, width: subsetElementWidth);
     } else {
       newModule.createArrayPort(newPortName, direction,
-          dimensions: subsetDimensions!, elementWidth: subsetElementWidth);
+          dimensions: subsetDimensions!,
+          elementWidth: subsetElementWidth,
+          numUnpackedDimensions: subsetNumUnpackedDimensions!);
     }
 
     return PortReference.fromString(newModule, newPortName);

lib/src/references/standard_port_reference.dart

@@ -86,7 +86,9 @@ class StandardPortReference extends PortReference {
     if (port is LogicArray) {
       final portArr = port as LogicArray;
       newModule.createArrayPort(newPortName, direction,
-          dimensions: portArr.dimensions, elementWidth: portArr.elementWidth);
+          dimensions: portArr.dimensions,
+          elementWidth: portArr.elementWidth,
+          numUnpackedDimensions: portArr.numUnpackedDimensions);
     } else {
       newModule.createPort(newPortName, direction, width: port.width);
     }

test/hierarchy_connection_test.dart

@@ -232,6 +232,52 @@ void main() {
     });
   });
 
+  group('pull up array port with unpacked dimensions', () {
+    test('standard port', () async {
+      final top = BridgeModule('top');
+      final child = BridgeModule('child');
+      final childPort = child.createArrayPort('arrayPort', PortDirection.input,
+          elementWidth: 8, numUnpackedDimensions: 1, dimensions: [4, 2]);
+      top.addSubModule(child);
+
+      final topPort = top.pullUpPort(childPort);
+
+      await top.build();
+
+      expect((topPort.port as LogicArray).numUnpackedDimensions, 1);
+    });
+
+    test('slice port whole dimension', () async {
+      final top = BridgeModule('top');
+      final child = BridgeModule('child')
+        ..createArrayPort('arrayPort', PortDirection.input,
+            elementWidth: 8, numUnpackedDimensions: 2, dimensions: [4, 2]);
+      top.addSubModule(child);
+
+      final slicePort = child.port('arrayPort[2]');
+      final topPort = top.pullUpPort(slicePort);
+
+      await top.build();
+
+      expect((topPort.port as LogicArray).numUnpackedDimensions, 1);
+    });
+
+    test('slice port portion', () async {
+      final top = BridgeModule('top');
+      final child = BridgeModule('child')
+        ..createArrayPort('arrayPort', PortDirection.input,
+            elementWidth: 8, numUnpackedDimensions: 2, dimensions: [4, 2]);
+      top.addSubModule(child);
+
+      final slicePort = child.port('arrayPort[2:1]');
+      final topPort = top.pullUpPort(slicePort);
+
+      await top.build();
+
+      expect((topPort.port as LogicArray).numUnpackedDimensions, 2);
+    });
+  });
+
   test('single bit to single-bit element through hierarchy', () async {
     final mod1 = BridgeModule('mod1')..addOutput('apple');
     final mod2 = BridgeModule('mod2')