Enable and test unconnected ports being left unconnected

lib/src/bridge_module.dart

@@ -65,6 +65,11 @@ class BridgeModule extends Module with SystemVerilog {
       ? DefinitionGenerationType.none
       : DefinitionGenerationType.standard;
 
+  @override
+  // since we have a "normal" `instantiationVerilog` that has module
+  // instantiation ports, we can accept empty port connections
+  bool get acceptsEmptyPortConnections => true;
+
   @override
   String instantiationVerilog(
     String instanceType,

lib/src/references/interface_reference.dart

@@ -555,6 +555,10 @@ extension _ExceptPairInterfaceExtensions on PairInterface {
       commonInOutPorts: _getMatchPortsExcept(PairDirection.commonInOuts,
               exceptPorts: exceptPorts)
           .toList(),
+
+      // since we're not actually cloning, just clone all we can, including
+      // deprecated APIs.
+      // ignore: deprecated_member_use
       modify: modify,
     );
   }

pubspec.yaml

@@ -13,7 +13,7 @@ dependencies:
   collection: ^1.15.0
   logging: ^1.2.0
   meta: ^1.15.0
-  rohd: ^0.6.6
+  rohd: ^0.6.7
 
 dev_dependencies:
   test: ^1.16.0

test/pretty_test.dart

@@ -83,14 +83,28 @@ west  west(.myInput(myInput));'''));
     await top.build();
     final sv = top.generateSynth();
 
-    expect(
-        sv,
-        contains('aggregator(.merged_bits(({'
-            'merged_bits_subset[3],'
-            'merged_bits_subset[2],'
-            'merged_bits_subset[1],'
-            'merged_bits_subset[0]'
-            '})),.clk(clk));'));
+    expect(sv, contains('''
+aggregator  aggregator(.merged_bits(({
+merged_bits_subset[3], /* 3 */
+merged_bits_subset[2], /* 2 */
+merged_bits_subset[1], /* 1 */
+merged_bits_subset[0]  /* 0 */
+})),.clk(clk));
+'''));
     expect(sv, contains('leaf1  leaf1(.out_bit(merged_bits_subset[1]));'));
   });
+
+  test('unconnected ports left unconnected', () async {
+    final top = BridgeModule('top');
+    final modA = top.addSubModule(BridgeModule('modA')
+      ..addInput('in_port', null)
+      ..addOutput('out_port'));
+    top.pullUpPort(modA.port('in_port'));
+
+    await top.build();
+
+    final sv = top.generateSynth();
+
+    expect(sv, contains('modA(.in_port(modA_in_port),.out_port());'));
+  });
 }

test/rb_general_utils_test.dart

@@ -18,8 +18,7 @@ import 'package:rohd_bridge/rohd_bridge.dart';
 import 'package:test/test.dart';
 
 void main() {
-  test('Get Int test', skip: 'Pending https://github.com/intel/rohd/issues/616',
-      () {
+  test('Get Int test', () {
     const binVal = "12'b111010100011";
     const hexVal = "12'hABC";
     const intVal = "12'd3445";