Simple UART for FPGA v1.3

• Added better simulation with automatic checking of transactions.
• Little code cleaning and code optimization.
• Added UART2WB bridge example (access to WB registers via UART).
• Added Parity Error output.

Simple UART for FPGA v1.2

• Added double FF for safe CDC.
• Fixed fake received transaction after FPGA boot without reset.
• Added more precisely clock dividers, dividing with rounding.
• UART loopback example is for CYC1000 board now.

Simple UART for FPGA v1.1

• Added better debouncer.
• Added simulation script and Quartus project file.
• Removed unnecessary resets.
• Signal BUSY replaced by DIN_RDY.
• Many other optimizations and changes.

Simple UART for FPGA v1.0

• Very simple and clean UART controller design.
• Controller was simulated and tested on hardware.
• Configurable parity and baud rate.
• Loopback example.