This project implements a high-speed and area-efficient 8-bit Dadda multiplier enhanced with compressor-based techniques. The design integrates 4-2 and 3-2 compressors into the Dadda multiplier architecture to reduce critical path delay, area, and power consumption. The implementation uses Verilog HDL for structural and behavioral modeling, with simulation and synthesis performed on Xilinx Vivado v 2024.2.
At nanometric scales, imprecise computing models offer efficient digital processing. The project leverages this by decomposing multiplication into parallel units using compressors to reduce the partial product reduction stage. The proposed design minimizes area complexity compared to existing concepts, verified through simulation and synthesis results.
The multiplier operates in three key stages: partial product generation, partial product reduction, and addition. The crucial improvement is made in the reduction stage by using 4-2 and 3-2 compressors, significantly decreasing multiplication delay, power, and area.
- Implementation of an 8-bit Dadda multiplier with compressor-based optimization.
- Use of approximate high-speed 4-2 and 3-2 compressors to enhance performance.
- Reduction in critical path delay and area utilization compared to conventional CSA-based designs.
- Verilog HDL coding with functional simulation and synthesis on Xilinx Vivado.
- Suitable for high-speed, low-power VLSI applications such as image processing and digital signal processing.
A 4x4 bit Dadda Multiplier, using CSA Dadda Tree: 2 – carry save levels, 4 FA, 2HA, 6-bit CPA
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An optimized parallel multiplier reducing the number of addition stages.
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Uses AND gates for partial product generation.
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Partial products are reduced using half adders, full adders, and compressors until two rows remain.
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Final summation is performed by a carry-propagate adder to produce the 16-bit result.
Working of compressor-based Dadda Multiplier
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4-2 Compressor: Redesigned for latency, area, and power optimization using XOR gates and multiplexers.
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3-2 Compressor: Uses multiplexers in place of XOR gates to reduce latency further in the final stage.
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Compressors reduce partial product columns effectively, decreasing computation stages.
- Reduced stages of computation from 5 (CSA-based) to 3 in the compressor-based design.
- Improved timing efficiency and smaller area on chip.
- Enhanced performance parameters, including lower LUT count, occupied slices, delay, and power consumption.
- Behavioral simulation confirms functionality and performance improvements.
- Verilog HDL source code for 8-bit Dadda multiplier.
- Testbench code for simulation.
- Schematic diagrams illustrating the design structure.
The project demonstrates that incorporating high-speed compressors in the partial product reduction stage of a Dadda multiplier significantly improves performance metrics, including speed, power efficiency, and area. This makes it ideal for modern VLSI systems requiring fast and low-power arithmetic computation, with applications in machine learning accelerators and advanced digital signal processing.
- Dwibedi E. Loga Shanmugam, G. Kishor, Mohd Abdul Khadar Jilani - Design and implementation of 4 to 2 compressor for multiplier applications.
- Tianqi Kong and Shuguo Li - Design and Analysis of Approximate 4-2 Compressors for High Accuracy Multipliers, IEEE Transactions on VLSI Systems, 2021.
- Karri Manikantta Reddy et al. - Design and analysis of multiplier using approximate 4-2 compressor, Elsevier AEU Journal, 2019.
- S. Sowmiya, K. Stella, and V.M. Senthilkumar - Design and Analysis of 4-2 Compressor for Arithmetic Application, Asian Journal of Applied Science and Technology, 2017.
Prepared by Indian Institute of Information Technology, Design Manufacturing, Kurnool.