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Merged
jwnrt merged 2 commits into from
Feb 3, 2026
Merged

hw/riscv: Re-enable opentitan machine #321

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bf7dcc6
[ot] hw/riscv: opentitan: use array for single OpenTitan hart
jwnrt Jan 30, 2026
a189987
[ot] configs/devices: riscv32: enable opentitan machine
jwnrt Jan 26, 2026
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8 changes: 4 additions & 4 deletions configs/devices/riscv32-softmmu/default.mak
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Original file line number Diff line number Diff line change
Expand Up @@ -9,7 +9,7 @@
# CONFIG_SIFIVE_E=n
# CONFIG_SIFIVE_U=n
# CONFIG_RISCV_VIRT=n
CONFIG_IBEXDEMO=y
CONFIG_OT_DARJEELING=y
CONFIG_OT_EARLGREY=y
CONFIG_OPENTITAN=n
# CONFIG_OPENTITAN=n
# CONFIG_OT_DARJEELING=n
# CONFIG_OT_EARLGREY=n
# CONFIG_IBEXDEMO=n
3 changes: 3 additions & 0 deletions hw/riscv/Kconfig
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Original file line number Diff line number Diff line change
Expand Up @@ -20,6 +20,7 @@ config IBEX_GPIO

config OT_DARJEELING
bool
default y
select IBEX
select IBEX_CLOCK_SRC
select IBEX_COMMON
Expand Down Expand Up @@ -70,6 +71,7 @@ config OT_DARJEELING

config OT_EARLGREY
bool
default y
select IBEX
select IBEX_CLOCK_SRC
select IBEX_COMMON
Expand Down Expand Up @@ -118,6 +120,7 @@ config OT_EARLGREY

config IBEXDEMO
bool
default y
select IBEX
select IBEX_CLOCK_SRC
select IBEX_COMMON
Expand Down
10 changes: 5 additions & 5 deletions hw/riscv/opentitan.c
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Original file line number Diff line number Diff line change
Expand Up @@ -128,7 +128,7 @@ static void lowrisc_ibex_soc_init(Object *obj)
{
LowRISCIbexSoCState *s = RISCV_IBEX_SOC(obj);

object_initialize_child(obj, "cpu", &s->cpu, TYPE_RISCV_CPU_LOWRISC_IBEX);
object_initialize_child(obj, "cpus", &s->cpus, TYPE_RISCV_HART_ARRAY);

object_initialize_child(obj, "plic", &s->plic, TYPE_SIFIVE_PLIC);

Expand All @@ -152,7 +152,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
MemoryRegion *sys_mem = get_system_memory();
int i;

Object *cpu = OBJECT(&s->cpu);
Object *cpu = OBJECT(&s->cpus.harts[0]);
object_property_set_int(cpu, "resetvec", s->resetvec,
&error_fatal);
object_property_set_bool(cpu, "m", true, &error_fatal);
Expand All @@ -162,7 +162,7 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
object_property_set_bool(cpu, "zbc", true, &error_fatal);
object_property_set_bool(cpu, "zbs", true, &error_fatal);
object_property_set_bool(cpu, "smepmp", true, &error_fatal);
qdev_realize(DEVICE(&s->cpu), NULL, &error_fatal);
qdev_realize(DEVICE(&s->cpus), NULL, &error_fatal);

/* Boot ROM */
memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
Expand Down Expand Up @@ -198,10 +198,10 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base);

for (i = 0; i < ms->smp.cpus; i++) {
CPUState *cpu = qemu_get_cpu(i);
CPUState *cpu_state = qemu_get_cpu(i);

qdev_connect_gpio_out(DEVICE(&s->plic), ms->smp.cpus + i,
qdev_get_gpio_in(DEVICE(cpu), IRQ_M_EXT));
qdev_get_gpio_in(DEVICE(cpu_state), IRQ_M_EXT));
}

/* UART */
Expand Down
4 changes: 2 additions & 2 deletions include/hw/riscv/opentitan.h
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Original file line number Diff line number Diff line change
Expand Up @@ -25,7 +25,7 @@
#include "hw/ssi/ibex_spi_host.h"
#include "hw/boards.h"
#include "qom/object.h"
#include "target/riscv/cpu.h"
#include "include/hw/riscv/riscv_hart.h"

#define TYPE_RISCV_IBEX_SOC "riscv.lowrisc.ibex.soc"
OBJECT_DECLARE_SIMPLE_TYPE(LowRISCIbexSoCState, RISCV_IBEX_SOC)
Expand All @@ -41,7 +41,7 @@ struct LowRISCIbexSoCState {
SysBusDevice parent_obj;

/*< public >*/
RISCVCPU cpu;
RISCVHartArrayState cpus;
SiFivePLICState plic;
IbexUartState uart;
IbexTimerState timer;
Expand Down
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