mathis-s · PhilippvK · Jan 13, 2025
diff --git a/core_descs/ExampleFP32.core_desc b/core_descs/ExampleFP32.core_desc
@@ -0,0 +1,25 @@
+// RUN: pattern-gen %s -O 3 --mattr=+m,+f --riscv-xlen 32 --riscv-flen 32 | FileCheck --check-prefixes=CHECK-RV32,CHECK-RV32-EXTEND -allow-unused-prefixes %s
+// RUN: pattern-gen %s -O 3 --no-extend --mattr=+m,+f --riscv-xlen 32 --riscv-flen 32 | FileCheck --check-prefixes=CHECK-RV32,CHECK-RV32-NOEXTED -allow-unused-prefixes %s
+
+// CHECK-RV32: Pattern for FMAC: (any_fma FPR32:$rd, FPR32:$rs1, FPR32:$rs2)
+FMAC {
+    encoding: 7'b0101000 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011;
+    assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
+    behavior: {
+        F[rd] = llvm_fmuladd_f32(F[rs1], F[rs2], F[rd]);
+    }
+}
+
+// CHECK-RV32-NEXT: Pattern for FMEAN: (fmul (fadd FPR32:$rs1, FPR32:$rs2), (f32 0.500000))
+FMEAN {
+    operands: {
+        unsigned<5> rd [[out]] [[is_freg]];
+        unsigned<5> rs1 [[in]] [[is_freg]];
+        unsigned<5> rs2 [[in]] [[is_freg]];
+    }
+    encoding: 7'b0101000 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011;
+    assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
+    behavior: {
+        F[rd] = llvm_fdiv_fp32(llvm_fadd_fp32(F[rs1], F[rs2]), llvm_uitofp_fp32(2));
+    }
+}
diff --git a/core_descs/ExampleFP32.ll b/core_descs/ExampleFP32.ll
@@ -0,0 +1,35 @@
+; ModuleID = 'mod'
+source_filename = "mod"
+
+define void @implFMAC(ptr %rs2, ptr %rs1, ptr noalias %rd) {
+  %rs1.v = load i32, ptr %rs1, align 4
+  %rs2.v = load i32, ptr %rs2, align 4
+  %rd.v = load i32, ptr %rd, align 4
+  %1 = bitcast i32 %rs1.v to float
+  %2 = bitcast i32 %rs2.v to float
+  %3 = bitcast i32 %rd.v to float
+  %4 = call float @llvm.fmuladd.f32(float %3, float %1, float %2)
+  %5 = bitcast float %4 to i32
+  store i32 %5, ptr %rd, align 4
+  ret void
+}
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare float @llvm.fmuladd.f32(float, float, float) #0
+
+define void @implFMEAN(ptr noalias %rd, ptr %rs1, ptr %rs2) {
+  %rs1.v = load i32, ptr %rs1, align 4
+  %rs2.v = load i32, ptr %rs2, align 4
+  %1 = bitcast i32 %rs1.v to float
+  %2 = bitcast i32 %rs2.v to float
+  %3 = fadd float %1, %2
+  %4 = bitcast float %3 to i32
+  %5 = bitcast i32 %4 to float
+  %6 = fdiv float %5, 2.000000e+00
+  %7 = bitcast float %6 to i32
+  store i32 %7, ptr %rd, align 4
+  ret void
+}
+
+attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+
diff --git a/core_descs/ExampleFP32.td b/core_descs/ExampleFP32.td
@@ -0,0 +1,15 @@
+let Predicates = [HasVendorXCValu] in {
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1, Constraints = "$rd = $rd_wb" in def FMAC_ : RVInst_FMAC<(outs GPR:$rd_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rd)>;
+
+def : Pat<
+	(i32 (any_fma FPR32:$rd, FPR32:$rs1, FPR32:$rs2)),
+	(FMAC_ GPR:$rs2, GPR:$rs1, GPR:$rd)>;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1, Constraints = "" in def FMEAN_ : RVInst_FMEAN<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2)>;
+
+def : Pat<
+	(i32 (fmul (fadd FPR32:$rs1, FPR32:$rs2), (f32 0.500000))),
+	(FMEAN_ GPR:$rs1, GPR:$rs2)>;
+
+}
diff --git a/core_descs/ExampleFP32InstrFormat.td b/core_descs/ExampleFP32InstrFormat.td
@@ -0,0 +1,22 @@
+class RVInst_FMAC<dag outs, dag ins> : RVInst<outs, ins, "fmac", "$rd, $rs1, $rs2", [], InstFormatOther> {
+	bits<5> rs2;
+	bits<5> rs1;
+	bits<5> rd;
+	let Inst{31-25} = 0x0;
+	let Inst{24-20} = rs2{4-0};
+	let Inst{19-15} = rs1{4-0};
+	let Inst{14-12} = 0x0;
+	let Inst{11-7} = rd{4-0};
+	let Inst{6-0} = 0x0;
+}
+class RVInst_FMEAN<dag outs, dag ins> : RVInst<outs, ins, "fmean", "$rd, $rs1, $rs2", [], InstFormatOther> {
+	bits<5> rd;
+	bits<5> rs1;
+	bits<5> rs2;
+	let Inst{31-25} = 0x0;
+	let Inst{24-20} = rs2{4-0};
+	let Inst{19-15} = rs1{4-0};
+	let Inst{14-12} = 0x0;
+	let Inst{11-7} = rd{4-0};
+	let Inst{6-0} = 0x0;
+}
diff --git a/core_descs/ExampleFP64.core_desc b/core_descs/ExampleFP64.core_desc
@@ -0,0 +1,25 @@
+// RUN: pattern-gen %s -O 3 --mattr=+m,+f,+d --riscv-xlen 64 --riscv-flen 64 | FileCheck --check-prefixes=CHECK-RV64,CHECK-RV64-EXTEND -allow-unused-prefixes %s
+// RUN: pattern-gen %s -O 3 --no-extend --mattr=+m,+f,+d --riscv-xlen 64 --riscv-flen 64 | FileCheck --check-prefixes=CHECK-RV64,CHECK-RV64-NOEXTED -allow-unused-prefixes %s
+
+// CHECK-RV64: Pattern for FMAC: (any_fma FPR64:$rd, FPR64:$rs1, FPR64:$rs2)
+FMAC {
+    encoding: 7'b0101000 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011;
+    assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
+    behavior: {
+        F[rd] = llvm_fmuladd_f64(F[rs1], F[rs2], F[rd]);
+    }
+}
+
+// CHECK-RV64-NEXT: Pattern for FMEAN: (fmul (fadd FPR64:$rs1, FPR64:$rs2), (f64 0.500000))
+FMEAN {
+    operands: {
+        unsigned<5> rd [[out]] [[is_freg]];
+        unsigned<5> rs1 [[in]] [[is_freg]];
+        unsigned<5> rs2 [[in]] [[is_freg]];
+    }
+    encoding: 7'b0101000 :: rs2[4:0] :: rs1[4:0] :: 3'b011 :: rd[4:0] :: 7'b0101011;
+    assembly: "{name(rd)}, {name(rs1)}, {name(rs2)}";
+    behavior: {
+        F[rd] = llvm_fdiv_fp64(llvm_fadd_fp64(F[rs1], F[rs2]), llvm_uitofp_fp64(2));
+    }
+}
diff --git a/core_descs/ExampleFP64.ll b/core_descs/ExampleFP64.ll
@@ -0,0 +1,35 @@
+; ModuleID = 'mod'
+source_filename = "mod"
+
+define void @implFMAC(ptr %rs2, ptr %rs1, ptr noalias %rd) {
+  %rs1.v = load i64, ptr %rs1, align 8
+  %rs2.v = load i64, ptr %rs2, align 8
+  %rd.v = load i64, ptr %rd, align 8
+  %1 = bitcast i64 %rs1.v to double
+  %2 = bitcast i64 %rs2.v to double
+  %3 = bitcast i64 %rd.v to double
+  %4 = call double @llvm.fmuladd.f64(double %3, double %1, double %2)
+  %5 = bitcast double %4 to i64
+  store i64 %5, ptr %rd, align 8
+  ret void
+}
+
+; Function Attrs: nocallback nofree nosync nounwind speculatable willreturn memory(none)
+declare double @llvm.fmuladd.f64(double, double, double) #0
+
+define void @implFMEAN(ptr noalias %rd, ptr %rs1, ptr %rs2) {
+  %rs1.v = load i64, ptr %rs1, align 8
+  %rs2.v = load i64, ptr %rs2, align 8
+  %1 = bitcast i64 %rs1.v to double
+  %2 = bitcast i64 %rs2.v to double
+  %3 = fadd double %1, %2
+  %4 = bitcast double %3 to i64
+  %5 = bitcast i64 %4 to double
+  %6 = fdiv double %5, 2.000000e+00
+  %7 = bitcast double %6 to i64
+  store i64 %7, ptr %rd, align 8
+  ret void
+}
+
+attributes #0 = { nocallback nofree nosync nounwind speculatable willreturn memory(none) }
+
diff --git a/core_descs/ExampleFP64.td b/core_descs/ExampleFP64.td
@@ -0,0 +1,15 @@
+let Predicates = [HasVendorXCValu] in {
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1, Constraints = "$rd = $rd_wb" in def FMAC_ : RVInst_FMAC<(outs GPR:$rd_wb), (ins GPR:$rs2, GPR:$rs1, GPR:$rd)>;
+
+def : Pat<
+	(i64 (any_fma FPR64:$rd, FPR64:$rs1, FPR64:$rs2)),
+	(FMAC_ GPR:$rs2, GPR:$rs1, GPR:$rd)>;
+
+let hasSideEffects = 0, mayLoad = 0, mayStore = 0, isCodeGenOnly = 1, Constraints = "" in def FMEAN_ : RVInst_FMEAN<(outs GPR:$rd), (ins GPR:$rs1, GPR:$rs2)>;
+
+def : Pat<
+	(i64 (fmul (fadd FPR64:$rs1, FPR64:$rs2), (f64 0.500000))),
+	(FMEAN_ GPR:$rs1, GPR:$rs2)>;
+
+}
diff --git a/core_descs/ExampleFP64InstrFormat.td b/core_descs/ExampleFP64InstrFormat.td
@@ -0,0 +1,22 @@
+class RVInst_FMAC<dag outs, dag ins> : RVInst<outs, ins, "fmac", "$rd, $rs1, $rs2", [], InstFormatOther> {
+	bits<5> rs2;
+	bits<5> rs1;
+	bits<5> rd;
+	let Inst{31-25} = 0x0;
+	let Inst{24-20} = rs2{4-0};
+	let Inst{19-15} = rs1{4-0};
+	let Inst{14-12} = 0x0;
+	let Inst{11-7} = rd{4-0};
+	let Inst{6-0} = 0x0;
+}
+class RVInst_FMEAN<dag outs, dag ins> : RVInst<outs, ins, "fmean", "$rd, $rs1, $rs2", [], InstFormatOther> {
+	bits<5> rd;
+	bits<5> rs1;
+	bits<5> rs2;
+	let Inst{31-25} = 0x0;
+	let Inst{24-20} = rs2{4-0};
+	let Inst{19-15} = rs1{4-0};
+	let Inst{14-12} = 0x0;
+	let Inst{11-7} = rd{4-0};
+	let Inst{6-0} = 0x0;
+}