This repository contains the design and simulation of an educational 6-bit CPU implemented at the RTL level using VHDL. The project was developed as part of an undergraduate Hardware–Software Co-Design course and focuses on demonstrating core computer architecture concepts such as datapath design, control logic, instruction execution, and verification via simulation.
The CPU is multi‑cycle and FSM‑controlled, with a custom instruction set architecture (ISA) designed specifically for this project.
- Custom 6-bit Instruction Set Architecture (ISA)
- Multi-cycle CPU with explicit Fetch / Decode / Execute phases
- Modular RTL design (ALU, Register File, Control Unit, Program Counter)
- Extended arithmetic instructions beyond the base ISA
- Complete testbench with waveform-based verification
- Error handling (e.g., division by zero)
The CPU consists of the following main components:
- Program Counter (PC) – 6-bit instruction address register
- Instruction Register (IR) – Holds the current instruction
- Register File – 4 general-purpose 6-bit registers (R0–R3)
- ALU – Performs arithmetic and logical operations
- Control Unit (FSM) – Manages instruction sequencing and control signals
- Memory Interface – Instruction and data access
The control logic is implemented as a finite state machine (FSM) that orchestrates instruction execution over multiple cycles.
| Opcode | Instruction | Description |
|---|---|---|
| 000 | LOAD | Load immediate value into register |
| 001 | ADD | Register addition |
| 010 | SUB | Register subtraction |
| 011 | JNZ | Jump if not zero |
| 100 | MUL | Register multiplication |
| 101 | DIV | Register division (with zero check) |
| 110 | POW | Exponentiation |
Note: MUL, DIV, and POW were added as extended instructions beyond the base course requirements.
Instruction execution is divided into the following stages:
- Fetch – Instruction is loaded from memory
- Decode – Opcode and operands are extracted
- Execute – ALU operation, branching, or register update
Each stage may span one or more clock cycles depending on the instruction type.
- A dedicated testbench is provided
- Functional correctness verified using waveform analysis
- Edge cases such as invalid operations and divide‑by‑zero are handled explicitly
Simulation results demonstrate correct sequencing, data flow, and control behavior.
6-bit-CPU-VHDL/
├── assembler/ # Assembler source file (Python)
├── docs/ # Project report (Persian)
├── src/ # RTL source file (VHDL)
├── tb/ # Testbench file
└── README.md
This project was completed during the undergraduate program as part of a hardware–software co-design curriculum. A detailed academic report (written in Persian) is available in the docs/ directory.
- Pipeline implementation
- FPGA synthesis and timing analysis
- Expanded ISA and memory model
- Performance optimization
This project is provided for educational purposes. You may reuse or modify the code with proper attribution.