AIM:
To design and simulate the traffic light controller.
SOFTWATE USED:
Quartus II
THEORY:
Consider a controller for traffic at the intersection of three main roads.
The traffic signal for all the three main roads have equal priority and they remain red by default.
In state 00,the traffic signals remains red for first five counts and yellow of road1 turns on for the next four counts.
In state 01, the green of road1 turns on for first five counts and yellow of road1 and road2 turns on for next four4 counts of this state.
In state 10, the traffic signal of road1 comes back to the red and that of road2 goes to green for tee first five counts.For the next four counts the traffic signal of road2 and road3 remains yellow.
In state 11, the traffic signal of road2 comes back to the red and that of road3 goes to green for the first five counts.For the next four counts the traffic signal of road3 turns to yellow
At the end of four states,the traffic signal of all the three roads come back to red.
Task Assigned
From the HDL code given formulate the correct code to divert the traffic to path 1 direction and disable the control in other directions (Assume user is at MR3 spot)
Procedure
- Type the program in Quartus software.
- Compile and run the program.
- Generate the RTL schematic and save the logic diagram.
- Create nodes for inputs and outputs to generate the timing diagram.
- For different input combinations generate the timing diagram
Program:
/* Program to implement the given logic function and to verify its operations in quartus using Verilog programming.
Developed by: RegisterNumber:*/
RTL Schematic
Output Timing Waveform
Result: