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15 changes: 9 additions & 6 deletions ntc_templates/templates/alcatel_sros_show_lag.textfsm
Original file line number Diff line number Diff line change
Expand Up @@ -5,14 +5,17 @@ Value WEIGHTED (Yes|No)
Value THRESHOLD (\d+)
Value UP_COUNT (\d+)
Value MC_ACT_STDBY (N/A|active|standby)
Value LAG_NAME (lag-\S+)

Start
^----------- -> Lag

Lag
^${LAG_ID}\s+${ADM}\s+${OPR}\s+${WEIGHTED}\s+${THRESHOLD}\s+${UP_COUNT}\s+${MC_ACT_STDBY}(\s|$$) -> Record
^Lag\s+Data\s*$$
^Lag-id\s+Adm\s+Opr\s+Weighted\s+Threshold\s+Up-Count\s+MC\s+Act/Stdby\s*$$
^\s+name\s*$$
^\d+\s+((up|down)\s+){2} -> Continue.Record
^${LAG_ID}\s+${ADM}\s+${OPR}\s+${WEIGHTED}\s+${THRESHOLD}\s+${UP_COUNT}\s+${MC_ACT_STDBY}\s*$$
^\s+${LAG_NAME}\s*$$
^\s*$$
^-----------
^===========
^===+
^---+
^Total
^. -> Error
231 changes: 131 additions & 100 deletions tests/alcatel_sros/show_lag/show_lag.yml
Original file line number Diff line number Diff line change
@@ -1,219 +1,250 @@
---
parsed_sample:
- lag_id: "1"
adm: "up"
- adm: "up"
lag_id: "1"
lag_name: ""
mc_act_stdby: "N/A"
opr: "up"
weighted: "No"
threshold: "0"
up_count: "2"
weighted: "No"
- adm: "up"
lag_id: "2"
lag_name: ""
mc_act_stdby: "N/A"
- lag_id: "2"
adm: "up"
opr: "up"
weighted: "No"
threshold: "0"
up_count: "2"
weighted: "No"
- adm: "up"
lag_id: "3"
lag_name: ""
mc_act_stdby: "N/A"
- lag_id: "3"
adm: "up"
opr: "up"
weighted: "No"
threshold: "0"
up_count: "1"
mc_act_stdby: "N/A"
- lag_id: "4"
adm: "down"
opr: "down"
weighted: "No"
threshold: "0"
up_count: "0"
- adm: "down"
lag_id: "4"
lag_name: ""
mc_act_stdby: "N/A"
- lag_id: "5"
adm: "down"
opr: "down"
weighted: "No"
threshold: "0"
up_count: "0"
weighted: "No"
- adm: "down"
lag_id: "5"
lag_name: ""
mc_act_stdby: "N/A"
- lag_id: "10"
adm: "down"
opr: "down"
weighted: "No"
threshold: "0"
up_count: "0"
weighted: "No"
- adm: "down"
lag_id: "10"
lag_name: ""
mc_act_stdby: "N/A"
- lag_id: "20"
adm: "up"
opr: "down"
weighted: "No"
threshold: "0"
up_count: "0"
weighted: "No"
- adm: "up"
lag_id: "20"
lag_name: ""
mc_act_stdby: "standby"
- lag_id: "70"
adm: "down"
opr: "down"
weighted: "No"
threshold: "0"
up_count: "0"
weighted: "No"
- adm: "down"
lag_id: "70"
lag_name: ""
mc_act_stdby: "N/A"
- lag_id: "80"
adm: "up"
opr: "down"
weighted: "No"
threshold: "0"
up_count: "0"
weighted: "No"
- adm: "up"
lag_id: "80"
lag_name: ""
mc_act_stdby: "N/A"
- lag_id: "90"
adm: "down"
opr: "down"
weighted: "No"
threshold: "0"
up_count: "0"
mc_act_stdby: "N/A"
- lag_id: "100"
adm: "up"
opr: "up"
weighted: "No"
- adm: "down"
lag_id: "90"
lag_name: ""
mc_act_stdby: "N/A"
opr: "down"
threshold: "0"
up_count: "1"
up_count: "0"
weighted: "No"
- adm: "up"
lag_id: "100"
lag_name: ""
mc_act_stdby: "N/A"
- lag_id: "101"
adm: "up"
opr: "up"
weighted: "No"
threshold: "0"
up_count: "1"
weighted: "No"
- adm: "up"
lag_id: "101"
lag_name: ""
mc_act_stdby: "N/A"
- lag_id: "102"
adm: "up"
opr: "up"
weighted: "No"
threshold: "0"
up_count: "1"
weighted: "No"
- adm: "up"
lag_id: "102"
lag_name: ""
mc_act_stdby: "N/A"
- lag_id: "103"
adm: "up"
opr: "up"
weighted: "No"
threshold: "0"
up_count: "1"
weighted: "No"
- adm: "up"
lag_id: "103"
lag_name: ""
mc_act_stdby: "active"
- lag_id: "104"
adm: "up"
opr: "up"
weighted: "No"
threshold: "0"
up_count: "1"
weighted: "No"
- adm: "up"
lag_id: "104"
lag_name: ""
mc_act_stdby: "N/A"
- lag_id: "105"
adm: "up"
opr: "up"
weighted: "No"
threshold: "0"
up_count: "1"
weighted: "No"
- adm: "up"
lag_id: "105"
lag_name: ""
mc_act_stdby: "N/A"
- lag_id: "106"
adm: "up"
opr: "up"
weighted: "No"
threshold: "0"
up_count: "1"
weighted: "No"
- adm: "up"
lag_id: "106"
lag_name: ""
mc_act_stdby: "N/A"
- lag_id: "107"
adm: "up"
opr: "up"
weighted: "No"
threshold: "0"
up_count: "1"
weighted: "No"
- adm: "up"
lag_id: "107"
lag_name: ""
mc_act_stdby: "N/A"
- lag_id: "108"
adm: "up"
opr: "up"
weighted: "No"
threshold: "0"
up_count: "1"
weighted: "No"
- adm: "up"
lag_id: "108"
lag_name: ""
mc_act_stdby: "N/A"
- lag_id: "109"
adm: "up"
opr: "up"
weighted: "No"
threshold: "0"
up_count: "1"
weighted: "No"
- adm: "up"
lag_id: "109"
lag_name: ""
mc_act_stdby: "N/A"
- lag_id: "110"
adm: "up"
opr: "up"
weighted: "No"
threshold: "0"
up_count: "1"
weighted: "No"
- adm: "up"
lag_id: "110"
lag_name: ""
mc_act_stdby: "active"
- lag_id: "111"
adm: "up"
opr: "up"
weighted: "No"
threshold: "0"
up_count: "1"
weighted: "No"
- adm: "up"
lag_id: "111"
lag_name: ""
mc_act_stdby: "N/A"
- lag_id: "112"
adm: "up"
opr: "up"
weighted: "No"
threshold: "0"
up_count: "1"
weighted: "No"
- adm: "up"
lag_id: "112"
lag_name: ""
mc_act_stdby: "N/A"
- lag_id: "114"
adm: "up"
opr: "up"
weighted: "No"
threshold: "0"
up_count: "1"
weighted: "No"
- adm: "up"
lag_id: "114"
lag_name: ""
mc_act_stdby: "N/A"
- lag_id: "115"
adm: "up"
opr: "up"
weighted: "No"
threshold: "0"
up_count: "1"
weighted: "No"
- adm: "up"
lag_id: "115"
lag_name: ""
mc_act_stdby: "N/A"
- lag_id: "120"
adm: "up"
opr: "up"
threshold: "0"
up_count: "1"
weighted: "No"
- adm: "up"
lag_id: "120"
lag_name: ""
mc_act_stdby: "N/A"
opr: "up"
threshold: "0"
up_count: "1"
weighted: "No"
- adm: "down"
lag_id: "124"
lag_name: ""
mc_act_stdby: "N/A"
- lag_id: "124"
adm: "down"
opr: "down"
weighted: "No"
threshold: "0"
up_count: "0"
weighted: "No"
- adm: "up"
lag_id: "140"
lag_name: ""
mc_act_stdby: "N/A"
- lag_id: "140"
adm: "up"
opr: "up"
weighted: "No"
threshold: "0"
up_count: "1"
weighted: "No"
- adm: "down"
lag_id: "150"
lag_name: ""
mc_act_stdby: "N/A"
- lag_id: "150"
adm: "down"
opr: "down"
weighted: "No"
threshold: "0"
up_count: "0"
mc_act_stdby: "N/A"
- lag_id: "153"
adm: "up"
opr: "up"
weighted: "No"
- adm: "up"
lag_id: "153"
lag_name: ""
mc_act_stdby: "active"
opr: "up"
threshold: "0"
up_count: "1"
mc_act_stdby: "active"
- lag_id: "180"
adm: "down"
opr: "down"
weighted: "No"
- adm: "down"
lag_id: "180"
lag_name: ""
mc_act_stdby: "N/A"
opr: "down"
threshold: "0"
up_count: "0"
mc_act_stdby: "N/A"
weighted: "No"
22 changes: 22 additions & 0 deletions tests/alcatel_sros/show_lag/show_lag_name.raw
Original file line number Diff line number Diff line change
@@ -0,0 +1,22 @@

===============================================================================
Lag Data
===============================================================================
Lag-id Adm Opr Weighted Threshold Up-Count MC Act/Stdby
name
-------------------------------------------------------------------------------
1 up up No 0 1 N/A
lag-1
2 up up No 0 1 N/A
lag-2
19 up up No 0 2 N/A
lag-19
20 down down No 0 0 N/A
lag-20
50 down down No 0 0 N/A
lag-myname
101 up up No 0 1 N/A
lag-101
-------------------------------------------------------------------------------
Total Lag-ids: 6 Single Chassis: 6 MC Act: 0 MC Stdby: 0
===============================================================================
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