nRF Desktop: nRF54LM20: execute the app code from RAM

applications/nrf_desktop/CMakeLists.txt

@@ -47,6 +47,61 @@ if(CONFIG_IMG_MANAGER)
   zephyr_library_link_libraries(MCUBOOT_BOOTUTIL)
 endif()
 
+if(CONFIG_BOOTLOADER_MCUBOOT)
+  if(NOT (CONFIG_MCUBOOT_BOOTLOADER_MODE_SINGLE_APP OR
+          CONFIG_MCUBOOT_BOOTLOADER_MODE_DIRECT_XIP OR
+          CONFIG_MCUBOOT_BOOTLOADER_MODE_RAM_LOAD))
+    message(WARNING "
+            ------------------------------------------------------------------------------
+            --- WARNING: The currently selected mode of the MCUboot bootloader has not ---
+            --- been used or tested with any nRF Desktop configuration.                ---
+            ------------------------------------------------------------------------------
+            ")
+  endif()
+
+  if(CONFIG_MCUBOOT_BOOTLOADER_MODE_RAM_LOAD)
+    message(WARNING "
+            -----------------------------------------------------------------------------
+            --- WARNING: The RAM load mode of the MCUboot bootloader is experimental. ---
+            -----------------------------------------------------------------------------
+            ")
+
+    # The RAM load requires the code partition to be defined in DTS.
+    if(CONFIG_PARTITION_MANAGER_ENABLED)
+      message(FATAL_ERROR
+              "The RAM load mode of the MCUboot bootloader is not supported with the Partition "
+              "Manager (PM). Please disable PM and use DTS for defining the memory layout.")
+    endif()
+
+    # Enforce the specific RAM layout in DTS when MCUboot uses the RAM load mode.
+    dt_nodelabel(app_rxm_region_node NODELABEL cpuapp_sram_app_rxm_region)
+    if(NOT app_rxm_region_node)
+      message(FATAL_ERROR
+              "Missing RXM (ROM + RAM) region definition (cpuapp_sram_app_rxm_region) for the "
+              "application image in DTS.")
+    endif()
+
+    dt_nodelabel(mcuboot_ram_region_node NODELABEL cpuapp_sram_mcuboot_ram_region)
+    if(NOT mcuboot_ram_region_node)
+      message(FATAL_ERROR
+              "Missing RAM region definition (cpuapp_sram_mcuboot_ram_region) for the MCUboot "
+              "bootloader in DTS.")
+    endif()
+
+    dt_reg_addr(app_rxm_region_addr PATH ${app_rxm_region_node})
+    dt_reg_addr(mcuboot_ram_region_addr PATH ${mcuboot_ram_region_node})
+    if(mcuboot_ram_region_addr LESS_EQUAL app_rxm_region_addr)
+      message(FATAL_ERROR
+              "The start address of the RXM region (0x${app_rxm_region_addr}) must be located "
+              "before the start address of the MCUboot RAM region (0x${mcuboot_ram_region_addr})."
+              "The current order is wrong — modify your DTS RAM layout to fix this error.")
+    endif()
+
+    # Enforce additional constraints of the ROM section that is part of the RXM region.
+    zephyr_linker_sources(RODATA linker/mcuboot_ram_load.ld)
+  endif()
+endif()
+
 if(CONFIG_DESKTOP_CONFIG_CHANNEL_ENABLE)
   zephyr_linker_sources(SECTIONS nrf_desktop.ld)
   zephyr_linker_section(NAME config_channel_modules KVMA RAM_REGION GROUP RODATA_REGION NOINPUT)

applications/nrf_desktop/Kconfig.defaults

@@ -24,6 +24,18 @@ config DESKTOP_LTO_DEFAULTS
 	help
 	  nRF Desktop enables LTO to limit memory usage and improve performance.
 
+config DESKTOP_MCUBOOT_RAM_LOAD_MCUBOOT_RAM_START_ADDR
+	hex
+	depends on MCUBOOT_BOOTLOADER_MODE_RAM_LOAD
+	depends on $(dt_nodelabel_exists,cpuapp_sram_mcuboot_ram_region)
+	default $(dt_nodelabel_reg_addr_hex,cpuapp_sram_mcuboot_ram_region)
+	help
+	  The start address of the MCUboot RAM region. The Kconfig option is used to validate
+	  if the executable RAM region of the application image (also called the ROM section)
+	  does not overlap with the RAM region of the MCUboot image. The validation process
+	  assumes a specific RAM layout in DTS - you can refer to the following file as an example:
+	  ./configuration/nrf54lm20dk_nrf54lm20a_cpuapp/memory_map_ram_load.dtsi
+
 config APP_EVENT_MANAGER_MAX_EVENT_CNT
 	default 64
 	help

applications/nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/app.overlay

@@ -6,6 +6,11 @@
 
 #include "app_common.dtsi"
 
+/* Application does not use cpuflpr core. Assign whole RRAM to cpuapp. */
+&cpuapp_rram {
+	reg = < 0x0 DT_SIZE_K(2036) >;
+};
+
 / {
 	hid_dev_0: hid_dev_0 {
 		compatible = "zephyr,hid-device";

applications/nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/app_common.dtsi

@@ -4,11 +4,6 @@
  * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
  */
 
-/* Application does not use cpuflpr core. Assign whole RRAM to cpuapp. */
-&cpuapp_rram {
-	reg = < 0x0 DT_SIZE_K(2036) >;
-};
-
 / {
 	/* Disable pwmleds and redefine them to align configuration with CAF LEDs requirements. */
 	/delete-node/ pwmleds;

applications/nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/app_llvm.overlay

@@ -6,6 +6,11 @@
 
 #include "app_common.dtsi"
 
+/* Application does not use cpuflpr core. Assign whole RRAM to cpuapp. */
+&cpuapp_rram {
+	reg = < 0x0 DT_SIZE_K(2036) >;
+};
+
 / {
 	hid_dev_0: hid_dev_0 {
 		compatible = "zephyr,hid-device";

applications/nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/app_ram_load.overlay

@@ -0,0 +1,25 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+#include "app_common.dtsi"
+#include "memory_map_ram_load.dtsi"
+
+/ {
+	chosen {
+		/* We need to point where we want to place the retained memory region that
+		 * is shared with the MCUboot bootloader image and contains the image metadata.
+		 */
+		zephyr,bootloader-info = &boot_info0;
+	};
+
+	hid_dev_0: hid_dev_0 {
+		compatible = "zephyr,hid-device";
+		label = "HID0";
+		protocol-code = "mouse";
+		in-polling-period-us = <125>;
+		in-report-size = <64>;
+	};
+};

applications/nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/app_release.overlay

@@ -6,6 +6,11 @@
 
 #include "app_common.dtsi"
 
+/* Application does not use cpuflpr core. Assign whole RRAM to cpuapp. */
+&cpuapp_rram {
+	reg = < 0x0 DT_SIZE_K(2036) >;
+};
+
 / {
 	hid_dev_0: hid_dev_0 {
 		compatible = "zephyr,hid-device";

applications/nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/app_release_ram_load.overlay

@@ -0,0 +1,30 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+#include "app_common.dtsi"
+#include "memory_map_ram_load.dtsi"
+
+/ {
+	chosen {
+		/* We need to point where we want to place the retained memory region that
+		 * is shared with the MCUboot bootloader image and contains the image metadata.
+		 */
+		zephyr,bootloader-info = &boot_info0;
+	};
+
+	hid_dev_0: hid_dev_0 {
+		compatible = "zephyr,hid-device";
+		label = "HID0";
+		protocol-code = "mouse";
+		in-polling-period-us = <125>;
+		in-report-size = <64>;
+	};
+};
+
+/* For nRF54L, watchdog status is disabled by default. Needs to be enabled in DTS overlay. */
+&wdt31 {
+	status = "okay";
+};

applications/nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/images/mcuboot/app_llvm.overlay

@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+/* Application does not use cpuflpr core. Assign whole RRAM to cpuapp. */
+&cpuapp_rram {
+	reg = < 0x0 DT_SIZE_K(2036) >;
+};

applications/nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/images/mcuboot/app_ram_load.overlay

@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+#include "../../memory_map_ram_load.dtsi"
+
+/ {
+	chosen {
+		/* We need to point where we want to place MCUboot code. */
+		zephyr,code-partition = &boot_partition;
+		/* We need to point where we want to place MCUboot RAM region. */
+		zephyr,sram = &cpuapp_sram_mcuboot_ram_region;
+		/* We need to point where we want to place the retained memory region that
+		 * is shared with the application image and contains the image metadata.
+		 */
+		zephyr,bootloader-info = &boot_info0;
+	};
+};

applications/nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/images/mcuboot/app_release.overlay

@@ -0,0 +1,10 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+/* Application does not use cpuflpr core. Assign whole RRAM to cpuapp. */
+&cpuapp_rram {
+	reg = < 0x0 DT_SIZE_K(2036) >;
+};

applications/nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/images/mcuboot/app_release_ram_load.overlay

@@ -0,0 +1,20 @@
+/*
+ * Copyright (c) 2025 Nordic Semiconductor ASA
+ *
+ * SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+ */
+
+#include "../../memory_map_ram_load.dtsi"
+
+/ {
+	chosen {
+		/* We need to point where we want to place MCUboot code. */
+		zephyr,code-partition = &boot_partition;
+		/* We need to point where we want to place MCUboot RAM region. */
+		zephyr,sram = &cpuapp_sram_mcuboot_ram_region;
+		/* We need to point where we want to place the retained memory region that
+		 * is shared with the application image and contains the image metadata.
+		 */
+		zephyr,bootloader-info = &boot_info0;
+	};
+};

applications/nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/images/mcuboot/prj_ram_load.conf

@@ -0,0 +1,53 @@
+#
+# Copyright (c) 2025 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+#
+CONFIG_SIZE_OPTIMIZATIONS=y
+
+CONFIG_HW_STACK_PROTECTION=y
+
+CONFIG_MAIN_STACK_SIZE=10240
+
+CONFIG_BOOT_BOOTSTRAP=n
+
+CONFIG_BOOT_VERSION_CMP_USE_BUILD_NUMBER=y
+
+CONFIG_FLASH=y
+
+# Enable retained memory and retention to support the MCUboot RAM load mode.
+CONFIG_RETAINED_MEM=y
+CONFIG_RETENTION=y
+CONFIG_RETAINED_MEM_ZEPHYR_RAM=y
+CONFIG_BOOT_SHARE_DATA=y
+CONFIG_BOOT_SHARE_DATA_BOOTINFO=y
+CONFIG_BOOT_SHARE_BACKEND_RETENTION=y
+
+# Reduce memory consumption
+CONFIG_BOOT_BANNER=n
+CONFIG_NCS_BOOT_BANNER=n
+CONFIG_SYS_CLOCK_EXISTS=n
+CONFIG_CLOCK_CONTROL=n
+CONFIG_NRF_GRTC_TIMER=n
+CONFIG_NRF_GRTC_START_SYSCOUNTER=n
+CONFIG_SPI_NOR=n
+CONFIG_GPIO=n
+CONFIG_SERIAL=n
+CONFIG_CONSOLE=n
+CONFIG_UART_CONSOLE=n
+CONFIG_PRINTK=n
+CONFIG_USE_SEGGER_RTT=n
+CONFIG_COMMON_LIBC_MALLOC=n
+CONFIG_COMMON_LIBC_CALLOC=n
+CONFIG_COMMON_LIBC_REALLOCARRAY=n
+
+# Activate Link Time Optimization (LTO)
+CONFIG_LTO=y
+CONFIG_ISR_TABLES_LOCAL_DECLARATION=y
+
+# Improve debugging experience by disabling reset on fatal error
+CONFIG_RESET_ON_FATAL_ERROR=n
+
+# Set according to the configuration of the cpuapp_sram_app_rxm_region DTS node.
+CONFIG_BOOT_IMAGE_EXECUTABLE_RAM_START=0x20000800
+CONFIG_BOOT_IMAGE_EXECUTABLE_RAM_SIZE=500736

applications/nrf_desktop/configuration/nrf54lm20dk_nrf54lm20a_cpuapp/images/mcuboot/prj_release_ram_load.conf

@@ -0,0 +1,52 @@
+#
+# Copyright (c) 2025 Nordic Semiconductor ASA
+#
+# SPDX-License-Identifier: LicenseRef-Nordic-5-Clause
+#
+CONFIG_SIZE_OPTIMIZATIONS=y
+
+CONFIG_HW_STACK_PROTECTION=y
+
+CONFIG_MAIN_STACK_SIZE=10240
+
+CONFIG_BOOT_BOOTSTRAP=n
+
+CONFIG_BOOT_VERSION_CMP_USE_BUILD_NUMBER=y
+
+CONFIG_FLASH=y
+
+# Enable retained memory and retention to support the MCUboot RAM load mode.
+CONFIG_RETAINED_MEM=y
+CONFIG_RETENTION=y
+CONFIG_RETAINED_MEM_ZEPHYR_RAM=y
+CONFIG_BOOT_SHARE_DATA=y
+CONFIG_BOOT_SHARE_DATA_BOOTINFO=y
+CONFIG_BOOT_SHARE_BACKEND_RETENTION=y
+
+CONFIG_RESET_ON_FATAL_ERROR=y
+
+# Reduce memory consumption
+CONFIG_BOOT_BANNER=n
+CONFIG_NCS_BOOT_BANNER=n
+CONFIG_SYS_CLOCK_EXISTS=n
+CONFIG_CLOCK_CONTROL=n
+CONFIG_NRF_GRTC_TIMER=n
+CONFIG_NRF_GRTC_START_SYSCOUNTER=n
+CONFIG_SPI_NOR=n
+CONFIG_GPIO=n
+CONFIG_SERIAL=n
+CONFIG_CONSOLE=n
+CONFIG_UART_CONSOLE=n
+CONFIG_PRINTK=n
+CONFIG_USE_SEGGER_RTT=n
+CONFIG_COMMON_LIBC_MALLOC=n
+CONFIG_COMMON_LIBC_CALLOC=n
+CONFIG_COMMON_LIBC_REALLOCARRAY=n
+
+# Activate Link Time Optimization (LTO)
+CONFIG_LTO=y
+CONFIG_ISR_TABLES_LOCAL_DECLARATION=y
+
+# Set according to the configuration of the cpuapp_sram_app_rxm_region DTS node.
+CONFIG_BOOT_IMAGE_EXECUTABLE_RAM_START=0x20000800
+CONFIG_BOOT_IMAGE_EXECUTABLE_RAM_SIZE=500736