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Mimas_A7_V3 BSP #3

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275 changes: 275 additions & 0 deletions Mimasa7_V3/3.0/board.xml
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<?xml version="1.0" encoding="UTF-8" standalone="no"?>
<board schema_version="2.0" vendor="numato.com" name="Mimasa7_V3" display_name="Mimasa7_V3" url="www.numato.com/" preset_file="preset.xml" >
<images>
<image name="" display_name="Mimas A7 Artix7 BOARD" sub_type="board">
<description>Mimas a7 Artix7 Board File Image</description>
</image>
</images>
<compatible_board_revisions>
<revision id="0">1.0</revision>
</compatible_board_revisions>
<file_version>3.0</file_version>
<description>Mimasa7_V3</description>
<components>
<component name="part0" display_name="Mimasa7_V3" type="fpga" part_name="xc7a50tfgg484-1" pin_map_file="part0_pins.xml" vendor="xilinx" spec_url="www.numato.com/">
<interfaces>
<interface mode="master" name="ddr3_sdram" type="xilinx.com:interface:ddrx_rtl:1.0" of_component="ddr3_sdram" preset_proc="ddr3_sdram_preset">
<description>DDR3 board interface.</description>
<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="mig_7series" order="0"/>
</preferred_ips>
</interface>
<interface mode="slave" name="reset" type="xilinx.com:signal:reset_rtl:1.0" of_component="reset">
<description>Reset Button</description>
<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="proc_sys_reset" order="0"/>
</preferred_ips>
<port_maps>
<port_map logical_port="RESET" physical_port="reset" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="reset"/>
</pin_maps>
</port_map>
</port_maps>
<parameters>
<parameter name="rst_polarity" value="1" />
</parameters>
</interface>

<interface mode="slave" name="sys_clock" type="xilinx.com:signal:clock_rtl:1.0" of_component="sys_clock" preset_proc="sys_clock_preset">
<parameters>
<parameter name="frequency" value="100000000"/>
</parameters>
<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="clk_wiz" order="0"/>
</preferred_ips>
<port_maps>
<port_map logical_port="clk" physical_port="clk" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="clk"/>
</pin_maps>
</port_map>
</port_maps>
<parameters>
<parameter name="frequency" value="100000000" />
</parameters>
</interface>
<interface mode="master" name="usb_uart" type="xilinx.com:interface:uart_rtl:1.0" of_component="usb_uart" preset_proc="uart_preset">
<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="axi_uartlite" order="0"/>
</preferred_ips>
<port_maps>
<port_map logical_port="TxD" physical_port="usb_uart_txd" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="usb_uart_txd"/>
</pin_maps>
</port_map>
<port_map logical_port="RxD" physical_port="usb_uart_rxd" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="usb_uart_rxd"/>
</pin_maps>
</port_map>
</port_maps>
</interface>




<interface mode="master" name="qspi_flash" type="xilinx.com:interface:spi_rtl:1.0" of_component="qspi_flash" preset_proc="qspi_flash_preset">
<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="axi_quad_spi" order="0"/>
</preferred_ips>
<port_maps>

<port_map logical_port="IO0_I" physical_port="qspi_flash_io0_i" dir="inout">
<pin_maps>
<pin_map port_index="0" component_pin="flash_d0"/>
</pin_maps>
</port_map>
<port_map logical_port="IO0_O" physical_port="qspi_flash_io0_o" dir="inout">
<pin_maps>
<pin_map port_index="0" component_pin="flash_d0"/>
</pin_maps>
</port_map>

<port_map logical_port="IO1_I" physical_port="qspi_flash_io1_i" dir="inout">
<pin_maps>
<pin_map port_index="0" component_pin="flash_d1"/>
</pin_maps>
</port_map>
<port_map logical_port="IO1_O" physical_port="qspi_flash_io1_o" dir="inout">
<pin_maps>
<pin_map port_index="0" component_pin="flash_d1"/>
</pin_maps>
</port_map>


<port_map logical_port="SS_I" physical_port="qspi_flash_ss_i" dir="inout">
<pin_maps>
<pin_map port_index="0" component_pin="qspi_flash_ss_io"/>
</pin_maps>
</port_map>
<port_map logical_port="SS_O" physical_port="qspi_flash_ss_o" dir="inout">
<pin_maps>
<pin_map port_index="0" component_pin="qspi_flash_ss_io"/>
</pin_maps>
</port_map>

</port_maps>
</interface>





<interface mode="master" name="eth_mdio_mdc" type="xilinx.com:interface:mdio_rtl:1.0" of_component="phy_onboard">
<description>Secondary interface to communicate with ethernet phy. </description>
<port_maps>
<port_map logical_port="MDIO_I" physical_port="eth_mdio_i" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="eth_mdio_i"/>
</pin_maps>
</port_map>
<port_map logical_port="MDIO_O" physical_port="eth_mdio_o" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="eth_mdio_i"/>
</pin_maps>
</port_map>
<port_map logical_port="MDIO_T" physical_port="eth_mdio_t" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="eth_mdio_i"/>
</pin_maps>
</port_map>
<port_map logical_port="MDC" physical_port="eth_mdc" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="eth_mdc"/>
</pin_maps>
</port_map>
</port_maps>
</interface>



<interface mode="master" name="eth_rgmii" type="xilinx.com:interface:rgmii_rtl:1.0" of_component="phy_onboard">
<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="eth_rgmii" order="0"/>
</preferred_ips>
<description>Primary interface to communicate with ethernet phy in RGMII mode. </description>
<port_maps>
<port_map logical_port="TD" physical_port="eth_txd" dir="out" left="3" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="eth_txd_0"/>
<pin_map port_index="1" component_pin="eth_txd_1"/>
<pin_map port_index="2" component_pin="eth_txd_2"/>
<pin_map port_index="3" component_pin="eth_txd_3"/>
</pin_maps>
</port_map>
<port_map logical_port="TX_CTL" physical_port="eth_tx_ctl" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="eth_tx_ctl"/>
</pin_maps>
</port_map>
<port_map logical_port="TXC" physical_port="eth_tx_clk" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="eth_tx_clk"/>
</pin_maps>
</port_map>
<port_map logical_port="RD" physical_port="eth_rxd" dir="in" left="3" right="0">
<pin_maps>
<pin_map port_index="0" component_pin="eth_rxd_0"/>
<pin_map port_index="1" component_pin="eth_rxd_1"/>
<pin_map port_index="2" component_pin="eth_rxd_2"/>
<pin_map port_index="3" component_pin="eth_rxd_3"/>
</pin_maps>
</port_map>
<port_map logical_port="RX_CTL" physical_port="eth_rx_ctl" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="eth_rx_ctl"/>
</pin_maps>
</port_map>
<port_map logical_port="RXC" physical_port="eth_rx_clk" dir="in">
<pin_maps>
<pin_map port_index="0" component_pin="eth_rx_clk"/>
</pin_maps>
</port_map>
</port_maps>
</interface>


<interface mode="master" name="phy_reset_out" type="xilinx.com:signal:reset_rtl:1.0" of_component="phy_onboard">
<description>Onboard Reset Button</description>
<preferred_ips>
<preferred_ip vendor="xilinx.com" library="ip" name="axi_ethernet" order="0"/>
</preferred_ips>
<port_maps>
<port_map logical_port="RESET" physical_port="phy_reset_n" dir="out">
<pin_maps>
<pin_map port_index="0" component_pin="phy_reset_n"/>
</pin_maps>
</port_map>
</port_maps>
</interface>

</interfaces>
</component>

<component name="ddr3_sdram" display_name="DDR3 SDRAM" type="chip" sub_type="ddr" major_group="External Memory">
<description>DDR3 memory</description>
<parameters>
<parameter name="ddr_type" value="ddr3"/>
<parameter name="size" value="256MB"/>
</parameters>
</component>
<component name="sys_clock" display_name="System Clock" type="chip" sub_type="system_clock" major_group="Clocks">
<description>3.3V Single-Ended 100MHz oscillator used as system clock on the board</description>
</component>
<component name="reset" display_name="FPGA Reset" type="chip" sub_type="system_reset" major_group="Reset">
<description>CPU Reset, Active High</description>
</component>
<component name="qspi_flash" display_name="QSPI flash" type="chip" sub_type="memory_flash_qspi" major_group="External Memory" part_name="N25Q128A13ESE40E" vendor="Micron">
<description>128Mb flash provides non-volatile storage for use by the FPGA.</description>
</component>
<component name="usb_uart" display_name="USB UART" type="chip" sub_type="uart" major_group="UART">
<description>USB-to-UART Bridge, which allows a connection to a host computer with a USB port</description>
</component>
<component name="phy_onboard" display_name="Gigabit Ethernet PHY" type="chip" sub_type="ethernet" major_group="Ethernet">
<description>PHY Ethernet on the board</description>
<component_modes>
<component_mode name="rgmii" display_name="RGMII mode">
<interfaces>
<interface name="eth_rgmii" order="0"/>
<interface name="eth_mdio_mdc" order="1"/>
<interface name="phy_reset_out" order="2" optional="true"/>
</interfaces>
</component_mode>
</component_modes>
</component>
</components>

<jtag_chains>
<jtag_chain name="chain1">
<position name="0" component="part0"/>
</jtag_chain>
</jtag_chains>
<connections>
<connection name="part0_sys_clock" component1="part0" component2="sys_clock">
<connection_map name="part0_sys_clock_1" c1_st_index="0" c1_end_index="0" c2_st_index="0" c2_end_index="0"/>
</connection>
<connection name="part0_reset" component1="part0" component2="reset">
<connection_map name="part0_reset_1" c1_st_index="1" c1_end_index="1" c2_st_index="0" c2_end_index="0"/>
</connection>
<connection name="part0_qspi_flash" component1="part0" component2="qspi_flash">
<connection_map name="part0_qspi_flash_map" c1_st_index="8" c1_end_index="10" c2_st_index="0" c2_end_index="2" />
</connection>
<connection name="part0_usb_uart" component1="part0" component2="usb_uart">
<connection_map name="part0_usb_uart_1" c1_st_index="2" c1_end_index="3" c2_st_index="0" c2_end_index="1"/>
</connection>
<connection name="part0_eth_mdio_mdc" component1="part0" component2="phy_onboard">
<connection_map name="part0_eth_rgmii_1" c1_st_index="7" c1_end_index="18" c2_st_index="0" c2_end_index="11"/>
<connection_map name="part0_eth_mdio_mdc_1" c1_st_index="4" c1_end_index="5" c2_st_index="0" c2_end_index="1"/>
<connection_map name="part0_eth_phy_reset_n" c1_st_index="19" c1_end_index="19" c2_st_index="0" c2_end_index="0"/>
</connection>
</connections>
</board>

<!DOCTYPE board SYSTEM "board.dtd"> <!-- for board.xml -->
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